LG Display LC320DUE-SDF1 Specification

( ) Preliminary Specification
(● ) Final Specification

LC320EUN

Product Specification

SPECIFICATION

FOR

APPROVAL

Title

BUYER General

MODEL

APPROVED BY

/

/

SIGNATURE

DATE

32.0” WUXGA TFT LCD

SUPPLIER LG Display Co., Ltd.

*MODEL LC320EUN

SUFFIX SDF1 (RoHS Verified)

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY

J.T. Eu / Team Leader

REVIEWED BY

S.B. Lee / Project Leader

SIGNATURE

DATE

/

Please return 1 copy for your confirmation with

your signature and comments.

Ver. 1.0

PREPARED BY

J.T. Jung / Engineer

TV Product Development Dept.

LG Display Co., Ltd.

1 /40

Product Specification

CONTENTS

LC320EUN

Number ITEM

COVER 1
CONTENTS
RECORD OF REVISIONS

1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS

3-1 ELECTRICAL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATIONS

3-4 LVDS SIGNAL SPECIFICATIONS
3-5 COLOR DATA REFERENCE

3-6 POWER SEQUENCE
4 OPTICAL SPECIFICATIONS
5 MECHANICAL CHARACTERISTICS

Page

2
3

4
5
6
6
8

10
11

14
15
17
23

6 RELIABILITY
7 INTERNATIONAL STANDARDS

7-1 SAFETY

7-2 EMC

7-3 ENVIRONMENT
8 PACKING

8-1 INFORMATION OF LCM LABEL

8-2 PACKING FORM

9 PRECAUTIONS

9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

Ver. 1.0

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2 /40

Product Specification

RECORD OF REVISIONS

Revision No. Revision Date Page Description

0.0 DEC, 01, 2010 - Preliminary Specification (First Draft)

1.0 FEB, 24, 2011 - Final Specification
17 Optical spec update

LC320EUN

Ver. 1.0

3 /40

LC320EUN

Product Specification

1. General Description

The LC320EUN is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 31.55 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7Million colors.
Ithas been designed to apply the 8-bit 2-port LVDS interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.

Mini-LVDS(RGB)

Control
Signals

Power Signals

Source Driver Circuit

S1 S1920

G1

TFT -LCD Panel

(1920 × RGB × 1080 pixels)

[Gate In Panel]

G1080

LVDS

2Port

LVDS
Select

OPC
Enable

ExtVBR-B

+12.0V

CN1

(51pin)

LVDS 1,2

Option
signal

I2C

EEPROM

SCL

SDA

Timing Controller

LVDS Rx + OPC + DGA

Integrated

Power Circuit

Block

PWM_OUT

CN2

1~3

(8 pin)

PWM_OUT

1~3

+24.0V, GND, On/Off

LED Driver

Scanning Block 1
Scanning Block 2
Scanning Block 3

General Features

Active Screen Size 31.55 inches(801.31mm) diagonal
Outline Dimension 735.4(H) × 433.0 (V) X 10.8(B)/23.6(D) mm (Typ.)
Pixel Pitch 0.36375 mm x 0.36375 mm
Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Color Depth 8bit, 16.7Million colors
Luminance, White 350 cd/m2 (Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Power Consumption Total 48.2W [Logic= 5.5W, LED Driver=42.7W (ExtVbr_B=100% )]
Weight 6.0 Kg (Typ.)
Display Mode Transmissive mode, Normally black
Surface Treatment Hard coating(2H), Anti-glare treatment of the front polarizer (Haze 10%)

Ver. 1.0

4 /40

LC320EUN

Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Unit Note

Min Max

LCD Circuit VLCD -0.3 +14.0 VDC

Power Input Voltage

Driver VBL -0.3 + 27.0 VDC
ON/OFF VOFF / VON -0.3 +5.5 VDC

Driver Control Voltage

Brightness EXTVBR-B 0.0 +3.6 VDC
T-Con Option Selection Voltage VLOGIC -0.3 +4.0 VDC
Operating Temperature TOP 0 +50 °C
Storage Temperature TST -20 +60 °C
Panel Front Temperature TSUR - +68 °C 4
Operating Ambient Humidity HOP 10 90 %RH
Storage Humidity HST 10 90 %RH

Value

Note

1. Ambient temperature condition (Ta = 25 ± 2 °C )

2. Temperature and relative humidity range are shown inthe figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.

3. Gravity mura can be guaranteed below 40°C condition.

4. The maximum operating temperatures is based on the test condition that the surface temperature

of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may be degraded in case of
improper thermal management in final product design.

90%

1

2,3

2,3

Ver. 1.0

Wet Bulb
Temperature [°C]

20

10

0

10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [°C]

30

40

50

60

60%

40%

10%

Storage

Operation

Humidity [(%)RH]

5 /40

LC320EUN

Product Specification

3. Electrical Specifications
3-1. Electrical Characteristics

It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight and LED Driver circuit.

Table 2. ELECTRICAL CHARACTERISTICS

Value

Parameter Symbol

Min Typ Max

Circuit :

Power Input Voltage VLCD 10.8 12.0 13.2 VDC

Unit Note

Power Input Current ILCD

Power Consumption PLCD
Rush current IRUSH -

ExtV

BR-B

Brightness Adjust for Back Light

ExtV

BR-B

Frequency

Note

1. The specified current and power consumption are under the V

-

-

5 - 100 %
1 - 100 %

40 50 Hz

460 575
680 850

5.5 6.9

- 5.0

60 80 Hz

=12.0V, Ta=25 ± 2°C, fV=60Hz

LCD

condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.

2. The current is specified at the maximum current pattern.

3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).

4. ExtV
After Driver ON signal is applied, ExtV
After that, ExtV

signal have to input available duty range and sequence.

BR-B

1% and 100% is possible

BR-B

should be sustained from 5% to 100% more than 500ms.

BR-B

For more information, please see 3-6-2. Sequence for LED Driver.

mA 1
mA 2

Watt 1

A 3

On Duty

4

Ver. 1.0

White : 255 Gray
Black : 0 Gray

Mosaic Pattern(8 x 6)

6 /40

Product Specification

Table 3. ELECTRICAL CHARACTERISTICS (Continue)

LC320EUN

Parameter Symbol

LED Driver :

Power Supply Input Voltage VBL 22.8 24.0 25.2 Vdc 1

Power Supply Input Current IBL

Power Supply Input Current (In-Rush) In-rush - - 3 A

Power Consumption PBL -

Input Voltage for

Control System

Signals

LED :

Life Time 30,000 50,000 Hrs 2

On/Off

On V on 2.5 - 5.0 Vdc
Off V off -0.3 0.0 0.7 Vdc

Min Typ Max

Values

-

1.78

42.7 46.8

1.95

Unit Notes

A 1

VBL = 22.8V
ExtV

W 1

BR-B

= 100%

4

Notes :

1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (ExtVBR-B: 100%), it is total power consumption.

2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at
25±2°C.

3. The duration of rush current is about 200ms. This duration is applied to LED on time.

4. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.

Ver. 1.0

7 /40

LC320EUN

Product Specification

3-2. Interface Connections

This LCD module employs two kinds of interface connection, 51-pin connector is used for the module
electronics and 14-pin connector is used for the integral backlight system.

3-2-1. LCD Module

-LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or compatible
Refer to below and next Page table

-Mating Connector : FI-R51HL(JAE) or compatible

Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION

No Symbol Description No Symbol Description

1
2
3
4
5

6
7

8
9

10
11

12
13
14
15
16
17
18
19
20
21
22
23
24

25
26

NC
NC
NC
NC

NC
NC

LVDS Select

ExtVBR-B

NC

OPC Enable

GND
R1AN
R1AP
R1BN
R1BP
R1CN
R1CP

GND

R1CLKN
R1CLKP

GND
R1DN
R1DP

NC
NC
NC

No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)

No Connection (Note 4)
No Connection (Note 4)

‘H’ =JEIDA , ‘L’ or NC= VESA

External PWM (from System)
No Connection (Note 4)

‘H’ = Enable , ‘L’ or NC = Disable

Ground
FIRST LVDS Receiver Signal (A-)

FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)

Ground
FIRST LVDS Receiver Clock Signal(-)

FIRST LVDS Receiver Clock Signal(+)
Ground

FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)

No Connection
No Connection
No Connection

27
28

29
30
31
32
33
34
35
36
37
38
39

40
41
42
43
44
45
46

47
48
49
50
51

- - -

NC

R2AN
R2AP
R2BN

R2BP
R2CN
R2CP

GND
R2CLKN
R2CLKP

GND

R2DN
R2DP

NC
NC
NC
NC

GND Ground

GND Ground

GND Ground

NC No connection
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V

No Connection
SECOND LVDS Receiver Signal (A-)

SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)

SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)

SECOND LVDS Receiver Signal (C+)
Ground

SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)

Ground
SECOND LVDS Receiver Signal (D-)

SECOND LVDS Receiver Signal (D+)
No Connection

No Connection
No Connection
No Connection

Note

Ver. 1.0

1. All GND(ground) pins should be connected together to the LCD module’s metal frame.

2. All VLCD (power input) pins should be connected together.

3. All Input levels of LVDS signals are based on the EIA 644 Standard.

4. #1~#6 & #9 NC (No Connection): These pins are used only for LGD (Do not connect)

5. Specific pins(pin No. #10) are used for Scanning function of the LCD module.
If not used, these pins are no connection. (Please see the Appendix VI for more information.)

6. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).

8 /40

Product Specification

3-2-2. Backlight Module

Master

-LED Driver Connector
: 20022WR -H14B1(Yeonho) or Equivalent

-Mating Connector
: 20022HS -14B2or Equivalent

Table 5. LED DRIVER CONNECTOR PIN CONFIGURATION

Pin No Symbol Description Note

LC320EUN

1
2
3
4
5
6
7
8

9
10
11
12

13
14

VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V

VBL Power Supply +24.0V
GND Backlight Ground
GND Backlight Ground
GND Backlight Ground
GND Backlight Ground
GND Backlight Ground

Status

ON/OFF

V

NC
NC

Back Light Status
Backlight ON/OFF control
Don’t care
Don’t care

Notes : 1. GND should be connected to the LCD module’s metal frame.

2. Normal : Low (under 0.7V) / Abnormal : High (upper 3.0V)

3. The impedance of pin #12 is over 50 [KΩ] .

1

2

◆ Rear view of LCM

1

Ver. 1.0

…

14

<Master>

PCB

1

14

…

9 /40

LC320EUN

Product Specification

3-3. Signal Timing Specifications

Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification fornormal operation.

Table 6. TIMING TABLE (DE Only Mode)

ITEM Symbol Min Typ Max Unit Note

Horizontal

Vertical

Frequency

Display

Period

Blank tHB 100 140 240 tCLK 1

Total tHP 1060 1100 1200 tCLK

Display

Period

Blank tVB

Total tVP

ITEM Symbol Min Typ Max Unit Note

DCLK fCLK 63.00 74.25 78.00 MHz

Horizontal fH 57.3 67.5 70 KHz 2

Vertical fV

tHV 960 960 960 tCLK 1920 / 2

tVV 1080 1080 1080 Lines

20

(228)

1100

(1308)

57

(47)

45

(270)

1125

(1350)

60

(50)

69

(300)

1149

(1380)

63

(53)

Lines 1

Lines

Hz

NTSC : 57~63Hz
(PAL : 47~53Hz)

2

Note:1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).

If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.

2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency

※ Timing should be set based on clock frequency.

Ver. 1.0

10 /40

3-4. LVDS Signal Specification

3-4-1. LVDS Input Signal Timing Diagram

LC320EUN

Product Specification

DE, Data

DCLK

First data

Second data

0.7VDD

0.3VDD

tCLK

DE(Data Enable)

0.5 VDD

Invalid data

Invalid data

Valid data

Pixel 0,0 Pixel 2,0

Valid data

Pixel 1,0 Pixel 3,0

tHP

Invalid data

Invalid data

tHV

DE(Data Enable)

Ver. 1.0

1 1080

tVV

tVP

11 /40

3-4-2. LVDS Input Signal Characteristics

1) DC Specification

LVDS -

LVDS +

LC320EUN

Product Specification

# VCM= {(LVDS+) + (LVDS-)}/2

0V

V

CM

V

IN_MAXVIN_MIN

Description Symbol Min Max Unit Note

LVDS Common mode Voltage V
LVDS Input Voltage Range V

CM

IN

1.0 1.5 V -

0.7 1.8 V -

Change in common mode Voltage ΔVCM 250 mV -

2) AC Specification

T

clk

LVDS Clock

A

LVDS Data

(Fclk = 1/Tclk )

T

clk

A

LVDS 1’st Clock

LVDS 2nd/ 3rd/ 4thClock

tSKEW

tSKEW

t

SKEW_mintSKEW_max

80%

20%

t

RF

Description Symbol Min Max Unit Note

LVDS Differential Voltage

High Threshold

Low Threshold
LVDS Clock to Data Skew t
LVDS Clock/DATA Rising/Falling time t
Effective time of LVDS t
LVDS Clock to Clock Skew (Even to Odd) t

Note

1. All Input levels of LVDS signals are based on theEIA 644 Standard.

2. If tRFisn’t enough, t

should be meet the range.

eff

3. LVDS Differential Voltage is defined within t

Ver. 1.0

V

TH

V

TL

SKEW

RF

eff

SKEW_EO

100 300 mV

-300 -100 mV

- |(0.25*T

260 |(0.3*T

)/7| ps -

clk

)/7| ps 2

clk

|±360| - ps -

- |1/7* T

eff

| ps -

clk

3

12 /40