LG XNOTE E510 Schematics

1

2

3

4

5

6

7

8

PCB STACK UP

LAYER 1 : TOP

01

LAYER 2 : SGND1
LAYER 3 : IN1
LAYER 4 : IN2

A A

LAYER 5 : VCC
LAYER 6 : BOT

VCC_CORE

MAX8736

VCC1.5

G966

VCC1.05

MAX1933

B B

VCC1.25

CRT

Page 14

LCD(WXGA 15.4)

Page 14

1.8VSUS

TPS51116

3VPCU
RVCC3
3VSUS
VCC3
5VPCU
RVCC5
5VSUS
VCC5

MAXIM
MAX8744ETJ+

C C

Page:26

SATA - HDD

Page 25

IDE - ODD

Page 25

USB PORT 0

Page 29

USB PORT 2

Page 29

USB PORT 6

Page 29

USB PORT 5

Page 29 4 IN 1 CARD

SATA

PATA

USB 2.0

PL3 Block Diagram

Intel

Merom

(35W)

Page 4,5

FSB(667/800MHZ)

R.G.B

LVDS X1

Crestline GM

Page 6,7,8,9,10,11,12,13

DMI(x2/x4)

ICH8M

Page 17,18,19,20

LPC

PC8769

32.768KHz

533/ 667 MHZ DDR II

PCI-E, 1X

PCI-E, 1X

USB4

Page 23

LAN(10/100M)
M88E8039

Page 24 Page 24

Azalia

MDC
CX20548-S
(Optional)

Page 28

CLOCK GENERATOR

ICS9LPR363

Page 3

DDRII-SODIMM1

Page 15,16

DDRII-SODIMM2

Page 15,16

PCIEMINI

AUDIO CODEC

CX20549-12Z

Page 26

RJ45

MAX 9789A

Page 27

Ext MIC

Page 26

INT SPK

Page 27

HP

Page 27

Page 31,32

D D

FAN Touch

PAD Board

Key FLASH

ROM

PCB P/N:DA0PL3MB6A7

1

2

3

4

RJ11

Page 28

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Block Diagram

Block Diagram

Block Diagram

Date: Sheet

Date: Sheet

5

6

Date: Sheet

7

PROJECT : PL3

8

A

A

138Thursday, January 11, 2007

138Thursday, January 11, 2007

138Thursday, January 11, 2007

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Page 01:
Page 02:
Page 03:
Page 04:
Page 05:
Page 06:

A A

Page 07:
Page 08:
Page 09:
Page 10:
Page 11:
Page 12:
Page 13:
Page 14:
Page 15:
Page 16:
Page 17:
Page 18:
Page 19:
Page 20:

B B

Page 21:
Page 22:
Page 23:
Page 24:
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Page 28:
Page 29:
Page 30:
Page 31:
Page 32:
Page 33:
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C C

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Page 36:
Page 37:
Page 38:
Page 39:

Block diagram
Table of contents
Clock generator ICS9PR363
Merom(Host Bus)
Merom(Power)
CPU Thermal/Fan Control
Crestline A(Host)
Crestline B(VGA,DMI)
Crestline C(DDR2)
Crestline D(VCC)
Crestline E(Power)
Crestline F(VSS)
Crestline (Straps)
Panel LCD/CRT
DDR2 SODIMM
DDR2 Termination
ICH8M (Host)
ICH8M (PCIE)
ICH8M (GPIO)
ICH8M (Power)
R5C832 (PCI)
R5C832 (4in1)
SD/MS/xD Connector
PCIE LAN 88E8039
Mini PCIE/EMI
SATA/ODD Connector
CODEC(CX20549)
Audio Amplifier MAX9789A
CONEXTANT MDC
Kerboard/USB
TP/LED/SW
KBC uR PC8769
KBC PC87541
CPU CORE MAX8736
VCC1.05

1.8VSUS/VCC1.5/VCC1.25
3VPCU/5VPCU
Battery Charger
Battery Connector

Voltage Rails

Power ON S0~S2 Ctl SignalON S3 ON S4 ON S5

9VPCU
5VPCU
3VPCU

RVCC3

5VSUS
3VSUS

1.8VSUS
VCC5

VCC3

VCC1.5 1.5V
VCC1.25 1.25V
VCC1.05
SMDDR_VTERM

VCC_CORE

Power On Sequence

ACIN
5VPCU/3VPCU
NBSWON#

PWRBTN#

RVCC_ON

RSMRST#

SUSB#,SUSC#

SUSON

MAINON

VSUS,VCC

VR_ON

VCORE_CPU

Voltage

9V
5V
3V

3V

5V
3V

1.8V
5V

3V

1.05V

0.9V

By CPU

V VVV
V VVV
V

VVV

V
V

V
V
V
V

V

VVV

VV
VV
VV

From 87541

From 87541

From 87541

From 87541

From 87541

RVCC_ON

SUSON
SUSON
SUSON

MAINON
MAINON

MAINON
MAINON
MAINON
MAINON

VR_ON

PCB STACK UP

LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 8 : BOT

PCI DEVICES IRQ ROUTING

PCI ROUTING
TABLE

REQ0# / GNT0# RICOH832

IDSEL

AD17

INTERUPT

INTA#,INTB#

DEVICE

2

PWROK

D D

1

2

PCIRST#

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

System Information

System Information

System Information

Date: Sheet

Date: Sheet

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

238Wednesday, January 10, 2007

238Wednesday, January 10, 2007

238Wednesday, January 10, 2007

8

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8

Clock Generator

A A

U5

U5
ICS9LPRS365AGLFT/ SLG8SP512T

L10 BKP1608HS181-T

L10 BKP1608HS181-T

VCC3

EMI FILTER BKP1608HS181-T(180,1.5A)

EMI FILTER BKP1608HS181-T(180,1.5A)

L12 BKP1608HS181-T

L12 BKP1608HS181-T

VCC1.05

EMI FILTER BKP1608HS181-T(180,1.5A)

EMI FILTER BKP1608HS181-T(180,1.5A)

0.1U close to each VDD_IO Power pin

B B

C241

C241

10U_8

10U_8

C234

C234

.1U_4

.1U_4

SATACLKREQ#19

PCLK_DEBUG23,31

PCLK_59131

C222 33P_4C222 33P_4

<check list>
XTAL length < 500mils

C217 33P_4C217 33P_4

CLKUSB_4819

14M_ICH19

C188

C188

10U_8

10U_8

C190

C190

.1U_4

.1U_4

CPU_BSEL0
CPU_BSEL2

C236

C236
.1U_4

.1U_4

C233

C233

.1U_4

.1U_4

C232

C232

C384

C384

.1U_4

.1U_4

.1U_4

.1U_4

VDD_CK_VCC1.05

C402

C402

C189

C189

.1U_4

.1U_4

.1U_4

.1U_4

T251T251

21

Y1

Y1

14.318MHZ

14.318MHZ

R110 2.2K_4R110 2.2K_4
R158 10K_4R158 10K_4

R159 22_4R159 22_4

C235

C235
.1U_4

.1U_4

C381

C381

.1U_4

.1U_4

R121 475_4R121 475_4
R113 *33_4R113 *33_4
R101 33_4R101 33_4
R298 33_4R298 33_4

R123 33_4R123 33_4

VDD_CK_VCC3

C192

C192

C380

C380

.1U_4

.1U_4

.1U_4

.1U_4

VDD_CK_VCC1.05

C183

C183

C240

C240

10U_8

10U_8

10U_8

10U_8

VDD_CK_VCC1.05

SATACLKREQ#_R
PCLK_R5C832_R
PCLK_MINI_R
PCLK_591_R
PCI_CLK_SIO_R
PCLK_ICH_R
CG_XIN
CG_XOUT
FSA
CPU_BSEL1
FSC

ICS9LPRS365AGLFT/ SLG8SP512T

IC(64P) ICS9LPRS365BGLFT(TSSOP)

IC(64P) ICS9LPRS365BGLFT(TSSOP)

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

61

VDD_REF

39

VDD_SRC

55

VDD_CPU

12

VDD_96_IO

20

VDD_PLL3_IO

26

VDD_SRC_IO_1

42

VSS_SRC3

36

VDD_SRC_IO_2

49

VDD_CPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/SRC5_EN

7

PCIF5/ITP_EN

60

XTAL_IN

59

XTAL_OUT

10

USB_48/FSA

57

FSB/TEST/MODE

62

REF0/FSC/TESTSEL

8

VSS_PCI

11

VSS_48

15

VSS_IO

19

VSS_PLL3

52

VSS_CPU

23

VSS_SRC1

29

VSS_SRC2

45

VDD_SRC_IO_3

58

VSS_REF

ICS9LPRS365BGLFT:ALPRS365K13
SLG8SP512T: AL8SP512K05

CK505

CK505

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

CKPWRGD/PWRDWN#

SRC8#/ITP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1/SE1

SRC1#/SE2

SRC0/DOT96

SRC0#/DOT96#

IO_VOUT

SCLK

SDA

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

48

CGCLK_SMB

64

CGDAT_SMB

63
38

37

CLK_CPU_BCLK_R

54

CLK_CPU_BCLK#_R

53

CLK_MCH_BCLK_R

51

CLK_MCH_BCLK#_R

50
47

46

CLK_PCIE_3GPLL#_R

35

CLK_PCIE_3GPLL_R

34

PCIE_CLK_RBS_R

33
32

R_CLK_PCIE_LAN

30

R_CLK_PCIE_LAN#

31
44

43

CLK_PCIE_ICH_R

41

CLK_PCIE_ICH#_R

40

CLK_PCIE_MINI_R

27

CLK_PCIE_MINI#_R

28
24

25

CLK_PCIE_SATA_R

21

CLK_PCIE_SATA#_R

22

DREFSSCLK_R

17

DREFSSCLK#_R

18

DREFCLK_R

13

DREFCLK#_R

14
56

During initial power-up be used to
sample FSB speed with FSA/B/C

RP35 0X2RP35 0X2

1
3

RP34 0X2RP34 0X2

1
3

1

RP36

RP36

3

R155 475_4R155 475_4

3

RP29

RP29

1

RP37 0X2RP37 0X2

1
3

RP30 0X2RP30 0X2

3
1

RP28 0X2RP28 0X2

3
1

3
1

RP31 0X2RP31 0X2

3
1

RP32 0X2RP32 0X2

CK_PWG 19

CGCLK_SMB 15
CGDAT_SMB 15

PM_STPPCI# 19

2
4

2
4

2
4

0X2

0X2

4
2

0X2

0X2

2
4

4
2

4
2

4
2

4
2

PM_STPCPU# 19
HCLK_CPU 4

HCLK_CPU# 4
HCLK_MCH 7

HCLK_MCH# 7

CLK_PCIE_3GPLL# 8
CLK_PCIE_3GPLL 8

CLK_MCH_OE# 8

CLK_PCIE_LAN 24
CLK_PCIE_LAN# 24

CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18

CLK_PCIE_MINI 23
CLK_PCIE_MINI# 23

CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17

DREFSSCLK 8
DREFSSCLK# 8

DREFCLK 8

DREFCLK# 8

C C

CPU_BSEL04

CPU_BSEL14

CPU_BSEL24

D D

R109 0_4R109 0_4

VCC1.05

R310 0_4R310 0_4

VCC1.05

R173 0_4R173 0_4 R162 0_4R162 0_4

VCC1.05

1

CPU_BSEL0_

R107 *56_4R107 *56_4
R95 1K_4R95 1K_4

CPU_BSEL1_

R161 *0_4R161 *0_4
R157 1K_4R157 1K_4

CPU_BSEL2_

R164 *0_4R164 *0_4
R163 1K_4R163 1K_4

R108 0_4R108 0_4

R165 0_4R165 0_4

2

MCH_BSEL0 8

MCH_BSEL1 8

MCH_BSEL2 8

3

BSEL Frequency Select Table

FrequencyFSAFSBFSC

0

0

1

0

0

1

1

0

1

0

1

1

1

0

1

01

1

1

1

0

0

0

4

266Mhz0

133Mhz

166Mhz

200Mhz

400Mhz

Reserved

100Mhz

333Mhz

CGCLK_SMB

CGDAT_SMB

5

PCLK_MINI_R
PCLK_ICH_R
PCI_CLK_SIO_R
SATACLKREQ#_R
PCIE_CLK_RBS_R

PCLK_ICH_R
PCI_CLK_SIO_R

R153

R153
10K_4

10K_4

Clock Gen I2C

VCC3

R154

R154
10K_4

10K_4

R297 10K_4R297 10K_4
R94 *10K_4R94 *10K_4
R124 *10K_4R124 *10K_4
R122 10K_4R122 10K_4
R156 10K_4R156 10K_4

R93 10K_4R93 10K_4
R112 10K_4R112 10K_4

Q6

2

2N7002EQ62N7002E

1

VCC3

Q5

2

2N7002EQ52N7002E

1

6

3

PCLK_SMB 19,23

change1:clock to data wrong connection b-test

3

PDAT_SMB 19,23

VCC3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Clock Generator

Clock Generator

Clock Generator

Date: Sheet

Date: Sheet

Date: Sheet

7

PROJECT : PL3

A

A

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of

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338Wednesday, January 10, 2007

338Wednesday, January 10, 2007

338Wednesday, January 10, 2007

8

1

2

3

4

5

6

7

8

VCC1.05

12

VCC1.5

R60

R60

27.4_4

27.4_4

1 2

438Wednesday, January 10, 2007

438Wednesday, January 10, 2007

438Wednesday, January 10, 2007

4

C153

C153
.1U_4

.1U_4

A

A

A

of

8

H_A#[3..16]7

A A

H_ADSTB#07
H_REQ#[0..4]7

H_A#[17..35]7

B B

H_ADSTB#17

H_A20M#17

H_FERR#17

H_IGNNE#17
H_STPCLK#17

H_INTR17
H_NMI17
H_SMI#17

C C

Populate ITP700Flex for bringup

del r5109 -b-test

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO ITP_DBRESET#
ITP_TRST#

H_RESET#

R174 27_4R174 27_4

D D

R175 680/F_4R175 680/F_4

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

T68T68
T67T67
T82T82
T72T72
T83T83
T93T93
T79T79
T27T27
T65T65
T80T80

VCC1.05

12

R166

R166
*51/F_4

*51/F_4

Layout Note:
Place R8 close ITP.

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

Layout Note:
Place R4,R361,R346 & R7 close to CPU.

12

12

R171

R171

R167

R167

51/F_4

51/F_4

39/F_4

39/F_4

ITP_TCK

12

ITP_TRST#

J4
L5
L4
K5

M3

N2
J1
N3
P5
P2
L2
P4
P1
R1

M1

K3
H2
K2
J3
L1

Y2
U5
R3

W6

U4
Y5
U1
R4
T5

T3
W2
W5

Y4

U2

V4
W3

AA4
AB2
AA3

V1

A6

A5

C4

D5

C6

B4

A3
M4

N5

T2

V3

B2

C3

D2

D22

D3

F6

12

R170

R170
150_4

150_4

U16A

U16A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#

ADDR GROUP 0

ADDR GROUP 0

A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

T64T64
T63T63
T96T96
T71T71
T92T92

T73T73

T95T95
T99T99

CONTROLXDP/ITP SIGNALS

CONTROLXDP/ITP SIGNALS

ADDR GROUP 1

ADDR GROUP 1

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

RESERVED

RESERVED

ITP debug signals

T29T29

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_IERR#

H_RESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

ITP_DBRESET#

R89 0_4R89 0_4

R106 75_4R106 75_4

R103 *2.2K_4R103 *2.2K_4

H_THERMDA
H_THERMDC

R150 *0_4R150 *0_4

12

R80 150_4R80 150_4

12

VCC3

H_ADS# 7
H_BNR# 7
H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

R105 56_4R105 56_4

1 2

H_INIT# 17
H_LOCK# 7
H_RESET# 7

H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

H_HIT# 7
H_HITM# 7

T91T91
T97T97
T84T84
T88T88
T85T85
T78T78

SYS_RST# 19

VCC1.05

H_PROCHOT# 34
H_THERMDA 6

H_THERMDC 6
THERMTRIP#_PWR 6

PM_THRMTRIP# 8,17

HCLK_CPU 3
HCLK_CPU# 3

H_D#[0..63]7

VCC1.05

H_DSTBN#07
H_DSTBP#07
H_DINV#07

Layout Note:
Place voltage
divider within

0.5" of GTLREF
pin

VCC1.05

R53

R53
1K_4

1K_4

1 2

R52

R52
2K/F_4

2K/F_4

1 2

R75 *1K_4R75 *1K_4

1 2

R58 *1K_4R58 *1K_4

1 2

C152 *.1U_4C152 *.1U_4

FSB

H_DSTBN#17
H_DSTBP#17
H_DINV#17

CPU_BSEL03
CPU_BSEL13
CPU_BSEL23

CPU_TEST1
CPU_TEST2

CPU_TEST4

12

BCLK

533 0 0 1133

166

667
800

200

ITP disable guidelines

Signal Resistor Value Connect To Resistor Placement

150 ohm +/- 5%

TDI

39 ohm +/- 1%

TMS

500-680ohm +/- 5%

TRST#

27 ohm +/- 1%

TCK
TDO

150 ohm +/- 5%

VTT
GND
GND
VTT

Note: Populate R5, R8, C372 & R430 when ITP connector is populated.

1

2

3

4

H_D#[0..63]

H_D#[0..63]

BSEL2 BSEL1 BSEL0

0

1
1

Within 2.0" of the ITPVTT
Within 2.0" of the ITP
Within 2.0" of the ITP
Within 2.0" of the ITP
Within 2.0" of the ITP

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

T22T22
T182T182
T153T153

1
00

U16B

U16B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

CPU_TEST3
CPU_TEST5
CPU_TEST6

6

H_D#[0..63]

H_D#32

Y22

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

PSI#

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

H_DSTBN#2 7
H_DSTBP#2 7

H_D#[0..63]

Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.

H_DINV#2 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

ICH_DPRSTP# 8,17,34
H_DPSLP# 17
H_DPWR# 7
H_PWRGD 17
H_CPUSLP# 7
PSI# 34

Reserved for EMI.

COMP0
COMP1
COMP2
COMP3

R169

R169

R168

R168

R59

1 2

27.4_4

27.4_4

1 2

R59

54.9/F_4

54.9/F_4

54.9/F_4

54.9/F_4

1 2

Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU Host Bus

CPU Host Bus

CPU Host Bus

Date: Sheet of

Date: Sheet of

Date: Sheet

7

PROJECT : PL3

1

VCC_CORE

12

A A

VCC_CORE

12

C174

C174
10U_8

10U_8

C171

C171
10U_8

10U_8

12

C394

C394
10U_8

10U_8

12

C176

C176
10U_8

10U_8

8 inside cavity, north side, secondary layer.

VCC_CORE

C204

C204
10U_8

10U_8

C181

C181
10U_8

10U_8

12

C210

C210
10U_8

10U_8

12

C187

C187
10U_8

10U_8

12

B B

VCC_CORE

12

8 inside cavity, south side, secondary layer.

VCC_CORE

C215

C215
10U_8

10U_8

12

C216

C216
10U_8

10U_8

12

6 inside cavity, north side, primary layer.

VCC_CORE

C C

12

C393

C393
10U_8

10U_8

12

C388

C388
10U_8

10U_8

6 inside cavity, south side, primary layer.

VCC1.05

C185

C185
.1U_4

.1U_4

12

C186

C186
.1U_4

.1U_4

12

2

C389

C389
10U_8

10U_8

C376

C376
10U_8

10U_8

C180

C180
10U_8

10U_8

C218

C218
10U_8

10U_8

C219

C219
10U_8

10U_8

C382

C382
10U_8

10U_8

C196

C196
.1U_4

.1U_4

12

C383

C383
10U_8

10U_8

12

C371

C371
10U_8

10U_8

12

C184

C184
10U_8

10U_8

12

C172

C172
10U_8

10U_8

12

12

12

C211

C211
10U_8

10U_8

C378

C378
10U_8

10U_8

C194

C194
.1U_4

.1U_4

12

C206

C206
10U_8

10U_8

12

C375

C375
10U_8

10U_8

12

C207

C207
.1U_4

.1U_4

12

12

12

12

12

12

12

3

VCC_CORE VCC_CORE

12

C379

C379
10U_8

10U_8

12

C173

C173
10U_8

10U_8

12

C193

C193
10U_8

10U_8

12

C177

C177
10U_8

10U_8

12

C195

C195
10U_8

10U_8

12

C370

C370
10U_8

10U_8

12

C205

C205
.1U_4

.1U_4

4

U16C

U16C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

.

.

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENSE

VSSSENSE

5

ICCODE:
for Merom processors
recommended design
target is 44A

ICCP:
1before vccore stable
peak current is 4.5A

2.after vccore stable

VCC1.05

continue current is

2.5A

12

+

+

C202

C202
330U_7343

330U_7343

ICCA 130mA

H_VID0 34
H_VID1 34
H_VID2 34
H_VID3 34
H_VID4 34
H_VID5 34
H_VID6 34

6

VCC1.5

R54

R54
0_6

0_6

12

VCC_CORE

12

C156

C156
.01U_4

.01U_4

Layout Note:
Place C105 near PIN
B26.

C151

C151
10U_8

10U_8

12

R137

R137
100_4

100_4

VCCSENSE 34

12

R140

R140
100_4

100_4

VSSSENSE 34

7

U16D

U16D

A4
A8

A11
A14
A16
A19
A23
AF2

B6
B8

B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3
E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4

K23
K26

L3

L6

L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

8

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

5

Layout out:
Place these inside socket cavity on North side secondary.

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU Power

CPU Power

CPU Power

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

A

of

538Wednesday, January 10, 2007

538Wednesday, January 10, 2007

538Wednesday, January 10, 2007

8

5

CPU Thermal Sensor

4

VCC3

3

2

1

6

D D

C C

SMBus from KBC

MBCLK31,32

MBDATA31,32

Thermal Trip

B B

THERMTRIP#_PWR4

VCC3

Q13

Q13

2

2N7002E

2N7002E

3

VCC3

Q12

Q12

2

2N7002E

2N7002E

3

DELAY_VR_PWRGOOD8,19,34

THERMTRIP#_PWR

VCC1.05

1

1

R148

R148

56.2/F_4

56.2/F_4

THERM_ALERT#19

R274

R274
10K_4

10K_4

R269

R269
10K_4

10K_4

VCC5

VCC1.05

2

1 3

R264 10K_4R264 10K_4

3

Q4

Q4
FDV301N

FDV301N

1

Q3

Q3

2

MMBT3904

MMBT3904

R265 *0_4R265 *0_4

CPUFAN#_ON

U15

U15

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

MAX6657

MAX6657

ADDRESS: 98H

SYS_SHDN# 33

R289

R289
200_6

200_6

LM86VCC

C373

C373
.1U_4

.1U_4

1

VCC

2

DXP

3

DXN

5

GND

<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard

C367

C367
2200P_4

2200P_4

VFAN31

H_THERMDA

H_THERMDC

C360

C360
.1U_4

.1U_4

CPUFAN#_ON

VCC5

H_THERMDA 4

H_THERMDC 4

CPU FAN Control

FANSIG31

U13

U13

VIN2VO

1

/FON

4

VSET

G995

G995

GND
GND
GND
GND

3
5
6
7
8

TH_FAN_POWER

TH_FAN_POWER

C354

C354
10U_8

10U_8

C353

C353
.01U_4

.01U_4

C358

C358
*.01U_4

*.01U_4

VCC3

R259

R259
10K_4

10K_4

CN13

CN13

1
2
3

FAN-CONN

FAN-CONN

4

5

FANPWR = 1.6*VSET

<CRB & Design guide>
Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing
(ZS1 default NC)

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thermal/FAN Control

Thermal/FAN Control

Thermal/FAN Control

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

A

638Wednesday, January 10, 2007

638Wednesday, January 10, 2007

638Wednesday, January 10, 2007

of

of

of

1

2

3

4

5

6

7

8

7

U12A

M10
N12

W10

AD12

AE3
AD9
AC9

AC7
AC14
AD11
AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9
AE11
AH12

AH5

AE7

AE5

AH2
AH13

E2
G2
G7

M6

H7
H3
G4
F3
N8
H2

N9
H5

P13

K9

M2

Y8
V4
M3

J1
N5
N3

W6
W9

N2
Y7
Y9
P4

W3

N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6
E5

B9
A9

U12A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

CRESTLINE_1p0

H_ADSTB#_0
H_ADSTB#_1

HOST

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

12

C327

C327
.1U_4

.1U_4

H_D#[0..63]

H_RESET#4

H_CPUSLP#4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_REF

H_D#[0..63]4

A A

VCC1.05

12

R246

R246
221_4

221_4

0.331V

H_SWING

12

R245

R245
100_4

100_4

B B

VCC1.05

C324

C324
.1U_4

.1U_4

1 2

impedance 55 ohm

12

12

R8

R9

54.9/F_4R854.9/F_4

54.9/F_4R954.9/F_4

H_SCOMP
H_SCOMP#

12

R244

R244

24.9_4

24.9_4

C C

H_RCOMP

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.

0.705V

VCC1.05

R248

R248
1K_4

1K_4

1 2

12

R247

R247
2K/F_4

2K/F_4

H_A#[3..35]

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4

H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4

H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4

H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

H_A#[3..35] 4

HCLK_MCH 3
HCLK_MCH# 3

Layout Note:
Place the 0.1 uF

D D

1

2

decoupling capacitor
within 100 mils from
GMCH pins.

3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH HOST

GMCH HOST

GMCH HOST

Date: Sheet of

Date: Sheet of

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

A

of

738Wednesday, January 10, 2007

738Wednesday, January 10, 2007

738Wednesday, January 10, 2007

8

1

2

3

4

5

6

7

8

U12B

U12B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

CFG3
CFG4
CFG5
CFG6

CFG8
CFG9
CFG10

CFG12
CFG13

CFG16

CFG19
CFG20

AL36

AM37

D20

H10

B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23

BG23

BC23
BD24
BJ29
BE24
BH39

AW20

BK20

C48

D47

B44

C44

A35

B37

B36

B34

C34

P27
N27
N24
C21
C23
F23
N23

G23

J20
C20
R24

L23

J23
E23
E20
K23
M20
M24

L32

N33

L35

G41

L39

L36

J36

AW49

AV20

N20
G36

BJ51
BK51
BK50
BL50
BL49

BL3
BL2
BK1
BJ1

E1

A5
C51
B50
A50
A49
BK2

CRESTLINE_1p0

CRESTLINE_1p0

RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
SA-MA14
SB_MA14
RSVD34
RSVD35
RSVD36
LVDSA_DATA#_3
LVDSA_DATA_3
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

DDR MUXINGCLKDMI

DDR MUXINGCLKDMI

CFGRSVD

CFGRSVD

PM

PM

GRAPHICS VIDME

GRAPHICS VIDME

NC

NC

MISC

MISC

SM_RCOMP_VOH
SM_RCOMP_VOL

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SDVO_CTRL_CLK

SDVO_CTRL_DATA

A A

12

C328

C328
.1U_4

.1U_4

SA_MA1415,16
SB_MA1415,16

T145T145
T20T20

B B

MCH_BSEL03
MCH_BSEL13
MCH_BSEL23

MCH_CFG_513

MCH_CFG_913

MCH_CFG_1213
MCH_CFG_1313

MCH_CFG_1613

MCH_CFG_1913
MCH_CFG_2013

PM_BMBUSY#19
ICH_DPRSTP#4,17,34
PM_EXTTS#015
PM_EXTTS#115

DELAY_VR_PWRGOOD6,19,34

C C

PM_THRMTRIP#4,17

PM_DPRSLPVR19,34

VCC3

R42 10K_4R42 10K_4

1 2

R38 10K_4R38 10K_4

1 2

R45 10K_4R45 10K_4

1 2

PLT_RST-R#18

PM_EXTTS#0
PM_EXTTS#1
PCIE_REQ4#

T7T7
T132T132

T10T10
T2T2
T3T3

T11T11
T6T6

T4T4
T5T5

T9T9
T14T14

R57 0_4R57 0_4
R44 0_4R44 0_4

R19 100_4R19 100_4
R15 *0_4R15 *0_4
R55 0_4R55 0_4

T148T148
T147T147
T146T146
T141T141
T142T142
T130T130
T125T125
T126T126
T127T127
T128T128
T131T131
T152T152
T151T151
T149T149
T144T144
T129T129

CFG15
CFG17

CFG18

TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9

TP_NC10

TP_NC11
TP_NC12

TP_NC13

TP_NC14

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_VREF_0
SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_A_CLK0 15
M_A_CLK1 15
M_B_CLK0 15
M_B_CLK1 15

M_A_CLK0# 15
M_A_CLK1# 15
M_B_CLK0# 15
M_B_CLK1# 15

M_A_CKE0 15,16
M_A_CKE1 15,16
M_B_CKE0 15,16
M_B_CKE1 15,16

M_A_CS#0 15,16
M_A_CS#1 15,16
M_B_CS#0 15,16
M_B_CS#1 15,16

M_A_ODT0 15,16
M_A_ODT1 15,16
M_B_ODT0 15,16
M_B_ODT1 15,16

SMRCOMPP
SMRCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

SMDDR_VREF_MCH

CLK_PCIE_3GPLL 3
CLK_PCIE_3GPLL# 3

DFGT_VID_0
DFGT_VID_1
DFGT_VID_2
DFGT_VID_3
DFGT_VR_EN

MCH_CLVREF

T15T15
T17T17

PCIE_REQ4#

R33

R33
20K_4

20K_4

1 2

1 2

C44 .1U_4C44 .1U_4
C143 .1U_4C143 .1U_4
R7 0_4R7 0_4

DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3

DMI_TXN[3:0] 18

DMI_TXP[3:0] 18

DMI_RXN[3:0] 18

DMI_RXP[3:0] 18

T133T133
T136T136
T135T135
T137T137
T134T134

CL_PWROK 19
CL_RST#0 19

CLK_MCH_OE# 3

R254

R254
0_4

0_4

DIGON14

CL_CLK0 19
CL_DATA0 19

MCH_ICH_SYNC# 19

VCC3

SMDDR_VREF

INT_LVDS_BKLT_PWM14

CRT_B14
CRT_G14
CRT_R14

BLON14

LVDS_CLK14
LVDS_DAT14

R49 2.4K_4R49 2.4K_4

TXLCLKOUT#14
TXLCLKOUT14

TXLOUT#014
TXLOUT#114
TXLOUT#214

TXLOUT014
TXLOUT114
TXLOUT214

R22 150_4R22 150_4
R20 150_4R20 150_4
R21 150_4R21 150_4

T13T13
T12T12

INTEL FAE (08/17)
PD 0OHM

DDCCLK14
DDCDAT14
HSYNC14

VSYNC14

R35 1.3K_4R35 1.3K_4

R34 150_4R34 150_4
R26 150_4R26 150_4
R25 150_4R25 150_4

0.333V

R41 10K_4R41 10K_4
R48 10K_4R48 10K_4

LVDS_IBG

T150T150

T16T16
T18T18

T19T19
T140T140
T139T139

T21T21
T143T143
T138T138

TV_COMP
TV_Y/G
TV_C/R

TV_DCONSEL_0
TV_DCONSEL_1

R37 0_4R37 0_4
R32 0_4R32 0_4

R30 0_4R30 0_4
R28 0_4R28 0_4
R23 0_4R23 0_4

DDCCLK
DDCDAT

R253 39_4R253 39_4

CRTIREF

R252 39_4R252 39_4

MCH_CLVREF

C355

C355
.1U_4

.1U_4

1 2

CRT_B_R
CRT_G_R
CRT_R_R

HSYNC_C
VSYNC_C

CRTIREF

CRT_B_R
CRT_G_R
CRT_R_R

VCC1.25 1.8VSUS

12

R262

R262
1K_4

1K_4

12

R260

R260
392_4

392_4

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27
J27
L27

M35

P33

H32
G32
K29
J29
F29
E29

K33
G35
F33
C32
E33

U12C

U12C

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

CRESTLINE_1p0

CRESTLINE_1p0

C106*.1U_4C106*.1U_4

C100*.1U_4C100*.1U_4

C91 *.1U_4C91 *.1U_4

SMRCOMPP
SMRCOMPN

1 2

12

12

VCC3G_PCIE_R

N43

PEG_COMPI

M43

PEG_COMPO

J51

PEG_RX#_0

L51

PEG_RX#_1

N47

PEG_RX#_2

T45

PEG_RX#_3

T50

PEG_RX#_4

U40

PEG_RX#_5

Y44

PEG_RX#_6

Y40

PEG_RX#_7

AB51

PEG_RX#_8

W49

PEG_RX#_9

LVDS

LVDS

TV VGA

TV VGA

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

CRT_B

CRT_G

CRT_R

12

R12

R12
20_4

20_4

12

R11

R11
20_4

20_4

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

1.439V

SM_RCOMP_VOH

12

C107

C107
.01U_4

.01U_4

SM_RCOMP_VOL

12

C97

C97
.01U_4

.01U_4

AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

12

12

C120

C120

2.2U_8

2.2U_8

C102

C102

2.2U_8

2.2U_8

1.8VSUS

12

12

12

R51 24.9_4R51 24.9_4

1 2

R36

R36
1K_4

1K_4

R31

R31

3.01K/F

3.01K/F

0.360V

R29

R29
1K_4

1K_4

1.05V_VCC_PEG

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH (VGA,DMI)

GMCH (VGA,DMI)

GMCH (VGA,DMI)

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

838Wednesday, January 10, 2007

838Wednesday, January 10, 2007

838Wednesday, January 10, 2007

8

A

of

of

of

1

2

3

4

5

6

7

8

9

M_A_DQ[63:0]15 M_B_DQ[63:0]15

A A

B B

C C

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BD8
AY9

BG10

AW9

BD7
BB9
BB5
AY7

AY6
BB7
AR5
AR8
AR9
AN3
AM8

AN10

AN9
AM9

AN11

AT5
AT7

AT9

U12D

U12D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_WE#

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

M_A_DQM0
M_A_DQM1
M_A_DQM2
M_A_DQM3
M_A_DQM4
M_A_DQM5
M_A_DQM6
M_A_DQM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

TP_SA_RCVEN#

M_A_BS#0 15,16
M_A_BS#1 15,16
M_A_BS#2 15,16

M_A_CAS# 15,16
M_A_DQM[0..7] 15

M_A_DQS[7:0] 15

M_A_DQS#[7:0] 15

M_A_A[13:0] 15,16

T8T8

M_A_RAS# 15,16

M_A_WE# 15,16

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12

BG12

BJ10

BL9
BK5
BL5
BK9

BK10

BJ8
BJ6
BF4

BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1

AT3
AY2
AY3
AU2

AT2

U12E

U12E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

TP_SB_RCVEN#

M_B_BS#0 15,16
M_B_BS#1 15,16
M_B_BS#2 15,16

M_B_CAS# 15,16
M_B_DQM[0..7] 15

M_B_DQS[7:0] 15

M_B_DQS#[7:0] 15

M_B_A[13:0] 15,16

M_B_RAS# 15,16

T1 *PADT1 *PAD

M_B_WE# 15,16

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH DDR2

GMCH DDR2

GMCH DDR2

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

A

of

938Wednesday, January 10, 2007

938Wednesday, January 10, 2007

938Wednesday, January 10, 2007

8

AT35

AT34
AH28
AC32
AC31

AK32

AJ31

AJ28
AH32
AH31
AH29

AF32

R30

AU32
AU33
AU35

AV33
AW33
AW35

AY35

BA32

BA33

BA35

BB33
BC32
BC33
BC35
BD32
BD35

BE32

BE33

BE35

BF33

BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34

BK32

BK33

BK34

BK35

BL33
AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24

AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28

AF21

AF26

AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

5

U12G

U12G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

VCC CORE

POWER

POWER

VCC SMVCC GFX

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

VCC1.05

D D

IVCCSM MAX: 3.318A

1.8VSUS

C C

VCC1.05

B B

A A

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

4

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

Ivcc (External GFX 1.310 A,
integrate 1.572 A)

Layout Note:
370 mils from edge.

12

+

+

C317

C317
330U_7343

330U_7343

Layout Note:
Inside GMCH cavity for VCC_AXG.

12

C70

C70
.1U_4

.1U_4

GMCH 1.05V

VCC Core

VCC_AXG

VCC_AXD

VTT

VCC_PEG

VCC_AXM

VCCR_RX_DMI

12

+

+

C319

C319
330U_7343

330U_7343

12

C95

C95
.1U_4

.1U_4

current(A)

1.573

7.7

0.2

0.85

1.2

0.54

0.25

Ivcc_AXG Graphics core supply
current 7.7A

12

12

C83

C83
.47U_6

.47U_6

Remark

( 1.3A for
external
GFX )

for integrated
Gfx

FSB VCCP

for PCIEG

for IAMT
function

DMI

12.313SUM

12

C51

C51
.1U_4

.1U_4

12

12

C49

C49
.1U_4

.1U_4

C38

C38
.22U_6

.22U_6

3

VCC1.05

12

+

+

C320

C320
220U_7343

220U_7343

Layout Note:
370 mils from edge.

12

C96

C96

C57

C57

1U_6

1U_6

10U_8

10U_8

VCC1.05

Ivcc_AXM
Controller
supply
current
540mA

C46

C46
.22U_6

.22U_6

12

C125

C125
.47U_6

.47U_6

12

VCC3

R249 10_4R249 10_4

1 2

12

Layout Note:
Inside GMCH cavity.

12

12

C326

C326
22U_8

22U_8

C60

C60
22U_8

22U_8

C108

C108
.22U_6

.22U_6

12

C124

C124
.1U_4

.1U_4

12

C135

C135
22U_8

22U_8

Layout Note:
Place close to GMCH edge.

12

12

C130

C130
1U_6

1U_6

C139

C139
1U_6

1U_6

CH751H-40HPT

CH751H-40HPT

12

C134

C134
.22U_6

.22U_6

VCC1.05

Layout Note:
Inside GMCH
cavity.

12

C115

C115
.1U_4

.1U_4

12

C84

C84
.22U_6

.22U_6

2

U12F

D11

D11

21

12

C118

C118
.1U_4

.1U_4

12

C117

C117
.1U_4

.1U_4

12

C116

C116
.22U_6

.22U_6

from CH73301M8L9 to CH733LM8812 1/11

1.8VSUS

12

C119

C119
.1U_4

.1U_4

Layout Note:
Place C901 where LVDS
and DDR2 taps.

U12F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

CRESTLINE_1p0

+

+

12

C138

C138
330U_7343

330U_7343

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS NCTF

VSS NCTF

VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VCC NCTF

VCC NCTF

POWER

POWER

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

VCC AXM NCTF

VCC AXM NCTF

1.8VSUS

12

12

Layout Note:
Place on the edge.

C131

C131
22U_8

22U_8

C114

C114
22U_8

22U_8

1

10

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

VCC1.05

CRESTLINE_1p0

CRESTLINE_1p0

5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH VCC,NCTF

GMCH VCC,NCTF

GMCH VCC,NCTF

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

A

of

10 38Thursday, January 11, 2007

10 38Thursday, January 11, 2007

10 38Thursday, January 11, 2007

5

VCC3

D D

VCC1.25

VCC1.25

C C

VCC1.5

VCC3

B B

1.25V_VCC_AXF

1.8VSUS_VCC_SM_CK

A A

BLM18PG181SN1D

BLM18PG181SN1D

1 2

L4

L4

1 2

BLM18PG181SN1D

BLM18PG181SN1D

L21

L21

1 2

BLM18PG181SN1D

BLM18PG181SN1D

12

C332

C332
1U_6

1U_6

12

C79

C79
10U_8

10U_8

L3

L3
BLM18PG181SN1D

BLM18PG181SN1D

1 2

5

L23

L23

1 2

3V_VCCSYNC

1.25V_VCCA_DPLLA

L7

L7
BLM18PG181SN1D

BLM18PG181SN1D

1.5V_VCCD_TVDAC

12

C90

C90
.1U_4

.1U_4

3V_TV_DAC

12

C337

C337
10U_8

10U_8

R251 0_6R251 0_6

12

C333

C333
10U_8

10U_8

Place caps close
to VCC_AXF

12

12

C74

C74
.1U_4

.1U_4

12

C345

C345

C111

C111

.1U_4

.1U_4

.1U_4

.1U_4

12

12

C36

C36

C35

C35

10U_8

10U_8

.1U_4

.1U_4

1.25V_VCCA_PEG_PLL

12

C155

C155
10U_8

10U_8

12

C99

C99
.1U_4

.1U_4

12

12

C93

C93

C339

C339

.1U_4

.1U_4

.1U_4

.1U_4

VCC1.25

L5

L5

1 2

BLM18PG181SN1D

BLM18PG181SN1D

C78

C78
10U_8

10U_8

12

12

C344

C344
.1U_4

.1U_4

12

12

C146

C146
.1U_4

.1U_4

VCC1.25

C336

C336
.1U_4

.1U_4

1.8VSUS

C142

C142
.1U_4

.1U_4

1.8VSUS

VCC3

12

C149

C149
.1U_4

.1U_4

VCC1.25

R47 0_6R47 0_6

VCC1.25

250mA

R258 0_6R258 0_6

4

12

C41

C41
.1U_4

.1U_4

4

1 2

C89

C89

+

+

*100U_7343

*100U_7343

12

C127

C127
10U_8

10U_8

1.25V_VCCA_PEG_PLL

C43

C43
.1U_4

.1U_4

C137

C137
1U_6

1U_6

3V_VCCA_DAC_BG

VCC3

C133

C133
1U_6

1U_6

L22

L22
BLM18PG181SN1D

BLM18PG181SN1D

R10 0_8R10 0_8

12

12

12

12

12

C144

C144
.1U_4

.1U_4

1 2

C352

C352
10U_8

10U_8

C67

C67

4.7U_6

4.7U_6

12

C341

C341
.1U_4

.1U_4

1.25V_VCCA_PEG_PLL

1.25V_VCCA_SM_CK

12

C98

C98
.1U_4

.1U_4

1.8VSUS_VCC_TX_LVDS

1.25V_VCCA_SM

12

C58

C58
10U_8

10U_8

12

C140

C140
.1U_4

.1U_4

VTTLF1
VTTLF2
VTTLF3

12

3V_VCCSYNC

3V_VCCA_DAC_BG

1.25V_VCCA_DPLLA

12

C47

C47
10U_8

10U_8

3V_TV_DAC

1.5V_VCCD_TVDAC

1.8V_VCCD_LVDS

12

C37

C37
.47U_6

.47U_6

3

100mA

12

C66

C66
1U_6

1U_6

150mA

C323

C323
.47U_6

.47U_6

3

C349

C349
1000P_4

1000P_4

12

C325

C325
.47U_6

.47U_6

AM2

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

AN2

A33
B33

A30
B32

B49
H49
AL2

A41
B41

K50
K49

U51

C25
B25
C27
B27
B28
A28

M32

N28

U48

H42

J32

L29

J41

U12H

U12H

VCCSYNC
VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1

VCCD_LVDS_2

3V_VCC_HV

3V_VCC_HV

CRTPLLA PEGA SMTV

CRTPLLA PEGA SMTV

POWER

POWER

A CK A LVDS

A CK A LVDS

D TV/CRTLVDS

D TV/CRTLVDS

D12

D12
CH751H-40HPT

CH751H-40HPT

R255 0_4R255 0_4

VTT_10
VTT_11
VTT_12
VTT_13
VTT_14

VTT

VTT

VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

AXD

AXD

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

PEG

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

VTTLF

CRESTLINE_1p0

CRESTLINE_1p0

VCC1.05

21

40 mil
wide

12

R256

R256
10_4

10_4

Ivcc_PEG
supply current

1.2A

VCC3

2

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9

2

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

change p/n:FROM CH44701ZB38 TO CH4471Z3B07

12

12

12

C52

C52

2.2U_6

2.2U_6

1.25V_AXD

12

C86

C86
1U_6

1U_6

1.25V_VCC_AXF

1.25V_VCC_DMI_MCH

1.8VSUS_VCC_SM_CK

200mA

1.8VSUS_VCC_TX_LVDS

12

1.05V_VCC_PEG

1.05V_VCC_RXR_DMI

VTTLF1
VTTLF2
VTTLF3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

C348

C348
.1U_4

.1U_4

12

C42

C42

C31

C31

.47U_4

.47U_4

4.7U_8

4.7U_8

12

C85

C85

C71

C71

1U_6

1U_6

22U_1206

22U_1206

1.25V_VCC_AXF

3V_VCC_HV

1.05V_VCC_PEG

12

C147

C147
.1U_4

.1U_4

12

12

C357

C357
.1U_4

.1U_4

GMCH POWER

GMCH POWER

GMCH POWER

1

VCC1.05

12

12

+

+

C32

C32

C321

C321

Ivcc_VTT FSB

220U_7343

220U_7343

VCC1.05

supply
current

0.85A

11 38Wednesday, January 10, 2007

11 38Wednesday, January 10, 2007

11 38Wednesday, January 10, 2007

4.7U_8

4.7U_8

R13 0_8R13 0_8

12

C104

C104
1U_6

1U_6

R261 0_6R261 0_6

12

C356

C356
.1U_4

.1U_4

R257 0_6R257 0_6

12

C350

C350
1000P_4

1000P_4

L6

L6

1 2

BLM18PG181SN1D

BLM18PG181SN1D

12

C150

C150
10U_6

10U_6

L24

L24

1 2

BLM18PG181SN1D

BLM18PG181SN1D

Ivcc_RX_DMI

C359

C359

supply current

10U_6

10U_6

250mA

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

1

11

VCC1.25

VCC1.25

1.8VSUS

VCC1.05

of

of

of

A

A

A

5

U12I

U12I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

D D

C C

B B

A A

5

AB20
AB23
AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43

AC47

AD1
AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AL1
AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4

AP48
AP50

AR11

AR2
AR39
AR44
AR47

AR7

AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51

AV39
AV48

AW1
AW12
AW16

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

CRESTLINE_1p0

VSS

VSS

4

4

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U12J

U12J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

CRESTLINE_1p0

3

VSS

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

2

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH VSS

GMCH VSS

GMCH VSS

Date: Sheet of

Date: Sheet of

2

Date: Sheet

PROJECT : PL3

1

1

12

of

12 38Wednesday, January 10, 2007

12 38Wednesday, January 10, 2007

12 38Wednesday, January 10, 2007

A

A

A