LG LEO2 B Users manual
Updated
2008-09-08
File
LEO2 Platform Hardware Manual
Rev.
V1.0
Title
LEO2-B Platform Hardware Manual
ABSTRACT 1
This document is hardware manual for LEO2-B Platform board. Contents of this document are 2
descriptions of each blocks and usage directions. It is recommended to peruse this manual before 3
operating LEO2-B Platform 4
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HISTORY 7
Rev Status
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KEY WORDS 9
Date Author Contents
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Type
Manual
Mobile Communication Technology Research Lab.
533 Hogye-dong, Dongan-gu, Anyang-shi,
Kyongki-do, KOREA
©Copyright, 2008 By LG Electronics Inc. All rights reserved.
No part of this document may be reproduced in any way, or by any means, without
the express written permission of LG Electronics Inc.
LGE Proprietary i MCTR Lab.
Updated
2008-09-08
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File
LEO2 Platform Hardware Manual
Rev.
V1.0
[Notice] 45
1. The product described in this manual may be modified without prior notice for reliability, 46
functionality or design improvement. 47
2. Information contained in this manual is correct and reliable, but LG shall not be held 48
responsible for damage due to the use of information, product or circuit or infringement of 49
property rights or other rights. 50
3. This manual does not grant users the property rights and other rights of the third party or 51
LG Electronics Inc. 52
4. No part of this manual may be transcribed or duplicated without the written permission of 53
LG Electronics Inc. 54
5. The appearance of the product shown in this manual may slightly differ from that of the 55
actual product. 56
LGE Proprietary ii MCTR Lab.
Updated
2008-09-08
File
LEO2 Platform Hardware Manual
Rev.
V1.0
CONTENTS 1
1. Introduction............................................................................................................................... １ 2
1.1 Scope ..................................................................................................................................... １ 3
1.2 Terminology............................................................................................................................ １ 4
1.3 Trademark List........................................................................................................................ １ 5
1.4 Special Mark........................................................................................................................... １ 6
2. Features and top level diagram ................................................................................................. ２ 7
2.1 Features ................................................................................................................................. ２ 8
2.2 Photograph of the LEO2-B platform board............................................................................... ２ 9
2.3 Top level block diagram .......................................................................................................... ３ 10
2.4 Placement map....................................................................................................................... ３ 11
3. Block description....................................................................................................................... ４ 12
3.1 FPGA subsystem.................................................................................................................... ４ 13
3.2 ARM subsystem...................................................................................................................... ４ 14
3.3 Debugger Interface ................................................................................................................. ５ 15
3.4 RF Interface............................................................................................................................ ６ 16
3.5 Reference Clock ..................................................................................................................... ７ 17
3.6 Reset ...................................................................................................................................... ８ 18
3.7 Application interface................................................................................................................ ８ 19
3.8 Power Supplies....................................................................................................................... ９ 20
4. DIP switch, LED and logic probing connector ............................................................................ ９ 21
4.1 ARM Processor debugging configuration switch setting........................................................... ９ 22
4.2 General purpose LED indication........................................................................................... １０ 23
4.3 Logic probing connector....................................................................................................... １１ 24
5. Description of Smart antenna and beam forming modes if applicable ..................................... １２ 25
6. Reference............................................................................................................................ １２3 26
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LGE Proprietary iii MCTR Lab.
Updated
2008-09-08
File
LEO2 Platform Hardware Manual
Rev.
V1.0
1
FIGURES 2
Figure 1. Photograph of LEO2-B platform........................................................................................ ２ 3
Figure 2. Top level block diagram.................................................................................................... ３ 4
Figure 3. Placement map of LEO2-B ............................................................................................. ３ 5
Figure 4. ARM processor Block ..................................................................................................... ４ 6
Figure 5. RF interface on LEO2-B platform board ............................................................................ ６ 7
Figure 6. Block diagram of RF daughter board................................................................................. ６ 8
Figure 7. Block diagram of clock distribution .................................................................................... ７ 9
Figure 8. Block diagram of platform board reset scheme.................................................................. ８ 10
Figure 9. Block diagram of application interface............................................................................... ８ 11
Figure 10. Block diagram of power supplies..................................................................................... ９ 12
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LGE Proprietary iv MCTR Lab.
Updated
2008-09-08
File
LEO2 Platform Hardware Manual
Rev.
V1.0
1
TABLES 2
Table 1. ARM processor setting DIP switches............................................................................... １０ 3
Table 2. LED signal mapping........................................................................................................ １１ 4
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LGE Proprietary v MCTR Lab.
1. Introduction 1
2
1.1 Scope 3
This document intends to describe the brief architecture and usage of the LEO2-B Platform 4
board. LEO2-B Platform board is designed for LTE User Equipment test and verification. 5
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1.2 Terminology 8
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ADC Analog to Digital Converter 10
AMBA Advanced Microcontroller Bus Architecture 11
AHB Advanced High-performance Bus 12
DAC Digital to Analog Converter 13
DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory 14
EPI External Perallel Interface 15
ETM Embedded Trace Macro-cell 16
JTAG Joint Test Action Group 17
LNA Low Noise Amplifier 18
UE User Equipment 19
UART Universal Asynchronous Receiver/Transmitter 20
SDIO Secure Digital Input Output 21
USB Universal Serial Bus 22
VGA Variable Gain Amplifier 23
ZDB Zero Delay BufferAMBA 24
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1.3 Trademark List 27
ARM926EJ-S are registered trademarks of ARM Ltd. 28
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1.4 Special Mark 31
The following table defines special marks used in this manual. 32
Mark Definition
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Updated
2008-09-08
File
LEO2 Platform Hardware Manual
Rev.
V1.0
LGE Proprietary
１
MCTR Lab.
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