LG KS10 User Manual

Date: July, 2007 / Issue 1.0

Service Manual

KS10

Model : KS10

- 3 -

1. INTRODUCTION.................................. 5

1.1 Purpose ...................................................... 5

1.2 Regulatory Information ............................... 5

2. PERFORMANCE ..................................7

2.1 System Overview.........................................7

2.2 Usable environment.....................................8

2.3 Radio Performance......................................8

2.4 Current Consumption.................................14

2.5 RSSI BAR ..................................................14

2.6 Battery BAR ...............................................15

2.7 Sound Pressure Level ...............................16

2.8 Charging ....................................................16

3. TECHNICAL BRIEF............................17

3.1 General Description ...................................17

3.2 GSM Mode.................................................19

3.3 UMTS Mode...............................................23

3.4 LO Phase-locked Loop ..............................26

3.5 Off-chip RF Components ...........................29

3.6 Digital Baseband

(Stn8810 / MSM6275)................................34

3.7. Hardware Architecture ..............................36

3.8. Subsystem of STn8810 ............................39

3.9. Hardware Peripheral system of

Stn8810 ....................................................42

3.10. Subsystem of MSM6275.........................47

3.11. External memory interface......................50

3.12. Hardware sub system of MSM6275........51

3.13. Audio and sound.....................................61

3.14. Camera interface ....................................67

3.15 Bluetooth..................................................76

3.16 Main Features..........................................77

4. TROUBLE SHOOTING.......................83

4.1 RF Component ..........................................83

4.2 SIGNAL PATH ...........................................85

4.3 Checking VCXO Block...............................87

4.4 Checking Ant. Switch Module Block ..........91

4.5 Checking WCDMA Block ...........................93

4.6 Checking GSM Block...............................103

4.7 Power on trouble......................................111

4.8 USB trouble .............................................114

4.9 SIM detect trouble....................................115

4.10 Key sense trouble ..................................116

4.11 Keypad backlight trouble .......................118

4.12 Folder on/off trouble...............................120

4.13 Micro SD trouble ....................................122

4.14 Charging trouble ....................................124

4.15 Audio trouble..........................................127

4.16 Camera trouble ......................................143

4.17 Main LCD trouble...................................149

4.18 Bluetooth trouble....................................152

5. DOWNLOAD.....................................155

5.1 Composition omposition ..........................155

5.2 LGDP2 Program install LGDP2 Program

install........................................................156

5.3 USB Driver setup USB Driver setup ........159

5.4 KS10 LGDP2 run file & DLL file setup .....162

5.5 Execute LGDP2 program.........................163

6. BLOCK DIAGRAM ...........................178

6.1 GSM & WCDMA RF Block.......................178

6.2 Interface Diagram ....................................180

6.3 KS10 Modem & Baseband

Block Diagram .........................................184

6.4 KS10 Application Processor Block

Diagram ...................................................185

6.5 KS10 Audio & BT Block Diagram ............186

Table Of Contents

LGE Internal Use Only

- 4 -

6.6 KS10 Camera Block Diagram .................187

6.7 KS10 LCD Block Diagram ......................188

6.8 KS10 Power Distribution Diagram ...........189

6.9 KS10 Clock Distribution Diagram ...........190

7. Circuit Diagram................................177

8. PCB LAYOUT ...................................202

9. Usage of Hot-Kimchi .......................209

9.1 Usage of Hot-Kimchi................................195

10. Engineering Mode .........................212

10.1 Version Info............................................213

10.2 Device Test............................................213

10.3 Factory Reset ........................................214

10.4 MTC .......................................................214

10.5 Save Log................................................214

11. EXPLODED VIEW & REPLACEMENT

PART LIST ..................................... 216

10.1 EXPLODED VIEW ................................ 216

10.2 Replacement Parts

<Mechanic component> ....................... 219

<Main component> ............................... 222

10.3 Accessory ............................................. 246

LGE Internal Use Only

Only for training and service purposes

- 5 -

LGE Internal Use Only

1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the features of this model.

1.2 Regulatory Information

A. Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of commoncarrier telecommunication service of facilities accessed through or connected to it. The manufacturer will not be responsible for any charges that result from such unauthorized use.

B. Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.

C. Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the phones or compatibility with the net work, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.

D. Maintenance Limitations

Maintenance limitations on the phones must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.

1. INTRODUCTION

- 6 -

LGE Internal Use Only

Only for training and service purposes

E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. In accordance with these agencies, you may be required to provide information such as the following to the end user.

F. Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.

G. Interference and Attenuation

A phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from unsuppressed engines or electric motors may cause problems.

H. Electrostatic Sensitive Devices

ATTENTION

Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign. Following information is ESD handling:

• Service personnel should ground themselves by using a wrist strap when exchange system boards.

• When repairs are made to a system board, they should spread the floor with anti-static mat which is also grounded.

• Use a suitable, grounded soldering iron.

• Keep sensitive parts in these protective packages until these are used.

• When returning system boards or parts like EEPROM to the factory, use the protective package as described.

1. INTRODUCTION

- 7 -

LGE Internal Use Only

2. PERFORMANCE

2.1 System Overview

2. PERFORMANCE

Item Specification

Shape GSM900/1800/1900 and WCDMA Slide Handset

Size 104 X 52 X 18.9 mm

Weight 118 g (with 950mAh Battery)

Power 3.7V normal, 950 mAh Li-Polymer

Talk Time Over 150 min (WCDMA, Tx=12 dBm, Voice)

(with 950mAh) Over 175 min (GSM, Tx=Max, Voice)

Standby Time Over 200 Hrs (WCDMA, DRX=1.28)

(with 950mAh) Over 220 Hrs (GSM, Paging period=9)

Antenna Internal type and Antenna

LCD Main 240 X 320 pixel TFT (QVGA LCD Module)

LCD Backlight Blue LED Back Light (main only)

Camera Dual Camera ; 1.3 Mega pixel (CMOS), VGA Camera (CMOS)

Vibrator Yes (Cylinder Type)

LED Indicator No

MIC Yes

Receiver Yes

Earphone Jack Yes

Connectivity Bluetooth, USB

Volume Key Push Type(+, -)

External Memory Micro-SD

I/O Connect 18 Pin

- 8 -

LGE Internal Use Only

Only for training and service purposes

2.2 Usable environment

1) Environment

2) Environment (Accessory)

* CLA : 12 ~ 24 V(DC)

2.3 Radio Performance

1) Transmitter - GSM Mode

* In case of DCS : [A] -> 1710, [B] -> 1785 * In case of PCS : [A] -> 1850, [B] -> 1910

2. PERFORMANCE

Item Specification

Voltage 3.7 V(Typ), [Shut Down : 3.22 V]

Operation Temp -20 ~ +60°C

Storage Temp -20 ~ +70°C

Humidity 85 % (Max)

Reference Spec. Min Typ. Max Unit

TA Power Available power 100 220 240 Vac

No Item GSM DCS & PCS

100k~1GHz -39dBm

9k ~ 1GHz -39dBm

MS allocated 1G~[A]MHz -33dBm

Channel

1G~12.75GHz -33dBm

[A]M~[B]MHz -39dBm

Conducted [B]M~12.75GHz -33dBm

1 Spurious 100k~880MHz -60dBm 100k~880MHz -60dBm

Emission 880M~915MHz -62dBm 880M~915MHz -62dBm

Idle Mode

915M~1GHz -60dBm 915M~1GHz -60dBm

1G~[A]MHz -50dBm 1G~[A]MHz -50dBm

[A]M~[B]MHz -56dBm [A]M~[B]MHz -56dBm

[B]M~12.5GHz -50dBm [B]M~12.5GHz -50dBm

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LGE Internal Use Only

2. PERFORMANCE

* In case of DCS : [A] -> 1710, [B] -> 1785 * In case of PCS : [A] -> 1850, [B] -> 1910

No Item GSM DCS & PCS

30M ~ 1GHz -36dBm

30M~1GHz -36dBm

MS allocated 1G~[A]MHz -30dBm

Channel

1G ~ 4GHz -30dBm

[A]M~[B]MHz -36dBm

Radiated [B]M~4GHz -30dBm

2Spurious 30M ~ 880MHz -57dBm 30M~880MHz -57dBm

Emission 880M ~ 915MHz -59dBm 880M~915MHz -59dBm

Idle Mode

915M~1GHz -57dBm 915M~1GHz -57dBm

1G~[A]MHz -47dBm 1G~[A]MHz -47dBm

[A]M~[B]MHz -53dBm [A]M~[B]MHz -53dBm

[B]M~4GHz -47dBm [B]M~4GHz -47dBm

3 Frequency Error ±0.1ppm ±0.1ppm

4 Phase Error

±5(RMS) ±5(RMS)

±20(PEAK) ±20(PEAK)

3dB below reference sensitivity 3dB below reference sensitivity

Frequency Error RA250 : ±200Hz RA250: ±250Hz

5 Under Multipath and HT100 : ±100Hz HT100: ±250Hz

Interference Condition TU50 : ±100Hz TU50: ±150Hz

TU3 : ±150Hz TU1.5: ±200Hz

0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB

200kHz -30dB 200kHz -30dB

250kHz -33dB 250kHz -33dB

Due to 400kHz -60dB 400kHz -60dB

Output RF

modulation 600 ~ 1800kHz -60dB 600 ~ 1800kHz -60dB

6 1800 ~ 3000kHz -63dB 1800 ~ 6000kHz -65dB

Spectrum

3000 ~ 6000kHz -65dB ≥6000kHz -73dB

≥6000kHz -71dB

Due to

400kHz -19dB 400kHz -22dB

Switching

600kHz -21dB 600kHz -24dB

transient

1200kHz -21dB 1200kHz -24dB

1800kHz -24dB 1800kHz -27dB

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LGE Internal Use Only

Only for training and service purposes

2. PERFORMANCE

No Item GSM DCS & PCS

Frequency offset 800kHz

7 Intermodulation attenuation –

Intermodulation product should

be Less than 55dB below the

level of Wanted signal

Power control

Power Tolerance

Power control

Power Tolerance

Level (dBm) (dB) Level (dBm) (dB)

533±3 030±3

631±3 128±3

729±3 226±3

827±3 324±3

925±3 422±3

10 23 ±3 5 20 ±3

8 Transmitter Output Power 11 21 ±3 6 18 ±3

12 19 ±3 7 16 ±3

13 17 ±3 8 14 ±3

14 15 ±3 9 12 ±4

15 13 ±3 10 10 ±4

16 11 ±5 11 8 ±4

17 9 ±5 12 6 ±4

18 7 ±5 13 4 ±4

19 5 ±5 14 2 ±5

15 0 ±5

9 Burst timing Mask IN Mask IN

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LGE Internal Use Only

2. PERFORMANCE

2) Transmitter - WCDMA Mode

No Item Specification

1 Maximum Output Power Class 3 : +24dBm(+1/-3dB)

Class 4 : +21dBm(±2dB)

2 Frequency Error ±0.1ppm

3 Open Loop Power control in uplink ±9dB@normal, ±12dB@extreme

Adjust output(TPC command)

cmd 1dB 2dB 3dB

+1 +0.5/1.5 +1/3 +1.5/4.5

4 Inner Loop Power control in uplink 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5

-1 -0.5/-1.5 -1/-3 -1.5/-4.5

Group (10 equel command group)

+1 +8/+12 +16/+24

5 Minimum Output Power -50dBm(3.84MHz)

Qin/Qout : PCCH quality levels

6 Out-of-synchronization handling of output power Toff@DPCCH/Ior : -22 -> -28dB

Ton@DPCCH/Ior : -24 -> -18dB

7 Transmit OFF Power -56dBm(3.84MHz)

8 Transmit ON/OFF Time Mask

±25us

PRACH,CPCH,uplinlk compressed mode

±25us

9 Change of TFC

Power varies according to the data rate

DTX : DPCH off

(minimize interference between UE)

10 Power setting in uplink compressed ±3dB(after 14slots transmission gap)

11 Occupied Bandwidth(OBW) 5MHz(99%)

-35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz,30k

12 Spectrum emission Mask

-35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz,1M

-39-10*(∆f-7.5)dBc@∆f=7.5~8.5MHz,1M

-49dBc@∆f=8.5~12.5MHz,1M

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LGE Internal Use Only

Only for training and service purposes

3)Receiver - GSM Mode

2. PERFORMANCE

No Item Specification

13 Adjacent Channel Leakage Ratio(ACLR)

33dB@5MHz, ACP>-50dBm

43dB@10MHz, ACP>-50dBm

-36dBm@f=9~150KHz, 1K BW

-36dBm@f=50KHz~30MHz, 10K BW

-36dBm@f=30MHz~1000MHz, 100K BW

14

Spurious Emissions -30dBm@f=1~12.5GHz, 1M BW

(*: additional requirement) (*)-41dBm@f=1893.5~1919.6MHz, 300K

(*)-67dBm@f=925~935MHz, 100K BW

(*)-79dBm@f=935~960MHz, 100K BW

(*)-71dBm@f=1805~1880MHz, 100K BW

15 Transmit Intermodulation

-31dBc@5MHz,Interferer -40dBc

-41dBc@10MHz, Interferer -40dBc

16 Error Vector Magnitude (EVM)

17.5%(>-20dBm)

(@12.2K, 1DPDCH+1DPCCH)

17 Transmit OFF Power

-15dB@SF=4.768Kbps, Multi-code

transmission

No Item GSM DCS & PCS

1

Sensitivity (TCH/FS Class II) -105dBm -105dBm

2

Co-Channel Rejection

C/Ic=7dB Storage -30 ~ +85

(TCH/FS Class II, RBER, TU high/FH)

3 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB

Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB

Wanted Signal :-98dBm Wanted Signal :-96dBm

4

Intermodulation Rejection 1st interferer:-44dBm 1st interferer:-44dBm

2nd interferer:-45dBm 2nd interferer:-44dBm

5

Blocking Response Wanted Signal :-101dBm Wanted Signal :-101dBm

(TCH/FS Class II, RBER)

Unwanted : Depend on Frequency Unwanted : Depend on Frequency

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LGE Internal Use Only

2. PERFORMANCE

4) Receiver - WCDMA Mode

No Item Specification

1 Reference Sensitivity Level -106.7 dBm(3.84 MHz)

-25dBm(3.84MHz)

2 Maximum Input Level -44dBm/3.84MHz(DPCH_Ec)

UE@+20dBm output power(Class3)

3 Adjacent Channel Selectivity (ACS)

33dB

UE@+20dBm output power(Class3)

-56dBm/3.84MHz@10MHz

4In-band Blocking UE@+20dBm output power(Class3)

-44dBm/3.84MHz@15MHz

UE@+20dBm output power(Class3)

-44dBm/3.84MHz@f=2050~2095 and

2185~2230MHz

UE@+20dBm output power(Class3)

-30dBm/3.84MHz@f=2025~2050 and

5 Out-band Blocking 2230~2255MHz

UE@+20dBm output power(Class3)

-15dBm/3.84MHz@f=1~2025 and

2255~12500MHz

UE@+20dBm output power(Class3)

6 Spurious Response

-44dBm CW

UE@+20dBm output power(Class3)

-46dBm CW@10MHz

7 Intermodulation Characteristic -46dBm/3.84MHz@20MHz

UE@+20dBm output power(Class3)

-57dBm@f=9KHz~1GHz, 100K BW

8 Spurious Emissions -47dBm@f=1~12.5GHz, 1M BW

-60dBm@f=1920MHz~1980MHz, 3.84M BW

-60dBm@f=2110MHz~2170MHz, 3.84M BW

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LGE Internal Use Only

Only for training and service purposes

2. PERFORMANCE

2.4 Current Consumption

(Stand by Test Condition : Bluetooth off, LCD backlight off) (Call Test Condition : Bluetooth off, LCD backlight dimming mode) (VT Test Condition : Speaker off, LCD backlight On)

2.5 RSSI BAR

Stand by Voice Call VT

WCDMA

Under 4.32 mA Under 335 mA Under 569mA

(DRX=1.28) (Tx=10dBm -Low power) (Tx=10dBm -Low power)

Under 4.32 mA Under 380 mA

GSM

(Paging=5period) (Tx=Max power)

Level Change WCDMA GSM

BAR 7 → 6 -86 ± 2 dBm -82 ± 2dBm

BAR 6 → 5 -90 ± 2 dBm -86 ± 2dBm

BAR 5 → 4 -94 ± 2 dBm -90 ± 2dBm

BAR 4 → 3 -98 ± 2 dBm -94 ± 2dBm

BAR 3 → 2 -102 ± 2 dBm -98 ± 2dBm

BAR 2 → 1 -106 ± 2 dBm -102 ± 2dBm

BAR 1 → 0 -110 ± 2 dBm -106 ± 2dBm

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LGE Internal Use Only

2.6 Battery BAR

2. PERFORMANCE

Indication Standby

Bar 7 3.96 ± 0.05V

Bar 7 → 6 3.95 ± 0.05V

Bar 6 → 5 3.86 ± 0.05V

Bar 5 → 4 3.78 ± 0.05V

Bar 4 → 3 3.74 ± 0.05V

Bar 3 → 2 3.69 ± 0.05V

Bar 2 → 1 3.63 ± 0.05V

Bar 1 → Empty 3.50 ± 0.05V

Low Voltage, 3.63,3.50 ± 0.05V (Stand-by) / 3.63, 3.50 ± 0.05V (Talk)

Warning message + tone Bar 2 → 1 / Bar 1 → Empty

Power Off 3.20 ± 0.05V

- 16 -

LGE Internal Use Only

Only for training and service purposes

2. PERFORMANCE

2.7 Sound Pressure Level

2.8 Charging

- Charging Method : CC & CV (Constant Current & Constant Voltage)

- Maximum Charging Voltage : 4.2V

- Maximum Charging Current : 650mA

- Nominal Battery Capacity : 950 mAh

- Charger Voltage : 4.8V

- Charging time : Max 3 h (Except time trickle charging)

- Full charge indication current (icon stop current) : 60mA

- Low battery POP UP : 3.48V

- Low battery alarm interval : Idle - 3 min, Dedicated - 1min

- Cut-off voltage : 3.22V

No Test Item Specification

1 Sending Loudness Rating (SLR) 8 ±3 dB

2 Receiving Loudness Rating (RLR)

Nor -4 ± 3 dB

Max -15 ± 3 dB 3 Side Tone Masking Rating (STMR) Min 17 dB 4 Echo Loss (EL) Min 40 dB 5 Sending Distortion (SD) Refer to Table 30.3 6 Receiving Distortion (RD) Refer to Table 30.4 7 Idle Noise-Sending (INS) Max -64 dBm0p

8 Idle Noise-Receiving (INR)

Nor Under -47 dBPA

Max Under -36 dBPA 9 Sending Loudness Rating (SLR) 8±3dB

10 Receiving Loudness Rating (RLR)

Nor -1 ±3 dB

Max -12 ±3 dB

11 Side Tone Masking Rating (STMR) Min 25 dB 12 Echo Loss (EL) Min 40 dB 13 Sending Distortion (SD) Refer to Table 30.3 14 Receiving Distortion (RD) Refer to Table 30.4 15 Idle Noise-Sending (INS) Max -55 dBm0p

16 Idle Noise-Receiving (INR)

Nor Under -45 dBPA

Max Under -40 dBPA

TDMA Noise

-. GSM : Power Level : 5

DCS/PCS : Power Level : 0

(Cell Power : -90 ~ -105 dBm)

17

-. Acoustic (Max Vol.)

MS/Headset SLR : 8 ±3dB

MS/Headset RLR : -15 ± 3dB/-12dB

(SLR/RLR : Mid-value setting)

MS

Headset

MS and

Headset

Max

Under -62 dBm

- 17 -

LGE Internal Use Only

3. TECHNICAL BRIEF

3.1 General Description

The KS10 supports UMTS-2100 DS-WCDMA, EGSM-900, DCS-1800, and PCS-1900. All receivers and the UMTS transmitter use the radio One1Zero-IF architecture to eliminate intermediate frequencies, directly converting signals between RF and baseband. The EGSM, DCS1800 and PCS1900 transmitters use a baseband-to-IF up-conversion followed by an offset phase-locked loop that translates the GMSK-modulated signal to RF.

1

QUALCOMM’s branded chipset that implements a Zero-IF radio architecture.

3. TECHNICAL BRIEF

KS10 high-level RF functional block diagram

- 18 -

LGE Internal Use Only

Only for training and service purposes

A generic, high-level functional block diagram of KS10 is shown in Figure 1-1. One antenna collects base station forward link signals and radiates handset reverse link signals. The antenna connects with receive and transmit paths through a switch module (plus a duplexer for UMTS-2100 operation).

UMTS band signals at the antenna are switched to the relevant UMTS duplexer. The UMTS receive band signals are amplified by the front-end LNAs of the RFR6250 IC before passing through a bandpass filter and being applied to the mixer inputs of the RFR6250 IC. On-chip circuits down-convert the received signal directly from RF to baseband using radioOne Zero-IF techniques. Generation and distribution of the UMTS LO, for the down-converter, is performed entirely on-chip (except for the loop filter). The RFR6250 IC outputs analog baseband signals for processing by the MSM device. This baseband interface is shared with the RTR6250 GSM receiver outputs, but is separate from the GPS baseband interface.

EGSM, DCS and PCS receive signals from the antenna switch module pass through their band-pass filters, then are applied to the RTR6250 IC. In a similar fashion to the UMTS paths, RTR6250 IC circuits down-convert the received signals directly from RF to baseband. The GSM LO for multiband down conversion is entirely generated within the RTR6250 IC (PLL and distribution functions) with exception of the off-chip loop filter. The RTR analog baseband outputs are routed to the MSM6275 IC for further processing (an interface shared with the RFR UMTS receive paths).

The UMTS transmit path begins with analog baseband signals from the MSM device that drive the RTR6250 IC. Integrated PLL and VCO circuits generate the Tx LO used in the quadrature upconverter that translates baseband signals directly to RF. The RTR6250 output driver stages deliver fairly highlevel signals that are filtered and applied to the power amplifiers (PA). The PA output is routed to the antenna through a duplexer and switch module.

The shared EGSM-900, DCS-1800, and PCS-1900 transmit path begins with the same baseband interface from the MSM6275 IC that is used for the UMTS band. A single EGSM/DCS/PCS quadrature upconverter translates the GMSK-modulated signal to a convenient intermediate frequency (IF) that forms one input to an offset phase-locked loop (OPLL). OPLL functions are split between the RTR6250 IC and off-chip loop filter and dual Tx VCO circuits, and translate the GMSK-modulated signal to the desired EGSM-900, DCS-1800 or PCS-1900 channel frequency. This signal is applied to a dual power amplifier (only one is active at a time). The enabled path continues with the PA, an automated power control (APC) circuit that samples the transmit power and adjusts its level, the switch module (which includes a band-appropriate lowpass filter), and the antenna.

KS10 power supply voltages are managed and regulated by the PM6250 Power Management IC. This versatile device integrates all wireless handset power management, general housekeeping, and user interface support functions into a single mixed signal IC. It monitors and controls the external power source and coordinates battery recharging while maintaining the handset supply voltages using low dropout, programmable regulators.

The device’s general housekeeping functions include an ADC and analog multiplexer circuit for monitoring on-chip voltage sources, charging status, and current flow, as well as userdefined off-chip variables such as temperature, RF output power, and battery ID. Various oscillator, clock, and counter circuits support IC and higher-level handset functions. Key parameters such as under-voltage lockout and crystal oscillator signal presence are monitored to protect against detrimental conditions.

3. TECHNICAL BRIEF

- 19 -

LGE Internal Use Only

3. TECHNICAL BRIEF

3.2 GSM Mode

3.2.1 GSM Receiver

The Dual-mode KS10’s receiver functions are split between the two RFICs as follows:

• UMTS-2100 operation uses the RFR6250 Receiver ICs to implement the receive signal path, accepting an RF input and delivering analog baseband outputs (I and Q).

• EGSM-900, DCS-1800, and PCS-1900 modes both use the RTR6250 IC only. Each mode has independent front-end circuits and down-converters, but they share common baseband circuits (with only one mode active at a time). All receiver control functions are beginning with SBI2-controlled parameters.

The EGSM, DCS, and PCS receiver inputs of RTR6250 are connected directly to the transceiver frontend circuits(filters and antenna switch module). EGSM, DCS, and PCS receiver inputs are similar to the RFR6250 UMTS Rx input in that they also use differential configurations to improve commonmode rejection and second-order non-linearity performance.

The balance between the complementary signals is critical and must be maintained from the RF filter outputs all the way into the IC pins Since EGSM, DCS, and PCS signals are time-division duplex (the handset can only receive or transmit at one time), switches are used to separate Rx and Tx signals in place of frequency duplexers - this is accomplished in the switch module.

The EGSM, DCS, and PCS receive signals are routed to the RTR6250 through band selection filters and matching networks that transform single-ended 50-Ω sources to differential impedances optimized for gain and noise figure. Similar to the RFR, the RTR input uses a differential configuration to improve second-order inter-modulation and common mode rejection performance. The RTR6250 input stages include MSM-controlled gain adjustments that maximize receiver dynamic range.

The amplifier outputs drive the RF ports of the quadrature RF-to-baseband downconverters. The downconverted baseband outputs are multiplexed and routed to lowpass filters (one I and one Q) having passband and stopband characteristics suitable for GMSK processing. These filter circuits include DC offset corrections. The filter outputs are buffered and passed on to the MSM6275 IC for further processing (an interface shared with the RFR6250 UMTS receiver outputs).

2

The RFIC operating modes and circuit parameters are MSM-controlled through the proprietary 3-line Serial Bus Interface (SBI). The Application Programming Interface (API) is used to implement SBI commands. The API is documented in AMSS Software - please see applicable AMSS Software documentation for details.

- 20 -

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

- 21 -

LGE Internal Use Only

3. TECHNICAL BRIEF

3.2.2 GSM Transmitter

The shared GSM Low-band (EGSM900) and High-band (DCS1800, PCS1900) transmit path begins with the baseband inputs from the MSM6275 IC. These differential analog input signals are buffered, lowpass filtered, corrected for DC offsets then applied to the GSM quadrature upconverter. The upconverter LO signals are generated from the transceiver VCO signal by the LO distribution and generation circuits within RTR6250. This upconverter translates the GMSK-modulated signal to a convenient intermediate frequency (IF) that forms one input to a frequency/phase detector circuit. This IF signal is the reference input to an offset phase-locked loop (OPLL) circuit as shown in Figure 1.2.2-1.

The feedback path of this OPLL circuit includes a downconversion from the RF output frequency range to the IF range. The two inputs to this downconversion mixer are formed as follows:

1. The dual Tx VCO output (operating in the desired RF output frequency range) is buffered within the

RTR6250 IC then applied to the mixer RF port.

2. The LO Generation and Distribution circuits that deliver the transmit path.s LO for the baseband-to-IF

upconversion also provides the offset LO signal that is applied to the feedback path.s mixer LO port.

Figure 1.2.2-1 Offset phase-locked loop interfaces

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LGE Internal Use Only

Only for training and service purposes

The mixer IF port output is the offset feedback signal - the variable input to the frequency/phase detector circuit. The detector compares its variable input to its reference input and generates an error signal that is lowpass filtered by the loop filter and applied to the dual Tx VCO tuning port to force the VCO output in the direction that minimizes errors. As mentioned earlier, the VCO output is connected to the feedback path thereby creating a closed-loop control system that will force frequency and phase errors between the variable and reference inputs to zero.

The waveform at the dual Tx VCO output is the GMSK-modulated signal centered at the desired GSM channel frequency. A phase-locked loop circuit is used to translate the GMSKmodulated signal from IF to RF primarily for two reasons:

1. Phase-locked loops provide a lowpass filter function from the reference input to the VCO output. These results in a bandpass function centered at the desired channel frequency that provides steep, well-controlled rejection of the out-of-band spectrum.

2. The resulting output bandpass function is virtually unchanged as the transmitter is tuned over channels spanning the GSM operating band.

The PA is a key component in any transmitter chain and must complement the rest of the transmitter precisely. For GSM band operation, the closed-loop transmit power control functions add even more requirements relative to the UMTS PA. In addition to gain control and switching requirements, the usual RF parameters such as gain, output power level, several output spectrum requirements, and power supply current are critical. The gain must be sufficient and variable to deliver the desired transmitter output power given the VCO output level, the subsequent passive devices’ losses, and the control set point. The maximum and minimum transmitter output power levels depend upon the operating band class and mobile station class per the applicable standard. Transmitter timing requirements and in-band and out-of-band emissions, all dominated by the PA, are also specified by the applicable standard.

The active dual Tx VCO output is applied to the dual power amplifier to continue the transmit path, and feedback to the RTR6250 IC to complete the frequency control loop. The PA operating band (EGSM or DCS/PCS) is selected by the MSM device GPIO control. (GSM_PA_BAND).

3. TECHNICAL BRIEF

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3. TECHNICAL BRIEF

3.3 WCDMA Mode

3.3.1 Receiver

The UMTS duplexer receiver output is routed to LNA circuits within the RFR6250 IC. The LNA gain is dynamically controlled by the MSM6275 IC to cover full receiver dynamic range and to save current consumption. The UMTS LNA output is routed to the down conversion mixer inputs, in the RFR6250 IC, through a band selection filter that transforms a single-ended 50-Ω source to differential 100-Ω load impedance that is matched to the RFR6250 IC. The RFR input uses a differential configuration to improve secondorder inter-modulation and common mode rejection performance. The RFR6250 IC input stages include MSM-controlled gain adjustments that further extend receiver dynamic range.

The amplifier output drives the RF port of the quadrature RF-to-baseband down-converter. The downconverted baseband outputs are routed to low-pass filters (one I and one Q) having pass-band and stop-band characteristics suitable for DS-WCDMA processing. The filter outputs are buffered and passed on to the MSM6275 IC for further processing. This baseband interface is shared with the RTR6250 GSM receiver outputs.

The RFR6250 IC includes LO generation and distribution circuitry to reduce off-chip component requirements. The GPS RX LO source is created using the PLL control elements of the RTR6250 PLL2, via a discrete loop filter components, in tandem with the VCO in the RFR6250. Using only this PLL signal, the RFR6250 LO generation and distribution circuits create the necessary LO signals for the UMTS quadrature down-converter. By definition, the ZIF down-converter requires FLOequal to FRF, and the RTR6250/RFR6250 design achieves this without allowing F

VCO

to equal FRF.

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Only for training and service purposes

3. TECHNICAL BRIEF

Figure 1.3.1-1 RFR6250 IC functional block diagram

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LGE Internal Use Only

3.3.2 Transmitter

The UMTS transmit path begins with analog baseband signals from the MSM device that drive the RTR6250 IC. The RTR6250 IC provides all the UMTS transmitter active signalpath circuits except the power amplifiers. Analog (I and Q) differential signals from the MSM device are buffered, filtered, and applied to Baseband-to-RF quadrature upconverters. Gain control is implemented on-chip. The RF outputs include an integrated matching inductor, reducing the off-chip matching network to a single series capacitor.

The RTR6250 UMTS output is routed to its power amplifier through a bandpass filter, and delivers fairly high-level signals that are filtered and applied to the PA. The PA device used in KU950 is “Load Insensitive PA”- no need to use isolator - and routed to the duplexer Tx port directly. Transmit power is delivered from the duplexer to the antenna through the switch module.

The RTR6250 IC integrates LO generation and distribution circuits on-chip, substantially reducing offchip requirements. Various modes and programmable features result in a highly flexible transceiver LO output that supports not only UMTS transmissions, but all EGSM900 and DCS1800/PCS1900 Rx and Tx modes as well.

The UMTS Tx LO (PLL1) is generated almost entirely on-chip, requiring only the loop filter off-chip (two capacitors and two resistors); all UMTS Tx VCO and PLL circuits are on-chip. An internal RTR6250 switch routes the internal VCO signal to the LO generation and distribution circuits to create the necessary UMTS Tx LO signals.

3. TECHNICAL BRIEF

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3.4 LO Phase-locked Loop

Most LO functions are fully integrated on-chip, do not require user adjustment, and need not be considered by handset designers. QUALCOMM has established and implemented frequency plans and LO generation schemes that support the radioOne 6250-IIseries chipset while requiring minimal off-chip design effort. Only one area requires handset designer attention: the loop filters of each phase-locked loop (PLL).

3.4.1 UMTS Rx PLL (PLL2)

UMTS Rx LO functional blocks are distributed between the RFR6250 IC, RTR6250 IC, and external UMTS_RX_CH_VCO and loop filter components (Figure 1.4.1-1). The external UMTS_RX_CH_VCO must be enabled for UMTS Rx operation and disabled otherwise; a dedicated MSM6275 IC signal (UHF_VCO_EN ) enables the VCO.

3. TECHNICAL BRIEF

Figure 1.4.1-1 UMTS Rx PLL functional block diagram

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3. TECHNICAL BRIEF

The RFR6250 IC accommodates single-ended or differential LO inputs; if single-ended, either pin can be active. AC-couple the inactive pin to ground using an appropriately valued capacitor (12 pF is used in KS10). The 27 pF capacitor should be used to AC-couple the active pin to the VCO signal. Using only the selected VCO signal, the RFR6250 IC LO generation and distribution circuits create the necessary LO signals for the active quadrature downconverter.

A sample of the downconverter LO is buffered and routed from RFR6250 IC pin 19 to RTR6250 IC pin 32 (RX_VCO_IN). This signal requires a terminating resistor near the RTR6250 IC input pin and an AC coupling capacitor that assures the internal RTR6250 IC biasing is not disrupted in the example. Good microstrip or stripline controlled-impedance techniques must be used.

Most UMTS Rx PLL circuits are included within the RTR6250 IC: reference divider, phase detector, charge pump, feedback divider, and digital logic that generate LOCK status. The buffered 19.2 MHz TCXO signal provides the synthesizer input (REF), the frequency reference to which the PLL is phase and frequency locked. The reference is divided by the RCounter to create a fixed frequency input to the phase detector, FR. The other phase detector input (FV) varies as the loop acquires lock, and is generated by dividing the RX_VCO_IN frequency using the feedback path.s N-Counter. The closed loop will force FV to equal FR when locked. If the loop is not locked the error between FV and FR will create an error signal at the output of the charge pump. This error signal is filtered by the loop filter and applied to the VCO, tuning the output frequency such that the error is decreased. Ultimately the loop forces the error to approach zero and the PLL is phase and frequency locked.

Many key PLL performance characteristics are largely determined by the loop filter design - stability, transitory response, settling time, and phase noise.

3.4.2 Transceiver PLL (PLL1)

All LO functional blocks for the other handset modes(UMTS Tx, EGSM Tx/Rx, DCS Tx/Rx, PCS Tx/Rx) are integrated into the RTR6250 IC except the loop filter components (Figure 1.4.2-1). On-chip circuits include reference divider, phase detector, charge pump, VCO, feedback divider, and digital logic status. The functional description given in Section 1.4.1 for the UMTS Rx PLL applies to the Transceiver PLL as well.

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LGE Internal Use Only

Only for training and service purposes

The off-chip loop filter allows optimization of key PLL performance characteristics (stability, transitory response, settling time, and phase noise) for different applications. Guidelines are provided in the next subsection for proper implementation of this critical circuit.

3. TECHNICAL BRIEF

Figure 1.4.2-1 Transceiver PLL functional block diagram

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3. TECHNICAL BRIEF

3.5 Off-chip RF Components

3.5.1 Front End Module(FL500)

Front End module integrates antenna switch module and GSM Rx filter. The antenna switch module allows multiple operating bands and modes to share the same antenna. In the KS10 design, a common antenna connects to one of six paths:

1) UMTS-2100 Rx/Tx, 2) EGSM Rx, 3) DCS-1800 Rx, 4) PCS-1900 Rx, 5)EGSM Tx, and 6) DCS1800, PCS-1900 Tx. UMTS operation requires simultaneous reception and transmission, so the UMTS Rx/Tx connection is routed to a duplexer that separates receive and transmit signals. GSM band of operation is time division duplexed, so only the receiver or transmitter is active at any time and a frequency duplexer is not required. The module includes lowpass filters for the GSM bands transmit paths to reduce out-of-band emissions, PA harmonics in particular.

The GSM mode RF filters are located before their LNAs, so their insertion losses are extremely critical (1.3 dB typical). Other important parameters are:

■ Out-of-band rejection or attenuation levels

❏ Far out-of-band signals - ranging from DC up to the first band of particular concern and from the

last band of particular concern to beyond three times the highest passband frequency.

❏ Frequencies of particular concern . bands known to include other wireless transmitters that may

deliver significant power levels to the receiver input.

❏ GSM band receivers operate while the handset transmitters are off so there are no Txband

leakage attenuation requirements.

■ Phase and amplitude balance - the UMTS discussion presented above applies for GSM bands as

well. See the data sheet for specific values. Of course, passband ripple and return loss are still important in all cases for the same reasons explained in the antenna switch module and duplexer sections.

3.5.2 UMTS duplexer (U506)

A UMTS duplexer splits a single operating band into receive and transmit paths. Important performance requirements include:

- Insertion loss . this component is also in the receive and transmit paths; In the KS10 typical losses:

UMTS Tx = 1.45 dB, UMTS Rx = 1.86 dB.

- Out-of-band rejection or attenuation . the duplexer provides input selectivity for the receiver, output

filtering for the transmitter, and isolation between the two. Rejection levels for both paths are specified over a number of frequency ranges. Two Tx-to-Rx isolation levels are critical to receiver performance:

- Rx-band isolation . the transmitter is specified for out-of-band noise falling into the Rx band. This

noise leaks from the transmit path into the receive path, and must be limited to avoid degrading receiver sensitivity. The required Rx-band isolation depends on the PA out of-band noise levels and Rx-band losses between the PA and LNA. Typical duplexer Rx band isolation value is 51 dB.

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Only for training and service purposes

- Tx-band isolation . the transmit channel power also leaks into the receiver. In this case, the leakage is outside the receiver passband but at a relatively high level. It combines with Rx band jammers to create cross-modulation products that fall in-band to desensitize the receiver. The required Tx-band isolation depends on the PA channel power and Tx-band losses between the PA and LNA. Typical duplexer Tx-band isolation value is 57 dB.

- Passband ripple . the loss of this fairly narrowband device is not flat across its passband. Passband ripple increases the receive or transmit insertion loss at specific frequencies, creating performance variations across the bands channels, and should be controlled.

- Return loss . minimize mismatch losses with typical return losses of 10 dB or more (VSWR <2:1).

- Power handling. high power levels in the transmit path must be accommodated without degraded performance. The specified level depends on the operating band class and mobile station class (per the applicable standard), as well as circuit losses and antenna EIRP. Several duplexer characteristics depend upon its source and load impedances. QUALCOMM strongly recommends an isolator be used between the UMTS PA and duplexer to assure proper performance.

3.5.3 UMTS Power Amplifier (U505)

The AWT6277 meets the increasing demands for higher output power in UMTS handsets. The PA module is optimized for VREF = +2.85 V, a requirement for compatibility with the Qualcomm® 6250 chipset. The device is manufactured on an advanced InGaP HBT MMIC technology offering state-ofthe-art reliability, temperature stability, and ruggedness. Selectable bias modes that optimize efficiency for different output power levels, and a shutdown mode with low leakage current, increase handset talk and standby time. The self-contained 4 mm x 4 mm x 1.1 mm surface mount package incorporates matching networks optimized for output power, efficiency, and linearity in a 50 Ω system.

3. TECHNICAL BRIEF

Figure 1.5.3-1 UMTS PA functional block diagram

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3. TECHNICAL BRIEF

3.5.4 Thermistor (R527)

This thermistor senses temperature variations around UMTS PA to adjust PA gain deviation for assure compliance with the applicable transmit power control standards. Negative temperature compensation thermistor is used in the KS10.

3.5.5. UMTS transmit power detector (U504)

This detector couples PA output power level to calibrate the transmitter characteristic over the channel variation and temperature. Its detector coupling range and converted voltage is based on diode sensitivity and transmitter power level. The KS10 uses National Semiconductor ADL5500 power detector IC. In Figure 1.5.5-1, C580 is set to 47ohm&Coupler resulting in an attenuation of 31.4dB. The output voltage is proportional to the logarithm of the input power. Figure1.5.5-2 shows the output voltage versus PA output power of the ADL5500 setup as depicted in Figure1.5.5-1

Figure 1.5.5-1 Block diagram of ADL5500 with resistive tap

Figure 1.5.5-2 Power detector response, Vout vs PA output power

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Only for training and service purposes

3.5.6 Dual band GSM power amplifier (U501)

The TQM7M5003 is a high-power, high-efficiency power amplifier module with integrated power control that provides over 50dB of control range. The devices is a self-contained 6mm°ø6mm module with 50Ω input and output terminals. The device is designed for use as the final RF amplifier in GSM850, EGSM900, DCS and PCS hand-held digital celluar equipment and other applications in the 824MHz to 849MHz, 880MHz to 915MHz, 1710MHz to 1785MHz and 1850MHz to 1910MHz bands. The VBATT pin connects to an internal current-sense resistor and interfaces to an integrated power amplifier control function, which is insensitive to variations in temperature, power supply, process, and input power. The ENABLE input allows initial turn-on of PAM circuitry to minimize battery drain.

3.5.7 GSM transmit VCO (U502)

The dual Tx VCO is a key component within the GSM OPLL. This VCO performance directly impacts PLL and transmitter performance. VCO specifications refer to muRata MQW5V0C869M datasheet.

The dual Tx VCO outputs, one for Low-band GSM and one for high band, drive a resistive network that splits the active signal into two signals: 1) the input to the active PA . this is the low loss path, and 2) the OPLL feedback signal . this is the high loss path. See Figure 8-1 for recommended topology and resistor values.

The losses from the VCO outputs to the PA inputs must be factored into the output chain.s power budget. Each path includes a π-pad that introduces approximately a 3-dB loss. The low band GSM π-pad is formed by R516 plus R522, R521, and R524; the high band GSM π-pad is formed by R518 plus R523, R520, and R524. One leg of each π-pad is used to couple the VCO output to form the feedback path as described below.

For a given VCO output drive level, the loss to the RTR6250 input must assure the specified input level is achieved (-18 to -12 dBm). Large resistors included in the π-pads are used to lightly couple off the VCO outputs to create the feedback signal. Since the RTR6250 TX_VCO_FB pin presents fairly high impedance. A series capacitor (82 pF) AC couples the feedback signal into the RTR6250 IC.

3. TECHNICAL BRIEF

Figure 1.5.6-1 GSM PA functional block diagram

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3. TECHNICAL BRIEF

3.5.8 UMTS Rx RF filter (FL501)

An RF filter is located between the UMTS LNA and mixer. Insertion loss is important, but not as critical as losses before the LNA. The most important parameters of this component include:

■ Out-of-band rejection or attenuation levels, usually specified to meet these conditions:

❏ Far out-of-band signals - ranging from DC up to the first band of particular concern and from the

last band of particular concern to beyond three times the highest passband frequency.

❏ Tx-band leakage - the transmitter channel power, although attenuated by the duplexer, still

presents a cross-modulation threat in combination with Rx-band jammers. The RF filter must provide rejection of this Tx-band leakage.

❏ Other frequencies of particular concern . bands known to include other wireless transmitters that

may deliver significant power levels to the receiver input.

■ Phase and amplitude balance - the ZIF architecture requires well-balanced differential inputs to the RFR6250 IC. This is accomplished by the RF filter which takes a single-ended output from the RFL6250 IC and provides differential outputs having nominal 180 phase separation. Phase and/or amplitude imbalance causes degraded common-mode rejection and second-order nonlinearity, so their requirements are specified jointly.

❏ ±3 degrees and ± 1 dB ❏ -12 to + 3 degrees and ± 0.7 dB

Of course, passband ripple and return loss are still important in all cases for the same reasons explained in the antenna switch module and duplexer sections.

3.5.9 VCTCXO (X500)

The Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO) provides the reference frequency for all RFIC synthesizers as well as clock generation functions within the MSM6275 IC. The 6275-series chipset requires a 19.2 MHz nominal VCTCXO frequency. The

oscillator frequency is controlled by the MSM6275’s TRK_LO_ADJ pulse density modulated signal in the same manner as the transmit gain control.

The filtered PDM signal results in an analog control signal into the VCTCXO tuning port whose voltage is directly proportional to the density of the digital bit stream. The MSM device varies the pulse density to change the analog control voltage that sets the oscillator frequency - all within a feedback control loop that minimizes handset frequency drift relative to the network.

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3.6 Digital Baseband (Stn8810 / MSM6275)

3.6.1 General features of Stn8810 device

• Support for Peripheral Device & multimedia function

• Support for high-speed downlink packet access (HSDPA) - 1.8 Mbps

• Minimal support for high-level operating system such as Symbian™, Linux and WinCE® operating systems (OSs).

• 1-Gbit NAND Flash memory, 512-Mbit DDR mobile RAM Stacked in Package

• Two DSP implementation for multimedia function

- Smart video accelerator : Programmable DSP (MMDSP+) for intermediate level processing, clocked at 66 MHz,

- Smart audio accelerator : High-performance block, flexible sophisticated audio accelerator based on the MMDSP+ programmable audio DSP, clocked at 133 MHz,

• ARM926EJ 32-bit RISC CPU at 350MHz

32-Kbyte instruction cache, 16-Kbyte data cache

• MultiMedia Card/SD Card/SDIO host controller

• 96 general-purpose I/Os (muxed with peripheral I/Os)

• Camera interfaces

- Supports high-resolution camera modules up to 4 Mpixels

- Serial camera interface up to 416 Mbit/s (MIPI legacy CSI)

- Parallel camera CCIR-656 interface up to 66 MHz (MIPI legacy CPI)

• Color LCD controller for STN or TFT panels or display interface for display module

- 24-bpp true color

- MIPI legacy DBI and DPI

• Host port interface (HPI)

- 16-bit parallel data bus,

- Multiplexed and non-multiplexed address/data bus,

- Indirect host access,

- Direct host access to a segment of STn8810 memory in multiplexed mode.

- Interface to modem for data communication

• I/O peripherals

- 3 autobaud UARTs (one with modem control signals) up to 3.692 Mbit/s

- 1 synchronous serial port (SSP) up to 24 Mbit/s

- 3 multichannel serial ports (MSP) up to 48 Mbit/s

- 2 I©˜C multi-master/slave interfaces

- One 8-channel, full-duplex high-speed serial interface, 108 Mbit/s

- Host port interface

- JTAG

3. TECHNICAL BRIEF

3. BB Technical Description

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3. TECHNICAL BRIEF

3.6.2 General features of MSM6275 device

• Support for multimode operation - WCDMA(UMTS), GSM/GPRS, EDGE

• Support for high-speed downlink packet access (HSDPA) - 1.8 Mbps

• Support for WCDMA (UMTS) uplink data rate up to 384 kbps

• High-performance ARM926EJ-S running at up to 225 MHz

• ARM Jazelle Java hardware acceleration for faster Java-based games and other applets

• QDSP4000 high-performance DSP cores

• Integrated gpsOne position location technology functionality

• Integrated Bluetooth 1.2 baseband processor for wireless connectivity to peripherals

• High-speed, serial mobile display digital interface (MDDI) Type I, which optimizes the interconnection cost between the MSM device and LCD panel

• Direct interface to digital camera module with video front end (VFE) image processing

• Vocoder support (AMR, FR, EFR, HR)

• Advanced 14x14 mm, 0.5 mm pitch, 409-pin lead-free CSP packaging technology

• WCDMA Access

- Maximum of eight simultaneous transport channels

- Four coded composite transport channels (CCTrCH)

- PS data rates supporting 384kbps DL / 64kbps UL

• GSM/GPRS Access

- GSM/GPRS network signaling (from Layer 1 to 3)

- GSM AMR,EFR,FR

• Operation and Services

- USIM Interfaces

- General Purpose I/O (GPIO) Interface

- Dual Memory Buses (EBI1-SDRAM & EBI2-NAND Flash)

- JTAG

- RTC

• Data Communication

- UARTs (ACB, EDB (RS232))

- Slave USB

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3. TECHNICAL BRIEF

3.7. Hardware Architecture

LGE Internal Use Only

Only for training and service purposes

MSM6275

PM6650

SDRAM + NAND

MAIN LCD

GSM

Quadband

PA

BLUETOOTH

18pin MMI Connector

1.3M CAMERA

Receiver

/ SPEAKER

MIC

RFR6250

RTR6250

Micro SD

USIM

GSMQua

d

TX VCO

UMTS

(2100)

PA

WCDMA RX

WCDMA TX

GSM

900/1800/1900

RX FILTER

GSM RX

GSM TX

UMTS

TX

FILTER

D U P L E X E R

UMTS

RX

FILTER

VGA CAMERA

FEM

STn8810

STw4810

Audio Codec.

(WM8753)

HPI I/F

Figure. Simplified Block Diagram

LGE Internal Use Only

3. TECHNICAL BRIEF

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Figure. STn8810 and supported peripherals

3.7.1. STn8810 and supported peripherals

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

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3.7.2. MSM6275 and supported peripherals

Figure. MSM6275 and supported peripherals

LGE Internal Use Only

3. TECHNICAL BRIEF

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3.8. Subsystem of STn8810

3.8.1. ARM926EJ processor

The STn8810 CPU is an ARM926EJ reduced instruction set computer (RISC) processor. This 32-bit processor core supports 32-bit ARM® and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density. The cached ARM CPU features a memory management unit (MMU) and is clocked at 264 MHz. It has a 32-Kbyte instruction cache and a 16-Kbyte data cache, and supports the Jazelle™ extensions for Java acceleration. It also includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock.

3.8.2. Smart video accelerator (SVA)

Using leading-edge technology, this block is a low-power, high-performance video accelerator that supports the following features:

• MPEG-4 simple profile level 3 video encoder and decoder; real time up to VGA 30 fps (encode only or decode only)

• H.263 profile 3 level 10 video codec; real time subQCIF or QCIF 15 fps for videoconferencing

• H.263 profile 3 level 30 video encoder or decoder; real-time up to CIF 30 fps

• JPEG baseline accelerated encoder or decoder, up to 4080 x 4080 pixels

• Programmable DSP (MMDSP+) for intermediate level processing, clocked at 66 MHz

• Picture pre-/post-processing

• Low-power implementation

3.8.3. Smart audio accelerator (SAA)

This high-performance block is a flexible sophisticated audio accelerator based on the MMDSP+ programmable audio DSP, clocked at 133 MHz, and features:

• 24-bit data path

• Ultra-low power implementation

The audio accelerator features:

• MP3, AAC, AAC+ (SBR) decoding, Midi synthesis, and more

• Speech codecs: AMR (WB, NB), and more

• Audio sample rates of 32 kHz, 44.1 kHz and 48 kHz

• Noise reduction and echo cancelling

• Stereo enhancements and surround effects

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

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3.8.4. Advanced power management unit (PMU)

The dynamic PMU optimizes power consumption of the STn8810. It delivers all the platform clocks, and handles reset management. It also manages GPIO levels during sleep mode and emergency self-refresh of SDRAM. The PMU controls the external voltage regulator, in order to change its settings in different modes. In deep-sleep mode, only GPIOs, the real-time clock (RTC), system and reset controller (SRC), PMU and secured RAM remain in operation. The PMU also controls the embedded 1.2 V voltage switch that switches off the logic supply after the platform has entered sleep mode. The family of power manager ICs, STw481x companion chips, seamlessly interface with the Nomadik STn8810 and optimize global system power consumption leveraging on the PMU.

3.8.5. Host port interface (HPI)

The host port interface features:

• 16-bit parallel data bus

• Multiplexed and non-multiplexed address/data bus

• Indirect host access

• Direct host access to a segment of STn8810 memory in multiplexed mode

3.8.6. General purpose inputs/outputs (GPIOs)

The STn8810 provides 96 programmable inputs or outputs that have switchable pull-up and pull-down resistors and are controllable in two modes:

• Software mode through an APB bus interface

• Hardware mode through a hardware control interface

The GPIO interface provides the following individually programmable functions:

• Any number of pins may be configured as interrupt sources

• Debouncing logic can be enabled for each GPIO to filter out glitches on I/Os

• Any GPIO may be used to wake up the device from sleep mode independent of interrupt programming, and the input level that triggers wake-up is definable for each enabled GPIO

3.8.7. Universal asynchronous receivers-transmitters (UARTs)

The STn8810 provides three autobaud UARTs, one of which offers all modem control/status signals. They are enhanced versions of the industry-standard 16C550 UART with a high data rate up to 3.692 Mbit/s.

LGE Internal Use Only

3. TECHNICAL BRIEF

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3.8.8. USB interface

The STn8810 USB interface is USB 2.0 compliant, with On-The-Go standard extension (rev 1.0) compliance. The USB-OTG features:

• Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) signaling bit rate

• Supports session request protocol (SRP) and host negotiation protocol (HNP)

• 8 bidirectional endpoints plus control endpoint 0

• Digital interface to external PHY

• Fully compatible with STw4810 power manager companion chip

3.8.9. I2C bus interface

The STn8810 provides two I©˜C bus interfaces that support the following features:

• Slave transmitter/receiver and master transmitter/receiver modes

• Multi-master capability

• 10-bit addressing

• Standard (100 kHz) and fast (400 kHz) speeds

• Compliance with I2C and DDC standards In addition to receiving and transmitting data, the interface converts data from serial to parallel format and vice-versa using an interrupt or polled handshake. The interrupts are enabled and disabled in software.

3.8.10. MultiMediaCard/secure data card interface (MMC/SD/SDIO)

This interface can directly control one SD card (without encryption/decryption logic) or SDIO card, or one MultiMediaCard. It also supports several of each card type using the GPIOs for card selection.

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

- 42 -

3.9. Hardware Peripheral system of Stn8810

3.9.1. Keypad

KS10 has 28 buttons, 12 function keys in Sub PCB (Folder), 12 numeric keys in main and 4 side keys. KS10 use key coder IC because Stn8810 has not enough GPIO. Key coder IC use interrupt and I2C interface for communication with STn8810. Figure shows the Keypad circuit. °ÆEND’ Key is connected to PM_ON_SW_N to PM6650

Table. Key Matrix Mapping Table

Figure. Schematic of key coder IC

COL0 COL1 COL2 COL3 COL4 COL5 COL6

ROW0 1 2 3 Vol. UP Left Soft Key UP Right Soft Key

ROW1 4 5 6 Vol. DOWN MENU OK CANCEL

ROW2 7 8 9 SHOT SEND DOWN END

ROW3 * 0 # LEFT EDIT RIGHT

Main Side Key Folder

KEY_COL(4:7)

KEY_ROW(0:3)

KEY_COL(5) KEY_COL(6) KEY_COL(7)

AP_VDD_IO_2.7V

R414

R415

3.3K

KEY_ROW(2)

KEY_ROW(3)

KEY_ROW(0)

KEY_ROW(1)

E6

A6 B5 A5 B4 A4 A3 B3 A2

Wake_INP6 Wake_INP7 K_Out4 K_Out5 K_Out6 K_Out7 Gen_IO_2 Gen_IO_3

A7

Gen_In1

A1

B2

Wake_INP5

Gen_In0

D6

B6

D7

C7

Wake_INP3

Wake_INP4

Wake_INP0

Wake_INP1Gen_IO_0

LM8333GGR8_NOPB

PWM

CLK_In

Gen_IO_1

F1

B1

D2

D1

68KR419

F7

E7

SCL_AB

Wake_INP2

U404

VCC1E1VCC2

E2

SDA_AB

C3

C2

GND1

C4

C418

0.1u

C1

C6

NC5

NC6

GND2C5GND3

D3

B7

NC7

GND4

D4

C419

0.1u

F5

NC8

GND5

G6

F6

NC1

NC2

GND6D5GND7

E3

E4

G7

NC3

_RESET

WD_Out

GND8

E5

NC4

K_Out3 K_Out2 K_Out1 K_Out0

Int_Rx

Int_Tx

GND9

I2CSCL1

I2CSDA1

KEY_COL(3:0)

TP407

KEY_COL(3) KEY_COL(2) KEY_COL(1)KEY_COL(4) KEY_COL(0)

TP406

KEYCODER_RSTN

KEYCODER_INT

G5 G4 F4 G3 F3 G2 G1 F2

AP_VDD_IO_2.7V

FOLDER_DETECT

LGE Internal Use Only

3. TECHNICAL BRIEF

- 43 -

Figure. Schematic of keypad

SW400

SW411

SW407

VA403 EVLC14S02050

VA405 EVLC14S02050

EVLC14S02050VA404

SW408

VA401 EVLC14S02050

EVLC14S02050VA406

SW401

EVLC14S02050VA402

SW409 SW410

SW402

VA407 EVLC14S02050

SW406

AP_VDD_IO_2.7V

246

8

135

7

SW404

RA400 100K

SW405SW403

KEY_COL(1) KEY_COL(2)

KEY_ROW(0)

KEY_ROW(1)

KEY_ROW(2)

KEY_ROW(3)

KEY_COL(0)

VA102 RSB6.8CST2R

RSB6.8CST2RVA101

SW106 SW108

VA105

VA104

RSB6.8CST2R

SW107

VA103

VA107

RSB6.8CST2R

VA106

RSB6.8CST2R

SW104 SW105SW103

SW102SW100

SW111SW109

SW101

SW110

KEY_ROW(0)

KEY_ROW(1)

KEY_COL(6)

KEY_COL(4) KEY_COL(5)

KEY_ROW(3)

KEY_ROW(2)

D402 RSB6.8CST2R

RSB6.8CST2RD401

D400

RSB6.8CST2R

1

2 3 4

CN400

KEY_ROW(0)

KEY_ROW(1)

KEY_COL(3)

RSB6.8CST2RD405

1 2 3 4

CN401

D404 RSB6.8CST2R

RSB6.8CST2RD403

KEY_COL(3)

KEY_ROW(2)

KEY_ON_SW_N

Side Key (Vol. UP/Down)

Side Key (Power/Shot)

Main PCB

Sub PCB

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

- 44 -

3.9.2. Folder on/off operation

There is a magnet to detect the folder status, opened or closed. If a magnet is close to the hall-effect switch, the voltage at pin1 of U402 goes to 0V. Otherwise, 2.7V. This folder signal is delivered to GPIO0 of the Key coder IC .

AP_VDD_IO_2.7V

0.1u

C414

U402 A3212EEH-T

3

GND1

GND2

4

2

NC1

5

NC2

1

OUTPUT

7

PGND

6

VDD

EUSY0200301

R413

100K

C413 1u

ZD1

RSB6.8CST2R

FOLDER_DETECT

Figure. Schematic of folder on/off detection circuit

LGE Internal Use Only

3. TECHNICAL BRIEF

- 45 -

3.9.3. Keypad backlight

There are 8 White LEDs on Top side of Main PCB and 9 White LEDs on Top side of sub PCB in board backlight circuit and, which are driven by KEYBD_BACKLIGHT line form PM6650. Key Pad backlight controlled by PM6650.

Figure. Schematic of main PCB keypad backlight circuit

100ohmR411

SSC-TWH104-HLS

LD407

SSC-TWH104-HLS

LD406

SSC-TWH104-HLS

LD402

EVL14K02200

VA400

R409 100ohm

100ohmR412

AP_+VPWR

LD400

SSC-TWH104-HLS

100ohmR406

R400

0

R408 100ohm

SSC-TWH104-HLS

LD401

SSC-TWH104-HLS

LD403

R403 100ohm

SSC-TWH104-HLS

LD405

100ohmR405

R402 100ohm

LD404

SSC-TWH104-HLS

KPD_DRV_N

Figure. Schematic of key PCB keypad backlight circuit

100ohmR109

EVL14K02200

VA100

100ohmR111

100ohmR110

LD108

SSC-TWH104-HLSSSC-TWH104-HLS

LD107

LD104

SSC-TWH104-HLS

AP_+VPWR

SSC-TWH104-HLS

LD103

100ohm

100ohmR113

R112

100ohmR114

LD102

SSC-TWH104-HLS

LD100

SSC-TWH104-HLS

100ohmR107 100ohm R108R106 100ohm

SSC-TWH104-HLS

LD101

LD105

SSC-TWH104-HLS SSC-TWH104-HLS

LD106

KPD_DRV_N

LGE Internal Use Only

Only for training and service purposes

3.9.4. Micro SD

3. TECHNICAL BRIEF

- 46 -

PMIC

(ST Micro.)

SD Socket

CPU

(ST Micro.)

USBINTN

CPU

(ST Micro.)

NA

USBVM

USBRCV

USBSCL

USBSDA

MCCLK

MCFBCLK

MCCMDDIR

MCCMD

MCDAT0DIR

MCDAT0

MCDAT31DIR

MCDAT1 MCDAT3

MCDAT2DIR

MCDAT2

TP305

1.8V Signal 2.85V Signal

Clock Clock

Command Command

Level shifting

PMIC

(ST Micro.)

Data Data

SD_INT

USBVM

K7

USBRCV

H8

USBINTN

G9

USBSCL

H9

USBSDA

MCCLK

H5

MCFBCLK

G3

MCCMDDIR

H1

MCCMD

K2

MCDAT0DIR

K1

MCDATA0

H4

MCDATA31DIR

H3

MCDATA1

H2

MCDATA3

K9

MCDAT2DIR

J1

MCDATA2

C335

C336

NA

NC1

NC2

NC3

NC4C5NC5F8NC6G8NC7

B1

B7

B8

GND1B9GND2

D3

K10

VBAT_MMC

VMMC

LATCHCLK

CLKOUT

DATAOUT3 DATAOUT2 DATAOUT1 DATAOUT0

CMDOUT

GPO1 GPO2

DN

J4

K5

F3G2 G1

F1 E3 E2 E1 F2

J5

C334

K6

1u

VMMC_3.1V

SD Socket

C332

2.2u

VMMC_3.1V

SD_DAT(1) SD_DAT(0)

SD_CLK

SD_CMD SD_DAT(3) SD_DAT(2)

MCDAT1

MCDAT0DIR

MCDAT0

MCCMDDIR

MCCMD

MCCLK

MCFBCLK

MCDAT3

MCDAT2

D12

C12

E13

D14

C14

E14

C13

D13

E17

MCCLK

MCCMD

MCFBCLK

MCDAT2

MCDAT3

MCCMDDIR

MCDAT0

MCDAT1

MSPTXD0

MCDAT31DIR

D15

E15

MSPTXD0

MCDAT0DIR

MCDAT31DIR

REMOTE_PWR_ON_AP

SW_RESET

MSPTFS0

MCDAT2DIR

MSPRXD0

F24

E16

F17

C15

G24

MSPTFS0

MSPSCK0

MSPRXD0

MSPTFS2_SMPCE1N

MSPTXD2_SMPCE2N

SD_INT

H22

MSPTCK2_SMPIORN

SD_DAT(1) SD_DAT(0)

SD_CLK

SD_CMD SD_DAT(3) SD_DAT(2)

NA

D301

R312

5

6

1

2

51K

R314

R313

PLR0504F

34

S300

GCC110-8S-R-E1000

SWASWBGND

8 7 6 5 4 3 2 1

GND

C339 1u

SD_INT

C343 NA

51K

R310

R309

R311

5

6

PLR0504F

D300

1234

LGE Internal Use Only

3. TECHNICAL BRIEF

- 47 -

3.10. Subsystem of MSM6275

3.10.1. ARM Microprocessor Subsystem

The MSM6275 device uses an embedded ARM926EJ-S microprocessor. This microprocessor, through the system software, controls most of the functionality for the MSM device, including control of the external peripherals such as the keypad, LCD, RAM, ROM, and EEPROM devices. Through a generic serial bus interface (SBI) the ARM926EJ-S configures and controls the functionality of the RFL6202, RFR6202, RTR6250, RTR6200, and PM6650 devices.

3.10.2. UMTS/HSDPA Subsystem

The UMTS/HSDPA subsystem performs the digital release 99 June 2004 of the WCDMA FDD standard and release 5 specifications of HSDPA signal processing.

The UMTS Subsystem performs the digital UMTS signal processing. Its components include:

•

Searcher engine

•

Demodulating fingers

•

Combining block

•

Frame deinterleaver

•

Viterbi decoder

•

Up-link subsystem

•

Turbo decoder

On the down-link channel the UMTS subsystem searches, demodulates, and decodes incoming CPICH, CCPCH, SCH, and Traffic Channel information. It extracts packet data from the downlink traffic channel and prepares the packet data for processing. For the up-link, the WCDMA subsystem processes the packet data and modulates the up-link traffic channel (DCH).

3.10.3. GSM/GPRS Subsystem

The GSM/GPRS/EGPRS subsystem reuses the MSM6275 GSM core. It performs the digital GSM signal processing and PA gain controls for GPRS support. The PA output level is controlled by an analog signal generated on the MSM. In GSM mode, the power profile ramps up before The burst and ramps down after the burst. In GPRS mode, at the beginning of each burst (up to Four active transmit slots), PA must be smoothly ramped up to some desired output power level, Held at that level for the current slot, smoothly ramped down/up during the transition period and Held to the new level for the next slot until the last slot. Then it must be smoothly ramped down to near-zero level. The MSM6275 support differential GSM PA power control output.

LGE Internal Use Only

Only for training and service purposes

3.10.4. RF Interface

The RF interface communicates with the mobile station external RF circuits. Signals to these Circuits control signal gain in the Rx and Tx signal path, control DC offset errors, and maintain the system frequency reference.

3.10.5. Serial Bus Interface (SBI)

The MSM6275 device’s SBI is designed specifically to be a quick, low pin count control Protocol for QUALCOMM’s RFL6202, RFR6202, RTR6250, RTR6200, and PM6650 ASICs. Using the SBI, the RTR6250, RFR6200, RFL6200, and PM6650 devices can be configured for different operating modes and for minimum power consumption, extending battery life in standby mode. The SBI also controls DC baseband offset errors.

3.10.6. HKADC

The MSM6275 device has an on-chip 8-bit analog-to-digital converter (HKADC) which is Intended to digitize DC signals corresponding to analog parameters such as battery voltage, temperature, and RF power levels.

The MSM6275 device has seven analog input pins (HKAIN[5:0]) which are multiplexed to the input of the internal HKADC.

3.10.7. Stereo Wideband CODEC

The MSM6275 device integrates a wideband voice/audio codec into the MSM. The codec supports two differential microphone inputs, one differential earphone output, one single-ended earphone output, and a differential analog auxiliary interface. The codec integrates the microphone and earphone amplifiers into the MSM6275 device, reducing the external component count to just a few passive components. The microphone (Tx) audio path consists of a two-stage amplifier with the gain of the second stage set externally. The Rx/Tx paths are designed to meet the ITU-G.712 requirements for digital transmission systems.

3.10.8. Vocoder Subsystem

The MSM6275 QDSP4000 supports AMR, FR, EFR, and HR. In addition, the QDSP4000 has modules to support the following audio functions: DTMF tone generation, DTMF tone detection, Tx/Rx volume controls, Tx/Rx automatic gain control (AGC), Rx automatic volume control (AVC), ear seal echo canceller (ESEC), acoustic echo canceller (AEC), noise suppression (NS), and programmable, 13-tap, Type-I, FIR, Tx/Rx compensation filters. The MSM6275 device’s integrated ARM9TDMI processor downloads the firmware into the QDSP4000 and configures the QDSP4000 to support the desired functionality.

3. TECHNICAL BRIEF

- 48 -

LGE Internal Use Only

3. TECHNICAL BRIEF

- 49 -

3.10.9. General-Purpose Input/Output Interface

The MSM6275 device has general-purpose bidirectional input/output pins. Some of the GPIO pins have alternate functions supported on them. The alternate functions include USB interface, additional RAM, ROM, general-purpose chip selects, parallel LCD interface, and a UART interface. The function of these pins is documented in the various software releases.

3.10.10. UART

There are three UARTs in the MSM6275 ASIC:

•

UART1 for data

•

UART2 (can be used for USIM interface)

•

UART3 (can be used for PM SBI interface)

3.10.11. USB

The MSM6275 device integrates a universal serial bus(USB) controller that supports both unidirectional and bidirectional transceiver interfaces. The USB controller acts as a USB peripheral communicating with the USB host. It is also capable of a USB OTG interface to a USB OTG Transceiver.

LGE Internal Use Only

Only for training and service purposes

3.11. External memory interface

The MSM6275 have two external memory interfaces with arbitration for the multi-layer AHB system and memory controllers. The EBI1 bus is a high performance bus that supports a wide variety of memories. EBI2 bus is targeted to be the interface for slow peripheral devices(i,.e., LCD) as well as the NAND flash memory.

•

EBI1 Features

- 16 bit static and dynamic memory interface

- 32 bit dynamic memory interface

- 24 bits of address for static memory devices which can support up to 32MBytes on each chip select

- Synchronous burst memories supported (burst NOR, burst PSRAM)

- Synchronous DRAM memories supported

- Byte addressable memory supporting 8 bit, 16 bit and 32 bit accesses

- Pseudo SRAM (PSRAM) memory support

•

EBI2 Features

- Support for asynchronous FLASH and SRAM(16bit & 8bit).

- Interface support for byte addressable 16bit devices(UB_N & LB_N signals).

- 2Mbytes of memory per chip select.

- Support for 8 bit wide NAND flash.

- Support for parallel LCD interfaces, port mapped of memory mapped(16 & 8 bit)

•

512Mb NAND flash memory + 512Mb SDRAM (1die)

3. TECHNICAL BRIEF

- 50 -

Interface Spec

Device Part Name Maker Read Access Time Write Access Time

FLASH TY90009800COGG Toshiba 35 ns/Bytes 50 ns/Bytes

SDRAM TY90009800COGG Toshiba 107 ns/4Double Word 53 ns/4Double Word

Table. External memory interface for KS10

LGE Internal Use Only

3. TECHNICAL BRIEF

- 51 -

3.12. Hardware sub system of MSM6275

3.12.1. RF Interface

3.12.1.1. RTR6250 (WCDMA_Tx, GSM_Tx/Rx)

MSM6275 controls RF part(RTR6250) using these signals.

•

SBST,SBDT,SBCK : SBI I/F signals for control Sub-chipset

•

PA_ON : Power AMP on RF part

•

RX_I/Q,TX_I/Q : I/Q for Tx/Rx of RF

•

TX_AGC_ADJ : control the gain of the Tx signal prior to the power amplifier

3.12.1.2. RFR6250 (WCDMA_Rx)

•

SBST,SBDT,SBCK : SBI I/F signals for control Sub-chipset

•

RX_I/Q, : I/Q for Rx of RF

3.12.1.3. The others

•

GSM_PA_BAND : DCS/GSM Band Selection of Power Amp

•

TRK_LO_ADJ : TCXO(19.2M) Control

•

PA_ON : WCDMA TX Power Amp Enable

•

ANT_SEL[0-2] : Ant Switch Module Mode Selection (WCDMA,GSM Tx/Rx,DCS Tx/Rx)

•

GSM_PA_RAMP : Power Amp Gain Control of APC_IC

•

GSM_PA_EN : Power Amp Gain Control Enable of APC_IC

•

GSM_TX_VCO_0_EN_N : GSM Band Tx VCO Enable of Dual VCO

•

GSM_TX_VCO_1_EN_N : DCS Band Tx VCO Enable of Dual VCO

- 52 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

(WCMDA 2100PAM Enable)

(WCMDA PAM MODE)

(Check CAM_DATA PINOUT !!!!)

MSM pin AD26

Place near

10%

Near to MSM

XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77

Y6

L25

UART3_RFR_N_GPIO87

TDI

TDO

A17

TMS

F15

TRK_LO_ADJ

L13

H15

TRST_N

H13

TX_AGC_ADJ

TX_ON_GRFC10

H12

H6

UART2_DP_RX_DATA_GPIO89

F18

SYNTH0_GP_PDM0_GPIO92

H23

SYNTH1_GPIO41

TCK

D16

TCXO_EN_GPIO94

F19

D15

SBDT

H26

SBST

SBST1_GPIO93

H18

P25

PA_POWER_CTL

AA25

Q_IM_CH0

Q_IM_CH1

W23

Y25

Q_IP_CH0

Q_IP_CH1

V23

B12

Q_OUT

A12

Q_OUT_N

RINGER_GPIO18

L19

RTCK

H16

L21

SBCK

J23

PA_ON0

F17

MDDIC_DATN

A23

A22

MDDIC_DATP

MDDIC_STBN

B23

B22

MDDIC_STBP

MDDIH_DATN

B19

B20

MDDIH_DATP

MDDIH_STBN

A19

A20

MDDIH_STBP

I2C_SCL_GPIO27

K21

I2C_SDA_GPIO26

AB25

I_IM_CH0

V25

I_IM_CH1

AC25

I_IP_CH0

W25

I_IP_CH1

I_OUT

B13

I_OUT_N

A13

GRFC3_GPIO6

GRFC4_AUX_SBCK_GPIO7

H10

D11

GRFC5_AUX_SBST_GPIO8

GRFC7_GPIO10

T23

B4

GRFC8_GPIO11

GRFX6_GPIO9

T19

GSM_PA_DAC_REF

AD26

N16

H17

GP_PDM1_PA_RANGE0

D17

GP_PDM2_PA_RANGE1

B8

GRFC0_GPIO3

A8

GRFC1_AUX_SBDT_GPIO4

D9

GRFC2_GPIO5

F10

F12

DAC_REF

GPIO17

K26

GPIO19

G21

L15

CAMIF_DATA7_GPIO59

D20

F16

CAMIF_DATA8_GPIO60

F20

CAMIF_DATA9_GPIO61

E23

CAMIF_HSYNC_GPIO15

CAMIF_PCLK_GPIO82

K23

CAMIF_VSYNC_GPIO16

B3

G23

BT_CLK_GPIO25

BT_DATA_GPIO20

R19

E26

BT_SBCK_GPIO23 BT_SBDT_GPIO22

E25

F23

BT_SBST_GPIO24

BT_TX_RX_N_GPIO21

H21

CAMIF_DATA0_GPIO83

J25

J26

CAMIF_DATA1_GPIO81

D21

CAMIF_DATA2_AUX_TRST_N_GPIO54

CAMIF_DATA3_AUX_TCK_GPIO55

C25

CAMIF_DATA4_AUX_TMS_GPIO56

D22

J19

CAMIF_DATA5_AUX_TDI_GPIO57

CAMIF_DATA6_AUX_TDO_GPIO58

AUX_PCM_CLK_GRFC14_GPIO80

K19

N21

AUX_PCM_DIN_GRFC13_GPIO14

AUX_PCM_DOUT_GRFC12_GPIO103

G4

AUX_PCM_SYNC_GRFC11_GPIO102

J8

600-1

R609100K

0.01u

C644

100K R611

51K

R610

R6071K

C646

0.1u

R6082K

VREG_MSMP_2.7V

C645 33nF

HPIEV_IT_STATE_ETMTRIGIN

RX0_I_P

RX0_I_M

RX0_Q_P

RX0_Q_M

EAR_SENSE_N

MSM_RTCK

MSM_TDO

HPI_IT_APE_ETMPSTA0_XTIDAT

HPI_IT_MOD_ETMSYNCA_XTIDAT

HPI_EME_MOD_ETMPSTA1_XTIDAT

HPI_EME_APE_ETMPSTA2_XTIDAT

MSM_TDI

MSM_TCK

TCXO_EN

MSM_TMS

MSM_TRST_N

TX_ON

TX_I_M

PA_ON

GSM_PA_RAMP

TX_Q_P

TX_Q_M

RF_SBCK

RF_SBDT

RF_SBST

DAC_REF

W_VMODE_N

GSM_PA_EN

GSM_PA_BAND

GSM_TX_VCO_1_EN_N

GSM_TX_VCO_0_EN_N

ANT_SEL1

ANT_SEL2

ANT_SEL0

GSM_PA_DAC_REF

TX_I_P

TX_AGC_ADJ TRK_LO_ADJ

Figure. Schematic of RF Interface of MSM6275

- 53 -

3. TECHNICAL BRIEF

3.12.2. MSM sub system

3.12.2.1. SIM interface

SIM interface scheme is shown in Figure. And, there control signals are followed

•

USIM_CLK : USIM Clock

•

USIM_Reset : USIM Reset

•

USIM_Data : USIM Data T/Rx

3.12.2.2. UART interface

UART signals are connected to MSM GPIO through IO connector with 115.2kbps speed. And, used for RF calibration and Data download.

LGE Internal Use Only

Figure. SIM Interface

Table. UART interface

MSM6275

PM6650

USIM

USIM CLK

USIM Reset

USIM Data

USIM Reset

USIM CLK

VREG_USIM 2.85V

GPIO_Map Name Note

GPIO_96 UART_RXD Data_Rx

GPIO_95 UART_TXD Data_Tx

- 54 -

3. TECHNICAL BRIEF

3.12.2.3. USB

The MSM6275 device contains a Universal Serial Bus (USB) interface to provide an efficient interconnect between the mobile phone and a personal computer (PC). The USB interface of the MSM6275 was designed to comply with the definition of a peripheral as specified in USB Specification, Revision 1.1. Therefore, by definition, the USB interface is also compliant as a peripheral with the USB Specification, Revision 2.0. The USB Specification Revision 1.1 defines two speeds of operation, namely low-speed (1.5 Mbps) and full-speed (12 Mbps), both of which are supported by the MSM6275. KS10’s USB interface uses the PM6650 internal logic for USB Transceiver.

LGE Internal Use Only

Only for training and service purposes

Name Note

USB_RCV Rx_Data to MSM

USB_DAT Data to/from MSM

USB_SE0 Data to/from MSM

USB_OE_N Out-Put Enable of Transceiver

USB_VBUS USB_Power From Host(PC)

USB_D+ USB Data+ to Host

USB_D- USB Data- to Host

Table. USB signal interface

Figure. USB Interface

MSM6275_USB Block PM6650_USB Block

Figure. Schematic of USB block (MSM6275 Side & PM6650 Side)

MSM6275 PM6650

MMI

Connector

USB_D-

USB_D+

USB_VBU S

USB_SE0

USB_DAT

USB_OE_ N

UART3_DP_RX_DATA_GPIO85

UART3_DP_TX_DATA_GPIO84

M19

P16

UART1_CTS_N_GPIO97

UART1_DP_RX_DATA_GPIO96

M23

UART1_DP_TX_DATA_GPIO95

L26

P21

UART1_RFR_N_PA_POWER_CTL_M_GPIO98

G6

UART2_CTS_N_GPIO90

UART2_DP_TX_DATA_GPIO88

E4

UART2_RFR_N_GPIO91

F4

UART3_CTS_N_GPIO86

L23

M21

GPIO42

GPIO44

D8

F14

GPIO64

GPIO39

F7

GPIO40

D6

D7

PM_SBCK

MSM_UART_RXD

MSM_UART_TXD

MSM_USIM_RST_N

MSM_USIM_DATA

MSM_USIM_CLK

PM_SBDT

PM_SBST

PM_INT_N

PS_HOLD

Draw the Artwork_line thickly !!!!!

--->> USB_VBUS , FLASH_DRV_N , KPD_DRV_N , KEY_ON_SW_N , MOT_PWR-

Power Line --> Route carefully!!!!!

4.7u

smd_1608h_9_r

C731

47K R710

C7321u

+VPWR

RB521S-30

D701

GP1_DRV_N(MPP7)

LCD_DRV_N

22

KPD_DRV_N

23

KPDPWR_N

24

VIB_DRV_N

25

VSW_5V

14

USB_CTL_N

15

USB_VBUS

16

USB_DAT

17

USB_D_P

18

USB_SE0

19

USB_D_M

20 21

VREG_5V USB_OE_N

13

USB_VBUS

100K

USB_CTL_N

USB_OE_N

USB_DAT

MSM_USB_D+

USB_SE0

MSM_USB_D-

- 55 -

3. TECHNICAL BRIEF

3.12.2.3. HKADC (House Keeping ADC)

The MSM6275 device has an on-chip 8-bit analog-to-digital converter (HKADC) which is tended to digitize DC signals corresponding to analog parameters such as battery voltage, temperature, and RF power levels. The MSM6275 device has six analog input pins which are multiplexed to the input of the internal HKADC.

LGE Internal Use Only

Figure. MSM6275 HKADC Block diagram

Table. HKADC channel table

ADC Ch# Signal Name Note

HKADC0 AMUX_OUT RF PAM Temperature sensing

HKADC1 VBATT_SENSE Battery voltage level sensing

HKADC2 HDET1 RF WCDMA PAM Power Level sensing

HKADC3 VBAT_TEMP Battery Temperature sensing

HKADC4 - -

HKADC5 - -

LGE Internal Use Only

Only for training and service purposes

3.12.3. Power Block

3.12.3.1. General

MSM6275A, included RF, is fully covered by PM6650-1M(Qualcomm PMIC). PM6650-1M cover the power of MSM6275A, MSM memory, RF block, USIM and TCXO.

Major power components are :

PM6650-1M (U700) : Phone power supply NUS5530MN (Q701) : External charger supply switching & Main Battery charging control

3.12.3.2. PM6650-1M

The PM6650-1M device (Figure 1-1) integrates all wireless handset power management. The power management portion accepts power from all the most common sources - battery, external charger, adapter, coin cell back-up - and generates all the regulated voltages needed to power the appropriate handset electronics. It monitors and controls the power sources, detecting which sources are applied, verifying that they are within acceptable operational limits, and coordinates battery and coin cell recharging while maintaining the handset electronics supply voltages. Eight programmable output voltages are generated using low dropout voltage regulators, all derived from a common trimmed voltage reference.

A dedicated controller manages the TCXO warm-up and signal buffering, and key parameters (undervoltage lockout and crystal oscillator signal presence) are monitored to protect against detrimental conditions.

MSM device controls and statuses the PM6650-1M IC using a three-line Serial BusInterface(SBI) supplemented by an Interrupt Manager for time-critical information. Another dedicated IC Interface circuit monitors multiple trigger events and controls the power-on sequence.

3. TECHNICAL BRIEF

- 56 -

LGE Internal Use Only

3. TECHNICAL BRIEF

- 57 -

Figure. PM6650-1M Functional Block Diagram

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

- 58 -

3.12.3.3. Charging control

A programmable charging block in PM6650-1M is used for battery charging. It is possible to set limits for the charging current. The external supply typically connects directly to pin (VCHG). The voltage on this pin (VCHG) is monitored by detection circuitry to ascertain whether a valid external supply is applied or not. For additional accuracy or to capture variations over time, this voltage is routed internally to the housekeeping ADC via the analog multiplexer. PM6650-1M circuits monitor voltages at VCHARGER and ICHARGE pins to determine which supply should be used and when to switch between the two supplies. These pins are connected to the Source (or emitter) and Drain (or collector) contacts of the pass transistor respectively.

4.2V~3.96V

3.86V~3.79V

3.78V~3.75V

3.95V ~ 3.87V

3.74V~3.70V 3.69V~3.64V 3.63V~3.51V 3.50V~3.20V

KS10 Charging Control block

Figure. KS10 Battery Bar Display (Standby condition)

LGE Internal Use Only

3. TECHNICAL BRIEF

- 59 -

3.12.3.3.1 Trickle charging

Trickle Charging of the main battery, enabled through SBI control and powered from VDD, is provided by the PM6650-1M IC, The trickle charger is on-chip programmable current source that supplies current from VDDto pin (VBAT). Trickle charging can be used for lithium-ion and nickelbased batteries, with its performance specified below (3.2V). The charging current is set to 80mA.

Parameter Min Typ Max Unit

Trickle Current 60 80 100 mA

- 60 -

3. TECHNICAL BRIEF

3.12.3.3.2 Constant current charging

The PM6650-1M IC supports constant current charging of the main battery by controlling the charger pass transistor and the battery transistor. The constant current charging continues until the battery reaches its target voltage, 4.2V.

3.12.3.3.3 Constant voltage charging

Constant voltage charging begins when the battery voltage reaches a target voltage, 4.2V. The end of constant voltage charging is commonly detected 10% of the full charging current (60mA)

•

Charging Method : CC & CV (Constant Current & Constant Voltage)

•

Maximum Charging Voltage : 4.2V

•

Maximum Charging Current : 650mA

•

Nominal Battery Capacity : 950 mAh

•

Charger Voltage : 4.8V

•

Charging time : Max 3 h (Except time trickle charging)

•

Full charge indication current (icon stop current) : 60mA

•

Low battery POP UP : 3.63V , 3.50V

•

Low battery alarm interval : warning tone once only

•

Cut-off voltage : 3.20V

LGE Internal Use Only

Only for training and service purposes

- 61 -

3. TECHNICAL BRIEF

3.13. Audio and sound

3.13.1. Overview of Audio & Sound & BT path

LGE Internal Use Only

MSM

AMP

Level

Shifter

AU_19.2M

Level

Shifter

I2CSCL0 I2CSDA0

PM_SCL

SCL

SDA

UART0

UART

PCM

I2S

WM_BCLK

WM_LRC

WM_MSPTCK0 WM_MSPTFS0

MSPRFS0

MSPRCK0

RXP RSN

WM_MONO1 WM_MONO2

MIC1

MIC2

MIC_BIAS

SPK_AMP_SD_N

OUT3

LOUT1

Speaker

Receiver

Head Set

MIC

LOUT2

ROUT2

ROUT1

EAR_SENSE_N

HOOK_SENSE_N

GPIO

Switch

STN8810

(CPU)

I2S

WM_DACDAT

WM_MSPRXD0

MSPRXD0

GPIO

Filter

BT_19.2M

ANT

WM_8753

(Audio Codec)

STLC2500C

(BT)

VREG_MSMP_2.7V

PM_SDA

Figure. Block diagram ofaAudio &sSound path

LGE Internal Use Only

Only for training and service purposes

3.13.2. Audio signal processing & interface

3.13.2.1. MSM6275A audio interface

The MSM6275 device integrates a wideband audio CODEC into the mobile station modem. The wideband codec allows the MSM device to support stereo music/ringer Melody applications in addition to the 8 kHz voice band applications on the forward link. In the audio transmit path, the device operates as 13-bit linear converter with software selectable 8 kHz and 16 kHz sampling rate. In the audio receive path, the device operates as a software selectable 13-bit or 16-bit linear converter with software selectable 8 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz sampling rate. Through software, the Rx path can be configured as either a mono or stereo output.

The integrated CODEC contains all of the required conversion and amplification stages for the audio front end. The CODEC operates as a 13-bit linear CODEC with the transmit (Tx) and receive (Rx) filters designed to meet ITU-T G.712 requirements. The CODEC includes a programmable sidetone path for summing a portion of the Tx audio into the Rx path. An on-chip Voltage/Current reference is provided to generate the precise voltages and currents required by the CODEC.

The interface supports two differential microphone inputs and a differential auxiliary input, each of which can be configured as single-ended if desired. In addition, the interface supports one differential earphone output, one single-ended earphone output, and one differential auxiliary output or two singleended line outputs.

The CODEC is configured through the QDSP4000 command types and is not directly controlled by the microprocessor. The CODEC configuration command is sent to the QDSP4000 and then the QDSP4000 executes the command and configures the CODEC. Data is exchanged between the codec interface and the QDSP4000 through its DMA interface. The QDSP4000 uses the Ex_DMA_4 channel for reading data from the codec and uses the Ex_DMA_5 channel to transfer data to the codec. The CODEC interface is shown in more detail in Figure below.

3. TECHNICAL BRIEF

- 62 -

Figure. Detailed diagram of MSM6275 audio interface

LGE Internal Use Only

3. TECHNICAL BRIEF

- 63 -

3.13.2.2. STn8810 audio interface

Smart Audio Accelerator (SAA)

This high-performance block performs an audio hardware accelerator based on a programmable audio DSP with 24-bit data path and ultra low power implementation.

Figure. Detailed diagram of STn8810 audio interface

- 64 -

3. TECHNICAL BRIEF

3.13.2.3. WM8753L audio interface

The WM8753L is a low Power, high quality stereo Codec with integrated Voice CODEC designed for portable digital telephony applications such as mobile phone, or headset with Hi-Fi playback capability.

The device integrates dual interfaces to two differentially connected microphones, and includes drevers for speakers, headphone and earpiece. External component requirements are reduced as no separate microphone or headphone amplifiers are required.

Advanced on-chip digital signal processing performs tone control, Bass Boost and automatic level control for the microphone or line input through the ADC.

LGE Internal Use Only

Only for training and service purposes

Figure. Detailed diagram of WM8753L audio interface

- 65 -

3. TECHNICAL BRIEF

LGE Internal Use Only

MSM6275A BLK Handset main MIC BLK

Place near

(CODEC VSS)

MSM pin W18

10%

SDCC_DAT1_GPIO99

F25

M25

SDCC_DAT2_GPIO100 SDCC_DAT3_GPIO101

M26

MICFBN

MICFBP

AC21

MICINN

AC19

AC20

MICINP

MICOUTN

AA18

AA19

MICOUTP

MDP_VSYNC_PRIMARY_GPIO105

AD2

AE3

MDP_VSYNC_SECONDA_GPIO104

MIC1N

AF20

MIC1P

AE20

AF21

MIC2N

MIC2P

AF22

MICBIAS

T15

AC22

HPH_L

W17

AA17

HPH_R

EAR1ON

AE18

EAR1OP

AF18

CCOMP

AA20

AF19

AUXIN

AE19

AUXIP

AC18

AUXON_AUXOR

AUXOP_AUXOL

AC17

C611 NANA

C608NAC610

0.1u

C607

C609 NA

L600

100nH

C600 10p

WM_HPH_R

WM_HPH_L

MICINP

WM_MONO1

WM_MONO2

MICFBN

MICFBP

MICINN

MICOUTN

MICOUTP

WM_RXN

WM_RXP

C245 1u

EVLC18S02015

VA200

C247 10p

2.2K

R221

C251 39p

2.2K

R227

MIC200

SUMY0009203

1 2

C252 39p

VA201

EVLC18S02015

39p

C246

1uC248

WM_MICBIAS

WM_MIC1P

WM_MIC1N

Head Set Jack BLK

1608

CONNECTOR VBATT_SENSE PIN CHECK!!

1%

Between (VBATT & +5V_PWR) and (Mic signal)

CAD for EMC Noise

1%

C249 47n

R717

NA

VREG_MSMP_2.7V

R716

0

U203 NCS2200SQ2T2G

GND

2

1

OUT

VCC

5

3

VIN+

VIN-

4

AP_VDD_IO_2.7V

5 6 7 8 9

11 12 13 14 15 16 17 18

19

2

20

21

22

3 4

CN202

1

10

C242 33u

FB503 1000

33uC244

10pC258

47pC255

R223 68

R225 NA

C240 1u

RSB6.8CST2RVA211

EVLC14S02050VA205

1

2

3

4

5

EVLC14S02050

VBATT

CN203

VA208

smd_1608h_9_r

1u

C254

2.2K

R217

680K

R226

C259

33p

0.01u

C257

C238

0.1u

C239

10p

USB_VBUS_IN

VA206 EVLC14S02050

4

G2

1

IN2OUT

NFM21PC105B1A3

U205

G1

3

FB245

10u

C237

100K R219

+5V_PWR

47pC256

EVLC14S02050VA204

PSD12-LFD200

VREG_MSMP_2.7V

INSTPAR

470K

R224

C253 33u

VA203

EVLC18S02003

330K

R218

VA207 EVLC14S02050

C241 1u

AP_VDD_IO_1.8V

EVLC18S02003

VA202

0.1u

C260

68R222

ICVL0505600V150FRVA209

1M

R216

VA210 RSB6.8CST2R

11K

R228

PSD05-LF

D201

INSTPAR

USB_D+ USB_D-

EAR_SENSE_N

HOOK_SENSE

WM_LOUT1

UART_RXD

UART_TXD

VBAT_TEMP

WM_MIC2N

WM_MIC2P

REMOTE_PWR_ON

VBATT_SENSE

WM_ROUT1

- 66 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

Audio Codec(WM8753) BLK

WM_DVDD

WM_AVDD

1u C229

NAC231

C227 10p

1uC224

100K R214

C223 NA

C226 1u

1u C230

C233 39p

C222 1u

AP_VDD_CAM_1.8V

R213100K

NA

R209

C232 39p

R212

0

C235

4.7u

R211

0

A8

VMID

A4

B5

VREF

VXCLKH3VXDIN

J1

J2

VXDOUT

VXFS

J3

R215100K

MONO2

A7

NC1C8NC2F8NC3

NC4

G2

E8

OUT3

OUT4

E9

J8

PCMCLK

H9

PGND

PVDD

G9

ROUT1

D9

ROUT2

B9

RXN

C2

RXP

B1

H1

SCLKG1SDIN

SPKRVDD

GPIO4

HPVDD

F9

HP_SPKRGND

C9

LINE1

A2

A1

LINE2

D8

LOUT1

A9

LOUT2

H4

LRC

J6

MCLK

C1

MIC1

MIC1N

D2

D1

MIC2

MIC2N

E2

MICBIAS

B4

F1

MODE_GPIO3

MONO1

B6

B7

U202

WM8753LEB-RV

A3

ACIN

B3

ACOP

ADCDAT

J5

A5

AGND

AVDD

A6

J4

BCLK

CSB_GPIO5

F2

DACDAT

H5

H6

DBVDD

DCVDD

J7

DGND

H7

G8

GP1_CLK1

GP2_CLK2

J9

E1

C225 1u

C228 1u

C234

4.7u

WM_DVDD

C236

4.7u

WM_DACDAT

WM_LRC

WM_MSPRXD0

MSPTXD0

MSPTCK0

MSPTFS0

WM_BCLK

WM_ADCDAT

SPK_AMP_EN

WM_HPH_R

WM_HPH_L

RECEIVER--

WM_ROUT2WM_MICBIAS

AU_SW

VT_SW

PM_SDA

PM_SCL

AU_19.2M

WM_RXP

WM_RXN

RECEIVER-

WM_MONO2

WM_MONO1

WM_MIC1N

WM_ROUT1

WM_MIC1P

WM_LOUT1WM_MIC2N

WM_LOUT2

WM_MIC2P

RECEIVER+

Audio Amp for loud Speaker

SPEAKER AMP

C262

0.068u

68KR230

R232 68K

R233

10K

R229

C261 NA

0.068u

C267

AP_+VPWR

R231

100K

2.2u

C263

1

_SHUTDOWN

BYPASS

2

7

GND

IN+

3

4

IN-

9

PGND

6

VDD

VO+

5

VO-

8

TPA6205A1DRBRU208

C268

NA

C266

0.22u

SPKL-

SPKL+

SPK_AMP_EN

WM_LOUT2

WM_ROUT2

- 67 -

3. TECHNICAL BRIEF

3.14. Camera interface

KS10 has two cameras : 2M Pixel CMOS and VGA Pixel CMOS Camera Below figures shows the camera board to board connector and camera I/F signal.

3.14.1. Mega Camera Interface

LGE Internal Use Only

R206 0

EVRC18S03Q015050R

G15G2

10

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

FL201

5G210

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

FL202 EVRC18S03Q015050R

G1

G2

10

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

FL200 EVRC18S03Q015050R

G1

5

CCIRID(0)_CAM

CCIRID(1)_CAM

CCIRID(3)_CAM CCIRID(2)_CAM

CCIRICLK_CAM

CCIRID(5)_CAM CCIRID(4)_CAM

CCIRID(3) CCIRID(2) CCIRID(1) CCIRID(0)

CCIRID(7) CCIRID(6) CCIRID(5) CCIRID(4)

CCIRID(6)_CAM

CCIRID(7)_CAM

CCIRIHS_CAM CCIRIVS_CAM

CAMCLK_27MHZ_CAM CAMCLK_27MHZ

CCIRIHS CCIRIVS

CCIRICLK

CAMCLK_27MHZ

MCAM_27M

Figure. Schematic of 2 Mega Camera EMI/ESD filter I/F

Hi-Z

AXK7L34227

DrivenLOW

HIGH

2M_CAMERA

C2130.1u

HB-1M1005-601JT

FB207

C21210u

31

32

33

34

4 5 6 7

8 9

17 18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

G1

G2

G3 G4

1

10 11 12 13 14 15 16

CN200

CSC3R270000BEVRS00 X200

27MHz

GND

2

3

OUT

TRI_OPEN

1

4

VDD

AP_VDD_IO_2.7V

HB-1M1005-601JT

FB206

R207 100K

AP_VDD_CAM_2.7V

C214

0.01u

C21010u

10

INOUT_A1

1

2

INOUT_A2

INOUT_A3

3

4

INOUT_A4

9

INOUT_B1

INOUT_B2

8

7

INOUT_B3

INOUT_B4

6

FL203 EVRC18S03Q015050R

G15G2

AP_VDD_CAM_2.7V

0.1u C211

10u C218

C207 1u

COM1

3

COM2

9

6

GND

IN1

4

IN2

8

NC1

5

NC2

7

NO1

2

NO2

101

VCC

SLAS4717EPMTR2G

U200

AP_VDD_CAM_1.8V

C21510u

0.1u C217

HB-1M1005-601JT

FB204

FB205

HB-1M1005-601JT

0.1u C216

I2CSDA0_SW

I2CSCL0_CAM

I2CSDA0_CAM

2M_PWDN

I2CSCL0_CAM

I2CSDA0_CAM

I2CSCL0_SW

I2CSDA0_SW

2M_RSTn

2M_RSTn_CAM

CCIRID(4)_CAM CCIRID(3)_CAM

I2CSCL0_SW

CCIRID(2)_CAM

CAM_PWR_EN

CCIRID(1)_CAM CCIRID(0)_CAM

CCIRIVS_CAM CCIRIHS_CAM

I2CSDA0

I2CSCL0

CCIRICLK_CAM

CCIRID(7)_CAM CCIRID(6)_CAM CCIRID(5)_CAM

Figure. Schematic of 2 Mega Camera Board to Board Connector

- 68 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

Table. Interface between 2M Camera Module and Main Board (in camera module)

Image data outputOYUV730

Image data outputOYUV629

Image data outputOYUV528

Image data outputOYUV427

Digital I/O VoltagePIOVDD32

Digital I/O VoltagePIOVDD31

Image data outputOYUV326

Digital Core VoltagePDVDD 1.8V33

GroundGNDGND6

Initializes sensor, Active LowIRESET5

GroundGNDGND4

GroundGNDGND3

Pixel ClockOPCLK2

Non-connectionNCNC11

Non-connectionNCNC10

Clock for two-wire serial interfaceISCK9

Data for two-wire serial interfaceI/OSDA8

Non-connectionNCNC7

Analog VoltagePAVDD 2.8V16

Actuator VoltagePLVDD 2.8V15

Actuator VoltagePLVDD 2.8V14

Power down mode, active HighIPDOWN13

GroundGNDGND12

Master clockICLKIN21

GroundGNDGND20

Vertical Synchronous signalOVSYNC19

Horizontal Synchronous signalOHSYNC18

Analog VoltagePAVDD 2.8V17

GNDGNDGND1

GroundGNDGND22

Image data outputOYUV023

Image data outputOYUV124

Image data outputOYUV225

Digital Core VoltagePDVDD 1.8V34

NotePortNameNo

- 69 -

3. TECHNICAL BRIEF

The 2MCamera module is connected to main board with 34pin Board to Board connector (AXK8L34125). Its interface is dedicated camera interface port in STN8810. The camera port supply 24MHz master clock to camera module and receive 40.078MHz pixel clock (max.15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits data from camera module.

The camera module is controlled by I2C port from STN8810.

LGE Internal Use Only

- 70 -

3. TECHNICAL BRIEF

3.14.2. VGA Camera Interface

LGE Internal Use Only

Only for training and service purposes

Figure. Schematic of Main slider FPCB B to B connector (in main BD)

Figure. Schematic of VGA Camera Board to Board Connector (in main slider FPCB)

AXK7L70227

MAIIN-SLIDER CON-HEADER

0R728

0R727

0R726

0R725

0R724

0R723

0R722

0R721

0R720

0R719

0R718

FB239

AP_VDD_CAM_2.7V

FB224

FB235

FB232

FB229

AP_+VPWR

INOUT_B4

5G110

G2

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

EVRC14S03Q030100R FL204

FB222

FB236

FB237

5G110

G2

1

INOUT_A1

2

INOUT_A2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

FB227

EVRC14S03Q030100RFL208

FB233

FB242

FB225

FB243

FB221

AP_VDD_CAM_1.8V

FB244

INOUT_A3

3

4

INOUT_A4

9

INOUT_B1

INOUT_B2

8

7

INOUT_B3

INOUT_B4

6

FL206 EVRC18S03Q015050R

G15G2

10

INOUT_A1

1

2

INOUT_A2

FB241

G15G2

10

INOUT_A1

1

2

INOUT_A2

INOUT_A3

3

4

INOUT_A4

9

INOUT_B1

INOUT_B2

8

7

INOUT_B3

INOUT_B4

6

FL205EVRC14S03Q030100R

FB223

AP_VDD_LCD_2.8V

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

EVRC14S03Q030100RFL207

5G110

G2

FB234

FB231FB230

64

65

66

67

68

69

7

70

8 9

G1 G2

G3 G4

50

51

52

53

54

55

56

57

58

59

6

60

61

62

63

35 36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34

CN201

1

10 11 12 13 14 15 16 17 18 19

2

FB240

FB238

CCIRID(2) CCIRID(1) CCIRID(0)

CCIRICLK

CCIRIHS

I2CSCL0_CAM

I2CSDA0_CAM

VGA_RSTn

CCIRIVS CCIRID(7) CCIRID(6) CCIRID(5) CCIRID(4) CCIRID(3)

DIS_CSN

LCD_NRESET

DIS_WEN

DIS_RS

CAMCLK_27MHZ_CAM

RECEIVER+

RECEIVER-

RECEIVER--

LCD_VS

LCD_DATA(3)

LCD_DATA(5)

LCD_DATA(7)

LCD_DATA(9)

LCD_DATA(11)

LCD_DATA(13)

LCD_DATA(15)

LCD_DATA(14)

LCD_DATA(12)

LCD_DATA(10)

LCD_DATA(8)

LCD_DATA(0)

LCD_DATA(2)

LCD_DATA(4)

LCD_DATA(6)

MOT_PWR-

WLED_CTL

VGA_STANDBY

KPD_DRV_N KEY_ROW(0) KEY_ROW(1) KEY_ROW(2) KEY_ROW(3)

KEY_COL(4)

KEY_COL(5)

KEY_COL(6)

KEY_COL(7)

LCD_DATA(1)

VGA_CAMERA

AXK720145G

HB-1M1005-601JT

FB101

FB100

HB-1M1005-601JT

1u

C102

AP_VDD_CAM_2.7V

C101

0.1u

C100

0.1u

192

20

3 4 5 6 7 8 9

1

10 11

12

13

14

15

16

17

18

AP_VDD_CAM_1.8V

CN100

VGA_STANDBY

CAMCLK_27MHZ_CAM

I2CSCL0_CAMCCIRICLK_CAM I2CSDA0_CAMCCIRID(0)_CAM

CCIRID(1)_CAM

VGA_RSTn

CCIRIHS_CAMCCIRID(2)_CAM CCIRIVS_CAMCCIRID(3)_CAM CCIRID(7)_CAMCCIRID(4)_CAM CCIRID(6)_CAMCCIRID(5)_CAM

- 71 -

3. TECHNICAL BRIEF

The VGA Camera module is connected to main slider FPCB with 20pin Board to Board connector(AXK820145). The main slider FPCB is connected to main board with 70pin board to board connector.

Its interface is dedicated camera interface port in STN8810. The camera port supply 24MHz master clock to camera module and receive 13.5MHz pixel clock (max. 15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits data from camera module.

The camera module is controlled by I2C port from STN8810.

LGE Internal Use Only

Table. Interface between Camera Module and Main Board (in camera module)

Image Data[1]OD16

Image Data[0]OD05

Video Output Clock D[0:7]OPCLK4

GroundGNDGND3

Master ClockIMCLK2

Image Data[6]OD611

Image Data[5]OD510

Image Data[4]OD49

Image Data[3]OD38

Image Data[2]OD27

Data for two wire serial interfaceI/OSDA16

GroundGNDGND15

Horizontal SynchronizationOHSYNC14

Vertical SynchronizationOVSYNC13

Image Data[7]OD712

Analog core circuit power supply voltage & Digital I/O circuit power supply voltage

PAVDD & IOVDD20

Digital core circuit power supply voltagePDVDD19

Reset initializes sensor Active LowIRESET18

Clock for two wire serial interfaceISCL17

Active ëHighíIENABLE1

NotePortNameNo

- 72 -

3. TECHNICAL BRIEF

3.14.3. LCD backlight / Camera LDO

U100(in SUB board, AAT3151) is a charge pump. U301(in main board, BH18LB1WHFB) supply a

1.8V power of mega camera and VGA camera. U303(in main board, MIC5219-2.7YM5) supply a 2.7V power of mega camera and VGA camera.

These parts are controlled by GPIOs of STN8810.

LGE Internal Use Only

Only for training and service purposes

Figure. Schematic of charge pump

LCD_Backlight driver

ZD101

RSB6.8CST2R

1u

C102

C101 1u

1u

C100

100K

R101

D3 D4

1

EN_SET

2

9

GND

13

PGND

8

VIN

VOUT

5

AP_+VPWR

AAT3151IWP_T1

3

C1+

C1-

4

C2+

6

7

C2-

10

D1

11

D2

12

U100

4.7u

C103

WLED_CTL

LED_ANODE

LED4

LED3

LED2

LED1

Figure. Schematic of camera LDO

AP_+VPWR

AP_VDD_CAM_2.7V

AP_VDD_CAM_1.8V

1u

C305

2.2u

C309

AP_+VPWR

U301 BH18LB1WHFV

BGND

6

GND

2

5

NC

1

STBY

VIN

34

VOUT

4

BYPEN

3

GND

2

1

IN5OUT

U303

MIC5219-2.7YM5

C308 1u

2.2u

C307C306

470p

CAM_PWR_EN

- 73 -

3. TECHNICAL BRIEF

3.14.4. LCD module

LGE Internal Use Only

Figure. LCD I/F Block Diagram

STN8810 LCD

MM_LCD_DATA[0:15]

MM_LCD_WE_N

MM_LCD_ADS_N

MM_LCD_CS_N

MM_LCD_IF_MODE_1

MM_LCD_IF_MODE_0

MM_LCD_RESET

MM_LCD_VSYNC

MM_LCD_RD_N

MM_LCD_RESET

MM_LCD_VSYNC

MM_LCD_RD_N

MM_LCD_DATA[0:15]

MM_LCD_WE_N

MM_LCD_ADS_N

MM_LCD_CS_N

NC

Figure. LCD Module

MAIN LCD

MODULE

260K Color TFT

240 * 320 Pixel

BD663474(Hitachi) Graphic Controller Driver Main LCD Panel

- 74 -

3. TECHNICAL BRIEF

3.14.5. Display

LCD module is connected to SUB board with 35-pin zip connector(XF2B-3545-31A).

The LCD is controlled by 16-bit in STN8810.

LGE Internal Use Only

Only for training and service purposes

Figure. Schematic of Main slider FPCB B to B connector (in main BD)

Figure. Schematic of LCD connector (in SUB board)

AXK7L70227

MAIIN-SLIDER CON-HEADER

0R728

0R727

0R726

0R725

0R724

0R723

0R722

0R721

0R720

0R719

0R718

FB239

AP_VDD_CAM_2.7V

FB224

FB235

FB232

FB229

AP_+VPWR

INOUT_B4

5G110

G2

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

EVRC14S03Q030100R FL204

FB222

FB236

FB237

5G110

G2

1

INOUT_A1

2

INOUT_A2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

FB227

EVRC14S03Q030100RFL208

FB233

FB242

FB225

FB243

FB221

AP_VDD_CAM_1.8V

FB244

INOUT_A3

3

4

INOUT_A4

9

INOUT_B1

INOUT_B2

8

7

INOUT_B3

INOUT_B4

6

FL206 EVRC18S03Q015050R

G15G2

10

INOUT_A1

1

2

INOUT_A2

FB241

G15G2

10

INOUT_A1

1

2

INOUT_A2

INOUT_A3

3

4

INOUT_A4

9

INOUT_B1

INOUT_B2

8

7

INOUT_B3

INOUT_B4

6

FL205EVRC14S03Q030100R

FB223

AP_VDD_LCD_2.8V

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

EVRC14S03Q030100RFL207

5G110

G2

FB234

FB231FB230

64

65

66

67

68

69

7

70

8 9

G1 G2

G3 G4

50

51

52

53

54

55

56

57

58

59

6

60

61

62

63

35 36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34

CN201

1

10 11 12 13 14 15 16 17 18 19

2

FB240

FB238

CCIRID(2) CCIRID(1) CCIRID(0)

CCIRICLK

CCIRIHS

I2CSCL0_CAM

I2CSDA0_CAM

VGA_RSTn

CCIRIVS CCIRID(7) CCIRID(6) CCIRID(5) CCIRID(4) CCIRID(3)

DIS_CSN

LCD_NRESET

DIS_WEN

DIS_RS

CAMCLK_27MHZ_CAM RECEIVER+ RECEIVER-

RECEIVER--

LCD_VS

LCD_DATA(3)

LCD_DATA(5)

LCD_DATA(7)

LCD_DATA(9)

LCD_DATA(11)

LCD_DATA(13)

LCD_DATA(15)

LCD_DATA(14)

LCD_DATA(12)

LCD_DATA(10)

LCD_DATA(8)

LCD_DATA(0)

LCD_DATA(2)

LCD_DATA(4)

LCD_DATA(6)

MOT_PWR-

WLED_CTL

VGA_STANDBY

KPD_DRV_N KEY_ROW(0) KEY_ROW(1) KEY_ROW(2) KEY_ROW(3)

KEY_COL(4) KEY_COL(5) KEY_COL(6) KEY_COL(7)

LCD_DATA(1)

XF2B-3545-31A-P

LCD Connector

(lower contact)

C105 820p

0R115

35

4

5

6

7

8

9

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

1

10

11

12

13

14

15

16

17

18

19

2

CN100

ZD100 RSB6.8CST2R

100K

R102

R103 100K R104 100K

1uC104

AP_VDD_LCD_2.8V

TP100

TP102

TP101

LCD_NRESET

LCD_DATA(0)

LCD_VS DIS_CSN

DIS_WEN

DIS_RS

LED_ANODE

LED3

LED2

LED1

LCD_DATA(1)

LCD_DATA(10) LCD_DATA(11) LCD_DATA(12) LCD_DATA(13) LCD_DATA(14) LCD_DATA(15)

LCD_DATA(2) LCD_DATA(3) LCD_DATA(4) LCD_DATA(5) LCD_DATA(6) LCD_DATA(7) LCD_DATA(8) LCD_DATA(9)

LCD_DATA(0:15)

LED4

- 75 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Table. Interface between 2M Camera Module and Main Board (in camera module

Interface I/O PowerPVCC234

Interface mode selectIIM230

ResetIRESET29

Data Bus (Instruction & Display Data)I/ODB1528

Data Bus (Instruction & Display Data)I/ODB1427

Maker ID (HI : VCC2 level)OMID(HIGH)32

Interface mode selectIIM131

Data Bus (Instruction & Display Data)I/ODB1326

Power Supply for Analog CircuitPVCC133

Power Supply for LED-LED(AN)6

Ground for LED-LED(CA)5

Ground for LED-LED(CA)4

Ground for LED-LED(CA)3

Ground for LED-LED(CA)2

Read StrobeIRD11

Write StrobeIWR10

Register SelectIRS9

Chip SelectICS8

Frame Head Pulse SignalOVSYNC-OUT7

Data Bus (Instruction & Display Data)I/ODB316

Data Bus (Instruction & Display Data)I/ODB215

Data Bus (Instruction & Display Data)I/ODB114

Data Bus (Instruction & Display Data)I/ODB013

GroundGNDGND12

Data Bus (Instruction & Display Data)I/ODB821

Data Bus (Instruction & Display Data)I/ODB720

Data Bus (Instruction & Display Data)I/ODB619

Data Bus (Instruction & Display Data)I/ODB518

Data Bus (Instruction & Display Data)I/ODB417

GroundGNDGND1

Data Bus (Instruction & Display Data)I/ODB922

Data Bus (Instruction & Display Data)I/ODB1023

Data Bus (Instruction & Display Data)I/ODB1124

Data Bus (Instruction & Display Data)I/ODB1225

Ground GNDGND35

NotePortNameNo

- 76 -

3. TECHNICAL BRIEF

3.15 Bluetooth

KS10 supported bluetooth, which is possible to data file transfer, BT headset call.

CPU (STn8810) interfaces with bluetooth one chip module (U401) which includes RF and baseband.

The STLC2500C is a single chip ROM-based Bluetooth solution for applications requiring integration up to HCI level.

The STLC2500C's main interfaces are UART for HCI transport between CPU (STn8810) and bluetooth module, PCM for voice between audio codec.(WM8753) and bluetooth module and GPIOs for control purposes. Voice data is transferred to CPU(STn8810) through audio codec.(WM8753).

The radio has been designed specifically for single chip requirements and for low power consumption. Radio signal from bluetooth antenna (ANT400) is transferred to bluetooth module through BALUN filter (FL400). Bluetooth module has its’ own oscillator (X400, 27MHz) for normal operation and use sleep clock(32.768KHz) from PM6650, PMIC of MSM 6275.

■ Bluetooth™ specification compliance: V1.2

■ Transmit Power : Power Class2

■ Ultra low power architecture with 3 different low power levels:

- Sleep Mode

- Deep Sleep Mode

- Complete Power Down Mode

LGE Internal Use Only

Only for training and service purposes

Figure. Diagram of STLC2500C

LGE Internal Use Only

3. TECHNICAL BRIEF

- 77 -

3.16 Main Features

3.16.1. Main features of KS10

- Slide Type

- WCDMA(2100) + GSM(900,1800) + PCS(1900) Triple mode

- Main LCD: 320*240, 262K (2.4”)

- 2.0M Pixel CMOS Camera

- VGA CMOS Camera

- φ17 speaker

- Stereo Headset

- Video telephony in WCDMA with camera

- HSDPA up to 1.8Mbps

- Loud Speaker phone(in GSM and WCDMA)

- 64 Poly Sound

- MP3/AAC/WMA decoder and play

- MPEG4 encoder/decoder and play/save

- H.263 decoder

- JPEG en/decoder

- Support Bluetooth, USB

- 104 x 52 x 18.9 mm

- 950mAh hard pack

LGE Internal Use Only

Only for training and service purposes

2. Main Components of KS10

3. TECHNICAL BRIEF

- 78 -

KEY Top Side

VGA camera

Speaker

1.3M camera

Intenna

LCD FPCB

MAIN Bottom SideMAIN Top Side

KEY Bottom Side

LCD

LGE Internal Use Only

3. TECHNICAL BRIEF

- 79 -

2. 1 Main Top Side

CN201

X500

U508

U701

U700

U402

U404

U406

U403

X200

U207

FL206

U306

X700

FL203

Side Key

Reference Description Reference Description

U207 over voltage protection IC X200 27MHz OSCILLATOR

U406 Analog Switch FL203 EMI_ESD FILTER

U403 Analog Switch Multiplexer FL206 EMI_ESD FILTER

U404 Key Coder IC CN201 B To B CONNECTOR

U402 hall-effect switch IC U508 RF Receiver(RFR6250E)

U701 MCP Memory U700 PMIC for MSM

U306 LDO Regulator X500 TCXO 19.2MHz

--X700 TCXO 32.768kHz

LGE Internal Use Only

Only for training and service purposes

2.2. Main Bottom Side

3. TECHNICAL BRIEF

- 80 -

Reference Description Reference Description

CN200 B To B CONNECTOR CN202 Connector(I/O, Ear jack, Power)

SW500 RF SWITCH CONNECTOR U501 GSM/EDGE Quadband PAM

CN402 JTAG-JIG-FPCB-CON CN203 Battery Connector

FL500 FILTER, SAPERATOR BAT700 Back up Battery

U506 DUPLEXER, GSM U208 AUDIO AMPLIFIER

U505 PAM _power amplifier module U502 Voltage Controlled Oscillator

U500 RF Transceiver (RTR6250D) U202 Audio Codec.

FL400 SAW FILTER _BPF U600 MSM6275 (Modem BB Chip)

J300 USIM Connector X100 19.2MHz Oscillator

U401 Bluetooth Single Chip U100 STN8810S12B2V1 (CPU)

X400 19.2MHz Oscillator U310 PMIC for CPU

U400 LDO Regulator L301 Power Inductor

S300 Micro-SD CONNECTOR MIC200 Microphone

CN200

SW500

FL500

U506

U505

U500

CN402

FL400

J300

U401

X400

U400

S300

CN202

U501

CN203

BAT700

U208 U502 U202

U600

X100

U100

U310

L301

MIC200

LGE Internal Use Only

3. TECHNICAL BRIEF

- 81 -

2.3. KEY Top Side

2.4. KEY Bottom Side

SW100

CN101

U100

CN100

Reference Description Reference Description

SW100 Dome Switch U100 LCD Backlight Driver

CN100 LCD Connector CN101

FUNCTION-SLIDER Connector

(FPCB to KEYPCB)

LGE Internal Use Only

Only for training and service purposes

2.5. LCD FPCB

3. TECHNICAL BRIEF

- 82 -

Reference Description Reference Description

Vibrator Vibrator PAD CN101

FUNCTION-SLIDER

Receiver Receiver PAD

Connector (FPCB to KEYPCB)

CN100 VGA_CAMERA Connector CN102

MAIN-SLIDER CON-SOCKET

Vibrator PAD

CN100

Receiver

CN101

CN102

LGE Internal Use Only

4. TROUBLE SHOOTING

- 83 -

4. TROUBLE SHOOTING

4.1 RF Component

RF component (Bottom)

U502

U503

U505

SW500

U504

U507

U501

U506

U500

FL500

Reference Description Reference Description

U505 WCDMA PAM U507 Coupler

U506 WCDMA Duplexer U501 GSM/D/PCS PAM

U503 WCDMA TX SAW U504 HDET

FL500 Front-End-Module U500 GSM/WCDMA Transceiver (RTR)

U502 GSM TX VCO SW500 RF Antenna Connector

LGE Internal Use Only

Only for training and service purposes

RF component (Top)

4. TROUBLE SHOOTING

- 84 -

Reference Description

U508 RFR6250(WCDMA RX)

FL501 WCDMA RX SAW

FL501

U508

LGE Internal Use Only

4. TROUBLE SHOOTING

- 85 -

4.2 SIGNAL PATH

GSM/DCS/PCS Rx Tx PATH

A. GSM/DCS/PCS Tx PATH

B. GSM/DCS/PCS Rx PATH

A

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 86 -

WCDMA RX/ TX PATH

C. WCDMA Tx PATH

D. WCDMA Rx PATH

- 87 -

4. TROUBLE SHOOTING

4.3 Checking VCXO Block

The reference frequency (19.2MHz) from X100 (VCXO) is used WCDMA TX part, GSM part and BB part.

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 88 -

Check 1. Crystal part

If you already check this crystal part, you can skip check 1.

Test Point (Crystal Part)

TCXO

C564

0.01u

C567 1000p

100ohm

R525

C563 1000p

2

GNDOUT

3

VCC4VCONT

1

19.2MHz

X500

100pC559

C566

0.1uF

VREG_TCXO_2.85V

1000pC562

TCXO_PM

RTR6250_TCXO

RFR6250_TCXO

TRK_LO_ADJ

Schematic of the Crystal Part

TP3

TP2

TP1

LGE Internal Use Only

4. TROUBLE SHOOTING

- 89 -

Schematic of the Crystal Part (19.2MHz)

TP1

C153

0.1u

NA

C152

AP_VDD_IO_1.8V

3

1

TRI_OPEN

VDD

4

19.2MHz

X100

CSC3M192000EEVRS00

2

GND

OUT

1

2

4

VCC

5

NL17SZ08XV5T2

U101

3 GND

AP_VDD_IO_1.8V

3

1

2

4

5

VCC

U103

NL17SZ08XV5T2

GND

C1540.1u

C1510.1u

AU_CLK_EN

AU_19.2M

REQUEST_MC

PWREN

CPU_19.2M

TP1

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 90 -

Check TP1

VCC of VCXO

≥

VCC 2.8V

Yes

Check TP2

TRK_LO_AD

≥

3V Voltage 0V

Yes

Check TP3

With Oscilloscope

19.2MHz Signal

Yes

J

≥

No

Check PMIC

Check MSM

Check soldering and components

VCXO is OK

Check other part

LGE Internal Use Only

4. TROUBLE SHOOTING

- 91 -

4.4 Checking Ant. Switch Module Block

VREG_RFR_2.85V

C511 47p

C502 NA

56p

ANT500

C506

NA

C512

L514 7.5nH

C520

0.1u

ANT501

47p

C510

L502

1p

UMTS_TX_RX

VC1

17 15

VC2

VC3

14

16

VDD

ANT

12

DCS_PCS_TX

8

3

DCS_RX1

DCS_RX2

4

1

EGSM_RX1

EGSM_RX2

2

EGSM_TX

10

7

GND1

GND2

9

11

GND3

GND4

13 18

GND5

GND6

20

5

PCS_RX1

PCS_RX2

6

19

FL500ESHS-L090UB

0

C500

56pC501

C509 47p

KMS-512

SW500

ANT

G1

G2

RF

56nH

L504

C519 47p

C507

1.5nH

C513 NA

WCDMA_2100

ANT_SEL0 ANT_SEL1 ANT_SEL2

Schematic of the Antenna Switch Block

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 92 -

Logic Table of the Antenna Switch

Checking Switch Block power source

Check Soldering of

ANT_SEL0, 1, 2 High Level

2.5V < Voltgae < 3.0V

Check VCC

TP1 VREG_RFRX_0_2.85V

Check the Logic

in each mode

YES

NO

Mode ANT_SEL0 ANT_SEL1 ANT_SEL2

EGSM TX High Low Low

EGSM RX Low Low Low

DCS/PCS TX Low High High

DCS RX Low Low High

PCS RX Low High Low

UMTS Low Low Low

LGE Internal Use Only

4. TROUBLE SHOOTING

- 93 -

4.5 Checking WCDMA Block

START

1. Check VCXO 19.2MHz

2. Check ANT. SW Module ANT_SEL0, 1, 2

3. Check RF Tx Level

4. Check PAM Block

5. Check RF Rx Level

6. Re-download SW & CAL.

1

5

3.4

2

LGE Internal Use Only

Only for training and service purposes

4.5.1 Checking VCXO Block

Refer to 3.3

4.5.2 Checking Ant. SW module

Refer to 3.4

4.5.3 Checking RF TX Level

Test Point (RF TX Level)

4. TROUBLE SHOOTING

- 94 -

TP1

TP2

TP3

TP4

LGE Internal Use Only

4. TROUBLE SHOOTING

- 95 -

TP1

TP4

TP3

TP2

ANT500

ANT501

ANT_SEL0 ANT_SEL1 ANT_SEL2

VREG_RFR_2.85V

WCDMA

L502

1p

C500

SW500

C502 NA

C519 47p

KMS-512

C509 47p

C520

0.1u

ANT

G2

RF

G1

C510 47p

L514 7.5nH

0

L504

56nH

C511 47p

56pC501

12

VDD

16

ANT

EGSM_RX1

EGSM_RX2

DCS_RX1

DCS_RX2

PCS_RX1

PCS_RX2

DCS_PCS_TX

EGSM_TX

UMTS_TX_RX

FL500ESHS-L090UB

1 2 3 4 5 6

8 10 19

56p

C506

C512 NA

C507

1.5nH

C513 NA

WCDMA_2100

7

GND1

9

GND2

11

GND3

13

GND4

18

GND5

20

GND6

17

VC1

15

VC2

14

VC3

L526

3.9nH

C561

22p

WCDMA_2100_TX_OUT

EFCH1950TDC1

G3

4

G2

L525

8.2nH

U503

3

1

INOUT

2G15

1.8nHC560

WCDMA_2100

C581 12p

RX TX

ANT

6.2KR529

C569

+VPWR

U506ACMD-7601

G1G2G3G4G5G6G7

IN

COUP

32

51

R531

1

OUT

50OHM

4

C568 22u

C570

0.01u

R530

3.9nH

L527

C571

0.01u

C575

1.8nH

1.2p

47

C580

GND2

6

GND3

7

RFOUT

8

GND4

9

VCC2 GND5

11

AWT6277R U505

VREF

VMODE

GND1

RFIN

VCC1

5 4 3 2 110

15p

W_VMODE_N

C573

0.1u

C574 100p

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 96 -

For testing, Max power output is needed.

Set the Phone Tx is ON

and PDM is 450

Check TP1

Over 21dBm ?

Change the board

RF Tx Level is OK

Check FEM

Check PAM Block

Refer to 3.5.4

NO

YES

Check TP2

Over 19dBm ?

NO

YES

Check TP3

Over 15dBm ?

NO

YES

Check TP4

Over -5dBm ?

NO

YES

Check Duplexer

LGE Internal Use Only

4. TROUBLE SHOOTING

- 97 -

4.5.4 Checking PAM Block

PAM control signal

PA_ON : WCDMA Tx Power Detect IC(HDET) Enable

PA_RO: WCDMA Tx Power Amp Gain Control

PA_ON must be HIGH(over 2.5V)

PA_FET_N must be LOW if the max Tx power is set (lower than 0.5V)

PAM_OUT

PAM_IN

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 98 -

PAM IN/OUT Signal

PAM OUT must be over 15dBm

PAM IN must be over -5dBm

PAM_IN

PAM_OUT

LGE Internal Use Only

4. TROUBLE SHOOTING

- 99 -

WCDMA

TP1

TP3

TP2

WCDMA_2100

C581 12p

RX TX

ANT

+VPWR

U506ACMD-7601

G1G2G3G4G5G6G7

IN

COUP

32

51

R531

1

OUT

50OHM

4

C568 22u

C570

0.01u

R530

3.9nH

L527

1.8nHC560

C571

0.01u

C575

1.8nH

1.2p

C580

L525

8.2nH

47

U503

EFCH1950TDC1

3

G3

4

INOUT

G2

2G15

11

1

L526

3.9nH

GND2

6

GND3

7

RFOUT

8

GND4

9

VCC2 GND5

AWT6277R U505

VREF

VMODE

GND1

VCC1

C561

22p

5 4 3

RFIN

2 110

WCDMA_2100_TX_OUT

6.2KR529

C569 15p

W_VMODE_N

C573

0.1u

C574 100p

ILNA_OUT

LGE Internal Use Only

Only for training and service purposes

4.5.5 Check RF Rx Level

Test Point (RF Rx Level)

4. TROUBLE SHOOTING

- 100 -

TP1

TP2

TOP BOTTOM

TP4 TP

3

BIAS

LGE Internal Use Only

4. TROUBLE SHOOTING

- 101 -

C570

C568

C571

TP1

TP2

TP3

BIAS

TP4

ANT500

ANT501

ANT_SEL0 ANT_SEL1 ANT_SEL2

WCDMA_2100

VREG_RFR_2.85V

RX TX

ANT

C581 12p

12

7

GND1

9

GND2

11

GND3

13

GND4

18

GND5

20

GND6

17

VC1

15

VC2

14

VC3

ANT

VDD

16

FL500ESHS-L090UB

EGSM_RX1

EGSM_RX2

DCS_RX1

DCS_RX2

PCS_RX1

PCS_RX2

DCS_PCS_TX

EGSM_TX

UMTS_TX_RX

1 2 3 4 5 6

8 10 19

56p

C506

C512 NA

C507

1.5nH

C513 NA

WCDMA_2100

L502 1p

C500

SW500

C502 NA

KMS-512

C509 47p

ANT

G2

RF

G1

C510 47p

0

L504

56nH

C511 47p

56pC501

L514 7.5nH

C519

C520

47p

0.1u

22u

0.01u

U506ACMD-7601

G1G2G3G4G5G6G7

1

IN

OUT

50OHM

COUP

4

32

51

R531

C586

1.2p

C575

R530

1.8nH

3.9nH

1.2p

L527

47

C580

L533

2.7nH

VREG_RFR_2.85V

GND2

6

GND3

7

RFOUT

8

GND4

9

VCC2 GND5

11

AWT6277R U505

L532

100nH

VREF

VMODE

GND1

VCC1

5 4 3

RFIN

2 110

ILNA_OUT

C587 680p

C595

C594

10p

0.1u

C599

C598

100p

0.1u

VOPS VRMS

ADL5500 U504

C574 100p

0.1u

13

PLNA_OUT

14

ILNA_OUT

15

PLNA_BIAS

16

PLNA_IN

17

ILNA_BIAS

18

ILNA_IN

19

VDDRF3

20

RX_IP

21

RX_IM

22

RX_QP

23

RX_QM

100p

C588

24

VDDA2

4.7u

10

R535

CP2_OUT

RX0_Q_M

RX0_Q_P RX0_I_M

RX0_I_P

C591

C572 1500pC573

12

VDDRF2

UMTS_TUNE

25

PMIXP

VDDA3

HDET1

C585

3

5

6

7

4

10

11

8

928

1

2

GND

IMIXP

IMIXM

GMIXP

PMIXM

BLANK

VDDA1

GMIXM

VDDRF1

PGND

GLNA_OUT

GLNA_BIAS

GLNA_IN

R_BIAS

VDDA8

SBST SBDT

U508

SBCK

(1%)

RFR6250E

VDDM

GRX_IP GRX_IM GRX_QP

GRX_QM

VDDA5

VDDA6

VDDA7

TCXO

VDDA4

GPS_TUNE

LO_OUT

CP_DUMP

CP_OUT

FAQ

35

32

34

36

33

26

27

29

30

31

C596

4.7p

C800 100p

100p

49 48 47

R532

46 45

11.3K

44 43 42 41 40 39 38 37

C593

C592

4.7u

100p

C597 100p

ILNA_OUT

8.2p C578

L530

2.2nH

FL501 B7827

1

2

3

G1

IN

G2

5

4

O1

O2

L529 33nH

C577

C584

33p

C579

0.1u

L528

2.7nH

L531

2.7nH

IMT_RX_M

IMT_RX_P

LG KS10 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual