This manual provides the information necessary to repair, calibration, description and download the features of
the GS290.
1.2. Regulatory Information
1.2.1. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons
other than your company’s employees, agents, subcontractors, or person working on your company’s behalf)
can result in substantial additional charges you’re your telecommunications services. System users are
responsible for the security of own system. There are may be risks of toll fraud associated with your
telecommunications system. System users are responsible for programming and configuring the equipment to
prevent unauthorized use. LGE does not warrant that this product is immune from the above case but will
prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or
connected to it. LGE will not be responsible for any charges that result from such unauthorized use.
1.2.2. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and
possibly causing harm or interruption in service to the telephone network, it should
disconnect telephone service until repair can be done. A telephone company may
temporarily disconnect service as long as repair is not done.
1.2.3. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the
GS290 or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing
the user to take appropriate steps to maintain telephone service.
1.2.4. Maintenance Limitations
Maintenance limitations on the GS290 must be performed only at the LGE or its authorized agents.
The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the
system and may void any remaining warranty.
The GS290 complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
1.2.6. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
1.2.7. Interference and Attenuation
An GS290 may interfere with sensitive laboratory equipment, medical equipment, etc. Interference
from unsuppressed engines or electric motors may cause problems.
1.2.8. Electrostatic Sensitive Devices
ATTENTION
Boards, which contains Electrostatic Sensitive Device(ESD), are indicated by the sign. Following
information is ESD handling: Service personnel should ground themselves by using a wrist strap
when exchange system boards.
When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded. Use a suitable, grounded soldering iron. Keep sensitive parts in these protective
packages until these are used. When returning system boards or parts such as EEPROM to the factory,
use the protective package as described.
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current – Constant Voltage
CLA Cigar Lighter Adapter
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milli-watt
DSP Digital Signal Processing
EEPROM Electrical Erasable Programmable Read-Only Memory
EGPRS Enhanced General Packet Radio Service
EL Electroluminescence
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GPRS General Packet Radio Service
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
LGE LG Electronics
OPLL Offset Phase Locked Loop
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
For the purposes of thismanual,followingabbreviationsapply:
APCAutomatic Power Control BBBasebandBERBitErrorRatioCC-CVConstant Current – ConstantVoltage CLACigar Lighter Adapter DACDigital to Analog ConverterDCSDigitalCommunicationSystemdBmdBrelativeto1milli-wattDSPDigitalSignalProcessingEEPROMElectricalErasableProgrammableRead-OnlyMemoryEGPRSEnhanced General Packet Radio Service ELElectroluminescence ESDElectrostatic Discharge FPCBFlexiblePrintedCircuitBoardGMSKGaussianMinimumShiftKeyingGPIBGeneralPurposeInterfaceBusGPRSGeneralPacketRadioServiceGSMGlobalSystemforMobileCommunicationsIPUIInternationalPortableUserIdentityIFIntermediate Frequency LCDLiquidCrystalDisplayLDOLow Drop Output LEDLightEmittingDiodeLGELG ElectronicsOPLLOffset Phase Locked Loop PAMPower Amplifier ModulePCBPrintedCircuitBoardPGAProgrammable Gain Amplifier PLLPhase Locked Loop PSTNPublicSwitchedTelephoneNetworkRFRadioFrequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC
Real Time Clock
SAW Surface Acoustic Wave
GS290OperationalDescriptionRevisionB
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
DCXO Digitally Controled Crystal Oscillator
WAP Wireless Application Protocol
S-GOLD3TM is a GSM/EDGE single chip mixed signal Baseband IC containing all analog and digital functionality
of a cellular radio. Additionally S-GOLD3TM Provides multimedia extensions such as camera, software MIDI, MP3
sound. It is designed as a single chip solution, integrating the digital and mixed signal portions of the base
band in 0.09um, 1.2V technology.
The chip will fully support the FR, EFR, HR and AMR-NB vocoding.
S-GOLD3
TM
support multi-slot operation modes HSCSD (up to class 10), GPRS for high speed data application
(up to class 12) and EGPRS (up to class 12) without additional external hardware.
3.2.2. Block Description
z Processing core
ARM926EJ-S 32 bit processor core for controller functions. The ARM926EJ-S includes an MMU, and the Jazelle
Java extension for Java acceleration.
- TEAKLite DSP core
z ARM-Memory
- 32k Byte Boot ROM on the AHB
- 96k Byte SRAM on the AHB, flexibly usable as program or data RAM
- 16k Byte Cache for Program (internal)
- 8k Byte tightly coupled memory for Program(internal)
- 8k Byte Cache for Data(internal)
- 8k Byte tightly coupled memory for Data(internal)
z DSP-Memory
- 104K x 16bit Program ROM
- 8k x 16bit Program RAM
- 60k x 16bit Data ROM
- 37k x 16bit Data RAM
- Incremental Redundancy(IR) Memory of 35904 words of 16bit
z Shared Memory Block
1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite.
z Controller Bus system
The processor cores and their peripherals are connected by powerful buses.
Multi-layer AHB for connecting the ARM and the other master capable building blocks with the internal and
external memories and with the peripheral buses.
The clock system allows widely independent selection of frequencies for the essential parts of the S-GOLD3.
Thus power consumption and performance can be optimized for each application.
z Functional Hardware block
- CPU and DSP Timers
- MOVE coprocessor performing motion estimation for video encoding algorithms
(H.263, MPEG-4)
- Programmable PLL with additional phase shifters for system clock generation
- GSM Timer Module that off-loads the CPU from radio channel timing
- GMSK / 8-PSK Modulator according to GSM-standard 05.04 (5/2000)
- GMSK Modulator: gauss-filter with B*T=0.3
- EDGE Modulator: 8PSK-modulation with linearized GMSK-Pulse-Filter
- Hardware accelerators for equalizer and channel decoding.
- Incremental Redundancy memory for EDGE class 12 support
- A5/1, A5/2, A5/3 Cipher unit
- GEA1, GEA2, GEA3 Cipher Unit to support GPRS data transmission
- Advanced static and dynamic power management features including TDMA-Frame
synchronous low power mode and enhanced CPU modes(idle and sleep modes)
- Pulse Number Modulation output for Automatic Frequency Correction(AFC)
- Serial RF Control interface: support of direct conversion RF
- A Universal Serial Interface(USIF) enabling asynchronous (UART) of synchronous (SPI)
serial data transmission
- 3 USIF with autobaud detection, hardware flow control and integrated
- A dedicated Fas IfDA Controller supporting IrDA’s SIR,MIR and FIR standards
(up to 4Mbps)
- I2C-bus interface (e.g. connection to S/M power)
- A fast display interface supporting serial and parallel interconnection
- An ITU-R BT.656 compatible Camera interface.
- Programmable clock output for a camera
- An multimedia/Secure Digital Card Interface (MMCI/SD:SDIO capable)
BBP ADC block is composed of 10 external ADC channel. This block operates charging process and other
related process by reading battery voltage and other analog values.
Table 4. S-Gold3 ADC channel usage
ADC channel
Resource Interconnection Description
M0 BAT_ID Battery temperature measure
M1 RF_TEMP RF block temperature measure
M2 N.C
M3 N.C
M4 N.C
M5N.C
M6 N.C
M7 N.C
M8 VSUPPLY Battery supply voltage measure
M9 N.C
M10 N.C
Resource Name Remark
USIF1
USIF1_TXD TXD Transmit Data
USIF1_RXD RXD Receive Data
USIF1_CTS USB_DP
USIF1_RTS USB_DM USIF2
USIF2_TXD NC NC
USIF2_RXD Other function USIF2_CTS BT_CTS
USIF2_RTS BT_RTS. USIF3
USIF3_TXD BT_TX BT Transmit tx
USIF3_RXD BT_RX BT Receive rx
Over a hundred allowable resources, GS290 is using as follows except dedicated to SIM and Memory. GS290
GPIO(General Purpose Input/Output) Map, describing application, I/O state, and enable level, is shown in below
table
GS290OperationalDescriptionRevisionB
3.2.7. GPIO map
Over a hundred allowable resources,GS290 is using asfollowsexceptdedicatedtoSIMandMemory.GS290GPIO(General Purpose Input/Output) Map, describing application,I/Ostate,andenablelevel,is shown in below table
SM-POWER is a highly integrated Power and Battery Management IC for mobile handsets. It has been specially
designed for usage with S-Gold3. Although optimized for usage with the Infineon S-GOLD baseband device it
is suitable for the S-GOLDlite and the E-GOLD+ baseband devices as well. It also supports the cellular RF
devices like SMARTi-DC, SMARTi-DC+, SMARTi-SD and the Bluemoon Single, Infineon’s single chip solution for
Bluetooth. If used with S-GOLD3 it provides all power supply functions (except for the RF PA) for a complete
advanced GSM Edge smart phone minimizing external device count.
Block Description
• Highly efficient step-down converter for main digital baseband supply including Core, DSP and
memory interface (External Bus Unit).
• Support of S-GOLD standby power-down concept
• Low-drop-out (LDO) regulators for Flash and mobile RAM memory devices
• Voltage independent switching of two SIM cards
• LDO regulators for baseband I/O supply
• LDO regulator for analog mixed-signal section of S-GOLD
• Low-noise LDO regulators for RF devices
• Supply for Bluemoon Single, Infineon’s single chip solution for Bluetooth
• Audio amplifier 8 Ohms for handsfree operation and ringing
• Charge Control for charging Li-Ion/Polymer batteries under software control
• Pre-charge current generator with selectable current level
• RTC regulator with ultra-low quiescent current
• USB interface support for peripheral and mini-host mode
• Backlight LEDs driver with current selection and PWM dimming function
• Two single LED driver outputs for signaling
• Vibrator driver with adjustable voltage
• Fully controlable by software via I2C – Bus
• Temperature and battery voltage sensors
• Interrupt channels for peripherals
• System debug mode
• VQFN 48 package with heat sink and non-protruding leads
– SDBB has high efficiency up to 95% and also a power save mode.
– Memory Interface is directly supported by the SDBB
– SDBB can also act as main supply voltage for E-GOLD+ or S-GOLDlite baseband devices.
– For S-GOLD two linear regulators for DSP and Core are cascaded after the SDBB.
SM-POWER supports the standby power-down concept of S-GOLD by temporarily switching off the linear
regulator for the DSP during mobile standby whenever this subsystem is not used. In this phase the ARM
controller and most peripherals including parts of the on-chip SRAM are kept powered-up with power being
supplied by the other linear regulator.
SM-POWER includes a fully differential audio amplifier able to drive loads down to a nominal value of 8 Ohm for
usage in hands-free phones and for ringing
– 450 mW maximum output power
– adjustable gain
– mute switch SM-POWER also integrates a charging function for Li-Ion, Li-Polymer batteries
– click and pop -protection SM-POWER also integrates a charging function for Li-Ion, Li-Polymer batteries
– Precharge current source with two current levels
– Constant current / constant voltage charging with 3 different termination voltages
– Programable charge current limitation for use with different batteries
– Freely programable pulse charging to reduce the thermal power dissipation in the constant voltage
charging phase
– Top-off charge current sensing SM-POWER completes the USB interface of S-GOLD
– Regulated voltage for S-GOLD USB interface including reverse current and overvoltage protection
– Switch to supply USB pull-up resistor
– Mini-host pull down resistor functionality
– Charge pump with internal switching capacitor for USB host VBUS supply voltage SM-POWER fully supports
LED and Vibra Motor functionality
– no external components needed
– driver for backlight LEDs adjustable in steps up to 140mA and with soft turn on and off by PWM dimming
– two driver outputs for single LEDs for precharge indication and signaling with i.e. change of colour
The bq25040 has a single power output that charges the battery. A system load can be placed in parallel with
the battery.The charge current is programmed using the ISET and EN/SET inputs. The charge current is
programmable to USB100, USB500 or a user programmed charge current up to 1.2A. Additionally, a 4.9V +/-3%
50mA LDO is integrated into the IC for supplying low power external circuitry. The one-wire interface (EN/SET)
is available to place the bq25040 into Test Jig Mode. In Test Jig Mode, the output is regulated at 4.2V and can
be used without a battery.The bq25040 has a single power output that charges the battery.. Either a 1-cell
Li-Ion or Li-Ion-Polymer battery with 4.1, 4.2 or 4.4 Volts may be used.
4.2V~3.74V 3.73V~3.65V 3.65V~3.59V 3.59V~3.35V
Figure 5 Battery Block Indication
1.Charging method : CC-CV
2.Charger detect voltage : 4.8 V
3.Charging time : 2h
4.Charging current : 645 mA
5.CV voltage : 4.2 V
6.Cutoff current : 105 mA
7.Full charge indication current (icon stop current) : 110 mA
Input ON is a power-on input for SM-POWER with 2 active high levels (see Figure 6). It might be triggered by a
push button or by the RTCOUT output of the S-GOLD device as well. To detect if the push-button is pressed
during system operation the logical level at pin ON or its change (if Bit 1 EION in INTCTRL2 is asserted) is
recorded in bit LON of the ISF register. If the high level of voltage at pin ON does not reach VIHdet (Vbat-0.8 ~
Vbat-0.3) the above-mentioned bit won’t be set.
To support Remote power on function for factory mass production, applied an analog switch as following
figure. As monitoring the RPWRON and Key matrix KP_OUT(2) & KP_IN (6), GS290 system recognize whether
remote power on or End-key pushed
GS290OperationalDescriptionRevisionB
Figure 7 Remote power on and End-key power on circuit
2Gbit NAND & 1Gbit DDRSDRAM employed on GS290 with 8 & 16 bit parallel data bus thru ADD(0) ~ ADD(29).
The 512Mbit Nand Flash memory with DDRAM stacked device family offers multiple high-performance
solutions.
n
0
15
31
C
041Cn
0
1
n01441C
641Cn01
K3.3501R
TP103
u1.0911C
SD_1V8
401RK01
u1.0901C
921Cu1.0
SD_1V8
SD_1V8
TP106
TP108
TP109
TP112
TP104
8
1
1Cn0
1
u1.0141C
541Cu1.0
631Cu1.0
n01731C
K522H1HACB-B060
U101
21T
11T
01T3T2T
1T
21R11R
01R
3R2R1R
21P
1
1P
3P2P1P
2N
2M
2L
01K9K8K
5K4K2K
1
1J
01J9J8J
7J
6J5J4J
3J
P8D5
P4D6
E6
P6F6
C8F5
C4E5
D7
P5C7
C6
P9L7
P7L6
H10K7
G2K6
C9N9
C5M9
L9
H2N8
M8
N3L8
E3N7
K3M7
L3N6
F3M6
M3N5
G3M5
L5
D11N4
E11M4
F11L4
G11E9
K11E7
L11F7
M11G5
N11G7
C10D9
D10D8
E10E8
F10F8
L10G8
M10G4
N10F4
P10E4
D4
2J
9H8H7H6H
5
H
4
H
3H
01G
9G
6G
9F
2F
11
H
2E
3D
2D
1
D
2
1
C
1
1C3C
2C1
C
21B11B
01B
3B2B1B
21A
11A
0
1A
3A
2A
1A
1CN
2CN
3
C
N
4CN
5CN
6CN
7CN
8CN
9CN
01CN
11CN
2
1
C
N
3
1
C
N
41CN
51CN
61CN
7
1
C
N
81CN
91CN
0
2
C
N
1
2
C
N
22CN
32
C
N
4
2
C
N
5
2
C
N
62CN
72CN
8
2
C
N
92CN
0
3
C
N
13CN
23CN
33
C
N
43
C
N
53CN
A0
A1I_O0
A2I_O1
A3I_O2
A4I_O3
A5I_O4
A6I_O5
A7I_O6
A8I_O7
A9I_O8
A10I_O9
A11I_O10
A12I_O11
A13I_O12
DQ0I_O13
DQ1I_O14
DQ2I_O15
DQ3
DQ4_CE
DQ5_WEN
DQ6_RE
DQ7ALE
DQ8CLE
DQ9R__B
DQ10_WP
DQ11
DQ12VCCN1
DQ13
DQ14VSS1
DQ15VSS2
LDQMVSS3
UDQMVSS4
LDQSVSS5
UDQSVSS6
_CLK
CLKVSSQ
CKE
BA0VDD1
BA1VDD2
_RASVDD3
_CAS
_WEDVDDQ1
_CSVDDQ2
63CN
73CN
8
3
C
N
93CN
04CN
14CN
24CN
3
4
C
N
44CN
54CN
64CN
7
4
C
N
84
C
N
94CN
05CN
15CN
25
C
N
35CN
45CN
5
5
C
N
65
C
N
75CN
85
C
N
9
5
C
N
06
C
N
16CN
26CN
3
6
C
N
46CN
56
C
N
66CN
76CN
8
6
C
N
96
C
N
07CN
TP102
TP107
ADD[29]
DATA[10]
DATA[15]
DATA[13]
DATA[12]
DATA[11]
DATA[9]
DATA[8]
DATA[2]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[1]
DATA[0]
UDQS
LDQS
ADD[28]
ADD[27]
ADD[26]
SDCLKI
_WR
_WR
SDCLKO
_RD
_RAM_CS
CKE
_CAS
FCDP
_BC1
_BC0
_NAND_CS
ADD[25]
ADD[4]
ADD[3]
ADD[24]
ADD[23]
ADD[22]
ADD[21]
ADD[20]
ADD[2]
ADD[19]
ADD[18]
ADD[17]
ADD[17]
ADD[16]
ADD[16]
ADD[9]
ADD[8]
ADD[13]
ADD[7]
ADD[12]
ADD[6]
ADD[11]
ADD[5]
ADD[10]
ADD[1]
ADD[0]
_RAS
ADD[15]
ADD[14]
DATA[14]
BA0
BA1
_WP
ADD[16:29]
A
DD[0:15]
DATA[0:15]
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
Large Block Memory
GS290OperationalDescriptionRevisionB
3.6. Memory
2Gbit NAND & 1Gbit DDRSDRAM employed on GS290 with8 & 16 bit parallel data bus thru ADD(0) ~ ADD(29). The 512Mbit Nand Flash memorywithDDRAMstacked devicefamilyoffersmultiplehigh-performancesolutions.
The keypad interface is a peripheral which can be used for scanning keypads up to 3 rows (outputs from Port
Control Logic) and 2columns (inputs to PCL). The number of rows and columns depend on settings of the PCL.
There are 2 snow white color LEDs on Key FPCB for keypad illumination. Keypad Back-light is controlled by
SM-Power Flash LED port which has constant current control function. The whole configuration of the
SM-POWER Flash LED drivers is shown in below Figure11
Figure 12 LCD Back light unit and Flash LED charge pump IC
The AAT3169 is a write-only single wire interface. It provides access to up to 32 registers that control device
functionality.In this system, two sets of pulse trains are transmitted via the SPIF pin. The first pulse set is used to
set the desired address. After the bus is held high for the address hold period, the next pulse set is used to write
the data value. After the data pulses are transmitted the bus is held high again for the data hold period to
signify the data write is complete. At this point the slave device latches the data into the address that was
selected by the first set of pulses. The protocol for using this interface is described in the following subsection.
GS290OperationalDescriptionRevisionB
3.10. LCD back-light illumination
Figure12LCDBacklightunitandFlashLEDchargepumpIC
The AAT3169 isa write-only single wireinterface. It provides access to up to 32 registers that control device functionality.In this system, two sets of pulse trains are transmittedviatheSPIFpin.Thefirstpulsesetisusedtoset the desiredaddress. After the bus isheldhigh for the address hold period, the nextpulse set is used to write thedatavalue.Afterthedatapulsesare transmitted the bus is held highagain for the data hold period to signify the data write is complete. Atthispointtheslavedevicelatchesthe data into the address thatwas selected bythe first set of pulses. The protocol for using this interface is described in the following subsection.
Audio amplifier sub system IC is an audio power amplifier capable of delivering 1.25W of continuous average
power into a mono 8Ω load, 42mW per channel of continuous average power into stereo 32Ω single-ended (SE)
loads. The LM49151 features digital volume control and ten distinct output modes. The digital volume control,
output modes (mono/SE/OCL) are programmed through a two-wire I2C interface that allows flexibility in
routing and mixing audio channels.
• +6 dBm RF Transmit power with level control from on-chip 6-bit DAC over a dynamic range > 30dB
• Class 1 and Class 2 support without the need for an external power amplifier or TX/RX switch.
Bluetooth Receiver
• Integrated channel filters
• Digital demodulator for improved sensitivity and co-channel rejection
• Real time digitized RSSI available on HCI interface
• Fast AGC for enhanced dynamic range
• Channel classification for AFH
Synthesiser
• Fully integrated synthesizer requires no external VCO varactor diode, resonator or loop filter
• Compatible with crystals between 7.5 and 40MHz(in multiples of 250KHz) or an external clock
Audio
• Single-ended stereo analogue output
• 16-bit 48 kHz digital audio bit stream output
Baseband and Software
• Internal 48Kbyte RAM, allows full speed data transfer, mixed voice and data, and full piconet operation,
including all medium rate packet types
• Logic for forward error correction, header error control, access code correlation. CRC, demodulation,
encryption bit stream generation, whitening and transmit pulse shaping. Supports all Bluetooth v 2.0 + EDR
features incl. ESCO and AFH
• Transcoders for A-law, u-law and linear voice from host and A-law, u-law and CVSD voice over air
Physical Interfaces
• Synchronous serial interface up to 4Mbits/s for system debugging
• UART interface with programmable baud rate up to 4Mbits/s with an optional bypass mode
The MAX14526 is a complete solution for multiplexing USB, UART and audio on a single mini/micro USB
connector. It contains an internal method for determining the device connected and uses an I2C bus for
control.
The switch will multiplex multiple inputs (USB, UART,Microphone, Stereo and Audio) on one mini/microUSB
connector. The USB and UART inputs support Hi-Speed USB and the audio inputs feature negative rail signal
operation allowing simple dc coupled headset speakers. The VB connection is protected against faults up to 28
volts. There is an internal device detection method which uses the USB ID signal pin and the voltage on VBUS.
Each accessory will have a unique detection based on resistor values and voltage on VBUS. The host
microprocessor uses I2C to control the switch position as well as read the results of the accessory detection.
The MAX14526 will also detect USB chargers including dedicated chargers (D+/D- shorted) and high power
host/hub chargers.
The RF transceiver (PMB 6272 SMARTi-PM) is an integrated single chip, quad-band transceiver for
GSM850/GSM900/GSM1800/GSM1900 designed for voice and data transfer applications. The transceiver
provides an analog I/Q baseband interface and consists of a direct conversion receiver and a quad-band polar
transmitter for GSM and EDGE with integrated PGA functionality. Further on a completely integrated
SD-synthesizer with HSCSD and GPRS/EDGE capability, a digitally controlled reference oscillator with three
outputs, a fully integrated quad-band RF oscillator and a three wire bus interface with all necessary control
circuits complete the transceiver.
The constant gain direct conversion receiver contains all active circuits for a complete receiver chain for
GSM/GPRS/EDGE (see Figure 25). The GSM850/900/DCS1800/ PCS1900 LNAs with balanced inputs are fully
integrated. No inter-stage filtering is needed. The orthogonal LO signals are generated by a divider-by-four for
GSM850/900 band and a divider-by-two for the DCS1800/PCS1900 band. Down conversion to baseband
domain is performed by low/high band quadrature direct down conversion mixers. The baseband chain
contains a LNB (low noise buffer), channel filter, output buffer and DC-offset compensation. The 3rd order low
pass filter is fully integrated and provides sufficient suppression of blocking signals as well as adjacent channel
interferers and avoids anti-aliasing through the baseband ADC. The receive path is fully differential to suppress
on-chip interferences. Several gain steps are implemented to cope with the dynamic range of the input signals.
Depending on the baseband ADC dynamic range, single- or multiple gain step switching schemes are
applicable. Furthermore an automatic DC-offset compensation can be used (depending on the gain setting) to
reduce the DC-offset at baseband-output. A programmable gain correction can be applied to correct for front
end- and receiver gain tolerances.
The GMSK transmitter supports power class 4 for GSM850 and GSM900 as well as power class 1 for DCS1800
and PCS1900. The digital transmitter architecture is based on a very low power fractional-N Sigma-Delta
synthesizer without any external components (see Figure39). The analog I/Q modulation data from the
baseband is converted to digital, filtered and transformed to polar coordinates. The phase/frequency signal is
further on processed by the Sigma-Delta modulation loop. The output of its associated VCO is divided by four
or two, respectively, and connected via an output buffer to the appropriate single ended output pin. This
configuration ensures minimum noise level. The 8PSK transmitter supports power class E2 for GSM850 and
GSM900 as well as for DCS1800 and PCS1900. The digital transmitter architecture is based on a polar
modulation architecture, where the analog modulation data (rectangular I/Q coordinates) is converted to
digital data stream and is subsequently transformed to polar coordinates by means of a CORDIC algorithm. The
resulting amplitude information is fed into a digital multiplier for power ramping and level control. The ready
processed amplitude signal is applied to a DAC followed by a low pass filter which reconstructs the analog
amplitude information. The phase signal from the CORDIC is applied to the Sigma-Delta fractional-N
modulation loop. The divided output of its associated VCO is fed to a highly linear amplitude modulator,
recombining amplitude and phase information. The output of the amplitude modulator is connected to a
single ended output RF PGA for digitally setting the wanted transmit power. The PA interface of SMARTi-PM
supports direct control of standard dual mode power amplifiers (PA’s) which usually have a power control input
VAPC and an optional bias
Figure 26 Transmitter part block diagram
control pin VBIAS for efficiency enhancement. In GMSK mode, the PA is in saturated high efficiency mode and is
controlled via its VAPC pin directly by the baseband ramping DAC. In this way both up- / down-ramping and
output power level are set. In 8PSK mode, the ramping functionality is assured by an on-chip ramping
generator, whereas output power is controlled by the PGA’s as described above.
The transceiver contains a fractional-N sigma-delta synthesizer for the frequency synthesis in the RX operation
mode. For TX operation mode the fractional-N sigma-delta synthesizer is used as Sigma-Delta modulation loop
to process the phase/frequency signal. The 26MHz reference signal is provided by the internal crystal oscillator.
This frequency serves as comparison frequency of the phase detector and as clock frequency for all digital
circuitry.The divider in the feedback path of the synthesizer is carried out as a multi-modulus divider (MMD).
The loop filter is fully integrated and the loop bandwidth is about 100 kHz to allow the transfer of the phase
modulation. The loop bandwidth is automatically adjusted prior to each slot (OLGA). To overcome the
statistical spread of the loop filter element values an automatic loop filter adjustment (ALFA) is performed
before each synthesizer startup. The fully integrated quad-band VCO is designed for the four GSM bands (850,
900, 1800, 1900 MHz) and operates at double or four times transmit or receive frequency. To cover the wide
frequency range the VCO is automatically aligned by a binary automatic band selection (BABS) before each
synthesizer startup.
Implemented in the S-Gold3 (FL500) are two outputs which are VC1, VC2 for direct control of front end modules
with two logic input pins to select RX and TX mode as well as low and high band operation..
Table 8 FEM Control Logic
22p
C524
22p
R501
KMS-518_P
SW500
G1
A
C
G2
100n
L501
0.5p
C510
C539
DNI
100R502
100R504
C503
47p
C508
47p
ANT500
DNI
C519
LMSP43NA-782
FL500
0
2
9131
11
81
518417
216
9
5
4
013
612
1
17
ANT
1XR
0
58
MS
G
2X
R
05
8
MSG
1CV
1XR00
9
MSG2CV
2XR009MSG
1X
R0
0
81
MS
G1DNG
2X
R0
08
1
MSG
2DNG
1X
R
009
1
MSG3DN
G
2X
R
009
1
MSG4
D
N
G
5DNG
XT0091_0081MSG
X
T
0
09_
0
58MSG1CN
2
C
N
0
R510
VC1
VC2
L
L
GSM 1800 / 1900_ RX
GSM850 / 900_RX
VC2 (FE2)
H
H
L
GSM850 / 900_TX
LL
L
GSM 1800 / 1900_ TX
VC1 (FE1)
CI:$0.05(CMOS->PIN)
GS290OperationalDescriptionRevisionB
3.20. Front End Module control
Implemented inthe S-Gold3 (FL500) are two outputs which are VC1, VC2 for direct control offront end modules withtwologicinputpinstoselectRXandTXmode as well as low and high band operation..
The SKY77344 Power Amplifier Module(PAM) is designed in a compact from fact for quad-band cellular
handsets comprising GSM850/900,DCS1800,PCS1900,supporting GMSK and linear EDGE modulation. Class12
General Packet Radio Service(GPRS) multi-slot operation is also supported.
The module consists of a GSM850/900 PA block and a DCS1800/PCS1900 PA block,impedance matching
circuitry for 50ohm input and output impedances, and a Multi-function Power Amplifier Control(MFC) block. A
custom CMOS integrated circuit provides the internal MFC function and interface circuitry.
Two separate Heterojunction Bipolar Transistor(HBT) PA blocks are fabricated onto InGaP die; one supports the
GSM850/900 bands, the other supports the DCS1800 and PCS1900 bands. Both PA blocks share common
power supply pins to distribute current. The InGaP die, the silicon die, nad the passive components are
mounted on a multi layer laminate substrate. The assembly is encapsulated with plastic overmold.
RF input and output ports are internally matched to 50ohm to reduce the number of external components
Extremely low leakage current(2.5uA) maximizes handset standby time. Band select(BS) circuitry select GSM
transmit frequency band(logic0) and DCS/PCS transmit frequency(logic1). MODE circuitry selects GMSK
modulation (logic0) or EDGE modulation(logic1). VRAMP controls the output power for GMSK modulation and
provides bias optimization for EDGE modulation depending on the state of MODE control.
The integrated multi-function(MFC) provides envelope amplitude control in GMSK mode, reducing sensitivity
to input drive, temp, power supply, and process variation. In EDGE mode, the MFC configures the PA for fixed
gain, and provides the ability to optimize the PA bias operation at different power levels, This circuitry regulates
PA bias conditions, reducing sensitivity to temp., power supply, and process variation. The Enable input
signal(pin8) provides a standby state to minimize battery drain..