This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services. System
users are responsible for the security of own system. There are may be risks of toll fraud associated with your
telecommunications system. System users are responsible for programming and configuring the equipment
to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the
above case but will prevent unauthorized use of common-carrier telecommunication service of facilities
accessed through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly causing
harm or interruption in service to the telephone network, it should disconnect telephone service until repair
can be done. A telephone company may temporarily disconnect service as long as repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the this phone or compatibility with the network,
the telephone company is required to give advanced written notice to the user, allowing the user to take
appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its authorized agent.
The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore,
note that unauthorized alternations or repair may affect the regulatory status of the system and may void
any remaining warranty.
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information such
as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated
by the sign. Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system
boards.
• When repairs are made to a system board, they should spread the floor with anti-static mat
which is also grounded.
• Use a suitable, grounded soldering iron.
• Keep sensitive parts in these protective packages until these are used.
• When returning system boards or parts like EEPROM to the factory, use the protective
BandGSM Q uad B and(850/ 9 00/ 1800/1900), UM TS(1900/ 850), Bl uet ooth
TypeSide Slide ty pe
Dimensi on105.5 × 53. 5 × 15. 8 m m
W ei ght110g (wit h s tandard batt ery)
Power950mAh Li -ion
Talk TimeOver 180 M i n : 950m Ah Li -i on2G
Stand-by TimeOver 250 hours : 950m Ah Li -i on
AntennaIntenna Type
LCD(Main)2.8" (240x400), TFT Color LCD
Back Ligh tYes
Back Ligh t col orW hi te
VibratorYes
SpeakerYes
MICSM T type
Receiv erYes
Earphone Jac kYes
SIM S o c ketYes(S IM Bl oc k Type) : 3. 0V & 1.8V
Vol um e K e yPush Type(+, -)
Camera K eyPush Type
I/O Connec t5Pi n M i c ro US B
Ear-M i c (St ereo Earphone) Travel A dapt o r 950mAh Li -
BER0.1%@-70dBm
BER ≤ 0.1% @ (Low,M i d, Hi gh Frequenc y)
2405MHz, 2441M Hz , 2477MHz
Interferenc e Ratio
Co-Channel interference, C/ I c o-c hannel 11dB
Adjacent(1MHz)interference, C/I 1MHz 0dB
Adjacent(2MHz)interference, C/I 2MHz -30dB
Adjacent(≥3MHz)i nt erference, C/ I ≥3MHz -40dB
Adjacent(≥3MHz)interferenc e to i n ba nd -9dB
mirror frequency, C/I im age ± 1M Hz -20 dB
BER ≤ 0.1% @want ed s i gnal -67dB m
interfering Si gnal F requenc y Power Level
30MHz~2000MHz -10dBm
2000MHz~ 2400M Hz -27dBm
5Intermodluat i on P erformanc e
6Max i mum Input L evel
2500MHz~ 3000M Hz -27dBm
3000MHz~12.75GHz -10dBm
BER ≤ 0.1% @want ed s i gnal -64dB m
st atic s i nwave signal at f1= -39dBm
a BT modulated signal f2=-39dB m (pay load PRBS 15)
- Access Central Processing Unit (CPU) subsystem – ARM926, Joint Test Action Group (JTAG),
Embedded Trace Module (ETM), Instruction and Data (I&D)-cache, and I&D-TCM
- Access peripheral subsystems – Subscriber Identity Module (SIM) interface, IrDA®, Universal Serial
Bus (USB), Universal Asynchronous Receiver/Transmitter (UART), and so on
- Digital Signal Processor (DSP) subsystem – CEVA-X1620, JTAG, Static Random Access Memory
(SRAM), and Program Data Read Only Memory (PDROM)
- Application CPU subsystem – containing ARM926, JTAG, ETM, I&D-cache, and I&D-TCM
- Application peripheral subsystems – I2C™, keypad, UART, and so on
- Graphics subsystem – XGAM subsystem
- Audio Processing Execution (APEX) and video encoder subsystems
In addition to the two subsystems above, there is also a test block, chip control block, and
a pad multiplexing block residing at the top level
y DSP
- The Digital Signal Processor Subsystem (DSPSUB) includes a DSP megacell, which
contains the DSP CPU together with a tightly coupled memory. The DSP is the Ceva-X
1620 core with a 64 kB instruction RAM and a 64 kB data RAM. It also contains debug
logic and interfaces. In addition to the megacell, the DSPSUB includes external memories,
peripheral units, and interfaces. The DSP megacell is clocked at 208 MHz.
- The DSPSUB includes an AHB master and an AHB slave interface. The AHB master
provides a direct access to the Internal Random Access Memory (IRAM) in the EGG core
through the AHB. The AHB slave interface allows the CPU and the DMA to access in the
program and data RAM residing in the DSPSUB.
y WCDMA subsystem
- The digital baseband controller WCDMA subsystem incorporate a WCDMA modem
- An interface to the WCMDA together with memory control and an internal single port
RAM. The WCDMA subsystem has three AHB slave interfaces.
- The Ericsson DB 3150 also includes HSDPA class 6 functionality.
- The WCDMA subsystem is handled and provided by Ericsson.
y XGAM subsystem
- The XGAM subsystem is a graphics acceleration module that provides hardware
support in the creation of visual imagery and the transfer of this data to a display.
The XGAM also provides support for connecting a Camera module. The visual data
could be graphics, still images, or video.
- The XGAM subsystem is handled and provided by Ericsson.
y Operation and Services
- IC™ Interface
-SIM Interfaces
- General Purpose I/O (GPIO) Interface
- External Memory Interface that supports NAND, NOR, PSRAM, SDRAM,
The digital baseband controller includes an access CPU subsystem, which includes the submodules
described below.
• 32 KiB I-cache
• 16 KiB D-cache
• Page table
• Memory Management Unit (MMU)
•JTAG
•ETM9
• 26 KiB I-TCM
•8 KiBD-TCM
- Application CPU subsystem
The digital baseband controller includes an Application CPU subsystem, which includes the
submodules described below.
• 32 KiB I-cache
• 16 KiB D-cache
• Page table
• MMU
•JTAG
•ETM9
•8 KiBI-TCM
•8 KiBD-TCM
C. Peripheral Hardware Subsystem
The digital baseband controller includes hardware that supports mobile terminal peripherals
such as a MMC, SD, UART, I2C, USB, keypad, and infrared. Collectively, this hardware
comprises the Peripheral subsystem.
The functional blocks of the Peripheral subsystem connect to the peripheral bus through four
separate bridges, which provide a simple interface to support different timing and memory
access arrangements.
D. DSP Hardware Subsystem
The Digital Signal Processor Subsystem (DSPSUB) includes a DSP megacell, which contains the DSP
CPU together with a tightly coupled memory. The DSP is the Ceva-X 1620 core with a 64 kB
instruction RAM and a 64 kB data RAM. It also contains debug logic and interfaces. In addition to the
megacell, the DSPSUB includes external memories, peripheral units, and interfaces. The DSP
megacell is clocked at 208 MHz.
The DSPSUB includes an AHB master and an AHB slave interface. The AHB master provides a direct
access to the Internal Random Access Memory (IRAM) in the EGG core through the AHB. The AHB
slave interface allows the CPU and the DMA to access in the program and data RAM residing in the
DSPSUB.
E. XGAM Subsystem
The XGAM subsystem is a graphics acceleration module that provides hardware support in the
creation of visual imagery and the transfer of this data to a display. The XGAM also provides support
for connecting a Camera module. The visual data could be graphics, still images, or video.
The XGAM subsystem is handled and provided by Ericsson.
F. System Control Subsystem
The SYSCON resides at the top level of the circuit architecture and is responsible for clock
generation and clock and reset distribution within the digital baseband controller, as well as to
external devices.
The block is a slave peripheral under control of the ARM processor. The programming of the
SYSCON controls the fundamental modes of operation within the digital baseband controller.
Individual blocks can also be reset and their clocks held inactive by accessing the appropriate
control registers.
3.1.4 RF Interface
A. DB3200 Interface
DB3200 controls GSM RF part using these signals through GSM RF chip-RF3300.
y RF_DATA_A
y RF_DATA_B
y RF_DATA_C
y TX_ADC_STRB
TX_ADC_STRB
RF_DATA_STRB
Figure 3-1- 5. Schematic of DB3200 RF Interface
B. WCDMA Radio Link Interface
y RF_WCDMA_PA_0_EN
y RF_WCDMA_PA_1_EN
y RF_WCDMA_DCDC_EN
y RF_WCDMA_PWRDET_E
The USB block supports the implementation of a “High-speed" device fully compliant to USB 2.0
standard. It provides an interface between the CPU (embedded local host) and the USB wire, and
handles USB transactions with minimal CPU intervention.
The USB specification allows up to 15 pairs of endpoints. Data for each endpoint is buffered in
RAM within the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO
register access. High-speed (high throughput) endpoints can use DMA while slower endpoints can
use FIFO register access.
The USB block can request up to six DMA channels, three for IN endpoints and three for OUT
endpoints.
There is a magnet to detect the slide module status, up or down.
If a magnet is close to the hall-effect switch U604, the voltage at Pin 1 of U604 goes to 0V. Otherwise
1.8V.
This SLIDE_DET signal is delivered to DB3200 ACC_GP_FLIPSENSE.