LG DRN-8060B Service Manual

3

INTRODUCTION

GENERAL FEATURE

SPECIFICATIONS

1. SUPPORTED SYSTEM

• IBM Compatible Pentium 133MHz or Above • MPEG II Board or Software MPEG II Program

2. SUPPORTED OS

3. GENERAL PERFORMANCE

• Rotational Speed........................................................DVD : 3.3X~8X (CAV) Approx. 4,800 rpm

(single layer - Press)

2.0X~4X (CAV) Approx. 3,800 rpm(DVD-R)

2.0X~4X (CAV) Approx. 4,200 rpm(dual layer)

CD-ROM : 10X~24X (CAV) Approx. 4,650~5,000rpm
CD-RW, V-CD, Audio CD : 6X~12X (CAV) Approx. 3,200rpm

• Data Transfer Rate

* Sustained Data Transfer Rate................................DVD(Outer side) : Approx. 10,800kbytes/sec

DVD (Inner side) : Approx. 4,500kbytes/sec
CD (Outer side) : Approx. 3,600kbytes/sec
CD (Inner side) : Approx. 1,550kbytes/sec

* Burst (ATAPI) .........................................................16.67 Mbytes/sec (PIO Mode 4)

16.67 Mbytes/sec (Muliword DMA Mode 2)

33.3 Mbytes/sec (Ultra DMA)

• Access Time (Including Latency)

* Random Access*1..................................................DVD : 150ms Typical (8X)

CD : 130ms Typical (24X)

* Full Access (First to Last Block)*2..........................DVD : 240ms Typical (8X)

CD : 220ms Typical (24X)

Notes :
*1 : Average Random Seek time is the typical value of more than 100times including latency and error

correction time.

*2 : Average Seek time is the typical value of more than 100times including latency and error correction time.

Test Disc : a CD : A-BEX TCDR-701

b DVD : A-BEX TDV-520 or TEAC MDVD411/MDVD-191or TDR-820

• Data Buffer Capacity .................................................. 512Kbytes

• ATAPI interface

• Ultra Slim type DVD-ROM drive. (Height : 12.7 mm)

• Ability to read single sided, single layer,
or dual layer DVD media

• ATA4, Ultra DMA33 support

• DVD-5, DVD-9, DVD-10 Capable

• Sustained Transfer Rate 10,800 KB/sec (Max.)
DVD media & 3600 KB/sec (Max.) CD-ROM Media

• (150)ms Average Access time in DVD mode

• (130)ms Average Access time in CD mode

• Support 8x(Max.) Rotational Modes in DVD mode

• Support 24x(Max.) Rotational Modes in CD mode

• DVD-R, CD-R, CD-RW read capability

• Drawer load

• MPC level 3 compatible

• Photo CD : Single and Multisession support

• XA ready

• Subcode Q

• Red Book Audio

• Analog Line out

• Digital Audio through Atapi interface

• Energy conservation modes

• Horizontal/Vertical operation

• MS-DOS (Ver 3.1 or Higher)

• Windows 3.1/95/98 Higher

• Windows NT (Ver 3.5, Ver 4.0) or Higher

• OS/2 Warp (Ver 3.0 & 4.0) or Higher

This service manual provides a variety of service
information. It contains the mechanical structure
of the DVD-ROM Drive together with mechanical
adjustments and the electronic circuits in

schematic diagram. This DVD-ROM Drive was
manufactured and assembled under our strict
quality control standards and meets or exceeds
industry specifications and standards.

4

4. POWER REQUIREMENTS

• Voltage .......................................................................+5V DC +5%

• Ripple .........................................................................+5V : 100mVp-p

• Seek ..........................................................................1300mA Max, 960mA Typical

• Normal Read ..............................................................1,000mA Max, 880mA Typical

• Standby & sleep .........................................................40mA Max

5. AUDIO PERFORMANCE

• Frequency Response .................................................20Hz~20KHz ( +3dB)

• S/N Ratio (IHF-A+20kHZ LPF) ...................................80 dB (Typical at 1 KHz 0dB)

75 dB (Limit at 1 KHz 0dB)

• T.H.D. (IHF-A+20kHZ LPF) ........................................0.05% (Typical at 1 KHz 0dB)

0.15% (Limit at 1 KHz 0dB)

• Channel Separation (IHF-A+20kHZ LPF)...................75 dB (Typical)

70 dB (Limit)

• Output Level (1kHz 0dB) 47KΩ Load.........................1.0Vrms +20%

DISASSEMBLY

5

1. CABINET

A. Release 3 screws (A).
B. Lift up the Cabinet in the direction of arrow (1).

(See Fig.1)

2. MAIN CIRCUIT BOARD

A. Inset and press a rod in the Emergency Eject Hole and

then the CD Tray will open in the direction of arrow (2).
B. Release 2 screws (B).
C. Remove the Main Circuit Board.

3. FRONT PANEL

A. Release 2 screws (C) and remove the Front Panel.
B. At this time, be careful not to damage the 2 hooks (a) of

the it. (See fig.3)

C. Release 3 screws (D) and remove the Cover Bottom (3).

4. BASE PICK-UP

A. Remove the Base Pick-up (4).

(1)

(A)

(A)

(A)

CABINET

2 HOOKS

HOOK (a)

FRONT PANEL

COVER BOTTOM

BASE PICK-UP

MAIN CIRCUIT BOARD

Emergency Eject Hole

Fig.1

Fig.3

Fig.2

Fig.4

(B)

(B)

(2)

(3)

(D)

(D)

(C)

(D)

(C)

(2)

(4)

15

PN201

14

15

R213

C233

C234

Q202

C203

C207

CD LD

CD PD

DVD LD

IC201 SSI3723

DVD PD

Q201

R202

Vcc

5V

Vcc

5V

10

9

DVD­ MD

DVD­ LD

LD

LD

CD­ MD

CD­ LD

DVD-LD(LASER DIODE)

CD-LD(LASER DIODE)

PICK-UP Unit

Monitor
Diode

Monitor
Diode

22

24

21

23

1-2. APC Circuit Operation

It drives the LD to the constant current and adjusts the LD input current , so that the output current is
constant.
IC201 (SSI3723) Pin , : PD IN, Monitor Input of Laser diode APC
IC201 (SSI3723) Pin , : LD OUT, External Current Driver Control output of the LD (Laser Diode)

The detect current from the monitor diode converts to the I/V (Current/Voltage) at the external resistor.
Beforehand, it adjusts a fixed level over for a standard GND.
If this voltage inputs to the PD IN (IC201 Pin 23, 24), it is amplified about 36.4 times (about 31.2dB).
So this voltage outputs from the LD OUT (IC201 Pin 21, 22).

The LD driving element (Q201/Q202) uses the TR more than 200hfe, and controls LD OUT (IC201 Pin 21,

22) connected to the base of Q201/Q202.
The APC control for the each DVD/CD sets Register of the IC201 (SSI3723) according to Disc in the
µ-COM.

DESCRIPTION OF CIRCUIT

1. APC (Automatic Power Control) Circuit

1-1. APC Circuit Constitution

23

24

21

22

16

E

A

B

C

F

F

D
C
B

A

E

1
13
11

16
17

19
20

1

3

4

12

1

18

CD (A, B, C)

DVD RF

17
18

64

5

6

9

10

11 12

13

14

15

16

AMP

AMP

MUX

ATT

AGC

AGC

40

GCA

GCA

SUM
AMP

BUFF

MUX

MUX

FE

TE

RF AC

To IC301 3

To IC301

143

To IC301 13
To IC401 117

GCA

39

57

EQ

Phase
Detector

EQ

DVD (A, B, C, D)

DVD
(A

2

, B2, C2, D2)

CD (E, F)

Pick-up Unit

PN201

IC201

SSI3723

4

4

RF DC

RF SIN

63

2. RF Amplifier Circuit

2-1. RF AMP Constitution

17

FOCUS & TRACKING SERVO PROCESS

SLED(Feed) SERVO PROCESS

F

F

D

C

B
A

B

A

E

E

C

Pick - Up

IC201

RF AMP
SSI3723

5

CD

E-F

(A. B. C. E. F)

6

DVD (A. B. C. D.)

TE/
DPD TE

SELECTOR

FE

Generating

DPD TE

Generating

TE

FOCUS
ERROR
DETECTOR

FOCUS &
TRACKING

ACTUATOR

IC601

DRIVE
BA5918

IC301

CD/DVD SERVO & DSP
CXD3011R

F+ F-T+ T-

LEVEL SHIFT

LEVEL SHIFT

FAO

TAO

D/A

DIGITAL

EQUALIZER

(AUTO ADJUSTMENT
CIRCUIT)

SLED

Control

Signal

A/D

TE FE

TE

SAO

Q502/Q503

5V

SLED MOTOR

Photo Interrupter

M

PHO - C

PHO - Vcc

FEED. MOTOR+

FEED. MOTOR-

LEVEL SHIFT

IC601

Q501

DRIVE
BA5918

2SC4617(BR)

IC501

u-COM

SLED CLK

(A. B. C)

(A. B. C.D)

(A

2

. B2. C2 .D2)

3. Focus/Tracking/Sled Servo Circuit

3-1. FOCUS, TRACKING & SLED SERVO PROCESS

17

3-2. Focus Servo for CD/DVD

Focus Servo for CD/DVD is based on focus error signal generated from RF AMP (SSI3723). It standardizes the
laser beam (CD : A, B,C, DVD : A, B,C,D) radiated from the pick-up.
Each other focus gain or path is made at the SSI3723 (IC201) according to the disc, Focus Error signal
output from the FE terminal and input to Servo IC (IC301 CXD3011R).
After the first amplification of this signal, the signal is converted to A/D and input to Digital Equalizer Block
assigned the most important part at the Focus Servo, and generates the focus servo with coefficient value
set at the µ-COM through the Digital Filter.
At this Digital Equalizer, auto adjustment for Focus Balance or Focus Loop Gain occurs and the basic offset
value for pick-up is accepted on the balance mode, and set the focus standard level to this value.
After the signal for Focus Servo is converted to the D/A and output through FAO (IC301 CXD3011R ).
This signal drives Focus Actuator through the Focus Drive IC (IC601:BA5918FP).

3-3. Tracking Servo for CD/DVD

For Tracking Servo, CD uses 3 Beam method (E-F), DVD uses DPD (Differential Phase Detect) method
[Phase (A+C) - Phase (B+D)]
According to the disc, Tracking Error is set at SSI3723, Gain or Path differs from each other, and the
generated signal output through the TE terminal.
This signal input to TE of IC301, after the first amplification, and converted to A/D.
The signal converted to A/D input to the Digital Equalizer assigned the most important part at the Tracking
Servo, Tracking Servo Gain is generated with Digital Filter coefficient value set according to the disc at the
µ-COM.

* Tracking signal is converted to D/A through the pin TAO terminal of IC301 and input to IC601

(BA5918FP) tracking drive.
This drive drives the tracking actuator actually.

3-4. Sled Servo (Feed Servo) for CD/DVD

Sled servo operates related with a tracking servo basically
It goes with the progressive track speed according to the disc rotation speed.
Sled drive voltage is generated with a accumulated capacity of tracking error signal and is applied sled
movement voltage according to the track movement capacity, and this voltage outputs to the pin SAO of
IC301. This value is the sled motor drove by the IC601 (Sled drive : BA5918FP). But, the shift speed
for pick-up is not controlled and broke with a only sled servo, itself, in the data access mode, and the
feedback is used according to the sled shift speed at this time. So, the accurated shift speed for
pick-up is controlled added to the sled signal.
The hall sensor is used in the feedback and SLEDCLK 95 output at the µ-COM (IC501) is used with it
in the sled kick or break.

113

112

111

19

E

A

B

C

3

4

F

M

PICK-UP

SPINDLE MOTOR

A+B+2C

CD RF

DVD RF

A+B+C+D

IC501

IC301

IC601
Drive(Amp)

IC401
DVD DSP
CXD1867R

PLL BLOCK

Gain
Ctrl

FG

PLL BLOCK

Spindle
Control

DVD RF

CD RF

Motor

Hall Sensor

U

HU+
HU­HV+
HV­HW+
HW-

V

W

Speed
Monitoring

u-com

DVD/CD SERVO &
CD DSP

CXD3011R

IC201

RF AMP

SSI3723

IC1

Q601

AN8473SA

Motor Drive

SPINDLE SERVO PROCESS

LEVEL SHIFT

A, B, 2C

A, B, C, D

RF

RF

A

D

C

B

FG

MDP

MDIN2

SPO

CD/

DVD

4. Spindle Servo Circuit

4-1. SPINDLE SERVO PROCESS

4-2. Spindle Servo for CD/DVD

DVD-ROM consists of the three spindle control respectively.
(1) DVD x 8 : CAV (DVD Single, Dual Layer)
(2) CD x 12 (max.) : CAV (CD-DA, CD-RW, Video-CD (6-12 x), Host command stand-by of CD-ROM and
CD-R)
(3) CD x 24 (max.) : CAV (CD-R, CD-ROM play mode)
In the spindle speed control mode respectively.
CD x 12(Max)/CD x 24(Max) CAV drives CAV servo with PLL of RF data read and received MDP.
(Pin 117 of IC301)
DVD x 8 (Max) CAV drives CAV servo with FG signal and received MDP. (Pin 117 of IC301)

20

DESCRIPTION OF DATA PROCESSING

1. CD Data Processing Flow

CD

Pickup

Unit

Motor

Drive

Generating

A/B/2C/E/F Signal

H8/3062

Buffer

CD Data Buffering

CXD1867R

CD-ROM Decoder

and Host Interface

CXD 3011R

CD DSP

SSI3723 RF

Signal processing IC

CD TE/FE/SLED

Spindle Control

Command

Data

Status

SDATA

CD DATA

CD RF

IC201

IC301

IC401

IC471

IC501

MA [0..8]

MDB [0..F]

DATA [0..7]

ADR [0..8]

SICLK

SIXLT

SIDAT

SCLK

CD Data ECC

Receive the order from Host

2’nd ECC

CD Data Buffering

Generating RF Signal

Generating Tracking Error

Generating Focusing Error

CD Servo Control

CD Data Flow Control

Host Command Receive or Data/Status Transfer˚

Error Correction

Generating Header Sync

Generating Subcode Sync

EFM Demodulation

21

2. DVD Data Processing Flow

DVD

Pickup

Unit

Motor

Drive

DVD

TE/FE/Sled/

Spindle control

Sled Control

CXD 3011R

CD DSP

H8/3062

Buffer

CXD1867R

DVD DSP

Command

Data/

Status

DVD RF

DATA [0..7]

ADR [0..8]

MA [0..8]

MDB [0..F]

Generating

A/B/E/F Signal

SSI3723 RF

Signal processing IC

Generating RF Signal

Generating Tracking Error

Generating Focusing Error

Error Signal

Receive the Command from Host

DVD Data Buffering

Copy Protection Control

DVD Data Buffering

DVD Servo Control

DVD Data Flow Control

Host Command Receive or Data/Status transfer

Focus Control

Tracking Control

Spindle Control

EDC + ECC processing

Generating DVD ID Sync

EFM Demodulation

22

CXD 1867R

HOST DVD

PLAYER

(MPEG2

DECODER)

H8/3062

Scrambled MPEG Data

Change the "KEY"

KEY Management Control

3. Copy Protection and Regional Code Management Block

Block Diagram

Brief Process

1. Regional Code for DVD Disc

– DVD-ROM drive transfers the regional code of the control data to host by the command of host, the DVD

player of host reads the regional code, and plays title in the case of allowed regional code only.

2. Management of DVD Disc for the scrambled of data

(1) DVD-ROM and DVD player of host generate the “KEY 1” respectively, transfer to opposite part, the

“KEY 2” is received, recognizes the data transfer or not with this value, and generates the bus key

encoded the data.
(2) Encoded “Disc Key” and “Title Key” host is transfer with the bus Key.
(3) DVD player of host reads the key value, and uses the value to restore the scrambled data.

* Refer to the next page for the details.

23

4. About Prevention the DVD-ROM from to be copy

A data is able to encode and record in the disc, if a copyright holder wants to prevent the disc from copying.

In case of a disc enhanced movie of 3 titles......

DISC KEY (2048 Bytes) is used to encode the whole contents in the disc and TITLE
KEY (5 Bytes) is used to encode the title respectively.
So, the data is encoded and stored in a disc through the unknown algorithms
with a disc key and title key. (At this time, the disc key and title key are stored
in a disc.)

…As above, the disc is able to copy when the disc key and title key are

opened.
Then, ROM-DRIVE encodes the disc key and title key and transfers to MPEG­2 board.

If you want to play the disc prevented from the copy......

First of all, ROM-DRIVE and MPEG-2 board identify with each other through the procedure as described
below.

1. Drive and host gives and takes the ID of 2bit. This ID is AGID (Authentication Grant ID).
The various decoder boards are attached to the host, in these, AGID sets the MPEG-2 board and drive.

2. After the AGID is set, MPEG-2 board generates the challenge key (10 Byte) and transfers to drive. The
board and drive generate key 1 (5Byte) with the challenge key respectively. (Of course, the Algorithm
generating the key 1 is not known.)

3. Compare with the generated key 1, if it corresponds each other, the first step of authentication is
completed. This is a course to identify the MPEG-2 board with a drive.

4. The second step of authentication is a course to identify a drive with the MPEG-2 board.
The dirve generates a challenge key and transfers it to the MPEG-2 board. The dirve and MPEG-2 board
generate the key 2 (5Byte) with the challenge key, compare with each other, and if it corresponds and the
secondary step of authentication is completed.

5. As above, the identification is completed.

6. The dirve and MPEG-2 board generate the Bus key with the key 1 and key 2 and own it.

7. Dirve encodes the disc key and title key with this Bus key and transfers to the MPEG-2 board.

8. The MPEG-2 board reads the encoded disc key and title key with the Bus key only.

9. MPEG-2 board lets data read from the drive to decode with the read disc key and title key and makes into
the video signal by decoding.

ROM-DRIVE

AGID

HOST

MPEG-2
DECODER

Challenge key

encoded disc key, title key

24

5. About the DVD-ROM Regional Code

DISC ROM - DRIVE MPEG-2 DECODER VGA CARD

MONITOR

1

CAN

U.S.A

MIX

CUB

BHS

PRI. VIR

1

BMG

GRL

2

2

ZAF
ISO
SWZ

FIN

POI

FST

LTU

BIR

UKR

TUR

FGY

JRN

TKM

AFG

PAK

CHN

MMR

MNG

RUS

KOR

JPN

HKG

MAC

TWN

PHL

6

3

2

1

5

5

4

1

MDI

MNP

GUM

PLW

PNG

NZL

AUS

4

The disc has
the regional
code of 8 bit.

Example)

The disc
manufactured
in the U.S.A,
has the
number one.

Transfer to
MPEG-2
Decoder
reading the
regional code.

Receiving
data from the
MPEG-2
decoder and
output
through the
monitor

If the decoder is setting to the
regional decoder 1 for the

U.S.A. ...

Check the received regional
code to number 1, all or not,
transfer the data to VGA card
in accordance with only a case
among the three case.

Regional code

+5V

GND

FROM HOST
ADAPTOR

3.3VA

IC101

RS5510H003C

IC501
H/8/3062

IC1
AN8473SA

IC301
CXD-3011R

IC401
CXD1867R
DVD SERVO/DSP

IC601
BA5918FP

IC801
BH3525FV

5VA

5V

3.3V

Spindle

Motor

Drive

Spindle

Motor

CD-Audio

EFM/CIRC

DAC

SSP

RF PLL

RF PLL

CLV

Servo

EFM

Demod.

DVD

Decode

PN701

ECC

Core

CD-ROM

Dec.

Authentication

A/V Dec.

I/F

DMA

I/F

ATAPI

I/F

DRAM

512kB(4M)

Sync.Det

CLV

Servo

Sync. det

Loading &

Sled Motor

Drive

Sled

Motor

Tracking &

Focus

Tracking &

Focus coil

Audio

Line

Amp

Reset

&

Regulator

SYSTEM

CONTROLLER

Q101

XC62H3302

NJM
2100

CD SERVO/DSP

LASER
PICK-UP

DVD, CD DISK

IC201
SP3723

IC471

H
O
S
T

I/F

A B CD

1

2

3

4

5

CD/DVD
RF AMP

EQ.

IC102

IC402(1/2)

X301

33.86MHz

To Motor Drive

IC401/501

VREF1

CXD1867

VC(1.65V)

To CXD1867

To CXD-3011R

(IC301)

SF-HD4SSLG

VREF

1.35V

X501

X501

20MHz

33.86MHz

50MHz

SPINDLE MOTOR ASSY CIRCUIT

CD-A

CD-A

CN2

TO

P-UP

1

CD-A

CD-A

CN1

40

CD-F

39

P/UP-VCC

P/UP-VCC

P/UP-GND

P/UP-GND

P/UP-GND

38

37

CD-VC

36

353433

CD-LD32CD-MD31CD-C

To

Main

Board

30

CD-E29CD-B

28

DVD-MD27DVD-LD26DVD-C25DVD-B24DVD-RF23DVD-A22DVD-D21DVD-VC

20

T (+)19F (-)18F (+)17T (-)

EC

16

MOTOR GND14MOTOR GND13MOTOR VCC12MOTOR VCC

PWR SAVE

11

10

ECR

9FG8

7

SLED CLOCK
6

PHO VCC

5

EJECT SW

4

LED (+)3SLED (-)2SLED (+)

1

LEAD IN SW

15

CD-F

2

NC

3

CD-VCC

4

CD-VC

5

CD-GND

6

CD-LD7CD-MD

8

NC

9

CD-C10CD-E11CD-B

12

CD-VR

13

DVD-VR

14

DVD-MD 15

DVD-HFM

16

DVD-LD-GND

17

DVD-LD

18

DVD-C

19

DVD-B

20

DVD-RF

21

DVD-A

22

DVD-D

23

DVD-LD-GND

24

DVD-VC

25

DVD-VCC

26

27

28

F (+)

F (-)

T (+)

29

T (-)

CN3

SLED CLK

SW

SW1

1

2

30

1

CA

KE

PH-E

PH-C2PH-A3PH-K4GND

5

EJECT SW

6

LED

7

SLED (+)

SLED (-)

8

9

CD-F

CD-VC

C03

L2

R4

VH

VM11

IC1 AN8473SA

R1

R2

0

100

BEAD

220

C2

C3

2200p

0.1u

0.1u

0.1u

D1

6.2V

0.1u

0.22(1/4W)

R5

C4

C7

R3

SW

R6

V

SPINDLE

MOTOR

360

47u/6.3V

1+2

CD-LD

CD-MD

CD-C

CD-E

CD-B

DVD-MD

DVD-LD

DVD-C

DVD-B

DVD-RF

DVD-A

DVD-D

DVD-VC

SLED CLK

T(+)

F(-)

F(+)

T(-)

C6

C5

47u/6.3V

+

H3

H2

H1

PHO VCC

EJECT

LED

SLED (+)

SLED (-)

CD-F

CD-VC

CD-LD

CD-MD

CD-C

CD-E

CD-B

DVD-MD

DVD-LD

DVD-C

DVD-B

DVD-RF

DVD-A

DVD-D

DVD-VC

T (+)

F (-)

F (+)

T (-)

PHO VCC

220

EJECT

LED

SLED (-)

SLED (+)

M

1

32

VM12

H3L2H3H3H2L4H2H5H1L6H1H7EC8ECR9FG10START

VPUMP

BC1

BC2

GNC

VDD

31

PWMSW

30NC29

A1228A11

27

PG1

26

A2225A21

24

PG2

23

A3222A31

21NC20CS19

VM2218VM21

17

11 12 13 14 15 16

62

25

IC201 (SSI3723) : RF Signal Processing for CD/DVD

It amplifies or equalize the RF signal from Pick-up, and generate the TE (Tracking Error) and FE
(Focus Error) signal for Servo respectively.
The TE signal uses the DPD (Differential Phase Detect) method for DVD and 3 Beam method for CD.
DVD FE = (A+C) - (B+D)

CD FE = F - E

Block Diagram

MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN

DESCRIPTION

DVDRFP

DVDRFN

RFSIN

MUX

ATT

4. SIGR b3

INPUT SEL

5. RFCR b7-6
INPUT IMP

SEL

5. RFCR b5-4

INPUT IMP SEL

4. SIGR b7-4
ATT

2

4

2

4

3

3

2

5

4

2

2

IMPUT

BIAS

AGC

PROGRAMMABLE

EQUALIZER

FILTER

DIFFERENTIATOR

2. FCCR b7-0

3. FBCR b6-0

+

-

+
+

+
+

+
+

+

-

+

-

+
+

+
+

+

+

+

-

+
+

+

-

+

-

SSOUT

13. CAR b1-0

13. CAR b3-2
SIGDET

2

2

Level

DAC

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

GCA

1. PDCR b3
CD/DVD

4. SIGR b2-0

6dB is added

@high gain mode

(16. CDR b4=1)

12dB is added

@high gain mode

(16. CDR b4=1)

12dB is added

@high gain mode

(16. CDR b4=1)

3

3

4

5

6

3

8. TRCR2 b3-0

+/- 4dB

+/- 4dB

+3dB

TOPHOLD

TOPHOLD

TOPHOLD

6dB

Amp

Offset

cancel

Offset
cansel

17. CER b4-0

AGCO

FULL WAVE

RECTIFIER

17. CER b6

FAST Attack

17. CER b5

SLOW decay

AGC

CHARGE

PUMP

5. RFCR b3

AGC HOLO

w/LPF

w/LPF

w/LPF

w/LPF

4. SIGR b2-0

12dB is added

@high gain mode

(16. CDR b4=1)

A+D

A+C

B+C

B+D

A

B

C

D

3. FBCR b7

OUTPUT INHIBIT

6. FOCR b7-4

70kHz

LPF

DAC

GCA

GCA

GCA

SUM
Amp

Clamp

& Env

Inv.

10. PIOR b4-0

70kHz

15. CCR-b4-0

+/- 6dB, 4bit

+/- 6dB, 4bit

6. FOCR b3-0

PII

14. CBR b1-0

14. CBR b3-2

SEL

Buff

5

4

9. CTCR b3-0

-6dB @normal

COMP

9. CTCR b7
BCA DET

SEL

PI
FE
TE
CE

V25
V125
V25/3

MNTR

Control

10. PIOR b7-5

14. CBR b5-4

16. CDR b5
HLDEN

18. CFR b2-0
CE-ATT

18. CFR b3
CEPOL

5. RFCR b2-0

EQ

EQ

EQ

EQ

3

3

Comp

PHASE

DETECTOR

PHASE

DETECTOR

LPF

MUX

SUB

OFFSET

Cancel

GCA

TE

RST

1. PDCR b3
CD/DVD

8. TRCR2 b7
CP/CN

Low Imp

18. CFR b4
CEFDB

7. TRCR b5-0

for PI output ref.

18. CFR b7-5

for TE, FE & CE

output ref.

16. CDR b2

16. CDR b1

V25/2

V25/3

VC=VPB/2

VCI for servo input

SERIAL PORT

REGISTER

V33 for Output buff

CONTROL
Signals
To each block

12. MRCR2 b4 MIR ONLVL

15. CCR b7 DISK DET

15. CCR b6 Disk Det High Gain
@CCR b7 Disk Det=1

11. MRCR b7-5

12. MRCR2 b7
Comp offset & hys

MIRR
COMP

16. CDR b6
LINKEN

11. MRCR b4
internal FDCHG

PEAK/
BOTTOM
HOLD

15. CCR b7
DISK DET

12. MRCR2 b1-0
Mirr gain

16. CDR b7
Mirro Clamp ON

11. MRCR b1-0
Input Imp

Pll

12. MRCR2 b3-2
Sink current

7. TRCR b7

7. TRCR b6

8. TRCR2 b6-4

5. RFCR b2-0

16. CDR b3
LD H/L

15. CCR b5
APC SEL
DVD/CD

DVD/PD

CDPD

AGCO

12. MRCR2 b6-5
MUX

A

CD_A

B

CD_B

CD_C

CD_D

CD_E

CD_F

C

D

A2

B2

C2

D2

LDON

CDLD

DVDLD

MEV

MEVO

MIN

MLPFMPMB

LINK

MIRR

VPA

VPB

VNA

VNB

V33

SCLK

SDATA

SDEN

VC

V25

V125

TE

CN

CP

LCN

LCP

MNTR

CE

RFDC

DFT

TPH

PI

FE

RX

BYP

2

2

2

2

11. MRCR b3-2
Mirr LPF

LPF
ATT
Pol sel.
Buff (-12dB)

INPUT
BUFF

Offset

cancel

LPF

VC

Dual APC

ATOP

ATON

AIN

AIP

FNP

FNN

DIN

DIP

RFAC

MUX

BOTTOM
ENVELOPE

Name

VPA

VPB

VNA

VNB

V33

V25

Description

Power supply pin for the RF block and serial port

Power supply pin for the servo block

Ground pin for the RF block and serial port

Ground pin for the servo block

Power supply pin for the output buffers

Reference power supply for the servo output

Pin No.

58

19

51

25

45

36

Type

–

–

–

–

–

–

POWER SUPPLY PINS

IC201 (SSI3723)

• Pin Description

INPUT PINS

26

Name

DVDRFP,DVDRFN

RFSIN

AIP, AIN

DIP, DIN

A, B, C, D

A2, B2, C2, D2

CD_A, B, C, D

CD_E, F

MIN

DVDPD

CDPD

LDON

LINK

Description

RF SIGNAL INPUTS: Differential RF signal attenuator input pins.

RF SIGNAL INPUT: Single-ended RF signal attenuator input pin.

AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.

ANALOG INPUTS FOR RF SINGLE BUFFER: Differential analog inputs to the

RF single-end output buffer and full wave rectifier.

PHOTO DETECTOR INTERFACE INPUTS: Inputs from the main beam Photo

detector matrix outputs.

PHOTO DETECTOR INTERFACE INPUTS: AC coupled inputs for the DPD

from the main beam Photo detector matrix outputs.

CD PHOTO DETECTOR INTERFACE INPUTS : CD_A, B, C, D come from

the CD main beam Photo detector matrix outputs.

CD PHOTO DETECTOR INTERFACE INPUTS: CD side beam photo dector

outputs and used for the CD tracking detection.

RF SIGNAL INPUT FOR MIRROR: AC coupled inputs for the mirror detection

circuit from MEVO.

APC INPUT: DVD APC input pin from the monitor photo diode.

APC INPUT: CD APC input pin from the monitor photo diode.

APC OUTPUT ON/OFF: APC output control pin. A high level activates LD

output. (open low)

LINKING SIGNAL INPUT PIN: In the linking area. This pin goes high and the

Mirror and TE outputs are disabled. When the link signal is enabled. (open low)

Pin No.

1,2

63

59,60

54,55

9, 10, 11, 12

3, 4, 5, 6

13, 14, 15, 16

17, 18

31

23

24

26

33

Type

I

I

I

I

I

I

I

I

I

I

I

I

I

27

Name

ATOP/ATON

FNP, FNN

RFAC(SIGO)

RFDC

FE

TE

CE

MEVO

DFT

MIRR

PI

DVDLD

CDLD

MNTR

Description

DIFFERENTIAL ATTENUATOR OUTPUTS: Attenuator outputs.

DIFFERENTIAL NORMAL OUTPUTS: Filter normal outputs.

SINGLE-ENDED NORMAL OUTPUT: Single-ended RF output.

RF SIGNAL OUTPUT: Single-ended RF summing output

reference to VPB-2.4(V).

FOCUSING ERROR SIGNAL OUTPUT: Focus error output reference to V125.

TRACKING ERROR SIGNAL OUTPUT: Tracking error output reference to V125.

CENTER ERROR SIGNAL OUTPUT: Center error output reference to V125.

RFDDC BOTTOM ENVELOPE OUTPUT: Bottom envelope, PI or bottom
clamped RF envelope signal output for Mirror detection.

DEFECT OUTPUT: CMOS output (V33 or VPB). When the PI signal level is
below the detection level or when the Rf signal level is below the detection level,
the DFT output goes high. This output is selected by serial port.

MIRROR DETECT OUTPUT: Mirror detect comparator output. CMOS
output(V33 or VPB).

PULL-IN SIGNAL OUTPUT: The summing signal output of A, B, C, D or CD_A,
B, C, D. Reference to V25/3.

APC OUTPUT: DVD APC output pin to control the laser power.

APC OUTPUT: CD APC output pin to control the laser power.

MONITOR OUTPUT: Monitor Output signal is selected by PIOR bit7-5

Pin No.

61,62

52,53

57

64

40

39

41

32

34

27

38

21

22

42

Type

O

O

O

O

O

O

O

O

O

O

O

O

O

O

OUTPUT PINS

Name

BYP

CP

CN

LCP

LCN

MP

MB

MEV

MLPF

TPH

VC

V125

RX

Description

The RF AGC integration capacitor C

BYP. is connected between BYP and VPA.

DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is
connected between CN.

DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is
connected between CP.

LENS SHIFT OFFSET CANCEL LPF PIN: The external capacitance is connected
between LCN.

LENS SHIFT OFFSET CANCEL LPF PIN: The external capacitance is connected
between LCP.

MIRR TOP HOLD PIN: The external capacitance is connected to VPB.

MIRR BOTTOM HOLD PIN: The external capacitance is connected to VPB.

RFDC BOTTOM ENVELOPE PIN: The external capacitance is connected to VPA.

MIRROR LPF PIN: An external capacitance is connected to VPB.

PI TOP HOLD PIN: An external capacitance is connected to VPB.

REFERENCE VOLTAGE OUTPUT: This pin provides the DC bias reference
Voltage (VPB/2). Output impedance is less than 50Ω.

REFERENCE VOLTAGE OUTPUT: DC bias voltage output and it is also used for
servo output reference. (V25/2)

REFERENCE RESISTOR INPUT: An external 12.0kΩ, 1% resistor is connected
from this pin to ground to establish a precise PTAT (proportional to absolute
temperature) reference current for the filter.

Pin No.

56

7

8

44

43

28

29

50

30

35

20

37

49

Type

–

–

–

–

–

–

–

–

–

–

–

–

–

ANALOG PINS

28

Name

SDEN

SDATA

SCLK

Description

SERIAL DATA ENABLE: Serial enable CMOS input. A high level input
enables the serial port. (not to be left open)

SERIAL DATA: Serial data bidirectional CMOS pin(V33). NRZ programming
data for the internal registers is applied to this input. (not to be left open)

SERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is
synchronized with the data applied to SDATA. (not to be left open)

Pin No.

48

47

46

Type

I

I/O

I

SERIAL PORT PINS

29

IC501 (H8/3062) : µ-COM

It Controls the total system giving or taking the data from the peripheral ICS.

• Pin Description

Pin

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

DRD-8080B

pin name

VCC1

RCLK

LDON

XCS

DSPMUTE

CD/DVD

PWRCTL_3V

XRST

LED

FWE

VSS1

SIDATA

SCLK/TXD

XILAT

SQCK/RXD

SICLK

NFOK
_

_

CD_H
_

VSS2
_

AUDMUTE

PWRCTL_5V

FWEON

D0

D1

D2

D3

D4

D5

D6

D7

VCC2

A0

A1

A2

5V

SP3723 control clock

APC output On/Off to SP3723

Chip select to CXD1867

Mute signal to CXD3011R

Spindle drive Gain Change

3.3V Control(IC102)

Reset out to CXD3011R, 1867R

Access LED

Flash memory writing enable input from Q201 emitter

GND

Serial Data signal to CXD3011R

Serial data signal to CXD3011R

Serial data latch output

Sub Q serial clock to CXD3011R

Serial clock signal to CXD3011R

FOK input signal from CXD3011R

NC

NC

“H” output at CD Mode

NC

GND

NC

Audio Mute Control

5V Control (Q101, Q102)

Flash memory writing enable output to Q201 base

Data bus to CXD1867R

Data bus to CXD1867R

Data bus to CXD1867R

Data bus to CXD1867R

Data bus to CXD1867R

Data bus to CXD1867R

Data bus to CXD1867R

Data bus to CXD1867R

5V

Address bus to CXD1867R

Address bus to CXD1867R

Address bus to CXD1867R

H8/3062

pin name

Vcc

PB-0

PB-1

PB-2

PB-3

PB-4

PB-5

PB-6

PB-7

FWE

Vss

P9-0

P9-1

P9-2

P9-3

P9-4

P9-5

P4-0

P4-1

P4-2

P4-3

Vss

P4-4

P4-5

P4-6

P4-7

D8

D9

D10

D11

D12

D13

D14

D15

Vcc

P1-0

P1-1

P1-2

I/O

I

O

O

I

O

O

O

O

O

I

I

O

O

O

O

O

O

O

O

O

O

I

O

O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

O

O

O

Description

30

Pin

No.

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

DRD-8080B

pin name

A3

A4

A5

A6

A7

VSS3

A8

CGFS

MAnSL

SENS

DGFS

SQSO



LOADIN









VSS4

XWAIT

RDE

RDATA



/STBY

/RES(RESET)

LOADIN

VSS5

EXTAL

XTAL

VCC3



XRD

XWR



MD0

MD1

MD2

AVCC

VREF

FE





LOADKEY

Description

Address bus to CXD1867R

Address bus to CXD1867R

Address bus to CXD1867R

Address bus to CXD1867R

Address bus to CXD1867R

GND

Address bus to CXD1867R

CD GFS signal from CXD3011R

IDE jumper input (H:Slave, L:Master)

SENS input signal from CXD3011R

DGFS input signal from CXD1867R

sub Q data from CXD3011R

NC

Tray closed S/W input

NC

NC

NC

NC

GND

Wait signal to CXD1867R

SP3723 enable data

SP3723 control data

NC

Hardware standby mode transition input

Reset input from reset part

Tray closed S/W input.

GND

Connect to X-TAL (20MHz)

Connect to X-TAL (20MHz)

5V

NC

Read signal to CXD1867R

Write signal to CXD1867R

NC

Operating mode control 0

Operating mode control 1

Operating mode control 2

5V

Referance voltage for A/D, D/A converters

Focus error A/D analog input from SP3723

NC

NC

Load key input from SW1(Lead in SW)

H8/3062

pin name

P1-3

P1-4

P1-5

P1-6

P1-7

V

SS

P2-0

P2-1

P2-2

P2-3

P2-4

P2-5

P2-6

P2-7

P5-0

P5-1

P5-2

P5-3

Vss

P6-0

P6-1

P6-2

P6-7

/STBY

/RES

NMI

Vss

EXTAL

XTAL

Vcc

/AS

/RD

/HWR

/LWR

MD0

MD1

MD2

Avcc

Vref

P7-0

P7-1

P7-2

P7-3

I/O

O

O

O

O

O

I

O

I

I

I

I

I

I

I

I

O

O

O

O

I

I

I

I

I

I

O

O

I

I

I

I

I

I

I

I

I

31

Pin

No.

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

DRD-8080B

pin name

APEO



TESTMD



AVSS

XINT0

XINT1

EJECT-SW

SCOR



VSS6

COUT

PWRCTL-PHO

SLEDCLK

FG0

FG1

MIRR

BCARF

DRVMU1

Description

Absolute phase error signal from CXD1867R

NC

MD test signal input

NC

GND

Int0 request from CXD1867R

Int1 request from CXD1867R

Eject key input.

Sub code sync input signal from CXD1867R & CXD3011R

NC

GND

COUT from CXD3011R

PHO Vcc control output (Q502)

Sled motor rotation senser clock input

Spindle motor rotation sensor clock input

Spindle motor rotation sensor clock input

MIRR input from SP3723

BCARF input from SP3723

Actuator driveIC(IC601) & Spindle driveIC(IC1) Mute control.

H8/3062

pin name

P7-4

P7-5

P7-6

P7-7

Avss

P8-0

P8-1

P8-2

P8-3

P8-4

Vss

PA-0

PA-1

PA-2

PA-3

PA-4

PA-5

PA-6

PA-7

I/O

I

I

I

O

I

I

I

I

I

I

I

O

I

I

I

I

I

O

32

IC401 (CXD1867R) : LSI processing for DVD-ROM Drive Signal

Block Diagram

116

111 113 114 115 76 95 78 94 91 92 93

23

57

51

55

54

46

117

130

131

132

16

126

125

124

120

121

144

142

140

138

137

135

136

107

109

146

160

158

163

155

151

150

148

147

153

159

162

157

167 18 17 19 20 21 16

127

RFDCC

DASYO

DASYI

XMWR

XCAS

XRAS

XMOE

MA9/mnt0

MA10/mnt1

MA11/mnt2

MA[8:0]

MDB[F:0]

XHRS

XPDI

REDY

XS16

HINT

HDRQ

65

DASP

53

XHAC

48

49

63

62

164

169

170

XHWR

XHRD

HCS1

HCS0

XRST

XTL2

XTL1

HA[2:0]

ASF1

ASF2

RFIN

PDO

PDHVCC

FDO

LPF1

LPF2

VC1

LPF5

VCOR1

VCOIN

MDPOUT

MDSOUT

CLVS

MDIN1

MDIN2

SPO

VC2

GFS

APEO

GSCOR

MDAT

BCLK

LRCK

C2PO

WFCK

SCOR

SBIN

EXCK

XRCI

DDAT

DLRC

DBCK

XTAL

XWR

XRD

D[7:0]

A[7:0]

XCS

XINT0

XINT1

XWAIT

79, 80,
82~87, 89

66~69, 71, 73~75, 96, 97, 99,
101, 102, 104~106

24, 26, 27,
29~32, 34,
35, 37,
39~41,
43~45

HDB[F:0]

56, 59, 60

1, 2, 4, 172~176

5, 7, 9~14

RF

Asymmetry

DMA Controller

(Priority resolve & Sequencer)

DVD

Main Data

ECC & EDC

SYNC Detect

EFM+

Demodulator

Sector ID

Detect

CD-ROM

Main Data

ECC & EDC

Descramble

Subcode

Deinterleave & ECC

SYNC Control

CD ESP

Authentication

CPU I/F, DMA Controller

DMA
FIFO

HOST

I/F

ATAPI

or

DMA

or

Video

ATAPI

Registers

ATAPI
Packet

FIFO

Internal Clock

VCO

Spindle
Control

CD-

DSP

I/F

DAC

I/F

PLL

33

Pin No. Name I/O INPUT OUTPUT I/O buffer Comment

[V] Current

1 D5 I/O 3.3 -4mA/4mA 5V tolerant
2 D6 I/O 3.3 -4mA/4mA 5V tolerant
3 Vss*  DGND 
4 D7 I/O 3.3 -4mA/4mA 5V tolerant
5 A0 I 3.3  5V tolerant
6V

DD*  3.3 

7 A1 I 3.3  5V tolerant
8V

DD5V*  5.0 

9 A2 I 3.3  5V tolerant
10 A3 I 3.3  5V tolerant
11 A4 I 3.3  5V tolerant
12 A5 I 3.3  5V tolerant
13 A6 I 3.3  5V tolerant
14 A7 I 3.3  5V tolerant
15 Vss*  DGND 
16 XWAIT I/O 3.3 -4mA/4mA 5V tolerant
17 XRD I 3.3  5V tolerant
18 XWR I 3.3  5V tolerant
19 XCS I 3.3  5V tolerant
20 XINT0 O 3.3 -8mA/8mA 
21 XINT1 I/O 3.3 -8mA/8mA 5V tolerant
22 V

DD*  3.3 

23 XHRS I 5.0  ATAPI PULL UP
24 HDB7 I/O 5.0 -4mA/12mA ATAPI
25 Vss*  DGND 
26 HDB8 I/O 5.0 -4mA/12mA ATAPI
27 HDB6 I/O 5.0 -4mA/12mA ATAPI
28 V

DDS*  5.0 

29 HDB9 I/O 5.0 -4mA/12mA ATAPI
30 HDB5 I/O 5.0 -4mA/12mA ATAPI
31 HDBA I/O 5.0 -4mA/12mA ATAPI
32 HDB4 I/O 5.0 -4mA/12mA ATAPI
33 Vss*  DGND 
34 HDBB I/O 5.0 -4mA/12mA ATAPI
35 HDB3 I/O 5.0 -4mA/12mA ATAPI
36 V

DD*  3.3 

37 HDBC I/O 5.0 -4mA/12mA ATAPI
38 V

DDS*  5.0 

39 HDB2 I/O 5.0 -4mA/12mA ATAPI
40 HDBD I/O 5.0 -4mA/12mA ATAPI
41 HDB1 I/O 5.0 -4mA/12mA ATAPI
42 Vss*  DGND 
43 HDBE I/O 5.0 -4mA/12mA ATAPI
44 HDB0 I/O 5.0 -4mA/12mA ATAPI
45 HDBF I/O 5.0 -4mA/12mA ATAPI
46 HDRQ O 5.0 -4mA/12mA ATAPI
47 V

DDS*  5.0 

48 XHWR I/O 5.0 -4mA/12mA ATAPI
49 XHRD I/O 5.0 -4mA/12mA ATAPI
50 V

DD*  3.3 

34

Pin No. Name I/O INPUT OUTPUT I/O buffer Comment

[V] Current

51 REDY O 5.0 -4mA/12mA ATAPI
52 Vss*  DGND 
53 XHAC I 5.0  ATAPI PULL UP
54 HINT I/O 5.0 -4mA/12mA ATAPI
55 XS16 O 5.0 -4mA/12mA ATAPI
56 HA1 I 5.0  ATAPI
57 XPD1 I/O 5.0 -4mA/12mA ATAPI
58 V

DDS*  5.0 

59 HA0 I 5.0  ATAPI
60 HA2 I 5.0  ATAPI
61 Vss*  DGND 
62 HCS0 I 5.0  ATAPI PULL UP
63 HCS1 I 5.0  ATAPI PULL UP
64 V

DD

*  3.3 
65 DASP I/O 5.0 -4mA/12mA ATAPI
66 MDB0 I/O 3.3 -4mA/4mA 5V tolerant
67 MDB1 I/O 3.3 -4mA/4mA 5V tolerant
68 MDB2 I/O 3.3 -4mA/4mA 5V tolerant
69 MDB3 I/O 3.3 -4mA/4mA 5V tolerant
70 Vss*  DGND 
71 MDB4 I/O 3.3 -4mA/4mA 5V tolerant
72 V

DD5V*  5.0 

73 MDB5 I/O 3.3 -4mA/4mA 5V tolerant
74 MDB6 I/O 3.3 -4mA/4mA 5V tolerant
75 MDB7 I/O 3.3 -4mA/4mA 5V tolerant
76 XMWR I/O 3.3 -4mA/4mA 5V tolerant
77 V

DD*  3.3 

78 XRAS I/O 3.3 -4mA/4mA 5V tolerant
79 MA0 O 3.3 -4mA/4mA 
80 MA1 O 3.3 -4mA/4mA 
81 Vss*  DGND 
82 MA2 O 3.3 -4mA/4mA 
83 MA3 O 3.3 -4mA/4mA 
84 MA4 O 3.3 -4mA/4mA 
85 MA5 O 3.3 -4mA/4mA 
86 MA6 O 3.3 -4mA/4mA 
87 MA7 O 3.3 -4mA/4mA 
88 V

DD*  3.3 

89 MA8 O 3.3 -4mA/4mA 
90 Vss*  DGND 
91 MA9/mnt0 O 3.3 -4mA/4mA 
92 MA10/mnt1 I/O 3.3 -4mA/4mA 5V tolerant
93 MA11/mnt2 I/O 3.3 -4mA/4mA 5V tolerant
94 XMOE O 3.3 -4mA/4mA 
95 XCAS O 3.3 -4mA/4mA 
96 MDB8 I/O 3.3 -4mA/4mA 5V tolerant
97 MDB9 I/O 3.3 -4mA/4mA 5V tolerant
98 Vss*  DGND 
99 MDBA I/O 3.3 -4mA/4mA 5V tolerant

100 V

DD*  3.3 

101 MDBB I/O 3.3 -4mA/4mA 5V tolerant

35

Pin No. Name I/O INPUT OUTPUT I/O buffer Comment

[V] Current

102 MDBC I/O 3.3 -4mA/4mA 5V tolerant
103 V

DD5V*  5.0 

104 MDBD I/O 3.3 -4mA/4mA 5V tolerant
105 MDBE I/O 3.3 -4mA/4mA 5V tolerant
106 MDBF I/O 3.3 -4mA/4mA 5V tolerant
107 GFS I/O 3.3 -4mA/4mA 
108 Vss*  DGND 
109 APE0 O 3.3 -8mA/8mA 
110 VDD*  3.3 
111 DASYO O 3.3 -8mA/8mA 
112 GNDA5*  AGND 
113 ASF1  3.3 
114 ASF2  3.3 
115 DASY1  3.3 
116 RFDCC  3.3 
117 RFIN  3.3 
118 VccA5*  3.3 
119 VccA4*  3.3 
120 VCOR1  3.3 
121 VCOIN  3.3 
122 GNDA4*  AGND 
123 GNDA3*  AGND 
124 LPF5  3.3 
125 VC1  3.3 
126 LPF2  3.3 
127 LPF1  3.3 
128 VccA3*  3.3 
129 VccA2*  3.3 
130 PDO  3.3 
131 PDHVCC  3.3 
132 FDO  3.3 
133 GNDA2*  AGND 
134 GNDA1*  AGND 
135 SPO  3.3 
136 VC2  3.3 
137 MDIN2  3.3 
138 MDIN1  3.3 
139 VccA1*  3.3 
140 CLVS I/O 3.3 -4mA/4mA 5V tolerant
141 Vss*  DGND 
142 MDSOUT I/O 3.3 -4mA/4mA 5V tolerant
143 V

DD*  3.3 

144 MDPOUT I/O 3.3 -4mA/4mA 5V tolerant
145 DFCT/LINK I/O 5.0 -4mA/4mA 5V tolerant Hystelesis type
146 GSCOR I/O 5.0 -4mA/4mA 5V tolerant Hystelesis type
147 EXCK O 5.0 -4mA/4mA 
148 SBIN I 5.0  5V tolerant Hystelesis type
149 Vss*  DGND 
150 SCOR I 5.0  5V tolerant Hystelesis type
151 WFCK I 5.0  5V tolerant Hystelesis type
152 V

DD5V*  5.0 

Pin No. Name I/O INPUT OUTPUT I/O buffer Comment

[V] Current

153 XRC1 I 5.0  5V tolerant Hystelesis type
154 V

DDS*  5.0 

155 C2PO I 5.0  5V tolerant Hystelesis type
156 V

DD*  3.3 

157 DBCK O 5.0 -4mA/4mA 
158 BCLK I 5.0  5V tolerant Hystelesis type
159 DDAT O 5.0 -4mA/4mA 
160 MDAT I/O 5.0 -4mA/4mA 5V tolerant Hystelesis type
161 Vss*  DGND 
162 DLRC O 5.0 -4mA/4mA
163 LRCK I 5.0  5V tolerant Hystelesis type
164 XRST I 5.0 Hystelesis type
165 IFS0 I 3.3 
166 IFS1 I 3.3 
167 XTAL I 5.0 
168 Vss*  DGND 
169 XTL2 O 3.3 
170 XTL1 I 3.3 
171 V

DD*  3.3 

172 D0 I/O 3.3 -4mA/4mA 5V tolerant
173 D1 I/O 3.3 -4mA/4mA 5V tolerant
174 D2 I/O 3.3 -4mA/4mA 5V tolerant
175 D3 I/O 3.3 -4mA/4mA 5V tolerant
176 D4 I/O 3.3 -4mA/4mA 5V tolerant

36

37

IC1 (AN8473SA) : Spindle Motor Drive IC

Start/Stop

VDD

VDD

START

FG

H1H

H1L

H2H

H2L

H3H

H3L

VH

EC

ECR

PWMSW

SSET

SRESET

PWMOUTL

PWMOUTU

BC2 BC1 VPUMP

VM21

Vt

Vc1

Hall

Amp

Matrix

Hall

Bias

PWM Freq.

Change

Divide
Circuit

Absolute

Value

Drive

Output

Circuit

MOTOR

Amp

Amp

Voltage

Boost

OSC

Heat

Protection

X5

FF

16

11

10

7

6

5

4

3

2

1

8

9

30

12

17

VM22

18

VM11

32

VM12

31

A11

27

A12

28

14 13

A21

24

A22

25

A31

21

A32

22

PG2

23

PG1

26

CS

19

GND

15

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Description

Hall bias

Hall3 input, negative

Hall3 input, positive

Hall2 input, negative

Hall2 input, positive

Hall1 input, negative

Hall1 input, positive

Torque control input

Torque control VREF

FG output

Start/Stop control

Boostor Pin

Boostor C connection

Boostor C connection

GND

Power supply, 5V

Pin Name

VH

H3L

H3H

H2L

H2H

H1L

H1H

EC

ECR

FG

Start

VPUMP

BC1

BC2

GND

VDD

Pin No.

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Description

Motor Vcc-2

Motor Vcc-2

Current sensing pin

NC

Drive output3

Drive output3

Power Current sensing pin2

Drive output2

Drive output2

Power Current sensing pin1

Drive output1

Drive output1

NC

Change PWM Freq.

Motor Vcc-1

Motor Vcc-1

Pin Name

VM21

VM22

CS

NC

A31

A32

PG2

A21

A22

PG1

A11

A12

NC

PWMSW

VM12

VM11

Block Diagram

• Pin Description

Spindle Speed

Control INPUT

38

• IC601 (BA5918FP) : Focus/Tracking/SLED Control Drive IC

Block Diagram

+

-

123456 78910111213

-

-

+

-

-

+

-

+

+

-

+

+

-

+

+

-

+

-

-

+

-

+

-

+

10K

10K10K

10K

10K

10K

10K 10K

10K 10K

10K

10K 10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

Vcc

Vcc

25 24 23 22 21 20 19 18 17 16 15 14

STBY

LEVEL
SHIFT

LEVEL
SHIFT

LEVEL
SHIFT

LEVEL
SHIFT

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

Pin No.

14

15

16

17

18

19

20

21

22

23

24

25

Function

Vcc

Bias amplifier input

Driver CH1 input

Driver CH2 input, gain adjustment pin

Driver CH2 input

Substrate Ground

Substrate Ground

Input for stand-by control

Vcc

Driver CH2 inverted output

Driver CH2 noninverted output

Driver CH1 inverted output

Driver CH1 noninverted output

Functio

Driver CH4 noninverted output

Driver CH4 inverted output

Driver CH3 noninverted output

Driver CH3 inverted output

Vcc

Substrate Ground

0p-amp input, positive

0p-amp input, negative

0p-amp output

Driver CH3 input

Driver CH3 input,gain adjustment pin

Driver CH4 input

Pin Name

VCC

BIAS.IN

VIN1

VIN2

VIN2

GND

GND

STBY

Vcc

V02(-)

V02(+)

V01(-)

V02(+)

Pin Name

V04(+)

V04(-)

V03(+)

V03(-)

Vcc

GND

0P IN (+)

0P IN (-)

0P OUT

VIN3

VIN3

VIN4

Pin Description

* Symbol of + and - (output of DRIVERS) means polarity to input pin.

(For example if voltage of pin 3 is high, pin 13 is high.)

39

IC301 (CXD3011R) : DSP

The CXD3011R is a Digital Signal Processor(DSP) LSI for CD players.
This LSI incorporates a Digital Servo, Digital Filter and 1-Bit DAC.

52

83

84

5

51

136

135

57

58
59

7

122

107

129

123

124

141

132

13
15

16

24

64

65

67

66
69

68

117

118

116

133

71

140

142

143

105

102

100

103

104

114

111

95

99

98

62

65

25

79

80

88

82

61

112

113

4

22

3

2

10

11

9
8

Clock
Generator

32K RAM

Digital PLL

Vari-Pitch

double

speed

EFM

Demodulator

Sync

D/A

protector

Address

generator

8Fs Digital Filter

+

1 bit DAC

Priority

encoder

Timing

CLV

processor

CAV

processor

Servo

auto

Digital Out

Generator1

Timing

Generator2

Selector

Noise

Shaper

18~times

oversampling

filter

P~W

Subcode

Subcode Q

processor

processor

CPU

interface

Servo

Interface

SERVO DSP

DAC O

pAmp

FOCUS SERVO

TRACKINGSERVO

FOCUS

SLED

TRACKING

SLED SERVO

O

pAmp

AnaSw

A/D

CONVERTER

MIRR
DFCT

FOK

Peak

detector

Error

corrector

data

processor

Serial/parallel

processor

Register

XTLO

BSSD

XTLI

VPCO1

6

VPCO2

XTSL

PCMDI

BCKI

LRCKI

DTSO

XWO

RMUTO

LMUTO

Error Rate

Counter

sequencer

OSC

MCKO

V16M

VCKI

FSTIO

C4M

C16M

VCTL

PCO

131

VCOO

VCOI

134

PDO

FILI

FILO

CLTV

RFAC

ASYI

ASYO

ASYE
WFCK
SCOR

EXCK

SBSO
SQCK
SQSO

MDP

MDS

MON

FSW

PWMI

TEST
TEST2
TEST3

XRST

ADIO

RFDC

CE

TE

SE

FE

VC

DV 1

DD

43

DV 2

DD

60

DV 3

DD

94

DV 4

DD

130

DV 5

DD

17

AV 1

DD

137

AV 2

DD

93

AV 3

DD

81

AV 4

DD

82

AV 5

DD

115

AV 6

DD

23

DV 1

SS

50

DV 2

SS

77

DV 3

SS

101

DV 4

SS

121

DV 5

SS

12

AV 1

SS

139

AV 2

SS

86

AV 3

SS

78

AV 4

SS

85

AV 5

SS

110

AV 6

SS

SAO

TAO

FAO

COUT

SENS

DATA

DOUT

MUTE

PSSL

PWMLP
PWMLN
PWMRP

PWMRN

DA16(48PCM)

DA14(64PCM)

DA15(48BCK)

DA13(64BCK)
DA12(64LRCK)

DA11~DA01

MD2

CLOK
XLAT

MIRR
DFCT
FOK

SIGNAL PROCESSOR BLOCK

SERVO BLOCK

DAC BLOCK

35

34

33

31

29

30

32

28

74

75

76

8

MUX

*

* : Asymmetry

Correction

38~42,
44~49

Block Diagram

40

IC301 CXD3011R

• Pin Description

Pin No. Symbol I/O Description

2 SE I Sled error signal input.

3 FE I Focus error signal input.

4 VC I Center voltage input.

5 VPCO1 O 1, Z, 0 Wide-band EFM PLL VCO2 charge pump output.

6 VPCO2 O 1, Z, 0 Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E

command FCSW.

7 VCTL I Wide-band EFM PLL VCO2 control voltage input.

8 FILO O Analog Master PLL filter output (slave = digital PLL).

9 FILI I Master PLL filter input.

10 PCO O 1, Z, 0 Master PLL charge pump output.

11 CLTV I Multiplier VCO control voltage input.

12 AVss1 Analog GND.

13 RFAC I EFM signal input.

14 BIAS I Asymmetry circuit constant current input.

15 ASYI I Asymmetry comparator voltage input.

16 ASYO O 1, 0 EFM full-swing output (low = Vss, high = V

DD)

17 AV

DD1 Analog power supply.

22 DV

DD1 Digital power supply.

23 DVss1 Digital GND.

24 ASYE I Asymmetry circuit on/off (low = off, high = on).

25 PSSL I Audio data output mode switching input (low: serial, high: parallel).

26 WDCK O 1, 0 D/A interface for 48-bit slot. Word clock f = 2Fs.

27 LRCK O 1,0 D/A interface for 48-bit slot. LR clock f =Fs.

28 LRCK1 I LR clock input to DAC (48-bit slot).

29 DA16 O 1, 0 DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two’s complement,

MSB first) when PSSL = 0.

30 PCMDI I Audio data input to DAC (48-bit slot).

31 DA15 O 1, 0 DA15 output when PSSL = 1, 48-bit slot bit clock output whe PSSL = 0.

32 BCK1 I Bit clock input to DAC (48-bit slot).

33 DA14 O 1, 0 DA14 output when PSSL = 1, 64-bit slot serial data output (two’ complement,

LSB first) when PSSL = 0.

34 DA13 O 1,0 DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.

35 DA12 O 1, 0 DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.

38 DA11 O 1, 0 DA11 output when PSSL = 1, GTOP output when PSSL = 0.

39 DA10 O 1, 0 DA10 output when PSSL = 1, XUGF output when PSSL = 0.

40 DA09 O 1, 0 DA09 output when PSSL = 1, XPLCK output when PSSL = 0.

41 DA08 O 1, 0 DA08 output when PSSL = 1, GFS output when PSSL = 0.

42 DA07 O 1, 0 DA07 output when PSSL = 1, RFCK output when PSSL = 0.

41

Pin No. Symbol I/O Description

43 DV

DD2 Digital power supply.

44 DV06 O 1, 0 DA06 output when PSSL = 1, C2PO output when PSSL = 0.

45 DA05 O 1, 0 DA05 output when PSSL = 1, XRAOF output when PSSL = 0.

46 DA04 O 1, 0 DA04 output when PSSL = 1, MNT3 output when PSSL = 0.

47 DA03 O 1, 0 DA03 output when PSSL = 1, MNT2 output when PSSL = 0.

48 DA02 O 1, 0 DA02 output when PSSL = 1, MNT1 output when PSSL = 0.

49 DA01 O 1, 0 DA01 output when PSSL = 1, MNT0 output when PSSL = 0.

50 DVss2 Digital GND.

51 XTSL I Crystal selection input.

52 MCKO O 1, 0 Clock output. Inverted output of XTLI.

57 FSTIO I/O 1, 0 Digital servo clock input/output.

(2/3 frequency division for XTLI pin is internally connected.)

58 C4M O 1, 0 1/4 frequency division output for XTLI pin. Changes with variable pitch.

59 C16M O 1, 0 16.9344MHz output. Changes simultaneously with variable pitch.

60 DV

DD3 Digital power supply.

61 MD2 I Digital Out on/off control (low = off, high = on).

62 DOUT O 1, 0 Digital Out output.

63 MUTE I Mute (low:off, high:on).

64 WFCK O 1, 0 WFCK (Write Frame Clock) output.

65 SCOR O 1, 0 Outputs a high signal when either suvcode sync S0 or S1 is detected.

66 SBSO O 1, 0 Sub P to W serial output.

67 EXCK I SBSO readout clock input.

68 SQSO O 1, 0 Sub-Q 80-bit, PCM peak and level data 16-bit outputs.

69 SQCK I SQSO readout clock input.

70 SCSY I GRSCOR resynchronization input. Normally low, resynchronization is executed

when high.

71 XRST I System reset. Reset when low.

74 XWO I Audio DAC sync window open input. Normally high, window open when low.

75 RMUTO O 1, 0 Audio DAC right channel zero detection flag.

76 LMUTO O 1, 0 Audio DAC left channel zero detection flag.

77 DVss3 Digital GND.

78 AVss4 Analog GND.

79 PWMRN O 1, Z, 0 Audio DAC PWM output. Right channel, reversed pahse.

80 PWMRP O 1, Z, 0 Audio DAC PWM output. Right channel, forward phase.

81 AV

DD4 Analog power supply.

82 AV

DD5 Master clock power supply.

83 XTLO O 1, 0 Master clock crystal oscillation circuit output.

84 XTLI I Master clock crystal oscillation circuit input.

85 AVss5 Master clock GND.

42

Pin No. Symbol I/O Description

86 AVss3 Analog GND.

87 PWMLP O 1, Z, 0 Audio DAC PWM output. Left channel, forward phase.

88 PWMLN O 1, Z, 0 Audio DAC PWM output. Left channel, reverse phase.

93 AV

DD3 Analog power supply.

94 DV

DD4 Digital power supply.

95 SENS O 1, Z, 0 SENS output to CPU.

96 SCLK I SENS serial data readout clock input. Set to high when not used.

97 ATSK I Anti-shock pin. Set to low when not used.

98 DATA I Serial data input from CPU.

99 XLAT I Latch input from CPU. Serial data is latched at the falling edge.

100 CLOK I Serial data transfer clock input from CPU.

101 DVss4 Digital GND.

102 COUT I/O 1, 0 Track count signal I/O.

103 MIRR I/O 1, 0 Mirror signal I/O.

104 DFCT I/O 1, 0 Defect signal I/O.

105 FOK I/O 1, 0 Focus OK signal I/O.

106 TESO O TEST pin. Leave this open.

107 FSW O 1, Z, 0 Spindle motor output filter switching output.

GRSCOR output when $8 command SCOR SEL = high.

110 AVss6 Analog GND.

111 SAO O Sled filter DAC anlog output.

112 TAO O Tracking filter DAC analog output.

113 FAO O Focus filter DAC analog output.

114 BSSD I Constant current input for servo filter DAC anlog output.

115 AV

DD6 Analog power supply.

116 MON O 1, 0 Spindle motor on/off control output.

117 MDP O 1, Z, 0 Spindle motor servo control output.

118 MDS O 1, Z, 0 Spindle motor servo control output.

119 LOCK I/O 1, 0 GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.

If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high.

120 SSTP I Disc innermost track detection signal input.

121 DVss5 Digital GND.

122 DTS0 I Test pin. Normally fixed to low.

123 TES2 I Test pin. Normally fixed to low.

124 TES3 I Test pin. Normally fixed to low.

129 PWMI I Spindle motor external pin input.

130 DV

DD5 Digital power supply.

131 VCOO O 1, 0 Analog EFM PLL oscillation circuit output.

132 VCOI I Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.

43

* In the CXD3011R, the following pins are NC.

Pins 1, 18 to 21, 36, 37, 53 to 56, 72, 73, 89 to 92, 108, 109, 125 to 128 and 144.

Notes :

• The 64-bit slot is a LSB first, two’s complement output. The 48-bit slot is a MSB first, two’s complement
output.

• GTOP is used to monitor the frame sync protection status. (High : Sync protection window released)

• XUGF is the frame sync obtained from EFM signal, and is negative pulse. It is the signal before sync

protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM
signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)

• C2PO represents the data error status.

• XRAOF is generated when the 32K RAM exceeds the +28F jitter margin.

Pin No. Symbol I/O Description

133 TEST I Test pin. Normally fixed to low.

134 PDO O 1, Z, 0 Analog EFM PLL charge pump output.

135 VCKI I Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.

Set VCKI to low when the external clock is not input to this pin.

136 V16M O 1, 0 Wide-band EFM PLL VCO2 oscillation output.

137 AV

DD2 Analog power supply.

138 IGEN I Connects the operational amplifier current soource reference resistance.

139 AVss2

_

Analog GND.

140 ADIO O

_

Operational amplifier output.

141 RFDC I RF signal input.

142 CE I Center servo analog input.

143 TE I Tracking error signal input.

44

TROUBLESHOOTING GUIDE

Reset or Power ON.

• Check the power short.

• Check PC power cable, power

supply and fuse.

Repair PC power supply.

NO

Replace IC101 (3.3V Regulator).

Check the 6 , 7 pin of

IC402. (1.65V)

NO

YES

OK

Between 36 pin (VREF) of

IC301 and 4 pin (VC)

of IC301.

Replace IC402

OK

YES

Are the pin 38 ~ 42

of PN 701 +5V respectively

after the power cable

connecting?

Is the pin 1 of

IC102 3.3V?

Check the VREF line.

NO

Is the pin 36 of

IC201 1.65V?

Replace IC101 (3.3V Regulator).

NO

YES

YES

NO

Is the pin 3 of

IC101 3.3V?

Replace X401, and X301 when
the power supply of IC401 and
IC301 is OK.

NO

YES

Do the X401, and

X301 oscillating?

Replace IC501 when the IC101
(3.3V Regulator & Reset IC) is
non-ok.

NO

YES

Does the pin 63

of IC501 change 0V to 5V at

the power supply initial

input mode?

Refer to “Tray open / close
doesn’t work.”

NO

YES

Does the tray open or

close?

(Check it after connecting the power cable only no interface cable)

A

45

Refer to “Laser Diode is not on.”

A

NO

Refer to “Servo part is

abnormal”.

NO

YES

Is the Laser Diode

“ON”?

Does the Focus move

up and down?

Refer to “Disc Reading
operation is abnormal.”

NO

YES

Is the TOC area

on the disc read? (Does

the LED Blink?)

46

Check and replace the Eject
SW or peripheral resistor and
pattern short.

Tray open(eject) doesn’t work.

NO

YES

Does the

waveform appear at

the IC501 pin 89 when push

the SW602 (open/close)?

B

5V

Push period

Check and replace the R602,
or pattern short.

NO

Does the

waveform appear

at the R602 connected to

IC601 pin 4, that is connected

to IC601 reversely?

normal

Does the

signal appear

at the IC601 pin 10

and 11?

Pin 10

Pin 11

YES

Check and replace the IC301.

NO

Does the

IC301 pin 111

appear in the open(eject)

mode ?

YES

YES

Check the cold soldering for
the IC601 and then replace
IC601.

NO

47

B

Is the

connecting status normal

between the PN201

and sled(Feed)

motor?

Check the cold soldering for
the PN201 and FPC
connecting status and then
replace Sled(Feed) motor.

NO

YES

Open(eject) mode is normal.

48

Refer to “Reset or Power ON”.

Laser Diode is not ON.

YES

Check the cold soldering for
the IC201 and then replace
IC201.

Check the cold soldering for
the IC501 and then replace
IC501.

Check the cold soldering for
the transistor Q202 and then
replace Q202.

Replace the Pick-up.

YES

YES

NO

NO

NO

NO

CD PART

DVD PART

NO

Does the focusing

actuator move up and

down?

Is the PN201

pin 15 about 2V at the

initial power on mode?

Does the

signal appear at IC201

Pin 21?

Is the collector of

transistor Q202 about

2V?

YES

YES

Does the

signal appear at IC501

Pin 26?

C

3V

5V

0V

5V

LD ON

OK

49

C

Is the PN201

pin 9 about 2V

at the initial power on mode?

NO

NO

NO

YES

YES

Replace the Pick-up.

Check the cold soldering for
the transistor Q201 and then
replace Q201.

Does the

signal appear at IC201

Pin 22?

Is the collector of

transistor Q201 about

2V?

3V

5V

Check the cold soldering for
the IC201 and then replace
IC201.

Check the cold soldering for
the IC501 and then replace
IC501.

NO

YES

Does the

signal appear at IC501

Pin 26?

YES

OK

0V

5V

LD ON

50

• Check the cold soldering for

the IC301 pin 13, 14, 15, 16.

• Check the FPC connecting

status PN 201.

• Check the pick up.

Check the CD RF SIGNAL.

NO

YES

Does the RF out signal

output?

(IC301 pin 64 : CD RF)

• Check the cold soldering for

the C208, C212.

• Replace IC201.

NO

YES

Does the RF

signal output at the

IC201 Pin 57?

(RF Level : about 1.0V)

Check the cold soldering for the
C319.

NO

Does the

RF signal input to the

IC301 Pin 13?

51

• Check the cold soldering for

the IC201 pin 1, 2, 3.

• Check the FPC connecting

status PN201.

• Check the pick up.

Check the DVD RF signal.

NO

YES

Does the RF out signal

output from the pick-up?

(IC201 pin 1 : DVD RF)

•

Check the cold soldering for the

C215, C214, C218, C219, C220,
C221.

• Replace IC301.

NO

YES

Does the RF signal output

from the IC201 pin57?

(RF Level : about 1.0V)

Check the cold soldering for the
R404, C404 and IC401.

NO

Does the RF signal

output from the IC401

pin117?

52

Check the cold soldering for the
IC401 and then replace IC401.

Disc Rotation is unstable.

NO

YES

Does the spindle

motor kick signal and

driving signal output from

the IC401 pin135(SPD0)?

<Fig.1>

<Fig. 1>

Check the cold soldering for the
R604 , R607, R606, R611,
C604, C607 and IC601 and then
replace IC601.

NO

YES

Does the

spindle driving signal

output from IC601 normally?

(IC601 Pin 22)

<Fig.2>)

<Fig. 2>

Check the cold soldering for the
PN201 and connecting status
FPC.

NO

YES

Does the

PN201 spindle driving

signal output from pin31,32

normally? <Fig. 2>
(For CD and DVD)

Replace the Spindle motor.

53

Servo part is abnormal.

Insert a disc.

Refer to “Spindle motor

Rotation is failed”.

• Check the FPC connecting

status PN201.

• Check the cold soldering for

the pin 10, 11 of IC601.

Refer to “Laser Diode is not

ON”.

YES

YES

YES

YES

YES

YES

YES

YES

NO

NO

Check the cold soldering for the

IC301 and IC401.

A

B

NO

NO

NO

NO

NO

C

CD: CGFS

IC301 Pin 41

DVD: DGFS

IC401 Pin 107

Does the pick-up slide

inner track?

Does the disc rotate?

Is the Laser Diode on?

Does the focus move up

and down?

Is the FOK signal “H”?

(IC301 Pin 105)

Does the disc rotate in

high speed repeatedly?

Is the GFS signal “H”?

OK

54

Check the cold soldering for

the IC601(BA5918FP)

pin 13, 14.

Replace IC601.

Check the FG signal line.

Check the cold soldering for

the PN201(pin 33) and IC501

Pin 96, 97.

YES

NO

YES

A

B

NO

Check the circuit between the

IC601 Pin 24 and R601

and the IC301 Pin 113.

C

Check the FAO signal.

(IC301 Pin 113 )

Does the square wave

output at the PN201 Pin

33(FG)?

V

1.65V

T

Check the cold soldering for the

IC201 Pin 1, 38, 40, 63 and C215,

C217 and IC301 Pin 3, 141.

55

Check the spindle drive

signal.

(IC401 BA6664 Pin 22)

Check the cold soldering for

the IC601(BA5918FP) and

periphrals.

Replace the

IC601(BA5918FP).

Spindle Motor Rotation is

failed.

Check the MDP signal.
(IC401 CXD1867R Pin 135)

Check the cold soldering
for the IC401(CXD1867R).

Check the X-tal oscillating
(33.8688MHz) at the IC301
(CXD3011R) Pin 83 and 84.

Check the IC301
(CXD3011R) Pin 83, 84 and
99 (µ-com I/F line).

Check the cold soldering
for the IC501(H8/3062)
µ-com.

Check the cold soldering

for the IC601 (BA5918FP)

and PN201 Pin 27~33.

Check the Main FPC and

spindle motor ASS’Y.

Replace the Main FPC.

Replace the Spindle Motor

Ass’y.

NO

YES

YES

YES

NO

Does the above

signal output after the

tray close?

Does the above

signal output after the

tray close?

Is the disc rotation OK?

V

1.65V

100ms

NO

T

56

No Audio output.

Check the Line out cable.

Insert the audio disc.

YES

Check the MICOM IC501 pin 24

and R801.

NO

NO

YES

NO

Check the cold soldering for the

PN701, PN1~4.

YES

Mute on “L”.

Mute off “H”.

YES

YES

YES

Check the IC801 and

peripheral components.

NO

NO

Replace IC801

Replace R318, R317 and
R316.

NO

Check the servo part.

Does the

signal output at the

Line out?

Is the

pin 4 of IC801 is the

”High”?

Does the

Audio signal output at

the C802 and C808?

Does the

Audio signal inputted at pin 6, 7,

10, 11, of IC801?

Does the

Audio signal output at

IC301 pin 79,80 and

87, 88?

Does the

signal output at the

pin 27, 29 and 31 of

IC301?

72

Optical

Pick-up

KRS-202A/220C

Spindle

Motor

FCS

TRK

SLED

Motor

Tray

Motor

Laser

Power

S/H

17.43MHz

RF/Servo Signal

Timing Signals

OPC/ROPC

Circuit

Address/Data

M62352

12ch

8bit DAC

AT93C86

1kB

EEPROM

BA5983FM

F.T.S.T DRIVE

CXA2551R

RF Amp

Wobble

ALPC

CPLD

Laser Control

S/H Signal Gen.

20MHZ

H8/3062

System

Controller

33.86MHz

OTI9790

DSP+Servo

DECODER

ENCODER

ATIP Demodulator

Write Strategy

I/F

Data

2MB

DRAM

H

O

S

T

I/F

Cable

Audio

Mute

H/P Amp

L,R

L,R

Line Out

Headphone

Jack

BA6664FM

MOTOR DRIVE

BA5925

Sled

Speed

BLOCK DIAGRAM

1. Block Diagram of CD-R/RW Drive

73

From HOST

PN201

41 42 43 44

+12V

+5V

GND

GND

L101

Bead

L102

Bead

12V

8V

8V

IC512

NJM7808

Regulator

IC511

NJM7808

Regulator

IC501 BA5983

FCS/TRK/SLD/TRY

Driver

Act _Mute

IC201

OTI-9790

DSP/Servo

/ATAPI

/PRST

/UCS0, 1

URDY, URD, UWR

UA[0:8], UAD[0:15]

IC301

HD64F3062

µ-COM

IC101

XC61AN

RESET

IC102

BA033S

Regulator

IC103

BA3939

Regulator

3.3V

4V

(3.9V)

5V

IC401

CXA2551 ASP

2V

IC514

NJM3414

OP Amp

2V_ACT

2.5V

/RESET

/CXACS

SDATA, SCLK

SDATA, SCLK

SDATA, SCLK

/DACS

/EPCS

32

IC302

AT93C86

EEPROM

IC409

M62352

DAC

2. Power Block Diagram

74

W/XR, OSCEN,ENBL,ODON

WFPDSH, RFPDSH, WBLSH, SPDSH, MPDSH

A,B,C,D,E,F,G,H

IC401

CXA2551

ASP

MD

HA+/-

H1+/-,H2+/-

TRY+/-

SLD+/-

FCS+/-

TRK+/-

HU,HV,HW

U,V,W

EC

TRY CTL

SLD FG

MPXO

RECD1,2,XTOR

PHO1

RFRP,RFCT

ATFG

CE

TZC

TE

FE

IC403

NJM3404

IC404

NJM2903

IC412

TC7W08

IC414

NC7SZ66

IC403

NJM3404

IC411

NJM3404

EFM1,2,3

WGATE,LDON

EFCK,EEPS

TEBC

TE

TX

CE

WBLIN

RPBC

RX

BS

/UCS0,1,URDY,URD,UWR

UA[0:8],UAD[0:15]

IC301

HD64F3062

µ-COM

SLD_MOV

IC509

BA5925

Sled Speed

IC409

M62352,DAC

IC501

BA5983

Drive

IC510

BA6664

Drive

SPDL FG

DMO

FAO/TAO

SLO

IC601

XC9536

CPLD

IC201

OTI-9790

IC509

NJM3404

IC508

BU4053

3. System Control Block Diagram

75

A,B,C,D,E,F,G,H

FPDO

VRDC, VWC1

MD

WREF

RPOWER

VWDC2

IC409

M62352

DAC

/DACS

SDATA,SCLK

BETA,ASYM1,2

BLEBEL0

IC401

CXA2551

ASP

PHO1

RRFIN

RRF

EQRFN,EQRFP

W/XR,OSCEN,ENBL,ODON

WFPDSH,RFPDSH,WBLSH,SPDSH,MPDSH

ERGCNT,WBLON

IC403

NJM3403

IC413

EL2245CS

IC405

BU4052B

IC301

HD64F3062

µ-COM

/UCS0,1,URDY,URD,UWR

UA[0:8],UAD[0:15]

Lout

Line out

Rout

Q804

Mute Control

IC801

H/P Amp

H/P Out

RFDC(1V)

EFM(RFAC)

(1.2V)

BS

IC201

OTI-9790

EFM1,2,3

WGATE,LDON

EFCK,EEPS

IC601

XC9536

CPLD

4. Write/Read Block Diagram

76

CXA2551R
RF Amp.
Wobble
ALPC

OTI9790

DSP + Servo
DECODER
ENCODER
ATIP Demodulator
Write Strategy
I/F

33.86MHz
I/F

cable

H
O
S
T

Data

Data

Command

DRAM

CPLD

*Optical
Pick-up
KRS-202A/220C

Disc
Motor unit
GRS-R02A/
OSM-32A

Laser
Control

SPINDLE

MOTOR

FOCUS

COIL

TRACKING

COIL

SLED

MOTOR

LOADING

MOTOR

BA6664FM

MOTOR DRIVE

BA5983FM

F.T.S.F DRIVE

20MHz

Beta

H8/3062
System
Controller

AUDIO
Circuitry

RF

ROPC
Circuit

A1,A2, B Level

Headphone
Jack

R-ch

L-ch

Line-out

+8V

+5V

GND

GND

+12V

+5V

GND

GND

+12V

8V Reg.

3.3V Reg. +3.3V

+3.9V

3.9V Reg.

A B CD

1

2

3

4

5

5. Block Diagram

* CED-8080B : Optical Pick-up KRS-202A
* CED-8083B : Optical Pick-up KRS-220C

6

PBM00(MAIN C.B.A)˚

ABCD

1

2

3

4

5

436

436

436

001

012

011

013

006

007

008

010

009

435

435

435

435

435

436

436

005

004

003

A01

A00

EXPLODED VIEW