LG DRD-8160B Service Manual

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INTRODUCTION

GENERAL FEATURE

SPECIFICATIONS

1. SUPPORTED SYSTEM

• IBM Compatible Pentium 133MHz or Above (with PIO mode 4, TX chip set recommended)

2. SUPPORTED OS

3. GENERAL PERFORMANCE

• Data Transfer Rate ...........................................................................................Sustained Data Transfer Rate

DVD (Outer side) : Approx. 21,600 kbytes/sec DVD (Inner side) : Approx. 8,100 kbytes/sec CD (Outer side) : Approx. 7,200 kbytes/sec CD (Inner side) : Approx. 3,300 kbytes/sec

• Data Buffer Capacity.......................................................................................................................512 kbytes

• Access Time.................................................................Random Access DVD : 120ms Typical (16X)

CD : 100ms Typical (48X)

4. POWER REQUIREMENTS

• Voltage ........................................................................................................................................+5V DC +5%

+12V DC +5%

• Ripple .....................................................................................................................................+5V : 100mVp-p

+12V : 100mVp-p

• Current .........................................................................................+12V : 400mA (Average), 1.3A (Maximum)

+5V : 500mA (Average), 1.2A (Maximum)

5. AUDIO PERFORMANCE

• Frequency Response......................................................................................................20Hz~20KHz(+3dB)

• S/N Ratio (IHF-A+20kHZ LPF) ..........................................................................75 dB (Typical at 1 KHz 0dB)

70 dB (Limit at 1 KHz 0dB)

• T.H.D. (IHF-A+20kHZ LPF)...............................................................................0.05% (Typical at 1 KHz 0dB)

0.15% (Limit at 1 KHz 0dB)

• Channel Separation (IHF-A+20kHZ LPF) .................................................................................75 dB(Typical)

70 dB(Limit)

• Output Voltage (1kHz 0dB) 47KΩ Load ................................................................................0.75Vrms +

20%

• Headphone Level (1kHz 0dB) 33Ω Load...............................................................................0.75Vrms +

20%

• Enhanced IDE interface

• Internal 5.25 inch, halfheight DVD-ROM Drive

• 120ms (Typical) Random Access Time (DVD)

• 100ms (Typical) Random Access Time (CD)

• Supports 16X (max) Rotational Modes in DVD Mode

• Supports 48X (max) Rotational Modes in CD Mode

• Max 21,600 kB/sec Sustained Transfer rate in DVD mode

• Max 7,200 kB/sec Sustained Transfer rate in CD mode

• Photo-CD Multisession Disc Spec compliant

• DVD-R, DVD-RW, DVD dual (OTP, PTP) disc spec

compliant.

• Multimedia MPC-3 Spec compliant

• Power Tray Loading/Ejection Mechanism

• 3-Way Eject Support (Software, Open/Close Button,

Emergency Eject)

• Closed Enclosure

• Built-in ATAPI Interface Controller

• Software Volume Control

• Easy CD-Audio Play front panel Controls

• Front panel Volume Control for Headphone Output

• Built-in MODE-1 ECC/EDC

• MTBF (125,000H) POH (at 10% Utilization)

• PIO Mode 4 & Multiword DMA Mode 2 Support

• ULTRA DMA 33 support

• Horizontal/Vertical Mounting

• Digital audio output connector

• Digital audio through ATAPI Interface

• Spin-down Mode for energy saving

• MS-DOS (Ver 3.1 or Higher)

• Windows 3.1/95/98/2000/ME/XP

• Windows NT (Ver 4.0)

• OS/2 Warp (Ver 3.0)

• Solaris (Ver 2.4 or Higher)

• Linux ’96 Slacware (Ver 3.1.0)

This service manual provides a variety of service information. It contains the mechanical structure of the DVD-ROM Drive together with mechanical adjustments and the electronic circuits in schematic

form. This DVD-ROM Drive was manufactured and assembled under our strict quality control standards and meets or exceeds industry specifications and standards.

LOCATION OF CUSTOMER CONTROLS

(1) Digital Audio Ouput Connector

This is a digital audio output or Video CD output connector. You can connect this to a digital audio system or a Video CD Board.

(2) Analog Audio Output Connector

The Audio Output Connector connects to a sound card.

(3) Master/Slave/CSEL Jumper

These three jumpers are used to set the DVD-ROM Drive to either a Master, Slave, or CSEL device.

(4) Interface Connector

This 40-pin connector is used to transfer data and control signals between the DVD-ROM Drive and your PC.

(5) Power-in Connector

Attach a power cable from the computer to this connector.

ROM

COMPACT

43 5 6

FRONT VIEW

BACK VIEW

(1) Headphone Jack

Standard

″

(3.5mm) stereo jack for listening to the

audio signal from audio CDs.

(2) Headphone Volume Control

Adjusts the headphone sound level.

(3) Disc Drawer

Accepts a CD-ROM/DVD-ROM disc on its tray.

(4) Busy Indicator

The Busy Indicator lights during initialization and dataread operations.

(5) Emergency Eject Hole

Insert a paper clip here to eject the drawer manually or when there is no power.

(6) Open/Close/Stop Button

This button is pressed to open or close the CD tray. If an audio CD is playing, pressing this button will stop it, and pressing it

again will open the tray.

1. CABINET and CIRCUIT BOARD DISASSEMBLY

1-1. Bottom Chassis

A. Release 4 screws (A) and remove the Bottom

Chassis in the direction of arrow (1). (See Fig. 1-1)

1-2. Front Bezel Assy

A. Insert and Press a rod in the Emergency Eject

Hole and then the CD Tray will open in the direction of arrow (2).

B. Remove the Tray Door in the direction of arrow (3)

by pushing it outward.

C. Release 3 stoppers and remove the Front Bezel

Assy.

1-3. Cabinet and Main Circuit Board

A. Remove the Cabinet in the direction of arrow (4).

(See Fig. 1-3) B. Release 2 hooks (a) and remove the CD Tray. C. Remove the Soldering of the LD- and LD+ (B) for

the Loading Motor, and then remove the Main

Circuit Board. D. At this time, be careful not to damage the 3

connectors of the Main Circuit Board.

2. MECHANISM ASSY

2-1. Base Pick-Unit Assy

A. Separate the Base Pick-Up Unit Assy from the

MechanismAssy. B. Release 2 screws (C) and 1hook and then

remove the Base Pick-Up Unit Assy.

DISASSEMBLY

(A)

(1)

Bottom Chassis

Fig. 1-1

Fig. 1-2

Fig. 1-3

Fig. 2-1

Cabinet

(4)

Hooks (a)

(B)

Main

Circuit Board

Tray Door

(3)

Stoppers

(2)

Emergency Eject Hole

Front Bezel Assy

CD Tray

Base Pick-up Unit Assy

Hook

(C)

Mechanism Assy

INTERNAL STRUCTURE OF THE PICK-UP

1. Structure of the Pick-Up

CN14 DVD VCC CN05 DVD VC CN08 DVD GND

CN10 DVD A CN09 DVD B

CN11 DVD C CN12 DVD D

CN06 DVD RF+

CN07 DVD RF-

CN13 DVD GND

CN17 DVD VR

CN18 DVD MD CN15 DVD LD

CN16 DVD LD GND

CN01 F+ CN02 F-

CN03 T+

CN04 T-

CN28 CD VCC

CN19 CD VC

CN20 CD GND CN26 CD A

CN27 CD B CN24 CD C CN29 CD E CN30 CD F CN25 CD RF

CN22 CD VR

CN23 CD MD CN21 CD LD

C001

X1 X1

C002

C003

VR02

TRACKING

FOCUS

Differential RF outputs circuit

HFM

ACTUATOR

VR01

L004

L002

L003

C004

VCC

RF+

A B C D

RF-

GND

Ri Rf

L001

LASER DIODE

PICK-UP UNIT

1) Focus Error Signal –> (A + C) - (B+C)

• In case of CD Disc This signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s up and down to focus on CD Disc.

2) Tracking Error Signal (3-Beam Method) –> E - F

• In case of CD Disc This signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s left and right shift to find the track on CD Disc.

3) RF Signal –> A+B+2C

• In case of CD Disc This signal is converted to DATA signal in DSP IC (IC201 : MT1329).

2. Structure of the Photo Diode (CD)

Infrared laser

Pick-Up module

Photo Diode

Tracking

Focusing

(As seen from light

receiving side)

1) Focus Error Signal –> (A+C) - (B+D)

• In case of DVD Disc

This signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s up and down to

focus on DVD Disc.

2) Tracking Error Signal (DPD Method) –> Differential phase of (A+C) and (B+D)

• In case of DVD Disc

This signal is generated in RF AMP IC (IC301 : MT1326) and controls the pick-up’s left and right shift to find the track on DVD Disc.

3) RF Signal –> A+B+C+D

• In case of DVD Disc

This signal is converted to DATA signal in DSP IC (IC201 : MT1329).

3. Structure of the Photo Diode (DVD)

(As seen from light

receiving side)

Red laser

Pick-Up module

Photo Diode

Tracking

Focusing

MDI

70k

500

Vref

LD1CTL,LD2CTL

LDC1,LDC2

70k

LDO

(Vp is the central voltage of MD)

(Inside block of IC301)

DESCRIPTION OF CIRCUIT

1. ALPC (Automatic laser power control)

1-1. ALPC Circuit Constitution

Dual laser power control for DVD and CD are provided. The laser power for CD and DVD can be programmable by LD1CTL and LD2CTL and the lasers ON/OFF are controlled by LDC1 and LDC2 for CD and DVD, respectively. The following figure briefly describes the ALPC block. When the bit LDC1 is set low, the output voltage of LD0 will be pulled to VCC, hence the laser of CD will be turned off. Same manner is DVD laser control with LDC2 bit.

ALPC (Automatic laser plower control)

EFRFATN RFATN RFISEL

RFIGMSEL

GM VGA Equalizer

AGC

DPD

DVD/CD SW

direction

3BEAM TE

Central SERVO

Envelope Detector

RFOP

attenuator

RFON

HRFRP

DPFN

DPFO

TEO

FEO

CSO

(DVD)

DVDC

DVDB

DVDD

DVDA

CDFPI

CDFNI

TNI

TPI

RFGC

DVDRFIP

DVDRFIN

DVDD

DVDC

DVDB

DVDA

CDD

CDC

CDB

CDA

2. RF Amplifier Circuit

RF signal flow chart

2-1. INPUT STAGE

This block, including programmable attenuators and transconductors, is used for proper attenuation of input signals for different pick-up heads. Three input modes, defined by RFISEL are available for multiple inputs selection. Input mode also affects Gm, as definded by RFIGNSEL. The following table describes the relationship between input modes and selected Gm multiplicators. For example, if user chooses RFISEL =’10’(RFIN, RFIP) and RFIGMSEL =’11’( ), then effective GM is equal

to .4 = .

4∗K

1∗K

RFISEL1 RFISEL0 INPUT Multiplicator of Gm Input pins for DVD-ROM Input pins for CD-ROM

0 0 A,B,C,D

∗

1 DVDA,DVDB,DVDC,DVDD CDA,CDB,CDC,CDD

0 1 FEN FEP

∗

2 DVDRFIN, DVDRFIP CDC,CDD

1 0 RFIN RFIP

∗

4 DVDRFIN, DVDRFIP CDC, CDD

1 1 RFIN RFIP

∗

4 DVDRFIN, DVDRFIP CDC,CDD

For DVD_ROM mode, RF signal may be the sum of DVDA, DVDB, DVDC and DVDD which is also apply to DPD tracking error circuit. Furthermore, RF signal also can be obtained from pins DVDRFIN and DVDRFIP, which are the differential signals from OEIC, if the RF signal from OEIC is single-ended, it is all still available for mode ‘RFIN-RFIP’ by simply keeping DVDFIN floating. For CD_ROM mode, the differential RF inputs from OEIC may feed into pins CDC and CDD, which have the same function as DVDRFIN and DVDRFIP. It means that the function about ‘RFIN-RFIP’ mode in CD-ROM is the same as DVD_ROM except input pins being from CDC and CDD.

2-2. AGC (Automatic Gain Control) LOOP

AGC loop, as shown in Fig.1, is carried out for amplifying the RF signal from PDIC to a constant level at the output (RFON, RFOP). By controlling the gain of the GCA, the automatic gain control circuit holds the signal at the output (RFON, RFOP) at a constant level independent of the signal at GCA input. The GCA output signal level is determined by the DC voltage set on the pin RFGC. As the figure shown above, there are three AGC modes, defined by AGCMOD : AGC enable, RFGC DAC enable, and AGC hold. For ‘AGC enable’ mode, AGC loop is activated and user can apply different attack and decay bandwidth by programming IAGCDEC and IAGCATT respectively to optimize the system performance. For ‘RFGC DAC enable’ mode, a built in DAC, defined in RFGC], is utilized to perform the function of off-line AGC. Users can set the signal gain via programming the DAC after calculating the level of RFRP signal. For ‘AGC hold’ mode, RFGC pin becomes high impedance and the gain will keep almost at a constant level, even with low leakage current. Beside the AGC hold mode defined by AGCMOD, there is also a AGC hold function for defect protection. The destructive RF signal caused by defect may confuse the AGC function, one can hold AGC during this period by programming R[4].

2-3. EQUALIZER

This filter is intended to be used in the read channel of CD-ROM and DVD-ROM drivers with 8x constant linear velocity (CLV). As shown in following figure, the filter is placed in the automatic gain control (AGC) loop where it performs a dual role. It cuts off high frequency noise in the amplified read signal resulting in lower bit error rates.

For various operation speed, the filter cutoff frequency must be tunable over a wide range of about 3M45MHz. The second filter objective is to boost the high frequency component of RF signal which suffers from different MTF (modulation transfer function) from 14T to 3T. The equalizer uses two real zeros symmetric about the imaginary axis. The major requirement in the pulse equalizer design is phase linearity in the point of reducing intersymbol interference. In addition, the group delay must be independent of the amount of equalization to minimize jitter tolerance and be kept constant over 2*fc.

A tradition 7-pole 2-zero 0.05˚ equiripple type is determined for this filter design. In filter structure consideration, feedforward technique has been realized for its easy implementation instead of signal flow graph. Consequently, the control of cutoff frequency ƒcand boost gain can be easily accomplished in the second order section, included in this filter.

EFRFATN RFATN RFISEL

RFIGMSEL

Voltage DAC

Current DAC

comp

VGA Equalizer

Tracking

Top detector

Bottom Detector

DVDRF

Bottom Detector

RFOP

attenuator

RFON

HRFRP

CRTPLP

CRTP

LRFRP

DEFECT

RFGC

DVDRFIP

DVDRFIN

DVDD

DVDC

DVDB

DVDA

CDD

CDC

CDB

CDA

comp

Charge pump

Voltage DAC

RF signal flow chart

CDFPI

DVDFPI

1:CD

67k

134k

10k

FEON1

FELG (1Eh, b5)

10k

3~21.6k

FEG(1Eh,b4-0)

FEOS(0.8h,b4-0)

10k

67k

134k

10k

0:DVD

CDFNI

DVDFNI

IDACFE

FEO

33k

3. SERVO SIGNAL

3-1. FOCUSING ERROR

Block diagram is shown in following figure. the signal gain for focusing error is programmable by FEG. For

CD_RW and dual layer DVD_ROM applications, the amplitude of input signals are about one third of the one for normal CD_ROM and single layer DVD_ROM disk. Therefore, increasing the gain by three times, defined by FELG=0, is necessary for suitable gain range. In addition, the output voltage of FEO will suffer a offset voltage shift over normal operation range from semiconduction process. MT1326 provides a offset adjustment circuit comprising with FEOS. By programming IDACFE, it will generate an offset current flowing through external resistor R0, hence tuning the voltage of FEO back to the normal operation range. The offset voltage adjustment

is given as ∆V

offset

= -(I

DACFE

R0).

Focussing error

3-2. RF LEVEL (FLVL)

The signal FLVL which is the low-passed RF summing signal is used to indicate the focusing status for DVDROM mode, as shown in following figure. It also has the gain and offset programmability by LVLG and LVLOS, respectively.

CDFPI

DVDFPI

1:CD

54.5p

27.5p

67k

134k

10k~72k

32p

FLVLNI

FELG (1Eh, b5)

10k~72k

67k

134k

27.5p

54.5p

10k

0:DVD

CDFNI

DVDFNI

LVLG(1Fh, b4-0)

LVLS(09h, b4-0)

IDACFE

1: CD 0: DVD

FLVL

33k

SBAD

RF Level signal generator

CDCSPI

DVDCSPI

1:CD

54.5p

27.5p

67k

134k

10k

32p

CSON1

FELG (1Eh, b5)

10k

67k

134k

27.5p

54.5p

10k

0:DVD

CDCSNI

DVDCSNI

CSOS(0Ah, b4-0)

IDACFE

1 : CSO 0 : REO

CSO SEL (01h)

CSO

33k

TEO

3-3. CENTRAL SERVO

This signal is for central servo application. It is also a one beam push-pull tracking error signal. User can

select either CSO or TEO as the output signal through output pin CSO by programming ‘CSOSEL’.

CSO signal generator

TPI

1:CD

54.5p

27.5p

67k

35k

134k

TEG

3k~21.6K

10k

FLVLNI

TELG (21h, b5)

3k~21.6k

TEB(0Bh, b4-0)

8.4~15.2K

TEB(0Bh, b4-0)

8.4~15.2K

67k

35k

134k

27.5p

54.5p

16k

0:DVD

TNI

CSOS(0Ah, b4-0)

IDAC

FLVL

(SBAD)

33k

32k

SBAD

If select CD then FLVL output is SBAD

SABDOS (97h,b4-0)

3-4. SBAD (SUB_BEAM ADD)

The SBAD signal, the summing signal of both satellite PDs, is applied toward monitoring the focusing status for CD-ROM mode. The gain parameters setting for this signals is the same as 3-beam tracking error by TEGAIN. Offset cancellation DAC, defined SBADOS, is also required.

Sub beam Adder

TPI

1:CD

54.5p

27.5p

67k

134k

TEG 3k~21.6K

TEB (0Bh, b4-0)

8.4~15.2K

TELG (21h, b5)

3k~21.6k

11.8k

32k

33k

47P

32k

16k

11.8k

TEB(0Bk, b4-0)

8.4~15.2K

TEOS (06h,b5-0)

67k

35k

134k

27.5p

54.5p

0:DVD

1:CD 0:DVD

IDAC

35k

TNI

DPD

DVDA

DPFO

DPFN

TEO

DVDB DVDC DVDD

3-5. TRACKING ERROR

Two tracking error, 3-beam tracking error and DPD (differential phase detection), are available for CD_ROM and DVD_ROM, respectively. The block diagram is shown in following figure. For 3-beam tracking error, one can select different gain by TEGAIN, as well as adjust the gain ratio between these two satellite signals by TEBAL for unbalance compensation in satellite PDs. For DVD_ROM mode, the tracking error signals is switched to DPD automatically.

Tracking error

Time

multiplexed

A/D

Parallel

digital

compensator

High pass

filter

FE_hpf

Focus

algorithm

D/A

FOO

RFLEVEL

FEI

199

198

3-6. FOCUS SERVO

Focus servo system

Focus search diagram

The focus servo system is shown on the above figure. The focus servo system is used to search the focus point of disk, and following that point a parallel digital compensator is used to control the focus actuator. The focus error signal (FEI) is sampled at 176.4kHz with an 8-bit flash A/D converter, then it is subtracted by FE, offset and is fed into the digital compensator. The digital compensator will output the result to FOO pin with a 10-bit D/A converter (FOO). Both A/D and D/A operate within the range from 0 to 2Vref.

The DSP commands FACTION82hw, FSET83hw FLEVEL184hw and FLEVEL285hw are the associated commands for the focus loop control. The following figure is the typical focus search timing.

TFOK

TFNG

FOK

FOON

RFLEVEL

FOKL

FONL

Vref

FE_hpf

FEI

Time

multiplexed

A/D

Track number

counter &

Timer

Short

seek

Alogrithm

Parallel

digital

compensator

D/A

PWM

Sled

compensator

TEI

FMO

TEZC

RFZC

TRO

196

3-7. TRACKING AND SHORT SEEK SERVO SYSTEM

Tracking servo system

The tracking servo system shown as the above figure is used to follow track center of disk. In addition, there is a short seeking control block built in to move the lens from 0 to 2000 tracks. Two compensators are used to control the dual actuator (track and sled) servo system. The tracking error signal (TEI) is sampled at 176.4 kHz with an 8-bit flash A/D converter. It is then subtracted by TE-offset, which is generated from auto-calibration, added by SB_hpf, and fed into the digital compensators. The results of the compensators will output to TRO and FMO pins with a 10-bit D/A and an 8-bit PWM generator. Both the A/D and D/A operate within the range from 0 to 2Vref, and the PWM generator operator operates from 0 to PWM2Vref.

The MT1329 supports actuator central servo control while cooperated with MT1326 RF chip. The TEI input of the MT1329 is connected to the CSO output of MT1326. When the central servo function is active, the MT1326 will select push-pull signal as CSO output during tracking off state (seeking) and select tracking error signal as CSO output during tracking on state (following). So the MT1329 uses push-pull signal to control tracking servo during seeking state and tracking compensator will let actuator to keep at central location around on pickup head. This will enhance the stability of the DVD-ROM/CD-ROM system when it changes from seeking state to following mode.

The initial tracking on can be done by using jump 0 track (SEEKSET4OFFW with 0000h and TACTION90hw), for the short seek unit provides high gain mode, peak hold brake, and quick seek-to-follow switching method. The short seek control unit is implemented with velocity control feedback to move tracking and sled actuator. As long as the target track reached, it will switch to tracking control mode to enter the close loop. In order to reduce the settling time, it will switch to high gain mode automatically and issue a peak hold brake to enter the steady state_as soon as possible.

The DSP commands are the associated commands for the track loop control.

The micro controller can be programmed to focus search as follows:

1. Light laser on through the MT1326.

2. Move object lens up or down by using the FACTION command. If object lens moves too slowly or it doesn’t cross focus point, try to adjust FSR or coefficient Kfsrch.

3. Normally FEI will have an S-shaped waveform. With the high pass filter to reduce offset voltage, the signal FE_hpf will be used to do the focus search.

4. After the absolute value of FE_hpf exceeds the level FONL, it will wait to enter focus servo loop (FOON flag

1) as long as FE_hpf reaches the zero-cross point.

5. If the focus compensator is robust enough and RFLEVEL signal is higher than level FOKL, focus servo will enter a steady state and count the time for the steady state. As long as the duration for RFLEVEL higher than the level FOKL exceed TFOK, the focus OK flag FOK will be set to indicate the focus servo is well locked.

6. IF the RFLEVEL signal is lower than the level FOKL for the duration longer than TFNG, both the FOON and FOK flags will be reset to indicate the system loses the focus point. The both flags can be monitored through the flag pins.

TEZI

TEZC

TEZILP

Tracking error zero crosing for seek control

As the above figures shows, the TEZC is the output of the comparator that compares the TEZI with its slice

level that is the output of the external low pass filter.

DESCRIPTION OF DATA PROCESSING

1. Data Processing Flow

Command

Data

Status

RF EQ & AGC

SERVO

DSP

Decoder & CSS

RF data slice EFM demodulator

CiRC error correction

Audio DAC

C3 decoder

Buffer/Memory controller

CSS controller

Atapi interface control

Data PLL

Servo ADC

Focus/tracking

control output

Sled control output

CAV Spindle control

P-up

Unit

IC601

(motor drive)

IC301

RF AMP

(MT1326)

IC201

DSP

(MT1329)

TE/CSO GEN

FE GEN

FLASH ROM

DRAM

MT1329

HOST DVD

PLAYER

(MPEG2 B/D)

Scrambled MPEG Data

Change the "KEY"

KEY Management Control

2. Copy Protection and Regional Code Management Block

Block Diagram

Brief Process

1. Regional Code for DVD Disc

– DVD-ROM drive transfers the regional code of the control data to host by the command of host, the DVD

player of host reads the regional code, and plays title in the case of allowed regional code only.

2. Management of DVD Disc for the scrambled of data

(1) DVD-ROM and DVD player of host generate the “KEY 1” respectively, transfer to opposite part, the

“KEY 2” is received, recognizes the data transfer or not with this value, and generates the bus key

encoded the data. (2) Encoded “Disc Key” and “Title Key” host is transfer with the bus Key. (3) DVD player of host reads the key value, and uses the value to restore the scrambled data.

* Refer to the next page for the details.

3. About Prevention the DVD-ROM from to be copy

A data is able to encode and record in the disc, if a copyright holder wants to prevent the disc from copying.

In case of a disc enhanced movie of 3 titles......

DISC KEY (2048 Bytes) is used to encode the whole contents in the disc and TITLE KEY (5 Bytes) is used to encode the title respectively. So, the data is encoded and stored in a disc through the unknown algorithms with a disc key and title key. (At this time, the disc key and title key are stored in a disc.)

…As above, the disc is able to copy when the disc key and title key are

opened. Then, ROM-DRIVE encodes the disc key and title key and transfers to MPEG2 board.

If you want to play the disc prevented from the copy......

First of all, ROM-DRIVE and MPEG-2 board identify with each other through the procedure as described below.

1. Drive and host gives and takes the ID of 2bit. This ID is AGID (Authentication Grant ID). The various decoder boards are attached to the host, in these, AGID sets the MPEG-2 board and drive.

2. After the AGID is set, MPEG-2 board generates the challenge key (10 Byte) and transfers to drive. The board and drive generate key 1 (5Byte) with the challenge key respectively. (Of course, the Algorithm generating the key 1 is not known.)

3. Compare with the generated key 1, if it corresponds each other, the first step of authentication is completed. This is a course to identify the MPEG-2 board with a drive.

4. The second step of authentication is a course to identify a drive with the MPEG-2 board. The dirve generates a challenge key and transfers it to the MPEG-2 board. The dirve and MPEG-2 board generate the key 2 (5Byte) with the challenge key, compare with each other, and if it corresponds and the secondary step of authentication is completed.

5. As above, the identification is completed.

6. The dirve and MPEG-2 board generate the Bus key with the key 1 and key 2 and own it.

7. Dirve encodes the disc key and title key with this Bus key and transfers to the MPEG-2 board.

8. The MPEG-2 board reads the encoded disc key and title key with the Bus key only.

9. MPEG-2 board lets data read from the drive to decode with the read disc key and title key and makes into the video signal by decoding.

ROM-DRIVE

AGID

HOST

MPEG-2 BOARD

Challenge key

encoded disc key, title key

4. About the DVD-ROM Regional Code

DISC ROM - DRIVE MPEG-2 BOARD VGA CARD

MONITOR

CAN

U.S.A

MIX

CUB

BHS

PRI. VIR

BMG

GRL

ZAF ISO SWZ

FIN

POI

FST

LTU

BIR

UKR

TUR

FGY

JRN

TKM

AFG

PAK

CHN

MMR

MNG

RUS

KOR

JPN

HKG

MAC

TWN

PHL

MDI

MNP

GUM

PLW

PNG

NZL

AUS

The disc has the regional code of 8 bit.

Example)

The disc manufactured in the U.S.A, has the number one.

Transfer to MPEG-2 board reading the regional code.

Receiving data from the MPEG-2 board and output through the monitor

If the board is setting to the regional

code 1 for the U.S.A. ...

Check the received regional code to number 1, all or not, transfer the data to VGA card in accordance with only a case among the three case.

Regional code

IC301 (MT1326) : RF Signal Processing for CD/DVD

It amplifies or equalize the RF signal from Pick-up, and generate the TE (Tracking Error) and FE (Focus Error) signal for Servo respectively. The TE signal uses the DPD (Differential Phase Detect) method for DVD and 3 Beam method for CD. DVD FE = (A+C) - (B+D)

CD FE = E - F

Block Diagram

MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN

DESCRIPTION

ATTENUATOR

DVDA

VGA EQ

ENVELOP

DETECTOR

AGC

DPD

SBAD

3 BEAM

LEVEL

CENTRAL

SERVO

SERIAL

PORT

APC

DVD APC

REF and 2VREF

Voltage Generator

OSP

OSN

RFOP

RFON

LRFRP

DEFECT

HRFRP

CRTP

CRTPLP

FLVLNI

FLVL

TEO

FEO

FEONI

CSO

CSONI

MDI2

LDO2

MDI1

LDO1

SD ATA

SLCK

SDEN

CDA

DVDB

CDB

DVDC

CDC

DVDD

CDD

DVDRFIN

DVDRFIP

RFGC

DPFN

DPFO

DPDMUTE

TPI TNI

CDFNI

CDFPI

DVDFNI

DVDFPI

CDCSNI

CDCSPI

DVDCSNI

DVDCSPI

V2REFO

VREFO

IC301 (MT1326)

• Pin Description

Pin Numbers Symbol Type Description

QFP100 and LQFP100

RF Flag Interface

14 DEFECT Digital output Flag of bad data output status

RF SIO interface

15 SLCK Digital input RF serial clock input

16 SDEN Digital input RF serial data enable

17 SDATA Digital IO RF serial data IO

12 RST Digital input Reset (active high)

13 XCK16M Digital input 16.9MHz for verification

40 DVDA Analog input DVD RF signal input A

41 DVDB Analog input DVD RF signal input B

42 DVDC Analog input DVD RF signal input C

43 DVDD Analog input DVD RF signal input D

38 DVDRFIN Analog input DVD RF signal input RFIN

39 DVDRFIP Analog input DVD RF signal input RFIP

53 CDA Analog input CD RF signal input A

54 CDB Analog input CD RF signal input B

55 CDC Analog input CD RF signal input C

56 CDD Analog input CD RF signal input D

61 OSP Analog Offset cancellation capacitor connecting

60 OSN Analog Offset cancellation capacitor connecting

86 RFOP Analog output RF positive output

85 RFON Analog output RF negative output

59 RFGC Analog RF VGA control

TRACKING ERROR

88 DPFN Analog DPD amplifier negative input

87 DPFO Analog DPD amplifier output

24 IR Analog DPD reference resister connecting

18 DPDMUTE Digital input DPD mute control input

83 TNI Analog input 3 beam satellite PD signal input

82 TPI Analog input 3 beam satellite PD signal input

97 TEO Analog output Tracking error output

Pin Numbers Symbol Type Description

FOCUSING ERROR & RF LEVEL & CENTRAL SERVO SIGNAL

64 CDFNI Analog input CD focusing error negative input

65 CDFPI Analog input CD focusing error positive input

44 DVDFNI Analog input DVD focusing error negative input

45 DVDFPI Analog input DVD focusing error positive input

95 FEO Analog output Focusing error output

96 FEONI Analog input Focusing error amplifier negative input

93 FLVL Analog output RF level output

94 FLVLNI Analog input RF level amplifier negative input

69 CDCSNI Analog input CD central servo signal negative input

70 CDCSPI Analog input CD central servo signal positive input

46 DVDCSNI Analog input DVD central servo signal negative input

47 DVDCSPI Analog input DVD central servo signal positive input

2 CSO Analog output Central servo signal output

3 CSONI Analog input Central servo amplifier negative input

ALPC

80 MDI1 Analog input Laser power monitor input

81 LDO1 Analog output Laser driver output

51 MDI2 Analog input Laser power monitor input

52 LDO2 Analog output Laser driver output

RF RIPPLE

9 CRTP Analog RF top envelop filter capacitor connecting

10 CRTPLP Analog Defect level filter capacitor connecting

8 HRFRP Analog output High frequency RF ripple output

7 LRFRP Analog output Low frequency RF ripple output

POWER

25,26,30,34,62,63 AVDD Power RF power

22,23,29,37,57,58 AGND GND GND

89,90 SVDD Power Servo analog power

98,99 SGND GND GND

5, 6 VDD Power Digital power

19,20 GND GND GND

REFERENCE VOLTAGE

92 VREFO Analog output Reference voltage 2.0V

91 V2REFO Analog output Reference voltage 4.0V

Pin Numbers Symbol Type Description

ALPC TRIMMING

32 TM1 Analog input Trimming pin for ALPC1

33 TM2 Analog input Trimming pin for ALPC1

35 TM3 Analog input Trimming pin for ALPC2

36 TM4 Analog input Trimming pin for ALPC2

HIGH SPEED TRACK COUNTING

1 TRLP Analog Low_pass filter capacitor connecting

100 TRLPA Analog Low_pass filter capacitor connecting

11 HTRC Digital output High speed track counting digital output

PCS

79 HALLSIN Analog input Negative input of amplifier for hall sensor signal

78 REFSIN Analog input Positive input of amplifier for hall sensor signal

77 SINPHI Analog output Amplifier output for hall sensor signal

76 HALLCOS Analog input Negative input of amplifier for hall sensor signal

75 REFCOS Analog input Positive input of amplifier for hall sensor signal

74 COSPHI Analog output Amplifier output for hall sensor signal

FOR MONITOR ONLY

27 MON Analog output

28 MOP Analog output

31 VCON Analog output

21 HTRCMPH Digital output

84 HTE Analog output

71 SWO Analog output Output from mux of SW1&SW2

72 SW2 Analog input External input for servo input select

73 SW1 Analog input External input for servo input select

IC201 (MT1329) : LSI processing for DVD-ROM Drive Signal

Block Diagram

RFZC/

TEZC

Circuit

RFRPSLV

TEZI

TEZISLV

HRFZC

ADCVDD

FEI

TEI

RFRP_DC

RFRP_AC

RFLEVEL

ADIN

ADCVSS

SLCK

SDEN

SDATA

FOO

TRO

FMO

PWMOUT1

PWMOUT2

PDMVDD

PWM2VREF

PWMVREF

PDMVSS

FLAGA

FLAGB

FLAGC

FLAGD

IO[3:0]

VPVDD

VCDCIN

VPVSS

ENDM

DMO

DACVREF

DACVDD

DACVSS

ADGO

HD[15:0]

PDIAG#

DASP#

HRST#

DIOW#

DIOR#

DMACK#

HA[2:0]

CS1FX#

CS3FX#

DMARQ

IORDY

INTRQ

IOCS16#

URST

UINT#

UPSEN#

UALE

UAD[7:0]

UP2_7-UP2_0

UA[7:0]

UA16

UWR#

URD#

UP3_5-UP3_4

UP3_2-UP3_0

IO4-IO9

RF Flag

Interface

Data

Slicer

Data

PLL

Sync

protection

CIRC/RSPC

Error Corrector

CDROM

Sync Detection

Descrambler

Audio/Effect

Interface

Audio

Digital Out

CSS Host

Data

FIFO

ATAPI

Packet

FIFO

Micro-controller/

MPEG command

I/F

8032

Mega

Interface

Key/LED

Interface

TROPENPWM

TRCLOSE

TRAYIN#

LED

PLY#/PAU#

EJ/STOP#

BA[1:0]

DQM

CLK

CKE

ROE#

RWE#

CASH#/RWEH#

CAS#

RAS#

RA[11:0]

RD[15:0]

PRST#

TEST

DMVSS DMVDD

IPLLVSS IPLLVDD XTALI

XTALO

JITFO VBDPLL LPIO LPFO PDO

JITFN PLLVSS LPIN LPFN IREF PLLVDD

RFIP RFIN

SCO RFDTSLV

BDO

LIMIT#

TRAYOUT#

256

SRAM

Host/MPEG A/V Interface

CDROM High-speed

Audio Playback

Decoder

Varipitch System

Clock

Generator

System Clock

DRAM

Clock

Generator

Reset

Logic

Buffer

Memory

Controller

EFM/EFM+

Demodulator

Subcode/ID

Demodulator

CLV/CAV

Controller

PWM

DAC

Varipitch

CLV Clock

Generator

Flags &

Program-

mable I/O

PDM &

PWM

DAC

Serial RF

Controller

Servo

ADC

Servo

DSP

Pin Numbers Symbol Type Description

RF data PLL interface

11 PLLVDD Power Power for data PLL and related analog circuitry.

10 JITFN Analog Input The input terminal of RF jitter meter.

9 JITFO Analog Output The output terminal of RF jitter meter.

8 PDO Analog Output Phase comparator output. Output the phase

difference of EFM and Pck. Sink or (source) a constant current to loop filter over this pin when phase difference occurs. Otherwise, this pin is high impedance.

7 IREF Analog Input Current reference input. It generates reference

current for data PLL. Connect an external 100K resistor to this pin and PLLVSS.

6 LPFN Analog Input The negative input terminal of loop filter amplifier.

5 LPFO Analog Output The output of loop filter amplifier.

4 LPIN Analog Input The negative input terminal of VCO intergrator.

3 LPIO Analog Ouput The output of VCO intergrator.

‘ 2 PLLVSS Ground Ground pin for data PLL and related analog circuitry.

1 VBDPLL Analog Output Reference voltage.

208 RFIN Analog Input The negative input terminal of RF differential signal.

207 RFIP Analog Input The positive input terminal of RF differential signal.

206 RFDTSLV Analog Output RF data slicer level output

205 SCO Analog Output Analog slicer current output. This pin is active when

TRONS=1, Otherwise this pin is high impedence.

Signal Amplifier Interface

204 ADCVDD Power Power pin for ADC circuitry.

203 HRFZC Analog Input High frequency RF ripple zero crossing.

202 RFRPSLV Analog Input RFRP slice level input.

201 RFRP_AC Analog Input RF ripple detect input (through AC-coupling)

200 RFRP_DC Analog Input RF ripple detect input.

199 RFLEVEL Analog Input Sub beam add input or RFRP low pass input.

198 FEI Analog Input Focus error input.

197 CSO Analog Input Central servo input.

196 TEI Analog Input Tracking error input.

195 TEZISLV Analog Input Tracking error zero crossing low pass input.

194 ADIN/IN0 Analog Input General A/D input/General digital input

193 ADCVSS Ground Ground pin for ADC circuitry.

Motor and Actuator Driver Interface

192 PDMVSS Ground Ground for PDM circuitry.

191 PWM2VREF Analog Input A reference voltage input for PWM circuitry. A typical

value of 4.0v.

IC201 (MT1329)

• Pin Description

Pin Numbers Symbol Type Description

190 PWMVREF Analog Input A reference voltage input for PWM circuitry. A typical

value of 2.0v.

189 PDMVDD Power Power for PDM circuitry.

12 FOO Analog Output Focus servo output. PDM output of focus servo

compensator.

13 TRO Analog Output Tracking servo ouput. PDM output of tracking servo

compensator.

14 PWMOUT1 Analog Output 1stGeneral PWM output.

15 PWMOUT2 Analog Output 2ndGeneral PWM output.

17 DMO Analog Outout Disk motor control output. PWM output.

18 FMO Analog Output Feed motor control. PWM output.

19 TROPENPWM Analog Output Tray open control output.Controlled by µP.

20 FG

CMOS 3.3V Input,

Motor Hall sensor input

Schmitt Input, pull up

22 TRCLOSE CMOS 3.3V Tray close output.

Output, 4mA

169 ENDM CMOS 3.3V Enable/disable disk motor. A logical high enable disk

Output, 4mA motor.

Panel Interface

168 LED CMOS 3.3V LED control output controlled by µP.

Output, 4mA

167 PLY#/PAU#

CMOS 3.3V Input,

Play/pause key input, active low.

166 EJ/STOP#

CMOS 3.3V Input,

Eject/stop key input, active low.

165 LIMIT#

CMOS 3.3V Input,

Sledge inner limit input, active low.

164 TRAYOUT#

CMOS 3.3V Input,

Tray_is _out input. A logical low indicates the tray is out. Feedback flag from tray connector.

163 TRAYIN#

CMOS 3.3V Input,

Tray_is_in input, A logical low indicates the tray is in. Feedback flag from tray connector.

Micro controller Interface

24 UALE TTL 5V I/O, Address Latch Enable.

25-33 UAD[7:0] CMOS 3.3V I/O, µP Address/Data Bus.

4mA

35 UP2_7 CMOS 3.3V I/O µP Upper Address Bus/µP Chip Select 2(for Internal

/UCS2 pull up, 4mA RAM)

36 UP2_6 CMOS 3.3V I/O, µP Upper Address Bus/µP Chip Select 1 (for Internal

RAM)

37-42 UP2_5 ~ CMOS 3.3V I/O, µP Upper Address Bus

Schmitt Input,

pull up, 4mA

/UCS1

UP2_0

Schmitt Input, pull up

Pin Numbers Symbol Type Description

44-51 UA[7:0] CMOS 3.3V I/O µP Lower Address Bus.

pull up, 4mA

54 UA16/UP1_0 CMOS 3.3V I/O Default : UP1_0 for general programmable I/O

4mA, pull up Downflash, µP Address Bit 16.

55 UPSEN# CMOS 3.3V I/O, Programmable Store Enable Output.

56 UWR# CMOS 3.3V I/O, µP Write Strobe.

57 URD# TTL 5V I/O, µP Read Strobe.

58 URST TTL 5V Output, Reset signal output active high.

4mA

59 UP3_0 TTL 5V I/O, pull Serial receive data/General Programmable I/O.

up, 4mA

60 UP3_1 TTL 5V I/O, pull Serial transmit data/General Programmable I/O

4mA

61 UP3_2 TTL 5V I/O, Pull External interrupt 0/General Programmable I/O.

up, 4mA

63 UP3_4 TTL 5V I/O, pull Timer 0 Input/General Programmable I/O

up, 4mA

64 UP3_5 TTL 5V I/O, pull Timer 1 Input/General Programmable I/O

up, 4mA

178-180 IO6~IO4 CMOS 3.3V I/O, General Programmable I/O

4mA Alternate function:

IO4:pull up IO4: Serial clock.Default is input. IO5: pull down IO5: Serial receives data. Default is input. IO6: pull down IO6:Serial transmits data. Default is output =0.

176 IO8/CS# CMOS 3.3V I/O, General Programmable I/O, Alternate function:Chip

select signal for flash ROM selection. (When in IDE update flash ROM mode), active low. Default is output=0.

23 UA17/UP1_1 CMOS 3.3V I/O, Default : UP1_1 for general Programmable I/O

pull up, 4mA Downflash : µP Address Bit 17.

62 UINT# Open Drain 5V µP Interrupt

Output, 8mA

Crystal Interface & DRAM clock Interface

52 DMVSS Ground Ground pin for DRAM clock circuitry.

53 DMVDD Power Power pin for DRAM clock circuitry.

66 XTALI Crystal Input X’tal input. The working frequency is 33.8688MHz.

67 XTALO Crystal Output X’tal output.

Memory Interface

69 DQM

CMOS 3.3V Output,

SDRAM Input/Output Mask. Default is 4mA.

Current programmable

Schmitt Input,

pull up, 4mA

Schmitt Input,

pull up, 4mA

Schmitt Input,

pull up, 4mA

pull down, 4mA

Pin Numbers Symbol Type Description

70 BA1 CMOS 3.3V Output, SDRAM Bank Address 1. Default is 4mA.

Current programmable

71 BA0 CMOS 3.3V Output, SDRAM Bank Address 0. Default is 4mA.

Current programmable

72 CKE CMOS 3.3V Output, SDRAM Clock Enable. Default is 4mA.

Current programmable

73 CLK CMOS 3.3V Output, SDRAM Clock. Default is 4mA.

Current programmable

74, 75 RA[11:10] CMOS 3.3V Output, RAM Address Bus[11:10]. Default is 4mA.

Current programmable

77-83, 85, RA[9:0] CMOS 3.3V Output, RAM Address Bus[9:0]. Default is 4mA.

86, 88 Current programmable

89 RAS# CMOS 3.3V Output, RAM Row Address Strobe. Default is 4mA.

Current programmable

90 ROE# CMOS 3.3V Output, RAM Output Enable. Default is 4mA.

Current programmable

91 RWE# CMOS 3.3V Output, RAM Write Enable (Low). Default is 4mA.

Current programmable

92 CASH#/RWEH# CMOS 3.3V Output, RAM Colume Address Strobe/Write Enable

Current programmable High. Default is 4mA.

93 CAS# CMOS 3.3V Output, RAM Colume Address Strobe(Low).

Current programmable Default is 4mA.

95-103, RD[15:0] CMOS 3.3V I/O, Current RAM Data Bus. Default is 4mA. Default is pull

up.

Audio Output Interface

114 ADGO TTL 5V Output, Audio digital output

4mA

115 DACVSS Ground Ground pin for internal DAC circuitry

116 RO Analog Output Audio DAC Right output

117 DACVREF Analog output Reference Voltage for External Audio Filter

Circuit

118 LO Analog Output Audio DAC Left Output

119 DACVDD Power Power Pin for Internal DAC circuitry

System Clock Interface

104 IPLLVDD Power Power pin for system varipitch circuitry.

105 IPLLVSS Ground Ground pin for system varipitch circuitry.

Host Interface

120 DASP# TTL 3.3V Input, Drive active/Slave present.

Schmitt Input, pull up

121 CS3FX# TTL 3.3V Input, Host chip select 2 (for 3Fxh/37xh)

Schmitt Input, pull up

122 CS1FX# TTL 3.3V Input, Host chip select 1 (for 1Fxh/17xh)

Schmitt Input, pull up

programmable, pull up,

pull down programmable

106-113

Pin Numbers Symbol Type Description

124, 125, 127 HA[2:0] TTL 3.3V Input, Host Address Bus.

Schmitt Input, pull up

126 PDIAG# TTL 3.3V Input, Passed Diagnostics

Schmitt Input, pull up

129 IOCS16# TTL 3.3V Output, I/O 16-bit Chip Select

10mA

130 INTRQ TTL 3.3V Output, Host Interrupt

10mA

131 DMACK# TTL 3.3V Input, DMA Acknowledge

Schmitt Input, pull up

132 IORDY TTL 3.3V Output, I/O Channel Ready

10mA

133 DIOR# TTL 3.3V Input, Drive I/O Read

Schmitt Input, pull up

135 DIOW# TTL 3.3V Input, Drive I/O Write

Schmitt Input, pull up

136 DMARQ TTL 3.3V Output, DMA Request

10mA

137-155 HD[15:0] TTL 3.3V I/O, Schmitt Host Data Bus, Default is 6mA. Default is pull

up.

157 HRST# CMOS 3.3V Input, Host Reset.

Schmitt Input, pull up

CLV Varipitch Interface

159 VPVDD Power Power pin for varipitch VCO circuitry.

160 VCOCIN Analog Input Connect capacitor for compensator loop filter.

161 VPVSS Ground Ground pin for vapipitch VCO circuitry.

Miscellaneous

158 PRST CMOS 3.3V Input, Power-On Reset.

Schmitt Input, pull down

162 TEST CMOS 3.3V Input, Test mode Pin.

Schmitt Input, pull down

Flag and Programmable I/O Interface

171 FLAGD CMOS 3.3V I/O,4mA The internal flags of servo DSP can be

selected to output over FLAGD pin. Default is output=0.

172 FLAGC CMOS 3.3V I/O,4mA The internal flags of servo DSP can be

selected to output over FLAGC pin. Default is output=0.

173 FLAGB CMOS 3.3V I/O,4mA The internal flags of servo DSP can be

selected to output over FLAGB pin. Default is output=0.

Pull down, 4mA

input, current

programmable, pull up,

pull down programmable

Pin Numbers Symbol Type Description

174 FLAGA CMOS 3.3V I/O, The internal flags of servo DSP can be selected to

output over FLAGA pin. To program the selection µP must write FLGMOD register. Default is output =0.

Alternate function: Internal or External µP select, “1”: use external µP (i.e. ICE mode determined by power on reset) and disable internal µP.

181 IO3 CMOS 3.3V I/O, Programmable I/O or internal non-servo flags output.

Default is input.

182 IO2 CMOS 3.3V I/O, Programmable I/O or internal non-servo flags output.

Default is input.

183 IO1 CMOS 3.3V I/O, Programmable I/O or internal non-servo flags output.

Default is input.

184 IO0 CMOS 3.3V I/O, Programmable I/O or internal non-servo flags output.

Default is input.

RF SIO interface & Defect

185 SDATA CMOS 3.3V I/O, RF serial data output

Schmitt Input, 4mA

186 SDEN CMOS 3.3V RF serial data latch enable

Output, 4mA

187 SLCK CMOS 3.3V RF serial clock output

Output, 4mA

188 BDO CMOS 3.3V Input, Flag of defect data input status

Schmitt Input,

pull down

Digital Power & Ground

34, 65, 84, 94, DVDD3 Power +3.3V digital supply

123,128,156,170

16,76,177 DVDD Power

+5V digital supply

21, 29, 43,68, DVSS Ground digital ground

87,101,134,140,

146,151,175

Pull down, 4mA

Pull up, 8mA

Pull up, 4mA

4mA

Pull up, 8mA

IC601 (M63022FP): Drive IC

VMI

Reverse Detect

120 MATRIX

HU+ HUHV+

HVHW+

HWHB

SPIN

REF

SL1 IN

SL2IN

FOIN

TOIN

5VCC

5V power supply

TO+

TO-

FO+

FO-

LO+

LO-

VM3

LOIN+

BRS

OSC

MU1

SL2-

SL2+

RSL2

VM2

SL1-

SL1+

RSL1

RSP

VM1

GND

X12

Hall Bias

CIL amp.

Current comp.

Logic

TSI

BIAS

Frequency generator

CTL amp.

Direction comp.

Regulator

• Pin Description

Block Diagram

Terminal SYMBOL TERMINAL FUNCTION

1 SL1IN Slide control voltage input 1. 2 SL2IN Slide control voltage input 2.. 3 VM2 Motor Power Supply 2(for Slide) 4 RSL2 Slide current sense 2. 5 SL2+ Slide non-inverted output 2 6 SL2- Slide inverted output 2 7 GND GND 8 RSL1 Slide current sense 1

9 SL1+ Slide non-inverted output 1 10 SL1- Slide inverted output 1 11 GND GND 12 W Motor drive output W 13 V Motor drive output V 14 U Motor drive output U 15 RSP Spindle current sense 16 HW- HW- sensor amp. input 17 HW+ HW+ sensor amp. input 18 HV- HV- sensor amp. input 19 HV+ HV+ sensor amp. input 20 HU- HU- sensor amp. input 21 HU+ HU+ sensor amp. input

Terminal SYMBOL TERMINAL FUNCTION

22 VM1 Motor power Supply 1(for Spindle) 23 HB Bias for Hall Sensor 24 FG Frequency generator output 25 REF Reference voltage input 26 SPIN Spindle control voltage input 27 FOIN Focus control voltage input 28 TOIN Tracking control voltage input 29 GND GND 30 5VCC 5V Power Supply (for FS. TS) 31 TO- Tracking inverted output 32 TO+ Tracking non-inberted output 33 GND GND 34 FO+ Focus non-inverted output 35 FO- Focus inverted output 36 LO+ Loading non-inverted output 37 LO- Loading inverted output 38 BRS Brake select control terminal 39 VM3 Motor Power Supply 3 (for Loading) 40 LOIN+ Loading control input (+) 41 MU1 mute 1 42 OSC PWM carrier oscillation set

TROUBLESHOOTING GUIDE

Reset or Power ON.

• Check the power short.

• Check PC power cable, power

supply and fuse.

Repair PC power supply.

YES

Are the pin 44

and 41 of CN 201 +5V and +12V

respectively after the power

cable connecting?

Replace IC101 (3.3V Regulator).

Is the pin 3 of

IC101 3.3V?

Replace X201 when the power supply of IC201 is OK.

YES

Do the X201

oscillating?

YES

Refer to “Tray open / close doesn’t work.”

Does the tray open or

close?

(Check it after connecting the power cable only no interface cable)

Refer to “Laser Diode is not on.”

Refer to “Servo part is

abnormal”.

YES

Is the Laser Diode

“ON”?

Does the Focus move

up and down?

Refer to “Disc Reading operation is abnormal.”

YES

Is the TOC area

on the disc read? (Does

the LED flicker?)

Check and replace the SW403 or peripheral resistor and pattern short.

Tray open/close doesn’t work.

YES

Does the

waveform appear at

the IC201 pin 163, 164 when

push the SW403 (open/close)?

Push period

Check and replace the R622, R625 or pattern short.

Does the

waveform appear

at the R622 connected to

IC201 pin 19?

open

normal

Does the

signal appear

at the IC601 pin 36

and 37?

closing period

Pin 37

Pin 36

opening period

YES

Check and replace the IC201.

Does the

IC201 pin 163 and

164 appear in the tray

open/close mode ?

YES

Check the cold soldering for the IC601 and then replace IC601.

Is the

connecting status normal

between the CN301

and loading motor?

Check the cold soldering for the CN301 and wire connecting status and then replace loading motor.

YES

Open/close mode is normal.

Refer to “Reset or Power ON”.

Laser Diode is not ON.

YES

Check the cold soldering for the IC301 and then replace IC301.

Check the cold soldering for the transistor Q301 and then replace Q301.

Replace the Pick-up.

YES

CD PART

DVD PART

Does the focusing

actuator move up and

down?

Is the PN301

pin 16 about 2.3V at the

initial power on mode?

Does the

signal appear at IC301

Pin 52?

Is the collector of

transistor Q301 about

2V?

YES

3.8V

Is the PN301

pin 10 about 2V

at the initial power on mode?

YES

Replace the Pick-up.

Check the cold soldering for the transistor Q302 and then replace Q302.

Does the

signal appear at IC301

Pin 81?

Is the collector of

transistor Q302 about

2V?

3.7V

Check the cold soldering for the IC301 and then replace IC301.

YES

• Check the cold soldering for

the IC301 pin 53, 54, 55, 56.

• Check the FPC connecting

status PN 301.

• Check the pick up.

Check the CD RF SIGNAL.

YES

Does the RF out signal

output?

(IC301 pin 86 : CD RF)

Check the cold soldering for the C234, C233.

Does the

RF signal input to the

IC201 Pin 207?

• Check the cold soldering for

the IC302 pin 40, 41, 42, 43.

• Check the FPC connecting

status PN301.

• Check the pick up.

Check the DVD RF signal.

YES

Does the RF out signal

output from the pick-up?

(IC301 pin 86 : DVD RF)

Check the cold soldering for the C234, C233.

Does the RF signal

output from the IC201

pin207?

Servo part is abnormal.

Insert a disc.

Refer to “Spindle motor

Rotation is failed”.

• Check the Flat cable

connecting status PN601.

• Check the cold soldering for

the pin 5, 6, 9, 10, of IC601.

Refer to “Laser Diode is not

ON”.

YES

Check the RF signal flow.

Does the pick-up slide

inner track?

Does the disc rotate?

Is the Laser Diode on?

Does the focus move up

and down?

Is the FEO signal “H”?

(IC201 Pin 198)

Does the disc rotate in

high speed repeatedly?

Is the RF signal Good?

Check the cold soldering for

the IC601pin 34, 35.

Replace IC601.

Check the FG signal line.

Check the cold soldering for

the IC601.

YES

Check the circuit between the

IC201 Pin 12

and the IC601 Pin 27.

Check the FOSO signal at the R207 connected to

IC201 pin 12.

Does the square wave

output at the IC601 Pin 24

(FG)?

1.35V

Check the cold soldering for the

IC301 pin95 and R234 and IC201

pin 198.

Check the spindle drive

signal.

(IC601 Pin 26)

Check the cold soldering for

the IC201 pin 17.

Replace the IC201.

Spindle Motor Rotation is

failed.

Check PN601.

Check the cold soldering for the PN601.

Replace the spindle Motor.

Reassembled PN601.

YES

Does the above

signal output after the

tray close?

Is the PN601

assembled ‘OK’?

Is the disc rotation OK?

2.2-2.4V

No Audio output.

Check the headphone jack and

cable.

Insert the audio disc.

YES

Check the DSP IC201 pin 179.

YES

Replace IC401.

YES

Check the cold soldering for the VR401, R412, R413, R406 and

R407.

YES

Check the IC401 and

peripheral components.

YES

Replace IC201

Check the cold soldering for the CN301 and connector CN401.

Check the peripheral parts

between the pin 97, 99 of

IC201 and CN301 pin 3, 6.

Does the

signal output at the

headphone jack?

Is the

Pin 2 of IC401 is 5V?

Does the

Audio signal output at

the C409 and C408?

Does the

Audio signal output at

the C403 and C404?

Does the

Audio signal inputted at pin 3, 6,

of CN401?

Does the

Audio signal output at

IC201 pin 116, 118?

Does the

signal output at the pin

Pin3, 6 of CN301?

A B CD

BLOCK DIAGRAM

Focus

actuator

Driv e

Tracking

actuator

Driv e

Slide

motor

Driv e

M63022FP

Audio Signal

Processor

Spindle

motor

Driv e

AGC

MT1316F(RF Amplifier)

HOST COMPUTER

Spindle motor

Optical Pick up

Slide motor

SF-HD3SS

DVD PLL

DVD SERVO DSP

Decoder/

CSS & ATAPI

Interface

Equalizer

APC

CD PLL

CD SERVO DSP

MT1318F(DSP&interface)

Latch

74HC373)

Focus

actuator

Driv e

Tracking

actuator

Driv e

Slide

motor

Driv e

M63022FP /M63023FP

Audio Signal

Processor

Spindle

motor

Driv e

AGC

MT1326F(RF Amplifier)

HOST COMPUTER

Spindle motor

Optical Pick up

Slide motor

SF-H

DVD PLL

DVD SERVO DSP

Decoder/

CSS & ATAPI

Interface

Equalizer

APC

CD PLL

CD SERVO DSP

MT1329F(DSP&interface)

Flash Rom

(SST39SF010)

DRAM

(M11B416256A)

PBM00 (MAIN C.B.A)

007

002

003

030

020

A02

A01

A03

020

051

028

050

029

434

021

434

413

001

413

430

028

027

026

025

024

435

033

434

010

009

008

011

012

005

034

013

434

017

016

015

004

006

022

021

430

A B C D E F GH

014

7 8

EXPLODED VIEW

LG DRD-8160B Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual