LG 84LM960V-W-ZB User Manual

Internal Use Only

North/Latin America http://aic.lgservice.com Europe/Africa http://eic.lgservice.com Asia/Oceania http://biz.lgservice.com

LED LCD TV

SERVICE MANUAL

CHASSIS : LD23E

MODEL : 84LM960V/W 84LM960V/W-ZB

CAUTION

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67361007 (1209-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 15

EXPLODED VIEW .................................................................................. 24

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks.

It will also protect the receiver and it's components from being damaged by accidental shorts of th e cir cuitry that may be inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exp ose d metallic par t. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication. NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions on page 3 of this publication, always follow the safety precautions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power source before;

a. Removing or reinstalling any component, circuit board mod-

ule or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug or

other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver. CAUTION: A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion hazard.

2. Test high voltage only by measuring it with an appropriate high voltage meter or other voltage measuring device (DVM, FETVOM, etc) equipped with a suitable high voltage probe. Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its assemblies.

4. Unless specied otherwise in this service manual, clean electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable non-abrasive applicator; 10 % (by volume) Acetone and 90 % (by volume) isopropyl alcohol (90 % - 99 % strength) CAUTION: This is a ammable mixture. Unless specied otherwise in this service manual, lubrication of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its electrical assemblies unless all solid-state device heat sinks are correctly installed.

7. Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this service manual. CAUTION: Do not connect the test xture ground strap to any heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES devices are integrated circuits and some eld-effect transistors and semiconductor “chip” components. The following techniques should be used to help reduce the incidence of component damage caused by static by static electricity.

1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test.

2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.

4. Use only an anti-static type solder removal device. Some solder removal devices not classied as “anti-static” can generate electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material).

7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will be installed. CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted oor can generate static electricity sufcient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle. Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F) b. Heat the component lead until the solder melts. c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand against

the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there only until the solder ows onto and around both the component lead and the foil. CAUTION: Work quickly to avoid overheating the circuit board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

Only for training and service purposes

- 4 -

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through which the IC leads are inserted and then bent at against the circuit foil. When holes are the slotted type, the following technique should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by gently prying up on the lead with the soldering iron tip as the solder melts.

2. Draw away the melted solder with an anti-static suction-type solder removal device (or with solder braid) before removing the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and solder it.

3. Clean the soldered areas with a small wire-bristle brush. (It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor Removal/Replacement

1. Remove the defective transistor by clipping its leads as close as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding leads extending from the circuit board and crimp the "U" with long nose pliers to insure metal to metal contact then solder each connection.

Power Output, Transistor Device Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as possible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit board.

3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder.

3. Solder the connections. CAUTION: Maintain original spacing between the replaced component and adjacent components and the circuit board to prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil to separate from or "lift-off" the board. The following guidelines and procedures should be followed whenever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board. (Use this technique only on IC connections).

1. Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern at connections other than IC Pins. This technique involves the installation of a jumper wire on the component side of the circuit board.

1. Remove the defective copper pattern with a sharp knife. Remove at least 1/4 inch of copper, to ensure that a hazardous condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern break and locate the nearest component that is directly connected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the nearest component on one side of the pattern break to the lead of the nearest component on the other side. Carefully crimp and solder the connections. CAUTION: Be sure the insulated jumper wire is dressed so the it does not touch components or sharp edges.

Fuse and Conventional Resistor Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow stake.

2. Securely crimp the leads of replacement component around notch at stake top.

Only for training and service purposes

- 5 -

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This specification is applied to the LCD TV used LD23E chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

ea ch drawing and s pe cificatio n b y p art number in accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

- Wireless : Wireless HD Specification (Option)

4. Model General Specification

No. Item Specication Remarks

1 Market EU(PAL Market-36Countries) DTV & Analog (Total 37 countries)

DTV (MPEG2/4, DVB-T) : 30 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus,

2 Broadcasting system 1) PAL-BG/DK/I/I’

2) SECAM L/L’, DK, BG, I

3) DVB-T/T2, C, S/S2

DTV (MPEG2/4, DVB-T2) : 7 countries

UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan

DTV (MPEG2/4, DVB-C) : 37 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan

DTV (MPEG2/4, DVB-S/S2) : 30 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan

DVB-S: Satellite

Only for training and service purposes

- 6 -

No. Item Specication Remarks

3 Receiving system Analog : Upper Heterodyne

Digital : COFDM, QAM

4 Input Voltage AC 100 ~ 240V 50/60Hz

► DVB-T

- Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32

- Modulation : Code Rate QPSK : 1/2, 2/3, 3/4, 5/6, 7/8 16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2

- Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,

- Modulation : Code Rate QPSK : 1/2, 2/5, 2/3, 3/4, 5/6 16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C

- Symbolrate :

4.0Msymbols/s to 7.2Msymbols/s

- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2

- symbolrate DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s DVB-S (QPSK) : 2 ~ 45Msymbol/s

- viterbi DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8 DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10

Only for training and service purposes

- 7 -

5. Component Video Input (Y, Cb/Pb, Cr/Pr)

No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock

1. 720×480 15.73 60.00 SDTV, DVD 480i

2. 720×480 15.63 59.94 SDTV, DVD 480i

3. 720×480 31.47 59.94 480p

4. 720×480 31.50 60.00 480p

5. 720×576 15.625 50.00 SDTV 576i

6. 720×576 31.25 50.00 SDTV 576p

7. 1280×720 45.00 50.00 HDTV 720p

8. 1280×720 44.96 59.94 HDTV 720p

9. 1280×720 45.00 60.00 HDTV 720p

10. 1920×1080 31.25 50.00 HDTV 1080i

11. 1920×1080 33.75 60.00 HDTV 1080i

12. 1920×1080 33.72 59.94 HDTV 1080i

13. 1920×1080 56.250 50 HDTV 1080p

14. 1920×1080 67.5 60 HDTV 1080p

6. RGB input (PC)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed

PC DDC

1 640*350 31.468 70.09 25.17 EGA Х

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 80 VESA (WXGA)

7 1360*768 47.712 60.015 85.5 WUXGA O

8 1920*1080 67.5 60.00 148.5 WUXGA(CEA861D) O

Only for training and service purposes

- 8 -

7. HDMI Input

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC Proposed

HDMI-PC DDC

1 640*350 31.468 70.09 25.17 EGA Х

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 80 VESA

7 1280*1024 63.981 60.020 108 VESA(SXGA) O

8 1360*768 47.712 60.015 85.5 VESA(WXGA) O

9 1920*1080 67.5 60.00 148.5 WUXGA(CEA861D) O

10 3840*2160 67.5 30.00 297.00 UD

11 3840*2160 56.25 25.00 297.00 UD

12 3840*2160 54.0 24.00 297.00 UD

HDMI-DTV

1 640*480 31.469 / 31.5 59.94/ 60 25.125 1 SDTV 480P

2 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 SDTV 480P

3 720*576 31.25 50 27 17,18 SDTV 576P

4 720*576 15.625 50 27 21 SDTV 576I

5 1280*720 37.500 50 74.25 19 HDTV 720P

6 1280*720 44.96 / 45 59.94 / 60 74.17/74.25 4 HDTV 720P

7 1920*1080 33.72 / 33.75 59.94 / 60 74.17/74.25 5 HDTV 1080I

8 1920*1080 28.125 50.00 74.25 20 HDTV 1080I

9 1920*1080 26.97 / 27 23.97 / 24 74.17/74.25 32 HDTV 1080P

10 1920*1080 25 33 HDTV 1080P

11 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 34 HDTV 1080P

12 1920*1080 56.250 50 148.5 31 HDTV 1080P

13 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 16 HDTV 1080P

14 3840*2160 67.5 30.00 297.00 UDTV 2160P

15 3840*2160 56.25 25.00 297.00 UDTV 2160P

16 3840*2160 54.0 24.00 297.00 UDTV 2160P

Only for training and service purposes

- 9 -

8. 3D Mode

8.1. RF Input(3D supported mode manually)

No. Resolution Proposed 3D input proposed mode

1 HD

2 SD

1080I 720P

576P

576I

8.2. RF Input(3D supported mode automatically)

No. Signal 3D input proposed mode

1 Frame Compatible

Side by Side(Half), Top & Bottom

8.3. HDMI Input

8.3.1. HDMI 1.3 (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P

2 1280*720 37.500 50 74.25 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I

4 1920*1080 28.125 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

6 1920*1080 28.12 25 74.25 HDTV 1080P

7 1920*1080 33.75 30.00 74.25 HDTV 1080P

8 1920*1080 56.25 50 148.5 HDTV 1080P

9 1920*1080 67.50 60.00 148.5 HDTV 1080P

10 3840*2160 67.5 30.00 297.00 UDTV 2160P 2D to 3D only

11 3840*2160 56.25 25.00 297.00 UDTV 2160P 2D to 3D only

12 3840*2160 54.0 24.00 297.00 UDTV 2160P 2D to 3D only

2D to 3D Side by Side(Half) Top & Bottom

2D to 3D

2D to 3D Side by Side(half), Top & Bottom, Single Frame Sequential

2D to 3D Side by Side(half), Top & Bottom

2D to 3D Side by Side(half), Top & Bottom, Checkerboard

2D to 3D Side by Side(half), Top & Bottom, Checkerboard, Single Frame Sequential, Row Interleaving, Column Interleaving

Only for training and service purposes

- 10 -

8.3.2. HDMI 1.4b (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed

1

640*480

2 62.938/63 59.94/ 60 50.35/50.4 1

3 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)

4

720*480

5 62.938/63 59.94 / 60 54/54.06 2,3

6 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)

7

720*576

8 62.5 50 54 17,18

9 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)

10

720*576

11 31.25 50 54 21

12 15.625 50 54 21 Side-by-side(Full) (SDTV 576I)

13

14 75 50 148.5 19

15 37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P)

1280*720

16 44.96 / 45 59.94 / 60 74.18/74.25 4

17 89.91/90 59.94 / 60 148.35/148.5 4

18 44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)

19

20 67.432/67.50 59.94 / 60 148.35/148.5 5

21 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)

1920*1080

22 28.125 50.00 74.25 20

23 56.25 50.00 148.5 20

24 28.125 50.00 74.25 20 Side-by-side(Full) (HDTV 1080I)

25

26 43.94/54 23.97 / 24 148.35/148.5 32

27 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)

28 28.12 25 74.25 33

29 56.24 25 148.5 33

1920*1080

30 28.12 25 148.5 33 Side-by-side(Full) (HDTV 1080P)

31 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34

32 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34

33 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)

34 56.250 50 148.5 31

35 67.43 / 67.5 59.94 / 60 148.35/148.50 16

31.469 / 31.5 59.94/ 60 25.125 1

31.469 / 31.5 59.94 / 60 27.00/27.03 2,3

31.25 50 27 17,18

15.625 50 27 21

37.500 50 74.25 19

33.72 / 33.75 59.94 / 60 74.17/74.25 5

26.97 / 27 23.97 / 24 74.18/74.25 32

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Frame packing Field alternative

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Frame packing Field alternative

Top-and-Bottom Side-by-side(half)

Frame packing Field alternative

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Frame packing Line alternative

Top-and-Bottom Side-by-side(half)

Secondary(SDTV 480P) Secondary(SDTV 480P)

Secondary(SDTV 480P) (SDTV 480P)

Secondary(SDTV 480P) Secondary(SDTV 480P)

Secondary(SDTV 480P) (SDTV 480P)

Secondary(SDTV 576P) Secondary(SDTV 576P)

Secondary(SDTV 576P) (SDTV 576P)

Secondary(SDTV 576I) Secondary(SDTV 576I)

Secondary(SDTV 576I) (SDTV 576I)

Primary(HDTV 720P) Primary(HDTV 720P)

Primary(HDTV 720P) (HDTV 720P)

Primary(HDTV 720P) Primary(HDTV 720P)

Primary(HDTV 720P) (HDTV 720P)

Secondary(HDTV 1080I) Primary(HDTV 1080I)

Primary(HDTV 1080I) (HDTV 1080I)

Secondary(HDTV 1080I) Primary(HDTV 1080I)

Primary(HDTV 1080I) (HDTV 1080I)

Primary(HDTV 1080P) Primary(HDTV 1080P)

Primary(HDTV 1080P) (HDTV 1080P)

Secondary(HDTV 1080P) Secondary(HDTV 1080P)

Secondary(HDTV 1080P) (HDTV 1080P)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

Primary(HDTV 1080P) (HDTV 1080P)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

Only for training and service purposes

- 11 -

8.4. HDMI-PC Input (3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

2D to 3D,

1 1024*768 48.36 60 65

2 1360*768 47.71 60 85.5

3 1920*1080 67.500 60 148.50

4 Others - - - 2D to 3D

Side by Side(half) Top & Bottom

2D to 3D, Side by Side(half) Top & Bottom

2D to 3D, Side by Side(half) Top & Bottom, Checker Board, Single Frame Sequential, Row Interleaving, Column Interleaving

HDTV 768P

HDTV 1080P

640*350 720*400 640*480 800*600 1152*864

8.5. RGB-PC Input (3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

2D to 3D,

1 1024*768 48.36 60 65

2 1360*768 47.71 60 85.5

3 1920*1080 67.500 60 148.50

4 Others - - - 2D to 3D

Side by Side(half) Top & Bottom

2D to 3D, Side by Side(half) Top & Bottom

HDTV 768P

HDTV 1080P

640*350 720*400 640*480 800*600 1152*864 1280*1024

Only for training and service purposes

- 12 -

8.6. Component Input(3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock 3D input proposed mode Proposed

2D to 3D,

1 1280*720 37.5 50 74.25

2 1280*720 45.00 60.00 74.25

3 1280*720 44.96 59.94 74.176

4 1920*1080 33.75 60.00 74.25

5 1920*1080 33.72 59.94 74.176

6 1920*1080 28.12 50 74.25

7 1920*1080 67.500 60 148.50

8 1920*1080 67.432 59.94 148.352

9 1920*1080 27.000 24.000 74.25

10 1920*1080 28.12 25 74.25

11 1920*1080 56.25 50 74.25

12 1920*1080 26.97 23.976 74.176

13 1920*1080 33.75 30.000 74.25

14 1920*1080 33.71 29.97 74.176

Side by Side(half), Top & Bottom

2D to 3D, Side by Side(half), Top & Bottom

HDTV 720P

HDTV 1080I

HDTV 1080P

Only for training and service purposes

- 13 -

8.7. USB Input(3D) (3D supported mode manually)

R

L

R

L

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

2D to 3D Side by Side(Half), Top & Bottom,

1 1920*1080 33.75 30 74.25

Checkerboard, Row Interleaving, Column Interleaving (Photo : side by Side(half), Top & Bottom)

HDTV 1080P

8.8. USB Input(3D) (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

Side by Side(Half),

1 1920*1080 33.75 30 74.25

Top & Bottom, Checkerboard, MPO(photo)

HDTV 1080P

8.9. DLNA Input (3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

2D to 3D Side by Side(Half), Top & Bottom,

1 1920*1080 33.75 30 74.25

Checkerboard, Row Interleaving, Column Interleaving (Photo : side by Side(half), Top & Bottom)

HDTV 1080P

8.10. DLNA Input (3D) (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

Side by Side(Half),

1 1920*1080 33.75 30 74.25

■ Remark: 3D Input mode

No. Side by Side Top & Bottom Checker board

1

Single Frame

Sequential

- 14 -

Only for training and service purposes

Top & Bottom, Checkerboard, MPO(photo)

Frame Packing

Line

Interleaving

HDTV 1080P

Column

Interleaving

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to all of the LED LCD TV with LD23E chassis.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument. (2) Adjustment must be done in the correct order. (3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz. (5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15.

In case of keeping module is in the circumstance of 0 °C, it should be placed in the circumstance of above 15 °C for 2 hours.

In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15 °C for 3 hours.

[Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area.

3. Automatic Adjustment

3.1. ADC Adjustment

3.1.1. Overview

ADC adjustment is needed to find the optimum black level and gain in Analog-to-Digital device and to compensate RGB deviation.

3.1.3. Adjustment

(1) Adjustment method

- Using RS- 232, ad just items in the other shown in "3.1.3.3)"

(2) Adj. protocol

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change

Begin adj. ad 00 10

Return adj. result

Read adj. data

Conrm adj. ad 00 99

End adj. aa 00 90 a 00 OK90x

xb 00 04 xb 00 06

(main) ad 00 20

(sub ) ad 00 21

b 00 OK04x (Adjust 480i, 1080p Comp1 ) b 00 OK06x (Adjust 1920*1080 RGB)

OKx (Case of Success) NGx (Case of Fail)

(main) 000000000000000000000000007c007b006dx

(Sub) 000000070000000000000000007c00830077x

NG 03 00x (Fail) NG 03 01x (Fail) NG 03 02x (Fail) OK 03 03x (Success)

Ref.) ADC Adj. RS232C Protocol_Ver1.0

(3) Adj. order

- aa 00 00 [Enter ADC adj. mode]

- xb 00 04 [Change input source to Component1 (480i& 1080p)]

- ad 00 10 [Adjust 480i&1080p Comp1]

- xb 00 06 [Change input source to RGB(1024*768)]

- ad 00 10 [Adjust 1920*1080 RGB]

- ad 00 90 End adj.

3.2. MAC address D/L, CI+ key D/L, Widevine key D/L

Connect: PCBA Jig → RS-232C Port== PC → RS-232C Port Communication Prot connection

3.1.2. Equipment & Condition

(1) USB to RS-232C Jig (2) MSPG-92 5 Series Pattern Generat or(MSPG-925FA,

pattern - 65)

- Resolution : 480i Comp1 1080P Comp1 1920*1080 RGB

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7 ± 0.1 Vp-p

- Image

Only for training and service purposes

- 15 -

▪ Com 1,2,3,4 and 115200(Baudrate) Mode check: Online Only ▪ Check the test process: DETECT → MAC → CI → Widevine

→ ESN ▪ Play: START ▪ Result: Ready, Test, OK or NG ▪ Printer Out (MAC Address Label)

3.3. LAN Inspection

3.3.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

3.3.2. LAN inspection solution

▪ LAN Port connection with PCB ▪ Network setting at MENU Mode of TV ▪ Setting automatic IP ▪ Setting state confirmation

→ If automatic setting is finished, you confirm IP and MAC

Address.

3.4. LAN PORT INSPECTION(PING TEST)

Connect SET → LAN port == PC → LAN Port

SET PC

3.4.1. Equipment setting

(1) Play the LAN Port Test PROGRAM. (2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

3.4.2. LAN PORT inspection(PING TEST)

(1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. (4) Remove LAN cable.

3.3.3. WIDEVINE key Inspection

- Confirm key input data at the "IN START" MENU Mode.

3.5. Model name & Serial number Download

3.5.1. Model name & Serial number D/L

▪ Press "Power on" key of service remote control.

(Baud rate : 115200 bps)

▪ Connect RS232 Signal Cable to RS-232 Jack. ▪ Write Serial number by use RS-232. ▪ Must check the serial number at Instart menu.

3.5.2. Method & notice

(1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory by D-book 4.0.

Only for training and service purposes

- 16 -

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes model name or serial number is initialized.(Not always) It is impossible to download by bar code scan, so It need Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name(ex 47LM960V-ZB) or Serial number like photo.

4) Check the model name Instart menu. → Factory name displayed. (ex 47LM960V-ZB)

5) Check the Diagnost ics.(DTV country only) → Buyer model displayed. (ex 47LM960V-ZB)

3.6. CI+ Key checking method

- Check the Section 4.2 Check whether the key was downloaded or not at ‘In Start’ menu. (Refer to below).

3.6.2. Check the method of CI+ key value(RS232)

1) Into the main ass’y mode(RS232: aa 00 00)

CMD 1 CMD 2 Data 0

A A 0 0

2) Check the mothed of CI+ key by command (RS232: ci 00 20)

CMD 1 CMD 2 Data 0

C I 2 0

3) Result value i 01 OK 1d1852d21c1ed5dcx

CI+ Key Value

3.7. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command

H-freq(kHz) V-freq.(Hz)

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

(2) Check the menu on in-start

=> Check the Download to CI+ Key value in LGset.

3.6.1. Check the method of CI+ Key value

(1) Check the method on Instart menu (2) Check the method of RS232C Command

1) Into the main ass’y mode(RS232: aa 00 00) CMD 1 CMD 2 Data 0

A A 0 0

2) Check the key download for transmitted command

(RS232: ci 00 10)

CMD 1 CMD 2 Data 0

C I 1 0

3) Result value

- Normally status for download : OKx

- Abnormally status for download : NGx

Only for training and service purposes

- 17 -

4. Manual Adjustment

* ADC adjustment is not needed because of OTP(Auto ADC

adjustment)

▪ Reference

- HDMI1 ~ HDMI4 / RGB

- In the data of EDID, bellows may be different by S/W or Input mode.

4.1 EDID(The Extended Display Identification Data)/DDC(Display Data Channel) download

4.1.1. Overview

It is a VESA regulation. A PC or a MNT will display an optimal resolution through information sharing without any necessity of user input. It is a realization of "Plug and Play".

4.1.2. Equipment

- Since embedded EDID data is used, EDID download JIG, HDMI cable and D-sub cable are not need.

- Adjustment remote control

4.1.3. Download method

(1) Press "ADJ" key on the Adjustment remote control then

select "10.EDID D/L", By pressing "Enter" key, enter EDID D/L menu.

(2) Select "Start" button by pressing "Enter" key, HDMI1/

HDMI2/ HDMI3/ HDMI4/ RGB are writing and display OK or NG.

For Analog For HDMI EDID

D-sub to D-sub DVI-D to HDMI or HDMI to HDMI

4.1.4. EDID DATA

▪ HDMI

0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F

0x00 00 FF FF FF FF FF FF 00 1E 6D

ⓒ

0x01

0x02 0F 50 54 A1 08 00 71 40 81 C0 81 00 81 80 95 00

0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C

0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39

0x06 3F 1F 52 10 00 0A 20 20 20 20 20 20

0x07

0x00 02 03 37 F1 4E 90 1F 04 13 05 14 03 02 12 20 21

0x01 22 15 01 26 15 07 50 09 57 07

0x02

0x03

0x04 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16

0x05 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51

0x06 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2

01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

ⓓ

ⓕ

E3 05 03 01 02 3A 80 18 71 1C 38 2D 40

ⓕ

▪ RGB

0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F

0x00 00 FF FF FF FF FF FF 00 1E 6D

ⓒ

0x01

0x02 0F 50 54 A1 08 00 71 40 81 C0 81 00 81 80 95 00

0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C

0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A

0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20

0x07

01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26

ⓓ

ⓐⓓ ⓑ

ⓕ

ⓐ ⓑ

ⓓ

01 ⓔ1

ⓔ3

00

ⓐ Product ID ⓑ Serial No: Controlled on production line. ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ → ‘01’

Year : ‘2012’ → ‘16’

ⓓ Model Name(Hex): LGTV ⓔ Checksum(LG TV): Changeable by total EDID data. ⓕ Vendor Specific(HDMI)

# HDMI 1(C/S : 43 96)

EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 0 0 1E 6D 01 00 01 01 01 01

10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 9 9 26

20 0F 50 5 4 A1 08 00 31 40 45 40 61 4 0 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 0 0 A0 5A 00 0 0 0 0 1E 6 6 21 50 B 0 51 00 1B 30

50 40 70 36 0 0 A0 5 A 00 00 0 0 1E 00 00 0 0 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 26 15 07 50 09 57 07 7B 03 0C 00 10 00

20 B8 3C 20 C0 6E 01 02 03 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 96

# HDMI 2(C/S : 43 86)

EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 26 15 07 50 09 57 07 7B 03 0C 00 20 00

20 B8 3C 20 C0 6E 01 02 03 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 86

Only for training and service purposes

- 18 -

# HDMI 3(C/S : 43 76)

EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 26 15 07 50 09 57 07 7B 03 0C 00 30 00

20 B8 3C 20 C0 6E 01 02 03 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 76

# HDMI 4(C/S : 43 66)

EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

4.2. White Balance Adjustment

4.2.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation (2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to prevent saturation of Full Dynamic range and data, one of R/G/B is fixed at 192, and the other two is lowered to find the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Warm-up time: About 5 Min

3) Surrounding Humidity : 20 % ~ 80 %

4.2.2. Equipment

(1) Color Analyzer: CA-210 (LED Module : CH 14) (2) Adjustment Computer(During auto adj., RS-232C protocol

is needed) (3) Adjustment Remote control (4) Video Signal Generator MSPG-925F 720p/216-Gray

(Model: 217, Pattern: 78) → Only when internal pattern is not available

▪ Color Analyzer Matrix should be calibrated using CS-1000.

4.2.3. Equipment connection MAP

Co lor Anal yze r

Pro be

RS -232 C

Pattern Gen era to r

Sig nal Sou rce

* If TV internal pattern is used, not needed

RS- 232 C

Co mp ute r

RS- 232 C

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 26 15 07 50 09 57 07 7B 03 0C 00 40 00

20 B8 3C 20 C0 6E 01 02 03 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66

# RGB(C/S : 5C)

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 5C

4.2.4. Adj. Command (Protocol)

START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP

- LEN: Number of Data Byte to be sent

- CMD: Command

- VAL: FOS Data value

- CS: Checksum of sent data

- A: Acknowledge Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

▪ RS-232C Command used during auto-adjustment.

RS-232C COMMAND

[CMD ID DATA]

wb 00 00 Begin White Balance adjustment

wb 00 10 Gain adjustment(internal white pattern)

wb 00 1f Gain adjustment completed

wb 00 20 Offset adjustment(internal white pattern)

wb 00 2f Offset adjustment completed

wb 00 ff

End White Balance adjustment (internal pattern disappears )

Explantion

Only for training and service purposes

- 19 -

Ex) wb 00 00 -> Begin white balance auto-adj.

wb 00 10 -> Gain adj. ja 00 ff -> Adj. data jb 00 c0 ... ... wb 00 1f → Gain adj. completed *(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. wb 00 ff → End white balance auto-adj.

▪ Adj. Map

Cool

Medium

Warm

Adj. item

R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

R Cut

G Cut

B Cut

R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

R Cut

G Cut

B Cut

R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

R Cut

G Cut

Command

(lower caseASCII)

CMD1 CMD2 MIN MAX

Data Range

(Hex.)

4.2.5. Adj. method

(1) Auto adj. method

1) Set TV in adj. mode using POWER ON key.

2) Zero calibrate probe then place it on the center of the Display.

3) Connect Cable.(RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre mode. (Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

(2) Manual adjustment. method

1) Set TV in Adj. mode using POWER ON.

2) Zero Calibrate the probe of Color Analyzer, then place it on the center of LCD module within 10 cm of the surface.

3) Press ADJ key → EZ adjust using adj. R/C → 7. WhiteBalance then press the cursor to the right(key ►).

(When right key(►) is pressed 216 Gray internal pattern will be displayed)

4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value.

5) Adjustment is performed in COOL, MEDIUM, WARM 3

modes of color temperature.

▪ If internal pattern is not available, use RF input. In EZ

Adj. menu 7.White Balance, you can select one of 2 Test-pattern: ON, OFF. Default is inner(ON). By selecting OFF, you can adjust using RF signal in 216 Gray pattern.

Default

(Decimal)

▪ Adjustment condition and cautionary items

1) Lighting condition in surrounding area Surrounding lighting should be lower 10 lux. Try to isolate adj. area into dark surrounding.

2) Probe location : Color Analyzer(CA-210) probe should be within 10 cm

and perpendicular of the module surface (80° ~ 100°)

3) Aging time

- After Aging Start, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked

using no signal or Full-white pattern.

4.2.6. Reference (White balance Adj. coordinate and color temperature)

▪ Luminance : 2066 Gray ▪ Standard color coordinate and temperature using CS-1000 (over 26 inch)

Mode

Cool 0.269 0.273 13000 K 0.0000

Medium 0.285 0.293 9300 K 0.0000

Warm 0.313 0.329 6500 K 0.0000

Coordinate

x y

Temp ∆uv

▪ Standard color coordinate and temperature using CA-210(CH 18)

Mode

Cool 0.269 ± 0.002 0.273 ± 0.002 13000 K 0.0000

Medium 0.285 ± 0.002 0.293 ± 0.002 9300 K 0.0000

Warm 0.313 ± 0.002 0.329 ± 0.002 6500K 0.0000

Coordinate

x y

Temp ∆uv

4.2.7. ALELF & EDGE LED White balance table

- EDGE LED module change color coordinate because of aging time.

- Apply under the color coordinate table, for compensated aging time.

- (Normal line)72LM95 , 84LM96

Net

Aging time

Cast

3.0

Net

Cast

3.0

(Min)

1 0-2 280 287 296 307 320 337 2 3-5 279 285 295 305 319 335 3 6-9 277 284 293 304 317 334 4 10-19 276 283 292 303 316 333 5 20-35 274 280 290 300 314 330 6 36-49 272 277 288 297 312 327 7 50-79 271 275 287 295 311 325 8 80-119 270 274 286 294 310 324 9 Over 120 269 273 285 293 309 323

- (

Aging Chamber)72LM950 ,84LM96

Aging time

(Min)

1 0-2 276 282 292 302 316 332 2 3-5 274 280 290 300 314 330 3 6-9 273 278 289 298 313 328 4 10-19 272 276 288 296 312 326 5 20-35 271 274 287 294 311 324 6 36-49 270 272 286 292 310 322 7 50-79 266 269 282 289 306 319 8 80-119 264 267 280 287 304 317 9 Over 120 263 266 279 286 303 316

Cool Medium Warm

X y x y x y

269 273 285 293 313 329

Cool Medium Warm

X y x y x y

269 273 285 293 313 329

Only for training and service purposes

- 20 -

4.3. EYE-Q function check

(1) Turn on TV. (2) Press EYE key of Adjustment remote control.

(3) Cover the Eye Q II sensor on the front of the using your

hand and wait for 6 seconds.

(4) Confirm that R/G/B value is lower than 10 of the "Raw

Data (Sensor data, Back light)". If after 6 seconds, R/G/B value is not lower than 10, replace Eye Q II sensor.

G

(5) Remove your hand from the Eye Q II sensor and wait for 6

seconds.

4.4. Local Dimming Function Check

Step 1) Turn on TV. Step 2) At the Local Dimming mode, module Edge Backlight

moving right to left Back light of IOP module moving. Step 3) Confirm the Local Dimming mode. Step 4) Press "exit" key.

4.5. Magic Motion Remote control test

(1) Equipment : RF Remote control for test, IR-KEY-Code

Remote control for test

(2) You must confirm the battery power of RF-Remote control

before test(recommend that change the battery per every lot)

(3) Sequence (test)

1) if you select the "Start(Mute)" key on the Adjustment remote control, you can pairing with the TV SET.

2) You can check the cursor on the TV Screen, when select the "OK" key on the Adjustment remote control.

3) You must remove the pairing with the TV Set by select "OK" key + "Mute" key on the Adjustment remote control for 5 seconds.

(6) Confirm that "ok" pop up. If change is not seen, replace

Eye Q II sensor.

4.6. 3D function test

(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4]) * HDMI mode NO. 872 , pattern No.83 (1) Please input 3D test pattern like below.

(2) When 3D OSD appear automatically, then select green key.

(3) Don't wear a 3D Glasses, check the picture like below.

Only for training and service purposes

- 21 -

4.7. Wi-Fi Test

Step 1) Turn on TV Step 2) Select Network Connection option in Network Menu.

Step 3) Select Start Connection button in Network Connection.

Step 4) If the system finds any AP like blow PIC, it is working

well.

4.9. Inspection of light scattering

▪ Test Method

(1) Push “Power only” key. (2) Push “HDMI” hot key. (3) Inspect whether light scattering is occurred in internal

black pattern or not.

(4) Push “Power only” key.

4.10. Option selection per country

4.10.1. Overview

- Option selection is only done for models in Non-EU

4.10.2. Method

(1) Press ADJ key on the Adj. R/C, then select Country Group

Meun

(2) Depending on destination, select Country Group Code 04

or Country Group EU then on the lower Country option, select US, CA, MX. Selection is done using +, - or ►◄ key.

4.8. LNB voltage and 22KHz tone check

(only for DVB-S/S2 model) ▪ Test method

(1) Set TV in Adj. mode using POWER ON. (2) Connect cable between satellite ANT and test JIG. (3) Press Yellow key(ETC+SWAP) in Adj Remote control to

make LNB on. (4) Check LED light ‘ON’ at 18 V menu. (5) Check LED light ‘ON’ at 22 KHz tone menu. (6) Press Blue key(ETC+PIP INPUT) in Adj Remote control

to make LNB off. (7) Check LED light ‘OFF’ at 18 V menu. (8) Check LED light ‘OFF’ at 22 KHz tone menu.

▪ Test result

(1) After press LNB On key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be ON.

(2) After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be OFF.

Only for training and service purposes

4.11. MHL Test

(1) Turn on TV (2) Select HDMI4 mode using input Menu. (3) Set MHL Zig(M1S0D3617) using MHL input, output and

power cord. (4) Connect HDMI cable between MHL Zig and HDMI4 port. (5) Check LED light of Zig and Module of Set.

Result) If, The LED light is green and The Module shows

- 22 -

normal stream → OK, Else → NG

5. Tool Option selection

▪ Method : Press "ADJ" key on the Adjustment remote control,

then select Tool option.

6. Ship-out mode check(In-stop)

▪ After final inspection, press "IN-STOP" key of the Adjustment

remote control and check that the unit goes to Stand-by mode.

7. GND and Internal Pressure check

7.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power cord is fully inserted to the SET. (If loose, re-insert)

(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically.

(Remove CORD, A/V form AV JACK BOX.)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process.

7.2. Checkpoint

▪ TEST voltage

- GND: 1.5 KV / min at 100 mA

- SIGNAL: 3 KV / min at 100 mA ▪ TEST time: 1 second ▪ TEST POINT

- GND TEST = POWER CORD GND & SIGNAL CABLE

METAL GND

- Internal Pressure TEST = POWER CORD GND & LIVE &

NEUTRAL

▪ LEAKAGE CURRENT: At 0.5 mArms

9. USB S/W Download(Service only)

(1) Put the USB Stick to the USB socket. (2) Automatically detecting update file in USB Stick.

- If your downloaded program version in USB Stick is Low, it didn't work. But your downloaded version is High, USB data is automatically detecting.(Download Version High & Power only mode, Set is automatically Download)

(3) Show the message "Copying files from memory".

(4) Updating is starting. (5) Updating Completed, The TV will restart automatically.

(6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn’t have a DTV/ ATV test on production line.

* After downloading, have to adjust Tool Option again.

(1) Push "IN-START" key in service remote control. (2) Select "Tool Option 1" and push "OK" key. (3) Punch in the number. (Each model has their number)

8. Audio

No. Item Min Typ Max Unit Remark

Audio practical max Output, L/R

1. (Distortion=10%

max Output)

Speaker (8Ω

2. Impedance)

Measurement condition: (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms (3) RGB PC: 1 KHz sine wave signal 0.7 Vrms

Only for training and service purposes

9.0 10.0 12.0 W

8.5 8.9 9.8 Vrms

10.0 15.0 W

Measurement condition

Auto Volume :Off Audio EQ : Off Clear Voice : Off Virtual Surround:Off

- 23 -

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essenti al that these special safet y parts shoul d be replac ed with the same compo nents as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

LV1

200D

320

400

200T

540

541

830

531

820

532

700

710

530

570

510

121

810

120

122

420

560

910

410

AG3

AG2

AG1

900

Clip Type

Dual Play

(Option)

200

201D

300

Only for training and service purposes

- 24 -

310

580

500

A10

A9

A22

A2

Set + Stand

Stand Base

+ Body

System Configuration

LGE Internal Use Only

NVRAM

Clock for LG1152

MAIN Clock(24Mhz)

C100

8pF

50V

X-TAL_1

GND_1

1

2

X101

24MHz

4

3

C101

8pF

50V

GND_2

X-TAL_2

PLL SET[1:0] ==> Internal Pull-UP. N.C is high 00 : CPU clock(1056Mhz), Main0,1/2 DDR (792/792 Mhz) 01 : CPU clock(792Mhz), Main0,1/2 DDR (672/792 Mhz) 10 : CPU clock(1152Mhz), Main0,1/2 DDR (792/672 Mhz) 11 : CPU clock(984Mhz), Main0,1/2 DDR (792/792 Mhz)

BOOT MODE "11" or "01" : NOR "10" : eMMC "00" : NAND

OPT

R102 22

R103 22

OPT

PLLSET1

PLLSET0

R112

XIN_MAIN

1M

XO_MAIN

JTAG I/F FOR MAIN

+3.3V_NORMAL

4.7K

R187

R185

OPT

BOOT_MODE1

+3.3V_NORMAL

R188

OPT

R186

4.7K

BOOT_MODE1

BOOT_MODE0

TRST_N0

TDI0 TDO0 TMS0 TCK0

SOC_RESET

OPT

R131 10K

R132 10K

OPT

R133 10K

R134 10K

BOOT_MODE0

+3.3V_NORMAL

HW_OPT_0

HW_OPT_1

HW_OPT_2

HW_OPT_3

HW_OPT_4

HW_OPT_5

HW_OPT_6

HW_OPT_7

HW_OPT_8

HW_OPT_9

HW_OPT_10

HP_AMP_MUTE

BackEnd 1

BackEnd 2

Pannel Resol

OPTIC I/F

3D Depth IC

DDR Size

CP BOX

FrontEnd 1

FrontEnd 2

OPT

22

R117

10K

URSA5

R110

FRC_EXTERNAL

R100 10K

10K

FRC3

FRC_INTERNAL

R107 10K

R111

FHD

R124 10K

UD

R125 10K

OPTIC

R138 10K

NON_OPTIC

R139 10K

OPT

3D_DEPTH

R140 10K

R145 10K

1GByte

R141 10K

R146 10K

NON_3D DEPTH

CP_BOX

R152 10K

R147 10K

DVB_T2_TUNER

NON_CP_BOX

R153 10K

R148 10K

NON_DVB_T2_TUNER

DVB_S_TUNER

R156 10K

R154 10K

DVB_C2_TUNER

R158 10K

R155 10K

NON_DVB_S_TUNER

NON_DVB_C2_TUNER

UD_FRC

R121 10K

NON_UD_FRC

R126 10K

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

MODEL_OPT_7

MODEL_OPT_8

MODEL_OPT_9

MODEL_OPT_10

MODEL OPTION 8 is just for CP Box It should not be appiled at MP

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

IC102

R1EX24256BSAS0A

A0

1

A1

A2

VSS

8

2

7

A0’h

3

6

4

5

Place to LVDS Wafer

FRC_RESET

I2C_SCL1

SoC internal

NO_FRC

FRC

0

0 1

1

HIGH

FHD

OPTIC

3D DEPTH

3D_Depth_IC

DDR Reserved

CP BOX

Enable

T2 Tuner

Support

S Tuner

Support

C2 Tuner

Support

UD FRC

(For UD)

C111

0.1uF

VCC

WP

SCL

SDA

R151 22

4.7K

R113

R160 22

R162 22

MHL_DET

HDMI_INT

LG FRC3

10

0

LOW

UD

NON_OPTIC

NON_3D_Depth_IC

DDR_Default

Disable

Not Support

+3.3V_NORMAL

Write Protection

- Low : Normal Operation

- High : Write Protection

R143

OPT

22

10K

FRC3

R170

SOC_RX

SOC_TX

2N7002K

URSA5

1

R142

OPT

22

FRC3_RESET

3D_DEPTH_RESET

I2C_BE_SDA1I2C_SDA1

I2C_BE_SCL1

LOCAL_DIM_EN

+5V_NORMAL

D

Q100

2N7002K

+5V_NORMAL

G

S

D

Q105

OPT

+3.3V_NORMAL

R178

2.2K

I2C_SCL5

I2C_SDA5

I2C_SCL3 I2C_SDA3

+3.3V_NORMAL

G

S

+3.3V_NORMAL

R203

100K

R180

R179

2.2K

OPT

3.3K

100K

2N7002K

R181

3.3K

D

R202

Q103

R182

G

S

IRB_SPI_MISO IRB_SPI_MOSI

IRB_SPI_CK IRB_SPI_SS

DTV_ATV_SELECT

I2C PULL UP

R196

3.3K

2.2K

R195

2.2K

XIN_MAIN

XO_MAIN

SOC_RESET

TRST_N0

TMS0 TCK0 TDI0 TDO0

PLLSET1

PLLSET0 BOOT_MODE1 BOOT_MODE0

ERROR_OUT

EPHY_INT /USB_OCD2 /USB_OCD3

UART1_RX

UART1_TX M_REMOTE_RX M_REMOTE_TX

AV1_CVBS_DET

R197

3.3K

R198

3.3K

I2C_SCL1 I2C_SDA1 I2C_SCL2 I2C_SDA2 I2C_SCL3 I2C_SDA3 I2C_SCL4 I2C_SDA4 I2C_SCL5 I2C_SDA5 I2C_SCL6 I2C_SDA6

R199

3.3K

R150 22

R101

R184

R183

1.2K

R104 560

1%

BOOT_MODE1 BOOT_MODE0

1.2K

22

I2C_SDA1 I2C_SCL1 I2C_SDA2 I2C_SCL2 I2C_SDA3 I2C_SCL3 I2C_SDA4 I2C_SCL4

I2C_SDA5 I2C_SCL5

I2C_SDA6 I2C_SCL6

A22

XIN_MAIN

B22

XO_MAIN

AB16

OPM1

AB17

OPM0

AE3

PORES_N

V23

TRST_N0

U25

TMS0

V25

TCK0

V24

TDI0

U24

TDO0

Y22

TRST_N1

AA22

TMS1

AB20

TCK1

AB21

TDI1

W22

TDO1

AB9

PLLSET1

AB8

PLLSET0

AB15

BOOT_MODE1

AB14

BOOT_MODE0

Y23

EXT_INTR3/GPIO48

W25

EXT_INTR2/GPIO63

W24

EXT_INTR1/GPIO62

W23

EXT_INTR0/GPIO61

Y5

UART0_RX/GPIO49

W6

UART0_TX/GPIO50

AA6

UART1_RX

Y6

UART1_TX

AB5

UART2_RX

AA5

UART2_TX

AB23

SPI_DI0/GPIO39

AB24

SPI_DO0/GPIO38

AA25

SPI_SCLK0/GPIO37

AB25

SPI_CS0/GPIO36

Y25

SPI_DI1/GPIO35

AA23

SPI_DO1/GPIO34

Y24

SPI_SCLK1/GPIO33

AA24

SPI_CS1/GPIO32

AB6

SCL0/GPIO60

AB4

SDA0/GPIO59

AC5

SCL1/GPIO58

AC4

SDA1/GPIO57

AD4

SCL2/GPIO56

AE4

SDA2/GPIO71

AE5

SCL3/GPIO70

AD5

SDA3/GPIO69

AE6

SCL4/GPIO68

AD6

SDA4/GPIO67

AC6

SCL5/GPIO66

AC7

SDA5/GPIO65

FPGA_LVDS_INFO

USB_CTL3

DiiVA_POD_CTL

M25

M24

M23

N23

T27

EB_CS3/GPIO64

EB_CS2/GPIO79

EB_CS1/GPIO78

EB_CS0/GPIO77

RMII_REF_CLK

RMII_CRS_DV

RMII_MDIO

RMII_MDC

AD2

AB1

AB2

AB3

AC2

R105 22

EPHY_MDC

EPHY_MDIO

EPHY_REFCLK

EPHY_CRS_DV

for DiiVA(China)

SEL_USB3

SEL_USB2

SEL_USB1

EB_ADDR[0-14]

EB_OE_N

EB_BE_N1

EB_BE_N0

EB_WE_N

T28

U27

EB_OE_N

EB_WE_N

U26

U28

EB_WAIT

EB_BE_N1

J22

K22

J23

EB_BE_N0

EB_ADDR17/GPIO84

EB_ADDR16/GPIO83

EB_ADDR15/GPIO82

EB_ADDR[11]

EB_ADDR[12]

EB_ADDR[13]

EB_ADDR[14]

L26

L27

L25

N26

EB_ADDR14

EB_ADDR13

EB_ADDR12

EB_ADDR[9]

EB_ADDR[8]

EB_ADDR[10]

N27

M26

L28

EB_ADDR9

EB_ADDR11

EB_ADDR10

IC100

LG1152D-B1

LG1152_NON_RM

RMII_TXEN

RMII_TXD1

RMII_TXD0

RMII_RXD1

RMII_RXD0

CAM_CE1_N

CAM_CE2_N

CAM_CD1_N

CAM_CD2_N

CAM_VS1_N

CAM_VS2_N

CAM_IREQ_N

CAM_RESET

CAM_INPACK_N

AC3

AE1

AD3

AD1

W26

V28

Y27

Y26

W28

W27

AA28

AB26

AA27

AA26

R108 22

R106 22

EPHY_EN

EPHY_TXD1

EPHY_RXD0

EPHY_TXD0

EPHY_RXD1

+3.3V_NORMAL

/PCM_CE2

/PCM_CE1

CAM_CD2_N

CAM_CD1_N

CI

10K

R166

CAM_IREQ_N

CI

R167 10K

PCM_RST

CAM_INPACK_N

EPHY_INT

EB_ADDR[5]

EB_ADDR[7]

EB_ADDR[6]

L24

L23

K28

EB_ADDR8

EB_ADDR7

EB_ADDR6

EB_ADDR5

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

CAM_IOIS16_N

Y28

V27

V26

CAM_REG_N

CAM_WAIT_N

CI

10K

R168

PCM_5V_CTL

HP_DET

EB_ADDR[3]

EB_ADDR[2]

EB_ADDR[4]

K27

K26

K25

K24

EB_ADDR4

EB_ADDR3

EB_ADDR2

SC_CLK/GPIO90

SC_DETECT/GPIO93

R25

U23

T25

SMARTCARD_DET

SMARTCARD_CLK

SEL_USB1 SEL_USB2 SEL_USB3 /RST_PHY

SC_DET DiiVA_POD_CTL

+3.3V_NORMAL

EB_ADDR[1]

EB_ADDR[0]

10K

R109

K23

V22

U22

EB_ADDR1

EB_ADDR0

EB_DATA15

EB_DATA14

SC_VCCEN/GPIO89

SC_VCC_SEL/GPIO88

SC_RST/GPIO91

SC_DATA/GPIO92

T24

T23

R24

SMARTCARD_RST

SMARTCARD_VCC

SMARTCARD_DATA

SMARTCARD_PWR_SEL

T22

R22

P22

N22

M22

EB_DATA9

EB_DATA13

EB_DATA12

EB_DATA11

EB_DATA10

SD_CLK/GPIO76

SD_CMD/GPIO73

SD_CD_N/GPIO75

SD_WP_N/GPIO74

SD_DATA3/GPIO72

C22

C23

A23

B23

A24

MOTOR_CCW

MOTOR_CLOSE_SW

MO_SENS_TO_MAIN_UP

MO_SENS_TO_MAIN_DOWN

EB_DATA[0-7]

EB_DATA[0]

EB_DATA[1]

EB_DATA[3]

EB_DATA[2]

EB_DATA[4]

EB_DATA[5]

EB_DATA[6]

EB_DATA[7]

L22

T26

R28

R27

R26

P28

P27

P26

N28

EB_DATA8

EB_DATA7

EB_DATA6

EB_DATA5

EB_DATA4

EB_DATA3

EB_DATA2

EB_DATA1

EB_DATA0

EMMC_RST EMMC_CLK

EMMC_CMD EMMC_DATA7 EMMC_DATA6 EMMC_DATA5 EMMC_DATA4 EMMC_DATA3 EMMC_DATA2 EMMC_DATA1 EMMC_DATA0

NAND_CS1

NAND_CS0

NAND_ALE

NAND_CLE

NAND_REN

NAND_WEN

SD_DATA2/GPIO87

SD_DATA1/GPIO86

SD_DATA0/GPIO85

USB_DP1

USB_DM1

USB_DP2

USB_DM2

USB_TXR_RKL

USB_ANALOGTEST

BT_USB_DP

BT_USB_DM

BT_TXR_RKL

BT_ANALOGTEST

R173

Y4

C25

B25

AA1

AA2

AA4

22

OPT

R175

R176

R174

B24

C24

A25

MOTOR_CW

IR_B_RESET

MOTOR_OPEN_SW

B27

A27

A26

B26

USB_DM3

USB_DP3

USB_HUB_IC_IN_DM

USB_HUB_IC_IN_DP

Place near Jack side

E28 F27 F26 C26

EMMC_DATA[7]

E27

EMMC_DATA[6]

E26

EMMC_DATA[5]

D27

EMMC_DATA[4]

D28

EMMC_DATA[3]

C27

EMMC_DATA[2]

C28

EMMC_DATA[1]

D26

EMMC_DATA[0]

R23 P24 N25 P23 N24 P25

AC1

GPIO31

V7

GPIO30

W5

GPIO29

W4

GPIO28

V6

GPIO27

V5

GPIO26

V4

GPIO25

U6

GPIO24

U5

GPIO23

U4

GPIO22

T6

GPIO21

T5

GPIO20

T4

GPIO19

R6

GPIO18

R5

GPIO17

R4

GPIO16

P6

GPIO15

P5

GPIO14

P4

GPIO13

N6

GPIO12

N5

GPIO11

N4

GPIO10

N3

GPIO9

M6

GPIO8

AC23

GPIO7

AC24

GPIO6

AE24

GPIO5

AD23

GPIO4

AE23

GPIO3

AC22

GPIO2

AD22

GPIO1

AE22

GPIO0

OPT

WIFI_DP

LG1152 B1

MAIN & GPIO

RCLAMP0502BA

WIFI_DM

M25

M24

M23

N23

T27

T28

U27

U26

U28

J22

K22

J23

EB_OE_N

EB_WE_N

EB_WAIT

EB_BE_N1

EB_BE_N0

A22

XIN_MAIN

B22

EB_CS3/GPIO64

EB_CS2/GPIO79

EB_CS1/GPIO78

EB_CS0/GPIO77

XO_MAIN

AB16

OPM1

EB_ADDR17/GPIO84

EB_ADDR16/GPIO83

AB17

OPM0

AE3

PORES_N

V23

TRST_N0

U25

TMS0

V25

TCK0

V24

TDI0

U24

TDO0

Y22

TRST_N1

AA22

TMS1

AB20

TCK1

AB21

TDI1

W22

TDO1

AB9

PLLSET1

AB8

PLLSET0

AB15

BOOT_MODE1

AB14

BOOT_MODE0

Y23

EXT_INTR3/GPIO48

W25

EXT_INTR2/GPIO63

W24

EXT_INTR1/GPIO62

W23

EXT_INTR0/GPIO61

Y5

UART0_RX/GPIO49

W6

UART0_TX/GPIO50

AA6

UART1_RX

Y6

UART1_TX

AB5

UART2_RX

AA5

UART2_TX

AB23

SPI_DI0/GPIO39

AB24

SPI_DO0/GPIO38

AA25

SPI_SCLK0/GPIO37

AB25

SPI_CS0/GPIO36

Y25

SPI_DI1/GPIO35

AA23

SPI_DO1/GPIO34

Y24

SPI_SCLK1/GPIO33

AA24

SPI_CS1/GPIO32

AB6

SCL0/GPIO60

AB4

SDA0/GPIO59

AC5

SCL1/GPIO58

AC4

SDA1/GPIO57

AD4

SCL2/GPIO56

AE4

SDA2/GPIO71

AE5

SCL3/GPIO70

AD5

SDA3/GPIO69

AE6

SCL4/GPIO68

AD6

SDA4/GPIO67

AC6

SCL5/GPIO66

AC7

SDA5/GPIO65

RMII_REF_CLK

RMII_CRS_DV

RMII_MDIO

RMII_MDC

RMII_TXEN

RMII_TXD1

RMII_TXD0

RMII_RXD1

RMII_RXD0

CAM_CE1_N

CAM_CE2_N

AD2

AB1

AB2

AB3

AC2

AC3

AE1

AD3

AD1

W26

V28

Y27

LG1152_RM IC100-*1

OPTIC_FPGA_RESET

OPTIC_SERDES_RESET

3D_DEPTH_RESET /RST_PHY

OLED_TCON_RESET

HW_OPT_9

HW_OPT_7 HW_OPT_8

DSUB_DET

SC_DET COMP1_DET HW_OPT_5 HW_OPT_6

M_RFModule_ISP

HW_OPT_10

M_RFModule_RESET

FRC_RESET HW_OPT_2 HW_OPT_1 HW_OPT_0

HW_OPT_4

FLASH_WP /RST_HUB

HW_OPT_3

HP_DET

RF_SWITCH_CTL

/TU_RESET

/S2_RESET

OPT

D100

I2C_SDA2 I2C_SCL2

SMARTCARD_DATA SMARTCARD_RST SMARTCARD_PWR_SEL SMARTCARD_VCC SMARTCARD_DET

L26

L27

L25

N26

N27

M26

L28

L24

L23

K28

K27

K26

K25

K24

K23

V22

U22

T22

R22

P22

N22

M22

L22

T26

R28

R27

R26

P28

P27

P26

N28

EB_ADDR9

EB_ADDR8

EB_ADDR7

EB_ADDR6

EB_ADDR5

EB_ADDR4

EB_ADDR3

EB_ADDR2

EB_ADDR1

EB_ADDR0

EB_DATA9

EB_DATA8

EB_DATA7

EB_DATA6

EB_DATA5

EB_DATA4

EB_DATA3

EB_DATA2

EB_DATA1

EB_ADDR14

EB_ADDR13

EB_ADDR12

EB_ADDR11

EB_ADDR15/GPIO82

CAM_CD1_N

CAM_CD2_N

CAM_VS1_N

CAM_VS2_N

CAM_IREQ_N

Y26

W28

W27

AA28

AB26

EB_DATA0

EB_ADDR10

EB_DATA15

EB_DATA14

EB_DATA13

EB_DATA12

EB_DATA11

EB_DATA10

E28

EMMC_RST

F27

EMMC_CLK

F26

EMMC_CMD

C26

EMMC_DATA7

E27

EMMC_DATA6

E26

EMMC_DATA5

D27

EMMC_DATA4

D28

EMMC_DATA3

C27

EMMC_DATA2

C28

EMMC_DATA1

D26

EMMC_DATA0

R23

NAND_CS1

P24

NAND_CS0

N25

NAND_ALE

P23

NAND_CLE

N24

NAND_REN

P25

NAND_WEN

AC1

GPIO31

V7

GPIO30

W5

GPIO29

W4

GPIO28

V6

GPIO27

V5

GPIO26

V4

GPIO25

U6

GPIO24

U5

GPIO23

U4

GPIO22

T6

GPIO21

T5

GPIO20

T4

GPIO19

R6

GPIO18

R5

GPIO17

R4

GPIO16

P6

GPIO15

P5

GPIO14

P4

GPIO13

N6

GPIO12

N5

GPIO11

N4

GPIO10

N3

GPIO9

M6

GPIO8

AC23

GPIO7

AC24

GPIO6

AE24

GPIO5

AD23

GPIO4

AE23

GPIO3

AC22

GPIO2

AD22

GPIO1

AE22

CAM_RESET

CAM_INPACK_N

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

CAM_IOIS16_N

Y28

V27

V26

AA27

AA26

GPIO0

SC_CLK/GPIO90

SC_DETECT/GPIO93

SC_VCCEN/GPIO89

SC_VCC_SEL/GPIO88

SC_RST/GPIO91

SC_DATA/GPIO92

SD_CLK/GPIO76

SD_CMD/GPIO73

SD_CD_N/GPIO75

SD_WP_N/GPIO74

SD_DATA3/GPIO72

SD_DATA2/GPIO87

SD_DATA1/GPIO86

SD_DATA0/GPIO85

USB_DP1

USB_DM1

USB_DP2

USB_DM2

USB_TXR_RKL

USB_ANALOGTEST

BT_USB_DP

BT_USB_DM

BT_TXR_RKL

BT_ANALOGTEST

Y4 R25

U23

T25

T24

T23

R24

C22

C23

A23

B23

A24

B24

C24

A25

B27

A27

A26

B26

C25

B25

AA1

AA2

AA4

SMARTCARD_CLK MOTOR_CLOSE_SW

MOTOR_OPEN_SW MOTOR_CW MOTOR_CCW

MO_SENS_TO_MAIN_UP

MO_SENS_TO_MAIN_DOWN

OPTIC_FPGA_RESET OPTIC_SERDES_RESET

OLED_TCON_RESET

FPGA_LVDS_INFO

IRB_SPI_MISO IRB_SPI_MOSI

IRB_SPI_CK IRB_SPI_SS

IR_B_RESET

EMMC_RST EMMC_CLK EMMC_CMD EMMC_DATA[0-7]

+3.3V_NORMAL

SW1

JTP-1127WEM

12

2.7K

R201

DEBUG

For ISP

Delete PV

4 3

1/16W

5%

+5V_NORMAL

G

D

HDMI_S/W_RESET

S

Q104 2N7002K

Debug

+3.3V_NORMAL

UART1_RX

UART1_TX

1

P100

12507WS-04L

1

DEBUG

2

3

4

5

+1.0V_VDD

LGE Internal Use Only

Max 360mA

AVDD10_DEMOD

L304

BLM18PG121SN1D

10uFC312

C318 0.1uF

C321 0.1uF

+1.0V_VDD

L302 BLM18PG121SN1D

LG1152A

IC101

VDD33

VDD33_CVBS

VDD33_HDMI

VDD33_XTAL

VDD25_VSB

VDD25_CVBS

VDD25_REF

VDD25_COMP

VDD25_AUD

VDD25_LVTX

VDD18_A

AVDD10_DEMOD

AVDD10_VSB

AVDD10_LVTX

VDDC_XTAL

+2.5V_NORMAL

For HDCP OTP Will be change to LOW for MP

For HeatSinK, AL Block / SMD Top

HEATSINK/ALBLOCK

MDS62110218

HEATSINK/ALBLOCK

MDS62110218

HEATSINK/ALBLOCK

MDS62110218

HEATSINK/ALBLOCK

M300

M303

M306

M307

MDS62110218

AVSS25_REF

HEATSINK/ALBLOCK

M301

MDS62110218

M302

MDS62110218

M321

MDS62110218

P1

P2 P14 R14 F18 H16 M16

L15 R13 R12 V13 P10 R10

P9

R9

V7 J16

P6

P7

V6 B18 G12 G13

N1

N2

G6

G7 R15 K15 D17 D18

N7 L16

G4

N10 K16 D16

G5

G8

G9 G10 G11 G14 G15

H4

H5

H6

H7

H8

H9 H10 H11 H12 H13 H14 H15

J4

J5

J6

J7

ALBLOCK

VDD33_1 VDD33_2 AVDD33_CVBS_1 AVDD33_CVBS_2 AVDD33_HDMI_1 AVDD33_HDMI_2 VDD33_XTAL

VDD25_VSB VDD25_CVBS_2 VDD25_CVBS_1 VDD25_CVBS_3 AVDD25_REF VDD25_COMP_3 VDD25_COMP_1 VDD25_COMP_2 VDD25_COMP_4 VDD25_AAD VDD25_AUD_1 VDD25_AUD_2 VDD25_AUD_3 VDD25_LVTX_1 VDD25_LVTX_2 VDD25_LVTX_3

VDD18_1 VDD18_2

VDDC10_1 VDDC10_2 AVDD10_CVBS AVDD10_VSB AVDD10_LVTX_1 AVDD10_LVTX_2 AVDD10_LLPLL VDDC_XTAL

VQPS

AVSS25_REF GND_XTAL GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24

M304

MDS62110218

M305

MDS62110218

M324

MDS62110218

HEATSINK/ALBLOCK

M323

MDS62110218

HEATSINK

GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90

J8 J9 J10 J11 J12 J13 J14 J15 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M17 N4 N5 N6 N8 N9 N11 N12 N13 N14 N15 N16 P3 P4 P5 P13 P15 P16 R3 R16 R17 R18 T13 U13

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

LG1152AN-B2

+1.8V_NORMAL

L326

BLM18PG121SN1D

10uFC421

+2.5V_NORMAL

L324 BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

+2.5V_NORMAL

L322

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

+3.3V_NORMAL

L319

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

M315

MDS62110215

M312

MDS62110215

M313

MDS62110215

M314

MDS62110215

M318

MDS62110215

ESD_AJ M317

MDS62110215

ESD

OPT

ESD

UD Option

M315-*1

MDS62110214

UD_ESD_9.5T

M312-*1

MDS62110214

UD_ESD_9.5T

M313-*1

MDS62110214

OPT_UD_ESD_9.5T

M314-*1

MDS62110214

UD_ESD_9.5T

M318-*1

MDS62110214

UD_ESD_AJ_9.5T

M317-*1

MDS62110214

UD_ESD_9.5T

10uFC422

Max 100mA

10uFC414

Max 50mA

10uFC401

Max 35mA

VDD33_CVBS

10uFC398

C403 0.1uF

VDD18_A

VDD25_CVBS

C417 0.1uF

VDD25_AUD

C423 0.1uF

C419 0.1uF

C409 0.1uF

C408 0.1uF

SMD Bottom

For Tuner Sensitivity / Under DDR

MDS62110215

UD Option

M308-*1

MDS62110214

M309-*1

MDS62110214

M322-*1

MDS62110214

10uFC305

M308

M309

M322

Max 1mA

VDDC_XTAL

+2.5V_NORMAL

+1.0V_VDD

L308

BLM18PG121SN1D

10uFC359

C313 0.1uF

+2.5V_NORMAL

L313 BLM18PG121SN1D

Max 250mA

10uFC375

C385 0.1uF

On Package Decap : 0.1uF *1ea

L315 BLM18PG121SN1D

10uFC379

C386 0.1uF

On Package Decap : 0.1uF *1ea

Max 256mA

+3.3V_NORMAL

VDD33_HDMI

L323

BLM18PG121SN1D

10uFC413

C405 0.1uF

On Package Decap : 0.1uF *1ea

GASKET_8.0X6.0X7.5H

GASKET except ATSC

GASKET_8.0X6.0X7.5H

LM8600

GASKET_8.0X6.0X7.5H

NON_UD

GASKET_8.0X6.0X9.5H

UD_GASKET except ATSC

GASKET_8.0X6.0X9.5H

UD_9.5T

GASKET_8.0X6.0X9.5H

UD_9.5T

Max 12mA

AVDD10_VSB

10uFC366

10uFC369

C370 0.1uF

C368 0.1uF

VDD25_LVTX

C390 0.1uF

C393 0.1uF

Max 10mA

VDD25_REF

L321 BLM15BD121SN1

L320

BLM15BD121SN1

AVSS25_REF

+3.3V_NORMAL

L309

BLM18PG121SN1D

OPT

ATSC

OPT_UD_9.5T

UD_ATSC_9.5T

C400 0.1uF

For ATSC

Max 250mA

VDD25_COMP

C407 0.1uF

OPT

C416 0.1uF

For Tuner Sensitivity / Under TUNER

M310

MDS62110215

M311

MDS62110215

UD Option

M310-*1

MDS62110214

M311-*1

MDS62110214

+1.0V_VDD

Max 35mA

AVDD10_LVTX

L305

BLM18PG121SN1D

10uFC332

C333 0.1uF

On Package Decap : 0.1uF *1ea

Max 28mA

L325

BLM18PG121SN1D

10uFC415

VDD25_VSB

+2.5V_NORMAL

On Package Decap : 0.1uF *1ea

Max 1mA

VDD33_XTAL

10uFC371

C381 0.1uF

SMD TOP FOR ESD

M316

MDS62110217

M320

MDS62110217

M319

MDS62110217

C338 0.1uF

C418 0.1uF

ESD

+1.5V_Bypass Cap

+1.5V_DDR

L300

BLM18PG121SN1D

5V

ZD301

ESD_LG1152

VCC1.5V_MAIN

Max 40mA

VREF_M0

R300

1K 1%

0.1uF

R301

1K 1%

On Package Decap : 0.1uF *1ea

+1.5V_DDR

BLM18PG121SN1D

On Package Decap : 0.1uF *2ea

+0.9V_VDD

10uFC301

5V

ZD300

ESD_LG1152

On Package Decap : 0.1uF *6ea

+0.9V_VDD

On Package Decap : 0.1uF *1ea

+1.8V_NORMAL

L312

BLM18PG121SN1D

On Package Decap:0.1uF *1ea

+1.8V_NORMAL

On Package Decap:0.1uF *1ea

+3.3V_NORMAL

L310

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

C308

C300

L301

10uFC303

10uFC307

Max 20mA

10uFC347

Max 120mA

VDD18_LVTX

10uFC374

Max 93mA

VDD18_LVRX

L318

BLM18PG121SN1D

10uFC397

10uFC372

1000pF

C306 0.1uF

C314 0.1uF

C353 0.1uF

C382 0.1uF

C404 0.1uF

C377 0.1uF

10uFC326

C316 0.1uF

C310 0.1uF

Max 5900mA

C322 0.1uF

C319 0.1uF

C388 0.1uF

C383 0.1uF

(18)

10uFC302

C317 0.1uF

C311 0.1uF

C323 0.1uF

C320 0.1uF

On Package Decap : 0.1uF *3ea

Max 340mA

VCC1.5V_DE

C336 0.1uF

C340 0.1uF

C327 0.1uF

C325 0.1uF

VDD33

C392 0.1uF

C394 0.1uF

C399 0.1uF

C391 0.1uF

Max 680mA

VCC1.5V_MAIN

C329 0.1uF

C334 0.1uF

C337 0.1uF

VCC1.5V_MAIN

C342 0.1uF

R302

R303

C343 0.1uF

1K 1%

C346 0.1uF

Max 40mA

VREF_M1

0.1uF

C350

C362

On Package Decap : 0.1uF *1ea

Max 40mA

VCC1.5V_DE

R304

R305

VREF_M2

1K 1%

0.1uF

1K 1%

C363

C351

On Package Decap : 0.1uF *1ea

10uFC309

10uFC341

Max 6mA

C315 0.1uF

Max 1320mA

C345 0.1uF

MAIN_XTAL

C324 0.1uF

AVDD10_OSPREY

C348 0.33uF

+0.9V_VDD

+1.0V_VDD

L303 BLM18PG121SN1D

L306

BLM18PG121SN1D

On Package Decap : 0.1uF *3ea

+1.8V_NORMAL

L316

BLM18PG121SN1D

10uFC395

On Package Decap:0.1uF *1ea

+1.8V_NORMAL

+3.3V_NORMAL

BLM18PG121SN1D

L314

BLM18PG121SN1D

L317

10uFC396

VDD18_MAIN_XTAL

10uFC378

Max 48.8mA

VDD33_USB

C402 0.1uF

1000pF

C349 0.33uF

Max 49mA

VDD18

C410 0.1uF

Max 31mA

C384 0.1uF

C389 0.1uF

C406 0.1uF

C411 0.1uF

C304 0.1uF

For secure BOOT OTP

Will be change to LOW for MP

LG1152

MAIN POWER

VDD33_USB

VDD18_LVTX

VDD18_LVRX

VDD18_MAIN_XTAL

VCC1.5V_DE

VCC1.5V_MAIN

VREF_M1

VREF_M0

AVDD10_OSPREY

+0.9V_VDD

MAIN_XTAL

VDD18

LG1152D

VDD33

U8 U9

U10

V8

V9 V10 J21 K21

AA10 AA11

VDD18

W18 W19 Y18 Y19

AG28 AH27

AA7 AA8 AA9 AG1

AA12 AA13 AB12

J28 B28 G22

F9

G8

G9 G10 G11

H8

H9 H10 H11 F22 G13 G14 G16 G17 G18 G19 G20 G21 H13 H14 H16 H17 H18 H19 H20 H21

VREF_M2

L4 F13 G12 F14 G15

L20 M20 M21 M27 M28 N20 N21 P20 P21 R20 R21

K8

K9 K10 K11

L8

L9 L10 L11

M8

M9 M10 M11

N8

N9 N10 N11

P8

P9 P10 P11

R8

R9 R10 R11

Y7

Y8 AF1 F28

H22

AA19

G23

G7

H7 H12 H15

J7

J8

J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20

K7 K12

IC100

LG1152D-B1

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 AVDD33_USB_1 AVDD33_USB_2 AVDD33_BT_USB_1 AVDD33_BT_USB_2

VDD18_1 VDD18_2 VDD18_3 VDD18_4 VDD18_5 VDD18_6 VDD18_LTX_1 VDD18_LTX_2 VDD18_LTX_3 VDD18_LTX_4 VDD18_LVRX_1 VDD18_LVRX_2 VDD18_LVRX_3 VDD18_DISPPLL VDD18_DR3PLL VDD18_MAIN_XTAL

VDD15_M2_1 VDD15_M2_2 VDD15_M2_3 VDD15_M2_4 VDD15_M2_5 VDD15_M2_6 VDD15_M2_7 VDD15_M2_8 VDD15_M2_9 VDD15_M0_1 VDD15_M0_2 VDD15_M0_3 VDD15_M0_4 VDD15_M0_5 VDD15_M0_6 VDD15_M0_7 VDD15_M0_8 VDD15_M0_9 VDD15_M0_10 VDD15_M0_11 VDD15_M0_12 VDD15_M0_13 VDD15_M0_14 VDD15_M0_15 VDD15_M0_16 VDD15_M0_17

VREF_M2_0 VREF_M1_0 VREF_M1_1 VREF_M0_0 VREF_M0_1

VDDC10_OSPREY_1 VDDC10_OSPREY_2 VDDC10_OSPREY_3 VDDC10_OSPREY_4 VDDC10_OSPREY_5 VDDC10_OSPREY_6 VDDC10_OSPREY_7 VDDC10_OSPREY_8 VDDC10_OSPREY_9 VDDC10_OSPREY_10 VDDC10_OSPREY_11

VDDC09_1 VDDC09_2 VDDC09_3 VDDC09_4 VDDC09_5 VDDC09_6 VDDC09_7 VDDC09_8 VDDC09_9 VDDC09_10 VDDC09_11 VDDC09_12 VDDC09_13 VDDC09_14 VDDC09_15 VDDC09_16 VDDC09_17 VDDC09_18 VDDC09_19 VDDC09_20 VDDC09_21 VDDC09_22 VDDC09_23 VDDC09_24 VDD09_LTX_1 VDD09_LTX_2 VDD09_LTX_3 AVDD09_DR3PLL

VDDC_MAIN_XTAL

SP_VQPS

GND_MAIN_XTAL

GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20

3

GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98

GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148

K13 K14 K15 K16 K17 K18 K19 K20 L7 L12 L13 L14 L15 L16 L17 L18 L19 L21 M7 M12 M13 M14 M15 M16 M17 M18 M19 N7 N12 N13 N14 N15 N16 N17 N18 N19 P7 P12 P13 P14 P15 P16 P17 P18 P19 R7 R12 R13 R14 R15 R16 R17 R18 R19 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 U7 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W20 W21 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y20 Y21 AA14 AA15 AA16 AA17 AA18 AA20 AA21 AB7 AB10 AB11 AB13 AB22

Place these close to tuner

LGE Internal Use Only

TU_CVBS

680pF C506

OPT

L503

SC_CVBS_IN

AV1_CVBS_IN

DSUB_B+

DSUB_G+

DSUB_R+

SC_B SC_G

SC_R

COMP1_Pb

COMP1_Y

COMP1_Pr

OPT

R3634

SCART_Lout

SCART_Rout

PC_L_IN

PC_R_IN

SC_L_IN

SC_R_IN

AV1_L_IN

AV1_R_IN

CHB_CVBS

2K

SC_FB

SC_ID

5.5V

C3625

R607 470K

EU

470K

D503

5pF 50V

R601 470K

R602

R603 470K

R617

L501

L500

L502

OPT

D504

5.5V

75 OPT

NON SCART

R525-*1

0

D506

D505

5.5V

OPT

R3633

+12V

100K

Q505

2K

R552

R554

OPT C573

560pF 50V

OPT

R618 220 CHB

CHB

D500

5.5V OPT

C528

EU

C574 560pF 50V

+5V_TU

B

EU

R525

75

D501

5.5V OPT

OPT

10pF

C580

100K

2.2uF

100K

L506

C581 560pF 50V

OPT

C572 330pF 50V

OPT

L508

C546

10pF

R538

10V

R549

5.5V

OPT

10pF

EU

C525

EU

E

C

R522

D502

OPT

C579

C3626

L509

EU

1uH

C508

EU 150pF 50V

EU

L504

1uH

50V 150pF C511

R616

220

CHB

R521 100

10K

EU

C524

10pF

5pF 50V OPT

2.2uF

L507

10pF

10V

NON SCART

C605

OPT

10pF

C578

EU

C522

R524

R524-*1

2.7K

0

OPT

C606

10pF

C607

10pF

75

R595

R600

DSUB_VSYNC

DSUB_HSYNC

Near Place Scart AMP

SCART_Lout_SOC

SCART_Rout_SOC

C575 100pF 50V

C587 100pF 50V

C576 330pF 50V

EU

EU R608

470K

C577 100pF 50V

R609

470K

75

R594

C6006

1uF 25V C6001

Place JACK Side

680pF C517 OPT

C514 150pF 50V

EU

1uF25V

EU

C509 150pF

EU

75

R52 8

75

1%

R606

C586 560pF 50V

OPT

75

R52 9

EU

10K

R60 06 EU

10K R6005

C582 330pF 50V OPT

75

1%

R605

L511

75

R53 0

EU L510

75 1%

R604

R614 75 1%

R615 75 1%

SCART_AMP_R_FB

SCART_AMP_L_FB

EU

C588 330pF 50V

C589 100pF 50V

DTV/MNT_V_OUT

R613 75

OPT

1%

SC_SOG_IN

10K

R555

DSUB_HSYNC DSUB_VSYNC

SC_SOG_IN

R553

Main clock for LG1152A

8pF

C513

8pF

C512

C500

R508 22K

2.2uF

C501

R509 22K

2.2uF

C502

C503

C504

C505

EU

2.2uF

R510

EU

R511

EU

R512 22K

R513 22K

22K

Place SOC Side

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+5V_NORMAL

EU

C510

0.1uF 16V

DTV/MNT_VOUT

Close to LG1152A

R536 68 R539 33 R541 68 R546 33 R547 0 R548 68 R550 33 R568 33 R569 33

R570 33 R564 150 R565 150 R566 0 R567 150

R514 75K

R515 100K

R516 75K

R517 100K

R518 75K

R519 100K

EU

R527

10K

SELECT

XIN_SUB

XO_SUB

SOC_RESET

R571 33 R572 33 R573 100

R559 68

R574 100 R551 33 R557 33 R575 33

R558 68

C516 0.047uF C518 0.047uF C523 0.047uF C526 0.047uF C527 1000pF C531 0.047uF C532 0.047uF C542 0.047uF C543 0.047uF C544 1000pF C545 0.047uF C538 0.047uF C539 0.047uF C540 1000pF C541 0.047uF

X-TAL_1

GND_1

1

2

X500

24MHz

4

3

GND_2

X-TAL_2

AUAD_L_CH5_IN

AUAD_R_CH5_IN

AUAD_L_CH4_IN

EU

AUAD_R_CH4_IN

EU

AUAD_L_CH3_IN

AUAD_R_CH3_IN

MMBT3904(NXP)

IC500

NLASB3157DFT2G

EU

R560 R561

0.047uF

R563 0

EU

22

1M

1

2

3

330 33

XO_SUB

6

VCC

5

A

4

Selece = High ==> A = B1 Selece = Low ==> A = B0

C549 C550 C551 C552 C553 C554 C555 C556 C557

C515 100pF 50V EU

R579 R580

R535

Q506

B1

GND

B0

L17 L18 P17 K17 K18

U14 T14 V15 U15 T15 U16 V14 T16 V16 V17 U17

P11 R11

V10

T11

U10 T10 V11 U11 V12 U12 T12

XIN_SUB

C

B

EU

E

LG1152AN-B2

XIN_SUB XO_SUB VSB_AUX_XIN XTLIN_AAD XTLOUT_AAD

M2

OPM1

M1

OPM0

R4

PORES_N

N3

L9A_SCL

M3

L9A_SDA

CVBS_IN1 CVBS_IN2 CVBS_IN3 CVBS_VCM CVBS_IN4 CVBS_IN5 CVBS_IN6 CB_IN CB_VCM BUF_OUT1 BUF_OUT2

P8

HSYNC

R8

VSYNC SC1_FB SC1_SID

U8

BINCOM_IN

V8

B_IN GINCOM_IN

T8

G_IN

V9

SOG_IN RINCOM_IN

U9

R_IN

T9

PB1_IN Y1_IN SOY1_IN PR1_IN PB2_IN Y2_IN SOY2_IN PR2_IN

EU

R507

10K

IC101

AAD_ADC_SIFM

AAD_ADC_SIF

AUDA_BGR_OUT

AUDA_OUTL

AUDA_OUTR AUD_SCART0_OUTLN AUD_SCART0_OUTLP AUD_SCART0_OUTRN AUD_SCART0_OUTRP

AUAD_L_CH5_IN AUAD_R_CH5_IN AUAD_L_CH4_IN AUAD_R_CH4_IN AUAD_L_CH3_IN AUAD_R_CH3_IN AUAD_L_CH2_IN AUAD_R_CH2_IN AUAD_L_CH1_IN AUAD_R_CH1_IN

AUAD_REFN

AUAD_REFP

AUAD_VR_OUT

AUMI_BIAS

AUMI_IN

AUMI_COM

DDCD0_DA DDCD0_CK

PHY0_RXCN_0 PHY0_RXCP_0 PHY0_RX0N_0 PHY0_RX0P_0 PHY0_RX1N_0 PHY0_RX1P_0 PHY0_RX2N_0 PHY0_RX2P_0

PHY0_ARC_OUT_0

ADC_I_INCOM

ADC_I_INP

ADC_I_INN

AUDA_OUTL

AUDA_OUTR

DTV_ATV_SELECT

R592

220

MMBT3906(NXP)

N17 N18

U1 R1 R2 T1 V2 U2 T2

U3 V3 V4 T3 U5 T5 U6 T6 U7 T7

T4 U4 V5

R7 R5 R6

E18 E17 E16

HPD0

J18 J17 H17 H18 G17 G18 G16 F16 F17

P12

ANTCON

M18

RFAGC

P18

IFAGC

T17 U18 T18

+5V_NORMAL

EU

E

EU

Q504

C

DTV/MNT_VOUT

C533 0.1uF C534 0.1uF

C536 2.2uF

AUAD_L_CH5_IN AUAD_R_CH5_IN AUAD_L_CH4_IN AUAD_R_CH4_IN AUAD_L_CH3_IN AUAD_R_CH3_IN

10K

R52010K

C115 C116 C117

H/NIM&CHB

R624 100

R626

R625 100

R627

R593

220 EU

B

10uFC535

AUDA_OUTL AUDA_OUTR

R501100

EU

R502100

EU

R534

R577 4.7K R578 4.7K

0.1uF

C603

0.01uF

22K

C604

0.01uF

22K

R599

75

OPT

22K

EU

R531

+3.3V_NORMAL

HDMI_CLKHDMI_CLK+ HDMI_RX0HDMI_RX0+ HDMI_RX1HDMI_RX1+ HDMI_RX2HDMI_RX2+

SPDIF_OUT_ARC

IF_AGC

HP_LOUT_MAIN

HP_ROUT_MAIN

EU

R532 22K

C5372.2uF C5472.2uF C5482.2uF

IF_N IF_P

EU

C558

1000pF

OPT

IC101

LG1152AN-B2

L1

INTR_GBB

BB_TP_VAL BB_TP_SOP BB_TP_ERR BB_TP_CLK

BB_SDA_I BB_SDA_O

BB_SCL

L9DA_SCL

CHB_DN

CHB_UP CHB_START CHB_DATA0 CHB_DATA1 CHB_DATA2 CHB_DATA3 CHB_DATA4

CLK_F54M CVBS_GC2 CVBS_GC1 CVBS_GC0

CVBS_UP CVBS_DN

FS00CLK

DAC_DATA0 DAC_DATA1 DAC_DATA2 DAC_DATA3 DAC_DATA4 DAC_START

AAD_GC0 AAD_GC1 AAD_GC2 AAD_GC3 AAD_GC4

AAD_DATA0 AAD_DATA1 AAD_DATA2 AAD_DATA3 AAD_DATA4 AAD_DATA5 AAD_DATA6 AAD_DATA7 AAD_DATA8 AAD_DATA9

HSR_AM0 HSR_AP0 HSR_BM0 HSR_BP0 HSR_CM0

HSR_CP0 HSR_CLKM0 HSR_CLKP0

HSR_DM0

HSR_DP0

HSR_EM0

HSR_EP0

HSR_AM1

HSR_AP1

HSR_BM1

HSR_BP1

HSR_CM1

HSR_CP1 HSR_CLKM1 HSR_CLKP1

HSR_DM1

HSR_DP1

HSR_EM1

HSR_EP1

L2 L3

K1 K2 J2 J3 K3 H1 H2 H3 J1

G1 G2 G3 B1 C1 A4 B4 C4 A2 D1 D2 E2 E1 F1 F2 B2 A3 C2

B3 C3 D3 E3 F3 D4 E4 F4 D5 E5 F5 D6

A5 B5 C5 A6 B6 C6

E6 F6 D7 B7 C7 A8 B8 C8

Close to LG1152A

A7

R581 33

D8 F7 E7 E8 F8

Close to LG1152A

A9

R582 33

B9

R583 33

C9 D9 E9 F9 C10 D10

E10 F10 D11 E11 F11 D12 E12 F12 D13 E13 F13 D14 E14 F14 D15 E15

F15

B10 A10 A11 B11 C12 C11 B12 A12 A13 B13 C14 C13 B14 A14 A15 B15 C16 C15 B16 A16 A17 B17 C18 C17

C529

220pF

OPT

50V

INTR_HDMI1

R576100

ATV_OUT

TUNER_SIF

SCART_Lout_SOC

SCART_Rout_SOC

EU

C520 0.01uF

C521 0.01uF

TPI_SOP TPI_CLK TPO_ERR TPO_VAL TPO_SOP TPO_CLK

CHB_DATA JDVR_SCLK

CHB_VAL CHB_ERR

TU_CVBS

SCART_Lout SCART_Rout

SC_R

CHB_CVBS

SC_CVBS_IN SC_B SC_G SC_FB SC_ID ATV_OUT

SC_L_IN

SC_R_IN TUNER_SIF TUNER_SIF

DTV/MNT_V_OUT

JDVR_SCLK

IF_N IF_P IF_AGC

FE_TS_CLK

FE_TS_SYNC

FE_TS_VAL

TPI_DVB_ERR

FE_TS_DATA[0-7]

TPO_DATA[0-7]

TPI_DATA[0-7]

TPI_ERR

TPI_VAL

OPTIC_GPIO1 OPTIC_BACK_CHANNEL

INTR_AFE3CH

AUD_HMR00ARC AUD_HMR0AMUTE AUD_HMR0ALRCK

AUD_HMR0ABCK

AUD_HMR0ASD4

AUD_HMR0ASD3

AUD_HMR0ASD2

AUD_HMR0ASD1

AUD_HMR0ASD0

AUD_DAC1_LRCH

AUD_DAC1_SCK AUD_DAC1_LRCK

AUD_FS25CLK AUD_FS24CLK AUD_FS23CLK AUD_FS21CLK AUD_FS20CLK

AUDCLK_OUT_SUB

AUD_DAC0_LRCK AUD_DAC0_LRCH

AUD_DAC0_SCK

AUD_ADC_LRCH

AUD_ADC_SCK AUD_ADC_LRCK AUD_MIC_LRCH

AUD_MIC_SCK AUD_MIC_LRCK

BB_TP_DATA0

BB_TP_DATA1

BB_TP_DATA2

BB_TP_DATA3

BB_TP_DATA4

BB_TP_DATA5

BB_TP_DATA6

BB_TP_DATA7

L9DA_SDA_I L9DA_SDA_O

AUDCLK_OUT

AAD_DATAEN

DCO_OUT_CLK

R9112 33

AH2

INTR_GBB

AG2

INTR_HDMI1

AF2

INTR_AFE3CH

AH3

AUD_HMR0ARC

AG3

AUD_HMR0AMUTE

AG4

AUD_HMR0ALRCK

AF4

AUD_HMR0ABCK

AF3

AUD_HMR0ASD4

AH5

AUD_HMR0ASD3

AG5

AUD_HMR0ASD2

AF5

AUD_HMR0ASD1

AH4

AUD_HMR0ASD0

AH6

AUD_DAC1_LRCH

AG6

AUD_DAC1_SCK

AF6

AUD_DAC1_LRCK

AH7

AUD_FS25CLK

AG7

AUD_FS24CLK

AH10

AUD_FS23CLK

AG10

AUD_FS21CLK

AF10

AUD_FS20CLK

AH8

AUDCLK_OUT_SUB

AF7

AUD_DAC0_LRCK

AE8

AUD_DAC0_LRCH

AD8

AUD_DAC0_SCK

AE7

AUD_ADC_LRCH

AD7

AUD_ADC_SCK

AC8

AUD_ADC_LRCK

AG8

AUD_MIC_LRCH

AH9

AUD_MIC_SCK

AF8

AUD_MIC_LRCK

AG9

BB_TPI_DATA0

AF9

BB_TPI_DATA1

AE9

BB_TPI_DATA2

AD9

BB_TPI_DATA3

AC9

BB_TPI_DATA4

AE10

BB_TPI_DATA5

AD10

BB_TPI_DATA6

AC10

BB_TPI_DATA7

AE11

BB_TPI_VAL

AD11

BB_TPI_SOP

AC11

BB_TPI_ERR

AE12

BB_TPI_CLK

AH11

BB_SDA_I

AG11

BB_SDA_O

AF11

BB_SCL

AH12

HS_SCL

AG12

HS_SDA_I

AF12

HS_SDA_O

AD12

CHB_DN

AC12

CHB_UP

AE13

CHB_START

AG13

CHB_DATA0

AF13

CHB_DATA1

AH14

CHB_DATA2

AG14

CHB_DATA3

AF14

CHB_DATA4

AH13

CLK_54

AE14

CVBS_GC2

AC13

CVBS_GC1

AD13

CVBS_GC0

AD14

CVBS_UP

AC14

CVBS_DN

AH15

FS00CLK

AG15

AUDCLK_TO_DIGITAL

AF15

DAC_DATA0

AE15

DAC_DATA1

AD15

DAC_DATA2

AC15

DAC_DATA3

AF16

DAC_DATA4

AE16

DAC_START

AD16

AAD_GC0

AC16

AAD_GC1

AE17

AAD_GC2

AD17

AAD_GC3

AC17

AAD_GC4

AE18

AAD_DATAEN

AD18

AAD_DATA0

AC18

AAD_DATA1

AE19

AAD_DATA2

AD19

AAD_DATA3

AC19

AAD_DATA4

AE20

AAD_DATA5

AD20

AAD_DATA6

AC20

AAD_DATA7

AE21

AAD_DATA8

AD21

AAD_DATA9

AC21

AUPLL_CLK

AG16

HS_RX1_AM

AH16

HS_RX1_AP

AH17

HS_RX1_BM

AG17

HS_RX1_BP

AF18

HS_RX1_CM

AF17

HS_RX1_CP

AG18

HS_RX1_CLKM

AH18

HS_RX1_CLKP

AH19

HS_RX1_DM

AG19

HS_RX1_DP

AF20

HS_RX1_EM

AF19

HS_RX1_EP

AG20

HS_RX2_AM

AH20

HS_RX2_AP

AH21

HS_RX2_BM

AG21

HS_RX2_BP

AF22

HS_RX2_CM

AF21

HS_RX2_CP

AG22

HS_RX2_CLKM

AH22

HS_RX2_CLKP

AH23

HS_RX2_DM

AG23

HS_RX2_DP

AF24

HS_RX2_EM

AF23

HS_RX2_EP

IC100

LG1152D-B1

STPIO_SOP/GPIO43 STPIO_VAL/GPIO42 STPIO_ERR/GPIO41

STPIO_DATA/GPIO40

TPI_DVB_CLK/GPIO47 TPI_DVB_SOP/GPIO46 TPI_DVB_VAL/GPIO45

TPI_DVB_DATA0/GPIO44

PCMI3LRCK/GPIO81

AUD_SUBSCK/GPIO51

AUD_SUBLRCK/GPIO52

STPI_CLK STPI_SOP STPI_VAL

STPI_ERR STPI_DATA STPIO_CLK

TPI_DVB_ERR

TPI_DVB_DATA1 TPI_DVB_DATA2 TPI_DVB_DATA3 TPI_DVB_DATA4 TPI_DVB_DATA5 TPI_DVB_DATA6 TPI_DVB_DATA7

TPI_CLK TPI_SOP TPI_VAL

TPI_ERR TPI_DATA0 TPI_DATA1 TPI_DATA2 TPI_DATA3 TPI_DATA4 TPI_DATA5 TPI_DATA6 TPI_DATA7

TPO_CLK

TPO_SOP

TPO_VAL

TPO_ERR TPO_DATA0 TPO_DATA1 TPO_DATA2 TPO_DATA3 TPO_DATA4 TPO_DATA5 TPO_DATA6 TPO_DATA7

AUDCLK_OUT

DACLRCH

DACSLRCH/GPIO95 DACCLFCH/GPIO94

DACSCK

DACLRCK

PCMI3LRCH

PCMI3SCK/GPIO80

IEC958OUT

AUD_SUBMCK

AUD_SUBLRCH

BTSCSEL

DTS_EN

TXA0N TXA0P TXA1N TXA1P TXA2N

TXA2P TXACLKN TXACLKP

TXA3N

TXA3P

TXA4N

TXA4P

TXB0N

TXB0P

TXB1N

TXB1P

TXB2N

TXB2P TXBCLKN TXBCLKP

TXB3N

TXB3P

TXB4N

TXB4P

PWM0/GPIO55 PWM1/GPIO54 PWM2/GPIO53

PWM_IN

AR102

CHB

AE27 AE26 AD28 AD27 AD26 AC28 AC26 AB28 AC27 AB27

AF27 AE28 AG27 AF28 AG26 AF26 AF25 AH26 AH25 AG25 AH24 AG24

H24 J25 J24 H25 J27 J26 H28 H27 H26 G28 G27 G26

D24 E23 D25 D23 H23 G25 G24 F25 F24 F23 E25 E24

C1 C2 A3 A2 B2 B1

B3 C3 A4

AE2

AD25 AC25 AD24 AE25

AB18 AB19

DTS_EN: ENABLE(’1’) (for development)

BTSC_EN: ENABLE(’1’) (for development)

N1 N2 P2 P1 P3 R3 R1 R2 T2 T1 T3 U3 U1 U2 V2 V1 V3 W3 W1 W2 Y2 Y1 Y3 AA3

L6 L5 M4 M5

47

R200

47

FE_TS_DATA[0] FE_TS_DATA[1] FE_TS_DATA[2] FE_TS_DATA[3] FE_TS_DATA[4] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7]

R542100

100

100 100

OPTIC_BACK_CHANNEL

R598 47

OPT

R619 47

OPT

R628 22

OPT

R629 47

+3.3V_NORMAL

R59622 R59722

SOC_TXA0N SOC_TXA0P SOC_TXA1N SOC_TXA1P SOC_TXA2N SOC_TXA2P SOC_TXACLKN SOC_TXACLKP SOC_TXA3N SOC_TXA3P SOC_TXA4N SOC_TXA4P SOC_TXB0N SOC_TXB0P SOC_TXB1N SOC_TXB1P SOC_TXB2N SOC_TXB2P SOC_TXBCLKN SOC_TXBCLKP SOC_TXB3N SOC_TXB3P SOC_TXB4N SOC_TXB4P

OPT EDGE_LED

BPL_IN

CHB

33

R556

TPI_DATA[0] TPI_DATA[1] TPI_DATA[2] TPI_DATA[3] TPI_DATA[4] TPI_DATA[5] TPI_DATA[6] TPI_DATA[7]

TPO_DATA[0] TPO_DATA[1] TPO_DATA[2] TPO_DATA[3] TPO_DATA[4] TPO_DATA[5] TPO_DATA[6] TPO_DATA[7]

R543

R544 R545

OPTIC_GPIO1

R631 R632

R633

R630 100

10K

100

CHB_CLK CHB_SYNC CHB_VAL CHB_ERR CHB_DATA

USB_CTL2

FE_TS_CLK FE_TS_SYNC FE_TS_VAL TPI_DVB_ERR FE_TS_DATA[0-7]

TPI_CLK TPI_SOP TPI_VAL TPI_ERR TPI_DATA[0-7]

TPO_CLK TPO_SOP TPO_VAL TPO_ERR TPO_DATA[0-7]

AUD_MASTER_CLK AUD_LRCH

FRC3_FLASH_WP AUD_SCK AUD_LRCK

C559

OPT

2.2uF

C630 82pF 50V

AMP_RESET_N

A_DIM PWM_DIM2 PWM_DIM

SPDIF_OUT

LG1152A LG1152D

LG1152 B0

MAIN AUDIO/VIDEO

3

IC100

LGE Internal Use Only

LG1152D-B1

M0_DDR_RESET_N

M0_DDR_DQSL_P M0_DDR_DQSL_N

M0_DDR_DQSU_P M0_DDR_DQSU_N

M0_DDR_ZQCAL

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_DML M0_DDR_DMU

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ2 M0_DDR_DQ3 M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7 M0_DDR_DQ8 M0_DDR_DQ9

M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

D18 E17 E18 E20 E16 D20 F16 F19 E15 D19 D14 E14 D17 F18 D16

F20 D15 F17

A17 A18 F15

F21 D22 E21 D21

E19

B20 A20

B16 C16

C19 C15

C20 B19 C21 B18 A21 C18 B21 A19 B17 C14 A16 B14 B15 A14 C17 A15 E22

R700 0 R701 0

SIGN50005

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8 M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CKE

M0_DDR_ODT M0_DDR_RASN M0_DDR_CASN M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSL_P M0_DDR_DQSL_N

M0_DDR_DQSU_P M0_DDR_DQSU_N

M0_DDR_DML M0_DDR_DMU

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ2 M0_DDR_DQ3 M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7 M0_DDR_DQ8 M0_DDR_DQ9 M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

240

1%

M0_DDR_CLK M0_DDR_CLKN

R704

VCC1.5V_MAIN

R709 10K

R705 200

R706 200

M0_DDR_CKE

M0_DDR_RESET_N

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CLK

M0_DDR_CLKN

IC700

H5TQ2G83BFR-PBC

DDR3

K4

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSL_P M0_DDR_DQSL_N

R742 10K

M0_DDR_DML

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ6

M0_DDR_DQ4 M0_DDR_DQ3 M0_DDR_DQ2 M0_DDR_DQ5

2Gbit

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

M0_DDR_VREFCA

M0_DDR_VREFDQ

J9

E2

VCC1.5V_MAIN

R720

H9

ZQ

240

1% A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

C706 0.1uF C707 C708 C709 C710 C711 C712

0.1uF

VCC1.5V_MAIN

R722

R723

1K 1%

VCC1.5V_MAIN

R724

R725

1K 1%

C724

1K 1%

C725

M0_DDR_VREFCA

0.1uF

C728

M0_DDR_VREFDQ

0.1uF

C729

1000pF

VCC1.5V_MAIN

R730

R731

1K 1%

VCC1.5V_MAIN

R732

R733

1K 1%

M0_1_DDR_VREFCA

1K 1%

C732

M0_1_DDR_VREFDQ

1K 1%

C733

0.1uF

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7

1000pF

M0_DDR_A8

1000pF

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSU_P M0_DDR_DQSU_N

M0_DDR_DMU

M0_DDR_DQ10 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ11M0_DDR_DQ7 M0_DDR_DQ15

M0_DDR_DQ9 M0_DDR_DQ8

M0_DDR_DQ12

C747

C748

H5TQ2G83BFR-PBC

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

IC703

DDR3 2Gbit

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

M0_1_DDR_VREFCA

J9

E2

H9

ZQ

A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

M0_1_DDR_VREFDQ

R739

240 1%

VCC1.5V_MAIN

C758

C746

C723

C760

C751

C756

0.1uF

C761

0.1uF

IC100

LG1152D-B1

C9 E9 F10 F12 F8 D11 E8 E11 E7 D10 C4 C5 D8 E10 C7

E12 F7 D9

A9 B9 D7

D13 C13 E13 D12

F11

C12 C11

A7 B7

A11 C6

A12 B11 A13 C10 B12 A10 B13 B10 A8 B4 C8 B5 B6 A5 B8 A6

R702 0 R703 0

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8 M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT M1_DDR_RASN M1_DDR_CASN M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSL_P M1_DDR_DQSL_N

M1_DDR_DQSU_P M1_DDR_DQSU_N

M1_DDR_DML M1_DDR_DMU

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DQ8 M1_DDR_DQ9 M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15

VCC1.5V_MAIN

M1_DDR_CKE

R710 10K

M1_DDR_RESET_N

M1_DDR_CLK

R707 200

M1_DDR_CLKN

M1_DDR_CLK

R708 200

M1_DDR_CLKN

IC100

LG1152D-B1

M2_DDR_RESET_N

R741 10K

M2_DDR_A0 M2_DDR_A1 M2_DDR_A2 M2_DDR_A3 M2_DDR_A4 M2_DDR_A5 M2_DDR_A6 M2_DDR_A7 M2_DDR_A8

M2_DDR_A9 M2_DDR_A10 M2_DDR_A11 M2_DDR_A12 M2_DDR_A13

M2_DDR_BA0 M2_DDR_BA1 M2_DDR_BA2

M2_DDR_CLK

M2_DDR_CLKN

M2_DDR_CKE

M2_DDR_ODT

M2_DDR_RASN M2_DDR_CASN

M2_DDR_WEN

M2_DDR_DQSU_P M2_DDR_DQSU_N

M2_DDR_DQSL_P M2_DDR_DQSL_N

M2_DDR_DML M2_DDR_DMU

M2_DDR_DQ0 M2_DDR_DQ1 M2_DDR_DQ2 M2_DDR_DQ3 M2_DDR_DQ4 M2_DDR_DQ5 M2_DDR_DQ6 M2_DDR_DQ7 M2_DDR_DQ8 M2_DDR_DQ9

M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15

M2_DDR_ZQCAL

M1_DDR_RESET_N

M1_DDR_DQSL_P M1_DDR_DQSL_N

D1 K4 D2 E5 H6 E4 J4 D6 J5 D3 H4 J6 K5 D4

E6 H5 F4

M2 M3 G6

F6 G5 G4 F5

D5

H3 J1

H1 H2

K3 F2

F1 L1 E3 L2 E1 M1 E2 L3 J3 G1 K2 F3 J2 G2 K1 G3 K6

M2_DDR_A0 M2_DDR_A1 M2_DDR_A2 M2_DDR_A3 M2_DDR_A4 M2_DDR_A5 M2_DDR_A6 M2_DDR_A7 M2_DDR_A8 M2_DDR_A9 M2_DDR_A10 M2_DDR_A11 M2_DDR_A12 M2_DDR_A13

M2_DDR_BA0 M2_DDR_BA1 M2_DDR_BA2

M2_DDR_CKE

M2_DDR_ODT M2_DDR_RASN M2_DDR_CASN M2_DDR_WEN

M2_DDR_RESET_N

M2_DDR_DQSU_P M2_DDR_DQSU_N

M2_DDR_DQSL_P M2_DDR_DQSL_N

M2_DDR_DML M2_DDR_DMU

M2_DDR_DQ0 M2_DDR_DQ1 M2_DDR_DQ2 M2_DDR_DQ3 M2_DDR_DQ4 M2_DDR_DQ5 M2_DDR_DQ6 M2_DDR_DQ7 M2_DDR_DQ8 M2_DDR_DQ9 M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15

240

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8

M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSL_P M1_DDR_DQSL_N

M1_DDR_DQSU_P M1_DDR_DQSU_N

M1_DDR_DML M1_DDR_DMU

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DQ8 M1_DDR_DQ9

M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2

M1_DDR_A3 M1_DDR_A4 M1_DDR_A5

M1_DDR_A6

M1_DDR_A7 M1_DDR_A8

M1_DDR_A9

M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DML

M1_DDR_DQ0

M1_DDR_DQ1

M1_DDR_DQ6

M1_DDR_DQ7 M1_DDR_DQ4 M1_DDR_DQ3 M1_DDR_DQ2 M1_DDR_DQ5

R711

1%

M2_DDR_CLK M2_DDR_CLKN

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8

J3 K9 J4

F8 G8

G10

H3 G2 F4 G4 H4

N3

C4 D4

B8 A8

B4 C8 C3 C9 E4 E9 D3 E8

A4 F2

F10

H2

H10

J8

VCC1.5V_DE

R712

R713

M2_DDR_CLK

M2_DDR_CLKN

1K 1%

IC701

H5TQ2G83BFR-PBC

DDR3 2Gbit

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQS DQS

DM/TDQS NF/TDQS

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6

VCC1.5V_DE

R714 10K

M2_DDR_RESET_N M2_CLK

M2_CLK

R715 150

M2_CLKN

R716 0 R717 0

M2_DDR_VREFCA

0.1uF 1000pF

C701

C700

VREFCA

VREFDQ

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

J9

E2

H9

ZQ

A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

M2_DDR_CKE

VCC1.5V_DE

R718

R719

1K 1%

M2_CLK M2_CLKN

M1_DDR_VREFCA

R721

240

1%

M2_DDR_VREFDQ

0.1uF

C702

C703

M1_DDR_VREFDQ

VCC1.5V_MAIN

C713 C714 C715 C716 C717 C718 C719

R743 10K

1000pF

0.1uF

M2_DDR_RESET_N

M2_DDR_A0 M2_DDR_A1 M2_DDR_A2 M2_DDR_A3 M2_DDR_A4 M2_DDR_A5 M2_DDR_A6 M2_DDR_A7 M2_DDR_A8

M2_DDR_A9 M2_DDR_A10 M2_DDR_A11 M2_DDR_A12 M2_DDR_A13

M2_DDR_BA0 M2_DDR_BA1 M2_DDR_BA2

M2_CLKN

M2_DDR_CKE

M2_DDR_ODT

M2_DDR_RASN M2_DDR_CASN

M2_DDR_WEN

M2_DDR_DQSL_P M2_DDR_DQSL_N

M2_DDR_DQSU_P M2_DDR_DQSU_N

M2_DDR_DML M2_DDR_DMU

M2_DDR_DQ0 M2_DDR_DQ1 M2_DDR_DQ2 M2_DDR_DQ3 M2_DDR_DQ4 M2_DDR_DQ5 M2_DDR_DQ6 M2_DDR_DQ7

M2_DDR_DQ8 M2_DDR_DQ9

M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15

VCC1.5V_MAIN

R726

R727

1K 1%

VCC1.5V_MAIN

R728

R729

1K 1%

M1_DDR_VREFCA

1K 1%

C726

M1_DDR_VREFDQ

1K 1%

C727

0.1uF 1000pF

C730

0.1uF 1000pF

C731

H5TQ1G63DFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

IC702

VREFCA

VREFDQ

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

NC_1 NC_2 NC_3 NC_4 NC_6

ZQ

VCC1.5V_MAIN

R734

R735

VCC1.5V_MAIN

R736

R737

M2_DDR_VREFCA

M8

H1

L8

VCC1.5V_DE

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1 J9 L1 L9 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M1_1_DDR_VREFCA

1K 1%

C734

M1_1_DDR_VREFDQ

1K 1%

C735

M2_DDR_VREFDQ

SIGN50000

C736 C737 C738 C739 C740 C741 C742 C743

C744

IC704

H5TQ2G83BFR-PBC

DDR3

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5

0.1uF

C749

0.1uF

C750

R738

C722

0.1uF

C704

0.1uF

C705

0.1uF

C720

0.1uF

C721

0.1uF

0.1uF 10uF

M1_DDR_A6 M1_DDR_A7

1000pF

M1_DDR_A8

M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN

1000pF

M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSU_P M1_DDR_DQSU_N

M1_DDR_DMU

M1_DDR_DQ10 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ11 M1_DDR_DQ15

M1_DDR_DQ9 M1_DDR_DQ8

M1_DDR_DQ12

240

10V

DDR3 1.5V bypass Cap - Place these caps near Memory

K4

A0

2Gbit

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

M1_1_DDR_VREFCA

J9

E2

H9

ZQ

A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

M1_1_DDR_VREFDQ

R740

240 1%

VCC1.5V_MAIN

C757

C752

C753

C754

C755

C745

C759

0.1uF

LG1152 B0

4MAIN DDR 50

+5V_CI_ON

LGE Internal Use Only

CI HOST I/F

PCM_RST

/PCM_WAIT

PCM_INPACK

/PCM_IORD /PCM_IOWR

R6202 R6203 R6200

CI_IN_TS_DATA[0-7]

R6211

10K

OPT

CI

22

CI

22

OPT

22

+5V_CI_ON

R6204

10K OPT

R6205

10K

OPT

CI_VS1

PCM_INPACK

/PCM_CE2

R6206 10K

+5V_CI_ON

OPT

R6207 10K

CI

C6200

0.1uF CI

/CI_CD1

CI_TS_DATA[3]

CI_TS_DATA[4] CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7]

/PCM_CE2

CI_VS1

CI_IN_TS_DATA[0] CI_IN_TS_DATA[1] CI_IN_TS_DATA[2] CI_IN_TS_DATA[3]

CI_IN_TS_DATA[4] CI_IN_TS_DATA[5] CI_IN_TS_DATA[6] CI_IN_TS_DATA[7]

CI_TS_CLK

/PCM_REG

CI_TS_VAL

CI_TS_SYNC CI_TS_DATA[0] CI_TS_DATA[1] CI_TS_DATA[2]

/CI_CD2

C6201 10uF 10V

CI

R6249

R6208 10K OPT

0

OPT

R6210

R6209

10K

OPT

5V <=> 3.3V

IC904

74LVC245A

DIR

1

A0

2

A1

3

A2

4

A3

5

A4

CI

6

A5

7

A6

8

A7

9

GND

10

IC905

74LVC1G00GW

1B 5 VCC

2A

3GND

CI

AND GATE => NAND GATE

20

19

18

17

16

15

14

13

12

11

4 Y

+3.3V_NORMAL

VCC

OE

B0

B1

B2

B3

B4

B5

B6

B7

CI

+3.3V_NORMAL

CI

C903

0.1uF

16V

C904

0

0.1uF R913

16V

OPT

EB_DATA[0]

EB_DATA[1]

EB_DATA[2]

EB_DATA[3]

EB_DATA[4]

EB_DATA[5]

EB_DATA[6]

EB_DATA[7]

DIR

/PCM_CE1

EB_DATA[0-7]

CI_ADDR[11] CI_ADDR[9]

CI_ADDR[13]

R6243 22

C6206

0.1uF

16V

CI_ADDR[12]

CI_ADDR[7] CI_ADDR[6] CI_ADDR[5]

CI_ADDR[4]

CI_ADDR[3]

CI_ADDR[2] CI_ADDR[1] CI_ADDR[0]

CI_DATA[0-7]

OPT

+5V_CI_ON

CI_ADDR[10]

CI_ADDR[11] CI_ADDR[9] CI_ADDR[8] CI_ADDR[13] CI_ADDR[14]

CI_ADDR[12] CI_ADDR[7] CI_ADDR[6] CI_ADDR[5] CI_ADDR[4] CI_ADDR[3] CI_ADDR[2] CI_ADDR[1] CI_ADDR[0]

/PCM_CE1

+5V_CI_ON

R6245

10K

OPT

+5V_CI_ON

R6244

10K

CI

R6246

10K

/PCM_OE

OPT

/PCM_WE /PCM_IRQA

CI_DATA[0-7]

CI_DATA[0] CI_DATA[1] CI_DATA[2] CI_DATA[3]

CI_DATA[0-7]

CI_DATA[4] CI_DATA[5] CI_DATA[6] CI_DATA[7]

DIR

CI

AR909

33

CI

AR910

33

WE=>OE

IOWE=>IORD

/PCM_OE

/PCM_IORD

P6200

10067972-000LF CI

GND

/CI_DET1

TS_OUT3 TS_OUT4 TS_OUT5 TS_OUT6 TS_OUT7

CARD_EN2

IORD IOWR

TS_IN_SYN

TS_IN0 TS_IN1 TS_IN2 TS_IN3

TS_IN4 TS_IN5 TS_IN6 TS_IN7

TS_OUT_CLK

CI_RESET

CI_WAIT

INPACK

TS_OUT_VAL TS_OUT_SYN

TS_OUT0 TS_OUT1 TS_OUT2

/CI_DET2

35 36 37 38 39 40 41 42

VS1

43 44 45 46 47 48 49 50

VCC

51

VPP

52 53 54 55 56 57 58 59 60

REG

61 62 63 64 65 66 67

GND

68

100

R6214

CI

0

R6213

OPT

CI

R6212 0

CI

R6215 100

0

OPT

GND

1

DAT3

2

DAT4

3

DAT5

4

DAT6

5

DAT6

6

/CARD_EN1

7

ADDR10

8

/O_EN

9

ADDR11

10

ADDR10

11

ADDR8

12

ADDR13

13

ADDR14

14

/WR_EN

15

/IRQA

16

VCC

17

VPP

18

TS_IN_VAL

19

TS_IN_CLK

20

ADDR12

21

ADDR7

22

ADDR6

23

ADDR5

24

ADDR4

25

ADDR3

26

ADDR2

27

ADDR1

28

ADDR0

29

DAT0

30

DAT1

31

DAT2

32

/IO_BIT

33

GND

34

69

G1G2

R6216

R6217

R6219

10K

OPT

CI_DATA[3] CI_DATA[4] CI_DATA[5] CI_DATA[6] CI_DATA[7]

CI

R6224 22

C6205 0.1uF

0

OPT

10K

OPT

CI

CI_DATA[0] CI_DATA[1] CI_DATA[2]

CI_IN_TS_VAL CI_IN_TS_CLK

CI_IN_TS_SYNC

CI_ADDR[10]

CI_ADDR[8]

CI_ADDR[14]

CI

TPO_DATA[0-7]

TPO_CLK TPO_SOP TPO_VAL TPO_ERR

TPO_DATA[0] TPO_DATA[1] TPO_DATA[2] TPO_DATA[3] TPO_DATA[4] TPO_DATA[5] TPO_DATA[6] TPO_DATA[7]

CI

AR904

33

AR905

CI

AR903

33

CI 33

CI_IN_TS_DATA[0] CI_IN_TS_DATA[1] CI_IN_TS_DATA[2] CI_IN_TS_DATA[3] CI_IN_TS_DATA[4] CI_IN_TS_DATA[5] CI_IN_TS_DATA[6] CI_IN_TS_DATA[7]

CI_IN_TS_CLK CI_IN_TS_SYNC CI_IN_TS_VAL

CI_ADDR[0] CI_ADDR[1] CI_ADDR[2] CI_ADDR[3]

CI_ADDR[4] CI_ADDR[5] CI_ADDR[6] CI_ADDR[7]

CI_ADDR[8]

CI_ADDR[9] CI_ADDR[10] CI_ADDR[11]

BUFFER FOR 5V => 3.3V

/CI_CD2

/CI_CD1

+5V_NORMAL

CI

10K

R915

CI C905

0.1uF 16V

CI

10K

R916

CI C906

0.1uF 16V

CI_TS_DATA[7] CI_TS_DATA[6] CI_TS_DATA[5] CI_TS_DATA[4]

CI_TS_DATA[3] CI_TS_DATA[2] CI_TS_DATA[1] CI_TS_DATA[0]

PCM_INPACK

CI_TS_CLK

CI_TS_VAL

CI_TS_SYNC

/PCM_WAIT

/PCM_IRQA

AR921

AR920

AR919

CI

100

CI

100

CI

100

GND_8

VCC_4

GND_7

GND_6

VCC_3

GND_5

2OE

48

1A0

47

1A1

46

45

1A2

44

1A3

43

42

2A0

41

2A1

40

39

2A2

38

2A3

37

3A0

36

3A1

35

34

3A2

33

3A3

32

31

4A0

30

4A1

29

28

4A2

27

4A3

26

3OE

25

CI

AR911

33

CI

AR912

33

CI

AR913

33

IC903

74LVC16244ADGG

CI

EB_ADDR[0] EB_ADDR[1] EB_ADDR[2] EB_ADDR[3]

EB_ADDR[4] EB_ADDR[5] EB_ADDR[6] EB_ADDR[7]

EB_ADDR[8] EB_ADDR[9] EB_ADDR[10] EB_ADDR[11]

+3.3V_NORMAL

1OE

1

1Y0

2

1Y1

3

GND_1

4

1Y2

5

1Y3

6

VCC_1

7

2Y0

8

2Y1

9

GND_2

10

2Y2

11

2Y3

12

3Y0

13

3Y1

14

GND_3

15

3Y2

16

3Y4

17

VCC_2

18

4Y0

19

4Y1

20

GND_4

21

4Y2

22

4Y3

23

4OE

24

CI_ADDR[12] CI_ADDR[13] CI_ADDR[14]

/PCM_REG

/PCM_OE

/PCM_WE /PCM_IORD /PCM_IOWR

C900

0.1uF

16V

CI

CAM_WAIT_N CAM_IREQ_N

CAM_CD2_N

CAM_CD1_N

CAM_INPACK_N

75

AR916

CI

33

AR915

AR914

CI

AR918 75

75

TPI_DATA[3]

TPI_DATA[2]

TPI_DATA[1]

TPI_DATA[0]

EB_ADDR[12] EB_ADDR[13] EB_ADDR[14] CAM_REG_N

EB_OE_N EB_WE_N EB_BE_N1 EB_BE_N0

CI

AR917

TPI_CLK

TPI_VAL

TPI_SOP

TPI_DATA[7]

TPI_DATA[6]

TPI_DATA[5]

TPI_DATA[4]

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

RL_ON

LGE Internal Use Only

+3.5V_ST

eMMC POWER

+3.3V_NORMAL

L2319

C2371

0.1uF 16V

1

+3.5V_ST

L2301 BLM18PG121SN1D

C2301

4.7uF 10V

POWER_ON/OFF1

+3.5V_ST

R2305 10K

+12V

C2306

0.1uF 50V

3.3V_EMMC

BLM18PG121SN1D

R2300 10K

10K

1

R2306

2

Q2301 MMBT3906(NXP)

3

L2303

BLM18SG121TN1D

C2307

0.1uF 16V

CIS21J121

L2302

+1.8V_NORMAL

L2306 BLM18PG121SN1D

C2372

0.1uF 16V

+1.8V

AP7173-SPG-13 HF(DIODES)

IC2300

IN

1

PG

2

VCC

3

EN

4

1.5A

GND/P.DIM2

PWM_DIM2

9

THERMAL

PWR ON

24V GND GND

3.5V

3.5V GND GND 12V 12V 12V

EMMC_VCCQ

[EP]

OUT

8

FB

7

SS

6

GND

5

OPT P2301 FW20020-24S

LPB

R2302 100

L2305

CIS21J121

C2317

0.1uF 50V

L/DIM0_VS

A_DIM

1

3

5

7

9

11

13

15

17

19

21

21 22

23

23 24

25

SMAW200-H24S2

P2300

2

2 4

4 6

6 8

8

10

10 12

12 14

14 16

16 18

18 20

20 22 24

24V 24V GND GND

3.5V

3.5V GND GND/V-sync INV ON A.DIM P.DIM1 Err OUT

Tuner 1.25V REG Input

+3.3V_TU

C2376 22uF 10V

SAMSUNG_eMMC

293 mA

+1.8V_NORMAL

1%

R1

C2308 2200pF 50V

R2314 3K 1%

R2315 100 1%

1/16W

3.9K R2321

R2

C2313 10uF 10V

C2315

0.1uF 16V

+24V

R2312 100

PWM_DIM

L2314 BLM18PG121SN1D

+3.3V_NORMAL

R2330 1K

0

R2304

+3.3V_TU_IN

ERROR_OUT

INV_CTL

3. soft start

POWER_ON/OFF2_2

+12V

L2311

CIS21J121

1

+12V

L2310 BLM18PG121SN1D

C2322 10uF 16V

Switching freq: 700K

+3.3V_NORMAL

+5V_NORMAL

R2334 10K

PANEL_CTL

+5V_Normal

R2301 10KPOWER_ON/OFF1

POWER_ON/OFF2_1

R1

C2334 100pF

50V

R2

1%

R2308

56K

R2311

10K 1%

OPT

R2348

10K

+2.5V

AP7173-SPG-13 HF(DIODES)

IN

1

PG

2

VCC

C2324

10uF

10V

3

EN

4

PANEL_POWER

0.01uF

R2341

C2336 1uF 10V

IC2303

THERMAL

1.5A

10K

C2326 50V

9

C2328

0.1uF 50V

33K

5.6K

C

Q2304 MMBT3904(NXP)

E

IC2304

TPS54327DDAR

1

9

2

THERMAL

3

4

3A

C2332 10uF

16V

VREG5

C2342 2200pF 50V

R2343

R2344

B

EN

VFB

SS

Vout=0.765*(1+R1/R2)

[EP]

OUT

8

FB

7

SS

6

GND

5

C2331 2200pF 50V

8

7

6

5

C2335

0.1uF 50V

[EP]GND

VIN

VBST

SW

GND

R2347

4.3K 1%

R2346 2K 1%

AO3407A

OPT

R2

Q2305

R1

S

G

MAX 1A

C2345

0.1uF 16V

D

700 mA

1uF

C2339

OPT

L2313

6.8uH

NR8040T4R7N

C2340 10uF 10V

25V

+2.5V_NORMAL

TYP 1450mA

+5V_NORMAL

C2343 22uF 10V

C2344

0.1uF 16V

PANEL_VCC

C2346

0.1uF 50V

Power_DET

+12V

4

+12V

L2309

BLM18PG121SN1D

C2354

10uF 16V

C2303

0.1uF 50V

4

+3.5V_ST

+24V

PD_24V R2364

8.2K 1%

PD_24V R2365

1.5K 1%

PD_+3.5V R2366 0 5%

C2359

0.1uF 16V

C2360

0.1uF 16V

VCC

PD_24V

PD_+12V R2362

2.7K 1%

PD_+12V R2363

1.2K 1%

+1.0V_VDD

VIN2

VIN1

VBST

SW2

SW1

IC2306

TPS54425PWPR

14

13

12

4A

11

10

9

8

THERMAL

15

1

2

3

4

5

6

7

[EP]PGND

PGND2

PGND1

Vout=0.765*(1+R1/R2)

R2373 100K

IC2307

NCP803SN293

3

1

GND

PD_24V

R2372 100K

PD_24V

IC2308

NCP803SN293

3

1

GND

VO

VFB

VREG5

SS

GND

PG

EN

RESET

2

RESET

2

R2309 100K

R2310 10K

C2305

0.1uF OPT

C2318 1uF 10V

+3.5V_ST

R2376 10K

OPT

not to RESET at 8kV ESD

LG1152 Max: 1728 mA LG1132 Max: 2000 mA

R1

R2313

9.1K

C2368 22uF 10V

1%

C2369 22uF 10V

C2319 3300pF 50V

POWER_ON/OFF2_3

L2316

2uH

POWER_DET

C2365

0.1uF 16V

24V-->3.48V 12V-->3.58V

ST_3.5V-->3.5V

URSA5 R2322-*1 24K

1%

R2

R2322 22K

1%

FRC3

OPT

C2321 22pF 50V

+1.0VDC

Vout=0.8*(1+R1/R2)

2

C2353 3300pF 50V OPT

OPT

MAX 4.7 A

+3.3V_NORMAL

L2318

CIS21J121

R2319

1.5K

R2382

30K

1/16W

1%

R2320

10K

L2307

CIS21J121

R1

1%

R2

L2300

BLM18PG121SN1D

Placed on SMD-TOP

C2300

C2304

10uF

16V

+12V

+3.3V_NORMAL

IC2301

[EP]LX

AOZ1038PI

C2309

0.1uF 16V OPT

PGND

VIN

AGND

FB

NC_2

1

8

NC_1

9

2

7

THERMAL

EN

3

6

COMP

4

5

6A

D2350

ADUC 20S 02 010L

*NOTE 17

OPT

R23160

R2317

20K

C2310

0.1uF 16V

C2311

2200pF

50V

R2318

L2304

2uH

10K

C2312 10uF 10V

POWER_ON/OFF2_1

C2314 10uF 10V

C2316 10uF 10V

C2352 10uF 10V

Vout=0.8*(1+R1/R2)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C2302

4.7uF 16V

RT/CLK

GND_1

GND_2

PVIN_1

PVIN_2

VIN

VSENSE

IC2305

EAN62348501

1

15

2

THERMAL

3

4

5

6

7

[EP]GND

PWRGD

14

C2349

BOOT

13

0.1uF 16V

PH_2

12

PH_1

11

EN

10

SS/TR

9

COMP

8

1.3K R2307

C2348

4700pF 50V

47pF 50V

22000pF 50V

C2373

R2381 0

Max 5926 mA

L2317

1uH

R2357 1K

C2374

1/16W

5%

Switching freq: 400 ~ 580 Khz

+0.9V_VDD

C2363

C2350

22uF

10V

POWER_ON/OFF2_3

OPT C2370 10uF 10V

Vout=0.8*(1+R1/R2)

4

+3.5V_ST

DDR MAIN 1.5V

L2308

C2320 10uF 10V

VIN_1

VIN_2

GND_1

GND_2

EP[GND]

1

2

3

4

10K

R2339

C2325

0.1uF

THERMAL

17

IC2302

TPS54319TRE

3A

7

5

6

COMP

AGND

VSENSE

3A

16V

BOOT14PWRGD15EN16VIN_3

13

12

11

10

9

8

RT/CLK

1/16W 5%

$ 0.145

PH_3

PH_2

PH_1

SS/TR

R2340 15K

C2327

0.1uF

16V

R2342

C2329

0.01uF 50V

330K1/16W 5%

C2330

4700pF

50V

NR8040T3R6N

POWER_ON/OFF2_3

L2312

3.6uH

C2333 22uF 10V

C2337 22uF 10V

1074 mA

+1.5V_DDR

C2341

0.1uF 16V

C2338 100pF 50V

R2349

R1

47K 1%

R2

R2350 56K 1/16W 1%

C2375 180pF 50V

R2378-*1

8.2K

1/16W

R2379-*1

15K

+0.9V_VDD

R2378

6.8K

R2379

12K

URSA5

1%

URSA5

1/16W

1%

Vout=0.6*(1+R1/R2)

1/16W

+12V

R2377 100K

C2347 10uF 16V

1/16W 5%

L2315

R1

1%

FRC3

R2

1%

FRC3

Vout=0.827*(1+R1/R2)=1.521V

LG1152

POWER