LG 55LM9600-UC, 84LM9600, 84LM9600-UC, 55LM9600-SA, 47LM9600 Service Manual

Printed in KoreaP/NO : MFL67460305 (1204-REV00)

CHASSIS : LA23E

MODEL : 55LM9600 55LM9600-UC

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

LED LCD TV

SERVICE MANUAL

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

Internal Use Only

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION .............................................................. 10

EXPLODED VIEW .................................................................................. 18

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental shorts of th e cir cuitry that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exp ose d metallic par t. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

IMPORTANT SAFETY NOTICE

SAFETY PRECAUTIONS

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This spec sheet is applied LCD TV with ( LA23E ) chassis

2. Test condition

Each part is tested as below without special notice.

1)

Temperature : 25

ºC

± 5 ºC (77±9 ºF), CST : 40±5

ºC

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage : Standard input voltage
(220~240V@ 60Hz)

4) Specification and performance of each parts are followed
ea ch drawing and s pe cificatio n b y p art number in
accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to
the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : UL, CSA, CE, IEC specification

- EMC: FCC, ICES, CE, IEC specification

- Wireless : WirelessHD Specification (Option)

4. General Specification

No Item Specication Remark

1 Market 1) North America

2 Broadcasting System 1) ATSC / NTSC

3 Receiving System 1) VSB/64 & 256 QAM/ NTSC-M

4 Input Voltage AC 100 ~ 240V 50/60Hz FHD + T120Hz

5 Available Channel 1) VHF : 02~13

2) UHF : 14~69

3) DTV : 02-69

4) CATV : 01~135

5) CADTV : 01~135

6 Screen Size 47/55 inche Wide(1920 × 1080) 47/55LM9600-UC

7 Aspect Ratio 16:9

8 Tuning System FS

9 LCD Module LC470DUT-SEF1 LGD 47LM9600-UC

LC550DUT-SEF1 LGD 55LM9600-UC

10 Operating Environment 1) Temp : 0 ~ 40 deg

2) Humidity : ~ 80 %

11 Storage Environment 1) Temp : -20 ~ 60 deg

2) Humidity : ~ 85 %

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

5. External input format

5.1. 2D mode

5.1.1. Component input (Y, CB/PB, CR/PR)

5.1.2. RGB Input (PC)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1. 720*480 15.73 60.00 13.5135 SDTV ,DVD 480I

2. 720*480 15.73 59.94 13.50 SDTV ,DVD 480I

3. 720*480 31.50 60.00 27.027 SDTV 480P

4. 720*480 31.47 59.94 27.00 SDTV 480P

5. 1280*720 45.00 60.00 74.25 HDTV 720P

6. 1280*720 44.96 59.94 74.176 HDTV 720P

7. 1920*1080 33.75 60.00 74.25 HDTV 1080I

8. 1920*1080 33.72 59.94 74.176 HDTV 1080I

9. 1920*1080 67.50 60.00 148.50 HDTV 1080P

10. 1920*1080 67.432 59.94 148.352 HDTV 1080P

11. 1920*1080 27.00 24.00 74.25 HDTV 1080P

12. 1920*1080 26.97 23.94 74.176 HDTV 1080P

13. 1920*1080 33.75 30.00 74.25 HDTV 1080P

14. 1920*1080 33.71 29.97 74.176 HDTV 1080P

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1 640*350 31.468 70.09 25.17 EGA Х

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1360*768 47.712 60.015 85.50 VESA (WXGA) Х

7 1920*1080 67.5 60 148.8 WUXGA

(Reduced Blanking)

O

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

5.1.3. HDMI Input 1 (PC/DTV)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed

HDMI-PC

1 31.468 70.09 25.17 25.17 EGA Х

2 31.469 70.08 28.32 28.32 DOS O

3 31.469 59.94 25.17 25.17 VESA(VGA) O

4 37.879 60.31 40.00 40.00 VESA(SVGA) O

5 48.363 60.00 65.00 65.00 VESA(XGA) O

6 54.348 60.053 80.00 85.50 VESA O

7 63.981 60.020 108.00 108.00 VESA (SXGA) O

8 47.712 60.015 85.50 148.5 VESA (WXGA) O

9 1920*1080 67.5 60 148.5

WUXGA(Reduced Blanking)

O

HDMI-DTV

1 720*480 31.50 60.00 27.027 SDTV 480P

2 720*480 31.47 59.94 27.00 SDTV 480P

3 1280*720 45.00 60.00 74.25 HDTV 720P

4 1280*720 44.96 59.94 74.176 HDTV 720P

5 1920*1080 33.75 60.00 74.25 HDTV 1080I

6 1920*1080 33.72 59.94 74.176 HDTV 1080I

7 1920*1080 67.50 60.00 148.50 HDTV 1080P

8 1920*1080 67.432 59.94 148.352 HDTV 1080P

9 1920*1080 27.00 24.00 74.25 HDTV 1080P

10 1920*1080 26.97 23.976 74.176 HDTV 1080P

11 1920*1080 33.75 30.00 74.25 HDTV 1080P

12 1920*1080 33.71 29.97 74.176 HDTV 1080P

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

5.2. 3D mode

5.2.1. RF Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 45 60 74.25 HDTV 1080I Side by Side (Half), Top & Bottom

2 1280*720 45 60 74.25 HDTV 720P Side by Side (Half), Top & Bottom

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Remark

1 1280*720p 45.00 60.00 74.25 Side by Side (Half) , Top & Bottom,

Single Frame Sequential

2 1920*1080i 33.75 60.00 74.25 Side by Side (Half) , Top & Bottom

3 1920*1080p 67.50 60.00 148.50 Side by Side (Half) , Top & Bottom

Checkerboard, Single Frame Sequential
Row Interleaving, Column Interleaving

4 1920*1080p 27.00 24.000 74.25 Side by Side (Half) , Top & Bottom

Checkerboard

5 1920*1080p 33.75 30.000 74.25 Side by Side (Half), Top & Bottom

Checkerboard

5.2.6. HDMI 1.3(3D supported mode manually)

5.2.2. USB Input (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 33.75 30.00 74.25 HDTV 1080p Side by Side (Half), Top & Bottom,

Checkerboard, MPO (Photo)

5.2.4. HDMI-PC Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Remark

1 1024*768 48.363 60.004 65.000 Side by Side (Half), Top & Bottom

2 1360*768 47.712 60.015 85.500 Side by Side (Half), Top & Bottom

3 1920*1080 67.50 60.00 148.50 Side by Side (Half), Top & Bottom

Checkerboard, Single Frame Sequential
Row Interleaving, Column Interleaving

5.2.5. RGB-PC Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Remark

1 1920*1080 67.5 60.000 148.5 Side by Side (Half) , Top & Bottom

2 1360*768 47.712 60.015 85.50 Side by Side (Half) , Top & Bottom

3 1024*768 48.363 60.00 65.00 Side by Side (Half) , Top & Bottom

5.2.3. USB Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 33.75 30.00 74.25 HDTV 1080p Side by Side (Half), Top & Bottom

Checkerboard, Single Frame
Sequential,
Row Interleaving, Column Inter­leaving
(Photo : Side by Side, Top & Bot­tom)

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

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5.2.7. HDMI 1.4a(3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1280*720p 89.91 / 90.00 59.94 / 60.00 148.35 / 148.50 Mandatory Frame Packing,

2 1280*720p 44.96 / 45.00 59.94 / 60.00 74.18 / 74.25 Mandatory Top & Bottom

3 1920*1080i 33.72 / 33.75 59.94 / 60.00 74.18 / 74.25 Mandatory Side by Side (Half)

4 1920*1080p 43.94 / 54.00 23.97 / 24.00 148.35 / 148.50 Mandatory Frame Packing,

5 1920*1080p 26.97 / 27.00 23.97 / 24.00 74.18 / 74.25 Mandatory Top & Bottom

6 1280*720p 44.96 / 45.00 59.94 / 60.00 74.18 / 74.25 Primary Side by Side (Half)

7 1920*1080i 67.432 / 67.50 59.94 / 60.00 148.35 / 148.50 Primary Frame Packing

8 1920*1080p 67.43 / 67.50 59.94 / 60.00 148.35 / 148.50 Primary Top & Bottom

9 1920*1080p 26.97 / 27.00 23.97 / 24.00 74.18 / 74.25 Primary Side by Side (Half)

10 1920*1080p 67.432 / 67.50 29.976 / 30.00 148.35 / 148.50 Primary Frame Packing,

11 1920*1080p 33.716 / 33.75 29.976 / 30.00 74.18 / 74.25 Primary Top & Bottom

12 1920*1080i 33.72 / 33.75 59.94 / 60.00 74.18 / 74.25 Secondary Top & Bottom

13 1920*1080p 67.43 / 67.50 59.94 / 60.00 148.35 / 148.50 Secondary Side by Side (Half)

14 1920*1080p 33.716 / 33.75 29.976 / 30.00 74.18 / 74.25 Secondary Side by Side (Half)

15 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 Secondary (16:9) Frame Packing,

16 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (16:9) Top & Bottom

17 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (16:9) Side by Side (Half)

18 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 Secondary (4:3) Frame Packing,

19 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (4:3) Top & Bottom

20 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (4:3) Side by Side (Half)

21 640*480p 62.938 / 63.00 59.94 / 60.00 50.35 / 50.40 Secondary Frame Packing,

22 640*480p 31.469 / 31.50 59.94 / 60.00 25.175 / 25.20 Secondary Top & Bottom

23 640*480p 31.469 / 31.50 59.94 / 60.00 25.175 / 25.20 Secondary Side by Side (Half)

24 1280*720p 89.91 / 90.00 59.94 / 60.00 148.35 / 148.50 Line Alternative

25 1280*720p 44.96 / 45.00 59.94 / 60.00 148.35 / 148.50 Side by Side (Full)

26 1920*1080i 67.432 / 67.50 59.94 / 60.00 148.35 / 148.50 Field Alternative

27 1920*1080i 33.72 / 33.75 59.94 / 60.00 148.35 / 148.50 Side by Side (Full)

28 1920*1080p 43.94 / 54.00 23.97 / 24.000 148.35 / 148.50 Line Alternative

29 1920*1080p 26.97 / 27.00 23.97 / 24.000 148.35 / 148.50 Side by Side (Full)

30 1920*1080p 67.432 / 67.50 29.976 / 30.00 148.35 / 148.50 Line Alternative

31 1920*1080p 33.716 / 33.75 29.976 / 30.00 148.35 / 148.50 Side by Side (Full)

32 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 16:9 Line Alternative

33 720*480p 31.469 / 31.50 59.94 / 60.00 54.00 / 54.054 16:9 Side by Side (Full)

34 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 4:3 Line Alternative

35 720*480p 31.469 / 31.50 59.94 / 60.00 54.00 / 54.054 4:3 Side by Side (Full)

36 640*480p 62.938 / 63.00 59.94 / 60.00 50.35 / 50.40 Line Alternative

37 640*480p 31.469 / 31.50 59.94 / 60.00 50.35 / 50.40 Side by Side (Full)

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

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5.3. 2D to 3D Mode

- Remark: 3D Input mode

No. Side by Side Top & Bottom Checkerboard Single Frame

Sequential

Frame Packing Line

Interleaving

Column

Interleaving

1

R

L

R

L

5.2.10. Component Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1280*720 44.96 59.94 74.176 HDTV 720P Side by Side, Top & Bottom

2 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom

3 1920*1080 33.72 59.94 74.176 HDTV 1080I Side by Side, Top & Bottom

4 1920*1080 67.500 60 148.50 HDTV 1080P Side by Side, Top & Bottom

5 1920*1080 67.432 59.94 148.352 HDTV 1080P Side by Side, Top & Bottom

6 1920*1080 27.000 24.000 74.25 HDTV 1080P Side by Side, Top & Bottom

7 1920*1080 26.97 23.976 74.176 HDTV 1080P Side by Side, Top & Bottom

8 1920*1080 33.75 30.000 74.25 HDTV 1080P Side by Side, Top & Bottom

9 1920*1080 33.71 29.97 74.176 HDTV 1080P Side by Side, Top & Bottom

5.2.8. DLNA Input (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 33.75 30.00 74.25 HDTV 1080p Side by Side (Half), Top & Bottom,

Checkerboard, MPO (Photo)

5.2.9. DLNA Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 33.75 30.00 74.25 HDTV 1080p Side by Side (Half), Top & Bottom

Checkerboard, Single Frame
Sequential,
Row Interleaving, Column Inter­leaving
(Photo : Side by Side, Top & Bot­tom)

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

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ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to LA23E/J Chassis applied LCD TV
all models manufactured in TV factory

2. Specification

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation

transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 ±5 °C of temperature and 65±10% of relative humidity if

there is no specific designation.
(4) The input voltage of the receiver must keep 100~240V,

50/60Hz.
(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15 °C
In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours

In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above
15°C for 3 hours.

[Caution]
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong.
Digital pattern 13ch and/or Cross hatch pattern 09ch), there
can some afterimage in the black level area

3. Adjustment items

3.1. Final assembly adjustment

▪ EDID/DDC check
▪ White Balance adjustment
▪ ADC Adjustment check
▪ RS-232C functionality check
▪ Factory Option setting per destination
▪ Ship-out mode setting (In-Stop)

3.2. Etc

▪ Ship-out mode
▪ Tool option menu
▪ USB Download(S/W Update, Option, Service only)

3.3. Automatic Adjustment

3.3.1. Overview

ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation

3.3.2. Equipment & Condition

1) Jig (RS-232C protocol)

2) Inner Pattern

- Resolution : 1080p (Inner Pattern)

- Resolution : 1024*768 RGB (Inner Pattern)

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7±0.1 Vp-p

3.3.3 Adjustment

3.3.3.1. Adjustment method

▪ Using RS-232, adjust items listed in 3.1 in the other shown in

“4.1.3.3”

3.3.3.2. Adj. protocol

3.3.3.3 Adj. order

▪ aa 00 00 [Enter ADC adj. mode]
▪ xb 00 40 [Change input source to Component1(480i)]
▪ ad 00 10 [Adjust 480i Comp1]
▪ xb 00 60 [Change input source to RGB(1024*768)]
▪ ad 00 10 [Adjust 1024*768 RGB]
▪ ad 00 90 End adj.

Ref) ADC adj. RS232C Protocol_Ver1.0

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change xb 00 40

xb 00 60

b 00 OK40x (Adjust 480i Comp1 )
b 00 OK60x (Adjust 1024*768 RGB)

Begin adj. ad 00 10

Return adj. result OKx (Case of Success)

NGx (Case of Fail)

Read adj. data (main)

ad 00 20

(sub )
ad 00 21

(main)
000000000000000000000000007c007b006dx

(Sub)
000000070000000000000000007c00830077x

Conrm adj. ad 00 99 NG 03 00x (Fail)

NG 03 01x (Fail)
NG 03 02x (Fail)
OK 03 03x (Success)

End adj. aa 00 90 a 00 OK90x

- 11 -

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4. Manual Adjustment

4.1. MAC Address, ESN Key and Widevine
Key download

4.1.1. Equipment & Condition

1) Play file: keydownload.exe

4.1.2. Communication Port connection

1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

4.1.3. Download process

1) Select the download items.

2) Mode check: Online Only

3) Check the test process

- U S, Canad a m ode ls : DET EC T -> M AC _WR IT E ->
WIDEVINE_WRITE

- Korea, Me xico models: DE TECT -> MA C_WRITE ->
WIDEVINE_WRITE

4) Play : START

5) Check of result: Ready, Test, OK or NG

6) Printer out (MAC Address Label)

4.1.4. Communication Port connection

1) Connect: PCBA Jig -> RS-232C Port == PC -> RS-232C

Port

4.1.5. Download

1) US, Canada, Mexico models (12Y LCD TV + MAC +
Widevine + ESN Key)

2) Korea, Mexico models (11Y LCD TV + MAC + Widevine
Only)

4.1.6. Inspection

- In INSTART menu, check these keys.

- 12 -

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4.2. PING Test

* LAN card can be verified by using PING test

4.2.1 Adjustment Method(Board)

(1) Connect LAN to the board and power on.
(Default IP can be set to automatic setting. When power

ON, IP can be automatically be achieved from the router)
(2) Press ADJ key in the adjustment remote control.
(3) Check Network status by pressing 13. ACAP PING TEST

in EZ ADJUST. If it operates properly, it will show “Network
is operating properly.” If it does not, it will show “Network is
not working properly.”

4.2.2 Adjustment Method(Manufacturer)

(4) Connect the PC with PING Test program installed and the

LAN port of the SET via Cross LAN Cable. (The IP setting
of the PC has to be 12.12.2.3)

(5) After the PING Test program has been executed, check the

program setting. (IP of the set will be 12.12.2.2. Double
check the setting. Do not check the Modem because it will
not be used.)

(6) Press the Power Only Key in Adjustment remote control.

(IP of the set will be set)

(7) Upon pressing “RUN” in the program, it will show “OK” or

“NG” according to the test result.

● After all the adjustments, to disable the IP setting, press

INSTOP key.

4.3 EDID Download

4.3.1 Overview

▪ It is a VESA regulation. A PC or a MNT will display an optimal

resolution through information sharing without any necessity
of user input. It is a realization of “Plug and Play”.

4.3.2 Equipment

▪ Since embedded EDID data is used, EDID download JIG,

HDMI cable and D-sub cable are not need.

▪ Adjust remocon

4.3.3 Download method

1) Press Adj. key on the Adj. R/C,

2) Select EDID D/L menu.

3) By pressing Enter key, EDID download will begin

4) If Download is successful, OK is display, but If Download is
failure, NG is displayed.

5) If Download is failure, Re-try downloads.

※ Caution) When EDID Download, must remove RGB/HDMI

Cable.

4.3.3.1. EDID DATA
# HDMI 1(C/S : 43 2C)
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 2C

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# HDMI 2(C/S : 43 1C)
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 3D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 1C

# HDMI 3(C/S : 43 0C
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 4D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 0C

# HDMI 4(C/S : 43 FC)
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 5D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 FC

# RGB(C/S : 5C)
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 5C

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

4.4. White Balance Adjustment

4.4.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel’s W/B deviation
(2) How-it-works: When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.

(3) Adj. condition: normal temperature

- Surrounding Temperature: 25±5 °C

- Warm-up time: About 5 Min

- Surrounding Humidity: 20% ~ 80%

4.4.2. Equipment

(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:

CH14)

(2) Adj. Computer (During auto adj., RS-232C protocol is

needed)
(3) Adjust Remocon
(4) Vi deo Signal Generator MSPG-925F 720p/204- Gray

(Model: 217, Pattern: 49)
※ Color Analyzer Matrix should be calibrated using CS-1000

4.4.3. Equipment connection

4.4.4. Adjustment Command (Protocol)

(1) RS-232C Command used during auto-adj.

RS-232C COMMAND

Explanation

CMD DATA ID

Wb 00 00 Begin White Balance adj.

Wb 00 ff End White Balance adj.

(internal pattern disappears )

(2) Adjustment Map

Adj. item Command

(lower caseASCII)

Data Range
(Hex.)

CMD1 CMD2 MIN MAX

Cool R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

Medium R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

Warm R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

4.4.5. Adj. method

4.4.5.1. Auto adj. method
(1) Set TV in ADJ mode using P-ONLY key (or POWER ON

key)

(2) Place optical probe on the center of the display

- It need to check probe condition of zero calibration before

adjustment.
(3) Connect RS-232C Cable
(4) Select mode in ADJ Program and begin a adjustment.
(5) When WB adjustment is completed with OK message,

check adjustment status of pre-set mode (Cool, Medium,

Warm)
(6) Remove probe and RS-232C cable.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need

4.4.5.2. Manual adj. method
(1) Set TV in Adj. mode using POWER ON
(2) Zero Calibrate the probe of Color Analyzer, then place it on

the center of LCD module within 10cm of the surface..

(3) Press ADJ key -> EZ adjust using adj. R/C -> 9. White-

Balance then press the cursor to the right (KEY►). When
KEY(►) is pressed 216 Gray internal pa ttern will be

displayed.

(4) One of R Gain / G Gain / B Gain should be fixed at 192,

and the rest will be lowered to meet the desired value.

(5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of

color temperature.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 6.White Balance, you can select one of 2 Test-pattern:
ON, OFF. Default is inner (ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.

▪ Adj. condition and cautionary items

(1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to isolate

adj. area into dark surrounding.

(2) Probe location: Color Analyzer (CA-210) probe should be

within 10cm and perpendicular of the module surface (80°~
100°)

(3) Aging time

- After Aging Sta rt, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked using no

signal or Full-white pattern.

Color Analyzer

Computer

Pattern Generator

※

Signal Source

Probe

RS-232C

RS-232C

RS-232C

※

If TV internal pattern is used, not needed

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

4.4.6. Reference (White Balance Adj. coordinate and
color temperature)

▪ Luminance: 204 Gray
▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Coordinate

Temp △uv

X Y

Cool 0.269 0.273 13,000K 0.0000

Medium 0.285 0.293 9,300K 0.0000

Warm 0.313 0.329 6,500K +0.0030

▪

Standard color coordinate and temperature using CA-210(CH 18) - ALEF

Mode

Coordinate

Temp △uv

X Y

Cool 0.269±0.002 0.273±0.002 13,000K 0.0000

Medium 0.285±0.002 0.293±0.002 9,300K 0.0000

Warm 0.313±0.002 0.329±0.002 6,500K +0.0030

▪

Standard color coordinate and temperature using CA-210(CH 14) - LGD

Mode

Coordinate

Temp △uv

X Y

Cool 0.269±0.002 0.273±0.002 13,000K 0.0000

Medium 0.285±0.002 0.293±0.002 9,300K 0.0000

Warm 0.313±0.002 0.329±0.002 6,500K 0.0000

4.4.6.1 ALELF&EDGE LED&IOL White balance table

▪ Edge LED module change color coordinate because of aging time
▪

apply under the color coordinate table, for compensated aging time

Edge (LM860X)

GP4

Aging time

(Min)

Cool Medium Warm

X Y X Y X Y

269 273 285 293 313 329

1 0-2 283 293 299 313 320 339

2 3-5 282 291 298 311 319 337

3 6-9 281 290 297 310 318 336

4 10-19 279 289 295 309 316 335

5 20-35 277 284 293 304 314 330

6 36-49 274 279 290 299 311 325

7 50-79 271 277 287 297 308 323

8 80-149 270 274 286 294 307 320

9 Over 150 269 273 285 293 306 319

4.4.7 THX Adjustment (For US Models)

For THX models, White Balance 4 point automatic control can
be done through the below steps. (Warm axis)
(1) 100 IRE White Balance Adjustment done.
(2) Control Backlight so the Maximum brightness
*In case of 100 IRE adjustment, backlight target value is
125cd/m2.
(3) 4 Point gamma and W/B adjustment done.
* With the controlled maximum brightness, adjust the Gamma

2.2 (60, 40, and 20 IRE / do not adjust at 80 IRE)

*For 10 IRE, set R, G, B gain to 0, 0, and 0, respectively.

4.5. Option selection per country

4.5.1. Overview

(1) Press ADJ key on the Adj. R/C, and then select Country

Group Menu.

(2) Depending on destination, select KR or US, then on the

lower Country option, select US, CA, MX. Selection is done
using +, - KEY

4.6. Tool Option Inspection

▪ Method: Press Adj. key on the Adj. R/C, then select Tool option.

Model Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6 Tool 7

47LM9600-UC

32999 45122 30605 20527 55823 1324 63115

55LM9600-UC

33001 45122 30605 20527 55823 1324 63115

4.7. Local Dimming Inspection (Optional)

4.7.1. ALEF models with local dimming

(1) Press ‘TILT” key of the Adj. R/C and check movin g

patterns. The black bar patterns moves from top to bottom.

If a local dimming function does not work, a whole screen

shows full white

4.8. Ship-out mode check (In-stop)

▪ After final inspection, press In-Stop key of the Adj. R/C and

check that the unit goes to Stand-by mode.

▪ After final inspection, Always turn on the Mechanical S/W.

4.9. WIFI MAC ADDRESS CHECK

a. Using RS232

Command Set ACK

Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]

b. check the menu on in-start

Note that there are Wi-Fi MAC and MAC address.
Wi-Fi MAC is used for wireless network and MAC address is used
for wired network

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

5. GND and Internal Pressure check

5.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord; Antenna cable and A/V
arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER (GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically.

(Remove CORD, A/V form AV JACK BOX)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.

5.2. Checkpoint

(1) Test voltage

- GND: 1.5KV/min at 100mA

- SIGNAL: 3KV/min at 100mA

(2) TEST time: 1 second
(3) TEST POINT

- GND Test = POWER CORD GND and SIGNAL CABLE
GND.

- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.

(4) LEAKAGE CURRENT: At 0.5mArms

6. EYE-Q Operation check

Step 1) Turn on the TV..
Step 2) Press ' EY E button' o n t he adjustm en t remote -

controller.

Step 3) Cover 'Eye Q sensor' on the front of set with your

hands, hold it for 6 seconds.

Step 4) Check "the Sensor Data" on the screen, make certain

that Data is below 10. If Data isn’t below 10 in 6
seconds, Eye Q sensor would be bad. You should
change Eye Q sensor.

Step 5) Uncover your hands from Eye Q sensor, hold it for 6

seconds.

Step 6) Check "Back Light(xxx)" on the screen, check data

increase . You should change Eye Q sensor.

7. Magic Motion Remote Control Inspection

- Requ ired Ins trument s: Ins pection RF-re mote con trol,
Inspection IR-KEY-CODE remote control.

- Prior to the test, AA battery for the RF-remote control should
be adequate.

(Change the battery for each LOT is recommended)

- Test procedures

(1) Press the ‘START’ key on the controller to pair with the set.
(2) Press the ‘OK’ key in the controller and check whether the

cursor appears on the set.

(3) Press ‘Vol+ (STOP)’ key to de-pair with the set.

8. 3D function test

8.1 Test equipment

(1) Pattern Generator MSHG-600 or MSPG-6100 (HDMI 1.4

support)

(2) Pattern: HDMI mode (model No. 872, pattern No. 83)

8.2 Test method

(1) Input 3D test signal as Fig.1.

(2) Press ‘OK” key as a 3D input OSD is shown.
(3) Check pattern as Fig2 without 3D glasses. (3D mode

without 3D glasses)

Fig.2

<OK in 3D mode without 3D glasses>

<Step 2>

<Step 5>

<Step 6>

<Step 3>

<Step 4>

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

9. HDMI ARC Function Inspection

9.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

9.2 Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

(2) Check the sound from the TV Set

(3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

* Remark: Inspect in Power Only Mode and check SW version

in a master equipment

.

10. USB S/W Download
(optional, Service only)

(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is lower

than that of TV set, it didn’t work. Otherwise USB data is

automatically detected.
(3) Show the message “Copying files from memory”
(5) Updating Completed, The TV will restart automatically
(6) If your TV is turned on, check your updated version and

Tool option.

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel
recover. If all channel data is cleared, you didn’t have a DTV/
ATV test on production line.

* After downloading, TOOL OPTION setting is needed again.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)

(5) Updating Completed, The TV will restart automatically
(6) If your TV is turned on, check your updated version and

Tool option.

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel
recover. If all channel data is cleared, you didn’t have a DTV/
ATV test on production line.

* After downloading, TOOL OPTION setting is needed again.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)

(4) Updating is staring.

- 18 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essenti al that these special safet y parts shoul d be replac ed with the same compo nents as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

IMPORTANT SAFETY NOTICE

A2

A21

A5

A24

AG1

300

200

510

120

121

122

560

570

501

840

850

810

710

400

521

820

860

830

540

530

200D

LV1

700

910

920

541

Except for Location No. 120, 121, 510, 521, 530, 540

HOME

/

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

EB_ADDR[9]

BOOT_MODE0

EB_DATA[0]

EB_DATA[1]

EB_ADDR[3]

EB_DATA[3]

EB_DATA[2]

EB_DATA[4]

EB_ADDR[2]

EB_ADDR[11]

EB_DATA[5]

EMMC_DATA[7]
EMMC_DATA[6]

EB_DATA[6]

EMMC_DATA[5]

EB_DATA[7]

EB_ADDR[12]

EB_ADDR[13]

EB_ADDR[6]

EMMC_DATA[0]

EB_ADDR[14]

EMMC_DATA[1]

EB_ADDR[0]

BOOT_MODE1

EMMC_DATA[2]

EB_ADDR[5]

EMMC_DATA[3]

EB_ADDR[7]

EMMC_DATA[4]

EB_ADDR[4]

EB_ADDR[1]

EB_ADDR[8]

EB_ADDR[10]

PLLSET1

R197

3.3K

+3.3V_NORMAL

I2C_SDA2

/PCM_CE2

R143

22

OPT

I2C_SDA5

+3.3V_NORMAL

/PCM_CE1

R133 10K

OPT

R180

3.3K

R168

10K

CI

I2C_SCL2

HW_OPT_7

R167 10K

CI

I2C_SDA4

CAM_IREQ_N

UART1_TX

R187

4.7K

R198

3.3K

I2C_SCL6

M_RFModule_ISP

BOOT_MODE1

HW_OPT_6

XO_MAIN

HW_OPT_0

HW_OPT_8

I2C_SDA2

CAM_CD2_N

RF_SWITCH_CTL

HW_OPT_2

R102 22

OPT

HW_OPT_4

R181

3.3K

FRC_RESET

/RST_HUB

TCK0

HW_OPT_1

UART1_RX

SOC_TX

CAM_REG_N

R196

3.3K

/USB_OCD3

R132 10K

OPT

I2C_SCL3

BOOT_MODE0

+3.3V_NORMAL

PLLSET0

TDI0

XIN_MAIN

CAM_CD1_N

C111

0.1uF

CAM_WAIT_N

UART1_RX

+3.3V_NORMAL

R166

10K

CI

R131 10K

OPT

ERROR_OUT

R103 22

OPT

R199

3.3K

I2C_SCL5

DSUB_DET

R150 22

+3.3V_NORMAL

I2C_SCL1

M_RFModule_RESET

CAM_INPACK_N

UART1_TX

R112

1M

R185

4.7K

OPT

SC_DET

TDO0

SOC_RX

TMS0

I2C_SCL5

I2C_SDA1

I2C_SCL4

M_REMOTE_TX

R186

4.7K

SOC_RESET

+3.3V_NORMAL

HW_OPT_3

R134 10K

OPT

R188

4.7K

OPT

HW_OPT_5

R142

22

OPT

I2C_SDA3

I2C_SDA6

/RST_PHY

TRST_N0

I2C_SCL2

I2C_SDA5

M_REMOTE_RX

COMP1_DET

HW_OPT_8

HW_OPT_1

R125 10K

UD

R138 10K

OPTIC

R100 10K

FRC_EXTERNAL

R139 10K

NON_OPTIC

R107 10K

FRC_INTERNAL

R140 10K

3D_DEPTH

R154 10K

DVB_S_TUNER

HW_OPT_2

R152 10K

DVB_T2_TUNER

R155 10K

NON_DVB_S_TUNER

HW_OPT_5

R153 10K

NON_DVB_T2_TUNER

HW_OPT_7

R141 10K

NON_3D DEPTH

HW_OPT_3

+3.3V_NORMAL

R146 10K

1GByte

R145 10K

OPT

R148 10K

NON_CP_BOX

R111

10K

FRC3

R124 10K

FHD

HW_OPT_4

R147 10K

CP_BOX

HW_OPT_6

R110

10K

URSA5

HW_OPT_0

HW_OPT_9

HW_OPT_9

R158 10K

NON_DVB_C2_TUNER

R156 10K

DVB_C2_TUNER

HP_DET

PCM_RST

/TU_RESET
/S2_RESET

I2C_BE_SDA1I2C_SDA1

R151 22

R160 22

R162 22

I2C_BE_SCL1

FRC3_RESET

I2C_SCL1

FRC_RESET

LOCAL_DIM_EN

R170

10K

FRC3

SMARTCARD_RST

SMARTCARD_VCC

SMARTCARD_DET

SMARTCARD_DATA

SMARTCARD_CLK

SMARTCARD_PWR_SEL

SMARTCARD_DATA

SMARTCARD_PWR_SEL

SMARTCARD_DET
SMARTCARD_CLK

SMARTCARD_RST

SMARTCARD_VCC

I2C_SDA3

I2C_SCL3

HDMI_INT

HDMI_S/W_RESET

MHL_DET

SW1

JTP-1127WEM

DEBUG

12

4 3

Q100

2N7002K

S

D

G

Q103

2N7002K

S

D

G

+5V_NORMAL

Q104
2N7002K

S

D

G

Q105

2N7002K

OPT

S

D

G

+3.3V_NORMAL

R201

2.7K

1/16W

5%

C100

8pF

50V

C101

8pF

50V

+5V_NORMAL

R202

100K

R203

100K

OPT

R126 10K

NOT_ZORAN_FRC

R121 10K

ZORAN_FRC

HW_OPT_10

HW_OPT_10

+3.3V_NORMAL

PLLSET1

EMMC_DATA[0-7]

R176

22

OPT

EB_OE_N

WIFI_DP

BOOT_MODE0

USB_HUB_IC_IN_DM

EMMC_CLK

R174

22

OPT

WIFI_DM

USB_DP3

USB_CTL3

EMMC_CMD

EMMC_RST

EB_DATA[0-7]

DTV_ATV_SELECT

USB_DM3

USB_HUB_IC_IN_DP

AV1_CVBS_DET

EB_BE_N1

EB_BE_N0

BOOT_MODE1

EB_WE_N

EB_ADDR[0-14]

PLLSET0

R105 22

EPHY_RXD0

EPHY_REFCLK

R108 22

EPHY_TXD1

EPHY_EN

EPHY_CRS_DV

EPHY_TXD0

EPHY_MDIO

EPHY_RXD1

EPHY_MDC

R106 22

I2C_SCL3

I2C_SCL5

I2C_SDA4

I2C_SCL6

I2C_SCL4

I2C_SDA6

I2C_SDA3

I2C_SCL1
I2C_SDA1

I2C_SDA2

I2C_SDA5

I2C_SCL2

XIN_MAIN

XO_MAIN

R104 560

1%

TDO0

TDI0

TMS0
TCK0

TRST_N0

PCM_5V_CTL

+5V_NORMAL

+3.3V_NORMAL

+3.3V_NORMAL

3D_DEPTH_RESET

FLASH_WP

MO_SENS_TO_MAIN_DOWN

MO_SENS_TO_MAIN_UP

MOTOR_CLOSE_SW

MOTOR_OPEN_SW

MOTOR_CW

MOTOR_CCW

MOTOR_CLOSE_SW

MO_SENS_TO_MAIN_DOWN

MOTOR_CW
MOTOR_CCW

MO_SENS_TO_MAIN_UP

MOTOR_OPEN_SW

R109

10K

+3.3V_NORMAL

P100

12507WS-04L

DEBUG

1

2

3

4

5

R184

1.2K

R183

1.2K

OLED_TCON_RESET

OPTIC_FPGA_RESET

FPGA_LVDS_INFO

OPTIC_SERDES_RESET

OPTIC_SERDES_RESET

OPTIC_FPGA_RESET

OLED_TCON_RESET

EPHY_INT

3D_DEPTH_RESET

IRB_SPI_SS

IRB_SPI_CK

IRB_SPI_MOSI

IRB_SPI_MISO

IR_B_RESET

IRB_SPI_MISO

IRB_SPI_SS

IRB_SPI_CK

IRB_SPI_MOSI

IR_B_RESET

EPHY_INT

SEL_USB3

SEL_USB2

/RST_PHY

SEL_USB3

SC_DET

SEL_USB1

SEL_USB1

HP_DET

SEL_USB2

IC102

R1EX24256BSAS0A

3

A2

2

A1

4

VSS

1

A0

5

SDA

6

SCL

7

WP

8

VCC

/USB_OCD2

R101 22

HP_AMP_MUTE

R117

22

OPT

DiiVA_POD_CTL

DiiVA_POD_CTL

IC100

LG1152D-B1

LG1152_NON_RM

XIN_MAIN

A22

XO_MAIN

B22

OPM1

AB16

OPM0

AB17

PORES_N

AE3

TRST_N0

V23

TMS0

U25

TCK0

V25

TDI0

V24

TDO0

U24

TRST_N1

Y22

TMS1

AA22

TCK1

AB20

TDI1

AB21

TDO1

W22

PLLSET1

AB9

PLLSET0

AB8

BOOT_MODE1

AB15

BOOT_MODE0

AB14

EXT_INTR3/GPIO48

Y23

EXT_INTR2/GPIO63

W25

EXT_INTR1/GPIO62

W24

EXT_INTR0/GPIO61

W23

UART0_RX/GPIO49

Y5

UART0_TX/GPIO50

W6

UART1_RX

AA6

UART1_TX

Y6

UART2_RX

AB5

UART2_TX

AA5

SPI_DI0/GPIO39

AB23

SPI_DO0/GPIO38

AB24

SPI_SCLK0/GPIO37

AA25

SPI_CS0/GPIO36

AB25

SPI_DI1/GPIO35

Y25

SPI_DO1/GPIO34

AA23

SPI_SCLK1/GPIO33

Y24

SPI_CS1/GPIO32

AA24

SCL0/GPIO60

AB6

SDA0/GPIO59

AB4

SCL1/GPIO58

AC5

SDA1/GPIO57

AC4

SCL2/GPIO56

AD4

SDA2/GPIO71

AE4

SCL3/GPIO70

AE5

SDA3/GPIO69

AD5

SCL4/GPIO68

AE6

SDA4/GPIO67

AD6

SCL5/GPIO66

AC6

SDA5/GPIO65

AC7

RMII_REF_CLK

AD2

RMII_CRS_DV

AB1

RMII_MDIO

AB2

RMII_MDC

AB3

RMII_TXEN

AC2

RMII_TXD1

AC3

RMII_TXD0

AE1

RMII_RXD1

AD3

RMII_RXD0

AD1

CAM_CE1_N

W26

CAM_CE2_N

V28

CAM_CD1_N

Y27

CAM_CD2_N

Y26

CAM_VS1_N

W28

CAM_VS2_N

W27

CAM_IREQ_N

AA28

CAM_RESET

AB26

CAM_INPACK_N

AA27

CAM_VCCEN_N

AA26

CAM_WAIT_N

Y28

CAM_REG_N

V27

CAM_IOIS16_N

V26

SC_CLK/GPIO90

R25

SC_DETECT/GPIO93

U23

SC_VCCEN/GPIO89

T25

SC_VCC_SEL/GPIO88

T24

SC_RST/GPIO91

T23

SC_DATA/GPIO92

R24

SD_CLK/GPIO76

C22

SD_CMD/GPIO73

C23

SD_CD_N/GPIO75

A23

SD_WP_N/GPIO74

B23

SD_DATA3/GPIO72

A24

SD_DATA2/GPIO87

B24

SD_DATA1/GPIO86

C24

SD_DATA0/GPIO85

A25

USB_DP1

B27

USB_DM1

A27

USB_DP2

A26

USB_DM2

B26

USB_TXR_RKL

C25

USB_ANALOGTEST

B25

BT_USB_DP

AA1

BT_USB_DM

AA2

BT_TXR_RKL

AA4

BT_ANALOGTEST

Y4

EMMC_RST

E28

EMMC_CLK

F27

EMMC_CMD

F26

EMMC_DATA7

C26

EMMC_DATA6

E27

EMMC_DATA5

E26

EMMC_DATA4

D27

EMMC_DATA3

D28

EMMC_DATA2

C27

EMMC_DATA1

C28

EMMC_DATA0

D26

NAND_CS1

R23

NAND_CS0

P24

NAND_ALE

N25

NAND_CLE

P23

NAND_REN

N24

NAND_WEN

P25

GPIO31

AC1

GPIO30

V7

GPIO29

W5

GPIO28

W4

GPIO27

V6

GPIO26

V5

GPIO25

V4

GPIO24

U6

GPIO23

U5

GPIO22

U4

GPIO21

T6

GPIO20

T5

GPIO19

T4

GPIO18

R6

GPIO17

R5

GPIO16

R4

GPIO15

P6

GPIO14

P5

GPIO13

P4

GPIO12

N6

GPIO11

N5

GPIO10

N4

GPIO9

N3

GPIO8

M6

GPIO7

AC23

GPIO6

AC24

GPIO5

AE24

GPIO4

AD23

GPIO3

AE23

GPIO2

AC22

GPIO1

AD22

GPIO0

AE22

EB_CS3/GPIO64

M25

EB_CS2/GPIO79

M24

EB_CS1/GPIO78

M23

EB_CS0/GPIO77

N23

EB_OE_N

T27

EB_WE_N

T28

EB_WAIT

U27

EB_BE_N1

U26

EB_BE_N0

U28

EB_ADDR17/GPIO84

J22

EB_ADDR16/GPIO83

K22

EB_ADDR15/GPIO82

J23

EB_ADDR14

L26

EB_ADDR13

L27

EB_ADDR12

L25

EB_ADDR11

N26

EB_ADDR10

N27

EB_ADDR9

M26

EB_ADDR8

L28

EB_ADDR7

L24

EB_ADDR6

L23

EB_ADDR5

K28

EB_ADDR4

K27

EB_ADDR3

K26

EB_ADDR2

K25

EB_ADDR1

K24

EB_ADDR0

K23

EB_DATA15

V22

EB_DATA14

U22

EB_DATA13

T22

EB_DATA12

R22

EB_DATA11

P22

EB_DATA10

N22

EB_DATA9

M22

EB_DATA8

L22

EB_DATA7

T26

EB_DATA6

R28

EB_DATA5

R27

EB_DATA4

R26

EB_DATA3

P28

EB_DATA2

P27

EB_DATA1

P26

EB_DATA0

N28

R178

2.2K

R179

2.2K

R182

2.2K

R195

2.2K

R173

R175

X101

24MHz

4

GND_2

1

X-TAL_12GND_1

3

X-TAL_2

FPGA_LVDS_INFO

D100

RCLAMP0502BA

OPT

SOC_RESET

R113

4.7K

IC100-*1

LG1152_RM

XIN_MAIN

A22

XO_MAIN

B22

OPM1

AB16

OPM0

AB17

PORES_N

AE3

TRST_N0

V23

TMS0

U25

TCK0

V25

TDI0

V24

TDO0

U24

TRST_N1

Y22

TMS1

AA22

TCK1

AB20

TDI1

AB21

TDO1

W22

PLLSET1

AB9

PLLSET0

AB8

BOOT_MODE1

AB15

BOOT_MODE0

AB14

EXT_INTR3/GPIO48

Y23

EXT_INTR2/GPIO63

W25

EXT_INTR1/GPIO62

W24

EXT_INTR0/GPIO61

W23

UART0_RX/GPIO49

Y5

UART0_TX/GPIO50

W6

UART1_RX

AA6

UART1_TX

Y6

UART2_RX

AB5

UART2_TX

AA5

SPI_DI0/GPIO39

AB23

SPI_DO0/GPIO38

AB24

SPI_SCLK0/GPIO37

AA25

SPI_CS0/GPIO36

AB25

SPI_DI1/GPIO35

Y25

SPI_DO1/GPIO34

AA23

SPI_SCLK1/GPIO33

Y24

SPI_CS1/GPIO32

AA24

SCL0/GPIO60

AB6

SDA0/GPIO59

AB4

SCL1/GPIO58

AC5

SDA1/GPIO57

AC4

SCL2/GPIO56

AD4

SDA2/GPIO71

AE4

SCL3/GPIO70

AE5

SDA3/GPIO69

AD5

SCL4/GPIO68

AE6

SDA4/GPIO67

AD6

SCL5/GPIO66

AC6

SDA5/GPIO65

AC7

RMII_REF_CLK

AD2

RMII_CRS_DV

AB1

RMII_MDIO

AB2

RMII_MDC

AB3

RMII_TXEN

AC2

RMII_TXD1

AC3

RMII_TXD0

AE1

RMII_RXD1

AD3

RMII_RXD0

AD1

CAM_CE1_N

W26

CAM_CE2_N

V28

CAM_CD1_N

Y27

CAM_CD2_N

Y26

CAM_VS1_N

W28

CAM_VS2_N

W27

CAM_IREQ_N

AA28

CAM_RESET

AB26

CAM_INPACK_N

AA27

CAM_VCCEN_N

AA26

CAM_WAIT_N

Y28

CAM_REG_N

V27

CAM_IOIS16_N

V26

SC_CLK/GPIO90

R25

SC_DETECT/GPIO93

U23

SC_VCCEN/GPIO89

T25

SC_VCC_SEL/GPIO88

T24

SC_RST/GPIO91

T23

SC_DATA/GPIO92

R24

SD_CLK/GPIO76

C22

SD_CMD/GPIO73

C23

SD_CD_N/GPIO75

A23

SD_WP_N/GPIO74

B23

SD_DATA3/GPIO72

A24

SD_DATA2/GPIO87

B24

SD_DATA1/GPIO86

C24

SD_DATA0/GPIO85

A25

USB_DP1

B27

USB_DM1

A27

USB_DP2

A26

USB_DM2

B26

USB_TXR_RKL

C25

USB_ANALOGTEST

B25

BT_USB_DP

AA1

BT_USB_DM

AA2

BT_TXR_RKL

AA4

BT_ANALOGTEST

Y4

EMMC_RST

E28

EMMC_CLK

F27

EMMC_CMD

F26

EMMC_DATA7

C26

EMMC_DATA6

E27

EMMC_DATA5

E26

EMMC_DATA4

D27

EMMC_DATA3

D28

EMMC_DATA2

C27

EMMC_DATA1

C28

EMMC_DATA0

D26

NAND_CS1

R23

NAND_CS0

P24

NAND_ALE

N25

NAND_CLE

P23

NAND_REN

N24

NAND_WEN

P25

GPIO31

AC1

GPIO30

V7

GPIO29

W5

GPIO28

W4

GPIO27

V6

GPIO26

V5

GPIO25

V4

GPIO24

U6

GPIO23

U5

GPIO22

U4

GPIO21

T6

GPIO20

T5

GPIO19

T4

GPIO18

R6

GPIO17

R5

GPIO16

R4

GPIO15

P6

GPIO14

P5

GPIO13

P4

GPIO12

N6

GPIO11

N5

GPIO10

N4

GPIO9

N3

GPIO8

M6

GPIO7

AC23

GPIO6

AC24

GPIO5

AE24

GPIO4

AD23

GPIO3

AE23

GPIO2

AC22

GPIO1

AD22

GPIO0

AE22

EB_CS3/GPIO64

M25

EB_CS2/GPIO79

M24

EB_CS1/GPIO78

M23

EB_CS0/GPIO77

N23

EB_OE_N

T27

EB_WE_N

T28

EB_WAIT

U27

EB_BE_N1

U26

EB_BE_N0

U28

EB_ADDR17/GPIO84

J22

EB_ADDR16/GPIO83

K22

EB_ADDR15/GPIO82

J23

EB_ADDR14

L26

EB_ADDR13

L27

EB_ADDR12

L25

EB_ADDR11

N26

EB_ADDR10

N27

EB_ADDR9

M26

EB_ADDR8

L28

EB_ADDR7

L24

EB_ADDR6

L23

EB_ADDR5

K28

EB_ADDR4

K27

EB_ADDR3

K26

EB_ADDR2

K25

EB_ADDR1

K24

EB_ADDR0

K23

EB_DATA15

V22

EB_DATA14

U22

EB_DATA13

T22

EB_DATA12

R22

EB_DATA11

P22

EB_DATA10

N22

EB_DATA9

M22

EB_DATA8

L22

EB_DATA7

T26

EB_DATA6

R28

EB_DATA5

R27

EB_DATA4

R26

EB_DATA3

P28

EB_DATA2

P27

EB_DATA1

P26

EB_DATA0

N28

MAIN & GPIO

1

A0’h

System Configuration

BOOT_MODE0

PLL SET[1:0] ==> Internal Pull-UP. N.C is high
00 : CPU clock(1056Mhz), Main0,1/2 DDR (792/792 Mhz)
01 : CPU clock(792Mhz), Main0,1/2 DDR (672/792 Mhz)
10 : CPU clock(1152Mhz), Main0,1/2 DDR (792/672 Mhz)
11 : CPU clock(984Mhz), Main0,1/2 DDR (792/792 Mhz)

I2C PULL UP

Write Protection

- Low : Normal Operation

- High : Write Protection

BOOT_MODE1

LG1152 B1

BOOT MODE
"11" or "01" : NOR
"10" : eMMC
"00" : NAND

NVRAM

Debug

MAIN Clock(24Mhz)

JTAG I/F FOR MAIN

Clock for LG1152

BackEnd 2

Pannel Resol

OPTIC I/F

FrontEnd 1

3D Depth IC

FrontEnd 2

CP BOX

BackEnd 1

DDR Size

Place to LVDS Wafer

For ISP

Delete PV

for DiiVA(China)

T2 Tuner

MODEL_OPT_1

MODEL_OPT_3

MODEL_OPT_9

MODEL_OPT_10

Enable

10

DDR Reserved

MODEL OPTION 8 is just for CP Box
It should not be appiled at MP

NON_3D_Depth_IC

1

NON_OPTIC

Support

OPTIC

LOW

0

0

Not Support

MODEL_OPT_6

MODEL_OPT_0

Zoran FRC

DDR_Default

MODEL_OPT_4

LG FRC3

FHD

S Tuner

1

0 1

CP BOX

Support

HIGH

Not Support

3D DEPTH

SoC
internal
FRC

Disable

3D_Depth_IC

MODEL_OPT_7

NO_FRC

UD

MODEL_OPT_5

Support

Not Support

MODEL_OPT_8

MODEL_OPT_2

Not Support

URSA5

Support

C2 Tuner

(For UD)

Place near Jack side

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

AVSS25_REF

+2.5V_NORMAL

VDD18

VDD33_USB

VDD33

VDD18

VDD18_LVTX

VDD18_LVRX

VDD18_MAIN_XTAL

VCC1.5V_DE

VCC1.5V_MAIN

VREF_M2

VREF_M0

VREF_M1

AVDD10_OSPREY

+0.9V_VDD

MAIN_XTAL

VDD33

VDD33_CVBS

VDD33_HDMI

VDD33_XTAL

VDD25_VSB

VDD25_CVBS

VDD25_REF

VDD25_COMP

VDD25_AUD

VDD25_LVTX

VDD18_A

AVDD10_DEMOD

AVDD10_VSB

AVDD10_LVTX

VDDC_XTAL

MAIN_XTAL

+2.5V_NORMAL

10uFC414

C406 0.1uF

C400 0.1uF

10uFC332

C402 0.1uF

L306
BLM18PG121SN1D

C350

0.1uF

10uFC307

L314
BLM18PG121SN1D

10uFC413

VREF_M0

L316
BLM18PG121SN1D

+1.8V_NORMAL

C381 0.1uF

+1.5V_DDR

L315

BLM18PG121SN1D

VDD25_COMP

C409 0.1uF

10uFC341

10uFC375

C329 0.1uF

VDD25_LVTX

L304

BLM18PG121SN1D

L326

BLM18PG121SN1D

C410 0.1uF

VREF_M1

+3.3V_NORMAL

VDD33

VDD25_VSB

L318
BLM18PG121SN1D

10uFC396

+3.3V_NORMAL

L317

BLM18PG121SN1D

10uFC378

C382 0.1uF

+1.0V_VDD

C388 0.1uF

VDDC_XTAL

C315 0.1uF

C377 0.1uF

VCC1.5V_MAIN

+1.8V_NORMAL

10uFC369

L321

BLM15BD121SN1

+1.8V_NORMAL

10uFC303

C390 0.1uF

AVDD10_OSPREY

10uFC422

C314 0.1uF

10uFC366

+2.5V_NORMAL

C423 0.1uF

R302

1K 1%

C370 0.1uF

C325 0.1uF

L323

BLM18PG121SN1D

C416 0.1uF

C337 0.1uF

C351

0.1uF

C317 0.1uF

VCC1.5V_MAIN

C321 0.1uF

10uFC397

C343 0.1uF

+2.5V_NORMAL

+3.3V_NORMAL

C334 0.1uF

+1.8V_NORMAL

C342 0.1uF

C318 0.1uF

VDD25_REF

VREF_M2

C333 0.1uF

AVSS25_REF

L312
BLM18PG121SN1D

C418 0.1uF

C345 0.1uF

L308
BLM18PG121SN1D

VDD18_A

+1.5V_DDR

R304

1K 1%

C324 0.1uF

VDD25_AUD

C336 0.1uF

C338 0.1uF

+0.9V_VDD

C393 0.1uF

10uFC415

VDD33_CVBS

C322 0.1uF

10uFC301

C306 0.1uF

C300

0.1uF

+1.0V_VDD

C327 0.1uF

AVDD10_DEMOD

10uFC302

C308

1000pF

C316 0.1uF

C310 0.1uF

+1.0V_VDD

C319 0.1uF

L302
BLM18PG121SN1D

AVDD10_LVTX

L303
BLM18PG121SN1D

C340 0.1uF

C311 0.1uF

10uFC312

L301

BLM18PG121SN1D

C404 0.1uF

VDD25_CVBS

L305
BLM18PG121SN1D

VDD18_LVTX

+0.9V_VDD

10uFC359

C391 0.1uF

10uFC421

C368 0.1uF

C394 0.1uF

C363

1000pF

L325
BLM18PG121SN1D

+0.9V_VDD

VDD18

+1.0V_VDD

R303

1K 1%

L319

BLM18PG121SN1D

10uFC398

C383 0.1uF

C346 0.1uF

+1.8V_NORMAL

C417 0.1uF

C353 0.1uF

VDD33_HDMI

L309

BLM18PG121SN1D

C384 0.1uF

L324
BLM18PG121SN1D

R300

1K 1%

C323 0.1uF

C419 0.1uF

C320 0.1uF

VCC1.5V_DE

C392 0.1uF

10uFC305

VCC1.5V_DE

C313 0.1uF

10uFC347

+1.0V_VDD

10uFC374

+3.3V_NORMAL

10uFC309

VDD33_XTAL

C411 0.1uF

10uFC379

10uFC395

C386 0.1uF

L313
BLM18PG121SN1D

+3.3V_NORMAL

+2.5V_NORMAL

C408 0.1uF

L310
BLM18PG121SN1D

+2.5V_NORMAL

C385 0.1uF

10uFC401

VCC1.5V_MAIN

R301

1K 1%

VDD33_USB

10uFC372

C403 0.1uF

VDD18_MAIN_XTAL

C399 0.1uF

10uFC371

R305

1K 1%

L300

BLM18PG121SN1D

C389 0.1uF

VDD18_LVRX

L320
BLM15BD121SN1

C362

1000pF

AVDD10_VSB

L322
BLM18PG121SN1D

MDS62110205

M308

GASKET except ATSC

GASKET_8.0X6.0X7.5H

MDS62110205

M310

OPT

MDS62110205

M311

ATSC

C407 0.1uF

C405 0.1uF

OPT

C304 0.1uF

MDS62110205

M312

ESD

+0.9V_VDD

MDS62110205

M314

ESD

MDS62110206

M309

OPT

SMR-T-6-6.5-8

MDS62110205

M315

ESD

IC100

LG1152D-B1

VDD33_1

U8

VDD33_2

U9

VDD33_3

U10

VDD33_4

V8

VDD33_5

V9

VDD33_6

V10

AVDD33_USB_1

J21

AVDD33_USB_2

K21

AVDD33_BT_USB_1

AA10

AVDD33_BT_USB_2

AA11

VDD18_1

W18

VDD18_2

W19

VDD18_3

Y18

VDD18_4

Y19

VDD18_5

AG28

VDD18_6

AH27

VDD18_LTX_1

AA7

VDD18_LTX_2

AA8

VDD18_LTX_3

AA9

VDD18_LTX_4

AG1

VDD18_LVRX_1

AA12

VDD18_LVRX_2

AA13

VDD18_LVRX_3

AB12

VDD18_DISPPLL

J28

VDD18_DR3PLL

B28

VDD18_MAIN_XTAL

G22

VDD15_M2_1

F9

VDD15_M2_2

G8

VDD15_M2_3

G9

VDD15_M2_4

G10

VDD15_M2_5

G11

VDD15_M2_6

H8

VDD15_M2_7

H9

VDD15_M2_8

H10

VDD15_M2_9

H11

VDD15_M0_1

F22

VDD15_M0_2

G13

VDD15_M0_3

G14

VDD15_M0_4

G16

VDD15_M0_5

G17

VDD15_M0_6

G18

VDD15_M0_7

G19

VDD15_M0_8

G20

VDD15_M0_9

G21

VDD15_M0_10

H13

VDD15_M0_11

H14

VDD15_M0_12

H16

VDD15_M0_13

H17

VDD15_M0_14

H18

VDD15_M0_15

H19

VDD15_M0_16

H20

VDD15_M0_17

H21

VREF_M2_0

L4

VREF_M1_0

F13

VREF_M1_1

G12

VREF_M0_0

F14

VREF_M0_1

G15

VDDC10_OSPREY_1

L20

VDDC10_OSPREY_2

M20

VDDC10_OSPREY_3

M21

VDDC10_OSPREY_4

M27

VDDC10_OSPREY_5

M28

VDDC10_OSPREY_6

N20

VDDC10_OSPREY_7

N21

VDDC10_OSPREY_8

P20

VDDC10_OSPREY_9

P21

VDDC10_OSPREY_10

R20

VDDC10_OSPREY_11

R21

VDDC09_1

K8

VDDC09_2

K9

VDDC09_3

K10

VDDC09_4

K11

VDDC09_5

L8

VDDC09_6

L9

VDDC09_7

L10

VDDC09_8

L11

VDDC09_9

M8

VDDC09_10

M9

VDDC09_11

M10

VDDC09_12

M11

VDDC09_13

N8

VDDC09_14

N9

VDDC09_15

N10

VDDC09_16

N11

VDDC09_17

P8

VDDC09_18

P9

VDDC09_19

P10

VDDC09_20

P11

VDDC09_21

R8

VDDC09_22

R9

VDDC09_23

R10

VDDC09_24

R11

VDD09_LTX_1

Y7

VDD09_LTX_2

Y8

VDD09_LTX_3

AF1

AVDD09_DR3PLL

F28

VDDC_MAIN_XTAL

H22

SP_VQPS

AA19

GND_MAIN_XTAL

G23

GND_1

G7

GND_2

H7

GND_3

H12

GND_4

H15

GND_5

J7

GND_6

J8

GND_7

J9

GND_8

J10

GND_9

J11

GND_10

J12

GND_11

J13

GND_12

J14

GND_13

J15

GND_14

J16

GND_15

J17

GND_16

J18

GND_17

J19

GND_18

J20

GND_19

K7

GND_20

K12

GND_21

K13

GND_22

K14

GND_23

K15

GND_24

K16

GND_25

K17

GND_26

K18

GND_27

K19

GND_28

K20

GND_29

L7

GND_30

L12

GND_31

L13

GND_32

L14

GND_33

L15

GND_34

L16

GND_35

L17

GND_36

L18

GND_37

L19

GND_38

L21

GND_39

M7

GND_40

M12

GND_41

M13

GND_42

M14

GND_43

M15

GND_44

M16

GND_45

M17

GND_46

M18

GND_47

M19

GND_48

N7

GND_49

N12

GND_50

N13

GND_51

N14

GND_52

N15

GND_53

N16

GND_54

N17

GND_55

N18

GND_56

N19

GND_57

P7

GND_58

P12

GND_59

P13

GND_60

P14

GND_61

P15

GND_62

P16

GND_63

P17

GND_64

P18

GND_65

P19

GND_66

R7

GND_67

R12

GND_68

R13

GND_69

R14

GND_70

R15

GND_71

R16

GND_72

R17

GND_73

R18

GND_74

R19

GND_75

T7

GND_76

T8

GND_77

T9

GND_78

T10

GND_79

T11

GND_80

T12

GND_81

T13

GND_82

T14

GND_83

T15

GND_84

T16

GND_85

T17

GND_86

T18

GND_87

T19

GND_88

T20

GND_89

T21

GND_90

U7

GND_91

U11

GND_92

U12

GND_93

U13

GND_94

U14

GND_95

U15

GND_96

U16

GND_97

U17

GND_98

U18

GND_99

U19

GND_100

U20

GND_101

U21

GND_102

V11

GND_103

V12

GND_104

V13

GND_105

V14

GND_106

V15

GND_107

V16

GND_108

V17

GND_109

V18

GND_110

V19

GND_111

V20

GND_112

V21

GND_113

W7

GND_114

W8

GND_115

W9

GND_116

W10

GND_117

W11

GND_118

W12

GND_119

W13

GND_120

W14

GND_121

W15

GND_122

W16

GND_123

W17

GND_124

W20

GND_125

W21

GND_126

Y9

GND_127

Y10

GND_128

Y11

GND_129

Y12

GND_130

Y13

GND_131

Y14

GND_132

Y15

GND_133

Y16

GND_134

Y17

GND_135

Y20

GND_136

Y21

GND_137

AA14

GND_138

AA15

GND_139

AA16

GND_140

AA17

GND_141

AA18

GND_142

AA20

GND_143

AA21

GND_144

AB7

GND_145

AB10

GND_146

AB11

GND_147

AB13

GND_148

AB22

IC101

LG1152AN-B2

VDD33_1

P1

VDD33_2

P2

AVDD33_CVBS_1

P14

AVDD33_CVBS_2

R14

AVDD33_HDMI_1

F18

AVDD33_HDMI_2

H16

VDD33_XTAL

M16

VDD25_VSB

L15

VDD25_CVBS_2

R13

VDD25_CVBS_1

R12

VDD25_CVBS_3

V13

AVDD25_REF

P10

VDD25_COMP_3

R10

VDD25_COMP_1

P9

VDD25_COMP_2

R9

VDD25_COMP_4

V7

VDD25_AAD

J16

VDD25_AUD_1

P6

VDD25_AUD_2

P7

VDD25_AUD_3

V6

VDD25_LVTX_1

B18

VDD25_LVTX_2

G12

VDD25_LVTX_3

G13

VDD18_1

N1

VDD18_2

N2

VDDC10_1

G6

VDDC10_2

G7

AVDD10_CVBS

R15

AVDD10_VSB

K15

AVDD10_LVTX_1

D17

AVDD10_LVTX_2

D18

AVDD10_LLPLL

N7

VDDC_XTAL

L16

VQPS

G4

AVSS25_REF

N10

GND_XTAL

K16

GND_1

D16

GND_2

G5

GND_3

G8

GND_4

G9

GND_5

G10

GND_6

G11

GND_7

G14

GND_8

G15

GND_9

H4

GND_10

H5

GND_11

H6

GND_12

H7

GND_13

H8

GND_14

H9

GND_15

H10

GND_16

H11

GND_17

H12

GND_18

H13

GND_19

H14

GND_20

H15

GND_21

J4

GND_22

J5

GND_23

J6

GND_24

J7

GND_25

J8

GND_26

J9

GND_27

J10

GND_28

J11

GND_29

J12

GND_30

J13

GND_31

J14

GND_32

J15

GND_33

K4

GND_34

K5

GND_35

K6

GND_36

K7

GND_37

K8

GND_38

K9

GND_39

K10

GND_40

K11

GND_41

K12

GND_42

K13

GND_43

K14

GND_44

L4

GND_45

L5

GND_46

L6

GND_47

L7

GND_48

L8

GND_49

L9

GND_50

L10

GND_51

L11

GND_52

L12

GND_53

L13

GND_54

L14

GND_55

M4

GND_56

M5

GND_57

M6

GND_58

M7

GND_59

M8

GND_60

M9

GND_61

M10

GND_62

M11

GND_63

M12

GND_64

M13

GND_65

M14

GND_66

M15

GND_67

M17

GND_68

N4

GND_69

N5

GND_70

N6

GND_71

N8

GND_72

N9

GND_73

N11

GND_74

N12

GND_75

N13

GND_76

N14

GND_77

N15

GND_78

N16

GND_79

P3

GND_80

P4

GND_81

P5

GND_82

P13

GND_83

P15

GND_84

P16

GND_85

R3

GND_86

R16

GND_87

R17

GND_88

R18

GND_89

T13

GND_90

U13

ZD301

5V

ESD_LG1152

ZD300

5V

ESD_LG1152

10uFC326

MDS62110205

M317

ESD

MDS62110205

M318

OPT

MDS62110205

M322

GASKET_8.0X6.0X7.5H

MDS62110217

M320

ESD

MDS62110217

M316

ESD

MDS62110217

M319

ESD

MDS62110218

M300

MDS62110218

M301

ALBLOCK

MDS62110218

M321

ALBLOCK

MDS62110218

M302

ALBLOCK

MDS62110218

M303

MDS62110218

M305

HEATSINK

MDS62110218

M304

HEATSINK

MDS62110218

M306

MDS62110218

M307

C349 0.33uF

C348 0.33uF

MDS62110205

M313

OPT

MAIN POWER

3

LG1152

For secure BOOT OTP
Will be change to LOW for MP

Will be change to LOW for MP

For HDCP OTP

LG1152A

LG1152D

Max 40mA

Max 5900mA

Max 20mA

Max 256mA

Max 1mA

Max 100mA

Max 120mA

Max 6mA

Max 40mA

Max 93mA

Max 250mA

Max 50mA

Max 680mA

Max 1mA

Max 40mA

Max 340mA

Max 49mA

Max 12mA

+1.5V_Bypass Cap

Max 360mA

(18)

Max 31mA

Max 10mA

Max 1320mA

Max 35mA

Max 28mA

Max 48.8mA

Max 250mA

Max 35mA

On Package Decap : 0.1uF *6ea

On Package Decap : 0.1uF *3ea

On Package Decap : 0.1uF *2ea

On Package Decap : 0.1uF *3ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap:0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap : 0.1uF *1ea

On Package Decap:0.1uF *1ea

On Package Decap:0.1uF *1ea

For Tuner Sensitivity / Under DDR

For Tuner Sensitivity / Under TUNER

For ATSC

For HeatSinK, AL Block / SMD Top

SMD Bottom

SMD TOP FOR ESD

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TPO_DATA[3]

TPI_DATA[0]

FE_TS_DATA[1]

TPO_DATA[0]

TPI_DATA[1]

TPO_DATA[7]

FE_TS_DATA[3]

TPO_DATA[4]

TPI_DATA[5]
TPI_DATA[6]

TPO_DATA[2]

TPI_DATA[7]

TPO_DATA[1]

TPO_DATA[6]

TPI_DATA[2]
TPI_DATA[3]

FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]

FE_TS_DATA[0]

FE_TS_DATA[7]

TPI_DATA[4]

TPO_DATA[5]

FE_TS_DATA[2]

R522

10K

EU

SC_SOG_IN

C502

2.2uF

EU

AUD_LRCH

C541 0.047uF

R544

100

AUAD_L_CH4_IN

R524

2.7K

EU

C557

0.047uF

SC_G

R566 0

AUAD_L_CH5_IN

R555

10K

AUD_SCK

C554

0.047uF

DSUB_HSYNC

AUAD_R_CH5_IN

C542 0.047uF

AV1_R_IN

SC_B

C556

0.047uF

C501

2.2uF

SC_ID

AV1_CVBS_IN

SC_FB

AUAD_L_CH3_IN

COMP1_Pb

TU_CVBS

R579

22

SC_CVBS_IN

CHB_CVBS

AUAD_R_CH3_IN

DSUB_VSYNC

C500

2.2uF

R545

100

C550

0.047uF

C544 1000pF

R543

100

R580

22

C539 0.047uF

R553

10K

C555

0.047uF

AUD_LRCK

C506

680pF

OPT

C504

2.2uF

R569 33

R570 33

R524-*1
0

NON SCART

AUD_MASTER_CLK

SC_R

C545 0.047uF

AUAD_R_CH4_IN

C505

2.2uF

C549

0.047uF

R528

75

C540 1000pF

C517

680pF
OPT

C551

0.047uF

AV1_L_IN

C503

2.2uF

EU

C553

0.047uF

C543 0.047uF

R568 33

R542100

SC_SOG_IN

R529

75

C552

0.047uF

R614
75
1%

R615
75
1%

R613
75
1%

OPT

R525
75

EU

R525-*1

0

NON SCART

R594

75

R600

75

R595

75

R608

470K

EU

L510

EU

R602
470K

EU

L507

EU

SC_L_IN

SC_R_IN

C575
100pF
50V

C573
560pF
50V

OPT

R607
470K

R601
470K

L506

C581
560pF
50V

OPT

C587
100pF
50V

L509

PC_L_IN

PC_R_IN

C579

10pF

R605

75
1%

C580

10pF

R604

75
1%

C578

10pF

R606

75

1%

COMP1_Y

COMP1_Pr

C589
100pF
50V

R603
470K

R609

470K

C574
560pF
50V
OPT

L508

C586
560pF
50V
OPT

L511

C577
100pF
50V

C572
330pF
50V

OPT

C576
330pF
50V

EU

C582
330pF
50V
OPT

C588
330pF
50V

EU

+5V_TU

R618
220
CHB

R616
220

CHB

R617

75
OPT

C524

10pF

OPT

C546

10pF

OPT

DSUB_VSYNC

C3626

5pF
50V
OPT

C3625

5pF
50V
OPT

R3633

2K

OPT

DSUB_HSYNC

R3634

2K

OPT

SC_FB

TU_CVBS

DTV/MNT_V_OUT

TUNER_SIF

SCART_Lout

SC_R

SC_G

SC_L_IN

SC_ID

TUNER_SIF

CHB_CVBS

SCART_Rout

SC_R_IN

SC_B

ATV_OUT

SC_CVBS_IN

R571 33
R572 33

R575 33

R551 33
R557 33

R558 68

R559 68

R539 33

SOC_TXB2N

SOC_TXB0N

R547 0

SOC_TXB3N

+3.3V_NORMAL

SOC_TXB3P

HDMI_CLK+

HDMI_RX2+

DSUB_G+

AUAD_R_CH3_IN

PWM_DIM

AUDA_OUTR

R630 100

SOC_TXA3N

XO_SUB

TPI_SOP

SOC_TXA3P

SOC_TXA2P

SOC_RESET

SOC_TXB2P

R563 0

EU

DSUB_B+

SOC_TXB4N

HDMI_CLK-

TPI_DVB_ERR

TPO_ERR

AUDA_OUTL

R629 47

SOC_TXA4P

AUAD_L_CH4_IN

C523 0.047uF

C518 0.047uF

FE_TS_SYNC

SOC_TXBCLKP

TPO_CLK

DSUB_R+

10uFC535

R598 47

OPT

R59622

SOC_TXA1N

C527 1000pF

+3.3V_NORMAL

R578 4.7K

BPL_IN

AUAD_R_CH5_IN

XIN_SUB

C532 0.047uF

SOC_TXB0P

SOC_TXA2N

HDMI_RX0+

R577 4.7K

SOC_TXB1N

FE_TS_CLK

R59722

SOC_TXA0P

C558

1000pF

OPT

AUAD_R_CH4_IN

AUAD_L_CH5_IN

HDMI_RX1-

DTV/MNT_VOUT

FE_TS_DATA[0-7]

C531 0.047uF

SOC_TXA1P

TPO_DATA[0-7]

R561

33

TPI_ERR

C515
100pF
50V
EU

TPO_SOP

C533 0.1uF

XO_SUB

SOC_TXB1P

XIN_SUB

SPDIF_OUT

R536 68

C534 0.1uF

TPI_CLK

SOC_TXACLKP

R541 68
R546 33

SOC_TXA0N

HDMI_RX0-

R535

1M

SOC_TXA4N

FE_TS_VAL

TPI_DATA[0-7]

R550 33

SOC_TXB4P

SOC_TXACLKN

C526 0.047uF

HDMI_RX1+

A_DIM

SOC_TXBCLKN

R619 47

OPT

C516 0.047uF

AUAD_L_CH3_IN

SPDIF_OUT_ARC

TPI_VAL

HDMI_RX2-

TPO_VAL

R548 68

R518 75K

R516 75K

EU

R514 75K

R519 100K

R517 100K

EU

R515 100K

R530

75

C538 0.047uF

R633

100

PWM_DIM2

R632

100

EDGE_LED

C115

0.1uF

R200

47

CHB

IF_AGC

C117

0.1uF

H/NIM&CHB

AR102

47

CHB

IF_P

CHB_SYNC

IF_N

CHB_ERR

IF_AGC

IF_N

CHB_VAL

IF_P

CHB_CLK

CHB_DATA

C116

0.1uF

H/NIM&CHB

TUNER_SIF

C559

2.2uF

OPT

JDVR_SCLK

CHB_ERR

TPO_DATA[0-7]

TPI_SOP

TPO_CLK

TPI_ERR

CHB_DATA

TPO_SOP

TPO_VAL

TPI_CLK

TPI_DATA[0-7]

TPO_ERR

CHB_VAL

TPI_VAL

R631

10K

OPT

TPI_DVB_ERR

FE_TS_SYNC

FE_TS_DATA[0-7]

FE_TS_CLK

FE_TS_VAL

R582 33

R581 33

R9112
33

R583 33

SCART_Lout_SOC

JDVR_SCLK

SCART_Rout_SOC

R507

10K

EU

+5V_NORMAL

Q504

MMBT3906(NXP)

EU

E

B

C

DTV/MNT_V_OUT

DTV_ATV_SELECT

C510

0.1uF
16V

EU

R593

220
EU

R592
220

EU

R527

10K

EU

ATV_OUT

Q506

MMBT3904(NXP)

EU

E

B

C

IC500

NLASB3157DFT2G

EU

3

B0

2

GND

4

A

1B16

SELECT

5

VCC

+5V_NORMAL

R599

75

OPT

DTV/MNT_VOUT

C5472.2uF
C5482.2uF

C5372.2uF

C536 2.2uF

C605

10pF

OPT

C606

10pF

OPT

C607

10pF

OPT

C528

10pF

OPT

FRC3_FLASH_WP

R531

22K

EU

C520 0.01uFEUR532 22K

EU

C521 0.01uF

EU

R501100

EU

R502100

EU

SCART_Rout

SCART_Lout

SCART_Rout_SOC

SCART_Lout_SOC

R552

100K

EU

+12V

C525

2.2uF
10V

EU

R554

100K

EU

R538

100K

EU

C522

2.2uF
10V

EU

R549

100K

EU

Q505
CHB

E

B

C

AMP_RESET_N

R628 22

OPT

C630
82pF
50V

R576100

EU

C529

220pF
OPT

50V

R556

33

USB_CTL2

HP_ROUT_MAIN

HP_LOUT_MAIN

R626

22K

AUDA_OUTL

C604

0.01uF

R627

22K

AUDA_OUTR

R625
100

C603

0.01uF

R624
100

R574 100

R573 100

OPTIC_GPIO1

OPTIC_BACK_CHANNEL

OPTIC_GPIO1
OPTIC_BACK_CHANNEL

L501

L500

L502

D500

5.5V
OPT

D501

5.5V
OPT

D502

5.5V
OPT

IC101

LG1152AN-B2

XIN_SUB

L17

XO_SUB

L18

VSB_AUX_XIN

P17

XTLIN_AAD

K17

XTLOUT_AAD

K18

OPM1

M2

OPM0

M1

PORES_N

R4

L9A_SCL

N3

L9A_SDA

M3

CVBS_IN1

U14

CVBS_IN2

T14

CVBS_IN3

V15

CVBS_VCM

U15

CVBS_IN4

T15

CVBS_IN5

U16

CVBS_IN6

V14

CB_IN

T16

CB_VCM

V16

BUF_OUT1

V17

BUF_OUT2

U17

HSYNC

P8

VSYNC

R8

SC1_FB

P11

SC1_SID

R11

BINCOM_IN

U8

B_IN

V8

G_IN

T8

SOG_IN

V9

R_IN

U9

GINCOM_IN

V10

PB1_IN

T9

Y1_IN

U10

SOY1_IN

T10

PR1_IN

V11

RINCOM_IN

T11

PB2_IN

U11

Y2_IN

V12

SOY2_IN

U12

PR2_IN

T12

AAD_ADC_SIFM

N17

AAD_ADC_SIF

N18

AUDA_BGR_OUT

U1

AUDA_OUTL

R1

AUDA_OUTR

R2

AUD_SCART0_OUTLN

T1

AUD_SCART0_OUTLP

V2

AUD_SCART0_OUTRN

U2

AUD_SCART0_OUTRP

T2

AUAD_L_CH5_IN

U3

AUAD_R_CH5_IN

V3

AUAD_L_CH4_IN

V4

AUAD_R_CH4_IN

T3

AUAD_L_CH3_IN

U5

AUAD_R_CH3_IN

T5

AUAD_L_CH2_IN

U6

AUAD_R_CH2_IN

T6

AUAD_L_CH1_IN

U7

AUAD_R_CH1_IN

T7

AUAD_REFN

T4

AUAD_REFP

U4

AUAD_VR_OUT

V5

AUMI_BIAS

R7

AUMI_IN

R5

AUMI_COM

R6

DDCD0_DA

E18

DDCD0_CK

E17

HPD0

E16

PHY0_RXCN_0

J18

PHY0_RXCP_0

J17

PHY0_RX0N_0

H17

PHY0_RX0P_0

H18

PHY0_RX1N_0

G17

PHY0_RX1P_0

G18

PHY0_RX2N_0

G16

PHY0_RX2P_0

F16

PHY0_ARC_OUT_0

F17

ANTCON

P12

RFAGC

M18

IFAGC

P18

ADC_I_INCOM

T17

ADC_I_INP

U18

ADC_I_INN

T18

IC101

LG1152AN-B2

INTR_GBB

L1

INTR_HDMI1

L2

INTR_AFE3CH

L3

AUD_HMR00ARC

K1

AUD_HMR0AMUTE

K2

AUD_HMR0ALRCK

J2

AUD_HMR0ABCK

J3

AUD_HMR0ASD4

K3

AUD_HMR0ASD3

H1

AUD_HMR0ASD2

H2

AUD_HMR0ASD1

H3

AUD_HMR0ASD0

J1

AUD_DAC1_LRCH

G1

AUD_DAC1_SCK

G2

AUD_DAC1_LRCK

G3

AUD_FS25CLK

B1

AUD_FS24CLK

C1

AUD_FS23CLK

A4

AUD_FS21CLK

B4

AUD_FS20CLK

C4

AUDCLK_OUT_SUB

A2

AUD_DAC0_LRCK

D1

AUD_DAC0_LRCH

D2

AUD_DAC0_SCK

E2

AUD_ADC_LRCH

E1

AUD_ADC_SCK

F1

AUD_ADC_LRCK

F2

AUD_MIC_LRCH

B2

AUD_MIC_SCK

A3

AUD_MIC_LRCK

C2

BB_TP_DATA0

B3

BB_TP_DATA1

C3

BB_TP_DATA2

D3

BB_TP_DATA3

E3

BB_TP_DATA4

F3

BB_TP_DATA5

D4

BB_TP_DATA6

E4

BB_TP_DATA7

F4

BB_TP_VAL

D5

BB_TP_SOP

E5

BB_TP_ERR

F5

BB_TP_CLK

D6

BB_SDA_I

A5

BB_SDA_O

B5

BB_SCL

C5

L9DA_SCL

A6

L9DA_SDA_I

B6

L9DA_SDA_O

C6

CHB_DN

E6

CHB_UP

F6

CHB_START

D7

CHB_DATA0

B7

CHB_DATA1

C7

CHB_DATA2

A8

CHB_DATA3

B8

CHB_DATA4

C8

CLK_F54M

A7

CVBS_GC2

D8

CVBS_GC1

F7

CVBS_GC0

E7

CVBS_UP

E8

CVBS_DN

F8

FS00CLK

A9

AUDCLK_OUT

B9

DAC_DATA0

C9

DAC_DATA1

D9

DAC_DATA2

E9

DAC_DATA3

F9

DAC_DATA4

C10

DAC_START

D10

AAD_GC0

E10

AAD_GC1

F10

AAD_GC2

D11

AAD_GC3

E11

AAD_GC4

F11

AAD_DATAEN

D12

AAD_DATA0

E12

AAD_DATA1

F12

AAD_DATA2

D13

AAD_DATA3

E13

AAD_DATA4

F13

AAD_DATA5

D14

AAD_DATA6

E14

AAD_DATA7

F14

AAD_DATA8

D15

AAD_DATA9

E15

DCO_OUT_CLK

F15

HSR_AM0

B10

HSR_AP0

A10

HSR_BM0

A11

HSR_BP0

B11

HSR_CM0

C12

HSR_CP0

C11

HSR_CLKM0

B12

HSR_CLKP0

A12

HSR_DM0

A13

HSR_DP0

B13

HSR_EM0

C14

HSR_EP0

C13

HSR_AM1

B14

HSR_AP1

A14

HSR_BM1

A15

HSR_BP1

B15

HSR_CM1

C16

HSR_CP1

C15

HSR_CLKM1

B16

HSR_CLKP1

A16

HSR_DM1

A17

HSR_DP1

B17

HSR_EM1

C18

HSR_EP1

C17

IC100

LG1152D-B1

INTR_GBB

AH2

INTR_HDMI1

AG2

INTR_AFE3CH

AF2

AUD_HMR0ARC

AH3

AUD_HMR0AMUTE

AG3

AUD_HMR0ALRCK

AG4

AUD_HMR0ABCK

AF4

AUD_HMR0ASD4

AF3

AUD_HMR0ASD3

AH5

AUD_HMR0ASD2

AG5

AUD_HMR0ASD1

AF5

AUD_HMR0ASD0

AH4

AUD_DAC1_LRCH

AH6

AUD_DAC1_SCK

AG6

AUD_DAC1_LRCK

AF6

AUD_FS25CLK

AH7

AUD_FS24CLK

AG7

AUD_FS23CLK

AH10

AUD_FS21CLK

AG10

AUD_FS20CLK

AF10

AUDCLK_OUT_SUB

AH8

AUD_DAC0_LRCK

AF7

AUD_DAC0_LRCH

AE8

AUD_DAC0_SCK

AD8

AUD_ADC_LRCH

AE7

AUD_ADC_SCK

AD7

AUD_ADC_LRCK

AC8

AUD_MIC_LRCH

AG8

AUD_MIC_SCK

AH9

AUD_MIC_LRCK

AF8

BB_TPI_DATA0

AG9

BB_TPI_DATA1

AF9

BB_TPI_DATA2

AE9

BB_TPI_DATA3

AD9

BB_TPI_DATA4

AC9

BB_TPI_DATA5

AE10

BB_TPI_DATA6

AD10

BB_TPI_DATA7

AC10

BB_TPI_VAL

AE11

BB_TPI_SOP

AD11

BB_TPI_ERR

AC11

BB_TPI_CLK

AE12

BB_SDA_I

AH11

BB_SDA_O

AG11

BB_SCL

AF11

HS_SCL

AH12

HS_SDA_I

AG12

HS_SDA_O

AF12

CHB_DN

AD12

CHB_UP

AC12

CHB_START

AE13

CHB_DATA0

AG13

CHB_DATA1

AF13

CHB_DATA2

AH14

CHB_DATA3

AG14

CHB_DATA4

AF14

CLK_54

AH13

CVBS_GC2

AE14

CVBS_GC1

AC13

CVBS_GC0

AD13

CVBS_UP

AD14

CVBS_DN

AC14

FS00CLK

AH15

AUDCLK_TO_DIGITAL

AG15

DAC_DATA0

AF15

DAC_DATA1

AE15

DAC_DATA2

AD15

DAC_DATA3

AC15

DAC_DATA4

AF16

DAC_START

AE16

AAD_GC0

AD16

AAD_GC1

AC16

AAD_GC2

AE17

AAD_GC3

AD17

AAD_GC4

AC17

AAD_DATAEN

AE18

AAD_DATA0

AD18

AAD_DATA1

AC18

AAD_DATA2

AE19

AAD_DATA3

AD19

AAD_DATA4

AC19

AAD_DATA5

AE20

AAD_DATA6

AD20

AAD_DATA7

AC20

AAD_DATA8

AE21

AAD_DATA9

AD21

AUPLL_CLK

AC21

HS_RX1_AM

AG16

HS_RX1_AP

AH16

HS_RX1_BM

AH17

HS_RX1_BP

AG17

HS_RX1_CM

AF18

HS_RX1_CP

AF17

HS_RX1_CLKM

AG18

HS_RX1_CLKP

AH18

HS_RX1_DM

AH19

HS_RX1_DP

AG19

HS_RX1_EM

AF20

HS_RX1_EP

AF19

HS_RX2_AM

AG20

HS_RX2_AP

AH20

HS_RX2_BM

AH21

HS_RX2_BP

AG21

HS_RX2_CM

AF22

HS_RX2_CP

AF21

HS_RX2_CLKM

AG22

HS_RX2_CLKP

AH22

HS_RX2_DM

AH23

HS_RX2_DP

AG23

HS_RX2_EM

AF24

HS_RX2_EP

AF23

STPI_CLK

AE27

STPI_SOP

AE26

STPI_VAL

AD28

STPI_ERR

AD27

STPI_DATA

AD26

STPIO_CLK

AC28

STPIO_SOP/GPIO43

AC26

STPIO_VAL/GPIO42

AB28

STPIO_ERR/GPIO41

AC27

STPIO_DATA/GPIO40

AB27

TPI_DVB_CLK/GPIO47

AF27

TPI_DVB_SOP/GPIO46

AE28

TPI_DVB_VAL/GPIO45

AG27

TPI_DVB_ERR

AF28

TPI_DVB_DATA0/GPIO44

AG26

TPI_DVB_DATA1

AF26

TPI_DVB_DATA2

AF25

TPI_DVB_DATA3

AH26

TPI_DVB_DATA4

AH25

TPI_DVB_DATA5

AG25

TPI_DVB_DATA6

AH24

TPI_DVB_DATA7

AG24

TPI_CLK

H24

TPI_SOP

J25

TPI_VAL

J24

TPI_ERR

H25

TPI_DATA0

J27

TPI_DATA1

J26

TPI_DATA2

H28

TPI_DATA3

H27

TPI_DATA4

H26

TPI_DATA5

G28

TPI_DATA6

G27

TPI_DATA7

G26

TPO_CLK

D24

TPO_SOP

E23

TPO_VAL

D25

TPO_ERR

D23

TPO_DATA0

H23

TPO_DATA1

G25

TPO_DATA2

G24

TPO_DATA3

F25

TPO_DATA4

F24

TPO_DATA5

F23

TPO_DATA6

E25

TPO_DATA7

E24

AUDCLK_OUT

C1

DACLRCH

C2

DACSLRCH/GPIO95

A3

DACCLFCH/GPIO94

A2

DACSCK

B2

DACLRCK

B1

PCMI3LRCK/GPIO81

B3

PCMI3LRCH

C3

PCMI3SCK/GPIO80

A4

IEC958OUT

AE2

AUD_SUBMCK

AD25

AUD_SUBLRCH

AC25

AUD_SUBSCK/GPIO51

AD24

AUD_SUBLRCK/GPIO52

AE25

BTSCSEL

AB18

DTS_EN

AB19

TXA0N

N1

TXA0P

N2

TXA1N

P2

TXA1P

P1

TXA2N

P3

TXA2P

R3

TXACLKN

R1

TXACLKP

R2

TXA3N

T2

TXA3P

T1

TXA4N

T3

TXA4P

U3

TXB0N

U1

TXB0P

U2

TXB1N

V2

TXB1P

V1

TXB2N

V3

TXB2P

W3

TXBCLKN

W1

TXBCLKP

W2

TXB3N

Y2

TXB3P

Y1

TXB4N

Y3

TXB4P

AA3

PWM0/GPIO55

L6

PWM1/GPIO54

L5

PWM2/GPIO53

M4

PWM_IN

M5

R521 100

R567 150

R564 150
R565 150

C512

8pF

C513

8pF

D504

5.5V

D506

5.5V

D503

5.5V

D505

5.5V

X500

24MHz

4

GND_2

1

X-TAL_12GND_1

3

X-TAL_2

R534

10K

R52010K

L504

1uH

L503

EU

1uH

C509
150pF

EU

C508
150pF
50V

EU

C511

150pF

50V

C514
150pF
50V

C6006

1uF25V

EU

R6006

10K

EU

C6001

1uF25V

EU

R6005

10K

EU

SCART_AMP_R_FB

SCART_AMP_L_FB

R508 22K

R510

22K

EU

R509 22K

R512 22K

R511

22K

EU

R513 22K

R560

330

3

MAIN AUDIO/VIDEO

LG1152 B0

Place these close to tuner

Place SOC Side

Place JACK Side

Close to LG1152A

Close to LG1152A

Main clock for LG1152A

DTS_EN: ENABLE(’1’) (for development)

LG1152A LG1152D

BTSC_EN: ENABLE(’1’) (for development)

Close to LG1152A

Selece = High ==> A = B1
Selece = Low ==> A = B0

Near Place Scart AMP

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

SIGN50000

SIGN50005

M2_DDR_BA1

R738

240

M2_DDR_A3

M2_DDR_RESET_N

M2_DDR_VREFCA

M2_DDR_A10

M2_DDR_DQSL_N

M2_DDR_DQ6

M2_DDR_DMU

M2_DDR_DQ13

M2_DDR_A0

C744

10uF

10V

C739

0.1uF

M2_DDR_DQ8

M2_DDR_A6

M2_DDR_DQ7

C741

0.1uF

M2_DDR_DML

M2_DDR_A9

M2_DDR_DQSL_P

C742

0.1uF

M2_DDR_RASN

M2_DDR_DQ14

M2_DDR_A8

M2_DDR_DQ5

M2_DDR_ODT

M2_DDR_DQ2

C736

0.1uF

M2_DDR_DQ15

C740

0.1uF

M2_DDR_DQ0
M2_DDR_DQ1

M2_DDR_DQ10

M2_DDR_WEN

M2_DDR_A11

C738

0.1uF

M2_DDR_A4

M2_DDR_CASN

M2_DDR_DQ11

M2_DDR_A1

M2_DDR_DQ12

M2_DDR_A5

M2_DDR_DQ3

M2_DDR_A12

M2_DDR_CKE

M2_DDR_BA0

M2_DDR_DQ9

M2_DDR_DQSU_N

VCC1.5V_DE

M2_DDR_DQSU_P

M2_DDR_VREFDQ

M2_DDR_A13

C737

0.1uF

M2_DDR_A7

M2_DDR_BA2

M2_DDR_A2

C743

0.1uF

M2_DDR_DQ4

H5TQ1G63DFR-PBC

IC702

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

NC_6

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

C722

0.1uF

C721

0.1uF

C705

0.1uF

C704

0.1uF

C720

0.1uF

VCC1.5V_MAIN

M0_DDR_VREFCA

M0_DDR_VREFDQ

VCC1.5V_MAIN

M0_1_DDR_VREFCA

M0_DDR_A5

R735

1K 1%

C751

0.1uF

C708

0.1uF

M1_DDR_DQSL_N

M0_DDR_BA0

VCC1.5V_MAIN

M0_DDR_RESET_N

M1_DDR_CKE

M0_DDR_RASN

M0_DDR_CLK

M1_DDR_DQSU_P

C707

0.1uF

M1_DDR_DQ1

R736

1K 1%

M1_DDR_DQ5

C735

0.1uF

M0_DDR_CLK

C733

0.1uF

R721

240
1%

C758

0.1uF

M1_DDR_A6

M0_DDR_A1

C715

0.1uF

M0_DDR_DQ3

C761

0.1uF

M1_DDR_A10

M1_DDR_A14

M0_DDR_A8

M1_DDR_A3

M1_DDR_BA0

C728

1000pF

VCC1.5V_MAIN

M1_DDR_DQ3

M0_DDR_DQSL_N

R730

1K 1%

M1_1_DDR_VREFDQ

C723

0.1uF

M1_DDR_A5

C729

1000pF

M0_1_DDR_VREFCA

M0_DDR_DMU

M0_DDR_CLKN

M0_DDR_ODT

M0_DDR_CLKN

M1_DDR_DQ10

M1_DDR_DQ2

M1_DDR_BA2

C752

0.1uF

M0_DDR_A9

C711

0.1uF

M1_DDR_DQSU_N

M0_DDR_A0

M1_DDR_RESET_N

M0_DDR_A11

M1_DDR_CLK

M1_DDR_VREFDQ

M0_DDR_BA1

M0_DDR_DQ12

M1_DDR_CASN

M1_DDR_A3

M0_DDR_DQ9

M1_DDR_A9

M0_DDR_DQ15

M0_DDR_A12

R727

1K 1%

M1_DDR_DQ4

M0_DDR_BA1

M1_DDR_A5

M0_DDR_A7

C748

1000pF

M0_DDR_CASN

C710

0.1uF

M1_DDR_DQ14

M1_DDR_A13

VCC1.5V_MAIN

M1_DDR_BA0

VCC1.5V_MAIN

M1_DDR_RESET_N

VCC1.5V_MAIN

M1_DDR_CKE

C732

0.1uF

VCC1.5V_MAIN

C724

0.1uF

M0_DDR_DQ6

M1_DDR_A12

M0_DDR_A10

R729

1K 1%

C745

0.1uF

R741
10K

C716

0.1uF

M0_1_DDR_VREFDQ

M1_DDR_DQ11

R737

1K 1%

C753

0.1uF

M1_DDR_A4

M0_DDR_RESET_N

M1_DDR_DML

M0_DDR_A11

R740

240
1%

M0_DDR_A4

M1_DDR_CASN

M0_DDR_CLK

M0_DDR_BA0

C717

0.1uF

M0_DDR_CLK

M1_DDR_DQ8

C709

0.1uF

R742
10K

M1_DDR_BA1

M1_DDR_CLK

R720

240
1%

C747

1000pF

M0_DDR_VREFDQ

M1_DDR_RESET_N

C749

1000pF

M0_DDR_BA2

M0_DDR_A10

M1_1_DDR_VREFCA

M1_DDR_DQ13

C757

0.1uF

R709
10K

R739

240
1%

M0_DDR_A13

M1_DDR_A2

M1_DDR_WEN

M0_DDR_DQSL_P

M1_DDR_BA2

M1_DDR_A7

M1_DDR_A0

M1_DDR_A6

M0_DDR_RASN

M0_DDR_WEN

M1_DDR_CKE

M1_DDR_A11

M1_DDR_DQ9

M0_DDR_DQ11M0_DDR_DQ7

M0_DDR_DQ10

M1_DDR_BA1

M1_DDR_DMU

M0_DDR_A14

VCC1.5V_MAIN

M1_DDR_A1

M0_DDR_CLKN

M0_DDR_A6

M1_DDR_CLKN

M1_DDR_DQ7

C731

1000pF

C719

0.1uF

M0_DDR_WEN

M0_DDR_ODT

M1_DDR_DQ0

C750

1000pF

C746

0.1uF

M1_DDR_DQ6

C730

1000pF

C718

0.1uF

C726

0.1uF

M0_DDR_A0

R734

1K 1%

R723

1K 1%

C706 0.1uF

M0_DDR_DQSU_P

M1_DDR_DQ12

M1_DDR_WEN

M0_DDR_A3

M1_DDR_ODT

M1_DDR_A2

R726

1K 1%

M0_DDR_DQ14

M0_DDR_A7

VCC1.5V_MAIN

R733

1K 1%

M0_DDR_A6

C727

0.1uF

M0_DDR_BA2

M0_DDR_VREFCA

M0_1_DDR_VREFDQ

VCC1.5V_MAIN

R710
10K

M1_DDR_CLKN

C759

0.1uF

C734

0.1uF

M1_1_DDR_VREFCA

M1_DDR_A1

M1_DDR_DQSL_P

M1_DDR_RASN

M1_DDR_A13

M0_DDR_DQSU_N

M0_DDR_DQ0

M0_DDR_RESET_N

R731

1K 1%

M0_DDR_A14

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_A7

M1_DDR_A4

VCC1.5V_MAIN

M0_DDR_CASN

M0_DDR_A3

M1_DDR_A12

C714

0.1uF

M1_DDR_CLK

R732

1K 1%

R725

1K 1%

C713

0.1uF

M0_DDR_A8

M1_DDR_VREFCA

M0_DDR_DQ1

M1_DDR_A11

M1_1_DDR_VREFDQ

C725

0.1uF

M0_DDR_DQ8

M1_DDR_RASN

VCC1.5V_MAIN

M0_DDR_A4

M0_DDR_CKE

R722

1K 1%

M0_DDR_CKE

M1_DDR_A0

M1_DDR_A8

C760

0.1uF

M0_DDR_A5

M1_DDR_A10

C754

0.1uF

M0_DDR_A1

M1_DDR_VREFCA

M1_DDR_ODT

M1_DDR_A14

M0_DDR_CLKN

M0_DDR_A12

M0_DDR_DQ5

C712

0.1uF

VCC1.5V_MAIN

M1_DDR_A9

M1_DDR_VREFDQ

M0_DDR_A2

C755

0.1uF

R724

1K 1%

M0_DDR_A9

M1_DDR_A8

M1_DDR_CLKN

M0_DDR_DQ13

M0_DDR_A2

C756

0.1uF

R728

1K 1%

M0_DDR_A13

M0_DDR_DQ2

M0_DDR_DML

M0_DDR_CKE

M0_DDR_DQ4

M1_DDR_DQ15

M0_DDR_BA1

M1_DDR_A8

M1_DDR_DQ4

M1_DDR_DQSL_P

M1_DDR_A2

M1_DDR_A4

M0_DDR_DQ11

M0_DDR_DQ0

M1_DDR_DQ15

M1_DDR_DQ10

M1_DDR_DQSL_N

M0_DDR_DQ12

M0_DDR_A14

M0_DDR_A9

M1_DDR_BA0

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_BA0

M0_DDR_DQ14

M0_DDR_CKE

M1_DDR_DQSU_P

M0_DDR_A1

M0_DDR_DQSU_N

M0_DDR_DQSL_P

M0_DDR_DML

M0_DDR_A6
M0_DDR_A7

M0_DDR_ODT

M1_DDR_A6

M1_DDR_WEN

M1_DDR_DQ6

M0_DDR_A2

M0_DDR_DQ2

M1_DDR_DQ8

M0_DDR_A5

M1_DDR_A10

M0_DDR_CLK

M1_DDR_DQ0

M0_DDR_DQ5

M1_DDR_A1

M1_DDR_A7

M1_DDR_A13

M0_DDR_A0

M0_DDR_A4

M1_DDR_DQ7

M1_DDR_CLKN

M0_DDR_DQ8

M1_DDR_ODT

M0_DDR_A12

M0_DDR_DQ9

M0_DDR_A3

M1_DDR_RESET_N

M0_DDR_DQ13

M1_DDR_A11

M1_DDR_RASN

M1_DDR_DQ13

M1_DDR_DQ9

M0_DDR_DQ7

M0_DDR_A13

M1_DDR_CASN

M1_DDR_A5

M0_DDR_A8

M1_DDR_DML

M1_DDR_BA1

M0_DDR_DQ1

R704

240

1%

M0_DDR_BA2

M0_DDR_RASN

M1_DDR_A0

M1_DDR_DQ1

M0_DDR_CASN

M0_DDR_A11

M1_DDR_DQ14

M1_DDR_DQ3

M1_DDR_A12

M1_DDR_DQ2

M0_DDR_DMU

M1_DDR_DQ5

M0_DDR_DQ6

M0_DDR_DQ3

M1_DDR_DQSU_N

M1_DDR_DQ11
M1_DDR_DQ12

M0_DDR_CLKN

M0_DDR_DQ10

M1_DDR_BA2

M1_DDR_CLK

M1_DDR_A3

M0_DDR_DQ15

M1_DDR_DMU

M1_DDR_A9

M1_DDR_A14

M0_DDR_DQ4

M0_DDR_DQSL_N

M1_DDR_CKE

M0_DDR_A10

M0_DDR_DQSU_P

M2_DDR_WEN

M2_DDR_A3

M2_DDR_DQ5

M2_DDR_A2

M2_DDR_DQ1

M2_DDR_CKE

M2_DDR_A12

M2_DDR_DQ6

M2_DDR_A1

M2_DDR_DQ7

M2_DDR_A11

M2_DDR_DQ11

M2_DDR_DQ3
M2_DDR_DQ4

M2_DDR_DQ9

M2_DDR_A13

M2_DDR_DQ14

M2_DDR_BA0

M2_DDR_CLK
M2_DDR_CLKN

M2_DDR_RASN

M2_DDR_DQSU_P

M2_DDR_BA1

M2_DDR_DML

M2_DDR_RESET_N

M2_DDR_DMU

M2_DDR_DQ13

M2_DDR_A5

M2_DDR_A9

M2_DDR_DQ2

M2_DDR_DQ10

M2_DDR_A10

M2_DDR_DQSL_P
M2_DDR_DQSL_N

M2_DDR_DQ8

M2_DDR_DQSU_N

M2_DDR_ODT

M2_DDR_DQ0

M2_DDR_DQ12

M2_DDR_A0

M2_DDR_A6

M2_DDR_CASN

M2_DDR_DQ15

R711

240

1%

M2_DDR_A8

M2_DDR_A7

M2_DDR_BA2

M2_DDR_A4

VCC1.5V_DE

R719

1K 1%

R712

1K 1%

R718

1K 1%

R743
10K

M2_DDR_VREFDQ

M2_DDR_CKE

C703

1000pF

M2_DDR_CLKN

M2_CLK

C700

0.1uF

R713

1K 1%

M2_CLKN

C701

1000pF

R714
10K

M2_DDR_CLK

M2_CLKN

M2_CLK

VCC1.5V_DE

C702

0.1uF

VCC1.5V_DE

M2_DDR_VREFCA

M2_DDR_RESET_N M2_CLK

M2_CLKN

H5TQ2G83BFR-PBC

IC700

NC_S1

A1

VSS_1

A2

VDD_1

A3

NC_1

A4

NF/TDQSA8VSS_2

A9

VDD_2

A10

NC_S2

A11

VSS_3

B2

VSSQ_1

B3

DQ0

B4

DM/TDQS

B8

VSSQ_2

B9

VDDQ_1

B10

VDDQ_2

C2

DQ2

C3

DQS

C4

DQ1

C8

DQ3

C9

VSSQ_3

C10

VSSQ_4

D2

DQ6

D3

DQS

D4

VDD_3

D8

VSS_4

D9

VSSQ_5

D10

VREFDQ

E2

VDDQ_3

E3

DQ4

E4

DQ7

E8

DQ5

E9

VDDQ_4

E10

NC_2

F2

VSS_5

F3

RAS

F4

CK

F8

VSS_6

F9

NC_3

F10

ODT

G2

VDD_4

G3

CAS

G4

CK

G8

VDD_5

G9

CKE

G10

NC_4

H2

CS

H3

WE

H4

A10/AP

H8

ZQ

H9

NC_5

H10

VSS_7

J2

BA0

J3

BA2

J4

NC_6

J8

VREFCA

J9

VSS_8

J10

VDD_6

K2

A3

K3

A0

K4

A12/BC

K8

BA1

K9

VDD_7

K10

VSS_9

L2

A5

L3

A2

L4

A1

L8

A4

L9

VSS_10

L10

VDD_8

M2

A7

M3

A9

M4

A11

M8

A6

M9

VDD_9

M10

NC_S3

N1

VSS_11

N2

RESET

N3

A13

N4

A14

N8

A8

N9

VSS_12

N10

NC_S4

N11

H5TQ2G83BFR-PBC

IC703

NC_S1

A1

VSS_1

A2

VDD_1

A3

NC_1

A4

NF/TDQSA8VSS_2

A9

VDD_2

A10

NC_S2

A11

VSS_3

B2

VSSQ_1

B3

DQ0

B4

DM/TDQS

B8

VSSQ_2

B9

VDDQ_1

B10

VDDQ_2

C2

DQ2

C3

DQS

C4

DQ1

C8

DQ3

C9

VSSQ_3

C10

VSSQ_4

D2

DQ6

D3

DQS

D4

VDD_3

D8

VSS_4

D9

VSSQ_5

D10

VREFDQ

E2

VDDQ_3

E3

DQ4

E4

DQ7

E8

DQ5

E9

VDDQ_4

E10

NC_2

F2

VSS_5

F3

RAS

F4

CK

F8

VSS_6

F9

NC_3

F10

ODT

G2

VDD_4

G3

CAS

G4

CK

G8

VDD_5

G9

CKE

G10

NC_4

H2

CS

H3

WE

H4

A10/AP

H8

ZQ

H9

NC_5

H10

VSS_7

J2

BA0

J3

BA2

J4

NC_6

J8

VREFCA

J9

VSS_8

J10

VDD_6

K2

A3

K3

A0

K4

A12/BC

K8

BA1

K9

VDD_7

K10

VSS_9

L2

A5

L3

A2

L4

A1

L8

A4

L9

VSS_10

L10

VDD_8

M2

A7

M3

A9

M4

A11

M8

A6

M9

VDD_9

M10

NC_S3

N1

VSS_11

N2

RESET

N3

A13

N4

A14

N8

A8

N9

VSS_12

N10

NC_S4

N11

H5TQ2G83BFR-PBC

IC704

NC_S1

A1

VSS_1

A2

VDD_1

A3

NC_1

A4

NF/TDQS

A8

VSS_2

A9

VDD_2

A10

NC_S2

A11

VSS_3

B2

VSSQ_1

B3

DQ0

B4

DM/TDQS

B8

VSSQ_2

B9

VDDQ_1

B10

VDDQ_2

C2

DQ2

C3

DQS

C4

DQ1

C8

DQ3

C9

VSSQ_3

C10

VSSQ_4

D2

DQ6

D3

DQS

D4

VDD_3

D8

VSS_4

D9

VSSQ_5

D10

VREFDQ

E2

VDDQ_3

E3

DQ4

E4

DQ7

E8

DQ5

E9

VDDQ_4

E10

NC_2

F2

VSS_5

F3

RAS

F4

CK

F8

VSS_6

F9

NC_3

F10

ODT

G2

VDD_4

G3

CAS

G4

CK

G8

VDD_5

G9

CKE

G10

NC_4

H2

CS

H3

WE

H4

A10/AP

H8

ZQ

H9

NC_5

H10

VSS_7

J2

BA0

J3

BA2

J4

NC_6

J8

VREFCA

J9

VSS_8

J10

VDD_6

K2

A3

K3

A0

K4

A12/BC

K8

BA1

K9

VDD_7

K10

VSS_9

L2

A5

L3

A2

L4

A1

L8

A4

L9

VSS_10

L10

VDD_8

M2

A7

M3

A9

M4

A11

M8

A6

M9

VDD_9

M10

NC_S3

N1

VSS_11

N2

RESET

N3

A13

N4

A14

N8

A8

N9

VSS_12

N10

NC_S4

N11

H5TQ2G83BFR-PBC

IC701

NC_S1

A1

VSS_1

A2

VDD_1

A3

NC_1

A4

NF/TDQS

A8

VSS_2

A9

VDD_2

A10

NC_S2

A11

VSS_3

B2

VSSQ_1

B3

DQ0

B4

DM/TDQS

B8

VSSQ_2

B9

VDDQ_1

B10

VDDQ_2

C2

DQ2

C3

DQS

C4

DQ1

C8

DQ3

C9

VSSQ_3

C10

VSSQ_4

D2

DQ6

D3

DQS

D4

VDD_3

D8

VSS_4

D9

VSSQ_5

D10

VREFDQ

E2

VDDQ_3

E3

DQ4

E4

DQ7

E8

DQ5

E9

VDDQ_4

E10

NC_2

F2

VSS_5

F3

RAS

F4

CK

F8

VSS_6

F9

NC_3

F10

ODT

G2

VDD_4

G3

CAS

G4

CK

G8

VDD_5

G9

CKE

G10

NC_4

H2

CS

H3

WE

H4

A10/AP

H8

ZQ

H9

NC_5

H10

VSS_7

J2

BA0

J3

BA2

J4

NC_6

J8

VREFCA

J9

VSS_8

J10

VDD_6

K2

A3

K3

A0

K4

A12/BC

K8

BA1

K9

VDD_7

K10

VSS_9

L2

A5

L3

A2

L4

A1

L8

A4

L9

VSS_10

L10

VDD_8

M2

A7

M3

A9

M4

A11

M8

A6

M9

VDD_9

M10

NC_S3

N1

VSS_11

N2

RESET

N3

A13

N4

A14

N8

A8

N9

VSS_12

N10

NC_S4

N11

IC100

LG1152D-B1

M0_DDR_A0

D18

M0_DDR_A1

E17

M0_DDR_A2

E18

M0_DDR_A3

E20

M0_DDR_A4

E16

M0_DDR_A5

D20

M0_DDR_A6

F16

M0_DDR_A7

F19

M0_DDR_A8

E15

M0_DDR_A9

D19

M0_DDR_A10

D14

M0_DDR_A11

E14

M0_DDR_A12

D17

M0_DDR_A13

F18

M0_DDR_A14

D16

M0_DDR_BA0

F20

M0_DDR_BA1

D15

M0_DDR_BA2

F17

M0_DDR_CLK

A17

M0_DDR_CLKN

A18

M0_DDR_CKE

F15

M0_DDR_ODT

F21

M0_DDR_RASN

D22

M0_DDR_CASN

E21

M0_DDR_WEN

D21

M0_DDR_RESET_N

E19

M0_DDR_DQSL_P

B20

M0_DDR_DQSL_N

A20

M0_DDR_DQSU_P

B16

M0_DDR_DQSU_N

C16

M0_DDR_DML

C19

M0_DDR_DMU

C15

M0_DDR_DQ0

C20

M0_DDR_DQ1

B19

M0_DDR_DQ2

C21

M0_DDR_DQ3

B18

M0_DDR_DQ4

A21

M0_DDR_DQ5

C18

M0_DDR_DQ6

B21

M0_DDR_DQ7

A19

M0_DDR_DQ8

B17

M0_DDR_DQ9

C14

M0_DDR_DQ10

A16

M0_DDR_DQ11

B14

M0_DDR_DQ12

B15

M0_DDR_DQ13

A14

M0_DDR_DQ14

C17

M0_DDR_DQ15

A15

M0_DDR_ZQCAL

E22

IC100

LG1152D-B1

M1_DDR_A0

C9

M1_DDR_A1

E9

M1_DDR_A2

F10

M1_DDR_A3

F12

M1_DDR_A4

F8

M1_DDR_A5

D11

M1_DDR_A6

E8

M1_DDR_A7

E11

M1_DDR_A8

E7

M1_DDR_A9

D10

M1_DDR_A10

C4

M1_DDR_A11

C5

M1_DDR_A12

D8

M1_DDR_A13

E10

M1_DDR_A14

C7

M1_DDR_BA0

E12

M1_DDR_BA1

F7

M1_DDR_BA2

D9

M1_DDR_CLK

A9

M1_DDR_CLKN

B9

M1_DDR_CKE

D7

M1_DDR_ODT

D13

M1_DDR_RASN

C13

M1_DDR_CASN

E13

M1_DDR_WEN

D12

M1_DDR_RESET_N

F11

M1_DDR_DQSL_P

C12

M1_DDR_DQSL_N

C11

M1_DDR_DQSU_P

A7

M1_DDR_DQSU_N

B7

M1_DDR_DML

A11

M1_DDR_DMU

C6

M1_DDR_DQ0

A12

M1_DDR_DQ1

B11

M1_DDR_DQ2

A13

M1_DDR_DQ3

C10

M1_DDR_DQ4

B12

M1_DDR_DQ5

A10

M1_DDR_DQ6

B13

M1_DDR_DQ7

B10

M1_DDR_DQ8

A8

M1_DDR_DQ9

B4

M1_DDR_DQ10

C8

M1_DDR_DQ11

B5

M1_DDR_DQ12

B6

M1_DDR_DQ13

A5

M1_DDR_DQ14

B8

M1_DDR_DQ15

A6

IC100

LG1152D-B1

M2_DDR_A0

D1

M2_DDR_A1

K4

M2_DDR_A2

D2

M2_DDR_A3

E5

M2_DDR_A4

H6

M2_DDR_A5

E4

M2_DDR_A6

J4

M2_DDR_A7

D6

M2_DDR_A8

J5

M2_DDR_A9

D3

M2_DDR_A10

H4

M2_DDR_A11

J6

M2_DDR_A12

K5

M2_DDR_A13

D4

M2_DDR_BA0

E6

M2_DDR_BA1

H5

M2_DDR_BA2

F4

M2_DDR_CLK

M2

M2_DDR_CLKN

M3

M2_DDR_CKE

G6

M2_DDR_ODT

F6

M2_DDR_RASN

G5

M2_DDR_CASN

G4

M2_DDR_WEN

F5

M2_DDR_RESET_N

D5

M2_DDR_DQSU_P

H3

M2_DDR_DQSU_N

J1

M2_DDR_DQSL_P

H1

M2_DDR_DQSL_N

H2

M2_DDR_DML

K3

M2_DDR_DMU

F2

M2_DDR_DQ0

F1

M2_DDR_DQ1

L1

M2_DDR_DQ2

E3

M2_DDR_DQ3

L2

M2_DDR_DQ4

E1

M2_DDR_DQ5

M1

M2_DDR_DQ6

E2

M2_DDR_DQ7

L3

M2_DDR_DQ8

J3

M2_DDR_DQ9

G1

M2_DDR_DQ10

K2

M2_DDR_DQ11

F3

M2_DDR_DQ12

J2

M2_DDR_DQ13

G2

M2_DDR_DQ14

K1

M2_DDR_DQ15

G3

M2_DDR_ZQCAL

K6

R700 0
R701 0

R703 0

R702 0

R716 0
R717 0

R715
150

R705
200

R706
200

R708
200

R707
200

4MAIN DDR 50

LG1152 B0

DDR3 1.5V bypass Cap - Place these caps near Memory

DDR3
2Gbit

DDR3
2Gbit

DDR3
2Gbit

DDR3
2Gbit

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

CI_DATA[7]

EB_DATA[0]

CI_DATA[1]

CI_DATA[5]

CI_DATA[3]

CI_DATA[2]

CI_DATA[0-7]

CI_DATA[6]

EB_DATA[1]

EB_DATA[7]

CI_DATA[0]

EB_DATA[5]

EB_DATA[0-7]

EB_DATA[2]

EB_DATA[4]

EB_DATA[3]

CI_DATA[4]

EB_DATA[6]

TPO_DATA[3]
TPO_DATA[4]

TPO_DATA[0]

TPO_DATA[7]

TPO_DATA[1]

TPO_DATA[5]
TPO_DATA[6]

TPO_DATA[2]

CI_ADDR[9]

CI_DATA[1]

CI_IN_TS_DATA[6]

CI_ADDR[1]

CI_DATA[6]

CI_IN_TS_DATA[3]

CI_ADDR[5]

CI_ADDR[13]

CI_IN_TS_DATA[2]

CI_ADDR[8]

CI_ADDR[2]

CI_ADDR[3]

CI_ADDR[4]

CI_DATA[0]

CI_DATA[7]

CI_DATA[4]

CI_ADDR[12]

CI_ADDR[11]

CI_IN_TS_DATA[0]

CI_DATA[5]

CI_ADDR[14]

CI_DATA[3]

CI_DATA[2]

CI_ADDR[10]

CI_ADDR[0]

CI_IN_TS_DATA[1]

CI_ADDR[7]

CI_IN_TS_DATA[7]

CI_ADDR[6]

CI_IN_TS_DATA[4]
CI_IN_TS_DATA[5]

R913

0

OPT

CI_ADDR[13]

CI_ADDR[8]

CI_ADDR[7]

EB_ADDR[12]

/PCM_IOWR

EB_ADDR[0]

CI_ADDR[1]

EB_BE_N1

DIR

EB_ADDR[1]

CI_ADDR[11]

EB_ADDR[13]

CI_ADDR[9]

AR912

33

CI

AR913

33

CI

CI_ADDR[5]

CI_ADDR[2]

EB_OE_N

/PCM_OE

EB_ADDR[2]

EB_ADDR[10]

C903

0.1uF

16V

CI

/PCM_OE

AR915

33

CI

AR909

33

CI

EB_DATA[0-7]

CI_DATA[0-7]

+3.3V_NORMAL

EB_ADDR[6]

CI_ADDR[4]

/PCM_WE

EB_ADDR[5]

EB_ADDR[4]

EB_ADDR[8]

/PCM_IORD

AR911

33

CI

EB_ADDR[11]

EB_WE_N

EB_ADDR[3]

/PCM_IORD

CI_ADDR[0]

CI_ADDR[6]

IC904

74LVC245A

CI

3

A1

2

A0

4

A2

1

DIR

6

A4

5

A3

7

A5

8

A6

9

A7

10

GND

11

B7

12

B6

13

B5

14

B4

15

B3

16

B2

17

B1

18

B0

19

OE

20

VCC

CI_ADDR[14]

EB_ADDR[14]

C904

0.1uF

16V

CI

EB_BE_N0

DIR

EB_ADDR[7]

+3.3V_NORMAL

CI_ADDR[12]

CI_ADDR[3]

CAM_REG_N

EB_ADDR[9]

CI_ADDR[10]

AR914

33

CI

AR910

33

CI

/PCM_CE1

/PCM_REG

IC905

74LVC1G00GW

CI

3GND2A4 Y

1B 5 VCC

TPO_CLK

TPO_VAL
TPO_ERR

TPO_DATA[0-7]

TPO_SOP

/PCM_WE

/PCM_OE

PCM_INPACK

+5V_CI_ON

CI_TS_CLK

CI_ADDR[0]

CI_ADDR[10]

/PCM_IORD

/PCM_CE1

P6200

10067972-000LF CI

G1G2

57

TS_OUT_CLK

21

ADDR12

52

VPP

16

/IRQA

10

ADDR11

47

TS_IN0

41

TS_OUT7

5

DAT6

36

/CI_DET1

59

CI_WAIT

23

ADDR6

45

IOWR

54

TS_IN5

18

VPP

49

TS_IN2

43

VS1

13

ADDR13

7

/CARD_EN1

38

TS_OUT4

2

DAT3

25

ADDR4

56

TS_IN7

20

TS_IN_CLK

51

VCC

15

/WR_EN

9

/O_EN

46

TS_IN_SYN

40

TS_OUT6

4

DAT5

35

GND

58

CI_RESET

22

ADDR7

53

TS_IN4

17

VCC

11

ADDR10

48

TS_IN1

42

CARD_EN2

12

ADDR8

6

DAT6

37

TS_OUT3

1

GND

24

ADDR5

55

TS_IN6

19

TS_IN_VAL

50

TS_IN3

44

IORD

14

ADDR14

8

ADDR10

39

TS_OUT5

3

DAT4

26

ADDR3

60

INPACK

27

ADDR2

61

REG

28

ADDR1

62

TS_OUT_VAL

29

ADDR0

63

TS_OUT_SYN

30

DAT0

64

TS_OUT0

31

DAT1

32

DAT2

33

/IO_BIT

34

GND

65

TS_OUT1

66

TS_OUT2

67

/CI_DET2

68

GND

69

CI_ADDR[8]

R6224 22

CI

CI_ADDR[14]

R6204

10K
OPT

/PCM_REG

CI_TS_DATA[1]

R6213

0

OPT

R6210

0

OPT

/PCM_IOWR

CI_ADDR[4]

R6211

10K
OPT

CI_TS_DATA[0]

/PCM_IRQA

/CI_CD1

CI_IN_TS_VAL

CI_TS_VAL

CI_ADDR[1]

CI_ADDR[11]

PCM_INPACK

CI_VS1

C6201
10uF
10V
CI

CI_TS_DATA[3]

+5V_CI_ON

CI_TS_DATA[5]

R6243 22

OPT

R6249

0

OPT

CI_ADDR[9]

R6207

10K

CI

R6216

0

OPT

CI_TS_DATA[7]

+5V_CI_ON

/CI_CD2

R6208
10K
OPT

C6205 0.1uF

CI

CI_DATA[0-7]

R6205

10K
OPT

CI_TS_DATA[6]

R6206

10K

OPT

CI_TS_DATA[4]

CI_TS_SYNC

C6200

0.1uF
CI

R6209
10K
OPT

CI_TS_DATA[2]

CI_VS1

R6202

22

CI

+5V_CI_ON

R6203

22

CI

R6200

22

OPT

R6217

10K

OPT

CI_IN_TS_DATA[0-7]

CI_ADDR[7]

R6219
10K
OPT

+5V_CI_ON

CI_ADDR[3]

/PCM_CE2

R6245
10K
OPT

CI_ADDR[13]

+5V_CI_ON

R6212 0

CI

R6214

100

CI

R6246

10K

OPT

R6244
10K

CI

CI_ADDR[5]

/PCM_WAIT

CI_ADDR[2]

CI_ADDR[6]

R6215 100

CI

/PCM_CE2

CI_IN_TS_SYNC

PCM_RST

C6206

0.1uF
16V

CI

CI_IN_TS_CLK

CI_ADDR[12]

AR905

33

CI

AR903

33

CI

AR904

33

CI

CI_IN_TS_DATA[7]

CI_IN_TS_DATA[6]

CI_IN_TS_DATA[0]
CI_IN_TS_DATA[1]

CI_IN_TS_DATA[5]

CI_IN_TS_DATA[2]

CI_IN_TS_DATA[4]

CI_IN_TS_DATA[3]

CI_IN_TS_SYNC
CI_IN_TS_VAL

CI_IN_TS_CLK

TPI_DATA[7]

AR919

100

CI

CAM_CD1_N

CAM_INPACK_N

C905

0.1uF
16V

CI

CI_TS_DATA[7]

AR921

100

CI

PCM_INPACK

CI_TS_DATA[2]

CI_TS_SYNC

C900

0.1uF

16V

CI

TPI_VAL

CAM_IREQ_N

TPI_DATA[4]

TPI_DATA[5]

TPI_DATA[2]

CAM_WAIT_N

/PCM_WAIT

TPI_DATA[0]

TPI_SOP

AR917

75

CI

/CI_CD1

TPI_DATA[3]

CI_TS_DATA[1]

/CI_CD2

CI_TS_CLK

CI_TS_DATA[5]

R915

10K

CI

AR916

75

CI

/PCM_IRQA

CI_TS_VAL

CI_TS_DATA[4]

CI_TS_DATA[0]

CAM_CD2_N

TPI_DATA[6]

AR918 75

CI

TPI_CLK

R916

10K

CI

IC903

74LVC16244ADGG

CI

26

4A3

27

4A2

28

GND_5

29

4A1

30

4A0

31

VCC_3

32

3A3

33

3A2

34

GND_6

35

3A1

36

3A0

37

2A3

38

2A2

39

GND_7

40

2A1

41

2A0

42

VCC_4

43

1A3

44

1A2

45

GND_8

46

1A1

47

1A0

48

2OE

17

3Y4

3

1Y1

6

1Y3

16

3Y2

15

GND_3

14

3Y1

13

3Y0

12

2Y3

11

2Y2

10

GND_2

9

2Y1

8

2Y0

7

VCC_1

4

GND_1

5

1Y2

25

3OE

24

4OE

23

4Y3

2

1Y0

22

4Y2

21

GND_4

1

1OE

20

4Y1

19

4Y0

18

VCC_2

+3.3V_NORMAL

TPI_DATA[1]

C906

0.1uF
16V

CI

+5V_NORMAL

CI_TS_DATA[6]

AR920

100

CI

CI_TS_DATA[3]

AND GATE => NAND GATE

IOWE=>IORD

CI HOST I/F

5V <=> 3.3V

WE=>OE

BUFFER FOR 5V => 3.3V

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THERMAL

THERMAL

THERMAL

THERMAL

THERMAL

THERMAL

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C2313
10uF
10V

C2315

0.1uF
16V

C2302

4.7uF
16V

+12V

+0.9V_VDD

C2348

4700pF 50V

POWER_ON/OFF2_3

R2342

330K1/16W 5%

R2305
10K

IC2307

NCP803SN293

1

GND

3

VCC2RESET

PANEL_VCC

C2365

0.1uF
16V

L2317

1uH

L2310

BLM18PG121SN1D

+5V_NORMAL

RL_ON

INV_CTL

C2339

1uF

25V

OPT

+3.5V_ST

C2343
22uF
10V

+3.3V_NORMAL

+1.5V_DDR

C2360

0.1uF
16V

PD_24V

C2327

0.1uF

16V

L2307

CIS21J121

PWM_DIM2

R2311

10K

1%

C2301

4.7uF
10V

P2300

SMAW200-H24S2

19

12V

14

GND

9

3.5V

4

24V

18

INV ON

13

GND

8

GND

3

24V

17

12V

12

3.5V

7

GND

2

24V

16

GND/V-sync

11

3.5V

6

GND

1

PWR ON

20

A.DIM

15

GND

10

3.5V

5

GND

21

12V22P.DIM1

23

GND/P.DIM224Err OUT

25

C2349

0.1uF
16V

PANEL_CTL

R2340
15K

1/16W 5%

R2341

10K

L2306
BLM18PG121SN1D

+3.5V_ST

+24V

C2363
22uF
10V

+3.3V_NORMAL

R2350
56K

1/16W

1%

L2308

C2306

0.1uF
50V

L2301
BLM18PG121SN1D

C2330

4700pF

50V

R2349

47K 1%

IC2308

NCP803SN293

PD_24V

1

GND

3

VCC2RESET

C2336
1uF
10V

+3.3V_NORMAL

C2374

22000pF 50V

R2372
100K

PD_24V

R2376
10K
OPT

R2300
10K

A_DIM

C2317

0.1uF
50V

R2373
100K

C2373

47pF 50V

R2312
100

C2350
22uF
10V

2200pF

C2308

50V

+12V

R2334
10K

3.3V_EMMC

C2340
10uF
10V

+3.5V_ST

+1.8V_NORMAL

+1.8V_NORMAL

L2319
BLM18PG121SN1D

+2.5V_NORMAL

POWER_ON/OFF2_2

R2321

3.9K

1/16W

1%

EMMC_VCCQ

PWM_DIM

C2347
10uF
16V

C2370
10uF
10V

OPT

C2371

0.1uF
16V

R2314
3K
1%

L/DIM0_VS

C2346

0.1uF
50V

L2302

CIS21J121

L2311

CIS21J121

POWER_ON/OFF2_1

L2312

3.6uH

NR8040T3R6N

C2307

0.1uF
16V

Q2304
MMBT3904(NXP)

E

B

C

R2357 1K

C2344

0.1uF
16V

C2341

0.1uF
16V

C2345

0.1uF
16V

R2381 0

1/16W

5%

C2332
10uF

16V

Q2301 MMBT3906(NXP)

1

2

3

+3.3V_TU_IN

POWER_DET

C2359

0.1uF
16V

L2314
BLM18PG121SN1D

C2337
22uF
10V

R2308

56K

1%

L2315

+0.9V_VDD

R2347

4.3K
1%

R2306

10K

+24V

POWER_ON/OFF2_3

C2320
10uF
10V

C2322
10uF
16V

2200pF

C2331

50V

C2326

0.01uF
50V

IC2304

TPS54327DDAR

3

VREG5

2

VFB

4

SS

1

EN

5

GND

6

SW

7

VBST

8

VIN

9

[EP]GND

+3.5V_ST

P2301
FW20020-24S

OPT

19

14

9

4

18

13

8

3

17

12

7

2

16

11

6

1

20

15

10

5

21 22
23 24

Q2305

AO3407A

G

D

S

R2348

10K

OPT

POWER_ON/OFF1

R2339

10K

R2330
1K

+3.5V_ST

C2372

0.1uF
16V

R2302
100

LPB

L2303

BLM18SG121TN1D

L2305

CIS21J121

C2334
100pF

50V

C2328

0.1uF
50V

+3.5V_ST

C2325

0.1uF
16V

C2338
100pF
50V

ERROR_OUT

+12V

+3.3V_TU

R2366
0
5%

PD_+3.5V

R2377
100K

1/16W
5%

C2335

0.1uF
50V

OPT

+12V

C2375
180pF
50V

R2315
100
1%

C2329

0.01uF
50V

+12V

+5V_NORMAL

C2333
22uF

10V

R2346
2K
1%

10uF

C2324

10V

C2342
2200pF
50V

L2313

6.8uH

NR8040T4R7N

R2362

2.7K
1%

PD_+12V

R2363

1.2K
1%

PD_+12V

R2364

8.2K
1%

PD_24V

R2365

1.5K
1%

PD_24V

C2314
10uF
10V

L2300

BLM18PG121SN1D

+12V

C2309

0.1uF
16V
OPT

C2312
10uF
10V

C2310

0.1uF
16V

R2320

10K

1%

R23160

OPT

L2304

2uH

C2300
10uF
16V

C2304
10uF
16V

C2353
3300pF
50V
OPT

C2352
10uF
10V

R2318

10K

C2316
10uF
10V

R2319

1.5K

1%

R2382

30K

1/16W

1%

+3.3V_NORMAL

POWER_ON/OFF2_1

C2318
1uF
10V

C2319
3300pF
50V

C2303

0.1uF
50V

+12V

C2305

0.1uF
OPT

R2309
100K

C2321
22pF
50V

OPT

L2316

2uH

C2369
22uF
10V

L2309
BLM18PG121SN1D

C2354
10uF
16V

C2368
22uF
10V

R2310 10K

POWER_ON/OFF2_3

R2317

20K

C2311

2200pF

50V

R2304

0

IC2301

AOZ1038PI

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

NC_1

8

NC_2

9

[EP]LX

IC2300

AP7173-SPG-13 HF(DIODES)

3

VCC

2

PG

4

EN

1

IN

5

GND

6

SS

7

FB

8

OUT

9

[EP]

IC2303

AP7173-SPG-13 HF(DIODES)

3

VCC

2

PG

4

EN

1

IN

5

GND

6

SS

7

FB

8

OUT

9

[EP]

IC2302

TPS54319TRE

1

VIN_1

3

GND_1

7

COMP

9

SS/TR

10

PH_1

11

PH_2

12

PH_3

13

BOOT14PWRGD15EN16VIN_3

5

AGND

8

RT/CLK6VSENSE

4

GND_2

2

VIN_2

17

EP[GND]

IC2306

TPS54425PWPR

3

VREG5

2

VFB

4

SS

1

VO

6

PG

5

GND

7EN8

PGND1

9

PGND2

10

SW1

11

SW2

12

VBST

13

VIN1

14

VIN2

15

[EP]PGND

D2350

ADUC 20S 02 010L

R2378

6.8K

1/16W

1%

FRC3

R2322
22K

1%
FRC3

+1.0VDC

IC2305

EAN62348501

3

GND_2

2

GND_1

4

PVIN_1

1

RT/CLK

6

VIN

5

PVIN_2

7

VSENSE

8

COMP

9

SS/TR

10

EN

11

PH_1

12

PH_2

13

BOOT

14

PWRGD

15

[EP]GND

R2343

33K

R2344

5.6K

R2307

1.3K

L2318

CIS21J121

OPT

R2301
10KPOWER_ON/OFF1

R2313

9.1K
1%

R2379

12K

1/16W

1%

FRC3

R2322-*1
24K

1%

URSA5

R2378-*1

8.2K

1/16W

1%

URSA5

R2379-*1

15K

1/16W

1%

URSA5

POWER

LG1152

3A

R2

2

Switching freq: 700K

R1

R2

4

R1

Vout=0.827*(1+R1/R2)=1.521V

3A

+1.0V_VDD

1.5A

R2

4

R2

Max 5926 mA

Vout=0.765*(1+R1/R2)

R2

Tuner 1.25V REG Input

LG1152 Max: 1728 mA

1074 mA

not to RESET at 8kV ESD

+2.5V

1

PANEL_POWER

eMMC POWER

293 mA

$ 0.145

MAX 1A

R1

700 mA

Vout=0.8*(1+R1/R2)

3. soft start

R1

R1

ST_3.5V-->3.5V

Switching freq: 400 ~ 580 Khz

TYP 1450mA

+5V_Normal

24V-->3.48V

Vout=0.6*(1+R1/R2)

+1.8V

1

3A

DDR MAIN 1.5V

1.5A

MAX 4.7 A

12V-->3.58V

Power_DET

4

LG1132 Max: 2000 mA

Placed on SMD-TOP

R1

*NOTE 17

R2

Vout=0.8*(1+R1/R2)

+3.3V_NORMAL

4A

Vout=0.765*(1+R1/R2)

R1

R2

6A

Vout=0.8*(1+R1/R2)

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

EEPROM_SCL

+3.5V_ST

GND

POWER_ON/OFF2_4

EDID_WP

R3023

4.7M
OPT

C3004

0.1uF
16V

R3009 10K

MICOM_JAPAN

MICOM_DEBUG

SW3000

JTP-1127WEM

MICOM_RESET_SW

12

4 3

R3027

270K

OPT

R3026

10K

PANEL_CTL

SOC_RX

POWER_ON/OFF1

IR

SIDE_HP_MUTE

INV_CTL

MICOM_RESET

POWER_ON/OFF2_3

MODEL1_OPT_1

MODEL1_OPT_3

LED_B/GP4_LED_R

AMP_MUTE

AMP_RESET_N

R3022 10K

R3006 10K

MICOM_LCD/OLED

MICOM_RESET

R3012 10K

MICOM_LOGO_LIGHT

MODEL1_OPT_1

I2C_SCL3

KEY1

MODEL1_OPT_2

EXT_AMP_MUTE

I2C_SDA3

MODEL1_OPT_0

R3025 22

MICOM_DIIVA

+3.5V_ST

COMMERCIAL_12V_CTL

MODEL1_OPT_4

+3.5V_ST

MODEL1_OPT_0

SOC_RESET

12V_EXT_PWR_DET

R3007 10K

MICOM_TOUCH_KEY

POWER_ON/OFF2_1

R3008 10K

MICOM_TACT_KEY

R3010 10K

MICOM_NON_JAPAN

KEY2

SCART_MUTE

R3014 1K

MODEL1_OPT_4

+3.5V_ST

RL_ON

POWER_ON/OFF2_2

R3005 10K

MICOM_PDP

X3000

32.768KHz

R3024 22

MODEL1_OPT_3

EEPROM_SDA

MODEL1_OPT_2

HDMI_CEC

R3011 10K

MICOM_DEBUG

POWER_ON/OFF2_3

EXT_AMP_RESET

MICOM_DEBUG

C3000

0.1uF

SOC_TX

R3013 10K

MICOM_NON_LOGO_LIGHT

POWER_DET

POWER_ON/OFF2_4

+3.5V_ST

HDMI_CEC

D3000

BAT54_SUZHO

R3029

120K

CEC_REMOTE

R3028
27K

+3.5V_ST

RUE003N02

Q3001

HDMI_CEC_FET_ROHM

S

D

G

EXT_AMP_RESET

SCART_MUTE

EXT_AMP_MUTE

12V_EXT_PWR_DET

COMMERCIAL_12V_CTL

R3030 10K

MICOM_GP4_10PIN

R3031 10K

MICOM_GP3_12/15PIN

+3.3V_NORMAL

R3034

4.7K
OPT

+3.3V_NORMAL

+3.3V_NORMAL

+3.3V_NORMAL

R3035

4.7K
OPT

+3.3V_NORMAL

Q3000
MMBT3904(NXP)

EDID_WP

E

B

C

P3000

12507WS-12L

MICOM_DEBUG

1

2

3

4

5

6

7

8

9

10

11

12

13

R3036

10K
OPT

R3037

10K
OPT

R3032

10K

AMP_RESET_BY_MICOM

R3033

10K

IC3000

R5F100GEAFB

MICOM

1

P60/SCLA0

2

P61/SDAA0

3

P62

4

P63

5

P31/TI03/TO03/INTP4

6

P75/KR5/INTP9/SCK01/SCL01

7

P74/KR4/INTP8/SI01/SDA01

8

P73/KR3/SO01

9

P72/KR2/SO21

10

P71/KR1/SI21/SDA21

11

P70/KR0/SCK21/SCL21

12

P30/INTP3/RTC1HZ/SCK11/SCL11

13

P50/INTP1/SI11/SDA11

14

P51/INTP2/SO11

15

P17/TI02/TO02

16

P16/TI01/TO01/INTP5

17

P15/PCLBUZ1/SCK20/SCL20

18

P14/RXD2/SI20/SDA20

19

P13/TXD2/SO20

20

P12/SO00/TXD0/TOOLTXD

21

P11/SI00/RXD0/TOOLRXD/SDA00

22

P10/SCK00/SCL00

23

P146

24

P147/ANI18

25

P27/ANI7

26

P26/ANI6

27

P25/ANI5

28

P24/ANI4

29

P23/ANI3

30

P22/ANI2

31

P21/ANI1/AVREFM

32

P20/ANI0/AVREFP

33

P130

34

P01/TO00/RXD1

35

P00/TI00/TXD1

36

P140/PCLBUZ0/INTP6

37

P120/ANI19

38

P41/TI07/TO07

39

P40/TOOL0

40

RESET41P124/XT2/EXCLKS

42

P123/XT1

43

P137/INTP0

44

P122/X2/EXCLK

45

P121/X1

46

REGC47VSS48VDD

C3002

8pF

C3003 8pF

R3000

10K

R3001 22

MICOM_DIIVA

POD_WAKEUP_N

FLG_POD_DR

/RST_DIIVA

FLG_POD_DR

/RST_DIIVA

POD_WAKEUP_N

R3002 22

MICOM_DIIVA

R3003 22

AMP_RESET_BY_MICOM

MODEL1_OPT_6

MODEL1_OPT_5

MODEL1_OPT_6

MODEL1_OPT_5

R3020 10K

MICOM_MHL

R3021 10K

MICOM_NON_MHL

R3016 10K

MICOM_GED

R3017 10K

MICOM_NON_GED

C3001 0.47uF

LOGO_LIGHT

LOGO_LIGHT

SI1012CR-T1-GE3

Q3001-*1

HDMI_CEC_FET_VISHAY

S

D

G

R3018

3.3K

R3019

3.3K

R3005-*2

22K

MICOM_OLED_FRC

R3005-*1

56K

MICOM_OLED_MAIN

MICOM

30

For Debug

PDP

LOGO_LIGHT

Renesas MICOM

NON LOGO_LIGHT

/ OLED

MICOM MODEL OPTION

MODEL_OPT_3

LCD





For CEC

IR Wafer

10Pin

MODEL_OPT_4

12/15Pin

IR Wafer

10

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

JAPAN

NON JAPAN

TOUCH_KEY

TACT_KEY

GP4 High/MID Power SEQUENCE

POWER_ON/OFF!

POWER_ON/OFF2_1

POWER_ON/OFF2_2

POWER_ON/OFF2_3

POWER_ON/OFF2_4

SOC_RESET

For Japan:LNB_INIT

HDMI_WAUP:HDMI_INIT

2011.12.12

for DiiVA

For LM86

(GP3_Soft touch)

NON_MHL

MHLMODEL_OPT_5

NON_GED

GEDMODEL_OPT_6

For JAPAN

GP4_HIGH

(GP4_TOOL)

For Sample Set

MICOM MODEL OPTION

Eye Sensor Option

MODEL_OPT_2

1

0

MC8101_ABOV

N/A

MODEL_OPT_4

0

1

CM3231_CAPELLA

CM3231_CAPELLA

(TACT_KEY)

(GP3 Soft touch) (GP4 Soft touch)

Don’t remove R3014,
Not making P40 floated

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THERMAL

THERMAL

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

5V_HDMI_3

D1+_HDMI1

HDMI_HPD_4

DDC_SCL_3

C3210

0.1uF
16V

CK-_HDMI2

CK+_HDMI1

R3208 0

5V_HDMI_1

CK-_HDMI1

D1-_HDMI1

CK-_HDMI3

D2-_HDMI4

D1-_HDMI2

HDMI_HPD_1

D0-_HDMI4

CK+_HDMI2

D0+_HDMI3

C3220

1uF

HDMI_RX0+

D2-_HDMI1

HDMI_HPD_2

D2-_HDMI2

R3204
0

DDC_SDA_1

D2-_HDMI1

R3207 0

DDC_SCL_3

DDC_SDA_4

DDC_SDA_4

D2-_HDMI2

D0-_HDMI3

+5V_NORMAL

R3237 33

DDC_SCL_4

D2+_HDMI3

R3240
10

DDC_SCL_2

D0+_HDMI1

CEC_REMOTE

D1-_HDMI4

CEC_REMOTE

D0-_HDMI1

CK+_HDMI4

DDC_SDA_1

R3238
10

D2+_HDMI4

D0+_HDMI4

5V_HDMI_4

HDMI_RX2-

DDC_SDA_2

CK-_HDMI4

D1+_HDMI3

+5V_NORMAL

HDMI_CLK+

C3213

1uF

R3222
0

D0+_HDMI2

DDC_SDA_3

5V_HDMI_4

D0+_HDMI4

D1+_HDMI2

D1-_HDMI3

5V_HDMI_4

DDC_SDA_3

HDMI_HPD_3

DDC_SCL_1

HDMI_HPD_1

DDC_SCL_1

JK3201

RSD-105156-100

EAG62611201

14

NC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

D2-_HDMI3

R3210
0

C3205
10uF
10V

D1-_HDMI3

D0-_HDMI2

5V_HDMI_2

D1+_HDMI2

CEC_REMOTE

5V_HDMI_3

DDC_SCL_4

C3219

1uF

DDC_SDA_2

CK+_HDMI3

HDMI_RX1+

C3211

0.1uF

16V

HDMI_HPD_3

HDMI_HPD_4

5V_HDMI_1

CK+_HDMI3

CK+_HDMI4

D0-_HDMI2

D0+_HDMI1

D2+_HDMI1

HDMI_RX2+

DDC_SCL_3

DDC_SDA_4

I2C_SDA5

D2-_HDMI4

D0-_HDMI3

CK-_HDMI3

DDC_SCL_2

DDC_SCL_1

D1+_HDMI1

DDC_SCL_2

SPDIF_OUT_ARC

R3232
10

5V_HDMI_2

R3205
0

CK-_HDMI2

5V_HDMI_1

JK3203

RSD-105156-100

EAG62611201

14

NC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

GND

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

R3209
0

CEC_REMOTE

DDC_SCL_4

CK-_HDMI1

HDMI_HPD_2

D0+_HDMI3

DDC_SDA_1

D1-_HDMI2

+5V_NORMAL

5V_HDMI_2

D1-_HDMI1

JK3200

RSD-105156-100

EAG62611201

14

NC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

D2+_HDMI1

HDMI_RX0-

D2+_HDMI3

D2+_HDMI2

D1-_HDMI4

R3236 33

I2C_SCL5

D1+_HDMI3

D2-_HDMI3

5V_HDMI_3

JK3202

RSD-105156-100

EAG62611201

14

ARC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

R3223
0

CK+_HDMI2

C3214

1uF

+5V_NORMAL

D2+_HDMI2

DDC_SDA_3

D0-_HDMI1

D0+_HDMI2

HDMI_CLK-

CK+_HDMI1

R3231
10

D0-_HDMI4

HDMI_RX1-

CK-_HDMI4

D1+_HDMI4

DDC_SDA_2

D2+_HDMI4

D1+_HDMI4

MHL_DET

C3208

0.1uF

RGB_DDC_SCL

RGB_DDC_SDA

RGB_5V

C3221

1uF
10V

R3242
10

C3202
1uF

10V

MHL_DET

5V_HDMI_4

+5V_NORMAL

MHL_DET

R3201

62K

1/10W

OPT

HDMI_S/W_RESET

R3244

10K

C3222
10uF
10V

HDMI_INT

HDMI_WKUP

+5V_NORMAL

C3218
10uF
10V

C3215

0.1uF

16V

C3212

1uF
10V

C3209

0.1uF

16V

+3.5V_ST

C3204

0.1uF
16V

C3203
10uF
10V

C3200
10uF
10V

+3.3V_NORMAL

L3200
BLM18PG121SN1D

C3206

0.1uF
16V

C3207

0.1uF
16V

R3245

10K

1/16W

5%

R3206

220K

1/16W

5%

R3211 33

R3215 33

OPT

R3214 33

C3223

0.047uF
25V

R3228
47K

R3225
47K

R3217

47K

R3219
47K

R3218
47K

R3220
47K

R3229

47K

R3226
47K

R3241

5.1K
5%

1/16W

R3239

5.1K
5%

1/16W

R3233

5.1K
5%

1/16W

R3234

5.1K
5%

1/16W

L3201

BLM18PG121SN1D

C3217

0.1uF
16V

C3216
10uF
10V

L3202

L3203

C3224

0.1uF
16V

C3225

0.1uF

16V

R3216
10

IC3200

AZ1117BH-1.2TRE1

1

GND/ADJ

2

OUT

3

IN

C3201
10uF
10V

R3200

62K

1/10W

HDMI_WKUP

12V_EXT_PWR_DET

R3203

10K

+3.3V_NORMAL

R3202

10K

+3.3V_NORMAL

C3226

0.1uF
16V

OPT

D3206

30V

MBR230LSFT1G

+3.5V_ST

MHL_DET

R3212 33

R3213

5.1K
5%

1/16W

IC3202
TPS2554

3

IN_2

2

IN_1

4

ILIM_SEL

1

GND

5EN6

ILIM1

7

ILIM0

8

OUT_1

9

OUT_2

10

FAULT

11

[EP]

Q3201

MMBT3906(NXP)

E

B

C

Q3200
MMBT3904(NXP)

E

B

C

+3.5V_ST

R3243
1K

1/16W
5%

R3246

10K

D3203

A2CA1

D3202

A2CA1

D3204

A2

C

A1

D3200

A2CA1

D3201

A2CA1

D3205

A2CA1

R3247
10K

D3207

5.6V

IC3201

SII9587CNUC

FHD

1

R1XCN

2

R1XCP

3

R1X0N

4

R1X0P

5

R1X1N

6

R1X1P

7

R1X2N

8

R1X2P

9

AVDD12_1

10

VDD12_1

11

R3XCN

12

R3XCP

13

R3X0N

14

R3X0P

15

R3X1N

16

R3X1P

17

R3X2N

18

R3X2P

19

AVDD12_2

20

VDD33_1

21

R4XCN

22

R4XCP

23

R4X0N24R4X0P25R4X1N26R4X1P27R4X2N28R4X2P

29

VDD12_2

30

DSDA031DSCL0

32

CBUS_HPD0

33

R0PWR5V

34

DSDA135DSCL1

36

CBUS_HPD1

37

R1PWR5V

38

DSDA339DSCL3

40

CBUS_HPD3

41

R3PWR5V

42

DSDA443DSCL4

44

CBUS_HPD4

45

R4PWR5V

46

DSDA5[VGA]

47

DSCL5[VGA]

48

R5PWR5V[VGA]

49

SBVCC5

50

PWRMUX_OUT

51

LPSBV

52

WKUP

53

CD_SENSE0

54

CD_SENSE1

55

GPIO2

56

CD_SENSE3

57

CD-SENSE4

58

GPIO0

59

GPIO1

60

TPWR

61

RESET_N

62

CSDA

63

CSCL

64

INT

65

SPDIF_IN

66

RSVDL

67

VDD12_368ARC69TX2P70TX2N71TX1P72TX1N73TX0P74TX0N75TXCP76TXCN77TCVDD1278TPVDD1279R0XCN80R0XCP81R0X0N82R0X0P83R0X1N84R0X1P85R0X2N86R0X2P87AVDD12_388VDD33_2

89

[EP]GND

R3221

10

OPT

SPDIF_OUT_ARC

SPDIF_OUT

R3224 33

OPT

R3248

1K

OPT

R3249

3.9K

OPT

IC3201-*1

SII9587CNUC-3

UD

1

R1XCN

2

R1XCP

3

R1X0N

4

R1X0P

5

R1X1N

6

R1X1P

7

R1X2N

8

R1X2P

9

AVDD12_1

10

VDD12_1

11

R3XCN

12

R3XCP

13

R3X0N

14

R3X0P

15

R3X1N

16

R3X1P

17

R3X2N

18

R3X2P

19

AVDD12_2

20

VDD33_1

21

R4XCN

22

R4XCP

23

R4X0N24R4X0P25R4X1N26R4X1P27R4X2N28R4X2P

29

VDD12_2

30

DSDA031DSCL0

32

CBUS_HPD0

33

R0PWR5V

34

DSDA135DSCL1

36

CBUS_HPD1

37

R1PWR5V

38

DSDA339DSCL3

40

CBUS_HPD3

41

R3PWR5V

42

DSDA443DSCL4

44

CBUS_HPD4

45

R4PWR5V

46

DSDA5[VGA]

47

DSCL5[VGA]

48

R5PWR5V[VGA]

49

SBVCC5

50

PWRMUX_OUT

51

LPSBV

52

WKUP

53

CD_SENSE0

54

CD_SENSE1

55

GPIO2

56

CD_SENSE3

57

CD-SENSE4

58

GPIO0

59

GPIO1

60

TPWR

61

RESET_N

62

CSDA

63

CSCL

64

INT

65

SPDIF_IN

66

RSVDL

67

VDD12_368ARC69TX2P70TX2N71TX1P72TX1N73TX0P74TX0N75TXCP76TXCN77TCVDD1278TPVDD1279R0XCN80R0XCP81R0X0N82R0X0P83R0X1N84R0X1P85R0X2N86R0X2P87AVDD12_388VDD33_2

89

[EP]GND

HDMI 32

GP4

ARC

HDMI2

HDMI4 With MHL

HDMI1 With ARC

HDMI3

HDMI S/W OUTPUT

HDMI4

HDMI1

HDMI2

HDMI3

Limit 0.8A

Vout=0.8*(1+R1/R2)

Device Address : 0XB0

Limit 0.8A

2011.10.19

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

Fiber Optic

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

JK3601

KJA-PH-0-0177

3 DETECT

4 L

5 GND

1 R

+3.3V_NORMAL

R3641

2.7K

D3615

30V
OPT

C3633

18pF

50V

R3644 22

JK3602

2F11TC1-EM52-4F

C

GND

B

VCC

A

VIN

4

SHIELD

DSUB_B+

R3620

2.7K
OPT

+3.3V_NORMAL

DSUB_G+

RGB_DDC_SCL

DSUB_DET

R3645
10K

RGB_EDID

DSUB_R+

R3643 22

JK3603

SLIM-15F-D-2

112233445

5

6677889

91010

111112121313141415

15

16

16

R3646
10K

C3615

0.1uF
16V

RGB_DDC_SDA

SPDIF_OUT

R3615

33

C3634
18pF

50V

EDID_WP

PC_R_IN

+5V_NORMAL

DSUB_HSYNC

DSUB_VSYNC

D3616
30V
OPT

PC_L_IN

R3642

2.7K

RGB_5V

RGB_5V

IC3600

M24C02-RMN6T

RGB_EDID

3

E2

2

E1

4

VSS

1

E0

5

SDA

6

SCL

7

WC

8

VCC

SOC_TX

SOC_RX

D3620

MMBD6100

A2

C

A1

R3647
100

RGB_DEBUG

D3623

5.6V
OPT

D3611

5.6V
OPT

D3612

5.6V

OPT

D3600
20V
OPT

D3601
20V
OPT

D3622

5.5V

ADUC 5S 02 0R5L
OPT

D3621

5.5V

ADUC 5S 02 0R5L

OPT

D3613

5.5V

ADUC 5S 02 0R5L

OPT

D3611-*1

5.6V

ESD_MTK

D3612-*1

5.6V

ESD_MTK

D3613-*1

5.5V

ADUC 5S 02 0R5L

ESD_MTK

R3602
100

RGB_DEBUG

R3600

0

NON_RGB_DEBUG

R3601

0

NON_RGB_DEBUG

RGB PC

PC AUDIO

RGB/ PC AUDIO/ SPDIF

SPDIF OUT

36

JACK HIGH / MID

2011.11.21

Closed to JACK

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

R3700

10K

HP_OUT

HP_LOUT

+3.3V_NORMAL

JK3700

KJA-PH-0-0177

EAG61030001

HP_OUT

3DETECT

4L

5GND

1R

HP_DET

HP_ROUT

VA3700

5.6V

OPT

VA3700-*1

5.6V

ESD_MTK_HP_OUT

VA3700-*2

5.6V

ESD_LG1152_HP_OUT

37

JACK_COMMON

2011.11.21

ESD for LG1152

ESD for MTK

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

AV1_R_IN

C38020.1uF

RS232

C3803

0.1uF

RS232

COMP1_Pr

+3.5V_ST

AV1_L_IN

+3.3V_NORMAL

AV1_CVBS_DET

IR_OUT

R3814

4.7K
OPT

C3801

0.1uF

RS232

COMP1_DET

JK3803

SPG09-DB-009

RS232

1

2

3

4

5

6

7

8

9

10

JK3800

KJA-PH-1-0177

AV_JACK_BLACK

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

IC3800
MAX3232CDR

EAN41348201

RS232

3

C1-

2

V+

4

C2+

1

C1+

6

V-

5

C2-

7

DOUT2

8

RIN29ROUT2

10

DIN2

11

DIN1

12

ROUT1

13

RIN1

14

DOUT1

15

GND

16

VCC

R3811

4.7K
OPT

COMP1_Pb

C38000.1uF

RS232

JK3801

KJA-PH-1-0177

COMP_JACK_BLACK

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

AV1_CVBS_IN

COMP1_Y

R3821

100

RS232

+3.3V_NORMAL

R3820

100

RS232

+3.5V_ST

12V_COMMERCIAL_OUT

12V_COMMERCIAL_OUT

+3.5V_ST

R3834

10K

OPT_RS232

SOC_RX

+3.5V_ST

SOC_TX

P3800

12507WS-04L

UART_4PIN_STRAIGHT

1

2

3

4

5

R3810
10K

R3806

10K

D3803

5.6V
OPT

D3800

5.6V
OPT

D3804

20V
OPT

D3805
20V

OPT

D3801

5.6V

OPT

D3802

5.6V

OPT

D3801-*1

5.6V

ESD_MTK

D3802-*1

5.6V

ESD_MTK

D3800-*1

5.6V

ESD_MTK

D3803-*1

5.6V

ESD_MTK

D3803-*2

5.6V
ESD_LG1152

D3801-*2

5.6V

ESD_LG1152

D3802-*2

5.6V

ESD_LG1152

D3800-*2

5.6V

ESD_LG1152

JK3801-*1

KJA-PH-1-0177-2

COMP_JACK_GREEN

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

JK3800-*1

KJA-PH-1-0177-1

AV_JACK_YELLOW

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

P3801

12507WR-04L

UART_4PIN_ANGLE

1

2

3

4

5

RS232C

CVBS 1 PHONE JACK

COMPONENT 1 PHONE JACK

38

JACK_COMMON

2011.11.21

12V 1A FOR COMMERCIAL(RS-232C POWER)

FOR COMMERCIAL

ESD For MTK ESD For LG1152

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

IR

R4118
10K
5%

L4100

BLM18PG121SN1D

C4102

0.1uF

LED_B/GP4_LED_R

+3.5V_ST

+3.5V_ST

R4105

22

COMMERCIAL_IR

C4107
100pF

50V

IR_OUT

+3.5V_ST

R4117

10K

5%

C4100

0.1uF

R4102

10K

COMMERCIAL_IR

R4108
0

COMMERCIAL_IR_US

R4113
100

KEY1

KEY2

R4123
100

EEPROM_SCL

R4124
100

R4119

47K

COMMERCIAL_IR

R4111

10K

COMMERCIAL_IR_EU

R4114
100

+3.5V_ST

+3.5V_ST

C4104
1000pF
50V

+3.5V_ST

+3.5V_ST

EEPROM_SDA

R4104

47K

COMMERCIAL_IR

R4100
0

IR_BYPASS

R4125 1.5K

Q4100
MMBT3904(NXP)
COMMERCIAL_IR

E

B

C

Q4101

MMBT3904(NXP)

COMMERCIAL_IR

E

B

C

Q4102

MMBT3904(NXP)

COMMERCIAL_IR_EU

E

B

C

Q4104

MMBT3904(NXP)

COMMERCIAL_IR

E

B

C

R4101

1K

COMMERCIAL_IR

R4109

1K

COMMERCIAL_IR_EU

R4115

3.3K

COMMERCIAL_IR

R4103

3.3K

COMMERCIAL_IR

R4107

10K

IR_BYPASS

P4102

12507WR-10L

GP4_IR_10P

1

2

3

4

5

6

7

8

9

10

11

D4106

20V

ADUC 20S 02 010L

OPT

D4105

20V

ADUC 20S 02 010L

OPT

D4101

5.6V

AMOTECH CO., LTD.

OPT

D4100

5.6V

AMOTECH CO., LTD.

OPT

D4104

5.6V
AMOTECH CO., LTD.

OPT

D4106-*1

20V

ADUC 20S 02 010L

ESD_MTK

10pF

D4105-*1

20V

ADUC 20S 02 010L

ESD_MTK

10pF

D4100-*1

5.6V

ESD_MTK

ADMC 5M 02 200L

200pF

D4101-*1

5.6V

ESD_MTK

ADMC 5M 02 200L

200pF

D4104-*1

5.6V

ESD_MTK

ADMC 5M 02 200L

200pF

D4104-*2

5.6V

ESD_LG1152

ADMC 5M 02 200L

200pF

D4101-*2

5.6V

ESD_LG1152

ADMC 5M 02 200L

200pF

D4100-*2

5.6V

ESD_LG1152

ADMC 5M 02 200L

200pF

IR & KEY

RGB Sensor

COMMERCIAL

Zener Diode is

Soft Touch Micom D/L

close to wafer

41

IR / KEY

2011.11.21

COMMERCIAL

ESD for LG1152

ESD for MTK

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only