LG 84LM9600 Service manual

Internal Use Only

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

LED LCD TV

SERVICE MANUAL

CHASSIS : LA23J

MODEL : 84LM9600 84LM9600-UC

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67366707 (1210-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION .............................................................. 11

EXPLODED VIEW .................................................................................. 20

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental shorts of th e cir cuitry that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exp ose d metallic par t. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied LED LCD TV with (LA23J) chassis

2. Test condition

Each part is tested as below without special notice.

1)

Temperature : 25

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage : Standard input voltage
(220~240V@ 60Hz)

4) Specification and performance of each parts are followed
ea ch drawing and s pe cificatio n b y p art number in
accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to
the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : UL, CSA, CE, IEC specification

- EMC: FCC, ICES, CE, IEC specification

- Wireless : WirelessHD Specification (Option)

ºC

± 5 ºC (77±9 ºF), CST : 40±5

ºC

.

4. General Specification

No Item Specication Remark

1 Market 1) North America

2 Broadcasting System 1) ATSC / NTSC

3 Receiving System 1) VSB/64 & 256 QAM/ NTSC-M

4 Input Voltage AC 100 ~ 240V 50/60Hz

5 Available Channel 1) VHF : 02~13

2) UHF : 14~69

3) DTV : 02-69

4) CATV : 01~135

5) CADTV : 01~135

6 Screen Size 84inch Wide(3840 × 2160) 84LM9600-UA

7 Aspect Ratio 16:9

8 Tuning System FS

9 LCD Module LC840EQD-SEF1(FPR CELL) LGD 84LM9600-UA

10 Operating Environment 1) Temp : 0 ~ 40 deg

2) Humidity : ~ 80 %

11 Storage Environment 1) Temp : -20 ~ 60 deg

2) Humidity : ~ 85 %

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. External input format

5.1. 2D mode

5.1.1. Component input (Y, CB/PB, CR/PR)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1. 720*480 15.73 60.00 13.5135 SDTV ,DVD 480I

2. 720*480 15.73 59.94 13.50 SDTV ,DVD 480I

3. 720*480 31.50 60.00 27.027 SDTV 480P

4. 720*480 31.47 59.94 27.00 SDTV 480P

5. 1280*720 45.00 60.00 74.25 HDTV 720P

6. 1280*720 44.96 59.94 74.176 HDTV 720P

7. 1920*1080 33.75 60.00 74.25 HDTV 1080I

8. 1920*1080 33.72 59.94 74.176 HDTV 1080I

9. 1920*1080 67.50 60.00 148.50 HDTV 1080P

10. 1920*1080 67.432 59.94 148.352 HDTV 1080P

11. 1920*1080 27.00 24.00 74.25 HDTV 1080P

12. 1920*1080 26.97 23.94 74.176 HDTV 1080P

13. 1920*1080 33.75 30.00 74.25 HDTV 1080P

14. 1920*1080 33.71 29.97 74.176 HDTV 1080P

5.1.2. RGB Input (PC)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

PC

1 640*350 31.468 70.09 25.17 EGA DDC

2 720*400 31.469 70.08 28.32 DOS Х

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 80.00 VESA O

7 1360*768 47.712 60.015 85.50 VESA (WXGA) X

8 1920*1080 67.5 60 148.5 WUXGA(Reduced Blanking) O

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.1.3. HDMI Input 1 (PC/DTV)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

HDMI-PC

1 640*350 31.468 70.09 25.17 EGA Х

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 80.00 VESA O

7 1280*1024 63.981 60.020 108.00 VESA (SXGA) O

8 1360*768 47.712 60.015 85.50 VESA (WXGA) O

9 1920*1080 67.5 60 148.5 WUXGA(Reduced Blanking) O

10 3840*2160 67.5 30.00 297.00 UD

11 3840*2160 56.25 25.00 297.00 UD

12 3840*2160 54.0 24.00 297.00 UD

HDMI-DTV

1 720*480 31.47 60 27.027 SDTV 480P

2 720*480 31.47 59.94 27.00 SDTV 480P

3 1280*720 45.00 60.00 74.25 HDTV 720P

4 1280*720 44.96 59.94 74.176 HDTV 720P

5 1920*1080 33.75 60.00 74.25 HDTV 1080I

6 1920*1080 33.72 59.94 74.176 HDTV 1080I

7 1920*1080 67.500 60 148.50 HDTV 1080P

8 1920*1080 67.432 59.939 148.352 HDTV 1080P

9 1920*1080 27.000 24.000 74.25 HDTV 1080P

10 1920*1080 26.97 23.976 74.176 HDTV 1080P

11 1920*1080 33.75 30.000 74.25 HDTV 1080P

12 1920*1080 33.71 29.97 74.176 HDTV 1080P

13 3840*2160 67.5 30.00 297.00 UDTV 2160P

14 3840*2160 56.25 25.00 297.00 UDTV 2160P

15 3840*2160 54.0 24.00 297.00 UDTV 2160P

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2. 3D mode

5.2.1. RF Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed Remark

1 1920*1080 45.00 60 74.25 HDTV 1080I Side by Side, Top & Bottom

2 1280*720 45.00 60 74.25 HDTV 720P Side by Side, Top & Bottom

5.2.2. HDMI Input(1.3a)- DTV (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Remark

1 1280*720p 45.00 60.00 74.25 Side by Side (Half), Top & Bottom,

Single Frame Sequential

2 1920*1080i 33.75 60.00 74.25 Side by Side (Half), Top & Bottom

3 1920*1080p 67.50 60.00 148.50 Side by Side (Half), Top & Bottom

Checkerboard, Single Frame Sequential

Row Interleaving, Column Interleaving

4 1920*1080p 27.00 24.000 74.25 Side by Side (Half), Top & Bottom

Checkerboard

5 1920*1080p 33.75 30.000 74.25 Side by Side (Half), Top & Bottom

Checkerboard

Only for training and service purposes

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.3. HDMI Input(1.4b) - (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1280*720p 89.91 / 90.00 59.94 / 60.00 148.35 / 148.50 Mandatory Frame Packing,

2 1280*720p 44.96 / 45.00 59.94 / 60.00 74.18 / 74.25 Mandatory Top & Bottom

3 1920*1080i 33.72 / 33.75 59.94 / 60.00 74.18 / 74.25 Mandatory Side by Side (Half)

4 1920*1080p 43.94 / 54.00 23.97 / 24.00 148.35 / 148.50 Mandatory Frame Packing,

5 1920*1080p 26.97 / 27.00 23.97 / 24.00 74.18 / 74.25 Mandatory Top & Bottom

6 1280*720p 44.96 / 45.00 59.94 / 60.00 74.18 / 74.25 Primary Side by Side (Half)

7 1920*1080i 67.432 / 67.50 59.94 / 60.00 148.35 / 148.50 Primary Frame Packing

8 1920*1080p 67.43 / 67.50 59.94 / 60.00 148.35 / 148.50 Primary Top & Bottom

9 1920*1080p 26.97 / 27.00 23.97 / 24.00 74.18 / 74.25 Primary Side by Side (Half)

10 1920*1080p 67.432 / 67.50 29.976 / 30.00 148.35 / 148.50 Primary Frame Packing,

11 1920*1080p 33.716 / 33.75 29.976 / 30.00 74.18 / 74.25 Primary Top & Bottom

12 1920*1080i 33.72 / 33.75 59.94 / 60.00 74.18 / 74.25 Secondary Top & Bottom

13 1920*1080p 67.43 / 67.50 59.94 / 60.00 148.35 / 148.50 Secondary Side by Side (Half)

14 1920*1080p 33.716 / 33.75 29.976 / 30.00 74.18 / 74.25 Secondary Side by Side (Half)

15 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 Secondary (16:9) Frame Packing,

16 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (16:9) Top & Bottom

17 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (16:9) Side by Side (Half)

18 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 Secondary (4:3) Frame Packing,

19 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (4:3) Top & Bottom

20 720*480p 31.469 / 31.50 59.94 / 60.00 27.00 / 27.027 Secondary (4:3) Side by Side (Half)

21 640*480p 62.938 / 63.00 59.94 / 60.00 50.35 / 50.40 Secondary Frame Packing,

22 640*480p 31.469 / 31.50 59.94 / 60.00 25.175 / 25.20 Secondary Top & Bottom

23 640*480p 31.469 / 31.50 59.94 / 60.00 25.175 / 25.20 Secondary Side by Side (Half)

24 1280*720p 89.91 / 90.00 59.94 / 60.00 148.35 / 148.50 Line Alternative

25 1280*720p 44.96 / 45.00 59.94 / 60.00 148.35 / 148.50 Side by Side (Full)

26 1920*1080i 67.432 / 67.50 59.94 / 60.00 148.35 / 148.50 Field Alternative

27 1920*1080i 33.72 / 33.75 59.94 / 60.00 148.35 / 148.50 Side by Side (Full)

28 1920*1080p 43.94 / 54.00 23.97 / 24.000 148.35 / 148.50 Line Alternative

29 1920*1080p 26.97 / 27.00 23.97 / 24.000 148.35 / 148.50 Side by Side (Full)

30 1920*1080p 67.432 / 67.50 29.976 / 30.00 148.35 / 148.50 Line Alternative

31 1920*1080p 33.716 / 33.75 29.976 / 30.00 148.35 / 148.50 Side by Side (Full)

32 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 16:9 Line Alternative

33 720*480p 31.469 / 31.50 59.94 / 60.00 54.00 / 54.054 16:9 Side by Side (Full)

34 720*480p 62.938 / 63.00 59.94 / 60.00 54.00 / 54.054 4:3 Line Alternative

35 720*480p 31.469 / 31.50 59.94 / 60.00 54.00 / 54.054 4:3 Side by Side (Full)

36 640*480p 62.938 / 63.00 59.94 / 60.00 50.35 / 50.40 Line Alternative

37 640*480p 31.469 / 31.50 59.94 / 60.00 50.35 / 50.40 Side by Side (Full)

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.4. HDMI-PC Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Remark

1 1024*768 48.363 60.004 65.000 Side by Side (Half), Top & Bottom

2 1360*768 47.712 60.015 85.500 Side by Side (Half), Top & Bottom

3 1920*1080 67.50 60.00 148.50 Side by Side (Half), Top & Bottom

Checkerboard, Single Frame Sequential

Row Interleaving, Column Interleaving

5.2.5. RGB-PC Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Remark

1 1920*1080 67.5 60.000 148.5 Side by Side (Half), Top & Bottom

2 1360*768 47.712 60.015 85.50 Side by Side (Half), Top & Bottom

3 1024*768 48.363 60.00 65.00 Side by Side (Half), Top & Bottom

5.2.6. USB Input (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed Remark

1 1920*1080 33.75 30.000 74.25 HDTV 1080p Side by Side (Half), Top & Bottom,

Checkerboard, MPO (Photo)

5.2.7. USB Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed Remark

1 1920*1080 33.75 30.000 74.25 HDTV 1080p Side by Side (Half), Top & Bottom

Checkerboard, Single Frame Sequential,
Row Interleaving, Column Interleaving
(Photo : Side by Side, Top & Bottom)

Only for training and service purposes

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.8. DLNA Input(3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed Remark

1 1920*1080 33.75 30.000 74.25 HDTV 1080p Side by Side (Half), Top & Bottom,

Checkerboard, MPO (Photo)

5.2.9. DLNA Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed Remark

1 1920*1080 33.75 30.000 74.25 HDTV 1080p Side by Side (Half), Top & Bottom

Checkerboard, Single Frame Sequential,
Row Interleaving, Column Interleaving
(Photo : Side by Side, Top & Bottom)

5.2.10. Component Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1280*720 44.96 59.94 74.176 HDTV 720P Side by Side,

Top & Bottom

2 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side,

Top & Bottom

3 1920*1080 33.72 59.94 74.176 HDTV 1080I Side by Side,

Top & Bottom

4 1920*1080 67.500 60 148.50 HDTV 1080P Side by Side,

Top & Bottom

5 1920*1080 67.432 59.94 148.352 HDTV 1080P Side by Side,

Top & Bottom

6 1920*1080 27.000 24.000 74.25 HDTV 1080P Side by Side,

Top & Bottom

7 1920*1080 26.97 23.976 74.176 HDTV 1080P Side by Side,

Top & Bottom

8 1920*1080 33.75 30.000 74.25 HDTV 1080P Side by Side,

Top & Bottom

9 1920*1080 33.71 29.97 74.176 HDTV 1080P Side by Side,

Top & Bottom

Only for training and service purposes

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to LA23J Chassis applied LCD TV all
models manufactured in TV factory

2. Specification

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation

transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 ±5 °C of temperature and 65±10% of relative humidity if

there is no specific designation.
(4) The input voltage of the receiver must keep 100~240V,

50/60Hz.
(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15 °C
In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours

In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above
15°C for 3 hours.

[Caution]
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong.
Digital pattern 13ch and/or Cross hatch pattern 09ch), there
can some afterimage in the black level area

3.3. Automatic Adjustment

3.3.1. Overview

ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation

3.3.2. Equipment & Condition

1) Jig (RS-232C protocol)

2) Inner Pattern

- Resolution : 1080p (Inner Pattern)

- Resolution : 1024*768 RGB (Inner Pattern)

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7±0.1 Vp-p

3.3.3 Adjustment

3.3.3.1. Adjustment method

▪ Using RS-232, adjust items listed in 3.1 in the other shown in

“4.1.3.3”

3.3.3.2. Adj. protocol

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change xb 00 40

xb 00 60

Begin adj. ad 00 10

Return adj. result OKx (Case of Success)

Read adj. data (main)

ad 00 20

b 00 OK40x (Adjust 480i Comp1 )
b 00 OK60x (Adjust 1024*768 RGB)

NGx (Case of Fail)

(main)
000000000000000000000000007c007b006dx

3. Adjustment items

3.1. Final assembly adjustment

▪ EDID/DDC check
▪ White Balance adjustment
▪ ADC Adjustment check
▪ RS-232C functionality check
▪ Factory Option setting per destination
▪ Ship-out mode setting (In-Stop)

3.2. Etc

▪ Ship-out mode
▪ Tool option menu
▪ USB Download(S/W Update, Option, Service only)

(sub )
ad 00 21

Conrm adj. ad 00 99 NG 03 00x (Fail)

End adj. aa 00 90 a 00 OK90x

3.3.3.3 Adj. order

▪ aa 00 00 [Enter ADC adj. mode]
▪ xb 00 40 [Change input source to Component1(480i)]
▪ ad 00 10 [Adjust 480i Comp1]
▪ xb 00 60 [Change input source to RGB(1024*768)]
▪ ad 00 10 [Adjust 1024*768 RGB]
▪ ad 00 90 End adj.

Ref) ADC adj. RS232C Protocol_Ver1.0

(Sub)
000000070000000000000000007c00830077x

NG 03 01x (Fail)
NG 03 02x (Fail)
OK 03 03x (Success)

Only for training and service purposes

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4. Manual Adjustment

4.1. MAC Address, ESN Key and Widevine
Key download

4.1.1. Equipment & Condition

1) Play file: keydownload.exe

4.1.2. Communication Port connection

1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

4.1.3. Download process

1) Select the download items.

2) Mode check: Online Only

3) Check the test process

- U S, Canad a m ode ls : DET EC T -> M AC _WR IT E ->
WIDEVINE_WRITE

- Korea, Me xico models: DE TECT -> MA C_WRITE ->
WIDEVINE_WRITE

4) Play : START

5) Check of result: Ready, Test, OK or NG

6) Printer out (MAC Address Label)

4.1.4. Communication Port connection

1) Connect: PCBA Jig -> RS-232C Port == PC -> RS-232C

Port

4.1.5. Download

1) US, Canada, Mexico models (12Y LCD TV + MAC +
Widevine + ESN Key)

2) Korea, Mexico models (11Y LCD TV + MAC + Widevine
Only)

Only for training and service purposes

4.1.6. Inspection

- In INSTART menu, check these keys.

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.2. PING Test

* LAN card can be verified by using PING test

4.2.1. Adjustment Method(Board)

(1) Connect LAN to the board and power on.
(Default IP can be set to automatic setting. When power

ON, IP can be automatically be achieved from the router)
(2) Press ADJ key in the adjustment remote control.
(3) Check Network status by pressing 13. ACAP PING TEST

in EZ ADJUST. If it operates properly, it will show “Network
is operating properly.” If it does not, it will show “Network is
not working properly.”

4.2.2. Adjustment Method(Manufacturer)

(4) Connect the PC with PING Test program installed and the

LAN port of the SET via Cross LAN Cable. (The IP setting
of the PC has to be 12.12.2.3)

(5) After the PING Test program has been executed, check the

program setting. (IP of the set will be 12.12.2.2. Double
check the setting. Do not check the Modem because it will
not be used.)

(6) Press the Power Only Key in Adjustment remote control.

(IP of the set will be set)

(7) Upon pressing “RUN” in the program, it will show “OK” or

“NG” according to the test result.

● After all the adjustments, to disable the IP setting, press

INSTOP key.

4.3 EDID Download

4.3.1 Overview

▪ It is a VESA regulation. A PC or a MNT will display an optimal

resolution through information sharing without any necessity
of user input. It is a realization of “Plug and Play”.

4.3.2 Equipment

▪ Since embedded EDID data is used, EDID download JIG,

HDMI cable and D-sub cable are not need.

▪ Adjust remocon

4.3.3 Download method

1) Press Adj. key on the Adj. R/C,

2) Select EDID D/L menu.

3) By pressing Enter key, EDID download will begin

4) If Download is successful, OK is display, but If Download is
failure, NG is displayed.

5) If Download is failure, Re-try downloads.

※ Caution) When EDID Download, must remove RGB/HDMI

Cable.

4.3.3.1. EDID DATA
# HDMI 1(C/S : 43 2C)
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

Only for training and service purposes

- 13 -

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 2C

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

# HDMI 2(C/S : 43 1C)
EDID Block 0, Bytes 0-127 [00H-7FH]

# HDMI 4(C/S : 43 FC)
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 3D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 1C

# HDMI 3(C/S : 43 0C
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 | 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 5D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 FC

# RGB(C/S : 5C)
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 5C

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

----------------------------------------------------------------------------------------­ 0 | 02 03 2E F1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0C 00 10 00 B8 4D 20 C0 0E 01 4F 00 FE
20 | 08 10 06 10 18 10 28 10 38 10 E3 05 03 01 02 3A
30 | 80 18 71 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E
40 | 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A 00 00
50 | 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 A0 5A
60 | 00 00 00 1E 26 36 80 A0 70 38 1F 40 30 20 25 00
70 | A0 5A 00 00 00 1A 00 00 00 00 00 00 00 00 00 0C

Only for training and service purposes

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.4. White Balance Adjustment

If TV internal pattern is used, not needed

4.4.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel’s W/B deviation
(2) How-it-works: When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.

(3) Adj. condition: normal temperature

- Surrounding Temperature: 25±5 °C

- Warm-up time: About 5 Min

- Surrounding Humidity: 20% ~ 80%

4.4.2. Equipment

(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:

CH14)

(2) Adj. Computer (During auto adj., RS-232C protocol is

needed)
(3) Adjust Remocon
(4) Vi deo Sig nal Generator MSP G-925F 720p/204 -Gray

(Model: 217, Pattern: 49)
※ Color Analyzer Matrix should be calibrated using CS-1000

4.4.3. Equipment connection

Color Analyzer

Probe

RS-232C

※

Signal Source

※

Pattern Generator

4.4.4. Adjustment Command (Protocol)

(1) RS-232C Command used during auto-adj.

RS-232C COMMAND

CMD DATA ID

Wb 00 00 Begin White Balance adj.

Wb 00 ff End White Balance adj.

(internal pattern disappears )

(2) Adjustment Map

Adj. item Command

(lower caseASCII)

CMD1 CMD2 MIN MAX

Cool R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

Medium R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

Warm R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

Explanation

Data Range
(Hex.)

RS-232C

Computer

RS-232C

4.4.5. Adj. method

4.4.5.1. Auto adj. method
(1) Set TV in ADJ mode using P-ONLY key (or POWER ON

key)

(2) Place optical probe on the center of the display

- It need to check probe condition of zero calibration before

adjustment.
(3) Connect RS-232C Cable
(4) Select mode in ADJ Program and begin a adjustment.
(5) When WB adjustment is completed with OK message,

check adjustment status of pre-set mode (Cool, Medium,

Warm)
(6) Remove probe and RS-232C cable.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need

4.4.5.2. Manual adj. method
(1) Set TV in Adj. mode using POWER ON
(2) Zero Calibrate the probe of Color Analyzer, then place it on

the center of LCD module within 10cm of the surface..

(3) Press ADJ key -> EZ adjust using adj. R/C -> 9. White-

Balance then press the cursor to the right (KEY►). When
KEY(►) is pressed 216 Gray interna l pattern will be

displayed.

(4) To Adjust Cool Mode, Change the G gain over 172 (default

data) and change the others (R/B Gain). Detail Adjust
method refer to “Case Cool” described below

(5) Adjust two modes (Medium / Warm) Fix the one of R/G/B

gain to 192 (default data) and decrease the others.

※ CASE Cool
First adjust the coordinate far away from the target value(x,
y).B
(1) x, y > target
(2) x, y < target
(3) x > target , y < target
(4) x < target , y >target
Every 4 case have to fit y value by adjusting B Gain and then
fit x value by adjusting R-Gain.
In this case, increasing/decreasing of B Gain and R Gain can
be adjusted.

How to adjust
(1) Adjust G gain over 172 and then adjust R Gain and B

Gain(In Case of Mostly Blue Gain Saturation )

(2) When B Gain > 255, Adjust the G Gain under 172 and

Readjust

※ CASE Medium / Warm
First adjust the coordinate far away from the target value(x, y).
(1) x, y > target
i) Decrease the R, G.
(2) x, y< target
i) First decrease the B gain,
ii) Decrease the one of the others.
(3) x > target , y < target
i) First decrease B, so make y a little more than the target.
ii) Adjust x value by decreasing the R
(4) x < target , y > target
i) First decrease B, so make x a little more than the target.
ii) Adjust x value by decreasing the G

Only for training and service purposes

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 6.White Balance, you can select one of 2 Test-pattern:
ON, OFF. Default is inner (ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.

▪ Adj. condition and cautionary items

(1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to isolate

adj. area into dark surrounding.

(2) Probe location: Color Analyzer (CA-210) probe should be

within 10cm and perpendicular of the module surface (80°~
100°)

(3) Aging time

- After Aging Start, Keep the Po wer ON status during 5
Minutes.

- In case of LCD, Back-light on should be checked using no

signal or Full-white pattern.

4.4.6. Reference (White Balance Adj. coordinate and
color temperature)

▪ Luminance: 204 Gray
▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Cool 0.269 0.273 13,000K 0.0000

Medium 0.285 0.293 9,300K 0.0000

Warm 0.313 0.329 6,500K +0.0030

▪

Standard color coordinate and temperature using CA-210(CH 18)

Mode

Cool 0.269±0.002 0.273±0.002 13,000K 0.0000

Medium 0.285±0.002 0.293±0.002 9,300K 0.0000

Warm 0.313±0.002 0.329±0.002 6,500K +0.0030

Coordinate

X Y

Coordinate

X Y

Temp △uv

Temp △uv

4.4.7 THX Adjustment (For US Models)

For THX models, White Balance 4 point automatic control can
be done through the below steps. (Warm axis)
(1) 100 IRE White Balance Adjustment done.
(2) Control Backlight so the Maximum brightness
*In case of 100 IRE adjustment, backlight target value is
125cd/m2.
(3) 4 Point gamma and W/B adjustment done.
* With the controlled maximum brightness, adjust the Gamma

2.2 (60, 40, and 20 IRE / do not adjust at 80 IRE)

*For 10 IRE, set R, G, B gain to 0, 0, and 0, respectively.

4.5. Option selection per country

4.5.1. Method

(1) Press ADJ key on the Adj. R/C, and then select Country

Group Menu.

(2) Depending on destination, select KR or US, then on the

lower Country option, select US, CA, MX. Selection is done
using +, - KEY

4.6. Tool Option Inspection

▪ Method: Press Adj. key on the Adj. R/C, then select Tool option.

Model Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6 Tool 7

84LM9600-UA

33005 41026 29485 20527 23055 1302 63115

4.7. Local Dimming Inspection (Optional)

4.7.1. Edge models with local dimming

(1) Press ‘TILT” key of the Adj. R/C and check movin g

patterns. The white window patterns moves from center-left
to center-right. If local dimming function does not work, the
top and bottom edge LED area shows not blinking

4.4.6.1 ALELF&EDGE LED&IOL White balance table

▪ Edge LED module change color coordinate because of aging time
▪

apply under the color coordinate table, for compensated aging time

Edge (LM860X)

Aging time

GP4

1 0-2 283 293 299 313 320 339

2 3-5 282 291 298 311 319 337

3 6-9 281 290 297 310 318 336

4 10-19 279 289 295 309 316 335

5 20-35 277 284 293 304 314 330

6 36-49 274 279 290 299 311 325

7 50-79 271 277 287 297 308 323

8 80-149 270 274 286 294 307 320

9 Over 150 269 273 285 293 306 319

Only for training and service purposes

(Min)

Cool Medium Warm

X Y X Y X Y

269 273 285 293 313 329

4.8. Ship-out mode check (In-stop)

▪ After final inspection, press In-Stop key of the Adj. R/C and

check that the unit goes to Stand-by mode.

▪ After final inspection, Always turn on the Mechanical S/W.

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.9. WIFI MAC ADDRESS CHECK

a. Using RS232

Command Set ACK

Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]

b. check the menu on in-start

6. EYE-Q Operation check

Step 1) Turn on the TV..
Step 2) Press ' EY E button' o n t he adjustm en t remote -

controller.

Step 3) Cover 'Eye Q sensor' on the front of set with your

hands, hold it for 6 seconds.

Step 4) Check "the Sensor Data" on the screen, make certain

that Data is below 10. If Data isn’t below 10 in 6
seconds, Eye Q sensor would be bad. You should
change Eye Q sensor.

Step 5) Uncover your hands from Eye Q sensor, hold it for 6

seconds.

Step 6) Check "Back Light(xxx)" on the screen, check data

increase . You should change Eye Q sensor.

Note that there are Wi-Fi MAC and MAC address.
Wi-Fi MAC is used for wireless network and MAC address is used
for wired network

5. GND and Internal Pressure check

5.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord; Antenna cable and A/V
arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER (GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically.

(Remove CORD, A/V form AV JACK BOX)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.

<Step 2>

<Step 4>

7. Magic Motion Remote Control Inspection

- Requ ired Ins trument s: Ins pection RF-re mote con trol,
Inspection IR-KEY-CODE remote control.

- Prior to the test, AA battery for the RF-remote control should
be adequate.

(Change the battery for each LOT is recommended)

- Test procedures

(1) Press the ‘START’ key on the controller to pair with the set.
(2) Press the ‘OK’ key in the controller and check whether the

cursor appears on the set.

(3) Press ‘Vol+ (STOP)’ key to de-pair with the set.

<Step 3>

<Step 5>

<Step 6>

5.2. Checkpoint

(1) Test voltage

- GND: 1.5KV/min at 100mA

- SIGNAL: 3KV/min at 100mA
(2) TEST time: 1 second
(3) TEST POINT

- GND Test = POWER CORD GND and SIGNAL CABLE
GND.

- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.

(4) LEAKAGE CURRENT: At 0.5mArms

Only for training and service purposes

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

8. 3D function test

8.1 Test equipment

(1) Pattern Generator MSHG-600 or MSPG-6100 (HDMI 1.4

support)

(2) Pattern: HDMI mode (model No. 872, pattern No. 83)

9. HDMI ARC Function Inspection

9.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

8.2 Test method

(1) Input 3D test signal as Fig.1.

(2) Press ‘OK” key as a 3D input OSD is shown.
(3) Check pattern as Fig2 without 3D glasses. (3D mode

without 3D glasses)

Fig.2

9.2 Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

(2) Check the sound from the TV Set

(3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

<OK in 3D mode without 3D glasses>

Only for training and service purposes

- 18 -

* Remark: Inspect in Power Only Mode and check SW version

in a master equipment

.

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

10. USB S/W Download
(optional, Service only)

(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is lower

than that of TV set, it didn’t work. Otherwise USB data is

automatically detected.
(3) Show the message “Copying files from memory”
(5) Updating Completed, The TV will restart automatically
(6) If your TV is turned on, check your updated version and

Tool option.

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel
recover. If all channel data is cleared, you didn’t have a DTV/
ATV test on production line.

* After downloading, TOOL OPTION setting is needed again.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)

(4) Updating is staring.

(5) Updating Completed, The TV will restart automatically
(6) If your TV is turned on, check your updated version and

Tool option.

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel
recover. If all channel data is cleared, you didn’t have a DTV/
ATV test on production line.

* After downloading, TOOL OPTION setting is needed again.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)

Only for training and service purposes

- 19 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essenti al that these special safet y parts shoul d be replac ed with the same compo nents as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

320

400

540

541

531

532

700

710

570

121

810

420

910

900

410

560

120

122

LV1

200D

200

300

201D

200T

830

820

530

510

310

580

500

A10

A9

AG1

A22

A2

Set + Stand

Stand Base

+ Body

Only for training and service purposes

- 20 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

System Configuration

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

NVRAM

Clock for LG1152

MAIN Clock(24Mhz)

C100

8pF

50V

X-TAL_1

GND_1

1

2

X101

24MHz

4

3

C101

8pF

50V

GND_2

X-TAL_2

PLL SET[1:0] ==> Internal Pull-UP. N.C is high
00 : CPU clock(1056Mhz), Main0,1/2 DDR (792/792 Mhz)
01 : CPU clock(792Mhz), Main0,1/2 DDR (672/792 Mhz)
10 : CPU clock(1152Mhz), Main0,1/2 DDR (792/672 Mhz)
11 : CPU clock(984Mhz), Main0,1/2 DDR (792/792 Mhz)

BOOT MODE
"11" or "01" : NOR
"10" : eMMC
"00" : NAND

OPT

R102 22

R103 22

OPT

PLLSET1

PLLSET0

R112

XIN_MAIN

1M

XO_MAIN

JTAG I/F FOR MAIN

+3.3V_NORMAL

+3.3V_NORMAL

4.7K

R187

BOOT_MODE1

4.7K

R185

OPT

BOOT_MODE1

+3.3V_NORMAL

4.7K

R188

OPT

4.7K

R186

BOOT_MODE0

TRST_N0

TDI0
TDO0
TMS0
TCK0

SOC_RESET

OPT

OPT

R131 10K

R132 10K

OPT

OPT

R133 10K

R134 10K

BOOT_MODE0

+3.3V_NORMAL

HW_OPT_0

HW_OPT_1

HW_OPT_2

HW_OPT_3

HW_OPT_4

HW_OPT_5

HW_OPT_6

HW_OPT_7

HW_OPT_8

HW_OPT_9

HW_OPT_10

HP_AMP_MUTE

BackEnd 1

BackEnd 2

Pannel Resol

OPTIC I/F

3D Depth IC

DDR Size

CP BOX

FrontEnd 1

FrontEnd 2

OPT

22

R117

10K

URSA5

R110

FRC_EXTERNAL

R100 10K

10K

FRC3

FRC_INTERNAL

R107 10K

R111

FHD

OPTIC

R124 10K

UD

NON_OPTIC

R125 10K

R138 10K

R139 10K

OPT

3D_DEPTH

R140 10K

R145 10K

1GByte

R141 10K

R146 10K

NON_3D DEPTH

CP_BOX

R152 10K

R147 10K

DVB_T2_TUNER

NON_CP_BOX

R153 10K

R148 10K

NON_DVB_T2_TUNER

DVB_S_TUNER

R156 10K

R154 10K

DVB_C2_TUNER

R158 10K

R155 10K

NON_DVB_S_TUNER

NON_DVB_C2_TUNER

ZORAN_FRC

R121 10K

NOT_ZORAN_FRC

R126 10K

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

MODEL_OPT_7

MODEL_OPT_8

MODEL_OPT_9

MODEL_OPT_10

Zoran FRC
(For UD)

MODEL OPTION 8 is just for CP Box
It should not be appiled at MP

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

IC102

R1EX24256BSAS0A

A0

1

A1

A2

VSS

8

2

7

A0’h

3

6

4

5

Place to LVDS Wafer

FRC_RESET

I2C_SCL1

SoC
internal

NO_FRC

FRC

0

0 1

1

HIGH

FHD

OPTIC

3D DEPTH

3D_Depth_IC

DDR Reserved

CP BOX

Enable

T2 Tuner

Support

S Tuner

Support

Support

C2 Tuner

Support

C111

0.1uF

VCC

WP

SCL

SDA

R151 22

4.7K

R113

R160 22

R162 22

MHL_DET

HDMI_INT

LG FRC3

10

0

LOW

UD

NON_OPTIC

NON_3D_Depth_IC

DDR_Default

Disable

Not Support

Not Support

Not Support

Not Support

+3.3V_NORMAL

Write Protection

- Low : Normal Operation

- High : Write Protection

R143

OPT

22

10K

FRC3

R170

SOC_RX

SOC_TX

2N7002K

URSA5

1

R142

OPT

22

FRC3_RESET

3D_DEPTH_RESET

I2C_BE_SDA1I2C_SDA1

I2C_BE_SCL1

LOCAL_DIM_EN

+5V_NORMAL

G

D

Q100

2N7002K

+5V_NORMAL

G

S

D

Q105

OPT

+3.3V_NORMAL

R178

2.2K

I2C_SCL5

I2C_SDA5

I2C_SCL3
I2C_SDA3

+3.3V_NORMAL

S

+3.3V_NORMAL

R203

100K

R180

3.3K

R179

2.2K

OPT

R181

100K

2N7002K

3.3K

R202

G

S

D

Q103

I2C PULL UP

R182

2.2K

R195

2.2K

SOC_RESET

BOOT_MODE1
BOOT_MODE0

ERROR_OUT

/USB_OCD2
/USB_OCD3

M_REMOTE_RX
M_REMOTE_TX

IRB_SPI_MISO
IRB_SPI_MOSI

IRB_SPI_CK
IRB_SPI_SS

AV1_CVBS_DET

DTV_ATV_SELECT

R196

3.3K

R197

3.3K

XIN_MAIN

XO_MAIN

TRST_N0

TMS0
TCK0
TDI0
TDO0

PLLSET1
PLLSET0

EPHY_INT

UART1_RX
UART1_TX

R198

3.3K

I2C_SCL1
I2C_SDA1
I2C_SCL2
I2C_SDA2
I2C_SCL3
I2C_SDA3
I2C_SCL4
I2C_SDA4
I2C_SCL5
I2C_SDA5
I2C_SCL6
I2C_SDA6

R199

3.3K

R150 22

R101 22

R184

R183

1.2K

R104 560

1%

BOOT_MODE1
BOOT_MODE0

1.2K
I2C_SDA1
I2C_SCL1
I2C_SDA2
I2C_SCL2
I2C_SDA3
I2C_SCL3
I2C_SDA4
I2C_SCL4

I2C_SDA5
I2C_SCL5

I2C_SDA6
I2C_SCL6

A22

XIN_MAIN

B22

XO_MAIN

AB16

OPM1

AB17

OPM0

AE3

PORES_N

V23

TRST_N0

U25

TMS0

V25

TCK0

V24

TDI0

U24

TDO0

Y22

TRST_N1

AA22

TMS1

AB20

TCK1

AB21

TDI1

W22

TDO1

AB9

PLLSET1

AB8

PLLSET0

AB15

BOOT_MODE1

AB14

BOOT_MODE0

Y23

EXT_INTR3/GPIO48

W25

EXT_INTR2/GPIO63

W24

EXT_INTR1/GPIO62

W23

EXT_INTR0/GPIO61

Y5

UART0_RX/GPIO49

W6

UART0_TX/GPIO50

AA6

UART1_RX

Y6

UART1_TX

AB5

UART2_RX

AA5

UART2_TX

AB23

SPI_DI0/GPIO39

AB24

SPI_DO0/GPIO38

AA25

SPI_SCLK0/GPIO37

AB25

SPI_CS0/GPIO36

Y25

SPI_DI1/GPIO35

AA23

SPI_DO1/GPIO34

Y24

SPI_SCLK1/GPIO33

AA24

SPI_CS1/GPIO32

AB6

SCL0/GPIO60

AB4

SDA0/GPIO59

AC5

SCL1/GPIO58

AC4

SDA1/GPIO57

AD4

SCL2/GPIO56

AE4

SDA2/GPIO71

AE5

SCL3/GPIO70

AD5

SDA3/GPIO69

AE6

SCL4/GPIO68

AD6

SDA4/GPIO67

AC6

SCL5/GPIO66

AC7

SDA5/GPIO65

FPGA_LVDS_INFO

USB_CTL3

DiiVA_POD_CTL

M25

M24

M23

N23

T27

EB_CS3/GPIO64

EB_CS2/GPIO79

EB_CS1/GPIO78

EB_CS0/GPIO77

RMII_REF_CLK

RMII_CRS_DV

RMII_MDIO

RMII_MDC

AD2

AB1

AB2

AB3

AC2

R105 22

EPHY_MDC

EPHY_MDIO

EPHY_REFCLK

EPHY_CRS_DV

for DiiVA(China)

SEL_USB3

SEL_USB2

SEL_USB1

EB_ADDR[0-14]

EB_OE_N

EB_BE_N1

EB_BE_N0

EB_WE_N

T28

U27

EB_OE_N

EB_WE_N

U26

U28

EB_WAIT

EB_BE_N1

J22

K22

J23

EB_BE_N0

EB_ADDR17/GPIO84

EB_ADDR16/GPIO83

EB_ADDR15/GPIO82

EB_ADDR[11]

EB_ADDR[12]

EB_ADDR[13]

EB_ADDR[14]

L26

L27

L25

N26

EB_ADDR14

EB_ADDR13

EB_ADDR12

EB_ADDR[9]

EB_ADDR[8]

EB_ADDR[10]

N27

M26

L28

EB_ADDR9

EB_ADDR11

EB_ADDR10

IC100

LG1152D-B1

LG1152_NON_RM

RMII_TXEN

RMII_TXD1

RMII_TXD0

RMII_RXD1

RMII_RXD0

CAM_CE1_N

CAM_CE2_N

CAM_CD1_N

CAM_CD2_N

CAM_VS1_N

CAM_VS2_N

CAM_IREQ_N

CAM_RESET

CAM_INPACK_N

AC3

AE1

AD3

AD1

W26

V28

Y27

Y26

W28

W27

AA28

AB26

AA27

AA26

R108 22

R106 22

EPHY_EN

EPHY_TXD1

EPHY_RXD0

EPHY_TXD0

EPHY_RXD1

+3.3V_NORMAL

/PCM_CE2

/PCM_CE1

CAM_CD2_N

CAM_CD1_N

CI

10K

R166

CAM_IREQ_N

CI

R167 10K

PCM_RST

CAM_INPACK_N

EPHY_INT

EB_ADDR[5]

EB_ADDR[7]

EB_ADDR[6]

L24

L23

K28

EB_ADDR8

EB_ADDR7

EB_ADDR6

EB_ADDR5

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

CAM_IOIS16_N

Y28

V27

V26

CAM_REG_N

CAM_WAIT_N

CI

10K

R168

PCM_5V_CTL

HP_DET

EB_ADDR[3]

EB_ADDR[2]

EB_ADDR[4]

K27

K26

K25

K24

EB_ADDR4

EB_ADDR3

EB_ADDR2

SC_CLK/GPIO90

SC_DETECT/GPIO93

R25

U23

T25

SMARTCARD_DET

SMARTCARD_CLK

SEL_USB1
SEL_USB2
SEL_USB3
/RST_PHY

SC_DET
DiiVA_POD_CTL

+3.3V_NORMAL

EB_ADDR[1]

EB_ADDR[0]

10K

R109

K23

V22

U22

EB_ADDR1

EB_ADDR0

EB_DATA15

EB_DATA14

SC_VCCEN/GPIO89

SC_VCC_SEL/GPIO88

SC_RST/GPIO91

SC_DATA/GPIO92

T24

T23

R24

SMARTCARD_RST

SMARTCARD_VCC

SMARTCARD_DATA

SMARTCARD_PWR_SEL

T22

R22

P22

N22

M22

EB_DATA9

EB_DATA13

EB_DATA12

EB_DATA11

EB_DATA10

SD_CLK/GPIO76

SD_CMD/GPIO73

SD_CD_N/GPIO75

SD_WP_N/GPIO74

SD_DATA3/GPIO72

C22

C23

A23

B23

A24

MOTOR_CCW

MOTOR_CLOSE_SW

MO_SENS_TO_MAIN_UP

MO_SENS_TO_MAIN_DOWN

EB_DATA[0-7]

EB_DATA[0]

EB_DATA[1]

EB_DATA[3]

EB_DATA[2]

EB_DATA[4]

EB_DATA[5]

EB_DATA[6]

EB_DATA[7]

L22

T26

R28

R27

R26

P28

P27

P26

N28

EB_DATA8

EB_DATA7

EB_DATA6

EB_DATA5

EB_DATA4

EB_DATA3

EB_DATA2

EB_DATA1

EB_DATA0

EMMC_RST
EMMC_CLK

EMMC_CMD
EMMC_DATA7
EMMC_DATA6
EMMC_DATA5
EMMC_DATA4
EMMC_DATA3
EMMC_DATA2
EMMC_DATA1
EMMC_DATA0

NAND_CS1

NAND_CS0

NAND_ALE

NAND_CLE

NAND_REN

NAND_WEN

SD_DATA2/GPIO87

SD_DATA1/GPIO86

SD_DATA0/GPIO85

USB_DP1

USB_DM1

USB_DP2

USB_DM2

USB_TXR_RKL

USB_ANALOGTEST

BT_USB_DP

BT_USB_DM

BT_TXR_RKL

BT_ANALOGTEST

R173

Y4

C25

B25

AA1

AA2

AA4

22

22

OPT

R175

R176

R174

B24

C24

A25

MOTOR_CW

IR_B_RESET

MOTOR_OPEN_SW

B27

A27

A26

B26

USB_DM3

USB_DP3

USB_HUB_IC_IN_DM

USB_HUB_IC_IN_DP

Place near Jack side

E28
F27
F26
C26

EMMC_DATA[7]

E27

EMMC_DATA[6]

E26

EMMC_DATA[5]

D27

EMMC_DATA[4]

D28

EMMC_DATA[3]

C27

EMMC_DATA[2]

C28

EMMC_DATA[1]

D26

EMMC_DATA[0]

R23
P24
N25
P23
N24
P25

AC1

GPIO31

V7

GPIO30

W5

GPIO29

W4

GPIO28

V6

GPIO27

V5

GPIO26

V4

GPIO25

U6

GPIO24

U5

GPIO23

U4

GPIO22

T6

GPIO21

T5

GPIO20

T4

GPIO19

R6

GPIO18

R5

GPIO17

R4

GPIO16

P6

GPIO15

P5

GPIO14

P4

GPIO13

N6

GPIO12

N5

GPIO11

N4

GPIO10

N3

GPIO9

M6

GPIO8

AC23

GPIO7

AC24

GPIO6

AE24

GPIO5

AD23

GPIO4

AE23

GPIO3

AC22

GPIO2

AD22

GPIO1

AE22

GPIO0

OPT

WIFI_DP

LG1152 B1

MAIN & GPIO

RCLAMP0502BA

WIFI_DM

M25

M24

M23

N23

T27

T28

U27

U26

U28

J22

K22

J23

EB_OE_N

EB_WE_N

EB_WAIT

EB_BE_N1

EB_BE_N0

A22

XIN_MAIN

B22

EB_CS3/GPIO64

EB_CS2/GPIO79

EB_CS1/GPIO78

EB_CS0/GPIO77

XO_MAIN

AB16

OPM1

EB_ADDR17/GPIO84

EB_ADDR16/GPIO83

AB17

OPM0

AE3

PORES_N

V23

TRST_N0

U25

TMS0

V25

TCK0

V24

TDI0

U24

TDO0

Y22

TRST_N1

AA22

TMS1

AB20

TCK1

AB21

TDI1

W22

TDO1

AB9

PLLSET1

AB8

PLLSET0

AB15

BOOT_MODE1

AB14

BOOT_MODE0

Y23

EXT_INTR3/GPIO48

W25

EXT_INTR2/GPIO63

W24

EXT_INTR1/GPIO62

W23

EXT_INTR0/GPIO61

Y5

UART0_RX/GPIO49

W6

UART0_TX/GPIO50

AA6

UART1_RX

Y6

UART1_TX

AB5

UART2_RX

AA5

UART2_TX

AB23

SPI_DI0/GPIO39

AB24

SPI_DO0/GPIO38

AA25

SPI_SCLK0/GPIO37

AB25

SPI_CS0/GPIO36

Y25

SPI_DI1/GPIO35

AA23

SPI_DO1/GPIO34

Y24

SPI_SCLK1/GPIO33

AA24

SPI_CS1/GPIO32

AB6

SCL0/GPIO60

AB4

SDA0/GPIO59

AC5

SCL1/GPIO58

AC4

SDA1/GPIO57

AD4

SCL2/GPIO56

AE4

SDA2/GPIO71

AE5

SCL3/GPIO70

AD5

SDA3/GPIO69

AE6

SCL4/GPIO68

AD6

SDA4/GPIO67

AC6

SCL5/GPIO66

AC7

SDA5/GPIO65

RMII_REF_CLK

RMII_CRS_DV

RMII_MDIO

RMII_MDC

RMII_TXEN

RMII_TXD1

RMII_TXD0

RMII_RXD1

RMII_RXD0

CAM_CE1_N

CAM_CE2_N

AD2

AB1

AB2

AB3

AC2

AC3

AE1

AD3

AD1

W26

V28

Y27

LG1152_RM
IC100-*1

OPTIC_FPGA_RESET

OPTIC_SERDES_RESET

3D_DEPTH_RESET
/RST_PHY

OLED_TCON_RESET

HW_OPT_9

HW_OPT_7
HW_OPT_8

DSUB_DET

SC_DET
COMP1_DET
HW_OPT_5
HW_OPT_6

M_RFModule_ISP

HW_OPT_10

M_RFModule_RESET

FRC_RESET
HW_OPT_2
HW_OPT_1
HW_OPT_0

HW_OPT_4

FLASH_WP
/RST_HUB

HW_OPT_3

HP_DET

RF_SWITCH_CTL

/TU_RESET

/S2_RESET

OPT

D100

I2C_SDA2
I2C_SCL2

SMARTCARD_DATA
SMARTCARD_RST
SMARTCARD_PWR_SEL
SMARTCARD_VCC
SMARTCARD_DET

L26

L27

L25

N26

N27

M26

L28

L24

L23

K28

K27

K26

K25

K24

K23

V22

U22

T22

R22

P22

N22

M22

L22

T26

R28

R27

R26

P28

P27

P26

N28

EB_ADDR9

EB_ADDR8

EB_ADDR7

EB_ADDR6

EB_ADDR5

EB_ADDR4

EB_ADDR3

EB_ADDR2

EB_ADDR1

EB_ADDR0

EB_DATA9

EB_DATA8

EB_DATA7

EB_DATA6

EB_DATA5

EB_DATA4

EB_DATA3

EB_DATA2

EB_DATA1

EB_ADDR14

EB_ADDR13

EB_ADDR12

EB_ADDR11

EB_ADDR15/GPIO82

CAM_CD1_N

CAM_CD2_N

CAM_VS1_N

CAM_VS2_N

CAM_IREQ_N

Y26

W28

W27

AA28

AB26

EB_DATA0

EB_ADDR10

EB_DATA15

EB_DATA14

EB_DATA13

EB_DATA12

EB_DATA11

EB_DATA10

E28

EMMC_RST

F27

EMMC_CLK

F26

EMMC_CMD

C26

EMMC_DATA7

E27

EMMC_DATA6

E26

EMMC_DATA5

D27

EMMC_DATA4

D28

EMMC_DATA3

C27

EMMC_DATA2

C28

EMMC_DATA1

D26

EMMC_DATA0

R23

NAND_CS1

P24

NAND_CS0

N25

NAND_ALE

P23

NAND_CLE

N24

NAND_REN

P25

NAND_WEN

AC1

GPIO31

V7

GPIO30

W5

GPIO29

W4

GPIO28

V6

GPIO27

V5

GPIO26

V4

GPIO25

U6

GPIO24

U5

GPIO23

U4

GPIO22

T6

GPIO21

T5

GPIO20

T4

GPIO19

R6

GPIO18

R5

GPIO17

R4

GPIO16

P6

GPIO15

P5

GPIO14

P4

GPIO13

N6

GPIO12

N5

GPIO11

N4

GPIO10

N3

GPIO9

M6

GPIO8

AC23

GPIO7

AC24

GPIO6

AE24

GPIO5

AD23

GPIO4

AE23

GPIO3

AC22

GPIO2

AD22

GPIO1

AE22

CAM_RESET

CAM_INPACK_N

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

CAM_IOIS16_N

Y28

V27

V26

AA27

AA26

GPIO0

SC_CLK/GPIO90

SC_DETECT/GPIO93

SC_VCCEN/GPIO89

SC_VCC_SEL/GPIO88

SC_RST/GPIO91

SC_DATA/GPIO92

SD_CLK/GPIO76

SD_CMD/GPIO73

SD_CD_N/GPIO75

SD_WP_N/GPIO74

SD_DATA3/GPIO72

SD_DATA2/GPIO87

SD_DATA1/GPIO86

SD_DATA0/GPIO85

USB_DP1

USB_DM1

USB_DP2

USB_DM2

USB_TXR_RKL

USB_ANALOGTEST

BT_USB_DP

BT_USB_DM

BT_TXR_RKL

BT_ANALOGTEST

Y4
R25

U23

T25

T24

T23

R24

C22

C23

A23

B23

A24

B24

C24

A25

B27

A27

A26

B26

C25

B25

AA1

AA2

AA4

SMARTCARD_CLK
MOTOR_CLOSE_SW

MOTOR_OPEN_SW
MOTOR_CW
MOTOR_CCW

MO_SENS_TO_MAIN_UP

MO_SENS_TO_MAIN_DOWN

OPTIC_FPGA_RESET
OPTIC_SERDES_RESET

OLED_TCON_RESET

FPGA_LVDS_INFO

IRB_SPI_MISO
IRB_SPI_MOSI

IRB_SPI_CK
IRB_SPI_SS

IR_B_RESET

EMMC_RST
EMMC_CLK
EMMC_CMD
EMMC_DATA[0-7]

+3.3V_NORMAL

SW1

JTP-1127WEM

12

2.7K

R201

DEBUG

For ISP

Delete PV

4 3

1/16W

5%

+5V_NORMAL

G

D

HDMI_S/W_RESET

S

Q104
2N7002K

Debug

+3.3V_NORMAL

UART1_RX

UART1_TX

1

P100

12507WS-04L

1

DEBUG

2

3

4

5

+1.0V_VDD

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

Max 360mA

AVDD10_DEMOD

L304

BLM18PG121SN1D

10uFC312

C318 0.1uF

C321 0.1uF

+1.0V_VDD

L302

BLM18PG121SN1D

LG1152A

IC101

VDD33

VDD33_CVBS

VDD33_HDMI

VDD33_XTAL

VDD25_VSB

VDD25_CVBS

VDD25_REF

VDD25_COMP

VDD25_AUD

VDD25_LVTX

VDD18_A

AVDD10_DEMOD

AVDD10_VSB

AVDD10_LVTX

VDDC_XTAL

+2.5V_NORMAL

For HDCP OTP
Will be change to LOW for MP

For HeatSinK, AL Block / SMD Top

HEATSINK/ALBLOCK

MDS62110218

HEATSINK/ALBLOCK

MDS62110218

HEATSINK/ALBLOCK

MDS62110218

HEATSINK/ALBLOCK

M300

M303

M306

M307

MDS62110218

AVSS25_REF

HEATSINK/ALBLOCK

HEATSINK/ALBLOCK

M301

MDS62110218

M302

MDS62110218

M321

MDS62110218

P1

P2
P14
R14
F18
H16
M16

L15
R13
R12
V13
P10
R10

P9

R9

V7
J16

P6

P7

V6
B18
G12
G13

N1

N2

G6

G7
R15
K15
D17
D18

N7
L16

G4

N10
K16
D16

G5

G8

G9
G10
G11
G14
G15

H4

H5

H6

H7

H8

H9
H10
H11
H12
H13
H14
H15

J4

J5

J6

J7

ALBLOCK

VDD33_1
VDD33_2
AVDD33_CVBS_1
AVDD33_CVBS_2
AVDD33_HDMI_1
AVDD33_HDMI_2
VDD33_XTAL

VDD25_VSB
VDD25_CVBS_2
VDD25_CVBS_1
VDD25_CVBS_3
AVDD25_REF
VDD25_COMP_3
VDD25_COMP_1
VDD25_COMP_2
VDD25_COMP_4
VDD25_AAD
VDD25_AUD_1
VDD25_AUD_2
VDD25_AUD_3
VDD25_LVTX_1
VDD25_LVTX_2
VDD25_LVTX_3

VDD18_1
VDD18_2

VDDC10_1
VDDC10_2
AVDD10_CVBS
AVDD10_VSB
AVDD10_LVTX_1
AVDD10_LVTX_2
AVDD10_LLPLL
VDDC_XTAL

VQPS

AVSS25_REF
GND_XTAL
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24

M304

MDS62110218

M305

MDS62110218

M324

MDS62110218

HEATSINK/ALBLOCK

M323

MDS62110218

HEATSINK

HEATSINK

HEATSINK

GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90

J8
J9
J10
J11
J12
J13
J14
J15
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M17
N4
N5
N6
N8
N9
N11
N12
N13
N14
N15
N16
P3
P4
P5
P13
P15
P16
R3
R16
R17
R18
T13
U13

SMD Bottom

M315

MDS62110215

M312

MDS62110215

M313

MDS62110215

M314

MDS62110215

ESD

ESD

OPT

ESD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

LG1152AN-B2

+1.8V_NORMAL

10uFC421

+2.5V_NORMAL

L326

BLM18PG121SN1D

10uFC422

Max 100mA

L324

BLM18PG121SN1D

10uFC414

VDD18_A

VDD25_CVBS

C417 0.1uF

On Package Decap : 0.1uF *1ea

Max 50mA

L322

BLM18PG121SN1D

10uFC401

VDD25_AUD

+2.5V_NORMAL

On Package Decap : 0.1uF *1ea

+3.3V_NORMAL

Max 35mA

L319

BLM18PG121SN1D

10uFC398

VDD33_CVBS

C403 0.1uF

C408 0.1uF

On Package Decap : 0.1uF *1ea

For Tuner Sensitivity / Under DDR

M318

MDS62110215

ESD_AJ

M317

MDS62110215

ESD

M308

MDS62110215

M309

MDS62110215

M322

MDS62110215

For Tuner Sensitivity / Under TUNER

M310

MDS62110215

M311

MDS62110215

C423 0.1uF

C419 0.1uF

C409 0.1uF

GASKET_8.0X6.0X7.5H

GASKET except ATSC

GASKET_8.0X6.0X7.5H

GASKET_8.0X6.0X7.5H

LM8600

OPT

ATSC

10uFC305

Max 1mA

VDDC_XTAL

C313 0.1uF

+2.5V_NORMAL

+1.0V_VDD

L313
BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

+2.5V_NORMAL

L315
BLM18PG121SN1D

10uFC379

On Package Decap : 0.1uF *1ea

+3.3V_NORMAL

L323
BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

SMD TOP FOR ESD

For ATSC

L308

BLM18PG121SN1D

10uFC359

Max 250mA

10uFC375

C386 0.1uF

Max 256mA

VDD33_HDMI

10uFC413

C405 0.1uF

M316

MDS62110217

M320

MDS62110217

M319

MDS62110217

VDD25_LVTX

C385 0.1uF

OPT

C416 0.1uF

ESD

ESD

ESD

10uFC366

C368 0.1uF

C390 0.1uF

Max 250mA

VDD25_COMP

C393 0.1uF

C407 0.1uF

Max 12mA

AVDD10_VSB

10uFC369

C370 0.1uF

L321
BLM15BD121SN1

L320

BLM15BD121SN1

AVSS25_REF

+3.3V_NORMAL

Max 10mA

VDD25_REF

C400 0.1uF

L309

BLM18PG121SN1D

+1.0V_VDD

Max 35mA

AVDD10_LVTX

L305

BLM18PG121SN1D

10uFC332

C333 0.1uF

On Package Decap : 0.1uF *1ea

Max 28mA

L325

BLM18PG121SN1D

10uFC415

VDD25_VSB

+2.5V_NORMAL

On Package Decap : 0.1uF *1ea

Max 1mA

VDD33_XTAL

10uFC371

C381 0.1uF

C338 0.1uF

C418 0.1uF

+1.5V_Bypass Cap

+1.5V_DDR

L300

BLM18PG121SN1D

5V

ZD301

ESD_LG1152

VCC1.5V_MAIN

Max 40mA

VREF_M0

R300

1K 1%

0.1uF

R301

1K 1%

On Package Decap : 0.1uF *1ea

+1.5V_DDR

BLM18PG121SN1D

On Package Decap : 0.1uF *2ea

+0.9V_VDD

10uFC301

5V

ZD300

ESD_LG1152

On Package Decap : 0.1uF *6ea

+0.9V_VDD

On Package Decap : 0.1uF *1ea

+1.8V_NORMAL

L312

BLM18PG121SN1D

On Package Decap:0.1uF *1ea

+1.8V_NORMAL

On Package Decap:0.1uF *1ea

+3.3V_NORMAL

L310

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

C308

C300

L301

10uFC303

10uFC307

Max 20mA

10uFC347

Max 120mA

VDD18_LVTX

10uFC374

Max 93mA

VDD18_LVRX

L318

BLM18PG121SN1D

10uFC397

10uFC372

1000pF

C306 0.1uF

C314 0.1uF

C353 0.1uF

C382 0.1uF

C404 0.1uF

C377 0.1uF

10uFC326

C316 0.1uF

C310 0.1uF

Max 5900mA

C322 0.1uF

C319 0.1uF

C388 0.1uF

C383 0.1uF

(18)

10uFC302

C317 0.1uF

C311 0.1uF

C323 0.1uF

C320 0.1uF

On Package Decap : 0.1uF *3ea

Max 340mA

VCC1.5V_DE

C336 0.1uF

C340 0.1uF

C327 0.1uF

C325 0.1uF

VDD33

C392 0.1uF

C394 0.1uF

C399 0.1uF

C391 0.1uF

Max 680mA

VCC1.5V_MAIN

C329 0.1uF

C334 0.1uF

C337 0.1uF

VCC1.5V_MAIN

C342 0.1uF

R302

R303

C343 0.1uF

1K 1%

1K 1%

C346 0.1uF

Max 40mA

VREF_M1

0.1uF

C350

C362

On Package Decap : 0.1uF *1ea

Max 40mA

VCC1.5V_DE

R304

R305

VREF_M2

1K 1%

0.1uF

1K 1%

C363

C351

On Package Decap : 0.1uF *1ea

10uFC309

10uFC341

Max 6mA

C315 0.1uF

Max 1320mA

C345 0.1uF

MAIN_XTAL

C324 0.1uF

AVDD10_OSPREY

C348 0.33uF

+0.9V_VDD

+1.0V_VDD

L303
BLM18PG121SN1D

L306

BLM18PG121SN1D

On Package Decap : 0.1uF *3ea

+1.8V_NORMAL

L316

BLM18PG121SN1D

10uFC395

On Package Decap:0.1uF *1ea

+1.8V_NORMAL

+3.3V_NORMAL

BLM18PG121SN1D

L314

BLM18PG121SN1D

L317

10uFC396

VDD18_MAIN_XTAL

10uFC378

Max 48.8mA

VDD33_USB

C402 0.1uF

1000pF

1000pF

C349 0.33uF

Max 49mA

VDD18

C410 0.1uF

Max 31mA

C384 0.1uF

C389 0.1uF

C406 0.1uF

C411 0.1uF

C304 0.1uF

For secure BOOT OTP

Will be change to LOW for MP

LG1152

MAIN POWER

VDD33_USB

VDD18_LVTX

VDD18_LVRX

VDD18_MAIN_XTAL

VCC1.5V_DE

VCC1.5V_MAIN

VREF_M1

VREF_M0

AVDD10_OSPREY

+0.9V_VDD

+0.9V_VDD

MAIN_XTAL

VDD18

LG1152D

VDD33

U8
U9

U10

V8

V9
V10
J21
K21

AA10
AA11

VDD18

W18
W19
Y18
Y19

AG28
AH27

AA7
AA8
AA9
AG1

AA12
AA13
AB12

J28
B28
G22

F9

G8

G9
G10
G11

H8

H9
H10
H11
F22
G13
G14
G16
G17
G18
G19
G20
G21
H13
H14
H16
H17
H18
H19
H20
H21

VREF_M2

L4
F13
G12
F14
G15

L20
M20
M21
M27
M28
N20
N21
P20
P21
R20
R21

K8

K9
K10
K11

L8

L9
L10
L11

M8

M9
M10
M11

N8

N9
N10
N11

P8

P9
P10
P11

R8

R9
R10
R11

Y7

Y8
AF1
F28

H22

AA19

G23

G7

H7
H12
H15

J7

J8

J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20

K7
K12

IC100

LG1152D-B1

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
AVDD33_USB_1
AVDD33_USB_2
AVDD33_BT_USB_1
AVDD33_BT_USB_2

VDD18_1
VDD18_2
VDD18_3
VDD18_4
VDD18_5
VDD18_6
VDD18_LTX_1
VDD18_LTX_2
VDD18_LTX_3
VDD18_LTX_4
VDD18_LVRX_1
VDD18_LVRX_2
VDD18_LVRX_3
VDD18_DISPPLL
VDD18_DR3PLL
VDD18_MAIN_XTAL

VDD15_M2_1
VDD15_M2_2
VDD15_M2_3
VDD15_M2_4
VDD15_M2_5
VDD15_M2_6
VDD15_M2_7
VDD15_M2_8
VDD15_M2_9
VDD15_M0_1
VDD15_M0_2
VDD15_M0_3
VDD15_M0_4
VDD15_M0_5
VDD15_M0_6
VDD15_M0_7
VDD15_M0_8
VDD15_M0_9
VDD15_M0_10
VDD15_M0_11
VDD15_M0_12
VDD15_M0_13
VDD15_M0_14
VDD15_M0_15
VDD15_M0_16
VDD15_M0_17

VREF_M2_0
VREF_M1_0
VREF_M1_1
VREF_M0_0
VREF_M0_1

VDDC10_OSPREY_1
VDDC10_OSPREY_2
VDDC10_OSPREY_3
VDDC10_OSPREY_4
VDDC10_OSPREY_5
VDDC10_OSPREY_6
VDDC10_OSPREY_7
VDDC10_OSPREY_8
VDDC10_OSPREY_9
VDDC10_OSPREY_10
VDDC10_OSPREY_11

VDDC09_1
VDDC09_2
VDDC09_3
VDDC09_4
VDDC09_5
VDDC09_6
VDDC09_7
VDDC09_8
VDDC09_9
VDDC09_10
VDDC09_11
VDDC09_12
VDDC09_13
VDDC09_14
VDDC09_15
VDDC09_16
VDDC09_17
VDDC09_18
VDDC09_19
VDDC09_20
VDDC09_21
VDDC09_22
VDDC09_23
VDDC09_24
VDD09_LTX_1
VDD09_LTX_2
VDD09_LTX_3
AVDD09_DR3PLL

VDDC_MAIN_XTAL

SP_VQPS

GND_MAIN_XTAL

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20

3

GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148

K13
K14
K15
K16
K17
K18
K19
K20
L7
L12
L13
L14
L15
L16
L17
L18
L19
L21
M7
M12
M13
M14
M15
M16
M17
M18
M19
N7
N12
N13
N14
N15
N16
N17
N18
N19
P7
P12
P13
P14
P15
P16
P17
P18
P19
R7
R12
R13
R14
R15
R16
R17
R18
R19
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
U7
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W20
W21
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y20
Y21
AA14
AA15
AA16
AA17
AA18
AA20
AA21
AB7
AB10
AB11
AB13
AB22

Place these close to tuner

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

TU_CVBS

680pF
C506

OPT

L503

SC_CVBS_IN

AV1_CVBS_IN

DSUB_B+

DSUB_G+

DSUB_R+

SC_B
SC_G

SC_R

COMP1_Pb

COMP1_Y

COMP1_Pr

OPT

R3634

SCART_Lout

SCART_Rout

PC_L_IN

PC_R_IN

SC_L_IN

SC_R_IN

AV1_L_IN

AV1_R_IN

CHB_CVBS

2K

SC_FB

SC_ID

C3625

470K

D503

5.5V

5pF
50V

R601
470K

R607

EU
R602
470K

R603
470K

R617

L501

L500

L502

OPT

D504

5.5V

75
OPT

NON SCART

R525-*1

0

D506

D505

5.5V

5.5V

OPT

R3633

+12V

100K

100K

2K

R552

R554

OPT

Q505

CHB

D500

5.5V

C528

EU

EU

C573
560pF
50V

C574
560pF
50V

OPT

+5V_TU

R618

220

CHB

B

5.5V

OPT

OPT

10pF

100K

100K

L506

OPT

C572
330pF
50V

L508

EU

R525

75

D501

OPT

C546

C580

10pF

R538

2.2uF
10V

R549

C581
560pF
50V

OPT

5.5V

OPT

10pF

EU

EU

C525

EU

E

C

R522

D502

OPT

C579

C3626

L509

EU

1uH

C508

EU
150pF
50V

EU

L504

1uH

50V
150pF
C511

R616

220

CHB

680pF
C517
OPT

R521 100

10K

EU

EU

NON SCART

R524

R524-*1

2.7K

0

OPT

OPT

OPT

C606

10pF

C605

C607

10pF

10pF

75

75

75

R595

R600

R594

DSUB_VSYNC

DSUB_HSYNC

Near Place Scart AMP

C6006

1uF 25V
C6001

SCART_Lout_SOC

SCART_Rout_SOC

C587
100pF
50V

C576
330pF
50V

EU

EU
R608

470K

R609

470K

C524

10pF

5pF
50V
OPT

2.2uF

L507

OPT

10pF

10V

C578

C522

EU

10pF

C575
100pF
50V

C577
100pF
50V

Place JACK Side

EU

C514
150pF
50V

EU

1uF25V

C509
150pF

EU

75

R52 8

75

1%

R606

C586
560pF
50V

OPT

75

R52 9

EU

10K

R60 06
EU

10K
R6005

C582
330pF
50V
OPT

75

1%

R605

L511

75

R53 0

EU
L510

75

1%

R604

R614
75
1%

R615
75
1%

SCART_AMP_R_FB

SCART_AMP_L_FB

EU

C588
330pF
50V

C589
100pF
50V

DTV/MNT_V_OUT

R613
75

OPT

1%

SC_SOG_IN

10K

10K

R555

DSUB_HSYNC
DSUB_VSYNC

SC_SOG_IN

R553

Main clock for LG1152A

8pF

C513

8pF

C512

C500

R508 22K

2.2uF

C501

R509 22K

2.2uF

EU

EU

2.2uF

2.2uF

2.2uF

2.2uF

R510

EU

R511

EU

R512 22K

R513 22K

22K

22K

C502

C503

C504

C505

Place SOC Side

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+5V_NORMAL

EU
C510

0.1uF
16V

DTV/MNT_VOUT

Close to LG1152A

R536 68
R539 33
R541 68
R546 33
R547 0
R548 68
R550 33
R568 33
R569 33

R570 33
R564 150
R565 150
R566 0
R567 150

R514 75K

R515 100K

R516 75K

R517 100K

R518 75K

R519 100K

EU
R527

10K

SELECT

XIN_SUB

XO_SUB

SOC_RESET

R571 33
R572 33

R573 100

R559 68

R574 100
R551 33
R557 33

R575 33

R558 68

C516 0.047uF
C518 0.047uF
C523 0.047uF
C526 0.047uF
C527 1000pF
C531 0.047uF
C532 0.047uF
C542 0.047uF
C543 0.047uF
C544 1000pF
C545 0.047uF
C538 0.047uF
C539 0.047uF
C540 1000pF
C541 0.047uF

X-TAL_1

GND_1

1

2

X500

24MHz

4

3

GND_2

X-TAL_2

AUAD_L_CH5_IN

AUAD_R_CH5_IN

AUAD_L_CH4_IN

EU

AUAD_R_CH4_IN

EU

AUAD_L_CH3_IN

AUAD_R_CH3_IN

Q506

MMBT3904(NXP)

IC500

NLASB3157DFT2G

EU

R560
R561

0.047uF

0.047uF

0.047uF

0.047uF

0.047uF

0.047uF

0.047uF

0.047uF

0.047uF

R563 0

EU

22

22

1M

1

2

3

330

33

XIN_SUB

XO_SUB

6

VCC

5

A

4

Selece = High ==> A = B1
Selece = Low ==> A = B0

C549
C550
C551
C552
C553
C554
C555
C556
C557

C515
100pF
50V
EU

R579
R580

R535

C

E

B1

GND

B0

L17
L18
P17
K17
K18

M2
M1

R4

N3
M3

U14
T14
V15
U15
T15
U16
V14
T16
V16
V17
U17

P8

R8
P11
R11

U8

V8
V10

T8

V9
T11

U9

T9
U10
T10
V11
U11
V12
U12
T12

EU

XIN_SUB
XO_SUB
VSB_AUX_XIN
XTLIN_AAD
XTLOUT_AAD
OPM1
OPM0

PORES_N

L9A_SCL
L9A_SDA

CVBS_IN1
CVBS_IN2
CVBS_IN3
CVBS_VCM
CVBS_IN4
CVBS_IN5
CVBS_IN6
CB_IN
CB_VCM
BUF_OUT1
BUF_OUT2

HSYNC
VSYNC
SC1_FB
SC1_SID
BINCOM_IN
B_IN
GINCOM_IN
G_IN
SOG_IN
RINCOM_IN
R_IN
PB1_IN
Y1_IN
SOY1_IN
PR1_IN
PB2_IN
Y2_IN
SOY2_IN
PR2_IN

B

EU

R507

10K

IC101

LG1152AN-B2

AAD_ADC_SIFM

AAD_ADC_SIF

AUDA_BGR_OUT

AUD_SCART0_OUTLN
AUD_SCART0_OUTLP
AUD_SCART0_OUTRN
AUD_SCART0_OUTRP

AUAD_L_CH5_IN
AUAD_R_CH5_IN
AUAD_L_CH4_IN
AUAD_R_CH4_IN
AUAD_L_CH3_IN
AUAD_R_CH3_IN
AUAD_L_CH2_IN
AUAD_R_CH2_IN
AUAD_L_CH1_IN
AUAD_R_CH1_IN

AUAD_VR_OUT

PHY0_RXCN_0
PHY0_RXCP_0
PHY0_RX0N_0
PHY0_RX0P_0
PHY0_RX1N_0
PHY0_RX1P_0
PHY0_RX2N_0
PHY0_RX2P_0

PHY0_ARC_OUT_0

ADC_I_INCOM

AUDA_OUTR

DTV_ATV_SELECT

AUDA_OUTL
AUDA_OUTR

AUAD_REFN
AUAD_REFP

AUMI_BIAS

AUMI_IN

AUMI_COM

DDCD0_DA
DDCD0_CK

HPD0

ANTCON

RFAGC
IFAGC

ADC_I_INP
ADC_I_INN

AUDA_OUTL

+5V_NORMAL

R592

220

EU

EU

Q504

MMBT3906(NXP)

N17
N18

U1
R1
R2
T1
V2
U2
T2

U3
V3
V4
T3
U5
T5
U6
T6
U7
T7

T4

10K
U4
V5

R7
R5
R6

E18
E17
E16

J18
J17
H17
H18
G17
G18
G16
F16
F17

P12
M18
P18

T17
U18
T18

R624
100

R625
100

R593

220
EU

E

B

C

DTV/MNT_VOUT

C533 0.1uF
C534 0.1uF

10uFC535

C536 2.2uF

AUDA_OUTL
AUDA_OUTR

EU

EU

AUAD_L_CH5_IN
AUAD_R_CH5_IN
AUAD_L_CH4_IN
AUAD_R_CH4_IN
AUAD_L_CH3_IN
AUAD_R_CH3_IN

R534

R52010K

R577 4.7K
R578 4.7K

0.1uF

C115

0.1uF

C116

0.1uF

C117

H/NIM&CHB

H/NIM&CHB

R626

22K

C604

0.01uF

R627

22K

R599

75

R501100

R502100

+3.3V_NORMAL

HDMI_CLK­HDMI_CLK+
HDMI_RX0­HDMI_RX0+
HDMI_RX1­HDMI_RX1+
HDMI_RX2­HDMI_RX2+

SPDIF_OUT_ARC

IF_AGC

C603

0.01uF

EU

OPT

C558

1000pF

OPT

22K

EU

EU

R531

R532 22K

C5372.2uF
C5472.2uF
C5482.2uF

IF_N
IF_P

HP_LOUT_MAIN

HP_ROUT_MAIN

IC101

LG1152AN-B2

L1

INTR_GBB

BB_TP_VAL
BB_TP_SOP
BB_TP_ERR
BB_TP_CLK

BB_SDA_I
BB_SDA_O

BB_SCL

L9DA_SCL

CHB_DN

CHB_UP
CHB_START
CHB_DATA0
CHB_DATA1
CHB_DATA2
CHB_DATA3
CHB_DATA4

CLK_F54M
CVBS_GC2
CVBS_GC1
CVBS_GC0

CVBS_UP
CVBS_DN

FS00CLK

DAC_DATA0
DAC_DATA1
DAC_DATA2
DAC_DATA3
DAC_DATA4
DAC_START

AAD_GC0
AAD_GC1
AAD_GC2
AAD_GC3
AAD_GC4

AAD_DATA0
AAD_DATA1
AAD_DATA2
AAD_DATA3
AAD_DATA4
AAD_DATA5
AAD_DATA6
AAD_DATA7
AAD_DATA8
AAD_DATA9

HSR_AM0
HSR_AP0
HSR_BM0
HSR_BP0
HSR_CM0

HSR_CP0
HSR_CLKM0
HSR_CLKP0

HSR_DM0

HSR_DP0

HSR_EM0

HSR_EP0

HSR_AM1

HSR_AP1

HSR_BM1

HSR_BP1

HSR_CM1

HSR_CP1
HSR_CLKM1
HSR_CLKP1

HSR_DM1

HSR_DP1

HSR_EM1

HSR_EP1

L2
L3

K1
K2
J2
J3
K3
H1
H2
H3
J1

G1
G2
G3
B1
C1
A4
B4
C4
A2
D1
D2
E2
E1
F1
F2
B2
A3
C2

B3
C3
D3
E3
F3
D4
E4
F4
D5
E5
F5
D6

A5
B5
C5
A6
B6
C6

E6
F6
D7
B7
C7
A8
B8
C8

Close to LG1152A

A7

R581 33

D8
F7
E7
E8
F8

Close to LG1152A

A9

R582 33

B9

R583 33

C9
D9
E9
F9
C10
D10

E10
F10
D11
E11
F11
D12
E12
F12
D13
E13
F13
D14
E14
F14
D15
E15

F15

B10
A10
A11
B11
C12
C11
B12
A12
A13
B13
C14
C13
B14
A14
A15
B15
C16
C15
B16
A16
A17
B17
C18
C17

C529

220pF

OPT

50V

INTR_HDMI1

R576100

ATV_OUT

TUNER_SIF

SCART_Lout_SOC

SCART_Rout_SOC

EU

EU

C520 0.01uF

C521 0.01uF

TPI_SOP
TPI_CLK
TPO_ERR
TPO_VAL
TPO_SOP
TPO_CLK

CHB_DATA
JDVR_SCLK

CHB_VAL
CHB_ERR

TU_CVBS

SCART_Lout
SCART_Rout

SC_R

CHB_CVBS

SC_CVBS_IN
SC_B
SC_G
SC_FB
SC_ID
ATV_OUT

SC_L_IN

SC_R_IN
TUNER_SIF
TUNER_SIF

DTV/MNT_V_OUT

JDVR_SCLK

IF_N
IF_P
IF_AGC

FE_TS_CLK

FE_TS_SYNC

FE_TS_VAL

TPI_DVB_ERR

FE_TS_DATA[0-7]

TPO_DATA[0-7]

TPI_DATA[0-7]

TPI_ERR

TPI_VAL

OPTIC_GPIO1
OPTIC_BACK_CHANNEL

INTR_AFE3CH

AUD_HMR00ARC
AUD_HMR0AMUTE
AUD_HMR0ALRCK

AUD_HMR0ABCK

AUD_HMR0ASD4

AUD_HMR0ASD3

AUD_HMR0ASD2

AUD_HMR0ASD1

AUD_HMR0ASD0

AUD_DAC1_LRCH

AUD_DAC1_SCK
AUD_DAC1_LRCK

AUD_FS25CLK
AUD_FS24CLK
AUD_FS23CLK
AUD_FS21CLK
AUD_FS20CLK

AUDCLK_OUT_SUB

AUD_DAC0_LRCK
AUD_DAC0_LRCH

AUD_DAC0_SCK

AUD_ADC_LRCH

AUD_ADC_SCK
AUD_ADC_LRCK
AUD_MIC_LRCH

AUD_MIC_SCK
AUD_MIC_LRCK

BB_TP_DATA0

BB_TP_DATA1

BB_TP_DATA2

BB_TP_DATA3

BB_TP_DATA4

BB_TP_DATA5

BB_TP_DATA6

BB_TP_DATA7

L9DA_SDA_I
L9DA_SDA_O

AUDCLK_OUT

AAD_DATAEN

DCO_OUT_CLK

R9112
33

AH2

INTR_GBB

AG2

INTR_HDMI1

AF2

INTR_AFE3CH

AH3

AUD_HMR0ARC

AG3

AUD_HMR0AMUTE

AG4

AUD_HMR0ALRCK

AF4

AUD_HMR0ABCK

AF3

AUD_HMR0ASD4

AH5

AUD_HMR0ASD3

AG5

AUD_HMR0ASD2

AF5

AUD_HMR0ASD1

AH4

AUD_HMR0ASD0

AH6

AUD_DAC1_LRCH

AG6

AUD_DAC1_SCK

AF6

AUD_DAC1_LRCK

AH7

AUD_FS25CLK

AG7

AUD_FS24CLK

AH10

AUD_FS23CLK

AG10

AUD_FS21CLK

AF10

AUD_FS20CLK

AH8

AUDCLK_OUT_SUB

AF7

AUD_DAC0_LRCK

AE8

AUD_DAC0_LRCH

AD8

AUD_DAC0_SCK

AE7

AUD_ADC_LRCH

AD7

AUD_ADC_SCK

AC8

AUD_ADC_LRCK

AG8

AUD_MIC_LRCH

AH9

AUD_MIC_SCK

AF8

AUD_MIC_LRCK

AG9

BB_TPI_DATA0

AF9

BB_TPI_DATA1

AE9

BB_TPI_DATA2

AD9

BB_TPI_DATA3

AC9

BB_TPI_DATA4

AE10

BB_TPI_DATA5

AD10

BB_TPI_DATA6

AC10

BB_TPI_DATA7

AE11

BB_TPI_VAL

AD11

BB_TPI_SOP

AC11

BB_TPI_ERR

AE12

BB_TPI_CLK

AH11

BB_SDA_I

AG11

BB_SDA_O

AF11

BB_SCL

AH12

HS_SCL

AG12

HS_SDA_I

AF12

HS_SDA_O

AD12

CHB_DN

AC12

CHB_UP

AE13

CHB_START

AG13

CHB_DATA0

AF13

CHB_DATA1

AH14

CHB_DATA2

AG14

CHB_DATA3

AF14

CHB_DATA4

AH13

CLK_54

AE14

CVBS_GC2

AC13

CVBS_GC1

AD13

CVBS_GC0

AD14

CVBS_UP

AC14

CVBS_DN

AH15

FS00CLK

AG15

AUDCLK_TO_DIGITAL

AF15

DAC_DATA0

AE15

DAC_DATA1

AD15

DAC_DATA2

AC15

DAC_DATA3

AF16

DAC_DATA4

AE16

DAC_START

AD16

AAD_GC0

AC16

AAD_GC1

AE17

AAD_GC2

AD17

AAD_GC3

AC17

AAD_GC4

AE18

AAD_DATAEN

AD18

AAD_DATA0

AC18

AAD_DATA1

AE19

AAD_DATA2

AD19

AAD_DATA3

AC19

AAD_DATA4

AE20

AAD_DATA5

AD20

AAD_DATA6

AC20

AAD_DATA7

AE21

AAD_DATA8

AD21

AAD_DATA9

AC21

AUPLL_CLK

AG16

HS_RX1_AM

AH16

HS_RX1_AP

AH17

HS_RX1_BM

AG17

HS_RX1_BP

AF18

HS_RX1_CM

AF17

HS_RX1_CP

AG18

HS_RX1_CLKM

AH18

HS_RX1_CLKP

AH19

HS_RX1_DM

AG19

HS_RX1_DP

AF20

HS_RX1_EM

AF19

HS_RX1_EP

AG20

HS_RX2_AM

AH20

HS_RX2_AP

AH21

HS_RX2_BM

AG21

HS_RX2_BP

AF22

HS_RX2_CM

AF21

HS_RX2_CP

AG22

HS_RX2_CLKM

AH22

HS_RX2_CLKP

AH23

HS_RX2_DM

AG23

HS_RX2_DP

AF24

HS_RX2_EM

AF23

HS_RX2_EP

IC100

LG1152D-B1

STPIO_SOP/GPIO43
STPIO_VAL/GPIO42
STPIO_ERR/GPIO41

STPIO_DATA/GPIO40

TPI_DVB_CLK/GPIO47
TPI_DVB_SOP/GPIO46
TPI_DVB_VAL/GPIO45

TPI_DVB_DATA0/GPIO44

PCMI3LRCK/GPIO81

AUD_SUBSCK/GPIO51

AUD_SUBLRCK/GPIO52

STPI_CLK
STPI_SOP
STPI_VAL

STPI_ERR
STPI_DATA
STPIO_CLK

TPI_DVB_ERR

TPI_DVB_DATA1
TPI_DVB_DATA2
TPI_DVB_DATA3
TPI_DVB_DATA4
TPI_DVB_DATA5
TPI_DVB_DATA6
TPI_DVB_DATA7

TPI_CLK
TPI_SOP
TPI_VAL

TPI_ERR
TPI_DATA0
TPI_DATA1
TPI_DATA2
TPI_DATA3
TPI_DATA4
TPI_DATA5
TPI_DATA6
TPI_DATA7

TPO_CLK

TPO_SOP

TPO_VAL

TPO_ERR
TPO_DATA0
TPO_DATA1
TPO_DATA2
TPO_DATA3
TPO_DATA4
TPO_DATA5
TPO_DATA6
TPO_DATA7

AUDCLK_OUT

DACLRCH

DACSLRCH/GPIO95
DACCLFCH/GPIO94

DACSCK

DACLRCK

PCMI3LRCH

PCMI3SCK/GPIO80

IEC958OUT

AUD_SUBMCK

AUD_SUBLRCH

BTSCSEL

DTS_EN

TXA0N
TXA0P
TXA1N
TXA1P
TXA2N

TXA2P
TXACLKN
TXACLKP

TXA3N

TXA3P

TXA4N

TXA4P

TXB0N

TXB0P

TXB1N

TXB1P

TXB2N

TXB2P
TXBCLKN
TXBCLKP

TXB3N

TXB3P

TXB4N

TXB4P

PWM0/GPIO55
PWM1/GPIO54
PWM2/GPIO53

PWM_IN

AR102

CHB

AE27
AE26
AD28
AD27
AD26
AC28
AC26
AB28
AC27
AB27

AF27
AE28
AG27
AF28
AG26
AF26
AF25
AH26
AH25
AG25
AH24
AG24

H24
J25
J24
H25
J27
J26
H28
H27
H26
G28
G27
G26

D24
E23
D25
D23
H23
G25
G24
F25
F24
F23
E25
E24

C1
C2
A3
A2
B2
B1

B3
C3
A4

AE2

AD25
AC25
AD24
AE25

AB18
AB19

DTS_EN: ENABLE(’1’) (for development)

BTSC_EN: ENABLE(’1’) (for development)

N1
N2
P2
P1
P3
R3
R1
R2
T2
T1
T3
U3
U1
U2
V2
V1
V3
W3
W1
W2
Y2
Y1
Y3
AA3

L6
L5
M4
M5

47

R200

47

FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]
FE_TS_DATA[7]

R542100

100

100
100

OPTIC_BACK_CHANNEL

R598 47

OPT

R619 47

OPT

R628 22

OPT

R629 47

+3.3V_NORMAL

R59622
R59722

SOC_TXA0N
SOC_TXA0P
SOC_TXA1N
SOC_TXA1P
SOC_TXA2N
SOC_TXA2P
SOC_TXACLKN
SOC_TXACLKP
SOC_TXA3N
SOC_TXA3P
SOC_TXA4N
SOC_TXA4P
SOC_TXB0N
SOC_TXB0P
SOC_TXB1N
SOC_TXB1P
SOC_TXB2N
SOC_TXB2P
SOC_TXBCLKN
SOC_TXBCLKP
SOC_TXB3N
SOC_TXB3P
SOC_TXB4N
SOC_TXB4P

OPT
EDGE_LED

BPL_IN

CHB

33

R556

TPI_DATA[0]
TPI_DATA[1]
TPI_DATA[2]
TPI_DATA[3]
TPI_DATA[4]
TPI_DATA[5]
TPI_DATA[6]
TPI_DATA[7]

TPO_DATA[0]
TPO_DATA[1]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[6]
TPO_DATA[7]

R543

R544
R545

OPTIC_GPIO1

R631
R632

R633

R630 100

10K

100

100

CHB_CLK
CHB_SYNC
CHB_VAL
CHB_ERR
CHB_DATA

USB_CTL2

FE_TS_CLK
FE_TS_SYNC
FE_TS_VAL
TPI_DVB_ERR
FE_TS_DATA[0-7]

TPI_CLK
TPI_SOP
TPI_VAL
TPI_ERR
TPI_DATA[0-7]

TPO_CLK
TPO_SOP
TPO_VAL
TPO_ERR
TPO_DATA[0-7]

AUD_MASTER_CLK
AUD_LRCH

FRC3_FLASH_WP
AUD_SCK
AUD_LRCK

C559

OPT

2.2uF

C630
82pF
50V

AMP_RESET_N

A_DIM
PWM_DIM2
PWM_DIM

SPDIF_OUT

LG1152A LG1152D

LG1152 B0

MAIN AUDIO/VIDEO

3

IC100

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

LG1152D-B1

M0_DDR_RESET_N

M0_DDR_DQSL_P
M0_DDR_DQSL_N

M0_DDR_DQSU_P
M0_DDR_DQSU_N

M0_DDR_ZQCAL

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_DML
M0_DDR_DMU

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ8
M0_DDR_DQ9

M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

D18
E17
E18
E20
E16
D20
F16
F19
E15
D19
D14
E14
D17
F18
D16

F20
D15
F17

A17
A18
F15

F21
D22
E21
D21

E19

B20
A20

B16
C16

C19
C15

C20
B19
C21
B18
A21
C18
B21
A19
B17
C14
A16
B14
B15
A14
C17
A15
E22

R700 0
R701 0

SIGN50005

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8
M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14

M0_DDR_BA0

M0_DDR_BA1

M0_DDR_BA2

M0_DDR_CKE

M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSL_P
M0_DDR_DQSL_N

M0_DDR_DQSU_P
M0_DDR_DQSU_N

M0_DDR_DML
M0_DDR_DMU

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ8
M0_DDR_DQ9
M0_DDR_DQ10

M0_DDR_DQ11

M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

240

1%

M0_DDR_CLK
M0_DDR_CLKN

R704

VCC1.5V_MAIN

R709
10K

R705
200

R706
200

M0_DDR_CKE

M0_DDR_RESET_N

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CLK

M0_DDR_CLKN

IC700

H5TQ2G83BFR-PBC

DDR3

K4

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSL_P
M0_DDR_DQSL_N

R742
10K

M0_DDR_DML

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ6

M0_DDR_DQ4
M0_DDR_DQ3
M0_DDR_DQ2
M0_DDR_DQ5

2Gbit

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

VREFCA

VREFDQ

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4

VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

NC_S1
NC_S2
NC_S3
NC_S4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

M0_DDR_VREFCA

M0_DDR_VREFDQ

J9

E2

H9

ZQ

A3
A10
D8
G3
G9
K2
K10
M2
M10

B10
C2
E3
E10

A1
A11
N1
N11

A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10

B3
B9
C10
D2
D10

VCC1.5V_MAIN

R720

240
1%

C706 0.1uF
C707
C708
C709

C710

C711

C712

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

VCC1.5V_MAIN

R722

R723

1K 1%

VCC1.5V_MAIN

R724

R725

1K 1%

1K 1%

C724

1K 1%

C725

M0_DDR_VREFCA

0.1uF

C728

M0_DDR_VREFDQ

0.1uF

C729

1000pF

1000pF

VCC1.5V_MAIN

R730

R731

1K 1%

VCC1.5V_MAIN

R732

R733

1K 1%

M0_1_DDR_VREFCA

1K 1%

C732

M0_1_DDR_VREFDQ

1K 1%

C733

0.1uF

0.1uF

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7

1000pF

M0_DDR_A8

1000pF

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSU_P
M0_DDR_DQSU_N

M0_DDR_DMU

M0_DDR_DQ10
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ11M0_DDR_DQ7
M0_DDR_DQ15

M0_DDR_DQ9
M0_DDR_DQ8

M0_DDR_DQ12

C747

C748

H5TQ2G83BFR-PBC

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

IC703

DDR3
2Gbit

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4

NC_S1
NC_S2
NC_S3
NC_S4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5

M0_1_DDR_VREFCA

J9

E2

H9

ZQ

A3
A10
D8
G3
G9
K2
K10
M2
M10

B10
C2
E3
E10

A1
A11
N1
N11

A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10

B3
B9
C10
D2
D10

M0_1_DDR_VREFDQ

R739

240
1%

VCC1.5V_MAIN

C758

C746

C723

C760

C751

C756

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

C761

0.1uF

IC100

LG1152D-B1

C9
E9
F10
F12
F8
D11
E8
E11
E7
D10
C4
C5
D8
E10
C7

E12
F7
D9

A9
B9
D7

D13
C13
E13
D12

F11

C12
C11

A7
B7

A11
C6

A12
B11
A13
C10
B12
A10
B13
B10
A8
B4
C8
B5
B6
A5
B8
A6

R702 0
R703 0

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8
M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_DDR_CLK
M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT
M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSL_P
M1_DDR_DQSL_N

M1_DDR_DQSU_P
M1_DDR_DQSU_N

M1_DDR_DML
M1_DDR_DMU

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15

VCC1.5V_MAIN

M1_DDR_CKE

R710
10K

M1_DDR_RESET_N

M1_DDR_CLK

R707
200

M1_DDR_CLKN

M1_DDR_CLK

R708
200

M1_DDR_CLKN

IC100

LG1152D-B1

M2_DDR_RESET_N

R741
10K

M2_DDR_A0
M2_DDR_A1
M2_DDR_A2
M2_DDR_A3
M2_DDR_A4
M2_DDR_A5
M2_DDR_A6
M2_DDR_A7
M2_DDR_A8

M2_DDR_A9
M2_DDR_A10
M2_DDR_A11
M2_DDR_A12
M2_DDR_A13

M2_DDR_BA0
M2_DDR_BA1
M2_DDR_BA2

M2_DDR_CLK

M2_DDR_CLKN

M2_DDR_CKE

M2_DDR_ODT

M2_DDR_RASN
M2_DDR_CASN

M2_DDR_WEN

M2_DDR_DQSU_P
M2_DDR_DQSU_N

M2_DDR_DQSL_P
M2_DDR_DQSL_N

M2_DDR_DML
M2_DDR_DMU

M2_DDR_DQ0
M2_DDR_DQ1
M2_DDR_DQ2
M2_DDR_DQ3
M2_DDR_DQ4
M2_DDR_DQ5
M2_DDR_DQ6
M2_DDR_DQ7
M2_DDR_DQ8
M2_DDR_DQ9

M2_DDR_DQ10
M2_DDR_DQ11
M2_DDR_DQ12
M2_DDR_DQ13
M2_DDR_DQ14
M2_DDR_DQ15

M2_DDR_ZQCAL

M1_DDR_RESET_N

M1_DDR_DQSL_P

M1_DDR_DQSL_N

D1
K4
D2
E5
H6
E4
J4
D6
J5
D3
H4
J6
K5
D4

E6
H5
F4

M2
M3
G6

F6
G5
G4
F5

D5

H3
J1

H1
H2

K3
F2

F1
L1
E3
L2
E1
M1
E2
L3
J3
G1
K2
F3
J2
G2
K1
G3
K6

M2_DDR_A0
M2_DDR_A1
M2_DDR_A2
M2_DDR_A3
M2_DDR_A4
M2_DDR_A5
M2_DDR_A6
M2_DDR_A7
M2_DDR_A8
M2_DDR_A9
M2_DDR_A10
M2_DDR_A11
M2_DDR_A12
M2_DDR_A13

M2_DDR_BA0
M2_DDR_BA1
M2_DDR_BA2

M2_DDR_CKE

M2_DDR_ODT
M2_DDR_RASN
M2_DDR_CASN
M2_DDR_WEN

M2_DDR_RESET_N

M2_DDR_DQSU_P
M2_DDR_DQSU_N

M2_DDR_DQSL_P
M2_DDR_DQSL_N

M2_DDR_DML
M2_DDR_DMU

M2_DDR_DQ0
M2_DDR_DQ1
M2_DDR_DQ2
M2_DDR_DQ3
M2_DDR_DQ4
M2_DDR_DQ5
M2_DDR_DQ6
M2_DDR_DQ7
M2_DDR_DQ8
M2_DDR_DQ9
M2_DDR_DQ10
M2_DDR_DQ11
M2_DDR_DQ12
M2_DDR_DQ13
M2_DDR_DQ14
M2_DDR_DQ15

240

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSL_P
M1_DDR_DQSL_N

M1_DDR_DQSU_P
M1_DDR_DQSU_N

M1_DDR_DML
M1_DDR_DMU

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9

M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DML

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DQ4
M1_DDR_DQ3
M1_DDR_DQ2
M1_DDR_DQ5

R711

1%

M2_DDR_CLK
M2_DDR_CLKN

H5TQ2G83BFR-PBC

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8

J3
K9
J4

F8
G8

G10

H3
G2
F4
G4
H4

N3

C4
D4

B8
A8

B4
C8
C3
C9
E4
E9
D3
E8

A4
F2

F10

H2

H10

J8

M2_DDR_CLK

M2_DDR_CLKN

VCC1.5V_DE

R712

1K 1%

R713

1K 1%

IC701

DDR3
2Gbit

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQS
DQS

DM/TDQS
NF/TDQS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6

VCC1.5V_DE

M2_DDR_VREFCA

C700

VREFCA

VREFDQ

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4

VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5

R714
10K

M2_DDR_RESET_N M2_CLK

M2_CLK

R715
150

M2_CLKN

R716 0
R717 0

0.1uF
1000pF

C701

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

NC_S1
NC_S2
NC_S3
NC_S4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

J9

E2

H9

ZQ

A3
A10
D8
G3
G9
K2
K10
M2
M10

B10
C2
E3
E10

A1
A11
N1
N11

A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10

B3
B9
C10
D2
D10

M2_DDR_CKE

VCC1.5V_DE

R718

R719

M2_CLK
M2_CLKN

1K 1%

1K 1%

M1_DDR_VREFCA

R721

240
1%

M2_DDR_VREFDQ

0.1uF

C702

C703

M1_DDR_VREFDQ

VCC1.5V_MAIN

C713
C714
C715
C716
C717
C718
C719

R743
10K

1000pF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

M2_DDR_RESET_N

M2_DDR_A0
M2_DDR_A1
M2_DDR_A2
M2_DDR_A3
M2_DDR_A4
M2_DDR_A5
M2_DDR_A6
M2_DDR_A7
M2_DDR_A8

M2_DDR_A9
M2_DDR_A10
M2_DDR_A11
M2_DDR_A12
M2_DDR_A13

M2_DDR_BA0
M2_DDR_BA1
M2_DDR_BA2

M2_CLKN

M2_DDR_CKE

M2_DDR_ODT

M2_DDR_RASN
M2_DDR_CASN

M2_DDR_WEN

M2_DDR_DQSL_P
M2_DDR_DQSL_N

M2_DDR_DQSU_P
M2_DDR_DQSU_N

M2_DDR_DML
M2_DDR_DMU

M2_DDR_DQ0
M2_DDR_DQ1
M2_DDR_DQ2
M2_DDR_DQ3
M2_DDR_DQ4
M2_DDR_DQ5
M2_DDR_DQ6
M2_DDR_DQ7

M2_DDR_DQ8
M2_DDR_DQ9

M2_DDR_DQ10
M2_DDR_DQ11
M2_DDR_DQ12
M2_DDR_DQ13
M2_DDR_DQ14
M2_DDR_DQ15

VCC1.5V_MAIN

R726

R727

1K 1%

VCC1.5V_MAIN

R728

R729

1K 1%

M1_DDR_VREFCA

1K 1%

C726

M1_DDR_VREFDQ

1K 1%

C727

0.1uF
1000pF

C730

0.1uF
1000pF

C731

IC702

H5TQ1G63DFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

NC_1
NC_2
NC_3
NC_4
NC_6

ZQ

VCC1.5V_MAIN

R734

R735

VCC1.5V_MAIN

R736

R737

M2_DDR_VREFCA

M8

H1

L8

VCC1.5V_DE

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M1_1_DDR_VREFCA

1K 1%

1K 1%

C734

M1_1_DDR_VREFDQ

1K 1%

1K 1%

C735

M2_DDR_VREFDQ

SIGN50000

C736
C737
C738
C739
C740
C741
C742
C743

C744

IC704

H5TQ2G83BFR-PBC

DDR3

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5

0.1uF

C749

0.1uF

C750

R738

C722

0.1uF

C704

0.1uF

C705

0.1uF

C720

0.1uF

C721

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
10uF

M1_DDR_A6
M1_DDR_A7

1000pF

M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN

1000pF

M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSU_P
M1_DDR_DQSU_N

M1_DDR_DMU

M1_DDR_DQ10
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ11
M1_DDR_DQ15

M1_DDR_DQ9
M1_DDR_DQ8

M1_DDR_DQ12

240

10V

DDR3 1.5V bypass Cap - Place these caps near Memory

K4

A0

2Gbit

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4

NC_S1
NC_S2
NC_S3
NC_S4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5

M1_1_DDR_VREFCA

J9

E2

H9

ZQ

A3
A10
D8
G3
G9
K2
K10
M2
M10

B10
C2
E3
E10

A1
A11
N1
N11

A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10

B3
B9
C10
D2
D10

M1_1_DDR_VREFDQ

R740

240
1%

VCC1.5V_MAIN

C757

C752

C753

C754

C755

C745

C759

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

LG1152 B0

4MAIN DDR 50

+5V_CI_ON

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

CI HOST I/F

PCM_RST

/PCM_WAIT

PCM_INPACK

/PCM_IORD
/PCM_IOWR

R6202
R6203

R6200

CI_IN_TS_DATA[0-7]

R6211

10K

OPT

CI

22

CI

22

OPT

22

+5V_CI_ON

R6204

10K

OPT

R6205

10K

OPT

CI_VS1

PCM_INPACK

/PCM_CE2

R6206
10K

+5V_CI_ON

R6207
10K

OPT

CI

C6200

0.1uF
CI

/CI_CD1

CI_TS_DATA[3]

CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

/PCM_CE2

CI_VS1

CI_IN_TS_DATA[0]
CI_IN_TS_DATA[1]
CI_IN_TS_DATA[2]
CI_IN_TS_DATA[3]

CI_IN_TS_DATA[4]
CI_IN_TS_DATA[5]
CI_IN_TS_DATA[6]
CI_IN_TS_DATA[7]

CI_TS_CLK

/PCM_REG

CI_TS_VAL

CI_TS_SYNC
CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]

/CI_CD2

C6201
10uF
10V

CI

R6249

R6208

10K

OPT

OPT

5V <=> 3.3V

IC904

74LVC245A

DIR

1

A0

2

A1

3

A2

4

A3

5

A4

CI

6

A5

7

A6

8

A7

9

GND

10

IC905

74LVC1G00GW

1B 5 VCC

2A

3GND

CI

AND GATE => NAND GATE

20

19

18

17

16

15

14

13

12

11

4 Y

+3.3V_NORMAL

VCC

OE

B0

B1

B2

B3

B4

B5

B6

B7

CI

+3.3V_NORMAL

CI

C903

0.1uF

16V

C904

0

0.1uF
R913

16V

OPT

EB_DATA[0]

EB_DATA[1]

EB_DATA[2]

EB_DATA[3]

EB_DATA[4]

EB_DATA[5]

EB_DATA[6]

EB_DATA[7]

DIR

/PCM_CE1

EB_DATA[0-7]

EB_DATA[0-7]

CI_ADDR[11]
CI_ADDR[9]

CI_ADDR[13]

R6243 22

C6206

0.1uF

16V

CI_ADDR[12]

CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]

CI_ADDR[4]

CI_ADDR[3]

CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

CI_DATA[0-7]

OPT

+5V_CI_ON

CI_ADDR[10]

CI_ADDR[11]
CI_ADDR[9]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[12]
CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]
CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

/PCM_CE1

+5V_CI_ON

R6245

10K

OPT

+5V_CI_ON

R6244

10K

CI

R6246

10K

/PCM_OE

OPT

/PCM_WE
/PCM_IRQA

CI_DATA[0-7]

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]
CI_DATA[3]

CI_DATA[0-7]

CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

DIR

CI

AR909

33

CI

AR910

33

WE=>OE

IOWE=>IORD

/PCM_OE

/PCM_IORD

R6209

10K

OPT

GND

100

/CI_DET1

R6214

CI

TS_OUT3
TS_OUT4
TS_OUT5
TS_OUT6
TS_OUT7

R6213

R6212 0

CI

R6215 100

CARD_EN2

TS_IN_SYN

0

OPT

TS_OUT_CLK

CI_RESET

CI

TS_OUT_VAL
TS_OUT_SYN

/CI_DET2

IORD
IOWR

TS_IN0
TS_IN1
TS_IN2
TS_IN3

TS_IN4
TS_IN5
TS_IN6
TS_IN7

CI_WAIT

INPACK

TS_OUT0
TS_OUT1
TS_OUT2

VS1

VCC
VPP

REG

GND

0

R6210

0

OPT

P6200

10067972-000LF CI

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

69

R6219

R6216

R6217

10K

OPT

CI_DATA[3]
CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

CI

R6224 22

C6205 0.1uF

0

OPT

10K

OPT

CI

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]

CI_IN_TS_VAL
CI_IN_TS_CLK

CI_IN_TS_SYNC

CI_ADDR[10]

CI_ADDR[8]

CI_ADDR[14]

CI

GND

1

DAT3

2

DAT4

3

DAT5

4

DAT6

5

DAT6

6

/CARD_EN1

7

ADDR10

8

/O_EN

9

ADDR11

10

ADDR10

11

ADDR8

12

ADDR13

13

ADDR14

14

/WR_EN

15

/IRQA

16

VCC

17

VPP

18

TS_IN_VAL

19

TS_IN_CLK

20

ADDR12

21

ADDR7

22

ADDR6

23

ADDR5

24

ADDR4

25

ADDR3

26

ADDR2

27

ADDR1

28

ADDR0

29

DAT0

30

DAT1

31

DAT2

32

/IO_BIT

33

GND

34

G1G2

TPO_DATA[0-7]

TPO_CLK
TPO_SOP
TPO_VAL
TPO_ERR

TPO_DATA[0]
TPO_DATA[1]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[6]
TPO_DATA[7]

CI

AR904

33

AR905

CI

AR903

33

CI

33

CI_IN_TS_DATA[0]
CI_IN_TS_DATA[1]
CI_IN_TS_DATA[2]
CI_IN_TS_DATA[3]
CI_IN_TS_DATA[4]
CI_IN_TS_DATA[5]
CI_IN_TS_DATA[6]
CI_IN_TS_DATA[7]

CI_IN_TS_CLK
CI_IN_TS_SYNC
CI_IN_TS_VAL

CI_ADDR[0]
CI_ADDR[1]
CI_ADDR[2]
CI_ADDR[3]

CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]

CI_ADDR[8]

CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]

BUFFER FOR 5V => 3.3V

/CI_CD2

/CI_CD1

+5V_NORMAL

CI

10K

R915

CI
C905

0.1uF
16V

CI

10K

R916

CI
C906

0.1uF
16V

CI_TS_DATA[7]
CI_TS_DATA[6]
CI_TS_DATA[5]
CI_TS_DATA[4]

CI_TS_DATA[3]
CI_TS_DATA[2]
CI_TS_DATA[1]
CI_TS_DATA[0]

PCM_INPACK

CI_TS_CLK

CI_TS_VAL

CI_TS_SYNC

/PCM_WAIT

/PCM_IRQA

AR921

AR920

AR919

CI

100

CI

100

CI

100

GND_8

VCC_4

GND_7

GND_6

VCC_3

GND_5

2OE

48

1A0

47

1A1

46

45

1A2

44

1A3

43

42

2A0

41

2A1

40

39

2A2

38

2A3

37

3A0

36

3A1

35

34

3A2

33

3A3

32

31

4A0

30

4A1

29

28

4A2

27

4A3

26

3OE

25

CI

AR911

33

CI

AR912

33

CI

AR913

33

IC903

74LVC16244ADGG

CI

EB_ADDR[0]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]

EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[6]
EB_ADDR[7]

EB_ADDR[8]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]

+3.3V_NORMAL

1OE

1

1Y0

2

1Y1

3

GND_1

4

1Y2

5

1Y3

6

VCC_1

7

2Y0

8

2Y1

9

GND_2

10

2Y2

11

2Y3

12

3Y0

13

3Y1

14

GND_3

15

3Y2

16

3Y4

17

VCC_2

18

4Y0

19

4Y1

20

GND_4

21

4Y2

22

4Y3

23

4OE

24

CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

/PCM_REG

/PCM_OE

/PCM_WE
/PCM_IORD
/PCM_IOWR

C900

0.1uF

16V

CI

CAM_WAIT_N
CAM_IREQ_N

CAM_CD2_N

CAM_CD1_N

CAM_INPACK_N

75

AR916

CI

33

33

AR915

AR914

CI

CI

CI

AR918 75

75

TPI_DATA[3]

TPI_DATA[2]

TPI_DATA[1]

TPI_DATA[0]

EB_ADDR[12]
EB_ADDR[13]
EB_ADDR[14]
CAM_REG_N

EB_OE_N
EB_WE_N
EB_BE_N1
EB_BE_N0

CI

AR917

TPI_CLK

TPI_VAL

TPI_SOP

TPI_DATA[7]

TPI_DATA[6]

TPI_DATA[5]

TPI_DATA[4]

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

RL_ON

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

+3.5V_ST

eMMC POWER

+3.3V_NORMAL

L2319

BLM18PG121SN1D

C2371

0.1uF
16V

1

+3.5V_ST

L2301
BLM18PG121SN1D

C2301

4.7uF
10V

POWER_ON/OFF1

+12V

R2305
10K

C2306

0.1uF
50V

3.3V_EMMC

R2300
10K

+3.5V_ST

10K

1

R2306

2

3

L2303

BLM18SG121TN1D

C2307

0.1uF
16V

CIS21J121

L2302

+1.8V_NORMAL

C2372

0.1uF
16V

+1.8V

AP7173-SPG-13 HF(DIODES)

IN

1

PG

2

VCC

3

EN

4

1.5A

Q2301 MMBT3906(NXP)

GND/P.DIM2

PWM_DIM2

L2306

BLM18PG121SN1D

IC2300

9

THERMAL

PWR ON

24V
GND
GND

3.5V

3.5V
GND
GND
12V
12V
12V

EMMC_VCCQ

[EP]

OUT

8

FB

7

SS

6

GND

5

OPT
P2301
FW20020-24S

LPB

R2302
100

L2305

CIS21J121

C2317

0.1uF
50V

L/DIM0_VS

A_DIM

1

1
3

3
5

5
7

7
9

9
11

11
13

13
15

15
17

17
19

19
21

21 22
23

23 24

25

SMAW200-H24S2

P2300

2

2
4

4
6

6
8

8

10

10
12

12
14

14
16

16
18

18
20

20
22
24

24V
24V
GND
GND

3.5V

3.5V
GND
GND/V-sync
INV ON
A.DIM
P.DIM1
Err OUT

Tuner 1.25V REG Input

+3.3V_TU

C2376
22uF
10V

SAMSUNG_eMMC

293 mA

+1.8V_NORMAL

1%

R1

C2308
2200pF
50V

R2314
3K
1%

R2315
100
1%

1/16W

3.9K
R2321

R2

C2313
10uF
10V

C2315

0.1uF
16V

+24V

R2312
100

PWM_DIM

L2314
BLM18PG121SN1D

+3.3V_NORMAL

R2330
1K

0

R2304

+3.3V_TU_IN

ERROR_OUT

INV_CTL

3. soft start

POWER_ON/OFF2_2

+12V

L2311

CIS21J121

1

+12V

L2310
BLM18PG121SN1D

C2322
10uF
16V

Switching freq: 700K

+3.3V_NORMAL

+5V_NORMAL

R2334
10K

PANEL_POWER

PANEL_CTL

+5V_Normal

R2301
10KPOWER_ON/OFF1

POWER_ON/OFF2_1

R1

C2334
100pF

50V

R2

1%

R2308

R2311

OPT

R2348

10K

56K

10K

1%

+2.5V

AP7173-SPG-13 HF(DIODES)

IN

1

PG

2

VCC

C2324
10uF
10V

3

EN

4

0.01uF

R2341

C2336
1uF
10V

IC2303

THERMAL

1.5A

10K

C2326
50V

9

C2328

0.1uF
50V

C2332
10uF

9

THERMAL

C2335

0.1uF
50V

16V

[EP]GND

VIN

8

VBST

7

SW

6

GND

5

VREG5

C2342
2200pF
50V

VFB

R2343

33K

R2344

5.6K

C

Q2304

B

MMBT3904(NXP)

E

IC2304

TPS54327DDAR

EN

1

2

3

SS

4

3A

Vout=0.765*(1+R1/R2)

[EP]

OUT

8

FB

7

SS

6

GND

5

C2331
2200pF
50V

R2346
2K
1%

R2347

4.3K
1%

AO3407A

OPT

R2

Q2305

R1

S

G

MAX 1A

C2345

0.1uF
16V

D

700 mA

1uF

C2339

OPT

L2313

6.8uH

NR8040T4R7N

C2340
10uF
10V

25V

+2.5V_NORMAL

TYP 1450mA

+5V_NORMAL

C2343
22uF
10V

C2344

0.1uF
16V

PANEL_VCC

C2346

0.1uF
50V

Power_DET

+12V

4

+12V

L2309

BLM18PG121SN1D

C2354

10uF
16V

C2303

0.1uF
50V

4

+3.5V_ST

+24V

PD_24V
R2364

8.2K
1%

PD_24V
R2365

1.5K
1%

PD_+3.5V
R2366
0
5%

C2359

0.1uF
16V

C2360

0.1uF
16V

VCC

VCC

PD_24V

PD_+12V
R2362

2.7K
1%

PD_+12V
R2363

1.2K
1%

+1.0V_VDD

VIN2

VIN1

VBST

SW2

SW1

IC2306

TPS54425PWPR

14

13

12

4A

11

10

9

8

THERMAL

15

1

2

3

4

5

6

7

[EP]PGND

PGND2

PGND1

Vout=0.765*(1+R1/R2)

R2373
100K

IC2307

NCP803SN293

3

1

GND

PD_24V

R2372
100K

PD_24V

IC2308

NCP803SN293

3

1

GND

VO

VFB

VREG5

SS

GND

PG

EN

RESET

2

RESET

2

R2309
100K

R2310 10K

C2305

0.1uF
OPT

C2318
1uF
10V

+3.5V_ST

R2376
10K

OPT

not to RESET at 8kV ESD

LG1152 Max: 1728 mA
LG1132 Max: 2000 mA

R1

R2313

9.1K

C2368
22uF
10V

1%

C2369
22uF
10V

C2319
3300pF
50V

POWER_ON/OFF2_3

L2316

2uH

POWER_DET

C2365

0.1uF
16V

24V-->3.48V
12V-->3.58V

ST_3.5V-->3.5V

URSA5
R2322-*1
24K

1%

R2

R2322
22K

1%

FRC3

OPT

C2321
22pF
50V

+1.0VDC

Vout=0.8*(1+R1/R2)

2

C2353
3300pF
50V
OPT

OPT

MAX 4.7 A

+3.3V_NORMAL

L2318

CIS21J121

R2319

1.5K

R2382

30K

1/16W

1%

R2320

10K

L2307

CIS21J121

R1

1%

1%

R2

L2300

BLM18PG121SN1D

Placed on SMD-TOP

C2300

C2304

10uF

10uF

16V

16V

+12V

+3.3V_NORMAL

IC2301

[EP]LX

AOZ1038PI

C2309

0.1uF
16V
OPT

PGND

VIN

AGND

FB

NC_2

1

8

NC_1

9

2

7

THERMAL

EN

3

6

COMP

4

5

6A

D2350

ADUC 20S 02 010L

*NOTE 17

OPT

R23160

R2317

20K

C2310

0.1uF
16V

C2311

2200pF

50V

R2318

L2304

2uH

10K

C2312
10uF
10V

POWER_ON/OFF2_1

C2314
10uF
10V

C2316
10uF
10V

C2352
10uF
10V

Vout=0.8*(1+R1/R2)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C2302

4.7uF
16V

RT/CLK

GND_1

GND_2

PVIN_1

PVIN_2

VIN

VSENSE

IC2305

EAN62348501

1

15

2

THERMAL

3

4

5

6

7

[EP]GND

PWRGD

14

C2349

BOOT

13

0.1uF
16V

PH_2

12

PH_1

11

EN

10

SS/TR

9

COMP

8

1.3K
R2307

C2348

4700pF 50V

47pF 50V

22000pF 50V

C2373

R2381 0

Max 5926 mA

L2317

1uH

R2357 1K

C2374

1/16W

5%

Switching freq: 400 ~ 580 Khz

+0.9V_VDD

C2363

C2350

22uF

22uF

10V

10V

POWER_ON/OFF2_3

OPT
C2370
10uF
10V

Vout=0.8*(1+R1/R2)

4

+3.5V_ST

DDR MAIN 1.5V

L2308

C2320
10uF
10V

VIN_1

VIN_2

GND_1

GND_2

EP[GND]

1

2

3

4

10K

R2339

C2325

THERMAL

17

IC2302

TPS54319TRE

3A

5

6

COMP

AGND

VSENSE

3A

0.1uF
16V

7

BOOT14PWRGD15EN16VIN_3

13

12

11

10

9

8

RT/CLK

1/16W 5%

$ 0.145

PH_3

PH_2

PH_1

SS/TR

R2340
15K

C2327

0.1uF

16V

R2342

C2329

0.01uF
50V

330K1/16W 5%

C2330

4700pF

50V

NR8040T3R6N

POWER_ON/OFF2_3

L2312

3.6uH

C2333
22uF
10V

C2337
22uF
10V

1074 mA

+1.5V_DDR

C2341

0.1uF
16V

C2338
100pF
50V

R2349

R1

47K 1%

R2

R2350
56K
1/16W
1%

C2375
180pF
50V

R2378-*1

8.2K

1/16W

R2379-*1

15K

+0.9V_VDD

R2378

6.8K

R2379

12K

URSA5

1%

URSA5

1/16W

1%

Vout=0.6*(1+R1/R2)

1/16W

1/16W

+12V

R2377
100K

C2347
10uF
16V

1/16W
5%

L2315

R1

1%

FRC3

R2

1%

FRC3

Vout=0.827*(1+R1/R2)=1.521V

LG1152

POWER

Renesas MICOM

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

For Debug

+3.5V_ST

MICOM_DEBUG

P3000

12507WS-12L

1

2

3

4

5

6

7

8

9

10

11

12

13

GP4 High/MID Power SEQUENCE

POWER_ON/OFF!

POWER_ON/OFF2_1

POWER_ON/OFF2_2

POWER_ON/OFF2_3

POWER_ON/OFF2_4

SOC_RESET

MICOM MODEL OPTION

MICOM_MHL

MICOM_GED

R3016 10K

R3020 10K

MICOM_GP4_10PIN

R3030 10K

Don’t remove R3014,
Not making P40 floated

R3014 1K

R3011 10K

MICOM_DEBUG

+3.5V_ST

MICOM_PDP

R3007 10K

R3005 10K

MICOM_JAPAN

MICOM_TOUCH_KEY

R3009 10K

MICOM_DEBUG

MICOM_RESET

R3005-*1

R3012 10K

MICOM_OLED_MAIN

MICOM_LOGO_LIGHT

R3005-*2

56K

MICOM_OLED_FRC

MODEL1_OPT_0
MODEL1_OPT_1
MODEL1_OPT_2
MODEL1_OPT_3
MODEL1_OPT_4

MODEL1_OPT_5
MODEL1_OPT_6

+3.3V_NORMAL

R3035

4.7K

MICOM MODEL OPTION

POWER_ON/OFF2_3

I2C_SCL3

I2C_SDA3

AMP_RESET_N

PANEL_CTL

MODEL1_OPT_5

HDMI_CEC

POWER_ON/OFF2_2

POWER_ON/OFF2_3

EEPROM_SDA

EEPROM_SCL

MODEL1_OPT_6

AMP_RESET_BY_MICOM

IR

+3.5V_ST

R3018

3.3K

+3.3V_NORMAL

R3032

10K

R3033

10K

R3003 22

AMP_RESET_BY_MICOM

P31/TI03/TO03/INTP4

P75/KR5/INTP9/SCK01/SCL01

P74/KR4/INTP8/SI01/SDA01

P71/KR1/SI21/SDA21

P70/KR0/SCK21/SCL21

P30/INTP3/RTC1HZ/SCK11/SCL11

R3019

3.3K

FLG_POD_DR

POD_WAKEUP_N

/RST_DIIVA

/RST_DIIVA

POD_WAKEUP_N

FLG_POD_DR

for DiiVA

+3.5V_ST

C3000

0.1uF

P60/SCLA0
P61/SDAA0

P62
P63

P73/KR3/SO01
P72/KR2/SO21

R3002 22

MICOM_DIIVA

R3001 22

MICOM_DIIVA

VDD

48

1
2
3
4
5
6
7
8
9
10
11
12

13

GND

VSS

47

14

C3001 0.47uF

REGC

46

15

OPT

8pF

C3002

C3003 8pF

X3000

32.768KHz
R3023

4.7M
OPT

P124/XT2/EXCLKS

P123/XT1

P137/INTP0

P122/X2/EXCLK

P121/X1

41

42

43

44

45

IC3000

R5F100GEAFB

MICOM

16

17

18

19

20

MICOM_DEBUG

LOGO_LIGHT

MICOM_RESET

MICOM_DIIVA

R3024 22

P41/TI07/TO07

P40/TOOL0

RESET

38

39

40

21

22

23

P146

10K

R3000

LOGO_LIGHT

+3.5V_ST

R3025 22

C3004

0.1uF
16V

P120/ANI19

37

36
35
34
33
32
31
30
29
28
27
26
25

24

12V_EXT_PWR_DET

HDMI_WAUP:HDMI_INIT

10K

MICOM_RESET_SW

SW3000

R3026

JTP-1127WEM

12

4 3

R3027

270K

OPT

P140/PCLBUZ0/INTP6
P00/TI00/TXD1
P01/TO00/RXD1

For Japan:LNB_INIT

P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7

POWER_ON/OFF2_4

RL_ON

SCART_MUTE

POWER_ON/OFF2_4





KEY2

KEY1

MODEL1_OPT_2

MODEL1_OPT_1

MODEL1_OPT_0

MODEL1_OPT_4

MODEL1_OPT_3

EXT_AMP_MUTE

EXT_AMP_RESET

COMMERCIAL_12V_CTL

12V_EXT_PWR_DET

SCART_MUTE

+3.3V_NORMAL

+3.3V_NORMAL

R3036

10K

OPT

R3037

10K

OPT

POWER_ON/OFF2_1

SIDE_HP_MUTE

10

P147/ANI18

P10/SCK00/SCL00

/ OLED

LOGO_LIGHT

JAPAN

TOUCH_KEY

PDP

IR Wafer

10Pin

(GP4_TOOL)

MHLMODEL_OPT_5

GEDMODEL_OPT_6

For LM86

For JAPAN

For Sample Set

GP4_HIGH

P17/TI02/TO02

P51/INTP2/SO11

P50/INTP1/SI11/SDA11

P16/TI01/TO01/INTP5

P13/TXD2/SO20

P14/RXD2/SI20/SDA20

P12/SO00/TXD0/TOOLTXD

P15/PCLBUZ1/SCK20/SCL20

P11/SI00/RXD0/TOOLRXD/SDA00

R30 22 10K

MODEL_OPT_0

MODEL_OPT_1

22K

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

NON LOGO_LIGHT

NON JAPAN

TACT_KEY

LCD

IR Wafer
12/15Pin

(GP3_Soft touch)

NON_MHL

NON_GED

R3006 10K

R3008 10K

R3010 10K

R3021 10K

R3017 10K

MICOM_NON_MHL

MICOM_NON_GED

R3031 10K

MICOM_LCD/OLED

MICOM_GP3_12/15PIN

MICOM_TACT_KEY

R3013 10K

MICOM_NON_JAPAN

MICOM_NON_LOGO_LIGHT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Eye Sensor Option

MODEL_OPT_4

MODEL_OPT_2

0

1

0

N/A

CM3231_CAPELLA

(GP3 Soft touch) (GP4 Soft touch)

1

MC8101_ABOV

(TACT_KEY)

CM3231_CAPELLA

POWER_ON/OFF1

+3.3V_NORMAL

R3034

4.7K

POWER_DET

OPT

COMMERCIAL_12V_CTL

LED_B/GP4_LED_R

B

SOC_RESET

C

Q3000
MMBT3904(NXP)

EDID_WP

E

SOC_TX

AMP_MUTE

EDID_WP

EXT_AMP_RESET

EXT_AMP_MUTE

CEC_REMOTE

BAT54_SUZHO

SOC_RX

INV_CTL

D3000

D

G

S

For CEC

+3.5V_ST

R3028
27K

Q3001-*1
SI1012CR-T1-GE3
HDMI_CEC_FET_VISHAY

G

D

S

Q3001
RUE003N02

HDMI_CEC_FET_ROHM

R3029

120K

HDMI_CEC

2011.12.12

MICOM

30

BODY_SHIELD

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

20

HP_DET

19

5V

18

GND

17

DDC_DATA

16

DDC_CLK

15

ARC

14

CE_REMOTE

13

CK-

12

CK_GND

11

CK+

10

D0-

9

D0_GND

8

EAG62611204

51U019S-312HFN-E-R-B-LG

EAG62611204

51U019S-312HFN-E-R-B-LG

EAG62611204

51U019S-312HFN-E-R-B-LG

JK3202

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11
10

9

8

7

6

5

4

3

2

1

JK3200

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11
10

9

8

7

6

5

4

3

2

1

JK3201

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

HP_DET

5V

GND

DDC_DATA

DDC_CLK

NC

CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

HP_DET

5V

GND

DDC_DATA

DDC_CLK

NC

CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

5V_HDMI_2

5V_HDMI_3

HDMI_HPD_1

R3207 0

R3208 0

CEC_REMOTE

CK-_HDMI1

CK+_HDMI1

D0-_HDMI1

D0+_HDMI1

D1-_HDMI1

D1+_HDMI1

D2-_HDMI1

D2+_HDMI1

DDC_SDA_1

DDC_SCL_1

HDMI1 With ARC

HDMI_HPD_2

R3209
0

R3210
0

R3204
0

R3205
0

DDC_SDA_2

DDC_SCL_2

HDMI_HPD_3

DDC_SDA_3

DDC_SCL_3

5V_HDMI_1

R3248

1K

OPT

R3249

3.9K

OPT

C3202

1uF

10V

HDMI2

HDMI3

SPDIF_OUT_ARC

OPT

C3226

0.1uF
16V

CEC_REMOTE

CK-_HDMI2

CK+_HDMI2

D0-_HDMI2

D0+_HDMI2

D1-_HDMI2

D1+_HDMI2

D2-_HDMI2

D2+_HDMI2

CEC_REMOTE

CK-_HDMI3

CK+_HDMI3

D0-_HDMI3

D0+_HDMI3

D1-_HDMI3

D1+_HDMI3

D2-_HDMI3

D2+_HDMI3

ARC

BODY_SHIELD

GND

20

HP_DET

19

5V

18

GND

17

DDC_DATA

16

DDC_CLK

15

NC

14

CE_REMOTE

13

CK-

12

CK_GND

11

CK+

10

D0-

9

D0_GND

8

EAG62611204

51U019S-312HFN-E-R-B-LG

JK3203

+5V_NORMAL

D3200

R3217

47K

+5V_NORMAL

D3201

R3218
47K

7

6

5

4

3

2

1

5V_HDMI_3

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

5V_HDMI_1

A2CA1

A2CA1

R3219
47K

R3220
47K

5V_HDMI_4

DDC_SDA_1

DDC_SCL_1

DDC_SDA_3

DDC_SCL_3

CEC_REMOTE

CK-_HDMI4

CK+_HDMI4

D0-_HDMI4

D0+_HDMI4

D1-_HDMI4

D1+_HDMI4

D2-_HDMI4

D2+_HDMI4

+5V_NORMAL

D3202

R3225

47K

+5V_NORMAL

D3203

R3226
47K

R3222
0

R3223
0

5V_HDMI_2

5V_HDMI_4

33

34

36

37

38

40

41

42

DSDA135DSCL1

DSDA339DSCL3

DSDA443DSCL4

R0PWR5V

R1PWR5V

R3PWR5V

CBUS_HPD1

CBUS_HPD3

HDMI_INT

I2C_SCL5

I2C_SDA5

10K

10K

R3203

R3242
10

C3221

C3222

1uF

10uF

10V

10V

12V_EXT_PWR_DET

VDD12_368ARC69TX2P70TX2N71TX1P72TX1N73TX0P74TX0N75TXCP76TXCN77TCVDD1278TPVDD1279R0XCN80R0XCP81R0X0N82R0X0P83R0X1N84R0X1P85R0X2N86R0X2P87AVDD12_388VDD33_2

67

RSVDL

66

SPDIF_IN

65

INT

64

CSCL

63

CSDA

62

RESET_N

61

TPWR

60

GPIO1

59

GPIO0

58

CD-SENSE4

57

CD_SENSE3

56

GPIO2

55

CD_SENSE1

54

CD_SENSE0

53

WKUP

52

LPSBV

51

PWRMUX_OUT

50

SBVCC5

49

R5PWR5V[VGA]

48

DSCL5[VGA]

47

DSDA5[VGA]

46

R4PWR5V

45

44

CBUS_HPD4

SPDIF_OUT

HDMI_S/W_RESET

MHL_DET

R3244

HDMI_WKUP

RGB_5V

RGB_DDC_SCL

RGB_DDC_SDA

[EP]GND

UD

R1XCN

1

R1XCP

2

THERMAL

R1X0N

3

89

R1X0P

4

R1X1N

1/16W
R3213

5.1K
5%

C3212

1uF
10V

R1X1P
R1X2N
R1X2P

AVDD12_1

VDD12_1

R3XCN
R3XCP
R3X0N
R3X0P
R3X1N
R3X1P
R3X2N
R3X2P

AVDD12_2

VDD33_1

R4XCN
R4XCP

10K

R3202

R3224 33

R3211 33

R3236 33

R3237 33

R3214 33

+5V_NORMAL

C3215

0.1uF

16V

OPT

R3215 33

R3212 33

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23

R4X0N24R4X0P25R4X1N26R4X1P27R4X2N28R4X2P

OPT

C3218
10uF
10V

IC3201-*1

SII9587CNUC-3

29

30

32

DSDA031DSCL0

VDD12_2

CBUS_HPD0

+3.3V_NORMAL

IC3202

[EP]

HDMI_HPD_4

DDC_SDA_4

DDC_SCL_4

R3243
1K

1/16W
5%

5.6V

D3207

A2CA1

R3228
47K

DDC_SDA_2

DDC_SCL_2

+3.5V_ST

A2CA1

D3205

R3229

47K

DDC_SDA_4

DDC_SCL_4

A2CA1

+3.3V_NORMAL

C3200
10uF
10V

C3223

0.047uF
25V

Q3200
MMBT3904(NXP)

L3200
BLM18PG121SN1D

5V_HDMI_4

MBR230LSFT1G

Limit 0.8A

+3.5V_ST

R3246

B

D3206

30V

1/10W

R3200

62K

1/10W

OPT

Limit 0.8A

10K

R3247
10K

B

C

E

C3205
10uF
10V

IC3200

AZ1117BH-1.2TRE1

IN

2

3

1

GND/ADJ

TPS2554

FAULT

OUT_2

OUT_1

ILIM0

ILIM1

R3201

62K

E

MMBT3906(NXP)

C

10

9

8

7

6

Q3201

THERMAL

11

1

2

3

4

5

MHL_DET

GND

IN_1

IN_2

ILIM_SEL

EN

HDMI2

HDMI3

C3211

C3210

0.1uF

0.1uF

16V

16V

OUT

C3201

C3203

10uF

10uF

10V

10V

Vout=0.8*(1+R1/R2)

+5V_NORMAL

C3208

0.1uF

5%

5%

1/16W

220K

1/16W

R3245

R3206

C

10K

HDMI4 With MHL

CK-_HDMI2

CK+_HDMI2

D0-_HDMI2

D0+_HDMI2

D1-_HDMI2

D1+_HDMI2

D2-_HDMI2

D2+_HDMI2

CK-_HDMI3

CK+_HDMI3

D0-_HDMI3

D0+_HDMI3

D1-_HDMI3

D1+_HDMI3

D2-_HDMI3

D2+_HDMI3

C3206

0.1uF
16V

C3204

C3207

0.1uF

0.1uF

16V

16V

D3204

A1

A2

L3201

BLM18PG121SN1D

C3216
10uF
10V

MHL_DET

R1XCN
R1XCP
R1X0N
R1X0P
R1X1N
R1X1P
R1X2N
R1X2P

AVDD12_1

VDD12_1

R3XCN
R3XCP
R3X0N
R3X0P
R3X1N
R3X1P
R3X2N
R3X2P

AVDD12_2

VDD33_1

R4XCN
R4XCP

C3217

0.1uF
16V

HDMI1

D1-_HDMI1

D0-_HDMI1

D0+_HDMI1

D1+_HDMI1

D2-_HDMI1

D2+_HDMI1

R0X0N

R0X0P

R0X1N

R0X1P

R0X2N

R0X2P

AVDD12_3

VDD33_2

[EP]GND

81

82

83

84

85

86

87

88

1
2

THERMAL

3

89
4
5
6
7
8
9
10

SII9587CNUC

11
12
13
14

Device Address : 0XB0

15
16
17
18
19
20
21
22

23

R4X0N24R4X0P25R4X1N26R4X1P27R4X2N28R4X2P

D1-_HDMI4

D0+_HDMI4

D0-_HDMI4

CK+_HDMI4

CK-_HDMI4

D2-_HDMI4

D1+_HDMI4

HDMI4

29

VDD12_2

D2+_HDMI4

30

DSDA031DSCL0

DDC_SDA_1

CK-_HDMI1

CK+_HDMI1

L3202

TPVDD12

R0XCN

R0XCP

79

80

IC3201

FHD

32

R0PWR5V

CBUS_HPD0

DDC_SCL_1

HDMI_HPD_1

C3213

L3203

TCVDD12

77

78

33

34

DSDA135DSCL1

DDC_SDA_2

5V_HDMI_1

R3231
10

1uF

HDMI_CLK-

TXCN

76

DDC_SCL_2

1/16W

R3233

5.1K
5%

HDMI S/W OUTPUT

HDMI_RX1-

HDMI_RX0-

HDMI_RX0+

TX1N

TX0P

TX0N

73

74

37

38

DSDA339DSCL3

R1PWR5V

DDC_SDA_3

5V_HDMI_2

R3232
10

C3214

1uF

HDMI_RX1+

TX1P

71

72

40

CBUS_HPD3

DDC_SCL_3

HDMI_HPD_3

1/16W

R3234

5.1K
5%

HDMI_CLK+

TXCP

75

36

CBUS_HPD1

HDMI_HPD_2

HDMI_RX2-

HDMI_RX2+

ARC69TX2P

TX2N

70

41

42

DSDA443DSCL4

R3PWR5V

DDC_SDA_4

5V_HDMI_3

R3240
10

C3220

1uF

VDD12_3

67

68

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

44

CBUS_HPD4

DDC_SCL_4

HDMI_HPD_4

1/16W

R3241

5.1K
5%

SPDIF_OUT_ARC

R3221

10

OPT

C3224

0.1uF
16V

RSVDL
SPDIF_IN
INT
CSCL
CSDA
RESET_N
TPWR
GPIO1
GPIO0
CD-SENSE4
CD_SENSE3
GPIO2
CD_SENSE1
CD_SENSE0
WKUP
LPSBV
PWRMUX_OUT
SBVCC5
R5PWR5V[VGA]
DSCL5[VGA]
DSDA5[VGA]
R4PWR5V

C3219

1uF

16V

0.1uF

C3225

HDMI_WKUP

5V_HDMI_4

R3238
10

+3.3V_NORMAL

+3.5V_ST

R3216
10

C3209

0.1uF

16V

MHL_DET

1/16W
R3239

5.1K
5%

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4

2011.10.19

HDMI 32

RGB/ PC AUDIO/ SPDIF

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

RGB PC

DSUB_VSYNC

DSUB_HSYNC

DSUB_R+

DSUB_B+

DSUB_G+

M24C02-RMN6T

E0

E1

E2

VSS

1

RGB_EDID

2

3

4

IC3600

D3615

30V
OPT

D3616
30V

OPT

RGB_5V

VCC

8

WC

7

SCL

6

SDA

5

Closed to JACK

C3633

18pF

RGB_5V

R3641

2.7K

C3634
18pF

50V

50V

A1

C

A2

MMBD6100

D3620

R3645

R3642

10K

2.7K

RGB_EDID

D3621
ADUC 5S 02 0R5L

5.5V
OPT

91010

111112121313141415

6677889

112233445

JK3603

SLIM-15F-D-2

15

5

+5V_NORMAL

R3643 22

R3644 22

D3622
ADUC 5S 02 0R5L

5.5V
OPT

NON_RGB_DEBUG

16

16

R3600

EDID_WP

RGB_DDC_SCL

RGB_DDC_SDA

0

+3.3V_NORMAL

R3646
10K

D3623

5.6V
OPT

D3600
20V
OPT

R3601

NON_RGB_DEBUG

DSUB_DET

+3.3V_NORMAL

SPDIF OUT

SPDIF_OUT

D3613-*1

5.5V

ADUC 5S 02 0R5L

ESD_MTK

RGB_DEBUG

R3602
100

SOC_RX

RGB_DEBUG

R3647
100

SOC_TX

D3601

20V

0

OPT

PC AUDIO

JK3601

KJA-PH-0-0177

5 GND

4 L

3 DETECT

1 R

R3615

33

ADUC 5S 02 0R5L

D3611

5.6V
OPT

D3612

5.6V
OPT

R3620

2.7K
OPT

D3613

5.5V

OPT

D3611-*1

ESD_MTK

D3612-*1

ESD_MTK

C3615

0.1uF
16V

PC_L_IN

5.6V

PC_R_IN

5.6V

JK3602

2F11TC1-EM52-4F

VIN

A

VCC

B

GND

C

Fiber Optic

4

SHIELD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

JACK HIGH / MID

2011.11.21

36

HP_LOUT

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

HP_ROUT

HP_DET

+3.3V_NORMAL

R3700

10K

HP_OUT

VA3700

5.6V
OPT

JK3700

KJA-PH-0-0177

5GND

4L

3DETECT

1R

EAG61030001

HP_OUT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

ESD for MTK

VA3700-*1

5.6V

ESD_MTK_HP_OUT

ESD for LG1152

VA3700-*2

5.6V

ESD_LG1152_HP_OUT

JACK_COMMON

2011.11.21

37