LG 55LW5700-SA, 65LW6500, 32LV3700, 32LV3700-SA, 65LW6500-DA Service Manual

LED LCD TV

SERVICE MANUAL

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

CHASSIS : LJ12C

MODEL : 55LW5700 55LW5700-SA

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

Internal Use Only

Printed in KoreaP/NO : MFL66981618 (1105-REV00)

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

- 2 -

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ......................................................................... 3

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 12

EXPLODED VIEW .................................................................................. 20

SVC. SHEET ...............................................................................................

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

- 3 -

SAFETY PRECAUTIONS

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1W), keep the resistor 10mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1MΩ and 5.2MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.

Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

1.5 Kohm/10W

To Instrument's
exposed 
METALLIC PARTS

Good Earth Ground
such as WATER PIPE,
CONDUIT etc.

AC Volt-meter

IMPORTANT SAFETY NOTICE

0.15uF

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

- 4 -

CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the

following servicing precautions and any of the safety precautions on
page 3 of this publication, always follow the safety precautions.
Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug or

other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an
explosion hazard.

2. Test high voltage only by measuring it with an appropriate high
voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its
assemblies.

4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10% (by volume) Acetone and 90% (by
volume) isopropyl alcohol (90%-99% strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication of
contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.

7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.

8. Use with this receiver only the test fixtures specified in this

service manual.

CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged easily
by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors and
semiconductor "chip" components. The following techniques
should be used to help reduce the incidence of component
damage caused by static by static electricity.

1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the

unit under test.

2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or
exposure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.

4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as "anti-static" can generate
electrical charges sufficient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.

6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads
electrically shorted together by conductive foam, aluminum foil
or comparable conductive material).

7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged
replacement ES devices. (Otherwise harmless motion such as
the brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity
sufficient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500°F to 600°F.

2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire­bristle (0.5 inch, or 1.25cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.

(500°F to 600°F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature

(500°F to 600°F)

b. First, hold the soldering iron tip and solder the strand against

the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the
component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

SERVICING PRECAUTIONS

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Only for training and service purposes

- 5 -

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the
circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by gently
prying up on the lead with the soldering iron tip as the solder
melts.

2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing the
IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and
solder it.

3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor
Removal/Replacement

1. Remove the defective transistor by clipping its leads as close as
possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.

Power Output, Transistor Device
Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit
board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as
possible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit
board.

3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.

Fuse and Conventional Resistor
Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.

2. Securely crimp the leads of replacement component around
notch at stake top.

3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC
connections).

1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
copper pattern. Solder the overlapped area and clip off any
excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.

1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly
connected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

1. Application range

This spec sheet is applied all of the 32”,42”,47”,55”,60”, 72”
LCD TV with LJ12C/D/E/N chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

1) Temperature: 25 ºC ± 5 ºC, CST : 40 ±5 ºC

2) Relative Humidity: 65 ± 10 %

3) Power Voltage : Standard input voltage(100-240V~, 50/60Hz)
* Standard Voltage of each product is marked by models

4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to
the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC: CE,IEC

- 6 -

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement.

4. General Specification(TV)

No Item Specification Remark

1 Receivable System 1) Digital : SBTVD /

2) Analog : NTSC / PAL-M / PAL-N

2 Available Channel 1) VHF : 02 ~ 13

2) UHF : 14 ~ 69

3) DTV : 02 ~ 69

4) CATV : 01 ~ 135
3 Input Voltage 1) AC 100 - 240V~ 50/60Hz
4 Market Central and South AMERICA
5 Screen Size 32 inch Wide(1920x1080) 32LV5500, 32LW5700

42 inch Wide(1920x1080) 42LV5500, 42LW5700
47 inch Wide(1920x1080)

47LV5500, 47LW5700 , 47LW9500

55 inch Wide(1920x1080)

55LV5500,

55LW5700,

55LW9500

72 inch Wide(1920x1080) 72LZ9700
6 Aspect Ratio 16:9
7 Tuning System FS
8 LCD Module LC320EUD-SDA1 (Vitiaz 6) 32LV5500-SD

LC420EUF-SDA1 (Vitiaz 6) 42LV5500-SD

LC470EUF-SDA1 (Vitiaz 6) 47LV5500-SD

LC550EUF-SDA1 (Vitiaz 6) 55LV5500-SD

LC320EUD-SDF1 (Vitiaz 6) 32LW5700-SA

LC420EUD-SDF1 (Vitiaz 6) 42LW5700-SA

LC470EUD-SDF1 (Vitiaz 6) 47LW5700-SA

LC470DUT-SDA1 (Vitiaz 6) 47LW9500-SA

LC550DUT-SDA1 (Vitiaz 6) 55LW9500-SA

LC470DUT-SDA1 (Vitiaz 5) 47LZ9600-SA

LC550DUT-SDA1 (Vitiaz 5) 55LZ9600-SA

LC550EUF-SDF1/SDF2(Vitiaz 6) 55LW5700-SA, 55LW6500-SA

LC720DUC-SCM1 (Vitiaz 5) 72LZ9700-SA
9 Operating Environment Temp : 0 ~ 40 deg

Humidity : ~ 80 %

10 Storage Environment Temp : -20 ~ 60 deg

Humidity : -85 %

- 7 -

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Only for training and service purposes

5. Chrominance & Luminance

5.1 LJ12C(42/47/55LW5700-SA)

No Item Min Typ Max Unit Remark

1 Max Luminance

Module

360 450 cd/m242/47/55LW5700-SA

(Center 1-point / 2D 290 360 cd/m

2

Full White Pattern) 3D 120 150

DCR 4M:1 5M:1
2 Luminance uniformity 77
2 Color coordinate RED X Typ. 0.650 Typ. 42LW5700-SA

Y -0.03 0.333 +0.03

GREEN X 0.307

Y 0.604

BLUE X 0.150

Y 0.059

WHITE X 0.279

Y 0.292

RED X Typ. 0.648 Typ. 47LW5700-SA

Y -0.03 0.332 +0.03

GREEN X 0.306

Y 0.606

BLUE X 0.150

Y 0.058

WHITE X 0.279

Y 0.292

RED X Typ. 0.651 Typ. 55LW5700-SA

Y -0.03 0.333 +0.03

GREEN X 0.307

Y 0.602

BLUE X 0.150

Y 0.060

WHITE X 0.279

Y 0.292

3. Contrast ratio 1100 1600 NORMAL

4. Color Temperature Cool 0.267 0.269 0.271 <Test Condition>

0.271 0.273 0.275 * The W/B Tolerance is ±0.015 for

Standard 0.283 0.285 0.287 Adjustment

0.291 0.293 0.295

** In the case of LED Model, Measure the color

Warm 0.311 0.313 0.315

temperature at the warm mode after heat run

0.327 0.329 0.331

T.V more than 60 minutes at Cinema mode.

- 8 -

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Only for training and service purposes

6. Component Video Input (Y, CB/PB, CR/PR)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I

2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I

3. 720*480 31.50 60 27.027 SDTV 480P

4. 720*480 31.47 59.94 27.0 SDTV 480P

5. 720*576 15.625 50* 13.5 SDTV 576I

6. 720*576 31.25 50* 13.5 SDTV 576P

7. 1280*720 37.5 50* 74.25 HDTV 720P

8. 1280*720 45.00 60.00 74.25 HDTV 720P

9. 1280*720 44.96 59.94 74.176 HDTV 720P

10. 1929*1080 28.125 50* 74.25 HDTV 1080I

11. 1920*1080 33.75 60.00 74.25 HDTV 1080I

12. 1920*1080 33.72 59.94 74.176 HDTV 1080I

13. 1920*1080 56.25 50* 148.5 HDTV 1080P

14. 1920*1080 67.500 60 148.50 HDTV 1080P

15. 1920*1080 67.432 59.94 148.352 HDTV 1080P

16. 1920*1080 27.000 24.000 74.25 HDTV 1080P

17. 1920*1080 26.97 23.976 74.176 HDTV 1080P

18. 1920*1080 33.75 30.000 74.25 HDTV 1080P

19. 1920*1080 33.71 29.97 740176 HDTV 1080P

7. RGB Input (PC)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

PC DDC

1. 640*350 31.468 70.09 25.17 EGA X

2. 720*400 31.469 70.08 28.32 DOS O

3. 640*480 31.469 59.94 25.17 VESA(VGA) O

4. 800*600 37.879 60.31 40.00 VESA(SVGA) O

5. 1024*768 48.363 60.00 65.00 VESA(XGA) O

6. 1360*768 47.712 60.015 85.50 VESA(WXGA) X

7. 1600*1200 75.00 60.00 162 VESA (UXGA) O

8. 1920*1080 67.50 60.00 148.5 HDTV 1080P O

• RGB PC Monitor Range Limits

Min Vertical Freq - 56 Hz
Max Vertical Freq - 62 Hz
Min Horiz. Freq - 30 kHz
Max Horiz. Freq - 80 kHz
Pixel Clock - 170 MHz

(* Except Brazil)

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Only for training and service purposes

- 9 -

8. HDMI input (PC/DTV)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

PC DDC

1. 640*350 31.468 70.09 25.17 EGA X

2. 720*400 31.469 70.08 28.32 DOS O

3. 640*480 31.469 59.94 25.17 VESA(VGA) O

4. 800*600 37.879 60.31 40.00 VESA(SVGA) O

5. 1024*768 48.363 60.00 65.00 VESA(XGA) O

6. 1280*768 47.776 59.870 79.5 CVT(WXGA) O

7. 1360*768 47.712 60.015 85.50 VESA (WXGA) O

8. 1280*1024 63.981 60.020 108.00 VESA (SXGA) O

9. 1600*1200 75.00 60.00 162 VESA (UXGA) O

10. 1920*1080 67.500 60.000 148.50 HDTV 1080P O

DTV

1 720*480 31.50 60 27.027 SDTV 480P

2 720*480 31.47 59.94 27.00 SDTV 480P

3 720*576 31.25 50* 13.5 SDTV 576P

4 1280*720 37.5 50* 74.25 HDTV 720P

5 1280*720 45.00 60.00 74.25 HDTV 720P

6 1280*720 44.96 59.94 74.176 HDTV 720P

7 1929*1080 28.125 50* 74.25 HDTV 1080I

8 1920*1080 33.75 60.00 74.25 HDTV 1080I

9 1920*1080 33.72 59.94 74.176 HDTV 1080I

10 1920*1080 56.25 50* 148.5 HDTV 1080P

11 1920*1080 67.500 60 148.50 HDTV 1080P

12 1920*1080 67.432 59.939 148.352 HDTV 1080P

13 1920*1080 27.000 24.000 74.25 HDTV 1080P

14 1920*1080 26.97 23.976 74.176 HDTV 1080P

15 1920*1080 33.75 30.000 74.25 HDTV 1080P

16 1920*1080 33.71 29.97 74.176 HDTV 1080P

(* Except Brazil)

• HDMI Monitor Range Limits

Min Vertical Freq - 56 Hz
Max Vertical Freq - 62 Hz
Min Horiz. Freq - 30 kHz
Max Horiz. Freq - 80 kHz
Pixel Clock - 170 MHz

- 10 -

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* Only 3DTV

9. HDMI Input(1.4a)

10. HDMI Input(1.3a)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed 3D input proposed mode

1 1920*1080 53.95 / 54 23.98 / 24 148.35/148.5 HDTV 1080P Frame packing

2 1280*720 89.9 / 90 59.94/60 148.35/148.5 HDTV 720P Frame packing

3 1280*720 75 50 148.5 HDTV 720P Frame packing

4 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side(half), Top and bottom

5 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side(half), Top and bottom,

6 1280*720 45 60 74.25 HDTV 720P Side by Side(half), Top and Bottom

7 1280*720 37.5 50 74.25 HDTV 720P Side by Side(half), Top and Bottom

8 1920*1080 33.75 60 74.25 HDTV 1080i Side by Side(half), Top and Bottom

9 1920*1080 28.125 50 74.25 HDTV 1080i Side by Side(half), Top and Bottom

10 1920*1080 27 24 74.25 HDTV 1080P Side by Side(half), Top and Bottom

11 1920*1080 33.75 30 89.1 HDTV 1080P Side by Side(half), Top and Bottom

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom

2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom

3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom

4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom

5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

6 1920*1080 33.75 30.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

7 1920*1080 67.50 60.00 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

- 11 -

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Only for training and service purposes

11. Wireless Input(1.3)

12. RGB input 3D(PC)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom

2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom

3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom

4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom

5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

6 1920*1080 33.75 30.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

7 1920*1080 67.50 60.00 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

PC DDC

1. 1920*1080 67.50 60.00 148.5 WUXGA (Reduced Blanking) (Side by Side), Top and Bottom

O

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Only for training and service purposes

- 12 -

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied all of the LJ12C/D/E/F/N
LCD TV models, which produced in manufacture department
or similar LG TV factory

2. Notice

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation

transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.

(4) The input voltage of the receiver must keep AC 100-220

V~ 50 / 60Hz.
(5) Before adjustment, execute Heat-Run for 5 minutes.

A After Receive 100% Full white pattern (06CH) then

process Heat-run

(or “8. Test pattern” condition of Ez-Adjust status)

A How to make set white pattern

1) Press Power ON button of Service Remocon

2) Press ADJ button of Service remocon. Select “8. Test
pattern” and, after select “White” using navigation
button, and then you can see 100% Full White pattern.

* In this status you can maintain Heat-Run useless any

pattern generator

* Notice: if you maintain one picture over 20 minutes

(Especially sharp distinction black with white
pattern – 13Ch, or Cross hatch pattern – 09Ch)
then it can appear image stick near black level.

3. Adjustment Items

3.1. PCB Assembly Adjustment

A MAC Address Download

A Adjust 480i Comp1
A Adjust 1080p Comp1/RGB

• If it is necessary, it can adjustment at Manufacture Line

• You can see set adjustment status at “1. ADJUST

CHECK” of the “In-start menu”

A EDID (The Extended Display Identification Data)/DDC

(Display Data Channel) download

3.2. Set Assembly Adjustment

A Color Temperature (White Balance) Adjustment
A Using RS-232C
A PING Test
A Selection Factory output option

4. PCB Assembly Adjustment

4.1. MAC Address

4.1.1. Equipment & Condition

• Play file: Serial.exe

• MAC Address edit

• Input Start / End MAC address

4.1.2 Download method

4.1.2.1 Communication Prot connection

Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port

4.1.2.2 MAC Address Download

• Com 1,2,3,4 and 115200(Baudrate)

• Port connection button click(1)

• Load button click(2) for MAC Address write.

• Start MAC Address write button(3)

• Check the OK Or NG

4.1.3 Equipment & Condition

• Each other connection to LAN Port of IP Hub and Jig

PCBA

PC(RS-232C)

RS-232C Por t

- 13 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

4.1.4 LAN inspection solution

• LAN Port connection with PCB

• Network setting at MENU Mode of TV

• Setting automatic IP

• Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC

Address.

4.1.5 LAN Port Inspection (PING Test)

4.1.5.1 Equipment setting

1) Play the LAN Port Test PROGRAM.

2) Input IP set up for an inspection to Test Program.
*IP Number : 12.12.2.2

4.1.6 LAN Port Inspection (PING Test)

1) Play the LAN Port Test Program.

2) connect each other LAN Port Jack.

3) Play Test (F9) button and confirm OK Message.

4) remove LAN CABLE

4.2. Using RS-232C

Adjust 3 items at 3.1 PCB assembly adjustments “adjustment
sequence” one after the order.

A Adjustment protocol

See ADC Adjustment RS232C Protocol_Ver1.0

A Necessary items before Adjustment items

• Pattern Generator : (MSPG-925FA)

•Adjust 480i Comp1 (MSPG-925FA:model :209 , pattern
:65) – Comp1 Mode

• Adjust 1080p Comp1 (MSPG-925FA:model :225 ,

pattern :65) – Comp1 Mode

• Adjust RGB (MSPG-925FA:model :225 , Pattern :65) –

RGB-PC Mode

* If you want more information then see the below

Adjustment method (Factory Adjustment)

A Adjustment sequence

• aa 00 00: Enter the ADC Adjustment mode.

• xb 00 40: Change the mode to Component1 (No actions)

• ad 00 10: Adjust 480i Comp

• ad 00 10: Adjust 1080p Comp

• xb 00 60: Change to RGB-PC mode(No action)

• ad 00 10: Adjust 1080p RGB

• xb 00 90: Endo of Adjustmennt

- 14 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5 Factory Adjustment

5.1 Manual Adjust Component 480i/1080p
RGB 1080p

A Summary : Adjustment component 480i/1080i and RGB

1080p is Gain and Black level setting at Analog to Digital
converter, and compensate the RGB deviation

A Using instrument

• Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator (It can output 480i/1080i
horizontal 100% color bar pattern signal, and its output
level must setting 0.7V±0.1V p-p correctly)

<Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern >

A You must make it sure its resolution and pattern cause

every instrument can have different setting

A Adjustment method 480i Comp1, Adjust 1080p Comp1/RGB

(Factory adjustment)

• ADC 480i Component1 adjustment

- Check connection of Component1

- MSPG-925FA -> Model: 209, Pattern 65

• Set Component 480i mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL”

• ADC 1080p Component1 / RGB adjustment

- Check connection both of Component1 and RGB

- MSPG-925FA -> Model: 225, Pattern 65

• Set Component 1080p mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL”

• After get each the signal, wait more a second and enter
the “IN-START” with press IN-START key of Service
remocon. After then select “7. External ADC” with
navigator button and press “Enter”.

• After Then Press key of Service remocon “Right
Arrow(VOL+)”

• You can see “ADC Component1 Success”

• Component1 1080p, RGB 1080p Adjust is same method.

• Component 1080p Adjustment in Component1 input
mode

• RGB 1080p adjustment in RGB input mode

• If you success RGB 1080p Adjust. You can see “ADC
RGB-DTV Success”

5.2 EDID (The Extended Display
Identification Data) / DDC (Display Data
Channel) Download.

A Summary

• It is established in VESA, for communication between PC
and Monitor without order from user for building user
condition. It helps to make easily use realize “Plug and
Play” function.

• For EDID data write, we use DDC2B protocol.

A Auto Download

• After enter Service Mode by pushing “ADJ” key,

• Enter EDID D/L mode.

• Enter “START” by pushing “OK” key.

=> Caution : - Never connect HDMI & D-sub Cable when

the user downloading .

- Use the proper cables below for EDID
Writing.

§ Edid data and Model option download (RS232)

- 15 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5.2.1 Manual Download

A Write HDMI EDID data

• Using instruments

- Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.

- S/W for DDC recording (EDID data write and read)

- D-sub jack

- Additional HDMI cable connection Jig.

• Preparing and setting.

- Set instruments and Jig. Like pic.5), then turn on PC and
Jig.

- Operate DDC write S/W (EDID write & read)

- It will operate in the DOS mode.

Pic.3) For write EDID data, setting Jig and another instruments.
See Working Guide if you want more information about EDID
communication.

• EDID data for Non 3DTV (Model name = LG TV )

- HDMI EDID table (0x1E : Physical Address)

1) HDMI 1 Check sum : 0x7F, 0xD9 (CEA Block 0x1E :10)

2) HDMI 2 Check sum : 0x7F, 0xC9 (CEA Block 0x1E :20)

3) HDMI 3 Check sum : 0x7F, 0xB9 (CEA Block 0x1E :30)

4) HDMI 4 Check sum : 0x7F, 0xA9 (CEA Block 0x1E :40)

- Analog (RGB) EDID table

1) RGB CheckSum : 1C

• EDID data for 3DTV ( Model name = LG TV )

- HDMI EDID table (0x1E : Physical Address)

1) HDMI 1 Check sum : 0x7F, 0xCB (CEA Block 0x1E :10)

2) HDMI 2 Check sum : 0x7F, 0xBB (CEA Block 0x1E :20)

3) HDMI 3 Check sum : 0x7F, 0xAB (CEA Block 0x1E :30)

4) HDMI 4 Check sum : 0x7F, 0x9B (CEA Block 0x1E :40)

- Analog (RGB) EDID table

1) CheckSum : 1C

PC

VSC

B/D

- 16 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5.3 Adjustment Color Temperature (White

balance)

A Using Instruments

• Color Analyzer: CA-210 (CH 9)

- Using LCD color temperature, Color Analyzer (CA-210)
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.

• Auto-adjustment Equipment (It needs when Auto­adjustment – It is availed communicate with RS-232C :
Baud rate: 115200)

• Video Signal Generator MSPG-925F 720p, 216Gray
(Model: 217, Pattern 78)

A Connection Diagram (Auto Adjustment)

• Using Inner Pattern

• Using HDMI input

<Pic.5 Connection Diagram for Adjustment White balance>

A White Balance Adjustment

If you can’t adjust with inner pattern, then you can adjust it
using HDMI pattern. You can select option at “Ez-Adjust
Menu – 7. White Balance” there items “NONE, INNER,
HDMI”. It is normally setting at inner basically. If you can’t
adjust using inner pattern you can select HDMI item, and
you can adjust.

In manual Adjust case, if you press ADJ button of service
remocon, and enter “Ez-Adjust Menu – 7. White Balance”,
then automatically inner pattern operates. (In case of
“Inner” originally “Test-Pattern. On” will be selected in The
“Test-Pattern. On/Off”.

• Connect all cables and equipments like Pic.5)

• Set Baud Rate of RS-232C to 115200. It may set 115200
orignally.

• Connect RS-232C cable to set

• Connect HDMI cable to set

A RS-232C Command (Commonly apply)

• “wb 00 00”: Start Auto-adjustment of white balance.

• “wb 00 10”: Start Gain Adjustment (Inner pattern)

• “jb 00 c0” :

• …

• “wb 00 1f”: End of Adjustment
* If it needs, offset adjustment (wb 00 20-start, wb 00 2f-

end)

• “wb 00 ff”: End of white balance adjustment (inner pattern
disappear)

CA-100+

COLOR

ANALYZER

TYPE; CA-100+

Full W hite Pattern

RS-232C

-- 17 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

O Notice) Adjustment Mapping information

• When Color temperature (White balance) Adjustment
(Automatically)

- Press “Power only key” of service remocon and operate
automatically adjustment.

- Set BaudRate to 115200.

• If it needs, then adjustment “Offset”.

A White Balance Adjustment (Manual adjustment)

• Test Equipment: CA-210

- Using LCD color temperature, Color Analyzer (CA-210)
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.

• Manual adjustment sequence is like bellowed one.

- Turn to “Ez-Adjust” mode with press ADJ button of
service remocon.

- Select “10.Test Pattern” with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.

- Let CA-210 to zero calibration and must has gap more
10cm from center of LCD module when adjustment.

- Press “ADJ” button of service remocon and select
“7.White-Balance” in “Ez-Adjust” then press “

G ” button

of navigation key.

(When press “

G ” button then set will go to full white

mode)

- Adjust at three mode (Cool, Medium, Warm)

- If “cool” mode
Let B-Gain to 192 and R, G, B-Cut to 64 and then
control R, G gain adjustment High Light adjustment.

- If “Medium” and “Warm” mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.

- All of the three mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.

- With volume button (+/-) you can adjust.

- After all adjustment finished, with Enter (A key) turn to
Ez-Adjust mode. Then with ADJ button, exit from
adjustment mode

Attachment: White Balance adjustment coordination and

color temperature.

• Using CS-1000 Equipment.

- COOL : T=11000K, Δuv=0.000, x=0.276 y=0.283

- MEDIUM : T=9300K, Δuv=0.000, x=0.285 y=0.293

- WARM : T=6500K, Δuv=0.000, x=0.313 y=0.329

• Using CA-210 Equipment. (9 CH)

- Contrast value: 216 Gray

• Using CA-210 Equipment. (14 CH)

- White Balance adjustment coordination and color
temperature for Edge / IOP LED, ALEF

-White Balance adjustment table for Edge (IOP) LED

Color coordination is different according to heat run time.
LGD IOP LED, LGD EDGE LED, LGD 3D EDGE LED
(for LV5500, LW5700)

White Balance adjustment table for ALEF Model
(LW9500)

White Balance adjustment table for IOL LED MODEL
(LZ9700)

Color Coordination

Color temperature Test Equipment

x y

COOL

CA-210

CA-210

CA-210

0.269±0.002 0.273±0.002

MEDIUM

0.285±0.002 0.293±0.002

WARM

0.313±0.002 0.329±0.002

Cool 13,000k

K

o

X=0.269 (±0.002)

Y=0.273 (±0.002)

Medium 9,300k

K

X=0.285 (±0.002)

Y=0.293 (±0.002)

Color

Temperature

Warm 6,500k

K

X=0.313 (±0.002)

Y=0.329 (±0.002)

<Test Signal>

Inner pattern

(216gray,85IRE)

o

o

Aging time Cool Medium Warm

(Min) x y x y x y

GP3

269 273 285 293 313 329

1 0-2

3-5
6-9

10-19

279 308
2 278 306
3 277 305
4 276 303
5 20-35 274 300
6 36-49 272 297
7 50-79 271 295
8 80-149 270 294
9 Over 150 269

288
286
285
283
280
277
275
274
273

295
294
293
292
290
288
287
286
285

319
318
317
316
314
312
311
310
309

338
336
335
333
330
327
325
324
323293

Aging time Cool Medium Warm

(Min) x y x y x y

GP3

269 273 285 293 313 329
1 0-2

3-5
6-9

10-19

282 314
2 281 312
3 280 311
4 279 309
5 20-35 277 304
6 36-49 274 299
7 50-79 271 297
8 80-149 270 294
9 Over 150 269

294
292
291
289
284
279
277
274
273

298
297
296
295
293
290
287
286
285

322
321
320
319
317
314
311
310
309

343
341
340
338
333
328
326
323
322293

Aging time Cool Medium Warm

(Min) x y x y x y

GP3

269 273 285 293 313 329

1 0-2

3-5
6-9

10-19

278 307
2 277 305
3 276 304
4 274 302
5 20-35 272 298
6 36-49 270 295
7 50-79 269 293
8 Over80 269 293

288
286
284
282
278
275
273
273

295
294
293
291
289
287
285
285

316
315
314
313
311
309
308
308

334
332
331
329
325
322
323
323

- 18 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5.4 EYE-Q function check

1) Turn on TV

2) Press EYE key of Adj. R/C

3) Cover the Eye Q II sensor on the front of the using your
hand and wait for 6 seconds

4) Confirm that R/G/B value is lower than 10 of the “Raw Data
(Sensor data, Back lignt )” . If after 6 seconds, R/G/B value
is not lower than 10, replace Eye Q II sensor

5) Remove your hand from the Eye Q II sensor and wait for 6
seconds

6) Confirm that “ok” pop up.
If change is not seen, replace Eye Q II sensor

5.5 HDCP (High-Bandwidth Digital
Contents Protection) Setting

• No Need.

5.6 Test of RS-232C control.

Press In-Start button of Service Remocon then set the
“4.Baud Rate” to 115200. Then check RS-232C control and

5.7 Selection of Country option.

Selection of country option is allowed only North American
model (Not allowed Korean model). It is selection of Country
about Rating and Time Zone.

Models: All models which use LA75A Chassis (See the first
page.)
Press “In-Start” button of Service Remocon, then enter the
“Option” Menu with “PIP CH-“ Button
Select one of these three (USA, CANADA, MEXICO) defends
on its market using “Vol. +/-“button.

* Caution : Don’t push The INSTOP KEY after completing

the function inspection.

6. GND and ESD Testing

6.1 Prepare GND and ESD Testing.

A Check the connection between set and power cord

6.2 Operate GND and ESD auto-test.

A Fully connected (Between set and power cord) set enter the

Auto-test sequence.

A Connect D-Jack AV jack test equipment.
A Turn on Auto-controller(GWS103-4)
A Start Auto GND test.
A If its result is NG, then notice with buzzer.
A If its result is OK, then automatically it turns to ESD Test.
A Operate ESD test
A If its result is NG, then notice with buzzer.
A If its result is OK, then process next steps. Notice it with

Good lamp and STOPER Down.Check Items.

A Test Voltage

• GND: 1.5KV/min at 100mA

• Signal: 3KV/min at 100mA

A Test time: just 1 second.
A Test point

• GND test: Test between Power cord GND and Signal
cable metal GND.

• ESD test: Test between Power cord GND and Live and

neutral.

A Leakage current: Set to 0.5mA(rms)

7. Preset Ch information.

In case of POWER ONLY, System color is operated multi
system
In case of IN STOP, System color is operated default system
(PAN-M)

- 19 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

8. Default Service option.

8.1 ADC-Set.

A R-Gain adjustment Value (default 128)
A G-Gain adjustment Value (default 128)
A B-Gain adjustment Value (default 128)
A R-Offset adjustment Value (default 128)
A G-Offset adjustment Value (default 128)
A B-Offset adjustment Value (default 128)

8.2 White balance. Value.

9. USB DOWNLOAD (*.epk file
download)

9.1 Put the USB Stick to the USB socket

9.2 Press Menu key, and move OPTION

9.3 Press “FAV” Press 7 times.

9.4 Select download file (epk file)

9.5 After download is finished, remove the

USB stick.

9.6 Press “IN-START” key of ADJ remote

control, check the S/W version.

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

- 20 -

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A2

A13

A5

300

LV1

LV2

200

530

710

540

400

521

810

510

120

500

910

900

A10

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

IMPORTANT SAFETY NOTICE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

L/DIM0_VS

I2C_SCL

RESET_LG1121

I2C_SDA

XTAL_OUT

C133
27pF
50V

L/DIM0_MOSI

XTAL_IN

3D_SYNC_Out

SPI_DI

SPI_SCLK

XTAL_OUT

XTAL_IN

SPI_DO

L/DIM0_SCLK

C120
27pF
50V

R154
1M

UART_RX

SPI_CS

UART_TX

SW100

JTP-1127WEM

+3.3VD

R124

33

R140 33

R145 33

R141 33

R144 33

R142 33

R143 33

R146 33

+3.3VD

C1109

0.1uF

SPI_DI

R160
10K

R159

4.7K

SPI_CS

SPI_DO

R161

33

R162

3.3K

SPI_SCLK

INCH_OPT_1

+3.3VD

+3.3VD

OUTPUT_OPT2

+3.3VD

+3.3VD

INCH_OPT_2

OUTPUT_OPT1

R125 10K

R126 33

UART_RX

R166

33

+3.3VD

UART_TX

+3.3V_IO

+1.0AVDD

+3.3V_XTAL

+2.5LVDS_TX

+1.0VDC

+2.5LVDS_RX

+2.5AVDD

C1155

0.1uF
16V

C1119

0.1uF
16V

C1124

0.1uF
16V

C1143

0.1uF
16V

+2.5LVDS_RX

C1159
10uF
25V

+2.5AVDD

C1151

0.1uF
16V

+2.5V

C1153

0.1uF
16V

C1134

0.1uF
16V

C1118

0.1uF
16V

C1126

0.1uF
16V

C1141

0.1uF
16V

C1142

0.1uF
16V

C1135

0.1uF
16V

C1133

0.1uF
16V

C1157

0.1uF
16V

+2.5V

C1154

0.1uF
16V

C1120

0.1uF
16V

C1150
10uF
25V

C1152

0.1uF
16V

C1149
10uF
25V

+2.5V

C1158

0.1uF
16V

+2.5AVDD

C1147

0.1uF
16V

+2.5LVDS_TX

C1156

0.1uF
16V

C1148

0.1uF
16V

+2.5LVDS_TX

C1125

0.1uF
16V

+2.5LVDS_RX

R123

33

P101

12507WR-04L

1

2

3

4

5

TDO
TDI
TCK
TMS

+3.3VD

TDO

TDI

TMS

TCK

R163 33

R164 33

R165 33R136 33

R137 33
R138 33

C105
33pF
50V
OPT

C104
33pF
50V

OPT

C102
33pF
50V
OPT

R151

10K

MINI_LVDS

R156

10K
XTR

R153

10K

R158

10K

OUTPUT_OPT2

INCH_OPT_1

R139 33

OPT

R120

33

OPT

OUTPUT_OPT1

INCH_OPT_2

R150

10K

LVDS

R152

10K
OPT

R157

10K
OPT

R155

10K

SHARP

R116 10K

R112
100

1%

R107
100

1%

R114
100

1%

R118
100

1%

R113
100

1%

R110
100

1%

R115
100

1%

R149
100

1%

R117
100

1%

R106
100

1%

R111
100

1%

R148
100

1%

C1136

0.1uF
16V

C1140

0.1uF
16V

R167 10K
R168 10K

R170
10K

OPT

+3.3VD

GPIO_0

R172
10K

OPT

+3.3VD

GPIO_1

GPIO_0
GPIO_1

R169

10K

R171
10K

R173

10K

R175

10K

R174

10K

R147 100K

TRST_N

TRST_N

R176 33

P102

YFW254-07

OPT

1

2

3

4

5

6

7

L104

CIS21J121

L105

CIS21J121

L106

CIS21J121

R177 33

OPT

R179 33

R181 33

R180 33

C1160
33pF
50V
OPT

C1161
33pF
50V
OPT

L/DIM1_VS

L/DIM1_SCLK
L/DIM1_MOSI

C1162
33pF
50V

OPT

R1051KR109

1K

TXC2N

TXE0N

TXG1P

TXCCLKP

TXH4N

TXDCLKP

TXD2N

TXH2N

TXG4P

TXF0N

TXB2N

TXB3N

TXCCLKN

TXG1N

TXB1P

TXD2P

TXFCLKN

TXA0P

TXD4P

TXC3P

TXH3P

TXGCLKP

TXA1N

TXC0N

TXH0N

TXF4N

TXBCLKP

TXE4P

TXF2N

TXACLKP

TXA3N

TXDCLKN

TXF1N

TXG2P

TXG4N

TXF0P

TXB4P

TXG3P

TXF3P

TXA0N

TXA2N

TXD4N

TXECLKN

TXH3N

TXC4P

TXH1N

TXC1P

TXD0N

TXD1N

TXG0P

TXBCLKN

TXB2P

TXE4N

TXE3N

TXD0P

TXA3P

TXB1N

TXD3P

TXACLKN

TXA1P

TXHCLKP

TXB4N

TXF3N

TXA4P

TXE2N
TXECLKP

TXE2P

TXGCLKN

TXA2P

TXE0P

TXH0P

TXH4P

TXD1P

TXC4N

TXF1P

TXE1N

TXG0N

TXB3P

TXF2P

TXH2P

TXFCLKP

TXH1P

TXB0N

TXE1P

TXG3N

TXC2P

TXD3N

TXC3N

TXC1N

TXG2N

TXHCLKN

TXC0P

TXE3P

TXB0P

TXF4P

TXA4N

R192

33

AGP_EN

R193

33

LR_IND

R194

33

R195

47K

R196

47K

OPT

RBF

R191

33

R189
10K

+3.3VD

MODE_SEL

R190
10K

TMODE[1]

+3.3VD

R187

3.3K
R185

3.3K

R186

3.3K

3.3K
R188

R183

0

R184
1K

TMODE[1]

I2C_SDA

SPI_SCLK

TRST_N

P100

12507WR-10L

1

2

3

4

5

6

7

8

9

10

11

I2C_SCL

SPI_DO

+3.3VD

SPI_DI

SPI_CS

OUTPUT_OPT4

OUTPUT_OPT3

R1000

10K
DP

+3.3VD

R1001

10K

NON_DP

OUTPUT_OPT4

R1002

10K
OPT

R1003

10K

OUTPUT_OPT3

+3.3VD

TP1

X100

24.75MHz
4

GND_21X-TAL_1

2

GND_13X-TAL_2

C1166

0.22uF

6.3V

C179

0.1uF
16V

C1180

0.22uF

6.3V

C185

0.1uF
16V

C175

0.1uF
16V

+1.0VDC

+1.0VDC

L103

CIS21J121

+1.0V

C147

0.1uF
16V

C170

0.1uF
16V

+1.0AVDD

L102

CIS21J121

+1.0VDC

C1113
10uF
25V

+1.0AVDD

+1.0VDC

C154

0.1uF
16V

C187

0.1uF
16V

C160

0.1uF
16V

C1165

0.22uF

6.3V

C167

0.1uF
16V

C198

0.1uF
16V

C148
10uF
25V

+1.0VDC

C172

0.1uF
16V

C1117
10uF
25V

C174
10uF
25V

+3.3V_IO

C1102

0.22uF

6.3V

C111

0.1uF
16V

C1179

0.22uF

6.3V

C108

0.1uF
16V

+3.3V_XTAL

C162

0.1uF
16V

C124

0.1uF
16V

C1105

0.22uF

6.3V

+3.3V_IO

L101

CIS21J121

C1103

0.22uF

6.3V

C127

0.1uF
16V

C125

0.1uF
16V

C119

0.1uF
16V

C116

0.1uF
16V

C181
10uF
25V

+3.3V_XTAL

C1104

0.22uF

6.3V

C169
10uF
25V

+3.3VD +3.3V_IO

+3.3V_IO

C106

0.1uF
16V

L100

CIS21J121

C156

0.1uF
16V

+3.3V_IO

C1101

0.22uF

6.3V

RESET

RESET_LG1121

R103
10K

+3.3VD

R182 0

C1106

1uF

6.3V

C1107

1uF

6.3V

C1167
1uF

6.3V

C1168

1uF

6.3V

C1169
1uF

6.3V

C1170

1uF

6.3V

C1171
1uF

6.3V

C1172

1uF

6.3V

C1173

1uF

6.3V

C1174

1uF

6.3V

C1175

1uF

6.3V

C1176

1uF

6.3V

C1177

1uF

6.3V

C1178
1uF

6.3V

R102 33

Q100
KRC103S

W/P

E

B

C

FLASH_WP

R1004
33

W/P

R1005

4.7K
OPT

R1006

4.7K
OPT

+3.3VD

FLASH_WP

R1007 0

R1008 0

R1009 0

W/P

FLASH_WP

IC101

LG1121A

RXA0P

AN2

RXA0N

AN1

RXA1P

AM2

RXA1N

AM1

RXA2P

AL2

RXA2N

AL1

RXACLKP

AK2

RXACLKN

AK1

RXA3P

AJ2

RXA3N

AJ1

RXA4P

AH2

RXA4N

AH1

RXB0P

AG2

RXB0N

AG1

RXB1P

AF2

RXB1N

AF1

RXB2P

AE2

RXB2N

AE1

RXBCLKP

AD2

RXBCLKN

AD1

RXB3P

AC2

RXB3N

AC1

RXB4P

AB2

RXB4N

AB1

DPM

J2

GSP/VST/GST1

H1

H_CONV

D1

POL

E2

SOE

E1

OPT_N

F2

GSC/VGH_ODD

D2

GOE/VGH_EVEN/EO

C1

FLK/GCLK1/GCLK

J1

OPT_P/GCLK2/MCLK

H2

GCLK3/GST2

G1

GCLK4

H3

GCLK5

G2

GCLK6

F1

RMLVDS

D18

TEMPSEL0

L3

TEMPSEL1

K2

TEMPSEL2

K1

L_VSOUT_LD

E31

R_VSOUT_LD

M3

M0_SCLK

E33

M0_MOSI

E34

M1_SCLK

G33

M1_MOSI

G34

M2_SCLK

L2

M2_MOSI

M2

M3_SCLK

L1

M3_MOSI

M1

GPIO[0]

AM10

GPIO[1]/VSYNC_IN

AN10

GPIO[2]

AP10

GPIO[3]/DE_IN

AP9

GPIO[4]

AN9

GPIO[5]

AN8

GPIO[6]

AP8

GPIO[7]

AP7

GPIO[8]/DE_OUT

AN7

GPIO[9]/LED_GPIO[0]

AM7

GPIO[10]/LED_GPIO[1]

AM6

GPIO[11]

AN6

GPIO[12]

AP6

GPIO[13]

AP5

GPIO[14]/SSP0_HS

E32

GPIO[15]/SSP0_MISO

F32

GPIO[16]/SSP0_CS

F33

GPIO[17]/SSP0_INTR

F34

GPIO[18]/SCAN_BLK1

AN5

GPIO[19]/SCAN_BLK2

AN4

GPIO[20]/SCAN_BLK3

AP4

GPIO[21]/SCAN_BLK4

AP3

GPIO[22]/SCAN_BLK5

AN3

GPIO[23]/SSP1_VS

C34

GPIO[24]/SSP1_HS

G32

GPIO[25]/SSP1_MISO

H32

GPIO[26]/SSP1_CS

H33

GPIO[27]/SSP1_INTR

H34

GPIO[28]/SSP2_HS

N1

GPIO[29]/SSP2_MISO

N2

GPIO[30]/LED_VSYNC

D34

GPIO[31]/3D_SYNC_OUT

AP2

UART_RXD

T1

UART_TXD

T2

SPI_SCLK

R1

SPI_CS

R2

SPI_DI

P2

SPI_DO

P1

SDA_M

V1

SCL_M

V2

SDA_S

U1

SCL_S

U2

SMODE

W2

TMODE0

Y1

TMODE1

Y2

TMODE2

AA1

TMODE3

AA2

TRST_N

AP12

TDO

AP11

TDI

AN11

TCK

AP13

TMS

AN13

PORES_N

W1

XTALO

AP15

XTALI

AP14

TXA0P/RRV7P

A2

TXA0N/RRV7N

B2

TXA1P/RRV6P

C3

TXA1N/RRV6N

C2

TXA2P/RRV5P

B3

TXA2N/RRV5N

A3

TXACLKP/RRV4P

A4

TXACLKN/RRV4N

B4

TXA3P/RRVCLKP

C5

TXA3N/RRVCLKN

C4

TXA4P/RRV3P

B5

TXA4N/RRV3N

A5

TXB0P/RRV2P

A6

TXB0N/RRV2N

B6

TXB1P/RRV1P

C7

TXB1N/RRV1N

C6

TXB2P/RRV0P

B7

TXB2N/RRV0N

A7

TXBCLKP

A8

TXBCLKN

B8

TXB3P

C9

TXB3N

C8

TXB4P

B9

TXB4N

A9

TXC0P/RLV7P

A10

TXC0N/RLV7N

B10

TXC1P/RLV6P

C11

TXC1N/RLV6N

C10

TXC2P/RLV5P

B11

TXC2N/RLV5N

A11

TXCCLKP/RLV4P

A12

TXCCLKN/RLV4N

B12

TXC3P/RLVCLKP

C13

TXC3N/RLVCLKN

C12

TXC4P/RLV3P

B13

TXC4N/RLV3N

A13

TXD0P/RLV2P

A14

TXD0N/RLV2N

B14

TXD1P/RLV1P

C15

TXD1N/RLV1N

C14

TXD2P/RLV0P

B15

TXD2N/RLV0N

A15

TXDCLKP

A16

TXDCLKN

B16

TXD3P

C17

TXD3N

C16

TXD4P

B17

TXD4N

A17

TXE0P/LRV7P

A18

TXE0N/LRV7N

B18

TXE1P/LRV6P

C19

TXE1N/LRV6N

C18

TXE2P/LRV5P

B19

TXE2N/LRV5N

A19

TXECLKP/LRV4P

A20

TXECLKN/LRV4N

B20

TXE3P/LRVCLKP

C21

TXE3N/LRVCLKN

C20

TXE4P/LRV3P

B21

TXE4N/LRV3N

A21

TXF0P/LRV2P

A22

TXF0N/LRV2N

B22

TXF1P/LRV1P

C23

TXF1N/LRV1N

C22

TXF2P/LRV0P

B23

TXF2N/LRV0N

A23

TXFCLKP

A24

TXFCLKN

B24

TXF3P

C25

TXF3N

C24

TXF4P

B25

TXF4N

A25

TXG0P/LLV7P

A26

TXG0N/LLV7N

B26

TXG1P/LLV6P

C27

TXG1N/LLV6N

C26

TXG2P/LLV5P

B27

TXG2N/LLV5N

A27

TXGCLKP/LLV4P

A28

TXGCLKN/LLV4N

B28

TXG3P/LLVCLKP

C29

TXG3N/LLVCLKN

C28

TXG4P/LLV3P

B29

TXG4N/LLV3N

A29

TXH0P/LLV2P

A30

TXH0N/LLV2N

B30

TXH1P/LLV1P

C31

TXH1N/LLV1N

C30

TXH2P/LLV0P

B31

TXH2N/LLV0N

A31

TXHCLKP

A32

TXHCLKN

B32

TXH3P

C33

TXH3N

C32

TXH4P

B33

TXH4N

A33

IC101

LG1121A

VDD_1

F5

VDD_2

F6

VDD_3

F7

VDD_4

F9

VDD_5

F11

VDD_6

F13

VDD_7

F15

VDD_8

F17

VDD_9

F20

VDD_10

F22

VDD_11

F24

VDD_12

F26

VDD_13

F28

VDD_14

F30

VDD_15

G5

VDD_16

G30

VDD_17

H5

VDD_18

H30

VDD_19

J5

VDD_20

J30

VDD_21

K5

VDD_22

K30

VDD_23

L5

VDD_24

L30

VDD_25

M5

VDD_26

N5

VDD_27

P5

VDD_28

P30

VDD_29

R5

VDD_30

R30

VDD_31

T5

VDD_32

T30

VDD_33

U5

VDD_34

U30

VDD_35

V5

VDD_36

W5

VDD_37

Y5

VDD_38

Y30

VDD_39

AA5

VDD_40

AA30

VDD_41

AB5

VDD_42

AB30

VDD_43

AC5

VDD_44

AC30

VDD_45

AD5

VDD_46

AD30

VDD_47

AE5

VDD_48

AE30

VDD_49

AF5

VDD_50

AF30

VDD_51

AG5

VDD_52

AG30

VDD_53

AH5

VDD_54

AH30

VDD_55

AJ5

VDD_56

AJ6

VDD_57

AJ7

VDD_58

AJ8

VDD_59

AJ9

VDD_60

AJ10

VDD_61

AJ11

VDD_62

AJ12

VDD_63

AJ17

VDD_64

AJ18

VDD_65

AJ19

VDD_66

AJ20

VDD_67

AJ21

VDD_68

AJ23

VDD_69

AJ24

VDD_70

AJ25

VDD_71

AJ27

VDD_72

AJ28

VDD_73

AJ29

VDD_74

AJ30

VDD33_1

D4

VDD33_2

D5

VDD33_3

D6

VDD33_4

D29

VDD33_5

D30

VDD33_6

D31

VDD33_7

D32

VDD33_8

D33

VDD33_9

E4

VDD33_10

F4

VDD33_11

G4

VDD33_12

H4

VDD33_13

J4

VDD33_14

K4

VDD33_15

L4

VDD33_16

M4

VDD33_17

N4

VDD33_18

P4

VDD33_19

R4

VDD33_20

T4

VDD33_21

U4

VDD33_22

V4

VDD33_23

W4

VDD33_24

Y4

VDD33_25

AA4

VDD33_26

AJ4

VDD33_27

AK4

VDD33_28

AK5

VDD33_29

AK6

VDD33_30

AK7

VDD33_31

AK8

VDD33_32

AK9

VDD33_33

AK10

VDD33_34

AK11

VDD33_35

AK12

AVDD33_XTAL

AK13

LVRX_LVDD_1

AC3

LVRX_LVDD_2

AE3

LVRX_LVDD_3

AJ3

LVRX_LVDD_4

AL3

LVTX_LVCC_1

D8

LVTX_LVCC_2

D10

LVTX_LVCC_3

D12

LVTX_LVCC_4

D14

LVTX_LVCC_5

D16

LVTX_LVCC_6

D19

LVTX_LVCC_7

D21

LVTX_LVCC_8

D23

LVTX_LVCC_9

D25

LVTX_LVCC_10

D27

AVDD10_1

AJ13

AVDD10_2

AJ14

AVDD10_3

AJ15

AVDD10_4

AJ16

AVDD25_1

AM14

AVDD25_2

AM15

AVDD25_3

AM16

IC101

LG1121A

VSS_1

B1

VSS_2

B34

VSS_3

D3

VSS_4

D7

VSS_5

D9

VSS_6

D11

VSS_7

D13

VSS_8

D15

VSS_9

D17

VSS_10

D20

VSS_11

D22

VSS_12

D24

VSS_13

D26

VSS_14

D28

VSS_15

E3

VSS_16

E5

VSS_17

E6

VSS_18

E7

VSS_19

E8

VSS_20

E9

VSS_21

E10

VSS_22

E11

VSS_23

E12

VSS_24

E13

VSS_25

E14

VSS_26

E15

VSS_27

E16

VSS_28

E17

VSS_29

E18

VSS_30

E19

VSS_31

E20

VSS_32

E21

VSS_33

E22

VSS_34

E23

VSS_35

E24

VSS_36

E25

VSS_37

E26

VSS_38

E27

VSS_39

E28

VSS_40

E29

VSS_41

E30

VSS_42

F3

VSS_43

F8

VSS_44

F10

VSS_45

F12

VSS_46

F14

VSS_47

F16

VSS_48

F18

VSS_49

F19

VSS_50

F21

VSS_51

F23

VSS_52

F25

VSS_53

F27

VSS_54

F29

VSS_55

F31

VSS_56

G3

VSS_57

G31

VSS_58

H31

VSS_59

J3

VSS_60

K3

VSS_61

M12

VSS_62

M13

VSS_63

M14

VSS_64

M15

VSS_65

M16

VSS_66

M17

VSS_67

M18

VSS_68

M19

VSS_69

M20

VSS_70

M21

VSS_71

M22

VSS_72

M23

VSS_73

M30

VSS_74

M31

VSS_75

N3

VSS_76

N12

VSS_77

N13

VSS_78

N14

VSS_79

N15

VSS_80

N16

VSS_81

N17

VSS_82

N18

VSS_83

N19

VSS_84

N20

VSS_85

N21

VSS_86

N22

VSS_87

N23

VSS_88

N30

VSS_89

N32

VSS_90

P3

VSS_91

P12

VSS_92

P13

VSS_93

P14

VSS_94

P15

VSS_95

P16

VSS_96

P17

VSS_97

P18

VSS_98

P19

VSS_99

P20

VSS_100

P21

VSS_101

P22

VSS_102

P23

VSS_103

P32

VSS_104

R3

VSS_105

R12

VSS_106

R13

VSS_107

R14

VSS_108

R15

VSS_109

R16

VSS_110

R17

VSS_111

R18

VSS_112

R19

VSS_113

R20

VSS_114

R21

VSS_115

R22

VSS_116

R23

VSS_117

R32

VSS_118

T3

VSS_119

T12

VSS_120

T13

VSS_121

T14

VSS_122

T15

VSS_123

T16

VSS_124

T17

VSS_125

T18

VSS_126

T19

VSS_127

T20

VSS_128

T21

VSS_129

T22

VSS_130

T23

VSS_131

T32

VSS_132

U3

VSS_133

U12

VSS_134

U13

VSS_135

U14

VSS_136

U15

VSS_137

U16

VSS_138

U17

VSS_139

U18

VSS_140

U19

VSS_141

U20

VSS_142

U21

VSS_143

U22

VSS_144

U23

VSS_145

U32

VSS_146

V3

VSS_147

V12

VSS_148

V13

VSS_149

V14

VSS_150

V15

VSS_151

V16

VSS_152

V17

VSS_153

V18

VSS_154

V19

VSS_155

V20

VSS_156

V21

VSS_157

V22

VSS_158

V23

VSS_159

V30

VSS_160

V31

VSS_161

V32

VSS_162

W3

VSS_163

W12

VSS_164

W13

VSS_165

W14

VSS_166

W15

VSS_167

W16

VSS_168

W17

VSS_169

W18

VSS_170

W19

VSS_171

W20

VSS_172

W21

VSS_173

W22

VSS_174

W23

VSS_175

W30

VSS_176

W32

VSS_177

Y3

VSS_178

Y12

VSS_179

Y13

VSS_180

Y14

VSS_181

Y15

VSS_182

Y16

VSS_183

Y17

VSS_184

Y18

VSS_185

Y19

VSS_186

Y20

VSS_187

Y21

VSS_188

Y22

VSS_189

Y23

VSS_190

Y32

VSS_191

AA3

VSS_192

AA12

VSS_193

AA13

VSS_194

AA14

VSS_195

AA15

VSS_196

AA16

VSS_197

AA17

VSS_198

AA18

VSS_199

AA19

VSS_200

AA20

VSS_201

AA21

VSS_202

AA22

VSS_203

AA23

VSS_204

AA32

VSS_205

AB3

VSS_206

AB4

VSS_207

AB12

VSS_208

AB13

VSS_209

AB14

VSS_210

AB15

VSS_211

AB16

VSS_212

AB17

VSS_213

AB18

VSS_214

AB19

VSS_215

AB20

VSS_216

AB21

VSS_217

AB22

VSS_218

AB23

VSS_219

AB32

VSS_220

AC4

VSS_221

AC12

VSS_222

AC13

VSS_223

AC14

VSS_224

AC15

VSS_225

AC16

VSS_226

AC17

VSS_227

AC18

VSS_228

AC19

VSS_229

AC20

VSS_230

AC21

VSS_231

AC22

VSS_232

AC23

VSS_233

AC32

VSS_234

AD3

VSS_235

AD4

VSS_236

AD32

VSS_237

AE4

VSS_238

AF3

VSS_239

AF4

VSS_240

AF32

VSS_241

AG3

VSS_242

AG4

VSS_243

AG32

VSS_244

AH3

VSS_245

AH4

VSS_246

AH32

VSS_247

AJ31

VSS_248

AJ32

VSS_249

AK3

VSS_250

AK14

VSS_251

AK15

VSS_252

AK16

VSS_253

AL4

VSS_254

AL5

VSS_255

AL6

VSS_256

AL7

VSS_257

AL8

VSS_258

AL9

VSS_259

AL10

VSS_260

AL11

VSS_261

AL12

VSS_262

AL13

VSS_263

AL14

VSS_264

AL15

VSS_265

AL16

VSS_266

AL17

VSS_267

AL18

VSS_268

AL19

VSS_269

AL20

VSS_270

AL21

VSS_271

AL22

VSS_272

AL23

VSS_273

AL24

VSS_274

AL25

VSS_275

AL26

VSS_276

AL27

VSS_277

AL28

VSS_278

AL29

VSS_279

AL30

VSS_280

AL31

VSS_281

AL32

VSS_282

AL33

VSS_283

AL34

VSS_284

AM3

VSS_285

AM4

VSS_286

AM5

VSS_287

AM8

VSS_288

AM9

VSS_289

AM11

VSS_290

AM12

VSS_291

AM13

VSS_292

AM23

VSS_293

AM25

VSS_294

AM26

VSS_295

AM30

VSS_296

AM34

VSS_297

AN12

VSS_298

AN14

VSS_299

AN15

VSS_300

AN16

IC102

MX25L4006EM2I-12G

Serial Flash

3

WP#

2

SO/SIO1

4

GND

1

CS#

5

SI/S

6

SCL

7

HOL

8

VCC

TXA1N_2D3D

TXA3N_2D3D

TXACLKN_2D3D

TXB2P_2D3D

TXB1N_2D3D

TXA0N_2D3D

TXACLKP_2D3D

TXB1P_2D3D

TXB2N_2D3D

TXA2N_2D3D

TXA1P_2D3D

TXB4N_2D3D

TXA0P_2D3D

TXBCLKN_2D3D

TXA3P_2D3D

TXB3N_2D3D

TXBCLKP_2D3D

TXB0P_2D3D

TXB3P_2D3D

TXB0N_2D3D

TXA4N_2D3D

TXB4P_2D3D

TXA2P_2D3D

TXA4P_2D3D

LG1121 GP3 2010. 10. 20

1LG1121 7

XTAL

SPI FLASH(4Mbit)

Output LVDS Data Mapping Selection

- GPIO[3] = 1 : FRC2 LVDS out

- GPIO[3] = 0 : FRC2 MINI_LVDS out

Output LVDS Data Mapping Selection

- GPIO[4] = 1 : GP3 SHARP module

- GPIO[4] = 0 : GP3 XTR T-con

UART

+2.5AVDD Decaps

+2.5VLVDS_TX Decaps

+2.5VLVDS_RX Decaps

For JTAG Interface

I2C Slave Address
0x1C (Direct access)
0x70 (In-direct access)

Serial Flash Boot Mode
GPIO[1:0]="00": 50MHz(Default Value)
"01": 20MHz
"10": 33.333MHz
"11": 25MHz

For SPI/I2C Interface

GPIO[18]=External BLU Control sync(120Hz) out
(GPIO[18],[30] connection)

GPIO[22],TP1=BLU sync Reference
(Video sync(240Hz) out monitoring)

GPIO[13:11]=Boot Code Selection
(S/W control for boot code start position)

+1.0AVDD Decaps

+1.0VDC Decaps

+3.3V_IO Decaps

Flash Memory Write Protection

Output LVDS Data Mapping Selection

- GPIO[3] = 1 : Display Port

- GPIO[3] = 0 : Non Display Port

THERMAL

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]
DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]

DDR1_DATA[0]
DDR1_DATA[1]
DDR1_DATA[2]
DDR1_DATA[3]
DDR1_DATA[4]
DDR1_DATA[5]
DDR1_DATA[6]
DDR1_DATA[7]
DDR1_DATA[8]
DDR1_DATA[9]
DDR1_DATA[10]
DDR1_DATA[11]
DDR1_DATA[12]
DDR1_DATA[13]
DDR1_DATA[14]
DDR1_DATA[15]

DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]
DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]

DDR0_A[0]
DDR0_A[1]
DDR0_A[2]
DDR0_A[3]
DDR0_A[4]
DDR0_A[5]
DDR0_A[6]
DDR0_A[7]
DDR0_A[8]
DDR0_A[9]
DDR0_A[10]
DDR0_A[11]
DDR0_A[12]

DDR0_DATA[0]
DDR0_DATA[1]
DDR0_DATA[2]
DDR0_DATA[3]
DDR0_DATA[4]
DDR0_DATA[5]
DDR0_DATA[6]
DDR0_DATA[7]
DDR0_DATA[8]
DDR0_DATA[9]
DDR0_DATA[10]
DDR0_DATA[11]
DDR0_DATA[12]
DDR0_DATA[13]
DDR0_DATA[14]
DDR0_DATA[15]

DDR0_A[0]
DDR0_A[1]
DDR0_A[2]
DDR0_A[3]
DDR0_A[4]
DDR0_A[5]
DDR0_A[6]
DDR0_A[7]
DDR0_A[8]
DDR0_A[9]
DDR0_A[10]
DDR0_A[11]
DDR0_A[12]

DDR0_DATA[0]
DDR0_DATA[1]
DDR0_DATA[2]
DDR0_DATA[3]
DDR0_DATA[4]
DDR0_DATA[5]
DDR0_DATA[6]
DDR0_DATA[7]

DDR1_DATA[0]
DDR1_DATA[1]
DDR1_DATA[2]
DDR1_DATA[3]
DDR1_DATA[4]
DDR1_DATA[5]
DDR1_DATA[6]
DDR1_DATA[7]

DDR1_DATA[9]
DDR1_DATA[10]

DDR1_DATA[14]

DDR1_DATA[8]

DDR1_DATA[12]

DDR1_DATA[15]

DDR1_DATA[11]

DDR1_DATA[13]DDR0_DATA[13]

DDR0_DATA[11]

DDR0_DATA[14]

DDR0_DATA[9]

DDR0_DATA[8]

DDR0_DATA[12]

DDR0_DATA[10]

DDR0_DATA[15]

DDR0_A[2]

DDR0_A[3]

DDR0_A[7]

DDR0_A[10]

DDR0_A[12]

DDR0_A[13]

DDR0_A[9]

DDR0_A[1]

DDR0_A[0]

DDR0_A[6]

DDR0_A[8]

DDR0_A[4]

DDR0_A[11]

DDR0_A[5] DDR1_A[5]

DDR1_A[4]

DDR1_A[9]

DDR1_A[3]

DDR1_A[1]

DDR1_A[6]

DDR1_A[8]

DDR1_A[13]

DDR1_A[0]

DDR1_A[10]

DDR1_A[7]

DDR1_A[11]

DDR1_A[2]

DDR1_A[12]

C224

0.1uF

DDR1_BA[0]
DDR1_BA[1]

DDR0_DQS[1]

DDR0_DQS_N[0]

C205

0.1uF

DDR0_CLKN

DDR1_DQS[0]

C235

0.1uF

DDR1_DM[1]

DDR1_BA[0]

DDR1_CASN

C208

0.1uF

C222

0.1uF

R219 240

1%

DDR0_DQS[0]

DDR1_ODT

DDR0_DM[1]

C226

0.1uF

C231

0.1uF

DDR1_WEN

C214

0.1uF

DDR0_CKE

DDR1_RASN

DDR0_CLK

DDR1_CASN

DDR1_ODT

DDR0_CLK

DDR0_DM[0]

DDR0_CASN

DDR1_DQS_N[0]

DDR1_CLKN

DDR0_BA[2]

DDR0_ODT

C200

10uF
10V

DDR1_CKE

DDR1_CLKN

DDR0_BA[2]

DDR1_DQS[1]

DDR1_DM[0]

DDR1_RASN

DDR1_WEN

C227

0.1uF

C211

0.1uF

DDR0_BA[1]

C284

0.1uF

C216

0.1uF

DDR1_DM[0]

DDR0_WEN

DDR1_CKE

C213

0.1uF

DDR0_RESET_N

C225

0.1uF

C230

0.1uF

C219

0.1uF

DDR1_DM[1]

DDR1_BA[1]

DDR1_CLK

DDR0_DQS_N[1]

DDR0_WEN

R228

240 1%

DDR0_RASN

DDR0_DQS_N[1]

DDR0_BA[0]

DDR0_CLKN

DDR1_RESET_N

R204

240 1%

DDR0_ODT

DDR1_DQS_N[1]

DDR0_DQS_N[0]

DDR0_RASN

DDR0_CASN

DDR0_CKE

DDR0_RESET_N

C228

0.1uF

DDR0_DM[0]

DDR0_BA[1]

DDR1_CLK

DDR1_DQS[1]

DDR1_BA[2]

DDR1_DQS_N[0]

C204

0.1uF

DDR1_BA[2]

C221

0.1uF

R214 240

1%

C229

0.1uF

DDR1_DQS[0]DDR0_DQS[0]

DDR1_DQS_N[1]

DDR0_DQS[1]

DDR0_BA[0]

C279

0.1uF

DDR0_DM[1]

C218

0.1uF

DDR1_RESET_N

DDR0_A[0-13]

DDR0_DATA[0-15]

DDR1_A[0-13]

DDR1_DATA[0-15]

DDR0_A[0-13]

DDR0_DATA[0-15]

DDR1_A[0-13]

DDR1_DATA[0-15]

AR204

68

DDR0_CASN

C207

0.1uF
16V

AR202

68

DDR0_WEN

C215

0.1uF
16V

C217

0.1uF
16V

AR200

68

C220

0.1uF
16V

C209

0.1uF
16V

DDR0_ODT

AR203

68

DDR0_BA[1]

DDR0_BA[0]

C203

0.1uF
16V

AR201

68

R205

68

DDR0_RASN

C212

0.1uF
16V

DDR0_BA[2]

AR207

68

C296

0.1uF
16V

C289

0.1uF
16V

DDR1_BA[1]

DDR1_BA[2]

DDR1_BA[0]

DDR1_ODT

AR205

68

C1203

0.1uF
16V

R229

68

DDR1_WEN

AR206

68

C293

0.1uF
16V

DDR1_CASN

DDR1_RASN

C298

0.1uF
16V

C1201

0.1uF
16V

C291

0.1uF
16V

AR209

68

AR208

68

C250
1000pF

R213
1K
1%

R211
1K
1%

C237

0.1uF

C245

0.1uF

R209
1K
1%

C246

0.1uF

R206
1K
1%

R208

1K
1%

C249

1000pF

R207
1K
1%

R212

1K
1%

C242

1000pF

C241

1000pF

C238

0.1uF

R210
1K
1%

R217
1K
1%

R215
1K
1%

C264

1000pF

R220
1K
1%

C260

0.1uF

C269

0.1uF

C273
1000pF

R221
1K
1%

R216

1K
1%

R218

1K
1%

C261

0.1uF

R222

1K
1%

C270

0.1uF

C265

1000pF

R223
1K
1%

C274

1000pF

+0.75V_VREF0_D0

+0.75V_VREF0_D1 +0.75V_VREF1_D1+0.75V_VREF1_D0

+1.5VQ0

+0.75V_VTT1

+0.75V_VREF1_D0

+1.5VQ1+1.5VQ1

+1.5VQ1

+0.75V_VTT1

+1.5V1+1.5VQ1

+1.5VQ1 +0.75V_VREF1_D1

+1.5VQ0+1.5VQ0 +1.5V0

+1.5VQ0

+0.75V_VREF0_M1

+1.5VQ0

+0.75V_VREF0_D1+0.75V_VREF0_D0

+1.5VQ0 +0.75V_VREF0_M0

+0.75V_VTT0

+1.5VQ1

+0.75V_VREF1_M1

+0.75V_VREF1_M0

+0.75V_VREF1_D0

+1.5VQ1

+0.75V_VREF1_D1

+0.75V_VREF0_D0

+0.75V_VREF0_D1

+1.5VQ0

+0.75V_VREF0_M0

+0.75V_VREF0_M1

L202

CIC21J501NE

L203

CIC21J501NE

+1.5VQ0

+1.5VQ0

R200

10K

R226

10K

+1.5VQ1

+0.75V_VREF1_M1

DDR0_A[0-13]

DDR1_A[0-13]

C253

0.1uF
16V

C257

0.1uF
16V

C276

0.1uF
16V

C281

0.1uF
16V

+0.75V_VTT0

R203

1001%

R227

100

1%

+0.75V_VREF1_M0

C287
10uF

R201

10K

C288

0.1uF

C201
10uF

+3.3VD

+0.75V_VTT0

C202
10uF

C290
4700pF

R202

10K

C206
10uF

C223

1000pF

+1.5VQ0

C210
10uF

+0.75V_VTT1

R224
10K

+3.3VD

C1224
4700pF

+1.5VQ1

C1219
10uF

C294
10uF

C1222
10uF

C1221

1000pF

C1218
10uF

C1220
10uF

C1223

0.1uF

R225

10K

L204

CIS21J121

L205

CIS21J121

L206

CIS21J121

L207

CIS21J121

C1227

0.1uF

C1207

0.1uF

C1225

0.1uF

C1226

0.1uF

C1233

0.22uF

6.3V

C1229

0.22uF

6.3V

C244

0.1uF

C1231

0.22uF

6.3V

C1234

0.22uF

6.3V

C1235

0.22uF

6.3V

C1228

0.22uF

6.3V

C1230

0.22uF

6.3V

C1232

0.22uF

6.3V

+1.5VQ1

+1.5VQ0

C247

0.1uF

C1236

0.22uF

6.3V

C259

0.1uF

C292

10uF
10V

C1206

0.1uF

C1205

0.1uF

C1202

0.1uF

C1215

0.1uF

C297

0.1uF

C1200

0.1uF

C1212

0.1uF

+1.5VQ1

C1210

0.1uF

H5TQ1G63DFR-PBC

IC201

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

NC_6

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

H5TQ1G63DFR-PBC

IC202

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

NC_6

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

C1237
1uF

6.3V

C1238

1uF

6.3V

IC200

TPS51200DRCR

3

VO

2

VLDOIN

4

PGND

1

REFIN

5

VOSNS

6

REFOUT

7

EN

8

GND

9

PGOOD

10

VIN

11

[EP]

IC203

TPS51200DRCR

3

VO

2

VLDOIN

4

PGND

1

REFIN

5

VOSNS

6

REFOUT

7

EN

8

GND

9

PGOOD

10

VIN

11

[EP]

IC101

LG1121A

DDR0_A[0]

AJ33

DDR0_A[1]

J34

DDR0_A[2]

AK34

DDR0_A[3]

AG33

DDR0_A[4]

K34

DDR0_A[5]

AG34

DDR0_A[6]

K33

DDR0_A[7]

AH33

DDR0_A[8]

K32

DDR0_A[9]

AK33

DDR0_A[10]

L34

DDR0_A[11]

J33

DDR0_A[12]

L32

DDR0_A[13]

AJ34

DDR0_A[14]

J32

DDR0_DQ[0]

AB33

DDR0_DQ[1]

P34

DDR0_DQ[2]

AB34

DDR0_DQ[3]

P33

DDR0_DQ[4]

AC34

DDR0_DQ[5]

N33

DDR0_DQ[6]

AC33

DDR0_DQ[7]

N34

DDR0_DQ[8]

T34

DDR0_DQ[9]

Y33

DDR0_DQ[10]

R34

DDR0_DQ[11]

AA33

DDR0_DQ[12]

U33

DDR0_DQ[13]

Y34

DDR0_DQ[14]

T33

DDR0_DQ[15]

W34

DDR0_CK

M34

DDR0_CK_N

M33

DDR0_DQS[0]

W33

DDR0_DQS_N[0]

V34

DDR0_DQS[1]

V33

DDR0_DQS_N[1]

U34

DDR0_CKE

M32

DDR0_WE_N

AE34

DDR0_RAS_N

AD33

DDR0_CAS_N

AD34

DDR0_ODT

AE33

DDR0_DM[0]

R33

DDR0_DM[1]

AA34

DDR0_BA[0]

AF33

DDR0_BA[1]

L33

DDR0_BA[2]

AF34

DDR0_RST_N

AH34

DDR0_ZQ_CAL

AE32

DDR0_VREF0

W31

DDR0_VREF1

N31

DDR0_VDDQ_1

J31

DDR0_VDDQ_2

K31

DDR0_VDDQ_3

L31

DDR0_VDDQ_4

P31

DDR0_VDDQ_5

R31

DDR0_VDDQ_6

T31

DDR0_VDDQ_7

U31

DDR0_VDDQ_8

Y31

DDR0_VDDQ_9

AA31

DDR0_VDDQ_10

AB31

DDR0_VDDQ_11

AC31

DDR0_VDDQ_12

AD31

DDR0_VDDQ_13

AE31

DDR0_VDDQ_14

AF31

DDR0_VDDQ_15

AG31

DDR0_VDDQ_16

AH31

DDR1_A[0]

AM17

DDR1_A[1]

AN33

DDR1_A[2]

AP16

DDR1_A[3]

AP19

DDR1_A[4]

AN32

DDR1_A[5]

AM18

DDR1_A[6]

AM32

DDR1_A[7]

AN18

DDR1_A[8]

AP33

DDR1_A[9]

AP17

DDR1_A[10]

AN31

DDR1_A[11]

AM33

DDR1_A[12]

AP32

DDR1_A[13]

AN17

DDR1_A[14]

AN34

DDR1_DQ[0]

AM22

DDR1_DQ[1]

AM28

DDR1_DQ[2]

AN22

DDR1_DQ[3]

AP29

DDR1_DQ[4]

AN21

DDR1_DQ[5]

AM29

DDR1_DQ[6]

AP22

DDR1_DQ[7]

AN29

DDR1_DQ[8]

AN27

DDR1_DQ[9]

AN24

DDR1_DQ[10]

AP28

DDR1_DQ[11]

AN23

DDR1_DQ[12]

AP27

DDR1_DQ[13]

AP24

DDR1_DQ[14]

AM27

DDR1_DQ[15]

AM24

DDR1_CK

AP30

DDR1_CK_N

AN30

DDR1_DQS[0]

AP25

DDR1_DQS_N[0]

AN25

DDR1_DQS[1]

AP26

DDR1_DQS_N[1]

AN26

DDR1_CKE

AP31

DDR1_WE_N

AP20

DDR1_RAS_N

AP21

DDR1_CAS_N

AM20

DDR1_ODT

AN20

DDR1_DM[0]

AN28

DDR1_DM[1]

AP23

DDR1_BA[0]

AM19

DDR1_BA[1]

AM31

DDR1_BA[2]

AN19

DDR1_RST_N

AP18

DDR1_ZQ_CAL

AM21

DDR1_VREF0

AJ22

DDR1_VREF1

AJ26

DDR1_VDDQ_1

AK17

DDR1_VDDQ_2

AK18

DDR1_VDDQ_3

AK19

DDR1_VDDQ_4

AK20

DDR1_VDDQ_5

AK21

DDR1_VDDQ_6

AK22

DDR1_VDDQ_7

AK23

DDR1_VDDQ_8

AK24

DDR1_VDDQ_9

AK25

DDR1_VDDQ_10

AK26

DDR1_VDDQ_11

AK27

DDR1_VDDQ_12

AK28

DDR1_VDDQ_13

AK29

DDR1_VDDQ_14

AK30

DDR1_VDDQ_15

AK31

DDR1_VDDQ_16

AK32

LG1121_DDR

2010. 10. 20

2

LG1121 GP3

7

DDR3 1.5V/0.75V Decap

- Place these caps near IC101

DDR3 1.5V/0.75V Decap

- Place these caps near IC101

DDR3 1.5V Decaps - Place these caps near Memory

DDR0 PHY VTT DDR1 PHY VTTDDR0 PHY VREF DDR1 PHY VREF

Close to REFOUT pin Close to REFOUT pin

DDR3 1.5V beCaps - Place these caps near Memory

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C307

0.1uF
16V

R314

4.3K
1%

L303

3.6uH

IC301

AP2132MP-2.5TRG1

EAN61387601

3

VIN

2

EN

4

VCTRL

1

PG

5

NC

6

VOUT

7

ADJ

8

GND

9

[EP]

R313
27K
1%

C311
2200pF

C310

0.1uF
16V
OPT

R315
10K
1%

0.1uF

C304
16V

R300

0

1/10W

C312
3300pF
50V

OPT

+2.5V

R304

1.5K
1%

C313

100pF

50V
OPT

C321

0.1uF
16V

+3.3VD

IC300

AOZ1072AI

DCDC_Old

EAN60922901

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

0.1uF

C320
16V

+1.0V

R305
1K
1%

L302

3.6uH

IC302

AOZ1024DI

EAN60660601

1

PGND

2

VIN

3

AGND

4

FB

5

COMP

6

EN

7

LX

C303

0.1uF
50V

C300
22uF
25V

+3.3VD

+3.3VD

C314
10uF
25V

C317
10uF
25V

C301
10uF
25V

C305
10uF
25V

VLCD_POWER

(+12V)

R301
10K

VLCD_POWER

(+12V)

VLCD_POWER

(+12V)

C302
10uF
10V

L301
CIS21J121

L300
CIS21J121

C329
2200pF

C332

100pF

50V
OPT

C322
10uF
25V

L306

3.6uH

VLCD_POWER

(+12V)

IC303

AOZ1072AI

DCDC_Old

EAN60922901

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

C324
10uF
25V

R323
10K
1%

L304
CIS21J121

C326

0.1uF
16V

C331
2200pF

C333

100pF

50V
OPT

C323
10uF
25V

L307

3.6uH

VLCD_POWER

(+12V)

IC304

AOZ1072AI

DCDC_Old

EAN60922901

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

C325
10uF
25V

R326
10K
1%

L305

CIS21J121

C327

0.1uF
16V

+1.5V0

+1.5V1

+2.5V

+2.5V

R319
47K

R320
47K

R306
47K

R309
47K

R308
18K

R303
47K

C308

0.1uF
16V

C309

0.1uF
16V

R322

2.7K
1%

R325

2.7K
1%

R321

6.2K
1%

R324

6.2K
1%

0.1uF

C328

16V

0.1uF

C330

16V

C342
2200pF

L309

3.6uH

R328
47K

IC305

AOZ1072AI

DCDC_Old

EAN60922901

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

0.1uF

C341

16V
C338
10uF
25V

+2.5V

R331
12K
1%

VLCD_POWER

(+12V)

C343

100pF

50V
OPT

C340

0.1uF
16V

C339
10uF
25V

R330

1.5K
1%

L308
CIS21J121

R329
2K
1%

+1.0V_2D3D

R312
10K
1%

R310

2.7K
1%

R311

1.2K
1%

C306
2200pF

50V

R302
15K

R318
15K

R307
43K

R327

5.1K

IC300-*1

AOZ1072AI-3

DCDC_Revision

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

R316
16K
1%

R317
51K
1%

C315
22uF
10V

C316
22uF
10V

C318
22uF
10V

C319
22uF
10V

C334
22uF
10V

C335
22uF
10V

C336
22uF
10V

C337
22uF
10V

C344
22uF
10V

C345
22uF
10V

IC303-*1

AOZ1072AI-3

DCDC_Revision

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

IC304-*1

AOZ1072AI-3

DCDC_Revision

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

IC305-*1

AOZ1072AI-3

DCDC_Revision

3

AGND

2

VIN

4

FB

1

PGND

5

COMP

6

EN

7

LX_1

8

LX_2

LG1121_POWER

2010. 10. 20

3

LG1121 GP3

7

R2

MAX 2.92A

MAX 435mA

MAX 405mA

Vout=0.8*(1+R1/R2)

R1

Vout=0.8*(1+R1/R2)

R1

R2

Vout=0.6*(1+R1/R2)

R1

R2

+1.0V_Normal

+3.3V_Normal

+2.5V_Normal

Vout=0.8*(1+R1/R2)

R1

R2

MAX 782mA

Vout=0.8*(1+R1/R2)

R1

R2

MAX 782mA

+1.5V_DDR0

+1.5V_DDR1

2D to 3D LG1131 Core

MAX 467mA

R2

Vout=0.8*(1+R1/R2)

R1

THERMAL

THERMAL THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

D404

100V

1N4148W

R442

3.6K
1/10W

C448

0.22uF
50V

C414
10uF
25V

V4

R443 33

R404 33

TH400
47k-ohm

L401
10uH

3.1A

C440

4.7uF
50V

VGH_S
(+27V)

C411

0.1uF
50V

C424

0.1uF
50V

R444 33

C421
10uF
25V

D405

100V

1N4148W

V13

R436
2K
1/8W
1%

OPT

R411

2.2

FLK

C450
10uF
25V

Q401
2SC3052

E

B

C

C442
10uF
25V
OPT

V17

VCC_LCM
(+3.3V)

R432

9.1K
1/8W

V12

V5

HVDD

(+8.4V)

VDD_LCM

(+16.8V)

VL

(+5V)

C436

4.7uF
50V

C412

0.1uF
50V

R439 22

C402
10uF
25V

C445

0.22uF
50V

OPT

C439
10uF
25V
OPT

C419

0.1uF
50V

C454

4.7uF
50V

C444

0.22uF
50V

OPT

V6

C429
10uF
25V
OPT

D402

40V

SMAB34

R428 33

C432
1uF
25V

R416
18K
1/10W

C430

4.7uF
50V

C405
10uF
25V

V18

R415 0

1/10W

C443

0.1uF
50V

C441

0.1uF
50V

C449

0.1uF
50V

OPT

R401 33

OPT

VDD_LCM

(+16.8V)

R424 33

C456
1uF
25V

VCOMOUT

C403
10uF
25V
OPT

R446 0

HVDD

(+8.4V)

C433
10uF
25V

R426 680

VDD_LCM
(+16.8V)

V15

C409

1uF
25V

D403

40V

SMAB34

R410
120K

VGL

(-5V)

C400
56pF
50V

R413
680

C452

4.7uF
50V

SWB

R417
18K
1/10W

R429 0

1/10W

R431
10K

C413

1000pF

HVDD

(+8.4V)

V14

R419 0

I2C_SCL

V1

L402
22uH

2.2A

D400

100V

1N4148W

VGH_S
(+27V)

VGH

(+27V)

C415

1uF
25V

C453
1uF
10V

C418
10uF
25V
OPT

C446
1uF
25V

VCC_LCM
(+3.3V)

I2C_SDA

C420
10uF
25V
OPT

R438 0

C431
10uF
25V

R409 0

1/10W

C423
10uF
25V

R425 33

VDD_LCM

(+16.8V)

R403

OPT

R400 15K

1%

R437 0

OPT

R433

0

C426
10uF
25V
OPT

C404
10uF
25V

C428

4.7uF
50V

Q400

MMBT3906(NXP)

EBC

C437
1uF
10V

R427 0

1/10W

VCC_LCM
(+3.3V)

I2C_SDA

V9

VCC_LCM
(+3.3V)

VLCD_POWER

(+12V)

VLCD_POWER

(+12V)

R445
10K

R435
0

C455

0.1uF
50V

R405

2.7K

R423 33

R406

0

1/10W

VCOMFB

C416

0.01uF
50V

C410
10uF
25V

R440 0

1/10W

CTRLP

VLCD_POWER

(+12V)

R407

OPT

VL

(+5V)

D401

100V

1N4148W

C427

0.1uF
50V

DPM

V7

VDD_LCM
(+16.8V)

I2C_SDA

R418

10K

C401
10uF
25V

R402 33

V16

C406
10uF
25V
OPT

VGH_S

(+27V)

R447 0

C447

0.22uF
50V

SWB

R430

5.1K

VCC_LCM
(+3.3V)

C417

0.1uF
50V

I2C_SCL

C451
10uF
25V

TCOMP

V3

C434
10uF
25V

R414

33K

R420 22

CTRLP

I2C_SCL

TCOMP

R441

10K

V10

GSC

V2

VCC_LCM
(+3.3V)

R448

10K

L400
22uH

C457
10uF
25V

C458
10uF
25V

VCORE

(+1.0V)

TCON_RST

R449 33

VGL_FB VGL_FB

R450 0

1/10W

R451

0

1/10W

R452

0

1/10W

R453

0

1/10W

R408
150K

1%

C422
120pF
50V

C407

0.47uF
50V

C408

0.47uF
50V

R454
10

1/10W

R455
10K

R456
10K
OPT

VCC_LCM
(+3.3V)

R412 0

L403

2.2uH

LQM2HPN2R2MG0L

C425

2200pF

50V

IC401

MAX17139

3

VL

2

TCOMP

4

AGND

1

EN1

6

PVINB3

5

AVIN

7

BST3

8

SWB3

9

OUT3

10

PGND3

11SS12

COMP

13

PGND_114PGND_2

15

SW_116SW_2

17

SWI18SWO

19

NC_1

20

CTRLP

21

VGH

22

VGL

23

NC_2

24

CTRLN

25

NC_3

26

RST

27

A0

28

SCL

29

SDA

30

VLOGIC2

31

PGND232SWB233VLOGIC134NC_435SWB1_136SWB1_237BST138PVINB12_139PVINB12_240NC_5

41

[EP]AGND

IC402

BUF08630

1

SDA

3

DVDD

7

AVDD_AVDD

9

BKSEL

10

GM1

11

GM2

12

GM3

13

GM4

14

GM5

15

GM6

16

NC_117HVDD18GM719GM820SCL

5

VCOM_OUT

8

AVDD_1

6

VCOM_FB

4

VCOM_GND

2

A0

21

EP[GND]

IC403

BUF08630

1

SDA

3

DVDD

7

AVDD_AVDD

9

BKSEL

10

GM1

11

GM2

12

GM3

13

GM4

14

GM5

15

GM6

16

NC_117HVDD18GM719GM820SCL

5

VCOM_OUT

8

AVDD_1

6

VCOM_FB

4

VCOM_GND

2

A0

21

EP[GND]

IC400

KIA3820FK

3

RE

2

VGH_M

4

CE

1

VGH

5

VDD

6

VDPM

7

GND

8

VFLK

C435
22uF
10V

C438
22uF
10V

T-Con Power/P-Gamma/GPM

2010. 10. 20

4

LG1121 GP3

7

Place Bottom

Place Bottom

Place Bottom

0xE8

Place Bottom

Place Bottom

[PMIC Block]

0xEA

[P-Gamma Block]

[GPM Block]

to prevent inrush current

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

V12

VCC_LCM

(+3.3V)

Z_OUT

GOE

C513
10uF
25V

VGL

(-5V)

C510
10uF
25V

V16

C502

0.1uF
50V

C519

0.01uF
50V

OPT_N

V5

VCOMFB

V7

V17

GSP

C506
10uF
25V

GSP

V7

V18

V3

C514
10uF
25V

H_CONV

V9

GSC

VCC_LCM
(+3.3V)

C512
10uF
25V

VGL

(-5V)

OPT_P

V12

V6

V13

V3

POL

C504
10uF
25V

VGH

(+27V)

V15

V4

V13

SOE

V5

C508
10uF
25V

GOE

Z_OUT

VCOMOUT

VCOMFB

C511
10uF
25V

VDD_LCM

(+16V)

V14

C509

0.01uF
50V

HVDD

(+8V)

V1

C518

0.1uF
50V

V10

H_CONV

C516
10uF
25V

V9

C517

0.1uF
50V

P501

104060-8017

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

81

VDD_LCM
(+16V)

V17

OPT_N

V2

VGH

(+27V)

V14

V1

P502

104060-8017

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

81

VCOMOUT

GSC

C505
10uF
25V

HVDD

(+8V)

V4

C503
10uF
25V

SOE

V2

V15

V18

C507

0.1uF
50V

V6

POL

C515
10uF
25V

V10

V16

RRV6P

RLVCLKN

RRVCLKN

RRV5P

RRV0N

RLV6P

RRV2N

RLV4P

RRVCLKP

RLV2P

RLV0P

RLV6N

RLV4N

RRV4N

RLVCLKP

RLV2N

RRV0P

RRV1P

RLV5N

RLV5P

RRV6N

RLV1P

RRV2P

RLV1N

RRV4P

RRV1N

RLV0N

RRV5N

LLV6P

LLV1N

LLVCLKP

LLV2N

LRV4P

LLV6N

LRV0P

LRV6P

LLV4N

LLVCLKN

LRV1P

LRVCLKP

LRV2N

LLV0P

LRV2P

LRVCLKN

LLV2P

LRV0N

LLV0N

LLV4P

LRV5P

LLV5P

LRV1N

LRV6N

LRV4N

LRV5N

LLV1P

LLV5N

R504

33

L/DIM0_VS

R503 33

P503

12507WR-08L

1

2

3

4

5

6

7

8

9

L/DIM1_MOSI

R506 33

L/DIM0_MOSI

P504

12507WR-08L

1

2

3

4

5

6

7

8

9

L/DIM1_SCLK

L/DIM0_SCLK

L/DIM1_VS

R505 33

I2C_SDA

I2C_SDA

I2C_SCL

I2C_SCL

MDS62110204

M1

GASKET_5.5T

MDS62110204

M2

GASKET_5.5T

MDS62110204

M3

GASKET_5.5T

MDS62110204

M4

GASKET_5.5T

MDS62110204

M5

GASKET_5.5T

MDS62110204

M6

GASKET_5.5T

RXBCLKN

C500
10uF
25V

RXB4N

RXA0P

R502 33

RXA4P

RXB1N

RXB2P

RXACLKP

RXA3N

I2C_SDA

RESET

RXB3N

RXB0N

RXA2P

I2C_SCL

R500 33

RXACLKN

RXB2N

RXB4P

RXA0N

RXA1N

P500

FI-RE51S-HFK-A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

RXA4N

L500

CIS21J121

RXBCLKP

RXB0P

RXB1P

RXA3P

RXA1P

RXB3P

3D_SYNC_Out

C501
10uF
25V

RXA2N

VLCD_POWER

(+12V)

MDS62110208

M6-*1

GASKET_4.5T

MDS62110208

M4-*1

GASKET_4.5T

MDS62110208

M2-*1

GASKET_4.5T

MDS62110208

M5-*1

GASKET_4.5T

MDS62110208

M1-*1

GASKET_4.5T

MDS62110208

M3-*1

GASKET_4.5T

MDS62110204

M7

OPT

LVDS/mini-LVDS wafer

2010. 10. 20

5

LG1121 GP3

7

[FRC-II 51P LVDS input wafer]

[LEFT FFC CONNECTOR][RIGHT FFC CONNECTOR]

[FRC-II 80P mini-LVDS output wafer] [To LED Driver]

SMD Gasket 4.5TSMD Gasket 4.5T

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

RLV1N

TXD0P

LLV0P

RRV2N

TXHCLKP

TXE1N

TXH3N

TXA0P

TXH0N

TXG0N

TXCCLKN

LLV4P

TXFCLKP

LLVCLKP

TXD4N

TXD4P

TXB2P

LRV4P

TXA3N

LLV6P

LRV6N

TXG1P

LRV1P

LLV5P

TXE2N

TXH1N

RRV0N

LLV6N

TXH2N

TXG1N

TXG3P

TXD3N

TXH1P

RRV4N

RRVCLKN

TXC0P

TXF0P

LRV4N

RLV4P

TXB1P

RLVCLKN

TXF4P

TXBCLKN

TXG2N

TXE2P

TXH4P

TXF3N

TXC3P

TXD1P

TXDCLKN

TXC3N

TXA0N

TXD0N

LRV2N

TXH4N

TXECLKP

TXB0P

TXDCLKP

LRV2P

RLV2N

TXF3P

TXF1P

RRV0P

TXD2P

RRV6P

TXA4P

RRVCLKP

LLV2N

RLV6N

TXFCLKN

TXHCLKN

TXA3P

TXA4N

TXC2N

TXE3P

TXB4N

RLV6P

TXC4N

LRV5P

TXD2N

TXA2P

TXF1N

RLV0N

TXB4P

TXGCLKN

TXB2N

LR_IND

LRV1N

TXE4N

RRV1N

RLV1P

TXE4P

RLV5P

AGP_EN

LRVCLKN

SOE

RRV1P

RRV5P

TXACLKN

RRV6N

TXE0N

TXB1N

RRV2P

TXD3P

TXF0N

RLV4N

TXG2P

TXE0P

TXACLKP

LLV1P

TXB3N

TCON_RST

RLV2P

TXF4N

TXGCLKP

RLVCLKP

TXBCLKP

TXH3P

LRV0P

TXG0P

LRV5N

RRV5N

LRV0N

LLVCLKN

TXC2P

TXE3N

TXA2N

RLV0P

TXC1P

TXF2N

TXH0P

TXD1N

TXE1P

TXA1P

RRV4P

TXB0N

TXC1N

I2C_SCL

TXH2P

TXB3P

TXC0N

TXCCLKP

TXF2P

MODE_SEL

TXG4N

LLV4N

TXC4P

TXG3N

LLV0N

LLV2P

LRVCLKP

TXECLKN

TXA1N

RLV5N

LLV5N

TXG4P

LRV6P

WP_EEPROM_TCON

LLV1N

H_CONV

POL

R602 33

FLK

R601 33

R600 33

R604 33

OPT_N

R606 33
R607 33

GSC

R603 33

R614 33

GOE

R608 33

GSP

OPT_P

R609 33

R612 33
R613 33

I2C_SDA

TCON_SDA

TCON_SCL

+3.3VDD

+1.0VDD

+3.3AVDD_RX

+3.3AVDD_TX

C609

0.1uF
16V

+3.3VDD

C633

0.1uF
16V

C651

0.1uF
16V

C605

0.1uF
16V

L600

CIS21J121

+3.3VDD

C601

0.1uF
16V

+1.0VDD

C606

0.1uF
16V

L601

CIS21J121

C602

0.1uF
16V

VCC_LCM
(+3.3V)

+1.0VDD

C659

0.1uF
16V

C661

0.1uF
16V

C660

0.1uF
16V

C603

0.1uF
16V

C607

0.1uF
16V

+3.3AVDD_RX

L602

CIS21J121

C643

0.1uF
16V

C627

0.1uF
16V

+3.3AVDD_RX

C604

0.1uF
16V

C612

0.1uF
16V

+3.3AVDD_TX+3.3AVDD_TX

L603

CIS21J121

C608

0.1uF
16V

C632

0.1uF
16V

C600

0.1uF
16V

R610 33
R611 33

TCON_SDA

TCON_SCL

WP_EEPROM_TCON

R619

10K

IC600

AT24C64D-SSHM-T

3

A2

2

A1

4

GND

1

A0

5

SDA

6

SCL

7

WP

8

VCC

P600

12507WR-03L

1

2

3

4

TCON_SDA

TCON_SCL

SW600

JTP-1127WEM

VCC_LCM
(+3.3V)

VCC_LCM
(+3.3V)

VCORE

(+1.0V)

VCC_LCM
(+3.3V)

R605 33

R617
10K

R618
10K

RBF

DPM

C676

0.22uF

6.3V

C677

0.22uF

6.3V

+3.3VDD

+3.3AVDD_TX

+1.0VDD

C670
1uF

6.3V

C671

1uF

6.3V

C672
1uF

6.3V

C673

1uF

6.3V

C674
1uF

6.3V

C675
1uF

6.3V

C678
1uF

6.3V

C679

1uF

6.3V

R6212KR620

2K

R615 15K

1%

C611

0.1uF
16V

C680
1uF
25V

C681
1uF
25V

C682
1uF
25V

IC601

LGE5811A

RXA0P

L17

RXA0N

L18

RXA1P

K18

RXA1N

K17

RXA2P

J18

RXA2N

J17

RXACLKP

H16

RXACLKN

J16

RXA3P

H17

RXA3N

H18

RXA4P

G18

RXA4N

G17

RXB0P

F16

RXB0N

G16

RXB1P

F17

RXB1N

F18

RXB2P

E18

RXB2N

E17

RXBCLKP

D16

RXBCLKN

E16

RXB3P

D17

RXB3N

D18

RXB4P

B18

RXB4N

C18

RXC0P

A17

RXC0N

B17

RXC1P

C16

RXC1N

C17

RXC2P

B16

RXC2N

A16

RXCCLKP

A15

RXCCLKN

B15

RXC3P

C14

RXC3N

C15

RXC4P

B14

RXC4N

A14

RXD0P

A13

RXD0N

B13

RXD1P

C12

RXD1N

C13

RXD2P

B12

RXD2N

A12

RXDCLKP

A11

RXDCLKN

B11

RXD3P

C10

RXD3N

C11

RXD4P

B10

RXD4N

A10

RXE0P

A9

RXE0N

B9

RXE1P

C8

RXE1N

C9

RXE2P

B8

RXE2N

A8

RXECLKP

A7

RXECLKN

B7

RXE3P

C6

RXE3N

C7

RXE4P

B6

RXE4N

A6

RXF0P

A5

RXF0N

B5

RXF1P

C4

RXF1N

C5

RXF2P

B4

RXF2N

A4

RXFCLKP

A3

RXFCLKN

B3

RXF3P

C2

RXF3N

C3

RXF4P

B2

RXF4N

A2

RXG0P

C1

RXG0N

B1

RXG1P

D1

RXG1N

D2

RXG2P

E3

RXG2N

D3

RXGCLKP

E2

RXGCLKN

E1

RXG3P

F1

RXG3N

F2

RXG4P

G3

RXG4N

F3

RXH0P

G2

RXH0N

G1

RXH1P

H1

RXH1N

H2

RXH2P

J3

RXH2N

H3

RXHCLKP

J2

RXHCLKN

J1

RXH3P

K2

RXH3N

K1

RXH4P

L1

RXH4N

L2

LLV0P

R1

LLV0N

R2

LLV1P

T1

LLV1N

U1

LLV2P

U2

LLV2N

V2

LLVCLKP

T2

LLVCLKN

T3

LLV3P

V3

LLV3N

U3

LLV4P

U4

LLV4N

V4

LLV5P

T4

LLV5N

T5

LRV0P

V5

LRV0N

U5

LRV1P

U6

LRV1N

V6

LRV2P

T6

LRV2N

T7

LRVCLKP

V7

LRVCLKN

U7

LRV3P

U8

LRV3N

V8

LRV4P

T8

LRV4N

T9

LRV5P

V9

LRV5N

U9

RLV0P

U10

RLV0N

V10

RLV1P

T10

RLV1N

T11

RLV2P

V11

RLV2N

U11

RLVCLKP

U12

RLVCLKN

V12

RLV3P

T12

RLV3N

T13

RLV4P

V13

RLV4N

U13

RLV5P

U14

RLV5N

V14

RRV0P

T14

RRV0N

T15

RRV1P

V15

RRV1N

U15

RRV2P

U16

RRV2N

V16

RRVCLKP

T16

RRVCLKN

T17

RRV3P

V17

RRV3N

U17

RRV4P

U18

RRV4N

T18

RRV5P

R17

RRV5N

R18

SOE

M1

GSP

M2

GOE

N1

GSC

P1

POL

N2

FLK

P2

DPM

L3

H_CONV

M3

OPT_P

N3

OPT_N

P3

RBF

K3

EEP_ADDR

R3

WP

K16

LR_IND

L16

AGP_EN

P17

MODE_SEL

P18

RMLVDS

R9

TEMPSEL0

L4

TEMPSEL1

P4

TEMPSEL2

R4

TMODE0

M16

TMODE1

N16

TMODE2

P16

TMODE3

R16

SCL_M

N18

SDA_M

N17

SCL_S

M18

SDA_S

M17

PORES_N

R15

IC601

LGE5811A

VDD_33_1

F14

VDD_33_2

G5

VDD_33_3

G14

VDD_33_4

H5

VDD_33_5

H14

VDD_33_6

J5

VDD_33_7

J14

VDD_33_8

K5

VDD_33_9

K14

VDD_33_10

L5

VDD_33_11

L14

VDD_33_12

M5

VDD_33_13

M14

VDD_33_14

N5

VDD_10_1

F5

VDD_10_2

G7

VDD_10_3

G8

VDD_10_4

G9

VDD_10_5

G10

VDD_10_6

G11

VDD_10_7

G12

VDD_10_8

H7

VDD_10_9

H12

VDD_10_10

J7

VDD_10_11

J12

VDD_10_12

K7

VDD_10_13

K12

VDD_10_14

L7

VDD_10_15

L12

VDD_10_16

M7

VDD_10_17

M8

VDD_10_18

M9

VDD_10_19

M10

VDD_10_20

M11

VDD_10_21

M12

RX_AVDD33_1

D6

RX_AVDD33_2

D7

RX_AVDD33_3

D8

RX_AVDD33_4

D9

RX_AVDD33_5

D10

RX_AVDD33_6

D11

RX_AVDD33_7

D12

RX_AVDD33_8

D13

RX_AVDD33_9

D14

TX_AVDD33_1

R5

TX_AVDD33_2

R6

TX_AVDD33_3

R7

TX_AVDD33_4

R8

TX_AVDD33_5

R10

TX_AVDD33_6

R11

TX_AVDD33_7

R12

TX_AVDD33_8

R13

TX_AVDD33_9

R14

GND_1

D4

GND_2

D5

GND_3

D15

GND_4

E4

GND_5

E5

GND_6

E6

GND_7

E7

GND_8

E8

GND_9

E9

GND_10

E10

GND_11

E11

GND_12

E12

GND_13

E13

GND_14

E14

GND_15

E15

GND_16

F4

GND_17

F15

GND_18

G4

GND_19

G15

GND_20

H4

GND_21

H8

GND_22

H9

GND_23

H10

GND_24

H11

GND_25

H15

GND_26

J4

GND_27

J8

GND_28

J9

GND_29

J10

GND_30

J11

GND_31

J15

GND_32

K4

GND_33

K8

GND_34

K9

GND_35

K10

GND_36

K11

GND_37

K15

GND_38

L8

GND_39

L9

GND_40

L10

GND_41

L11

GND_42

L15

GND_43

M4

GND_44

M15

GND_45

N4

GND_46

N14

GND_47

N15

GND_48

P5

GND_49

P6

GND_50

P7

GND_51

P8

GND_52

P9

GND_53

P10

GND_54

P11

GND_55

P12

GND_56

P13

GND_57

P14

GND_58

P15

XTR T-Con block 6

LG1121 GP3

7

2010. 10. 20

+3.3VDD Decaps

+1.0VDD Decaps

+3.3AVDD_RX Decaps

+3.3AVDD_TX Decaps

I2C Slave Address : 0xA6

- Write Protection
HIGH : Write Protection
LOW or NC : Normal Operation

[T-Con EEPROM[64KBIT)]

[T-Con EEPROM Debug]

<- EEPROM Address = 0xA6

2. LR_IND

- Left/Right frame Indicator
LOW : Left
HIGH : Right

3. AGP_EN

- NO input indicator
LOW : Normal
HIGH : No input

4. MODE_SEL

- 2D/3D mode selection
LOW : 2D mode
HIGH : 3D mode

1. RBF

- Pattern selection of No Video input
LOW : Rolling Pattern
HIGH : Black Pattern

I2C Slave Address : 0x72

LG5811 will be change LG5811A.
Please use LG5811 unitil revision.

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

I2C_SDA

SW700

JTP-1127WEM

RXB4P

RXB3N

RXB0P

RXB2P

RXB4N

RXB0N

RXB1N

RXB2N

RXBCLKP

RXB1P

RXBCLKN

RXB3P

RXA3N

RXA3P

RXA0N

RXA1N
RXA0P

RXA4N

RXA1P

RXA2P

RXA4P

RXACLKN

RXA2N

RXACLKP

TXA4N_2D3D
TXA3P_2D3D

TXA2N_2D3D

TXA1N_2D3D

TXACLKN_2D3D

TXA0P_2D3D

TXACLKP_2D3D

TXA1P_2D3D

TXA2P_2D3D

TXA3N_2D3D

TXA4P_2D3D

TXA0N_2D3D

TXB2N_2D3D

TXB1N_2D3D

TXB3N_2D3D

TXB0P_2D3D

TXB3P_2D3D

TXBCLKN_2D3D
TXB2P_2D3D

TXB1P_2D3D

TXB4P_2D3D

TXBCLKP_2D3D

TXB0N_2D3D

TXB4N_2D3D

I2C_SCL

R706
100

1%

R700
100

1%

R702
100

1%

R704
100

1%

R708
100

1%

R710
100

1%

R707
100

1%

R701
100

1%

R703
100

1%

R705
100

1%

R709
100

1%

R711
100

1%

C717

0.1uF
16V

C711

0.1uF
16V

C708

0.1uF
16V

C704

0.1uF
16V

C724

0.1uF
16V

C702

0.1uF
16V

C720

0.1uF
16V

C703

0.1uF
16V

C719

0.1uF
16V

C722

0.1uF
16V

C701

0.1uF
16V

C715

0.1uF
16V

C707

0.1uF
16V

C710

0.1uF
16V

C709

0.1uF
16V

C700

0.1uF
16V

C705

0.1uF
16V

C712

0.1uF
16V

C721

0.1uF
16V

+1.0V_LG1131

C723

0.1uF
16V

C718

0.1uF
16V

+3.3V_LG1131_Rx +1.0V_LG1131

L701

CIS21J121

+3.3V_LG1131_VDD

C725

0.1uF
16V

+3.3VD

C714

0.1uF
16V

L700

CIS21J121

C713

0.1uF
16V

C706

0.1uF
16V

+1.0V_LG1131+1.0V_2D3D

RESET_LG1131

R712 33

R713 33

RESET_LG1131

RESET

R715
10K

RESET_LG1131

+3.3VD

R714 1K

R717

0

R718
0

R716
0

IC700

LG1131A

1

VDD10_1

2

RXB4P

3

RXB4N

4

RXB3P

5

RXB3N

6

RXBCLKP

7

RXBCLKN

8

RXB2P

9

RXB2N

10

RXB1P

11

RXB1N

12

RXB0P

13

RXB0N

14

AVDD33_1

15

GND_1

16

RXA4P

17

RXA4N

18

RXA3P

19

RXA3N

20

RXACLKP

21

RXACLKN

22

RXA2P

23

RXA2N

24

RXA1P

25

RXA1N

26

RXA0P

27

RXA0N

28

AVDD33_2

29

GND_230GND_3

31

VDD33_132VDD10_2

33

GND_4

34

VDD10_3

35

T_DIN036T_DIN137T_DIN2

38

VDD10_4

39

GND_5

40

T_DIN3

41

T_DOUT042T_DOUT143VDD10_5

44

GND_6

45

T_DOUT246VDD33_2

47

GND_7

48

T_DOUT3

49

GND_8

50

VDD10_6

51

GND_9

52

VDD10_7

53

GND_1054GND_11

55

TXA0N

56

TXA0P

57

TXA1N

58

TXA1P

59

TXA2N

60

TXA2P

61

TXACLKN

62

TXACLKP

63

TXA3N

64

TXA3P

65

TXA4N

66

TXA4P

67

AVDD33_3

68

GND_12

69

TXB0N

70

TXB0P

71

TXB1N

72

TXB1P

73

TXB2N

74

TXB2P

75

TXBCLKN

76

TXBCLKP

77

TXB3N

78

TXB3P

79

TXB4N

80

TXB4P

81

GND_13

82

AVDD33_483AVDD33_584GND_1485VDD10_886GND_1587T_ENB88EXTCLK_IN89TEST090VDD33_391GND_1692VDD10_993TEST194TEST295T_DOUT496T_DOUT597VDD33_498GND_1799VDD10_10

100

T_DOUT6

101

SDA

102

SCL

103

RESET

104

VDD10_11

105

GND_18

106

VDD10_12

107

GND_19

108

AVDD33_6

109

[EP]

C729

0.1uF
16V

+3.3VD

L702

CIS21J121

C730

0.1uF
16V

+3.3VD +3.3V_LG1131_TX

L703

CIS21J121

+3.3V_LG1131_TX

+3.3V_LG1131_Rx

+3.3V_LG1131_VDD

+3.3V_LG1131_VDD
C726
10uF
25V

C727
10uF
25V

C728
10uF
25V

C731
1uF
25V

C732
1uF
25V

C733
1uF
25V

2010. 10. 4LG1121 GP3

772D to 3D block(LG1131)

+1.0V_LG1131 Decaps

t_dout(0) : PLL CLOCK OUTPUT(1x)

t_dout(2) : VCO CLOCK OUTPUT

t_dout(4) : rst_pix2_n

I2C Slave Address : 0x8E

+3.3V_LG1131_LVDS_Tx +3.3V_LG1131_VDD

+3.3V_LG1131_LVDS_Rx

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

NAND_DATA[0]

NAND_DATA[1]

CI_ADDR[12]

NAND_DATA[2]

CI_ADDR[2]

NAND_DATA[1]

NAND_DATA[3]

CI_ADDR[7]

CI_ADDR[13]
CI_ADDR[14]

NAND_DATA[4]

NAND_DATA[2]

NAND_DATA[3]

NAND_DATA[7]

NAND_DATA[5]

CI_ADDR[8]

NAND_DATA[7]

NAND_DATA[0]

NAND_DATA[6]

CI_ADDR[4]

CI_ADDR[9]

NAND_DATA[4]

CI_ADDR[3]

NAND_DATA[6]

NAND_DATA[5]

CI_ADDR[10]
CI_ADDR[11]

CI_ADDR[5]
CI_ADDR[6]

R185 0

TXA0N

SOC_RESET

TXBCLKP

R151

0

16Gbit

R147
1K

TXD0P

R170
10K

SDA2_3.3V

HDMI_ARC

R172

4.7K

OPT

TXD1P

C103

0.1uF

54MHz_XTAL_P

R183
10K

C101

0.1uF

TXA1P

DTV/MNT_V_OUT

TXC0P

TXC1P

R180
10K

TXDCLKN

TXA3N

R115
10K

R132 4.7K

R120
10K

SCL0_3.3V

TXACLKN

+3.3V_Normal

R116
10K
OPT

NAND_DATA[6]

+3.3V_Normal

HDMI_CLK+

R118
10K

R150
1K

NAND_WEb

+3.3V_Normal

P101

TJC2508-4A

1

VCC

2

SCL

3

SDA

4

GND

TXD2P

NAND_DATA[5]

C106

4.7uF

CI_ADDR[8]

SC_ID

NAND_CEb2

+3.3V_Normal

R145 22

OPT

R157
10K
OPT

CI_ADDR[12]

R169
0

CI_ADDR[7]

C112 0.1uF

TXB4P

R107 2.7K

C107
33pF
50V

DVB_S

TXD1N

NAND_CEb

NAND_RBb

R101

4.7K

R124
1K
OPT

C119

0.1uF
16V

NAND_CLE

TXB2N

+3.3V_Normal

TXD4P

5V_HDMI_2

NAND_CEb2

C104 10uF

10V

TXA1N

TXB3N

BSS83

Q101

SBD

G

NAND_DATA[3]

HDMI_CLK-

R176
10K

SDA0_3.3V

R111
10K
OPT

R191 33

TXD3P

TXB0P

R154
10K
OPT

BCM_RX

HDMI_RX2+

TXC2P

R103

4.7K

OPT

+3.3V_Normal

TXD2N

TXCCLKP

C102

4700pF

R198
10K

C111 0.01uF

NAND_ALE

TXBCLKN

NAND_DATA[0-7]

TXCCLKN

R179
10K
OPT

HDMI_RX1+

R117
10K
OPT

R135

33

C108
33pF
50V

DVB_S

R177
10K

FLASH_WP

TXA4N

R165
10K

R195

4.7K

IC103

M24M01-HRMN6TP

BCM_NVM_1M

3

E2

2

E1

4

VSS

1

NC

5

SDA

6

SCL

7

WP

8

VCC

NAND_DATA[7]

R173

4.7K

TXB4N

R190 33

NAND_DATA[0-7]

NAND_WEb

R196
10K

NAND_CEb

R108 10K

CI_ADDR[4]

+3.3V_Normal

NAND_REb

R156
1K

/CI_CE1

R155
10K

A_DIM

R153
1K

TXA3P

HDMI_RX1-

NAND_DATA[0]

5V_HDMI_1

R194

2.7K

R127
10K
OPT

NAND_CLE

R125
1K

R178
10K
OPT

C105

2.2uF
10V

CI_ADDR[13]

C109
33pF
50V

54MHz_XTAL_N

R159
1K

5V_HDMI_4

R128
10K

/PCM_WAIT

+3.3V_Normal

HDMI_RX0-

CI_ADDR[3]

BCM_TX

C110
33pF
50V

TXB1P

+3.3V_Normal

R184
10K

OPT

NAND_ALE

R144 22

OPT

TXA0P

R122
10K

SCL2_3.3V

NAND_DATA[1]

+3.3V_Normal

R106
3K

R119
10K

OPT

TXC3N

R175
10K
OPT

SCL3_3.3V

HDMI_RX0+

R123
10K
OPT

R167
10K
OPT

CI_ADDR[2]

R130
2K

OPT

R110

1.5K

R113
10K

R193
10K

R181
10K
OPT

R112
10K

TXACLKP

R148

0

16Gbit

TXB3P

R182
10K

TXC4N

R163
1K

+3.3V_Normal

LNB_INT

R114
10K

OPT

R140
560
1%

R158
10K

R162
1K

TXA2P
TXA2N

NAND_RBb

NAND_DATA[4]

R136 33

R149 0

16Gbit

R143 22

OPT

TXC4P

R186 0

BSS83

Q102

SBD

G

NAND_DATA[2]

R139 0

TXB1N

CI_ADDR[11]

CI_ADDR[9]

5V_HDMI_3

+3.3V_Normal

R166
1K

RGB_DDC_SCL

+3.3V_Normal

TXD4N

TXC1N

54MHz_XTAL_P

TXDCLKP

R171
10K
OPT

TXC2N

TXC0N

R160
10K
OPT

TXB0N

NAND_REb

TXC3P

CI_ADDR[6]

R168
10K

PCM_5V_CTL

R189
1M
OPT

+3.3V_Normal

R141 4.7K

TXD0N

54MHz_XTAL_N

R192
10K
OPT

R14610K

C118

0.1uF
16V

+3.3V_Normal

+3.3V_Normal

/CI_CE2

TXA4P

R164
10K

OPT

+3.3V_Normal

R161
10K

R142 22

OPT

R188
10K

R187
10K
OPT

SDA3_3.3V

NAND_CLE

R109

1.5K

FLASH_WP

TXB2P

+3.3V_Normal

TXD3N

+3.3V_Normal

CI_ADDR[2-14]

HDMI_RX2-

R174

4.7K

OPT

RGB_DDC_SDA

NAND_ALE

R126

1.2K

R129

1.2K

R121

1.2K

R131

1.2K

R199 22
R197 22

R105

4.7K

R104

4.7K

IC102

TC58DVG3S0ETA00

NAND_8Gbit

26

NC_17

27

NC_18

28

NC_19

29

I/O1

30

I/O2

31

I/O3

32

I/O4

33

NC_20

34

NC_21

35

NC_22

36

VSS_2

37

VCC_2

38

NC_23

39

PSL

40

NC_24

41

I/O5

42

I/O6

43

I/O7

44

I/O8

45

NC_25

46

NC_26

47

NC_27

48

NC_28

17

ALE

3

NC_3

6

NC_6

16

CLE

15

NC_10

14

NC_9

13

VSS_1

12

VCC_1

11

NC_8

10

NC_7

9

CE

8

RE

7

RY/BY

4

NC_4

5

NC_5

25

NC_16

24

NC_15

23

NC_14

2

NC_2

22

NC_13

21

NC_12

1

NC_1

20

NC_11

19

WP

18

WE

IC102-*1

TH58DVG4S0ETA20

DEV_NAND_16Gbit

26

NC_15

27

NC_16

28

NC_17

29

I/O1

30

I/O2

31

I/O3

32

I/O4

33

NC_18

34

NC_19

35

NC_20

36

VSS_2

37

VCC_2

38

NC_21

39

PSL

40

NC_22

41

I/O5

42

I/O6

43

I/O7

44

I/O8

45

NC_23

46

NC_24

47

NC_25

48

NC_26

17

ALE

3

NC_3

6

RY/BY2

16

CLE

15

NC_8

14

NC_7

13

VSS_1

12

VCC_1

11

NC_6

10

CE2

9

CE1

8

RE

7

RY/BY1

4

NC_4

5

NC_5

25

NC_14

24

NC_13

23

NC_12

2

NC_2

22

NC_11

21

NC_10

1

NC_1

20

NC_9

19

WP

18

WE

LGE35230(BCM35230KFSBG)

IC101

NON_BCM_CAP

HDMI0_CLKN

B5

HDMI0_CLKP

C5

HDMI0_D0N

A4

HDMI0_D0P

B4

HDMI0_D1N

A3

HDMI0_D1P

B3

HDMI0_D2N

A2

HDMI0_D2P

B2

CEC

W2

DDC0_SCL

V4

DDC0_SDA

W4

HDMI0_HTPLG_IN

V3

HDMI0_HTPLG_OUT

V2

HDMI0_ARC

D13

HDMI0_RESREF

E6

TXOUT0_L0N

AE27

TXOUT0_L0P

AE28

TXOUT0_L1N

AF27

TXOUT0_L1P

AF28

TXOUT0_L2N

AG27

TXOUT0_L2P

AG28

TXCLK_LN

AE26

TXCLK_LP

AF26

TXOUT0_L3N

AH27

TXOUT0_L3P

AG26

TXOUT0_L4N

AF25

TXOUT0_L4P

AE25

TXOUT0_U0N

AH26

TXOUT0_U0P

AG25

TXOUT0_U1N

AE24

TXOUT0_U1P

AD24

TXOUT0_U2N

AH25

TXOUT0_U2P

AF24

TXCLK_UN

AE23

TXCLK_UP

AD23

TXOUT0_U3N

AG24

TXOUT0_U3P

AF23

TXOUT0_U4N

AC22

TXOUT0_U4P

AD22

TXOUT1_L0N

AG23

TXOUT1_L0P

AH23

TXOUT1_L1N

AE22

TXOUT1_L1P

AE21

TXOUT1_L2N

AF22

TXOUT1_L2P

AH22

TXCLK1_LN

AG22

TXCLK1_LP

AF21

TXOUT1_L3N

AG21

TXOUT1_L3P

AF20

TXOUT1_L4N

AD21

TXOUT1_L4P

AC21

TXOUT1_U0N

AG20

TXOUT1_U0P

AH20

TXOUT1_U1N

AD19

TXOUT1_U1P

AE19

TXOUT1_U2N

AF19

TXOUT1_U2P

AH19

TXCLK1_UN

AE18

TXCLK1_UP

AD18

TXOUT1_U3N

AG19

TXOUT1_U3P

AF18

TXOUT1_U4N

AG18

TXOUT1_U4P

AF17

LT0VCAL_MONITOR

AC18

GPIO_BL_ON

AH16

BL_PWM/GPIO

AG16

LGE35230(BCM35230KFSBG)

IC101

NON_BCM_CAP

TVM_XTALIN

AG6

TVM_XTALOUT

AF6

IRRXDA

V5

FP_IN0

AB4

FP_IN1

Y4

SPARE_ADC1

AA4

SPARE_ADC2

Y5

FS_IN1

AB2

FS_IN2

AB5

VGA_SDA

U3

VGA_SCL

U2

RDA

Y2

TDA

Y1

BSCDATAA

AA3

BSCCLKA

AA2

RDB/GPIO

H3

TDB/GPIO

H2

BSC_S_SCL

H4

BSC_S_SDA

H5

NMIB

F25

POWER_CTRL

W5

AON_HSYNC

U5

AON_VSYNC

U4

AON_GPIO_36

W3

AON_GPIO_37

W1

AON_RESETOUTB

AB6

TVM_BYPASS

Y6

RESETB

Y3

RESETOUTB

G24

TMODE

J6

TESTEN

W6

VDAC_VREG

F7

VDAC_RBIAS

E7

FAD_7

AB1

FAD_6

AB3

FAD_5

AC1

FAD_4

AC2

FAD_3

AC3

FAD_2

AD2

FAD_1

AD3

FAD_0

AE2

FALE

AG1

FCEB_0

AF1

FCEB_1

AC5

FCEB_2

AE6

FCEB_3

AG5

NFWPB

AF3

FWE

AG2

FRD

AE3

FRDYB

AA5

FA_0

AF2

FA_1

AE1

FA_2

AC4

FA_3

AD5

FA_4

AD4

FA_5

AE4

FA_6

AE5

FA_7

AD6

FA_8

AH3

FA_9

AF4

FA_10

AH4

FA_11

AG4

FA_12

AF5

FA_13

AG3

FA_14

AH2

FA_15

AH5

TRSTB

AD15

TDI/GPIO

AF14

TDO

AH14

TMS/GPIO

AD14

TCK/GPIO

AG14

DINT/GPIO

AC16

AVS_VFB

AH7

AVS_VSENSE

AG7

AVS_RESETB

AD7

AVS_NDRIVE_1

AF7

AVS_PDRIVE_1

AH8

VDAC_1

C6

VDAC_2

D7

X101

54MHz

EAW58812611
SUNNY ELECTRONICS CORPORATION

CRYSTAL_BCM_Sunny

4

GND_21X-TAL_1

2

GND_1

3

X-TAL_2

X101-*1

54MHz

CRYSTAL_BCM_Lihom

EAW60763703

LIHOM CO., LTD.

4

GND_2

1

X-TAL_1

2

GND_13X-TAL_2

X101-*2

54MHz

CRYSTAL_BCM_KDS

DAISHINKU CORPORATION.

EAW58239604

4

GND_2

1

X-TAL_1

2

GND_13X-TAL_2

IC103-*1

AT24C256C-SSHL-T

BCM_NVM_256K

3

A2

2

A1

4

GND

1

A0

5

SDA

6

SCL

7

WP

8

VCC

C114

12pF
50V

C113
12pF

50V

SRST

SRST

MAIN & NAND FLASH

BBS CONNECT

Write Protection

- High : Normal Operation

- Low : Write Protection

NAND_DATA[0]:
0: System is LITTLE endian (O)
1: System is BIG endian

CI_ADDR[7]:
0: Disable EDID automatic Downloading from Flash (O)
1: Enable EDID automatic Downloading from Flash

NAND_DATA[6] :
0: Disable OSC clock output on chip Pin (O)
1: Enable OSC clock output on chip pin.

CI_ADDR[6]:
0: Host MIPS run at 500 MHz (O)
1: Host MIPS run at 250 MHz

NAND_CLE:
0: Differential Oscillators TVM not bypassed (O)
1: Differential Oscillators TVM bypassed

NAND_DATA[4]:
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O)

Write Protection

- Low : Normal Operation

- High : Write Protection

000 = ECC disabled
001 = ECC 1-bit repair
010 = ECC 4-bit BCH (O)
011 = ECC 8-bit BCH, 27 byte spare
100 = ECC 12-bit BCH, 27 byte spare
101 = ECC 8-bit BCH, 16 byte spare
110, 111 = Reservedd

NAND ECC (FA3, FA2, FALE)

BCM REFRENCE is 562ohm

A8’h

FOR HDMI STANDARD
APPLY ONLY WHEN CONNECT TO PULL-UP GPIO

BCM35230

1

CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
TVM Crystal oscillator bias/gain control
0000: 210uA
0001: 390uA
0010: 570uA
0011: 730uA
0100: 890uA (O)
0111: 1290uA
1000: 1416uA
1111: 2196uA
0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved

CI_ADDR[8]:
0: RESETOUTb (in On/Off only) stay asserted until software releases them.
1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
at end of RESETb pulse (O)

NAND_DATA[3]:
0: MIPS will boot from external flash (O)
1: MIPS will boot from ROM

NAND_DATA[5]:
0: FLASH MODE (O)
1: BSC_SLAVE(BBS) MODE

Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)

0000: ST Micro M25P or compatible Serial Flash
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O)
0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices
0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
0111: 3B dual IO Serial Flash
1001: BB dual IO Serial Flash
1011: fast Serail Flash > 50Mhz
1100: OneNAND Flash (always 16-bit)
1110: Reserved
1101, 1111: Reserved

NAND FLASH MEMORY 8Gbit

Strap Setting

54MHz X-TAL

NVRAM

IC102 1ST : EAN61000101 2ND : T-TH58DVG4S0ETA20

DUAL COMPONENT

IC102-*1

DVB_S Option: apply EU Satellite model

2010.09.18

16Gbit

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

FE_TS_DATA[2]

PCM_MDI[7]

PCM_MDI[5]
PCM_MDI[6]

FE_TS_DATA[7]

PCM_MDI[4]

FE_TS_DATA[4]

PCM_TS_DATA[5]

FE_TS_DATA[5]

PCM_MDI[2]

PCM_MDI[1]

PCM_MDI[0]

FE_TS_DATA[3]

FE_TS_DATA[6]

FE_TS_DATA[0]

PCM_TS_DATA[1]

PCM_TS_DATA[3]

PCM_TS_DATA[0]

FE_TS_DATA[1]

PCM_TS_DATA[2]

PCM_TS_DATA[7]

PCM_TS_DATA[6]

PCM_MDI[3]

PCM_TS_DATA[4]

CHBO_TS_CLK

PCM_TS_VAL

COMP1_DET

PLL_MIPS_AVDD

L213

BLM18PG121SN1D

ADAC_AVDD25

C231
33pF
50V

NON_NTP

+0.9V_CORE

C227
33pF
50V

NON_NTP

R264

1K

OPT

+2.5V_BCM35230

PCM_TS_SYNC

EPHY_VDD25

SIDE_USB_CTL2

R266

1K

NO_S_TUNNER

C281

0.1uF

MODEL_OPT_2

C290

0.1uF

VAFE2_DVDD

SDA1_3.3V

R241

100

PLL_VAFE_AVDD25

TU_TS_SYNC

C220

0.1uF

C280

0.1uF

C234

0.1uF

3D_GPIO_1

SCL1_3.3V

C257

0.1uF

+0.9V_CORE

L216

BLM18PG121SN1D

MODEL_OPT_2

MODEL_OPT_3

L209

BLM18PG121SN1D

C247
22uF

/PCM_IRQA

R227 22

RF_BOOSTER_CTL

AADC_AVDD25

+0.9V_CORE

R208 0

F/NIM_EU_CN

+0.9V_CORE

+0.9V_CORE

+0.9V_CORE

+0.9V_CORE

C299

0.1uF

R267

1K

NO_PHM

R253

1K

OLED

+0.9V_CORE

PCM_MISTRT

ADAC_AVDD25

L/DIM0_MOSI

R251

1K

BCM_FRC/URSA5

C242

0.1uF

SIDE_USB_OCD2

R226 22

R285 22

PWM_DIM

C278

0.1uF

C236

0.1uF

+2.5V_BCM35230

USB_AVDD33

+2.5V_BCM35230

+3.3V_Normal

HDMI_AVDD33

+1.5V_DDR

R281 22

C273

0.1uF

R218 22

MODEL_OPT_4

R204 0

F/NIM_EU_CN

TW9910_RESET

C213

0.1uF

R221 22

BCM_L/DIM

SC_DET/COMP2_DET

R254

1K

R203 0

F/NIM_EU_CN

R265

1K

NO_T2_TUNER

C272

0.01uF

IF_N

C211

0.1uF

+0.9V_CORE

R215 22

PCM_MIVAL_ERR

HDMI_AVDD33

C215

0.01uF

L/DIM0_VS

MODEL_OPT_0

MODEL_OPT_7

R282 22

CHB_RESET

SIDE_USB_DM

HDMI_AVDD

R242

100

C276

0.01uF
OPT

C270

0.1uF

C201
100pF

OPT

R256

1K

S_TUNER

IF_AGC

CI_DET

+0.9V_CORE

R230 22

BCM_L/DIM

C269

0.1uF

+3.3V_Normal

PCM_TS_DATA[0-7]

C283

0.1uF

3D_GPIO_2

FE_TS_DATA[0-7]

L211

BLM18PG121SN1D

R262

1K

HD

C255

0.1uF

R255

1K

T2_TUNER

L204

BLM18PG121SN1D

SIDE_USB_OCD1

R261

1K

NO_FRC/FRC2

R240

2.7K

R225 0

OPT

PLL_MIPS_AVDD

VAFE2_VDD25

ERROR_OUT

EPHY_VDD25

L218

BLM18PG121SN1D

MODEL_OPT_7

L215

BLM18PG121SN1D

R283
22

VAFE3_DVDD

+3.3V_Normal

R211

6.04K

C297

0.1uF

PLL_VAFE_AVDD

DTV_ATV_SELECT

L207

BLM18PG121SN1D

R260

1K

NO_FRC/BCM_FRC

R207 0

F/NIM_EU_CN

+2.5V_BCM35230

SIDE_USB_CTL1

R286
10K

WIFI

R210

4.87K
1%

M_RFModule_RESET

USB_AVDD

EPHY_RDN

R205 0

F/NIM_EU_CN

CHBO_TS_SERIAL

C289

0.1uF

+2.5V_BCM35230

AV2_CVBS_DET

R220 22

3D_GPIO_0

+3.3V_Normal

L/DIM0_SCLK

C222

0.01uF

VAFE3_VDD25

RF_SWITCH_CTL_2

VAFE3_VDD25

+0.9V_CORE

R222 22

BCM_L/DIM

+3.3V_Normal

R206 0

F/NIM_EU_CN

L202

BLM18PG121SN1D

VDAC_AVDD33

PCM_TS_CLK

MODEL_OPT_1

+3.3V_Normal

R228 22

PLL_AUD_AVDD

+2.5V_BCM35230

C268

0.1uF

EPHY_TDP

R202

0

F/NIM_EU_CN

+2.5V_BCM35230

L212

BLM18PG121SN1D

MODEL_OPT_4

MODEL_OPT_3

C288

0.1uF

MODEL_OPT_6

EPHY_TDN

TS_VAL_ERR

C282

0.1uF

+1.5V_DDR

+3.3V_Normal

L214

BLM18PG121SN1D

PCM_MDI[0-7]

C274
22uF

R250

1K

FRC2/URSA5

R235

100

MODEL_OPT_1

M_REMOTE_RX

R223 22

R280
22

C258

0.1uF

FRC_RESET

L206

BLM18PG121SN1D

C298

0.1uF

DC_MREMOTE

USB_AVDD33

IF_P

L219

BLM18PG121SN1D

R263

1K

LCD

WIFI_DM

SIDE_USB_DP

C221

0.1uF

VDAC_AVDD33

MODEL_OPT_5

C229

0.1uF

C218

0.1uF
16V

MODEL_OPT_6

INSTANT_MODE

EPHY_RDP

PCM_RST

PLL_VAFE_AVDD25

L201

BLM18PG121SN1D

+3.3V_Normal

WIFI_DP

+0.9V_CORE

RF_SWITCH_CTL

R257

1K

PHM

CHBO_TS_SYNC

+2.5V_BCM35230

R201 0

OPT

+0.9V_CORE

C293

0.1uF

AADC_AVDD25

R284 22

L217

BLM18PG121SN1D

R214 22

+3.3V_Normal

C217

0.1uF

16V

C223

0.01uF

PLL_MAIN_AVDD

L210

BLM18PG121SN1D

R224 22

C284
22uF

PLL_MAIN_AVDD

C267

0.1uF

+3.3V_Normal

C216 0.01uF

PLL_VAFE_AVDD

MODEL_OPT_5

C275

0.1uF
OPT

CHBO_TS_VAL_ERR

VAFE2_DVDD

+2.5V_BCM35230

+3.3V_Normal

C292
22uF

R213 2K

USB_AVDD

L203

BLM18PG121SN1D

VAFE2_VDD25

+3.3V_Normal

C256

0.1uF

VAFE3_DVDD

DD_MREMOTE

R212
1K

Non_CHB

L205

BLM18PG121SN1D

PCM_MCLKI

MODEL_OPT_0

R252

1K

FHD

PLL_AUD_AVDD

+3.3V_Normal

C251

0.1uF
16V

HDMI_AVDD

TU_TS_CLK

DSUB_DET

R209 0

F/NIM_EU_CN

R216 22

C271

0.01uF

EPHY_ACTIVITY
EPHY_LINK

3D_SYNC

R233

1.2K

R234

1.2K

R231 100

URSA_RESET

R231-*1 0

FRC2_RESET

R232

4.7K
URSA_RESET

+3.3V_Normal

C203
10uF
10V

C205
10uF
10V

C248
10uF
10V

C249
10uF
10V

C253
10uF
10V

C259
10uF
10V

C261
10uF
10V

C262
10uF

C207

4.7uF
10V

C209

4.7uF
10V

C238

4.7uF
10V

C250

4.7uF
10V

C254

4.7uF

C252

4.7uF
10V

C260

4.7uF

C263

4.7uF

C264

4.7uF

C265

4.7uF

C266

4.7uF C277

4.7uF

C279

4.7uF

C285

4.7uF

C286

4.7uF

C287

4.7uF

C291

4.7uF

C294

4.7uF

C295

4.7uF

C296

4.7uF

C225

0.22uF

6.3V

LGE35230(BCM35230KFSBG)

IC101

NON_BCM_CAP

EPHY_VREF

F26

EPHY_RDAC

D26

EPHY_TDP

F27

EPHY_TDN

F28

EPHY_RDP

E27

EPHY_RDN

E26

USB_MONCDR

F5

USB_RREF

E5

USB_PORT1DN

C2

USB_PORT1DP

D1

USB_PWRFLT_1/GPIO

E1

USB_PWRON_1/GPIO

D2

USB_PORT2DN

B1

USB_PORT2DP

C1

USB_PWRFLT_2/GPIO

C3

USB_PWRON_2/GPIO

C4

TCLKA/GPIO

M4

TDATA_0/GPIO

L5

TDATA_1/GPIO

M5

TDATA_2/GPIO

L6

TDATA_3/GPIO

N3

TDATA_4/GPIO

N1

TDATA_5/GPIO

N2

TDATA_6/GPIO

M3

TDATA_7/GPIO

M2

TSTRTA/GPIO

L4

TVLDA/GPIO

N4

TCLKD/GPIO

K6

TDATD_0/GPIO

J4

TDATD_1/GPIO

K5

TDATD_2/GPIO

J2

TDATD_3/GPIO

J3

TDATD_4/GPIO

K2

TDATD_5/GPIO

K1

TDATD_6/GPIO

K3

TDATD_7/GPIO

L1

TSTRTD/GPIO

L3

TVLDD/GPIO

L2

MPEG_CLK/GPIO

P4

MPEG_D_0/GPIO

T2

MPEG_D_1/GPIO

R3

MPEG_D_2/GPIO

R2

MPEG_D_3/GPIO

P3

MPEG_D_4/GPIO

P2

MPEG_D_5/GPIO

P1

MPEG_D_6/GPIO

R6

MPEG_D_7/GPIO

N5

MPEG_SYNC/GPIO

T4

MPEG_DATA_EN/GPIO

P5

MCIF_RESET/GPIO

R4

MCIF_SCLK/GPIO

U1

MCIF_SCTL/GPIO

T3

MCIF_SDI/GPIO

T1

MCIF_SDO/GPIO

T5

VI_IFP0

C17

VI_IFM0

B17

VDDR_AGC

D15

AGC_SDM_2

B16

AGC_SDM_1

A16

GPIO_0

A15

GPIO_1

C16

GPIO_2

G28

GPIO_3

G26

PCI_VIO_0

W14

PCI_VIO_1

W15

PCI_VIO_2

W13

GPIO_4

J5

GPIO_5

R5

GPIO_6

V6

GPIO_7

H6

GPIO_70

AE15

GPIO_71

AF15

GPIO_72

AG15

GPIO_73

AF16

GPIO_74

AD16

GPIO_75

AE16

GPIO_76

AG17

GPIO_77

AH17

GPIO_78

AE17

GPIO_79

AD17

PCI_AD05

AB13

PCI_AD06

AC15

PCI_AD07

AB12

PCI_AD08

AB11

PCI_AD09/GPIO

AE14

PCI_AD10/GPIO

AG13

PCI_AD11/GPIO

AH13

PCI_AD12/GPIO

AF13

PCI_AD13/GPIO

AE13

PCI_AD14/GPIO

AD12

PCI_AD15/GPIO

AF12

PCI_AD16/GPIO

AG10

PCI_AD17/GPIO

AF10

PCI_AD18/GPIO

AE10

PCI_AD19/GPIO

AD10

PCI_AD20/GPIO

AE9

PCI_AD21/GPIO

AE8

PCI_AD22

AC10

PCI_AD23

AC11

PCI_AD24

AC8

PCI_AD25

AB8

PCI_CBE00

AC14

PCI_CBE01/GPIO

AG12

PCI_CBE02/GPIO

AH10

PCI_CBE03

AB7

PCI_DEVSELB/GPIO

AG11

PCI_FRAMEB/GPIO

AD11

PCI_IRDYB/GPIO

AE11

PCI_PAR/GPIO

AD13

PCI_PERRB/GPIO

AE12

PCI_REQ1B

AC12

PCI_SERRB/GPIO

AC13

PCI_STOPB/GPIO

AH11

PCI_TRDYB/GPIO

AF11

LGE35230(BCM35230KFSBG)

IC101

NON_BCM_CAP

VDDC_1

V12

VDDC_2

V7

VDDC_3

M10

VDDC_4

N10

VDDC_5

P10

VDDC_6

R10

VDDC_7

T10

VDDC_8

U10

VDDC_9

V10

VDDC_10

W10

VDDC_11

V13

VDDC_12

L11

VDDC_13

M11

VDDC_14

N11

VDDC_15

P11

VDDC_16

R11

VDDC_17

T11

VDDC_18

U11

VDDC_19

V11

VDDC_20

W11

VDDC_21

V14

VDDC_22

L18

VDDC_23

M18

VDDC_24

N18

VDDC_25

P18

VDDC_26

R18

VDDC_27

T18

VDDC_28

U18

VDDC_29

V18

VDDC_30

W18

VDDC_31

V15

VDDC_32

L19

VDDC_33

M19

VDDC_34

N19

VDDC_35

P19

VDDC_36

R19

VDDC_37

T19

VDDC_38

U19

VDDC_39

V19

VDDC_40

W19

VDDC_41

V16

VDDC_42

V17

POR_VDD

L10

VDDR1_1

L22

VDDR1_2

AA28

VDDR1_3

V28

VDDR1_4

R28

VDDR1_5

M28

VDDR1_6

J28

VDDR1_7

K23

VDDR1_8

M22

VDDR1_9

T22

VDDR1_10

T23

VDDR1_11

U22

VDDR1_12

Y22

DDR_LDO_VDDO

R22

VDDR3_1

G15

VDDR3_2

H22

VDDR3_3

G23

VDDR3_4

AB9

VDDR3_5

K7

VDDR3_6

AB15

VDDR3_7

L7

VDDR3_8

AB14

VDDR3_9

M7

VDDR3_10

N6

VDDR3_11

P6

AON_VDDC_1

AA6

AON_VDDC_2

AA7

AON_POR_VDD

Y7

AON_VDDR3

U7

AON_VDDR10_1

T7

AON_VDDR10_2

T6

VSS_1

K10

VSS_2

K11

VSS_3

K12

VSS_4

L12

VSS_5

M12

VSS_6

N12

VSS_7

P12

VSS_8

R12

VSS_9

T12

VSS_10

U12

VSS_11

W12

VSS_12

K13

VSS_13

L13

VSS_14

M13

VSS_15

N13

VSS_16

P13

VSS_17

R13

VSS_18

T13

VSS_19

U13

VSS_20

W16

VSS_21

K14

VSS_22

L14

VSS_23

M14

VSS_24

N14

VSS_25

P14

VSS_26

R14

VSS_27

T14

VSS_28

U14

VSS_29

K15

VSS_30

L15

VSS_31

M15

VSS_32

N15

VSS_33

P15

VSS_34

R15

VSS_35

T15

VSS_36

U15

VSS_37

K16

VSS_38

L16

VSS_39

M16

VSS_40

N16

VSS_41

P16

VSS_42

R16

VSS_43

T16

VSS_44

U16

VSS_45

K17

VSS_46

L17

VSS_47

M17

VSS_48

N17

VSS_49

P17

VSS_50

R17

VSS_51

T17

VSS_52

U17

VSS_53

W17

VSS_54

K18

VSS_55

K19

VSS_56

H7

VSS_57

G14

VSS_58

AB16

VSS_59

R7

VSS_60

M6

VSS_61

AB23

VSS_62

P7

VSS_63

W7

VSS_64

J7

VSS_65

N7

VSS_66

AB10

VSS_67

AC23

VSS_68

AC6

VSS_69

G19

VSS_70

AA22

VSS_71

J23

VSS_72

J22

VSS_73

K22

VSS_74

J25

VSS_75

N22

VSS_76

N23

VSS_77

M25

VSS_78

P22

VSS_79

R25

VSS_80

V22

VSS_81

W22

VSS_82

W23

VSS_83

V25

VSS_84

AA25

LGE35230(BCM35230KFSBG)

IC101

NON_BCM_CAP

AADC_AVDD25

F19

ADACA_AVDD25

D25

ADACC_AVDD25

D24

ADACD_AVDD25

E24

EPHY_BVDD25

F24

EPHY_AVDD25

E25

POR_VDD25

F8

HDMI0_AVDD

D5

HDMI0_AVDD33

D4

LT0VDD25_1

AE20

LT0VDD25_2

AD20

LT0VDD25_3

AC20

LT0VDD25_4

AB20

SPDIF_IN_AVDD25

D14

USB_AVDD

E4

USB_AVDD33

D3

VDAC_AVDD33

D6

VAFE2_DVDD

D18

VAFE2_AVDD25_1

E17

VAFE2_AVDD25_2

D16

VAFE2_DVDD25

D17

VAFE3_DVDD

D9

VAFE3_AVDD25_1

D8

VAFE3_AVDD25_2

E8

VAFE3_AVDD25_3

F9

VAFE3_DVDD25

E9

PLL_AUD_AVDD

G25

PLL_MAIN_AVDD

K4

PLL_MIPS_AVDD

AD25

PLL_VAFE_AVDD

D11

TVM_OSC_AVDD

AE7

AUX_AVDD33

U6

AADC_AVSS

F20

ADACA_AVSS

G22

ADACC_AVSS

G21

ADACD_AVSS

F22

EPHY_AVSS

F23

HDMI0_AVSS_1

F6

HDMI0_AVSS_2

G6

LT0VSS_1

AB22

LT0VSS_2

AB21

LT0VSS_3

AB19

LT0VSS_4

AC19

LT0VSS_5

AB18

LT0VSS_6

AB17

LT0VSS_7

AC17

SPDIF_IN_AVSS

F15

USB_AVSS_1

G7

USB_AVSS_2

G8

VDAC_AVSS

G9

VAFE2_VSS_1

G20

VAFE2_VSS_2

E18

VAFE2_VSS_3

G18

VAFE2_VSS_4

G17

VAFE2_VSS_5

F18

VAFE2_VSS_6

G16

VAFE2_VSS_7

F16

VAFE3_VSS_1

G13

VAFE3_VSS_2

G12

VAFE3_VSS_3

F12

VAFE3_VSS_4

G11

VAFE3_VSS_5

G10

VAFE3_VSS_6

F10

PLL_MIPS_AVSS

AD26

PLL_VAFE_AVDD25

D12

TVM_OSC_AVSS

AC7

R232-*1

4.7K
FRC2_RESET

NFM18PS105R0J

C233

6.3V

OUTIN

GND

NFM18PS105R0J

C244

6.3V

OUTIN

GND

NFM18PS105R0J

C204

6.3V

OUTIN

GND

R287
10K

WIFI

C202
390pF
50V

C206
390pF
50V

C208
390pF
50V

C210
390pF
50V

BCM_C0

C210-*1
220pF
50V

BCM_A0/B0

C212
390pF
50V

C214
390pF
50V

C224
1uF
25V
OPT

C226

0.1uF
16V
OPT

C232

4.7uF
10V

L220

MLG1005S22NJT

POWER 2.5V

MAIN POWER

closed to soc

CORE 0.9V

close to soc

50

BCM35230

POWER 3.3V

2

MODEL_OPT_2

LOW

MODEL OPTION

HIGH

HDFHD

LCDOLED

16001333

Support

DDR speed

MODEL_OPT_3

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

MODEL_OPT_7 Enable Disable

Not Support

Not SupportSupport

MODEL_OPT_0

MODEL_OPT_1

00 11

1 100

NO_FRC

BCM
internal
FRC

LG FRC2

external
URSA5

T2 Tuner

S Tuner

PHM

use only for A0/B0 chip

Place as close as possible to the pad

Place as close as possible to the pad

Very close to R22 Ball

Place Cap

Place as close as possible to the pad

Very close to R22 Ball

Place Cap

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

DSUB_B+

C305 1uF 10V

INCM_VID_AV2

INCM_G

C307 1uF 10V

INCM_G

C330 0.1uF

INCM_AUD_AV2

R328 100

SC/COMP2_L_IN

R317
36

R327 100

C311 1uF 10V

R326 100

R324 0

C322 0.1uF

C335 0.1uF

INCM_SIF

SC_B/COMP2_Pb

HP_LOUT_P

SC_RE2INCM_AUD_PC

C319 0.1uF

C306 1uF 10V

AUD_SCK

INCM_B

DSUB_G+

C339
22pF
OPT

C302
33pF
50V

AV1_R_IN

INCM_VID_SC/COMP2

C320 0.1uF

SC/COMP2_R_IN

DSUB_VSYNC

TU_RESET_SUB

DSUB_HSYNC

R320
12K
OPT

C334 0.1uF

INCM_R

C328 0.1uF

R304
36

INCM_VID_COMP1

C338
22pF
OPT

INCM_TUNER

PC_R_IN

SDA3_3.3V

SCL3_3.3V

R303
36

SC_RE1

AUD_MASTER_CLK

C312 1uF 10V

AV2_CVBS_IN

C303 0.1uF

R329 100

C336 0.1uF

INCM_AUD_PC

C324 0.1uF

SC_R/COMP2_Pr

HP_ROUT_N

HP_DET

C340
33pF
OPT

C337
22pF
OPT

C329 0.1uF

INCM_VID_SC

C314 1uF 10V

SC_CVBS_IN

INCM_VID_AV1

SC_FB

R316
36

HP_ROUT_P

TU_SIF

AUD_LRCH

C332 0.1uF

C310 1uF 10V

C323 0.1uF

INCM_B

C313 1uF 10V

C325 0.1uF

R319
10K
OPT

R306
75
1%

OPT

SCART1_Lout_N

M_REMOTE_TX

R311
36

SCART1_Lout_P

C321 0.1uF

INCM_TUNER

TU_RESET

INCM_AUD_SC/COMP2

AV1_CVBS_IN

R314
12K

PC_L_IN

R322 0

C333 0.1uF

R323 0

C318 0.1uF

C316 1uF 10V

DSUB_R+

C331 0.1uF

INCM_AUD_SC/COMP2

SCART1_Rout_P

+3.3V_Normal

INCM_SIF

C317 0.1uF

INCM_AUD_AV2

INCM_R

TU_CVBS

AV1_L_IN

C315 1uF 10V

R315
120
OPT

S2_RESET

C326 0.1uF

INCM_VID_AV2

C327 0.1uF

INCM_AUD_AV1

COMP1_Pb

C304 0.1uF

INCM_VID_AV1

SCART1_Rout_N

INCM_VID_COMP1

AV2_R_IN

C309 1uF 10V

C301
33pF
50V

AV1_CVBS_DET

R313
10K

AV2_L_IN

SC_G/COMP2_Y

COMP1_Y

HP_LOUT_N

SPDIF_OUT

+2.5V_BCM35230

C308 1uF 10V

R321 0

R305
240

OPT

AUD_LRCK

+2.5V_BCM35230

INCM_VID_SC/COMP2

INCM_AUD_AV1

R312
36

/RST_HUB

COMP1_Pr

R302

1.2K

R301

1.2K

LGE35230(BCM35230KFSBG)

IC101

NON_BCM_CAP

VI_R

B6

VI_INCM_R

A6

VI_G

C7

VI_INCM_G

A7

VI_B

B7

VI_INCM_B

C8

HSYNC_IN

C13

VSYNC_IN

A13

VI_Y1

C9

VI_PR1

A9

VI_PB1

B9

VI_INCM_COMP1

B8

VI_SC_R1

C11

VI_SC_G1

A10

VI_SC_B1

B10

VI_INCM_SC1

C10

VI_FB_1/GPIO

D10

VI_FS1

F13

VI_SC_R2

A12

VI_SC_G2

C12

VI_SC_B2

B12

VI_INCM_SC2

B11

VI_FB_2/GPIO

E12

VI_FS2

E14

VI_L1

E15

VI_C1_1

F17

VI_INCM_LC1_1

E16

VI_C1_2

F14

VI_INCM_LC1_2

E11

VI_CVBS1

C18

VI_INCM_CVBS1

B18

VI_CVBS2

A18

VI_INCM_CVBS2

C19

VI_CVBS3

A19

VI_INCM_CVBS3

B19

VI_CVBS4

C20

VI_INCM_CVBS4

B20

VI_SIF1_1

E19

VI_INCM_SIF1_1

D19

VI_SIF1_2

E10

VI_INCM_SIF1_2

F11

LGE35230(BCM35230KFSBG)

IC101

NON_BCM_CAP

SPDIF_INC_P

B15

SPDIF_INC_N

C15

SPDIF_IND_P

C14

SPDIF_IND_N

B14

I2SSCK_IN/GPIO

G4

I2SWS_IN

F4

I2SSD_IN/GPIO

G5

AADC_LINE_L1

C25

AADC_LINE_R1

B24

AADC_INCM1

A24

AADC_LINE_L2

E22

AADC_LINE_R2

E23

AADC_INCM2

D23

AADC_LINE_L3

C24

AADC_LINE_R3

C23

AADC_INCM3

B23

AADC_LINE_L4

E21

AADC_LINE_R4

D21

AADC_INCM4

D22

AADC_LINE_L5

B22

AADC_LINE_R5

C22

AADC_INCM5

A22

AADC_LINE_L6

F21

AADC_LINE_R6

D20

AADC_INCM6

E20

AADC_LINE_L7

A21

AADC_LINE_R7

C21

AADC_INCM7

B21

I2SSCK_OUTA/GPIO

AF8

I2SWS_OUTA/GPIO

AF9

I2SSD_OUTA0/GPIO

AG9

I2SSOSCK_OUTA/GPIO

AC9

I2SSD_OUTA1/GPIO

AD8

I2SSD_OUTA2/GPIO

AD9

I2SSCK_OUTC/GPIO

E2

I2SWS_OUTC/GPIO

F2

I2SSD_OUTC/GPIO

E3

I2SSOSCK_OUTC/GPIO

F3

I2SSCK_OUTD/GPIO

G2

I2SWS_OUTD/GPIO

G3

I2SSD_OUTD/GPIO

G1

I2SSOSCK_OUTD/GPIO

H1

SPDIF_OUTA/GPIO

B13

AUDMUTE_0/GPIO

AG8

AUDMUTE_1

E13

ADAC_AL_N

C28

ADAC_AL_P

C27

ADAC_AR_N

D28

ADAC_AR_P

D27

ADAC_CL_N

C26

ADAC_CL_P

A27

ADAC_CR_N

B27

ADAC_CR_P

B28

ADAC_DL_N

B25

ADAC_DL_P

A25

ADAC_DR_N

A26

ADAC_DR_P

B26

R310
0

R318
0

R325 0

NON_EU

R325-*1

10

EU

LGE35230

IC101-*1

BCM_CAP

VI_R

B6

VI_INCM_R

A6

VI_G

C7

VI_INCM_G

A7

VI_B

B7

VI_INCM_B

C8

HSYNC_IN

C13

VSYNC_IN

A13

VI_Y1

C9

VI_PR1

A9

VI_PB1

B9

VI_INCM_COMP1

B8

VI_SC_R1

C11

VI_SC_G1

A10

VI_SC_B1

B10

VI_INCM_SC1

C10

VI_FB_1/GPIO

D10

VI_FS1

F13

VI_SC_R2

A12

VI_SC_G2

C12

VI_SC_B2

B12

VI_INCM_SC2

B11

VI_FB_2/GPIO

E12

VI_FS2

E14

VI_L1

E15

VI_C1_1

F17

VI_INCM_LC1_1

E16

VI_C1_2

F14

VI_INCM_LC1_2

E11

VI_CVBS1

C18

VI_INCM_CVBS1

B18

VI_CVBS2

A18

VI_INCM_CVBS2

C19

VI_CVBS3

A19

VI_INCM_CVBS3

B19

VI_CVBS4

C20

VI_INCM_CVBS4

B20

VI_SIF1_1

E19

VI_INCM_SIF1_1

D19

VI_SIF1_2

E10

VI_INCM_SIF1_2

F11

BCM35230

3

MAIN AUDIO/VIDEO

50

Run Along DSUB_R Trace

PHONE JACK

Near

TU2101/2
TU2201/2/3

Near

Near

AUDIO INCM

JK1104

Near

Near

Near

JK1102

Route Between PC_L_IN & PC_R_IN Trace

Route Between AV2_L_IN & AV2_R_IN Trace

Run Along AV1_CVBS Trace

JK1102

Run Along TUNER_CVBS_IF_P Trace

JK1103
JK2501

Run Along DSUB_G Trace

Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace

Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace

VIDEO INCM

Route Along With TUNER_SIF_IF_N

Run Along DSUB_B Trace

Near

Run Along AV2_CVBS Trace

Near

JK1103
JK2501

P801

JK1101

TU2101/2
TU2201/2/3

Route Between AV1_L_IN & AV1_R_IN Trace

Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace

Near

P801

Near

Near

P801

Near

JK801

Near

JK1104

BCM35230_with_CAP_220pF