LG 55EC930V-ZA, 55EC940V-ZB Schematic

Internal Use Only

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

OLED TV

SERVICE MANUAL

CHASSIS : ED42D

MODEL : 55EC930V 55EC930V-ZA

55EC940V 55EC940V-ZB

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL68522302 (1408-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 13

BLOCK DIAGRAM ................................................................................. 20

EXPLODED VIEW .................................................................................. 21

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental sh orts of the cir cui try that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the

measured resistance should be between 1 MΩ and 5.2 MΩ.

When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precau­tions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power
source before;

a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug

or other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explo­sion hazard.

2. Test high voltage only by measuring it with an appropriate
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its
assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture.
Unless specied otherwise in this service manual, lubrication

of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks
are correctly installed.

7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged eas­ily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component dam­age caused by static by static electricity.

1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alter­natively, obtain and wear a commercially available discharg­ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.

2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or expo­sure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder
ES devices.

4. Use only an anti-static type solder removal device. Some sol-

der removal devices not classied as “anti-static” can generate
electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads elec­trically shorted together by conductive foam, aluminum foil or
comparable conductive material).

7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective mate­rial to the chassis or circuit assembly into which the device will
be installed.
CAUTION: Be sure no power is applied to the chassis or cir­cuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replace­ment ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity suf­cient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropri­ate tip size and shape that will maintain tip temperature within
the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire­bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand

against the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there
only until the solder ows onto and around both the compo­nent lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent at against the cir­cuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by
gently prying up on the lead with the soldering iron tip as the
solder melts.

2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing
the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and
solder it.

3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor
Removal/Replacement

1. Remove the defective transistor by clipping its leads as close
as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remain­ing on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.

Power Output, Transistor Device
Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit
board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as pos­sible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit
board.

3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.

3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed when­ever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connec­tions).

1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.

1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly con­nected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

Fuse and Conventional Resistor
Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.

2. Securely crimp the leads of replacement component around
notch at stake top.

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This specification is applied to the OLED TV used ED42D
chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage

: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.

(4) Specification and performance of each parts are followed

ea ch dra wing and spe cificat ion by part n umber in
accordance with BOM.

(5) The receiver must be operated for about 5 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

4. Model General Specification

No. Item Specication Remarks

1 Market EU(PAL Market-37Countries) DTV & Analog (Total 37 countries)

DTV (MPEG2/4, DVB-T) : 26 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia,
Bulgaria, France, Spain, Belgium, Luxemburg, Greece, Czech,
Croatia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania, Poland,
Portugal, Romania, Albania, Bosnia, Slovakia, Belarus

DTV (MPEG2/4, DVB-T2): 11 countries

UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kaza­khstan, Russia, Italy, Croatia, Serbia

DTV (MPEG2/4, DVB-C): 37 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia,
Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
Czech, Croatia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania,
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Bela­rus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan

DTV (MPEG2/4, DVB-S): 37 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia,
Bulgaria, France, Spain, Belgium, Luxemburg, Greece, Czech, Tur­key, Morocco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal,
Romania, Albania, Bosnia, Slovakia, Belarus, UK(Ireland), Sweden,
Denmark, Finland, Norway, Ukraine, Kazakhstan, Russia, Italy,
Croatia, Serbia

Supported satellite : 35 satellites

ABS1 75.0E, AMOS 4.0W, ASIASAT3S 105.5E, ASTRA 19.2E,
ASTRA 23.5E, ASTRA 28.2E, ASTRA 4.8E, ATLANTIC BIRD2

8.0W, ATLANTIC BIRD3 5.0W, BADR 26.0E, DIRECTV-1R 56.0E,
EUROBIRD 9A 9.0E, EUROBIRD3 33.0E, EUTELSAT 36 A/B 36.0E,
EUTELSAT W2A 10.0E, EUTELSAT W3A 7.0E, EUTELSAT7WA

7.3W, EUTELSAT 16.0E, EXPRESS AM1 40.0E, EXPRESS AM3

140.0E, EXPRESS AM33 96.5E, HELLASSAT 39.0E, HISPASAT
1CDE 30.0W, HOTBIRD 13.0E, INTELSAT10&7 68.5E, INTELSAT15

85.2E, INTELSAT1R 50.0W, INTELSAT903 33.5W, INTELSAT904

60.0E, NILESAT 7.0W, NSS12 57.0E, THOR 0.8W, TURKSAT

42.0E,YAMAL201 90.0E, OTHER

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

No. Item Specication Remarks

1) Digital TV

- DVB-T/T2

- DVB-C

2 Broadcasting system

3 Program coverage

4 Receiving system

- DVB-S/S2

2) Analogue TV

- PAL/SECAM B/G/I/D/K

- SECAM L/L’

1) Digital TV

- VHF, UHF

- C-Band, Ku-Band

2) Analogue TV

- VHF : E2 to E12

- UHF : E21 to E69

- CATV : S1 to S20

- HYPER : S21 to S47

Analog : Upper Heterodyne
Digital : COFDM, QAM

► DVB-T

- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32

- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2 (Model : *L*V*-Z* (T2 only Model))

- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,

- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C

- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s

- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2

- symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s

- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10

5 Scart (1EA) PAL, SECAM

6 Video Input RCA(1EA) PAL, SECAM, NTSC4.43 4 System : PAL, SECAM, NTSC4.43, PAL60
7 Component Input (1EA) Y/Cb/Cr, Y/Pb/Pr 480i /576i/480p/576p/720p/1080i/1080p

8 HDMI Input (4EA)

9 Audio Input (1EA) DVI Audio, AV1/AV2/Component L/R Input.

10 Head phone out (1EA)

11 SDPIF out (1EA) SPDIF out
12 USB (3EA) EMF, DivX HD, For SVC (download) JPEG, MP3, DivX HD
13 Ethernet Connect(1EA) Ethernet Connect
14 PCMCIA Card slot (1EA) PCMCIA slot
15 RS-232C(1EA) For SVC only Side, Phone type

HDMI1-DTV, HDMI2-DTV, HDMI3-DTV,
HDMI4-DTV

Antenna, AV1, AV2, Component,
HDMI1, HDMI2, HDMI3, HDMI4, USB1,
USB2, USB3

Scart Jack is Full scart and support ATV/DTV-OUT
(not support DTV Auto AV)

HDMI1: PC support(HDMI version 1.4)
Support HDCP

Only for training and service purposes

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Component Video Input (Y, Pb, Pr)

No.

1. 720×480 15.73 60.00 SDTV, DVD 480i

2. 720×480 15.63 59.94 SDTV, DVD 480i

3. 720×480 31.47 59.94 480p

4. 720×480 31.50 60.00 480p

5. 720×576 15.625 50.00 SDTV, DVD 625 Line

6. 720×576 31.25 50.00 HDTV 576p

7. 1280×720 45.00 50.00 HDTV 720p

8. 1280×720 44.96 59.94 HDTV 720p

9. 1280×720 45.00 60.00 HDTV 720p

10. 1920×1080 31.25 50.00 HDTV 1080i

11. 1920×1080 33.75 60.00 HDTV 1080i

12. 1920×1080 33.72 59.94 HDTV 1080i

13. 1920×1080 56.250 50 HDTV 1080p

14. 1920×1080 67.5 60 HDTV 1080p

Resolution H-freq(kHz) V-freq(Hz) Pixel clock

Specication

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

6. HDMI Input

6.1. DTV mode

No. Resolution H-freq(kHz) V-freq.(Hz) Proposed

1. 640*480 31.469 / 31.5 59.94/60 SDTV 480P

2. 720*480 31.469 / 31.5 59.94 / 60 SDTV 480P

3. 720*576 31.25 50 SDTV 576P

4. 720*576 15.625 50 SDTV 576I

5. 1280*720 37.500 50 HDTV 720P

6. 1280*720 44.96 / 45 59.94 / 60 HDTV 720P

7. 1920*1080 33.72 / 33.75 59.94 / 60 HDTV 1080I

8. 1920*1080 28.125 50.00 HDTV 1080I

9. 1920*1080 26.97 / 27 23.97 / 24 HDTV 1080P

10. 1920*1080 28.125 25 HDTV 1080P

11. 1920*1080 33.716 / 33.75 29.976 / 30.00 HDTV 1080P

12. 1920*1080 56.250 50 HDTV 1080P

13. 1920*1080 67.43 / 67.5 59.94 / 60 HDTV 1080P

6.2. PC mode

No. Resolution H-freq(kHz) V-freq.(Hz) Proposed

1 640 x 350 @70Hz 31.468 70.09 EGA

2 720 x 400 @70Hz 31.469 70.08 DOS

3 640 x 480 @60Hz 31.469 59.94 VESA(VGA)

4 800 x 600 @60Hz 37.879 60.31 VESA(SVGA)

5 1024 x 768 @60Hz 48.363 60.00 VESA(XGA)

6 1152 x 864 @60Hz 54.348 60.053 VESA

7 1280 x 1024 @60Hz 63.981 60.020 VESA(SXGA)

8 1360 x 768 @60Hz 47.712 60.015 VESA(WXGA)

9 1920 x 1080 @60Hz 67.5 60.00 WUXGA(Reduced Blanking))

Only for training and service purposes

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

7. 3D Mode

7.1. HDMI 1.4b (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed

1

640*480

2 62.938 / 63 59.94/ 60 50.35/50.4 1

3 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)

4

720*480

5 62.938 / 63 59.94 / 60 54/54.06 2,3

6 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)

7

720*576

8 62.5 50 54 17,18

9 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)

10

11 75 50 148.5 19

12 37.5 50 148.5 19 Side-by-side(Full) (HDTV 720P)

1280*720

13 44.96 / 45 59.94 / 60 74.18/74.25 4

14 89.91 / 90 59.94 / 60 148.35/148.5 4

15 44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)

16

17 67.432 / 67.5 59.94 / 60 148.35/148.5 5

18 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)

19 28.125 50.00 74.25 20

20 56.25 50.00 148.5 20

21 28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I)

22 26.97 / 27 23.97 / 24 74.18/74.25 32

23 43.94 / 54 23.97 / 24 148.35/148.5 32

1920*1080

24 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)

25 28.125 25 74.25 33

26 56.25 25 148.5 33

27 28.125 25 148.5 33 Side-by-side(Full) (HDTV 1080P)

28 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34

29 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34

30 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)

31 56.25 50 148.5 31

32 67.43 / 67.5 59.94 / 60 148.35/148.50 16

31.469 / 31.5 59.94/ 60 25.175/25.2 1

31.469 / 31.5 59.94 / 60 27.00/27.03 2,3

31.25 50 27 17,18

37.5 50 74.25 19

33.72 / 33.75 59.94 / 60 74.18/74.25 5

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Field alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Field alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Frame packing
Line alternative

Top-and-Bottom
Side-by-side(half)

Top-and-Bottom
Side-by-side(half)

Secondary(SDTV 480P)
Secondary(SDTV 480P)

Secondary(SDTV 480P)

(SDTV 480P)

Secondary(SDTV 480P)
Secondary(SDTV 480P)

Secondary(SDTV 480P)

(SDTV 480P)

Secondary(SDTV 576P)
Secondary(SDTV 576P)

Secondary(SDTV 576P)

(SDTV 576P)

Primary(HDTV 720P)
Primary(HDTV 720P)

Primary(HDTV 720P)

(HDTV 720P)

Primary(HDTV 720P)
Primary(HDTV 720P)

Primary(HDTV 720P)

(HDTV 720P)

Secondary(HDTV 1080I)

Primary(HDTV 1080I)

Primary(HDTV 1080I)

(HDTV 1080I)

Secondary(HDTV 1080I)

Primary(HDTV 1080I)

Primary(HDTV 1080I)

(HDTV 1080I)

Primary(HDTV 1080P)
Primary(HDTV 1080P)

Primary(HDTV 1080P)

(HDTV 1080P)

Secondary(HDTV 1080P)
Secondary(HDTV 1080P)

Secondary(HDTV 1080P)

(HDTV 1080P)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

Primary(HDTV 1080P)

(HDTV 1080P)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

Only for training and service purposes

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

7.2. HDMI Input(1.3)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode

1 720*480 31.5 60 27.03 SDTV 480P

2 720*576 31.25 50 27 SDTV 576P

3 1280*720 45.00 60.00 74.25 HDTV 720P

4 1280*720 37.500 50 74.25 HDTV 720P

5 1920*1080 33.75 60.00 74.25 HDTV 1080I

6 1920*1080 28.125 50.00 74.25 HDTV 1080I

7 1920*1080 27.00 24.00 74.25 HDTV 1080P

8 1920*1080 28.12 25 74.25 HDTV 1080P

9 1920*1080 33.75 30.00 74.25 HDTV 1080P

10 1920*1080 67.50 60.00 148.5 HDTV 1080P

11 1920*1080 56.250 50 148.5 HDTV 1080P

2D to 3D, Side by Side(Half), Top & Bot­tom, Checker Board, Frame Sequential,
Row Interleaving, Column Interleaving

2D to 3D, Side by Side(Half), Top & Bottom

2D to 3D, Side by Side(Half), Top & Bot­tom, Checker Board, Row Interleaving,
Column Interleaving

2D to 3D, Side by Side(Half), Top &
Bottom, Checker Board, Single Frame
Sequential, Row Interleaving, Column
Interleaving

7.3. RF Input(3D supported mode manually)

No. Resolution Proposed 3D input proposed mode

1 HD (DTV)

2 SD (DTV)

3 SD (ATV : CVBS / SCART) -

1080I

720P

576P

576I

2D to 3D
Side by Side(Half)
Top & Bottom

7.4. RF Input (3D supported mode automatically)

No. Signal 3D input proposed mode

1 Frame Compatible Side by Side(Half), Top & Bottom

7.5. USB, DLNA (Movie) Input (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 704x480 - - - 2D to 3D

Over 704x480

2

interlaced

Over 704x480

3

progressive

Over 704x480

4

progressive

- - - 2D to 3D, Side by Side(Half), Top & Bottom

- 50 / 60 -

- others -

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board,
Row Interleaving, Column Interleaving, Frame Sequential

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board,
Row Interleaving, Column Interleaving

7.6. USB, DLNA (Photo) Input (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 320x240 - - - 2D to 3D

2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom

Only for training and service purposes

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* USB, DNLA Input (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1080P 33.75 30 -

Side by Side(Half), Top & Bottom, Checker Board,
MPO(Photo), JPS(Photo)

7.7. HDMI-PC Input (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1024*768 48.36 60 65

2 1360*768 47.71 60 85.5

3 1920*1080 67.500 60 148.50

4 Others - - -

2D to 3D, Side by Side(half)
Top & Bottom

2D to 3D, Side by Side(half), Top
& Bottom, Checker Board, Single
Frame Sequential, Row Interleaving,
Column Interleaving

2D to 3D,
Side by Side(half)
Top & Bottom

HDTV 768P

HDTV 1080P

640*350
720*400
640*480
800*600
1152*864

7.8. Component Input(3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P

2 1280*720 37.500 50 74.25 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I

4 1920*1080 28.125 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

6 1920*1080 28.12 25 74.25 HDTV 1080P

7 1920*1080 33.75 30.00 74.25 HDTV 1080P

8 1920*1080 67.50 60.00 148.5 HDTV 1080P

9 1920*1080 56.250 50 148.5 HDTV 1080P

10 Others - - - SDTV

2D to 3D, Side by Side(Half), Top & Bottom

7.9. Miracast, Widi (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1024X768p - 30 / 60 -

2D to 3D, Side by Side(Half), Top & Bottom2. 1280x720p - 30 / 60 -

3 1920X1080p 30 / 60

4 Others - 2D to 3D

7.10. 3D Input mode

No. Side by Side Top & Bottom Checker board

1

ii.

Only for training and service purposes

iii.

iv.

- 12 -

Single Frame

Sequential

Frame

Packing

v.

vi.

2D to 3D

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to ED42D Chassis applied
OLED TV all models manufactured in TV factory.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz.
(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15 °C.

In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
hours.
In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.

[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.

(3) Download process

1) Select the download items.

2) Mode check: Online Only

3) Check the test process

: DETECT → MAC_WRITE → ESN → WID EVI NE_

WRITE → CI+ → HDCP14 → HDCP20

4) Play: START

5) Check of result: Ready, Test, OK or NG

(4) Inspection

- In INSTART menu, check these keys.

3.3. LAN port Inspection

3.3.1. Equipment and Condition

Each other connection to LAN Port of IP Hub and Jig.

3.3.2. LAN inspection solution

▪ LAN Port connection with PCB
▪ Setting automatic IP

3. MAIN PCBA Adjustments

3.1. ADC Calibration

- An ADC calibration is not necessary because MAIN SoC

(LGE1311) is already calibrated from IC Maker.

3.2. MAC Address, ESN, Widevine, HDCP2.0
key download

* CI+ key : only for ED42D(55EC930V-ZA)

(1) Equipment & Condition

1) Play file: keydownload.exe

(2) Communication Port connection

1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

3) Connect

: PCBA Jig → RS-232C Port == PC → RS-232C Port

▪ If you want manual connection, enter Network connection at

MENU Mode of TV. Press Start connection key, then
Network will be connected.

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

3.2.3. Widevine, ESN, HDCP1.4, HDCP2.0 key inspection

- Confirm key input data at the "IN START" MENU Mode.



3.3. LAN PORT INSPECTION(PING TEST)

3.3.1. Equipment setting

(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program.

- IP Number : 12.12.2.2

Connect: SET → LAN Port == PC → LAN Port

SET PC

3.3.2. LAN PORT inspection(PING TEST)

(1) Play the LAN Port Test Program.
(2) Connect each other LAN Port Jack.
(3) Play Test (F9) button and confirm OK Message.
(4) Remove LAN cable.

3.4. Model name & Serial number Download

3.4.1. Model name & Serial number D/L

▪ Press "P-ONLY" key of service remote control.

(Baud rate : 115200 bps)

▪ Connect RS-232C Signal to USB Cable to USB.
▪ Write Serial number by use USB port.
▪ Must check the serial number at Instart menu.

3.4.2. Method & notice

(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory
by D-book 4.0.

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always)
It is impossible to download by bar code scan, so It need
Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name or Serial number
[Example]

4) Check the model name Instart menu. → Factory name

displayed.

[Example]

3.5. CI+ Key checking method

* Only for ED42D(55EC930V-ZA)

Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).

Check the Download to CI+ Key value in LGset.

3.5.1. Check the method of CI+ Key value

(1) Check the method on Instart menu
(2) Check the method of RS232C Command

1) Into the main ass’y mode(RS232: aa 00 00)

CMD 1 CMD 2 Data 0

A A 0 0

2) Check the key download for transmitted command
(RS232: ci 00 10)

CMD 1 CMD 2 Data 0

C I 1 0

3) Result value

- Normally status for download : OKx

- Abnormally status for download : NGx

3.5.2. Check the method of CI+ key value(RS232)

1) Into the main ass’y mode(RS232: aa 00 00)

CMD 1 CMD 2 Data 0

A A 0 0

2) Check the mothed of CI+ key by command
(RS232: ci 00 20)

CMD 1 CMD 2 Data 0

C I 2 0

3) Result value
i 01 OK 1d1852d21c1ed5dcx

CI+ Key Value

Only for training and service purposes

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4. Manual Adjustment

4.1. ADC adjustment need not. Because of
OTP(Auto ADC adjustment)

4.2. EDID DATA

HDMI EDID DATA 3D

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D

ⓒ

10
20 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20
70
80 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 29 3D 06 C0 15 07 50 09 57 07
A0
B0
C0 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18
D0 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D
E0 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

ⓓ

ⓕ

ⓕ ⓖ

- HDMI1 ~ HDMI4

- In the data of EDID, bellows may be different by Input mode.

ⓐ Product ID

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ → ‘01’, Year : ‘2014’ → ‘18’

ⓓ Model Name(Hex): LGTV

Chassis MODEL NAME(HEX)

ED42D 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ Checksum(LG TV): Changeable by total EDID data.

Input ⓔ1 ⓔ2 ⓔ3

HDMI1 E7 85 X

HDMI2 E7 75 X

HDMI3 E7 65 X

HDMI4 E7 55 X

ⓕ Vendor Specific(HDMI)

INPUT MODEL NAME(HEX)

HDMI1 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10

HDMI2 78 03 0C 00 20 00 B8 2D 20 C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10

HDMI3 78 03 0C 00 30 00 B8 2D 20 C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10

HDMI4 78 03 0C 00 40 00 B8 2D 20 C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10

ⓐ ⓑ

ⓓ

ⓔ1

01

ⓕ

02 3A 80 18 71 38

ⓔ2

5. White Balance Adjustment

5.1. Overview

5.1.1. W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation
(2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Surrounding Humidity : 20 % ~ 80 %

3) Surrounding Humidity: 20% ~ 80%

4) Befor e White balance adjustment, Keep power on
status, don’t power off

5.1.2. Adj. condition and cautionary items

(1) Lighting condition in surrounding area surrounding lighting

should be lower 10 lux. Try to isolate adj. area into dark
surrounding.

(2) Probe location: Color Analyzer(CA-210) probe should be

within 10 cm and perpendicular of the module surface
(80°~ 100°).

(3) Aging time

1) After Aging Start, Keep the Power ON status during 5
Minutes.

2) In case of LCD, Back-light on should be checked using
no signal or Full-white pattern.

5.2. Equipment

(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:

CH14 / OLED : CH : 17)

(2) Adjustment Computer(During auto adj., RS-232C protocol

is needed)
(3) Adjustment Remote control
(4) Video Signal Generator MSPG-925F 720p/204-Gray

(Model: 217, Pattern: 49)

▪ Color Analyzer Matrix should be calibrated using CS-1000.

5.3. Equipment connection MAP

Col or Analy zer

Pro be

USB t o RS-23 2C

Sig nal Sou rce

* If TV internal pattern is used, not needed

* Pat tern Ge nerat or

RS- 232C

Com puter

RS- 232C

ⓖ Colorimetry Data Block(HDMI) : Not supporting XvYcc

INPUT MODEL NAME(HEX)

HDMI1 E3 05 00 00

HDMI2 E3 05 00 00

HDMI3 E3 05 00 00

Only for training and service purposes

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.4. Adj. Command (Protocol)

(1) RS-232C Command used during auto-adj.

RS-232C COMMAND

CMD DATA ID

Wb 00 00 Begin White Balance adj.

Wb 00 ff

End White Balance adj.(internal pattern disappears)

(2) Adjustment Map

Command

(lower case ASCII)

CMD1 CMD2 MIN MAX

Cool

Medium

Warm

Adj. item

R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

R Cut

G Cut

B Cut

R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

R Cut

G Cut

B Cut

R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

R Cut

G Cut

Explanation

Data Range

(Hex.)

Default

(Decimal)

5.6. Reference(White Balance Adj. coordinate
and color temperature)

(1) Luminance: 204 Gray, 80IRE
(2) Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Coordinate

x y

Temp ∆uv

Cool 0.277 0.278 11,000K -0.0030

Medium 0.286 0.289 9,300K 0.0000

Warm 0.313 0.329 6,500K +0.0030

(3) Standard color coordinate and temperature using CA-210

(CH-17)

Mode

Coordinate

x y

Temp ∆uv

Cool 0.277 ± 0.002 0.278 ± 0.002 11,000 K -0.0030

Medium 0.286 ± 0.002 0.289 ± 0.002 9,300 K 0.0000

Warm 0.313 ± 0.002 0.329 ± 0.002 6,500 K +0.0030

6. Tool Option setting & Inspection

▪ Press "ADJ" key on the Adjustment remote control, then

select Tool option.

Model Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6 Tool 7

55EC930V-ZA 33894 5139 700 64797 2214 2431 34703

5.5. Adjustment method

5.5.1. Auto WB calibration

(1) Set TV in ADJ mode using P-Only key(or POWER ON key).
(2) Place optical probe on the center of the display.

- It need to check probe condition of zero calibration before
adjustment.

(3) Connect RS-232C Cable
(4) Select mode in ADJ Program and begin adjustment.
(5) When WB adjustment is completed with OK message, check

adjustment status pre-set mode.(Cool, Medium, Warm)

(6) Remove probe and RS-232C cable

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

5.5.2. White balance table

(1) Cool Mode

1) Purpose : Especially G-gain fix adjust leads to the

luminance enhancement. Adjust the color temperature
to reduce the deviation of the module color temperature.

2) Pr inciple : To adjust the white balance wit hout the

saturation, Adjust the G gain more than 172 (If R gain or
G gain is more than 255, G gain can adjust less than
172 ) and change the others (R/B Gain).

3) Adjustment mode : mode - Cool

(2) Medium / Warm Mode

1) Purpose : Adjust the color temperature to reduce the

deviation of the module color temperature.

2) Pr inciple : To adjust the white balance wit hout the

saturation, Fix the one of R/G/B gain to 192 (default
data) and decrease the others.

3) Adjustment mode : Two modes - Medium / Warm

7. Magic motion remote control check

Results are automatically marked in Instart OSD after through
the AP/Magic Remocon Equipment on the line.

Only for training and service purposes

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

8. WIFI MAC ADDRESS CHECK

(1) Using RS232

Command Set ACK

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

(2) Check the menu on in-start

9. 3D pattern test

9.1. Test equipment

(1) Pattern Generator MSHG-600 or MSPG-6100 (HDMI 1.4

support)

(2) Pattern: HDMI mode (model No. 872, pattern No. 83)

10. Eye-Q function check

(1) Press 'EYE button' on the adjustment remote-control.
(2) Check each raw data.
(3) Cover 'Eye Q sensor' on the front of set with hand and wait

for 6 seconds.

(4) Check each data is lower than 10 and ‘OK’ message. If data

isn’t lower than 10 in 6 seconds, replace Eye Q sensor.
(5) Uncover hand from Eye Q sensor and wait for 6 seconds.
(6) Check each data increase or not. If data don’t increase,

replace Eye Q sensor.

11. Joystick function check

(1) Channel Up Test : Press UP KEY OF SET

9.2. Test method

(1) Input 3D test signal as below.

<Fig.1> HDMI Mode No.872, Pattern No. 83

(2) Press ‘OK” key as a 3D input OSD is shown.
(3) Check pattern as Fig2 without 3D glasses. (3D mode

without 3D glasses)

<Fig.2> OK in 3D mode without

3D glasses

<Fig.3> NG in 3D mode without

3D glasses

(2) Channel Down Test : Press DOWN KEY OF SET

(3) Volume Up Test : Press Left KEY OF SET

(4) Volume Down Test : Press Right KEY OF SET

Only for training and service purposes

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

(5) Enter Test : Press Enter KEY OF SET

- Don’t need to run a test with this sequence. For example,

the sequence such as ‘Right → Up → Down → Left → Enter’

is allowed.

13. AUDIO output check

13.1. AUDIO output check

(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal (0.5 Vrms)

13.2. Specification

Item Min Typ Max Unit Remark

Audio practical
max Output, L/R

(Distortion=10%

max Output)

9.0 10.0 12.0 W

8.5 8.9 9.9 Vrms

- Condition: EQ/AVL/Clear
Voice Off

- Speaker (8Ω Impedance)

12. HDMI ARC Function Inspection

12.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

12.2. Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

(2) Check the sound from the TV Set

(3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

13.3. Audio Output Inspection

- Input “Check-S KEY” of adjust remote controller to inspect
speaker

(1) When you click the first, the output volume of left &right

main speakers must be 50.

(2) When you click the second, the output volume of left &right

main speakers must be 80.

(3) When you click the third, the output volume of left &right

main speakers must be 100.

(4) When you click the fourth, the output volume of left main

speaker must be 50.

(5) When you click the fifth, the output volume of right main

speaker must be 50.

14. GND and HI-POT Test

14.1. GND & HI-POT auto-check preparation

- Check the POWER cable and SIGNAL cable insert ion
condition

14.2. GND & HI-POT auto-check

(1) Pallet moves in the station. (POWER CORD / AV CORD is

tightly inserted)
(2) Connect the AV JACK Tester.
(3) Controller (GWS103-4) on.
(4) GND Test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, execute next process (Hi-pot test).
(Remove A/V CORD from A/V JACK BOX)

(5) HI-POT test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, GOOD Lamp on and move to next
process automatically.

* Remark: Inspect in Power Only Mode and check SW version

in master equipment

Only for training and service purposes

14.3. Checkpoint

(1) Test voltage

- GND: 1.5 KV/min at 100 mA

- SIGNAL: 3 KV/min at 100 mA

(2) TEST time: 1 second
(3) TEST POINT

- GND Test = POWER CORD GND and SIGNAL CABLE

GND.

- Hi-po t Test = PO WE R COR D GND an d LI VE &

NEUTRAL.

(4) LEAKAGE CURRENT: At 0.5 mArms

- 18 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

15. USB S/W download(Service only)

(1) Put the USB Stick to the USB socket.
(2) Go to General menu then enter to About This TV.

(3) Enter the USB EXPERT MODE.

(4) Updating is starting.
(5) Updating completed, the TV will restart automatically
(6) If your TV is turned on, check your updated version and

Tool option.

* If downloading version is more high than your TV have,

TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
have a DTV/ATV test on production line.

* After downloading, Tool option setting is needed again.

(1) Push "IN-START" key in service remote control.
(2) Select "Tool Option 1" and push "OK" key.
(3) Punch in the number. (Each model has their number)

Only for training and service purposes

- 19 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

BLOCK DIAGRAM

SUB

ASSY

IR

KEY

I2C

LGD T-CON

SYSTEM EEPROM

DDR3 1600 X 16

(256MB X 2EA)

DDR3 1600 X 16

(512MB X 2EA)

X_TAL

24MHz

P_TS

P_TS

(256Kb)

eMMC

(8GB : AJJA)(4GB: EU,CN)

51P MCX cable

I2C 5

A B

P_TS P_TS

Analo g Demo d

Dig ital Demod(T/C)

P_TS

IF (+/-)

Vby1

USB 2.0

USB 3.0

OCP

1.5A

OCP

1.5A

I2C1

Audio AMP (Front)

Audio AMP (Tweeter)

I2C 1

I2S Out

IC101

M14

HDMI

MUX

OCP

1A

WIFI

BLUETOOTH

USB_WIFI-BT

AMP

TI

IR / KEY/EYE

YPbP

r

CVB

S

CVBS/RGB

PWM

Sub Mic om

LOGO LIGHT

I2C 3

ETHERNET

SPDIF OUT

LAN

PHY

X_TAL

32.768KHz

(RENESAS

R5F1000G)

X_TAL

25MHz

CI Slot

IF

Si2158B

DVB T/C TUNER

ATV /

DVB-T/C

Only for training and service purposes

Tuner : I2C 6

D-Demod : I2C 4

REA

DVB T2/C/S2 TUNER

SID

R

AV

COMP

LAN

OPTIC

(ARC)S

HDMI2

USB1(2.0)

AIF

HDMI1

USB2(2.0)

USB3(2.0)

E

IDE

TS_ [0:7]

(MHL)

HDMI3

HDMI4

H/P (Line Out)

(IR Bla Ready)

DIF

CXD2844

IQ

RDA

5815M

Si2158B

ATV /

DVB-S

DVB-T/C

(H)

LNB

DVB-S : I2C 4

- 20 -

SCART

REA

LGE

MAIN PCB

R

- 10 bit

- YUV444

4lane

Vby1

LGD

- 120 Hz

Module

T-CON 120Hz

interface

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

400

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

AV1

700

710

LV1

200

521

530

540

522

570

571

502

500

501

900

510

511

121

811

120

810

AT1

AG1

Only for training and service purposes

- 21 -

A22

A2

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

System Configuration

Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

Clock for M14-A0

MAIN Clock(24Mhz)

LOADCAP_ATSC_PCB

10pF

C101

C102
LOADCAP_ATSC_PCB

System Clock for Analog block(24Mhz)

PLL SET[1:0] : internal pull up
"00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz)
"10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz)
"11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)

OP MODE[1:0]
"00" : Normal Mode
"01/10/11" : Internal Test mode

+3.3V_NORMAL

R101 3.3K

R102 3.3K

Extenal test only

+3.3V_NORMAL

+3.3V_TUNER

R148

3.3K

R146

3.3K

KR_PIP_NOT

KR_PIP_NOT

1.5K

1.5K

KR_PIP

R146-*1

KR_PIP

R148-*1

10pF

Extenal test only

OPT

OPT

R149

2

3

OPT

R103 3.3K

R104 3.3K

OPT

3.3K

X-TAL_1

GND_1

1

X101

24MHz

4

GND_2

X-TAL_2

PLLSET1

PLLSET0

OPM1

OPM0

+3.3V_TUNER

R150

3.3K

R155

1.2K

KR_PIP_NOT

3.3K

KR_PIP

KR_PIP

R155-*1

1M

R118

R180
560

LOADCAP_DVB_PCB

C101-*1

6.8pF
50V

+3.3V_NORMAL

3.3K

R121

OPT

INSTANT_MODE0

+3.3V_NORMAL

R157

R156

KR_PIP_NOT

3.3K

R156-*1

3.3K

1.2K

XTAL_IN

XTAL_OUT

LOADCAP_DVB_PCB

C102-*1

6.8pF
50V

INSTANT boot MODE
"1 : Instant boot
"0 : normal

(internal pull down)

INSTANT_BOOT

I2C PULL UP

R159

3.3K

R158

3.3K

R160

3.3K

R161

+3.3V_NORMAL

3.3K

R127

OPT

3.3K

R128

BOOT_MODE0

I2C

I2C_1 : AMP
I2C_2 : T-CON,L/DIMING
I2C_3 : MICOM
I2C_4 : S/Demod,T2/Demod, LNB
I2C_5 : NVRAM
I2C_6 : TUNER_MOPLL(T/C,ATV)

R162

3.3K

3.3K

IC103

AT24C256C-SSHL-T

A0

1

A1

2

A2

3

GND

4

NVRAM_ATMEL

BOOT MODE
"0 : EMMC
"1 : TEST MODE



BOOT_MODE

I2C_SDA1
I2C_SCL1
I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC
I2C_SDA2
I2C_SCL2

I2C_SDA4
I2C_SCL4

I2C_SDA5
I2C_SCL5

I2C_SDA6
I2C_SCL6

NVRAM

VCC

8

WP

7

SCL

6

SDA

5

+3.3V_NORMAL

C107

0.1uF
16V

Write Protection

- Low : Normal Operation

- High : Write Protection

R143 33

R144 33

IC103-*1

M24256-BRMN6TP

E0

VCC

1

8

WC

E1

7

2

SCL

E2

6

3

SDA

VSS

5

4

NVRAM_ST

I2C_SCL5

I2C_SDA5

I2C_SCL_MICOM_SOC
I2C_SDA_MICOM_SOC

LOCAL DIMMING I2C CONTROL

+3.3V_NORMAL

OPT

OPT

R105

3.3K

R106

3.3K

LED_SCL
LED_SDA

SOC_RESET

FORCED_JTAG_0

P102

12507WS-04L

1

2

3

4

5

+3.3V_NORMAL

R163
10K

OPT

C104

0.1uF
16V

L/DIM0_VS

L/DIM0_SCLK

L/DIM0_MOSI

IRB_SPI_MOSI/TDO1
IRB_SPI_MISO/TDI1

M_REMOTE_RX
M_REMOTE_TX

1/16W

33

AR100

I2C_SCL4
I2C_SDA4

I2C_SCL6
I2C_SDA6

PWM_DIM2

PWM_DIM

EMMC_CLK
EMMC_CMD
EMMC_RST

EMMC_DATA[0-7]

OPT

XTAL_IN

XTAL_OUT

BOOT_MODE

PLLSET0
PLLSET1

TCK0
TDI0

TRST_N1
IRB_SPI_SS/TMS1
IRB_SPI_CK/TCK1

I2C_SCL1
I2C_SDA1

I2C_SCL2
I2C_SDA2

I2C_SCL5
I2C_SDA5

33

R107

33

R108

OPM0
OPM1

R178 33

OPT

R182 10K

R183 10K
R184 10K

R185 10K

SOC_RX

SOC_TX

EMMC_DATA[7]
EMMC_DATA[6]
EMMC_DATA[5]
EMMC_DATA[4]
EMMC_DATA[3]
EMMC_DATA[2]
EMMC_DATA[1]
EMMC_DATA[0]

12505WS-10A00

JTAG_CPU

B23
A23

R169

AG21

33

AJ18

AB8
AC8

AD8
AE8

AR101

AG30
AG28
AG29
AH29
AJ27
AH27
AG26
AH26

AJ12
AJ13
AH12
AG12

AH23
AG22

AH11
AG11

AG10

AH22
AJ22
AH10
AJ10
AG23
AH24

Y7
Y6
W7
W6
W5

AH7
AJ7

AG8
AH8

AH9
AG9

AJ9

AC6
AC7
AD7
AB7

G32
G33
G31
D31
F33
F32
E32
F31
D33
D32
E31

33

R179
10K

1/16W
5%

Jtag-0 I/F

+3.3V_NORMAL

P103

1

2

3

4

5

6

7

8

9

10

11

M14_LCD

IC101

LG1311

XIN_MAIN
XO_MAIN

PORES_N

BOOT_MODE

PLLSET0
PLLSET1

OPM0
OPM1

L_VSOUT_LD/TRST0_N
DIM0_SCLK/TMS0
DIM1_SCLK/TCK0
DIM1_MOSI/TDI0
DIM0_MOSI/TDO0

SPI_CS0
SPI_SCLK0
SPI_DO0
SPI_DI0/TRST1_N
SPI_CS1/TMS1
SPI_SCLK1/TCK1
SPI_DO1/TDO1
SPI_DI1/TDI1

EXT_INTR0
EXT_INTR1
EXT_INTR2
EXT_INTR3

UART0_RXD
UART0_TXD
UART1_RXD
UART1_TXD

UART1_RTS_N
UART1_CTS_N

SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
SCL4
SDA4
SCL5
SDA5

PWM0
PWM1
PWM2
PWM_IN

EMMC_CLK
EMMC_CMD
EMMC_RESETN
EMMC_DATA7
EMMC_DATA6
EMMC_DATA5
EMMC_DATA4
EMMC_DATA3
EMMC_DATA2
EMMC_DATA1
EMMC_DATA0

USB2_0_DP0
USB2_0_DM0

USB2_0_TXRTUNE

USB2_1_DP0
USB2_1_DM0

USB2_1_TXRTUNE

USB3_DP0

USB3_DM0
USB3_TXP0
USB3_TXM0
USB3_RXP0
USB3_RXM0

USB3_RESREF0

USB3_DP1

USB3_DM1
USB3_TXP1
USB3_TXM1
USB3_RXP1
USB3_RXM1

USB3_RESREF1

HUB_PORT_OVER0
HUB_VBUS_CTRL0

EB_CS3
EB_CS2
EB_CS1
EB_CS0

EB_WE_N
EB_OE_N

EB_WAIT
EB_BE_N1
EB_BE_N0

CAM_CD1_N
CAM_CD2_N
CAM_CE1_N
CAM_CE2_N

CAM_IREQ_N

CAM_RESET

CAM_INPACK_N

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

EB_ADDR0
EB_ADDR1
EB_ADDR2
EB_ADDR3
EB_ADDR4
EB_ADDR5
EB_ADDR6
EB_ADDR7
EB_ADDR8
EB_ADDR9

EB_ADDR10
EB_ADDR11
EB_ADDR12
EB_ADDR13
EB_ADDR14
EB_ADDR15

EB_DATA0
EB_DATA1
EB_DATA2
EB_DATA3
EB_DATA4
EB_DATA5
EB_DATA6
EB_DATA7

L/DIM0_VS

TDI0

L/DIM0_MOSI

L/DIM0_SCLK

TCK0

SOC_RESET

FORCED_JTAG_0

AN9
AM9
AN8

H32
J31
H33

N31
N32
P33
P32
M32
M33
P31

K33
K32
L32
L31
K31
J32
M31

W28
W29

H28
J30
J28
J29

G30
F30
H29
G29
G28

P28
P27
U28
R29
V27
T28
T29
R28
U27
N29

K30
E30
M30
N28
M28
M29
L29
K29
K28
L28
D30

EB_ADDR[10]

F29

EB_ADDR[11]

C32

EB_ADDR[12]

C33

EB_ADDR[13]

C31

EB_ADDR[14]

B33

B32
A32
B31
A31
A30
B30
C30
C29

(TRST0_N)

(TDO0)

(TMS0)

R1712001%

R1722001%

R1732001%

R1742001%

/USB_OCD1

/USB_OCD2
/USB_OCD3

EB_BE_N1
EB_BE_N0

CAM_CD1_N
CAM_CD2_N

CAM_IREQ_N
CAM_INPACK_N
CAM_WAIT_N

EB_ADDR[0]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]
EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[6]
EB_ADDR[7]
EB_ADDR[8]
EB_ADDR[9]

EB_DATA[0]
EB_DATA[1]
EB_DATA[2]
EB_DATA[3]
EB_DATA[4]
EB_DATA[5]
EB_DATA[6]
EB_DATA[7]

12505WS-10A00

WIFI_DP
WIFI_DM

USB_DP3
USB_DM3

USB_DP1
USB_DM1

USB_DP2
USB_DM2

USB_CTL1

USB_CTL2
USB_CTL3
EB_WE_N

EB_OE_N

/PCM_CE1
/PCM_CE2

PCM_RESET
PCM_5V_CTL
CAM_REG_N

Jtag-1 I/F

+3.3V_NORMAL

P104

OPT

1

2

3

4

5

6

7

8

9

10

11

EB_ADDR[0-14]

TP102

EB_DATA[0-7]

TP103

PAGE 1

TP104
TP105

TP106
TP107

TP108
TP109

TP110
TP111
TP112
TP113
TP114
TP115
TP116
TP117

EB_WE_N
EB_OE_N

EB_BE_N1
EB_BE_N0

CAM_CD1_N
CAM_CD2_N

/PCM_CE1
/PCM_CE2
CAM_IREQ_N
PCM_RESET
CAM_INPACK_N
PCM_5V_CTL
CAM_WAIT_N
CAM_REG_N

EB_ADDR[0-14]

EB_DATA[0-7]

TRST_N1

IRB_SPI_MISO/TDI1

IRB_SPI_MOSI/TDO1

IRB_SPI_SS/TMS1

IRB_SPI_CK/TCK1

SOC_RESET

M14_OLED_VBY1

LG1311V-B1

IC101-*1

B23

XIN_MAIN

A23

XO_MAIN

AG21

PORES_N

AJ18

BOOT_MODE

AB8

PLLSET0

AC8

PLLSET1

AD8

OPM0

AE8

OPM1

Y7

L_VSOUT_LD/TRST0_N

Y6

DIM0_SCLK/TMS0

W7

DIM1_SCLK/TCK0

W6

DIM1_MOSI/TDI0

W5

DIM0_MOSI/TDO0

AG30

SPI_CS0

AG28

SPI_SCLK0

AG29

SPI_DO0

AH29

SPI_DI0/TRST1_N

AJ27

SPI_CS1/TMS1

AH27

SPI_SCLK1/TCK1

AG26

SPI_DO1/TDO1

AH26

SPI_DI1/TDI1

AJ12

EXT_INTR0

AJ13

EXT_INTR1

AH12

EXT_INTR2

AG12

EXT_INTR3

AH23

UART0_RXD

AG22

UART0_TXD

AH7

UART1_RXD

AJ7

UART1_TXD

AG8

UART1_RTS_N

AH8

UART1_CTS_N

AH11

SCL0

AG11

SDA0

AH9

SCL1

AG9

SDA1

AG10

SCL2

AJ9

SDA2

AH22

SCL3

AJ22

SDA3

AH10

SCL4

AJ10

SDA4

AG23

SCL5

AH24

SDA5

AC6

PWM0

AC7

PWM1

AD7

PWM2

AB7

PWM_IN

G32

EMMC_CLK

G33

EMMC_CMD

G31

EMMC_RESETN

D31

EMMC_DATA7

F33

EMMC_DATA6

F32

EMMC_DATA5

E32

EMMC_DATA4

F31

EMMC_DATA3

D33

EMMC_DATA2

D32

EMMC_DATA1

E31

EMMC_DATA0

USB2_0_DP0
USB2_0_DM0

USB2_0_TXRTUNE

USB2_1_DP0
USB2_1_DM0

USB2_1_TXRTUNE

USB3_DP0

USB3_DM0
USB3_TXP0
USB3_TXM0
USB3_RXP0
USB3_RXM0

USB3_RESREF0

USB3_DP1

USB3_DM1
USB3_TXP1
USB3_TXM1
USB3_RXP1
USB3_RXM1

USB3_RESREF1

HUB_PORT_OVER0
HUB_VBUS_CTRL0

EB_WE_N
EB_OE_N

EB_WAIT
EB_BE_N1
EB_BE_N0

CAM_CD1_N
CAM_CD2_N
CAM_CE1_N
CAM_CE2_N

CAM_IREQ_N

CAM_RESET

CAM_INPACK_N

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

EB_ADDR0
EB_ADDR1
EB_ADDR2
EB_ADDR3
EB_ADDR4
EB_ADDR5
EB_ADDR6
EB_ADDR7
EB_ADDR8
EB_ADDR9

EB_ADDR10
EB_ADDR11
EB_ADDR12
EB_ADDR13
EB_ADDR14
EB_ADDR15

EB_DATA0
EB_DATA1
EB_DATA2
EB_DATA3
EB_DATA4
EB_DATA5
EB_DATA6
EB_DATA7

AN9
AM9
AN8

H32
J31
H33

N31
N32
P33
P32
M32
M33
P31

K33
K32
L32
L31
K31
J32
M31

W28
W29

H28

EB_CS3

J30

EB_CS2

J28

EB_CS1

J29

EB_CS0

G30
F30
H29
G29
G28

P28
P27
U28
R29
V27
T28
T29
R28
U27
N29

K30
E30
M30
N28
M28
M29
L29
K29
K28
L28
D30
F29
C32
C33
C31
B33

B32
A32
B31
A31
A30
B30
C30
C29

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M14-Peripheral

MID_LG1311

M14 Symbol A

2013.04.04
1

31

PAGE 2

Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

FE_DEMOD1_TS_DATA[0-7]

TPI_ERR

AMP_RESET_N

TP226
TP227

FE_DEMOD3_TS_SYNC

FE_DEMOD3_TS_DATA

TPI_DATA[0-7]

Near AMP

C200

1000pF

50V

R231

4.7K

TP228

FE_DEMOD1_TS_CLK

FE_DEMOD1_TS_SYNC

FE_DEMOD1_TS_VAL

FE_DEMOD1_TS_ERROR

FE_DEMOD3_TS_CLK
FE_DEMOD3_TS_VAL

SC_DET

R226

100

1/16W

5%

LED_SDA

INSTANT_BOOT

LED_SCL

CAM_SLIDE_DET

CAM_TRIGGER_DET

/RST_HUB

IC101

LG1311

AH30

TP_DVB_CLK

AH32

TP_DVB_SOP

AH31

TP_DVB_VAL

AH33

TP_DVB_ERR

FE_DEMOD1_TS_DATA[7]
FE_DEMOD1_TS_DATA[6]
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[3]
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[0]

FE_DEMOD2_TS_CLK

FE_DEMOD2_TS_SYNC

FE_DEMOD2_TS_VAL

FE_DEMOD2_TS_ERROR

FE_DEMOD2_TS_DATA

TPI_CLK
TPI_SOP
TPI_VAL

SC_DET

/RST_PHY

2D/3D_CTL

BT_RESET

HP_DET

OPT

OPC_EN

DEBUG

BIT0

/RST_HUB

COMP1_DET

BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7

TPI_ERR

TPI_DATA[0]
TPI_DATA[1]
TPI_DATA[2]
TPI_DATA[3]
TPI_DATA[4]
TPI_DATA[5]
TPI_DATA[6]
TPI_DATA[7]

MODEL_OPT_11

TP225

RF_SWITCH_CTL

/TU_RESET1
/TU_RESET2

R224

33

CAM_SLIDE_DET

CAM_TRIGGER_DET

MODEL_OPT_12

AV1_CVBS_DET

IR_B_RESET

MODEL_OPT_8
MODEL_OPT_9

MODEL_OPT_10 EPI_LOCK8/6

AM33

TP_DVB_DATA7

AL32

TP_DVB_DATA6

AL33

TP_DVB_DATA5

AK32

TP_DVB_DATA4

AK33

TP_DVB_DATA3

AK31

TP_DVB_DATA2

AJ30

TP_DVB_DATA1

AJ31

TP_DVB_DATA0

AL31

STPI0_CLK

AN32

STPI0_SOP

AM32

STPI0_VAL

AN31

STPI0_ERR

AM31

STPI0_DATA

AH28

STPI1_CLK

AJ28

STPI1_SOP

AK30

STPI1_VAL

AJ29

STPI1_ERR

AG27

STPI1_DATA

A28

TPI_CLK

B28

TPI_SOP

B29

TPI_VAL

C28

TPI_ERR

A27

TPI_DATA0

B27

TPI_DATA1

C27

TPI_DATA2

B26

TPI_DATA3

C26

TPI_DATA4

B25

TPI_DATA5

A25

TPI_DATA6

C25

TPI_DATA7

AG13

GPIO31

AJ19

GPIO30

AG14

GPIO29

AG15

GPIO28

AJ15

GPIO27

AH19

GPIO26

AH18

GPIO25

AG19

GPIO24

AH5

GPIO23

AJ5

GPIO22

AJ6

GPIO21

AH6

GPIO20

AG6

AG24
AH16

AJ21
AH21

AG16
AJ24
AH17
AG17
AH13
AH15
AG18
AH14
AJ16
AH20

GPIO19

AG5

GPIO18

AF7

GPIO17

AG7

GPIO16
GPIO15
GPIO14

V29

GPIO13
GPIO12
GPIO11

V28

GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0

R225

OPT

33

TPIO_CLK
TPIO_SOP
TPIO_VAL

TPIO_ERR
TPIO_DATA0
TPIO_DATA1
TPIO_DATA2
TPIO_DATA3
TPIO_DATA4
TPIO_DATA5
TPIO_DATA6
TPIO_DATA7

EPI_SOE
EPI_MCLK
EPI_GCLK

EPI_EO

EPI_VST

TX_0N
TX_0P
TX_1N
TX_1P
TX_2N
TX_2P
TX_3N
TX_3P
TX_4N
TX_4P
TX_5N
TX_5P
TX_6N
TX_6P
TX_7N
TX_7P
TX_8N
TX_8P
TX_9N

TX_9P
TX_10N
TX_10P
TX_11N
TX_11P
TX_12N
TX_12P
TX_13N
TX_13P
TX_14N
TX_14P
TX_15N
TX_15P
TX_16N
TX_16P
TX_17N
TX_17P
TX_18N
TX_18P
TX_19N
TX_19P
TX_20N
TX_20P
TX_21N
TX_21P
TX_22N
TX_22P
TX_23N
TX_23P

TX_LOCKN

D28
E29
E28
F28
D27
E27
F27
E26
F26
E25
D25
F25

AA5
AB5
AA7
AA6
AB6

AK8
AL8
AK7
AL7
AM6
AN6
AK6
AL6
AK5
AL5
AN4
AN3
AM2
AM1
AM4
AM3
AL4
AL3
AK2
AK1
AK4
AK3
AJ4
AJ3
AH2
AH1
AH4
AH3
AG4
AG3
AF2
AF1
AF4
AF3
AE4
AE3
AD2
AD1
AD4
AD3
AC4
AC3
AB2
AB1
AB4
AB3
AA4
AA3

AM8

TPO_CLK
TPO_SOP
TPO_VAL
TPO_ERR

TPO_DATA[0]
TPO_DATA[1]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[6]
TPO_DATA[7]

EPI_SOE
MCLK_SOC
GCLK_SOC
EO_SOC
GST_SOC

TXB4N/TX0N
TXB4P/TX0P
TXB3N/TX1NFE_DEMOD3_TS_ERROR
TXB3P/TX1P
TXBCLKN/TX2N
TXBCLKP/TX2P
TXB2N/TX3N
TXB2P/TX3P
TXB1N/TX4N
TXB1P/TX4P
TXB0N/TX5N
TXB0P/TX5P

TXD4N/TX12N
TXD4P/TX12P
TXD3N/TX13N
TXD3P/TX13P
TXDCLKN/TX14N
TXDCLKP/TX14P
TXD2N/TX15N
TXD2P/TX15P
TXD1N/TX16N
TXD1P/TX16P
TXD0N/TX17N
TXD0P/TX17P

TPO_DATA[0-7]

TXA4N/TX6N
TXA4P/TX6P
TXA3N/TX7N
TXA3P/TX7P
TXACLKN/TX8N
TXACLKP/TX8P
TXA2N/TX9N
TXA2P/TX9P
TXA1N/TX10N
TXA1P/TX10P
TXA0N/TX11N
TXA0P/TX11P

TXC4N/TX18N
TXC4P/TX18P
TXC3N/TX19N
TXC3P/TX19P
TXCCLKN/TX20N
TXCCLKP/TX20P
TXC2N/TX21N
TXC2P/TX21P
TXC1N/TX22N
TXC1P/TX22P
TXC0N/TX23N
TXC0P/TX23P

TPO_ERR

EPI_SOE

+3.3V_NORMAL

BIT0_1

R201 10K

BIT0_0

R202 10K

BIT [0/1]

0 / 0
0 / 1
1 / 0
1 / 1

TAIWAN/COLOM

CHINA/HONGKONG

ASIA/AFRICA

EU/CIS

BIT1_1

R203 10K

BIT1_0

R204 10K

ATSC

N/AMERICA

KOREA

S/AMERCIA

Model Option

BIT3_1

BIT2_1

R205 10K

R207 10K

BIT0
BIT1

BIT3_0

BIT2_0

R206 10K

R208 10K

JP

JAPAN

BIT4_1

R209 10K

BIT4_0

R210 10K

BIT5_1

R211 10K

BIT5_0

R212 10K

BIT2
BIT3
BIT4
BIT5

BACK-END OPTIONAREA OPTION

BIT[2/3/4/5]DVB
0 / 0 / 0 / 0
0 / 0 / 0 / 1
0 / 0 / 1 / 0
0 / 0 / 1 / 1
0 / 1 / 0 / 0
0 / 1 / 0 / 1
0 / 1 / 1 / 0
0 / 1 / 1 / 1
1 / 0 / 0 / 0
1 / 0 / 0 / 1
1 / 0 / 1 / 0
1 / 0 / 1 / 1
1 / 1 / 0 / 0
1 / 1 / 0 / 1
1 / 1 / 1 / 0
1 / 1 / 1 / 1

BIT6_1

R213 10K

BIT [6/7]

BIT7_1

R215 10K

0 / 0
0 / 1
1 / 0
1 / 1

EU/CIS

T/C

T2/C/S2/ATV_EXT

T2/C

T2/C/S2/ATV_SOC

BIT6
BIT7

BIT6_0

BIT7_0

R214 10K

R216 10K

TYPE

EPI FHD, 120Hz, V14 (8 lane)
EPI FHD, 120Hz, v14_32inch (6 lane)
EPI FHD, 120Hz, V13 (6 lane)
EPI FHD, 120Hz, V12 (6 lane)

EPI FHD, 60Hz, V14_32 inch (6lane)

LVDS FHD, 120Hz
LVDS FHD, 60Hz

LVDS HD, 60Hz

LVDS FHD, 60Hz, CP BOX
LVDS HD, 60Hz SMALL SMART

Vby1 FHD, 120Hz
LVDS FHD, 120Hz OLED

FRC

FHD

PANEL TYPE

OLED

AJJA

T/C
T2/C/ATV_EXT
T2/C/ATV_SOC

T2/C/S2

DDR3_DDP

R219 10K

R217 10K

DDR3_1.5GB

DDR3_2GB

R220 10K

R218 10K

DDR3_NON_DDP

TAIWAN/COL

T/C

T2/C PIP

T2/C

DDR_3G

R221 10K

R222 10K

NON_DDR_3G

MODEL_OPT_8

MODEL_OPT_9

MODEL_OPT_10

MODEL_OPT_11

MODEL_OPT_12

BRAZILKOREA

ISDB PIP

ISDB

ATV_SOC
ATV_EXT

OPT

R227 10K

NORTH AMERICA

ATSC PIP

ATV_SOC
ATV_EXT

OPT

R229 10K

CHINA/HONG

Default Default

ATSC PIP

MODEL_OPT_8
MODEL_OPT_9
MODEL_OPT_10

OPT

OPT

R230 10K

R228 10K

LOW

DDR3

NON_DDP

DDR3

FOR UD

NON_DDR3 3G

NOT GPIO! OLED ECO POWER CTL

HIGH

DDP

1.5GB

2GB

DDR3 3G

JAPAN

MODEL_OPT_11

MODEL_OPT_12

FE_DEMOD2_TS_CLK

FE_DEMOD2_TS_SYNC

FE_DEMOD2_TS_VAL

FE_DEMOD2_TS_ERROR

FE_DEMOD2_TS_DATA

FE_DEMOD3_TS_CLK

FE_DEMOD3_TS_SYNC

FE_DEMOD3_TS_VAL

FE_DEMOD3_TS_ERROR

FE_DEMOD3_TS_DATA

TPI_DATA[0-7]

TPO_DATA[0-7]

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR

M14-Display In/Out

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TPI_CLK
TPI_SOP
TPI_VAL

TPO_CLK
TPO_SOP
TPO_VAL

TP202
TP203
TP204
TP205
TP206

TP207
TP208
TP209
TP210
TP211

TP212

TP213
TP214
TP215

TP221

TP218
TP219
TP220

DEBUG

+3.3V_NORMAL

SW201

JTP-1127WEM

12

3

4

For ISP

R223

3.3K

MID_LG1311

M14 Symbol B

2013.04.04
2

31

PLACE AT JACK SIDE

Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

Place JACK Side

AV1_CVBS/COMP1_Y Circuit was moved to 34Page

COMP1_Pb

COMP1_Pr

TU_CVBS

COMP1/AV1/DVI_L_IN

COMP1/AV1/DVI_R_IN

C303
150pF
50V

OPT

1005

75

1%

R318

1005

1%

75

R326

Place SOC Side

33

R333

R335 33

TU_ALL_2178B

R329 100

AUDIO IN

R309 27K

R310 27K

C316 4.7uF

1%

C317 4.7uF

1%

R323 10K

C322 0.047uF

C324 0.047uF

TU_ALL_2178B

C318 0.047uF

R322 10K

1%

1%

COMP2_PB_IN_SOC

COMP2_PR_IN_SOC

TU_CVBS_SOC

AUAD_L_CH3_IN

AUAD_R_CH3_IN

COMP

TP308
TP310

TP311

TP312
TP313
TP314
TP315

TP316
TP317

TP302
TP303
TP304
TP305
TP306
TP307

SC_CVBS_IN_SOC
SC_FB_SOC

SC_ID_SOC
COMP1_PB_IN_SOC

COMP1_Y_IN_SOC
COMP1_Y_IN_SOC_SOY
COMP1_PR_IN_SOC

AUAD_L_CH2_IN
AUAD_R_CH2_IN

SMARTCARD_DATA/SD_EMMC_CLK
SMARTCARD_VCC/SD_EMMC_CMD
SMARTCARD_DET/SD_EMMC_DATA[3]
SMARTCARD_RST/SD_EMMC_DATA[2]
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
SMARTCARD_CLK/SD_EMMC_DATA[0]

TP318
TP319

TP320

Placed as close as possible to LG1311

Tuner IF Filter

C331
22pF

TU_ALL_IntDemod

C332

0.01uF

C333

0.01uF
TU_ALL_IntDemod

TU_ALL_IntDemod

ADC_I_INN

To ADC

ADC_I_INP

C331 option

- TU_IntDemod_IF_22p -> EU/AJ All_IndDemod, US/KR/BR/TW/CO 2tuner All

- TU_IntDemod_IF_15p -> US/KR/BR/TW/CO 1tuner All

R344

R345

TU_ALL_IntDemod

51

TU_IntDemod_IF_22p

51

Placed as close as possible to IC101

R37 4

51K

AUAD_L_REF

1%

R37 8

47K
1%

C313

4.7uF
10V

R38 0

51K

1%

AUAD_R_REF

R38 1

47K
1%

DDR3 VENDOR OPTION

+3.3V_NORMAL

SCART_LOUT_SOC

SCART_ROUT_SOC

DTV/MNT_V_OUT_SOC

TU_IntDemod_IF_15p

C331-*1
15pF
50V

IF_N

L303

OPT

IF_P

AVDD25

L307

120-ohm

C354
10uF

10V

C353

4.7uF
10V

SOC_CVBS_OUT

SCART_LOUT_SOC
SCART_ROUT_SOC

TUNER_SIF

IF_AGC

AUD_MASTER_CLK

AUD_LRCH

AUD_SCK

AUD_LRCK

MAIN I2S_I/F

OPT

INT_ADEMOD

R11022
390

INT_ADEMOD

DTV/MNT_V_OUT_SOC

AVDD25

EU

C334

0.01uF
50V

C335
22pF
OPT

TU_ALL_2178B

C312 0.1uF

C309
1000pF
50V

C338

0.1uF
OPT

Close to IC101

INT_ADEMOD

R11023
390

INT_ADEMOD

C11009
68pF
50V

OPT

EU
C336

0.01uF

EU

50V

R351 22K

SPDIF_OUT

C337
33pF

OPT

TU_ALL_IntDemod

R350

470

SOC_CVBS_OUT

C11010
68pF
50V

R356

R353 0

C339
100pF
50V

COMP1_Y_IN_SOC_SOY

COMP2_Y_IN_SOC_SOY

R357 68
R358 68
R359 68

BLM15BD121SN1

R354 0
R355 0

EU

AUAD_L_CH2_IN
AUAD_R_CH2_IN

R352 22K

AUAD_L_CH3_IN
AUAD_R_CH3_IN

C340
22pF
OPT

I2S_AMP

ADC_I_INP
ADC_I_INN

C11011

TU_CVBS_SOC

SC_CVBS_IN_SOC

AV1_CVBS_IN_SOC

C343 0.047uF

68

EU

SC_ID_SOC
SC_FB_SOC

COMP1_Y_IN_SOC
COMP1_PB_IN_SOC
COMP1_PR_IN_SOC

COMP2_Y_IN_SOC
COMP2_PB_IN_SOC
COMP2_PR_IN_SOC

L304

BLM15BD121SN1

EU
EU

AUDA_OUTL
AUDA_OUTR

AUAD_R_REF
AUAD_L_REF

R360 33

R365 100

R366 100
C342
22pF
OPT

R368 100
R369

GOOGLE

R367 0

INT_ADEMOD

0.1uF

16V

0.047uF

C344
C345 0.047uF
C346 0.047uF

C349

0.1uF

L305

16V

10uF 10VC347

C348 2.2uF

10V

100

GOOGLE

R371 0

C351 0.1uF

C352 0.1uF

GOOGLE

R370 0

AL27
AK26
AM27

AL26

AN27

AL25
AM25

AN23
AL22
AK21
AK22

AL24
AK23
AL23
AK24

AL21
AM23
AN25

AM21
AN21

AK16
AL16

AL19
AK19
AN19
AM19
AN17
AM17
AL17
AK17

AK20
AL20

AK18
AL18

AN15

AM15

AN11
AK11
AK10
AL10
AL11
AM11

AK29
AL29
AM29

AK27
AL30

AK28
AL28
AN29

AD5
AE5
AE7
AE6

AD6

IC101

LG1311

CVBS_IN1
CVBS_IN2
CVBS_IN3

CVBS_VCM

BUF_OUT1

SC1_SID
SC1_FB

SOY1_IN
Y1_IN
PB1_IN
PR1_IN

SOY2_IN
Y2_IN
PB2_IN
PR2_IN

ADC1_COM
ADC2_COM
ADC3_COM

AVSS25_COMP_REF
AVDD25_COMP_REF

AUDA_SCART_OUTL
AUDA_SCART_OUTR

AUAD_L_CH1_IN
AUAD_R_CH1_IN
AUAD_L_CH2_IN
AUAD_R_CH2_IN
AUAD_L_CH3_IN
AUAD_R_CH3_IN
AUAD_L_CH4_IN
AUAD_R_CH4_IN

AUDA_OUTL
AUDA_OUTR

AUAD_L_REF
AUAD_R_REF

AUD_VBG_EXT

IEC958OUT

AUDCLK_OUT
DAC_LRCH
DAC_SLRCH
DAC_CLFCH
DAC_SCK
DAC_LRCK

PCMI3LRCH
PCMI3LRCK
PCMI3SCK
AUDCLK_IN

FRC_LRSYNC

AAD_ADC_SIF
AAD_ADC_SIFM
IFAGC

DMD_DAC_OUT
DMD_SIF_OUT

DMD_ADC_INP
DMD_ADC_INN
DMD_ADC_INCOM

SD_CLK

SD_CMD
SD_CD_N
SD_WP_N

SD_DATA3
SD_DATA2
SD_DATA1
SD_DATA0

RMII_REF_CLK

RMII_CRS_DV

RMII_MDIO

RMII_MDC
RMII_TXEN
RMII_TXD1
RMII_TXD0
RMII_RXD1
RMII_RXD0

HDMI_1_SCL
HDMI_1_SDA
HDMI_1_HPD

HDMI_1_5V_DET

HDMI_1_ARC

HDMI_1_RX_0

HDMI_1_RX_0B

HDMI_1_RX_1

HDMI_1_RX_1B

HDMI_1_RX_2

HDMI_1_RX_2B

HDMI_1_RX_C

HDMI_1_RX_CB

HDMI_2_SCL
HDMI_2_SDA
HDMI_2_HPD

HDMI_2_5V_DET

HDMI_2_RX_0

HDMI_2_RX_0B

HDMI_2_RX_1

HDMI_2_RX_1B

HDMI_2_RX_2

HDMI_2_RX_2B

HDMI_2_RX_C

HDMI_2_RX_CB

HDMI_3_SCL
HDMI_3_SDA
HDMI_3_HPD

HDMI_3_5V_DET

HDMI_3_RX_0

HDMI_3_RX_0B

HDMI_3_RX_1

HDMI_3_RX_1B

HDMI_3_RX_2

HDMI_3_RX_2B

HDMI_3_RX_C

HDMI_3_RX_CB

HDMI_4_SCL

HDMI_4_SDA
HDMI_4_CBUS_HPD
HDMI_4_CD_SENSE

HDMI_4_5V_DET

HDMI_4_RX_0

HDMI_4_RX_0B

HDMI_4_RX_1

HDMI_4_RX_1B

HDMI_4_RX_2

HDMI_4_RX_2B

HDMI_4_RX_C

HDMI_4_RX_CB

E22
D22
F22
F24
D24
E24
F23
E23

AK14
AK12
AL12
AK13
AL13
AM13
AN13
AL14
AK15

AE27
AF28
AE29
AF27
AE28

AF33
AF32
AE31
AE30
AD31
AD30
AF31
AF30

AD28
AD29
AC27
AD27

AC31
AC30
AB33
AB32
AA31
AA30
AD32
AD33

AB28
AB27
AB29
AC28

Y32
Y33
W31
W30
V33
V32
Y31
Y30

Y27
AA28
Y28
AA29
AA27

T31
T30
T32
T33
R31
R30
U31
U30

PAGE 3

SMARTCARD_CLK/SD_EMMC_DATA[0]
SMARTCARD_RST/SD_EMMC_DATA[2]
SMARTCARD_VCC/SD_EMMC_CMD
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
DDR3_OPT1
DDR3_OPT2
SMARTCARD_DET/SD_EMMC_DATA[3]
SMARTCARD_DATA/SD_EMMC_CLK

EPHY_REFCLK
EPHY_CRS_DV
EPHY_MDIO
EPHY_MDC
EPHY_EN
EPHY_TXD1
EPHY_TXD0

R520733

EPHY_RXD1

R520633

EPHY_RXD0

DDC_SCL_1
DDC_SDA_1
HDMI_HPD_1

SPDIF_OUT_ARC

D0+_HDMI1
D0-_HDMI1

D1+_HDMI1
D1-_HDMI1
D2+_HDMI1
D2-_HDMI1
CK+_HDMI1
CK-_HDMI1

DDC_SCL_2

DDC_SDA_2

HDMI_HPD_2

D0+_HDMI2
D0-_HDMI2
D1+_HDMI2
D1-_HDMI2
D2+_HDMI2
D2-_HDMI2
CK+_HDMI2
CK-_HDMI2

DDC_SCL_3

DDC_SDA_3

HDMI_HPD_3

5V_HDMI_3_SOC

D0+_HDMI3
D0-_HDMI3
D1+_HDMI3
D1-_HDMI3
D2+_HDMI3
D2-_HDMI3
CK+_HDMI3
CK-_HDMI3

DDC_SCL_4

DDC_SDA_4

HDMI_HPD_4

MHL_DET

D0+_HDMI4
D0-_HDMI4
D1+_HDMI4
D1-_HDMI4
D2+_HDMI4
D2-_HDMI4
CK+_HDMI4
CK-_HDMI4

5V_HDMI_1

R372
10

C356
1uF
10V

5V_HDMI_2

R373
10

C357
1uF

10V

5V_HDMI_4

R375
10

C359
1uF
10V

R376

5.1K

R377

5.1K

R379

5.1K

HP_OUT
L308

BLM18PG121SN1D

HP_LOUT_AMP

BLM18PG121SN1D

HP_ROUT_AMP

HP_OUT
L309

HP_OUT
C365

0.22uF
10V

HP_OUT
C366

0.22uF
10V

HP_LOUT

HP_ROUT

Place at JACK SIDE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M14-AV In/Out

HP_LOUT_MAIN

HP_ROUT_MAIN

4.7K

4.7K

R384

R382

OPT

OPT

R383 4.7K

R385 4.7K

AUDIO OUT

R303

22K

R304

22K

R311 0

C305

0.01uF
50V

R312 0

C306

0.01uF
50V

DDR3_OPT1
DDR3_OPT2

AUDA_OUTL

AUDA_OUTR

DDC_SCL_3
DDC_SDA_3

HDMI_HPD_3

5V_HDMI_3_SOC

D0+_HDMI3
D0-_HDMI3
D1+_HDMI3
D1-_HDMI3
D2+_HDMI3
D2-_HDMI3
CK+_HDMI3
CK-_HDMI3

MID_LG1311

M14 Symbol C

TP321
TP322
TP323
TP324

TP325
TP326
TP327
TP328
TP329
TP330
TP331
TP332

2013.04.04
3

31

PAGE 4

Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

IC101

LG1311

M0_DDR_U_CLKP
M0_DDR_U_CLKN
M0_DDR_D_CLKP
M0_DDR_D_CLKN

M0_DDR_RESET_N

M0_DDR_DQS_P0
M0_DDR_DQS_N0
M0_DDR_DQS_P1
M0_DDR_DQS_N1
M0_DDR_DQS_P2
M0_DDR_DQS_N2
M0_DDR_DQS_P3
M0_DDR_DQS_N3

M0_DDR_VREF1
M0_DDR_VREF2

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_DM0
M0_DDR_DM1
M0_DDR_DM2
M0_DDR_DM3

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ8
M0_DDR_DQ9

M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15
M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23
M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

M0_DDR_ZQCAL

VREF_M0_0

A22
A3

E13
E11
E15
E17
D8
D16
D9
E16
E9
E14
D7
D10
D11
D14
E10
E12

D17
E8
D13

C8
B8
C17
B17
D12

E19
D19
D18
E18

D15

B18
C18
B16
A16
B9
C9
B7
A7

A15
A18
A6
A9

B20
B13
C21
C14
A21
A13
B21
C13
B14
B19
C15
C20
C16
A19
B15
C19
B11
C5
C12
B4
A12
A4
B12
C4
B5
B10
C6
C11
C7
A10
B6
C10

E7

VREF_M0_1

R401 240

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8
M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1

M0_DDR_BA2

M0_U_CLK
M0_U_CLKN
M0_D_CLK

M0_DDR_CKE

M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS0
M0_DDR_DQS_N0
M0_DDR_DQS1
M0_DDR_DQS_N1
M0_DDR_DQS2
M0_DDR_DQS_N2
M0_DDR_DQS3
M0_DDR_DQS_N3

M0_DDR_DM0
M0_DDR_DM1
M0_DDR_DM2
M0_DDR_DM3

M0_DDR_DQ0
M0_DDR_DQ1

M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4

M0_DDR_DQ5

M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ8
M0_DDR_DQ9

M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14

M0_DDR_DQ15

M0_DDR_DQ16

M0_DDR_DQ17

M0_DDR_DQ18

M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21

M0_DDR_DQ22

M0_DDR_DQ23
M0_DDR_DQ24

M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27

M0_DDR_DQ28
M0_DDR_DQ29

M0_DDR_DQ30

M0_DDR_DQ31

1%

+1.5V_DDR

R402

R403

+1.5V_DDR

OPT

+1.5V_DDR

R406

R407

+1.5V_DDR

R408

R409

VREF_M0_0

1K 1%

1K 1%

C401

R404
10K

100

R40 5

M0_DDR_VREFCA

1K 1%

C402

0.1uF

1K 1%

M0_DDR_VREFDQ

1K 1%

0.1uF

1K 1%

C403

0.1uF

M0_DDR_RESET_N

M0_D_CLK

M0_D_CLKN

M0_DDR_CKE

+1.5V_DDR

+1.5V_DDR

R411

R412

+1.5V_DDR

R413

R414

VREF_M0_1

R415

1K 1%

R416

1K 1%

R417
10K

M0_U_CLK

100

R41 0

M0_U_CLKN

M0_1_DDR_VREFCA

1K 1%

C406

0.1uF

1K 1%

M0_1_DDR_VREFDQ

1K 1%

0.1uF

1K 1%

C407

C408

0.1uF

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8
M0_DDR_A9

M0_DDR_A10

M0_DDR_A11
M0_DDR_A12

M0_DDR_A13

M0_DDR_A14

M0_DDR_A15

M0_DDR_BA0

M0_DDR_BA1

M0_DDR_BA2

M0_D_CLK

M0_D_CLKN

M0_DDR_CKE

M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DM0
M0_DDR_DM1

M0_DDR_DQ0

M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7

M0_DDR_DQ8
M0_DDR_DQ9

M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

IC401

H5TQ4G63AFR-PBC

DDR3

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

4Gbit

A0

(x16)

A1

DDR_512MB_HYNIX_1600_29n

A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

ZQ

M0_DDR_VREFCA

M0_DDR_VREFDQ

M8

H1

R418

L8

240

1%

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5V_DDR

IC401-*1

MT41K256M16HA-125:E

DDR_512MB_MICRON

N3

A0

VREFCA

P7

A1

P3

A2

N2

A3

VREFDQ

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

VDD_1

A9

L7

VDD_2

A10/AP

R7

VDD_3

A11

N7

VDD_4

A12/BC

T3

A13

VDD_5
VDD_6

M7

NC_5

VDD_7
VDD_8

M2

BA0

VDD_9

N8

BA1

M3

BA2

VDDQ_1

J7

CK

VDDQ_2

K7

CK

VDDQ_3

K9

CKE

VDDQ_4
VDDQ_5

L2

CS

VDDQ_6

K1

ODT

VDDQ_7

J3

RAS

VDDQ_8

K3

CAS

VDDQ_9

L3

WE

NC_1

T2

RESET

NC_2
NC_3
NC_4

F3

DQSL

G3

DQSL

C7

DQSU

VSS_1

B7

DQSU

VSS_2
VSS_3

E7

DML

VSS_4

D3

DMU

VSS_5
VSS_6

E3

DQ0

VSS_7

F7

DQ1

VSS_8

F2

DQ2

VSS_9

F8

DQ3

VSS_10

H3

DQ4

VSS_11

H8

DQ5

VSS_12

G2

DQ6

H7

DQ7

VSSQ_1

D7

DQ8

VSSQ_2

C3

DQ9

VSSQ_3

C8

DQ10

VSSQ_4

C2

DQ11

VSSQ_5

A7

DQ12

VSSQ_6

A2

DQ13

VSSQ_7

B8

DQ14

VSSQ_8

A3

DQ15

VSSQ_9

C413 1uF
C414 1uF

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A14

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14

M0_DDR_A15

M0_DDR_BA0M0_D_CLKN
M0_DDR_BA1
M0_DDR_BA2

M0_U_CLK

M0_U_CLKN
M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_DM2
M0_DDR_DM3

M0_DDR_DQ16

M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23

M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

MT41K256M16HA-125:E

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

IC402-*1

DDR_512MB_MICRON

IC402

H5TQ4G63AFR-PBC

DDR3

N3

4Gbit

A0

P7

(x16)

A1

P3

DDR_512MB_HYNIX_1600_29n

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

A14

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

M0_1_DDR_VREFCA

VREFCA

VREFDQ

ZQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M8

H1

L8

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M0_1_DDR_VREFDQ

+1.5V_DDR

R419

240

1%

C429
C430

1uF
1uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MID_LG1311

M14 DDR3-M0

2013.04.04
4

31

PAGE 5

Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

IC101

LG1311

M1_DDR_U_CLKP
M1_DDR_U_CLKN
M1_DDR_D_CLKP
M1_DDR_D_CLKN

M1_DDR_RESET_N

M1_DDR_DQS_P0
M1_DDR_DQS_N0
M1_DDR_DQS_P1
M1_DDR_DQS_N1
M1_DDR_DQS_P2
M1_DDR_DQS_N2
M1_DDR_DQS_P3
M1_DDR_DQS_N3

M1_DDR_VREF1
M1_DDR_VREF2

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DM0
M1_DDR_DM1
M1_DDR_DM2
M1_DDR_DM3

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9

M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15
M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23
M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31

M1_DDR_ZQCAL

VREF_M1_0

A2
Y1

M5
N5
K5
H5
T4
H4
R4
J5
T5
L5
U4
P4
P5
K4
R5
N4

G4
U5
L4

R3
R2
F3
F2
M4

F5
E4
F4
G5

J4

E2
E3
G2
G1
P2
P3
T2
T1

H1
E1
U1
P1

C2
K2
B3
J3
B1
K1
B2
K3
J2
D2
H3
C3
G3
D1
H2
D3
M2
V3
L3
W2
L1
W1
L2
W3
V2
N2
U3
M3
T3
N1
U2
N3

E5

R501

VREF_M1_1

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8
M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_U_CLK
M1_U_CLKN
M1_D_CLK
M1_D_CLKN
M1_DDR_CKE

M1_DDR_ODT
M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQS_N0
M1_DDR_DQS1

M1_DDR_DQS_N1

M1_DDR_DQS2

M1_DDR_DQS_N2

M1_DDR_DQS3
M1_DDR_DQS_N3

M1_DDR_DM0

M1_DDR_DM2

M1_DDR_DM3

M1_DDR_DQ0
M1_DDR_DQ1

M1_DDR_DQ2

M1_DDR_DQ3

M1_DDR_DQ4

M1_DDR_DQ5

M1_DDR_DQ6

M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11

M1_DDR_DQ12
M1_DDR_DQ13

M1_DDR_DQ14

M1_DDR_DQ15

M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18

M1_DDR_DQ19

M1_DDR_DQ20
M1_DDR_DQ21

M1_DDR_DQ22

M1_DDR_DQ23

M1_DDR_DQ24

M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27

M1_DDR_DQ28
M1_DDR_DQ29

M1_DDR_DQ30

M1_DDR_DQ31

240
1%

+1.5V_DDR

R508

R509

+1.5V_DDR

OPT

+1.5V_DDR

R504

R505

+1.5V_DDR

R506

R507

VREF_M1_0

1K 1%

1K 1%

R502
10K

100

R50 3

M1_DDR_VREFCA

1K 1%

1K 1%

M1_DDR_VREFDQ

1K 1%

0.1uF

1K 1%

C503

C501

0.1uF

M1_DDR_RESET_N

M1_D_CLK

M1_D_CLKN

C502

0.1uF

+1.5V_DDR

M1_DDR_CKE

+1.5V_DDR

+1.5V_DDR

VREF_M1_1

R515

1K 1%

R516

1K 1%

100

R51 0

M1_1_DDR_VREFCA

R511

1K 1%

R512

1K 1%

M1_1_DDR_VREFDQ

R513

1K 1%

0.1uF

R514

1K 1%

C508

C506

M1_U_CLK

M1_U_CLKN

C507

0.1uF

0.1uF

R517
10K

M1_DDR_RASNM1_DDR_DQS0
M1_DDR_CASN

M1_DDR_RESET_N

M1_DDR_DQS0

M1_DDR_DQS_N0

M1_DDR_DQS1M1_DDR_DM1

M1_DDR_DQS_N1

M1_DDR_DM0
M1_DDR_DM1

M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_D_CLK

M1_D_CLKN
M1_DDR_CKE

M1_DDR_ODT

M1_DDR_WEN

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7

M1_DDR_DQ8
M1_DDR_DQ9

IC501

H5TQ4G63AFR-PBC

N3

DDR3

A0

P7

4Gbit

A1

P3

DDR_512MB_HYNIX_1600_29n

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

IC501-*1

MT41K256M16HA-125:E

DDR_512MB_MICRON

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

VREFCA

VREFDQ

ZQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

IC502-*3

MT41K128M16JT-125:K

DDR_256MB_MICRON

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

+1.5V_DDR

M8

H1

L8

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

M1_1_DDR_VREFCA

R519

+1.5V_DDR

C540

C541 1uF

M1_1_DDR_VREFDQ

240

1uF

DDR3 1.5V bypass Cap

: Place these caps near Memory

+1.5V_DDR

M1_DDR_VREFCA

R518

1uF

M1_DDR_VREFDQ

240

DDR3 1.5V bypass Cap

: Place these caps near Memory

H5TQ2G63FFR-PBC

DDR_256MB_HYNIX_1600_29n

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

IC501-*2

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

IC502-*1

MT41K256M16HA-125:E

DDR_512MB_MICRON

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4

A14

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

+1.5V_DDR

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C524

C525 1uF

VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

A14

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

1_2Gbit : T7(NC_6)

4Gbit : T7(A14)

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_U_CLK

M1_U_CLKN
M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQS2

M1_DDR_DQS_N2

M1_DDR_DQS3

M1_DDR_DQS_N3

M1_DDR_DM2
M1_DDR_DM3

M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20

M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23

M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26

M1_DDR_DQ27
M1_DDR_DQ28

M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31

IC502-*2

H5TQ2G63FFR-PBC

DDR_256MB_HYNIX_1600_29n

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

B2

R3

VDD_1

A9

D9

L7

VDD_2

A10/AP

G7

R7

VDD_3

A11

N7

K2

VDD_4

A12/BC

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

IC502

H5TQ4G63AFR-PBC

N3

DDR3

A0

P7

4Gbit

A1

P3

DDR_512MB_HYNIX_1600_29n

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

IC501-*3

MT41K128M16JT-125:K

DDR_256MB_MICRON

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

B2

R3

VDD_1

A9

D9

L7

VDD_2

A10/AP

G7

R7

VDD_3

A11

N7

K2

VDD_4

A12/BC

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQ0

VSS_7

F7

M9

DQ1

VSS_8

F2

P1

DQ2

VSS_9

F8

P9

DQ3

VSS_10

H3

T1

DQ4

VSS_11

H8

T9

DQ5

VSS_12

G2

DQ6

H7

DQ7

B1

VSSQ_1

D7

B9

DQ8

VSSQ_2

C3

D1

DQ9

VSSQ_3

C8

D8

DQ10

VSSQ_4

C2

E2

DQ11

VSSQ_5

A7

E8

DQ12

VSSQ_6

A2

F9

DQ13

VSSQ_7

B8

G1

DQ14

VSSQ_8

A3

G9

DQ15

VSSQ_9

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MID_LG1311

M14 DDR3-M1

2013.04.04
5

31

PAGE 6

Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

VDD3V3_HDMI

AVDD33

C637

0.1uF
16V

+1.5V_DDR

+1.5V_DDR

AVDD25_C4TX

AVDD25

AVDD25_AUD

GND JIG POINT

DVDD33

TP5207

TP5208

JP601

AA23
AC12
AC13
AC14
AC15
AC11

AF22

AA11
AC18
AC19
AC20
AC21
AC22
AC23

AC17
AB23

L18
L21
L22
L23
M23
T11
Y23

P23
R23
T23
U23
V23

F10
F11
F12
F13
F14
F15
F16
F17

V11
W11
Y11

G19
H19
H20

JP602

F9

G6
H6
J6
K6
L6
M6
N6
P6
R6

IC101

LG1311

DVDD33_1
DVDD33_2
DVDD33_3
DVDD33_4
DVDD33_5
DVDD33_6
DVDD33_7
DVDD33_8
DVDD33_9
DVDD33_10
DVDD33_11
DVDD33_12
AVDD33_BT_USB
AVDD33_USB_1
AVDD33_USB_2
AVDD33_HDMI_1
AVDD33_HDMI_2
AVDD33_HDMI_3

AVDD33_CVBS

DVDD15_M0_1
DVDD15_M0_2
DVDD15_M0_3
DVDD15_M0_4
DVDD15_M0_5
DVDD15_M0_6
DVDD15_M0_7
DVDD15_M0_8
DVDD15_M0_9

DVDD15_M1_1
DVDD15_M1_2
DVDD15_M1_3
DVDD15_M1_4
DVDD15_M1_5
DVDD15_M1_6
DVDD15_M1_7
DVDD15_M1_8
DVDD15_M1_9

AVDD25_C4TX_1
AVDD25_C4TX_2
AVDD25_C4TX_3
AVDD25_C4TX_4
AVDD25_COMP_1
AVDD25_COMP_2
AVDD25_CVBS_1
AVDD25_CVBS_2
AVDD25_DMD
AVDD25_AAD
DVDD25_XTAL
AVDD25_DR3PLL
SP_VQPS

AVDD25_AUD
AVDD25_APLL

JP604

JP603

DVDD11_1
DVDD11_2
DVDD11_3
DVDD11_4
DVDD11_5
DVDD11_6
DVDD11_7
DVDD11_8

DVDD11_9
DVDD11_10
DVDD11_11
DVDD11_12
DVDD11_13
DVDD11_14
DVDD11_15
DVDD11_16
DVDD11_17
DVDD11_18
DVDD11_19
DVDD11_20
DVDD11_21
DVDD11_22
DVDD11_23
DVDD11_24
DVDD11_25
DVDD11_26
DVDD11_27
DVDD11_28
DVDD11_29
DVDD11_30
DVDD11_31
DVDD11_32
DVDD11_33
DVDD11_34
DVDD11_35
DVDD11_36
DVDD11_37
DVDD11_38
DVDD11_39

DVDD11_40
DVDD11_41
DVDD11_42
DVDD11_43
DVDD11_44
DVDD11_45
DVDD11_46
DVDD11_47
DVDD11_48
DVDD11_49
DVDD11_50
DVDD11_51

AVDD11_APLL

AVDD11_COMP_LLPLL

AVDD11_C4TX_1
AVDD11_C4TX_2
AVDD11_C4TX_3
AVDD11_C4TX_4

DVDD11_XTAL

DVDD11_DR3PLL

DVDD11_CVBSPLL

AVDD11_DMD_1
AVDD11_DMD_2

DVDD18_EMMC_1
DVDD18_EMMC_2

+1.1V_VDD

M20
M21
N13
N14
N15
N16
N17
N18
P20
P21
R13
R14
R15
R16
R17
R18
R19
R20
R21
T13
T20
T21
U14
U15
U16
U17
U18
U19
U20
U21
V13
V20
V21
W13
W14
W15
W16
W17
W18
W19
Y13
Y20
Y21
AA13
AA14
AA15
AA17
AA18
AA19
AA20
AA21
AB21
AB19
V12
W12
Y12
AA12

G18
H18

AF23
AF24
AF25

L26
M26

TP5209

+1.1V_VDD

AVDD11_DMD

TP5210

DVDD18_EMMC

+3.3V_Bypass Cap

+3.3V_NORMAL

L601

BLM18PG121SN1D

C601

4.7uF

+2.5V_Bypass Cap

+2.5V_NORMAL

L602

BLM18PG121SN1D

C602

4.7uF

+2.5V_NORMAL

AVDD25_AUD

L603

BLM18PG121SN1D

C603

4.7uF

DVDD33

10V

AVDD25

10V

10V

C604

4.7uF

C605

4.7uF

C606

4.7uF

B22
B24
C22
C23
C24

D4
D5

D6
D20
D21

E6
E20
E21

F6

F7

F8
F18
F19
F20
F21

G7

G8

G9
G10
G11
G12
G13
G14
G15
G16
G17
G20
G21
G22
G23
G24
G25
G26
G27

H7

H8

H9
H10
H11
H12
H13
H14
H15
H16
H17
H21
H22
H23
H24
H25
H26
H27
H31

J7

J8
J26
J27

K7

K8
K26
K27

L7

L8
L11
L12
L13
L14
L15
L16
L17
L19
L20
L27

M7

M8
M11
M12
M13
M14
M15
M16
M17
M18
M19
M22
M27

N7

N8
N11
N12
N19
N20
N21
N22
N23
N26
N27
N30

P7

P8
P11
P12
P13
P14
P15
P16
P17
P18

IC101

LG1311

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113

GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226

P19
P22
P26
P30
R7
R8
R11
R12
R22
R26
R27
T6
T7
T8
T12
T14
T15
T16
T17
T18
T19
T22
T26
T27
U6
U7
U8
U11
U12
U13
U22
U26
V4
V5
V6
V7
V8
V14
V15
V16
V17
V18
V19
V22
V26
V30
V31
W4
W8
W20
W21
W22
W23
W26
W27
Y2
Y3
Y4
Y8
Y14
Y15
Y16
Y17
Y18
Y19
Y22
Y26
AA8
AA16
AA22
AA26
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB20
AB22
AB26
AB30
AB31
AC16
AC26
AD26
AE26
AF6
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF26
AG20
AG25
AG31
AH25
AJ25
AK9
AK25
AL9
AL15

+1.1V_Bypass Cap

+3.3V_NORMAL

C607

0.1uF
16V

10V

L606

BLM18PG121SN1D

C614

4.7uF

AVDD33

10V

C615

0.1uF
16V

AFE 3CH Power

+2.5V_NORMAL

C608

0.1uF

10V

16V

C609

0.1uF

10V

16V

AVDD25_C4TX

L604

BLM18PG121SN1D

C610

0.1uF
16V

C613

4.7uF

C616

0.1uF

10V

16V

+1.1V_VDD

C618

C617

4.7uF

4.7uF
10V

+1.1V_VDD

BLM18PG121SN1D

10V

L607

C619

4.7uF
10V

AVDD11_DMD

C622

4.7uF
10V

C620

4.7uF
10V

C625

0.1uF

C623

4.7uF

16V

C626

0.1uF

10V

16V

0.1uF

0.1uF
16V

16V

C628

C627

+1.5V_Bypass Cap

+1.5V_DDR

OPT

C631

+1.5V_DDR

C629
22uF
10V

OPT

C630
22uF
10V

0.1uF
16V

C632

0.1uF
16V

C633

0.1uF
16V

C634

0.1uF
16V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

MID_LG1311

VCC & GND

2013.04.04
6

31

PCM_RESET

Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

/PCM_WAIT

PCM_INPACK

/PCM_IORD
/PCM_IOWR

R702
R703

R701

CI_IN_TS_DATA[0-7]

CI

33

CI

33

OPT

33

+5V_CI_ON

PCM_INPACK

/PCM_CE2

10K

R707

CI

0.1uF
CI

/CI_CD1

CI_TS_DATA[3]

CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

/PCM_CE2

CI_IN_TS_DATA[0]
CI_IN_TS_DATA[1]
CI_IN_TS_DATA[2]
CI_IN_TS_DATA[3]

CI_IN_TS_DATA[4]
CI_IN_TS_DATA[5]
CI_IN_TS_DATA[6]
CI_IN_TS_DATA[7]

CI_TS_CLK

/PCM_REG

CI_TS_VAL

CI_TS_SYNC
CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]

/CI_CD2

C701

C702

4.7uF
10V

CI

+5V_CI_ON

R715

CI

R716 100

PAGE 7

C705

0.1uF
16V

CI_ADDR[12]

CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]

CI_ADDR[4]

CI_ADDR[3]

CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

CI_DATA[0-7]

R721 33

OPT

CI_ADDR[10]

CI_ADDR[11]
CI_ADDR[9]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[12]
CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]
CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

/PCM_CE1

+5V_CI_ON

R722

10K

CI
CI_DATA[0]
CI_DATA[1]
CI_DATA[2]
CI_DATA[3]

/PCM_OE

CI

/PCM_WE
/PCM_IRQA

CI_DATA[0-7]

CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

AR713

33

CI

AR714

33

EB_DATA[0]
EB_DATA[1]
EB_DATA[2]
EB_DATA[3]

EB_DATA[4]
EB_DATA[5]
EB_DATA[6]
EB_DATA[7]

EB_DATA[0-7]

EB_DATA[0-7]

CI

JK701

10125901-015LF

35

100

36

CI

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

65
66
67
68

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2660
2761
2862
2963
3064
31
32
33
34

G1G2

69

CI_DATA[3]
CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

CI

R720 33

C704 0.1uF

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]

CI_ADDR[10]

CI_ADDR[11]
CI_ADDR[9]

CI_ADDR[8]

CI_ADDR[13]

CI_ADDR[14]

CI

CI

TPO_DATA[0-7]

/CI_CD2
/CI_CD1

TPO_CLK
TPO_SOP
TPO_VAL

+5V_NORMAL

CI

10K

R725

CI

C706

0.1uF
16V

TPO_DATA[0]
TPO_DATA[1]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[6]
TPO_DATA[7]

CI

10K

/PCM_WAIT

R726

/PCM_IRQA

CI

C707

0.1uF
16V

PCM_INPACK

CI_TS_VAL

CI_TS_SYNC

CI_TS_DATA[7]
CI_TS_DATA[6]
CI_TS_DATA[5]
CI_TS_DATA[4]

CI_TS_CLK

CI_IN_TS_VAL

CI_IN_TS_CLK
CI_IN_TS_SYNC

C703
12pF
50V
OPT

CI

AR701

33

CI

AR702

33

CI

AR703

33

AR704

CI

100

AR705

CI

100

AR706

CI

100

CI_IN_TS_DATA[0]
CI_IN_TS_DATA[1]
CI_IN_TS_DATA[2]
CI_IN_TS_DATA[3]
CI_IN_TS_DATA[4]
CI_IN_TS_DATA[5]
CI_IN_TS_DATA[6]
CI_IN_TS_DATA[7]

CI_IN_TS_CLK
CI_IN_TS_SYNC
CI_IN_TS_VAL

CAM_WAIT_N
CAM_IREQ_N

CAM_CD2_N
CAM_CD1_N

CAM_INPACK_N

TPI_VAL
TPI_SOP

TPI_DATA[7]
TPI_DATA[6]
TPI_DATA[5]
TPI_DATA[4]

C708
12pF
50V

OPT

TPI_CLK

CI_ADDR[0]
CI_ADDR[1]
CI_ADDR[2]
CI_ADDR[3]

CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]

CI_ADDR[8]

CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]

CI

AR709

33

CI

AR710

33

CI

AR711

33

EB_ADDR[0]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]

EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[6]
EB_ADDR[7]

EB_ADDR[8]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]

CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

/PCM_REG

/PCM_OE
/PCM_WE

/PCM_IORD
/PCM_IOWR

CI

AR712

33

CI

AR708

33

EB_ADDR[12]
EB_ADDR[13]
EB_ADDR[14]
CAM_REG_N

EB_OE_N
EB_WE_N
EB_BE_N1
EB_BE_N0

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

CI_TS_DATA[3]
CI_TS_DATA[2]
CI_TS_DATA[1]
CI_TS_DATA[0]

AR707

CI

100

TPI_DATA[3]
TPI_DATA[2]
TPI_DATA[1]
TPI_DATA[0]

MID_LG1311

PCMCIA

2013.03.22
7

31