LG 43UF690T, 49UF690T, 43F690Y, 43F690T Schematic

Internal Use Only

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

LED TV

SERVICE MANUAL

CHASSIS : LB53K

MODEL : 43/49UF690T/690Y

43/49UF690T/690Y-TC

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL68704916 (1504-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 10

BLOCK DIAGRAM .................................................................................. 18

EXPLODED VIEW .................................................................................. 19

SCHEMATIC CIRCUIT DIAGRAM ........................................... APPENDIX

TROUBLE SHOOTING GUIDE ................................................. APPENDIX

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precau­tions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power
source before;

a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug

or other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explo­sion hazard.

2. Test high voltage only by measuring it with an appropriate
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its
assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture.
Unless specied otherwise in this service manual, lubrication

of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks
are correctly installed.

7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged eas­ily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component dam­age caused by static by static electricity.

1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alter­natively, obtain and wear a commercially available discharg­ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.

2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or expo­sure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder
ES devices.

4. Use only an anti-static type solder removal device. Some sol-

der removal devices not classied as “anti-static” can generate
electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads elec­trically shorted together by conductive foam, aluminum foil or
comparable conductive material).

7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective mate­rial to the chassis or circuit assembly into which the device will
be installed.
CAUTION: Be sure no power is applied to the chassis or cir­cuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replace­ment ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity suf­cient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropri­ate tip size and shape that will maintain tip temperature within
the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire­bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand

against the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there
only until the solder ows onto and around both the compo­nent lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent at against the cir­cuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by
gently prying up on the lead with the soldering iron tip as the
solder melts.

2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing
the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and
solder it.

3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor
Removal/Replacement

1. Remove the defective transistor by clipping its leads as close
as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remain­ing on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.

Power Output, Transistor Device
Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit
board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as pos­sible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit
board.

3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.

3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed when­ever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connec­tions).

1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.

1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly con­nected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

Fuse and Conventional Resistor
Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.

2. Securely crimp the leads of replacement component around
notch at stake top.

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This specification is applied to the LED TV used LB53K
chassis.

2. Requirement for Test

Each part is tested as below without special notice

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

each drawing and specification by part number in
accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC specification

- Wireless : Wireless HD Specification (Option)

4. Model General Specification

No. Item Specication Remarks

1 Market Asia, Oceania, Africa, Middle East(PAL/DVB Market)

2 Television system

3 Channel Storage ATV / DTV - 1500EA

4 Receiving system

5 Video Input RCA PAL, SECAM, NTSC 4 System : PAL, SECAM, NTSC, PAL60

6 Component Input Y/Pb/Pr

7 Head phone out

8 HDMI Input HDMI1-DTV,HDMI2-DTV, HDMI3-DTV PC(HDMI Ver. 1.4), Support HDCP

9 Audio Input DVI Audio, Component, AV1

10 SPDIF out SPDIF out

11 USB Input For My Media(Movie/Photo/Music List) or For SVC

1) PAL-BG/DK/I/I’

2) SECAM L/L’, DK, BG, I

3) DVB-T/T2, C, S/S2

Analog : Upper Heterodyne
Digital : COFDM(DVB-T) Only DVB-T Model
Digital : COFDM(DVB-T/T2) Only DVB-T2 Model
Digital : QAM

Antenna, AV1, Component, HDMI1, HDMI2, HDMI3,
USB1, USB2, USB3

► DVB-T

- Guard Interval(Bitrate_Mbit/s): 1/4, 1/8, 1/16, 1/32

- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2

- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,

- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C

- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s

- Modulation :
16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2

- Symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s

- Viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode: 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. External Input Support Format

5.1. 2D

(1) CVBS input

No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed Remarks

1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I) NTSC-M

2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I) NTSC-M

3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz PAL-BDGHI

(2) Component (Y, CB/PB, CR/PR)

No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed

1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I)

2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I)

3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz

4 720*480p 31.47 59.94 27.00 SDTV 480P

5 720*480p 31.50 60.00 27.03 SDTV 480P

6 720*576p 31.25 50.00 27.00 SDTV 576P 50Hz

7 1280*720 44.96 59.94 74.18 HDTV 720P

8 1280*720 45.00 60.00 74.25 HDTV 720P

9 1280*720 45.00 50.00 74.25 HDTV 720P 50Hz

10 1920*1080 28.13 50.00 74.25 HDTV 1080I 50Hz,

11 1920*1080 33.72 59.94 74.18 HDTV 1080I

12 1920*1080 33.75 60.00 74.25 HDTV 1080I

13 1920*1080 56.25 50.00 148.50 HDTV 1080P

14 1920*1080 67.50 60.00 148.50 HDTV 1080P

Only for training and service purposes

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

(3) HDMI (DTV)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks

1 640*480 31.47 59.94 25.13 SDTV 480P

2 640*480 31.50 60.00 25.13 SDTV 480P

3 720*480 15.73 59.94 13.50 SDTV, DVD 480I(525I)

Spec. out but display4 720*480 15.75 60.00 13.51 SDTV, DVD 480I(525I)

5 720*576 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz

6 720*480 31.47 59.94 27.00 SDTV 480P

7 720*480 31.50 60.00 27.03 SDTV 480P

8 720*576 31.25 50.00 27.00 SDTV 576P

9 1280*720 44.96 59.94 74.18 HDTV 720P

10 1280*720 45.00 60.00 74.25 HDTV 720P

11 1280*720 37.50 50.00 74.25 HDTV 720P

12 1920*1080 28.13 50.00 74.25 HDTV 1080I

13 1920*1080 33.72 59.94 74.18 HDTV 1080I

14 1920*1080 33.75 60.00 74.25 HDTV 1080I

15 1920*1080 26.97 23.98 63.30 HDTV 1080P

16 1920*1080 27.00 24.00 63.36 HDTV 1080P

17 1920*1080 33.71 29.97 79.12 HDTV 1080P

18 1920*1080 33.75 30.00 79.20 HDTV 1080P

19 1920*1080 56.25 50.00 148.50 HDTV 1080P

20 1920*1080 67.43 59.94 148.35 HDTV 1080P

21 1920*1080 67.50 60.00 148.50 HDTV 1080P

22 3840*2160 53.95 23.98 297.00 UDTV 2160P

23 3840*2160 54.00 24.00 297.00 UDTV 2160P

24 3840*2160 56.25 25.00 297.00 UDTV 2160P

25 3840*2160 61.43 29.97 297.00 UDTV 2160P

26 3840*2160 67.50 30.00 297.00 UDTV 2160P

27 3840*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

28 3840*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0

29 3840*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

30 4096*2160 53.95 23.98 297.00 UDTV 2160P

31 4096*2160 54.00 24.00 297.00 UDTV 2160P

32 4096*2160 56.25 25.00 297.00 UDTV 2160P

33 4096*2160 61.43 29.97 297.00 UDTV 2160P

34 4096*2160 67.50 30.00 297.00 UDTV 2160P

35 4096*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

36 4096*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0

37 4096*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

(4) HDMI Input (PC)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks

1 640*350 31.47 70.09 25.17 EGA

2 720*400 31.47 70.08 28.32 DOS

3 640*480 31.47 59.94 25.17 VESA(VGA)

4 800*600 37.88 60.32 40.00 VESA(SVGA)

5 1024*768 48.36 60.00 65.00 VESA(XGA)

6 1360*768 47.71 60.02 84.75 VESA(WXGA)

7 1152*864 54.35 60.05 80.00 VESA

8 1280*1024 63.98 60.02 109.00 SXGA

9 1920*1080 67.50 60.00 158.40 WUXGA(Reduced Blanking)

10 3840*2160 54.00 24.00 297.00 UDTV 2160P

11 3840*2160 56.25 25.00 297.00 UDTV 2160P

12 3840*2160 67.50 30.00 297.00 UDTV 2160P

13 4096*2160 53.95 23.98 297.00 UDTV 2160P

14 4096*2160 54.00 24.00 297.00 UDTV 2160P

Only for training and service purposes

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to all of the LED TV with
LB53K chassis.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz.
(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15.

In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
hours.

In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.

[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.

3.2. LAN Inspection

3.2.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

3.2.2. LAN inspection solution

▪ LAN Port connection with PCB
▪ Network setting at MENU Mode of TV
▪ Setting automatic IP
▪ Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC
Address.

3.2.3. WIDEVINE key Inspection

- Confirm key input data at the "IN START" MENU Mode.



3. Automatic Adjustment

3.1. MAC address D/L, CI+ key D/L(Option),
Widevine key D/L, ESN D/L, HDCP20 D/L

Connect: USB port
Communication Prot connection

▪ Com 1,2,3,4 and 115200(Baudrate)

Mode check: Online Only

▪ Check the test process

: DETECT→MAC→ESN→Widevine→CI(option)→HDCP20
▪ Play: Press Enter key
▪ Result: Ready, Test, OK or NG
▪ Printer Out (MAC Address Label)

3.3. LAN PORT INSPECTION(PING TEST)

Connect SET → LAN port == PC → LAN Port

SET PC

3.3.1. Equipment setting

(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

3.3.2. LAN PORT inspection(PING TEST)

(1) Play the LAN Port Test Program.

(2) Connect each other LAN Port Jack.

(3) Play Test (F9) button and confirm OK Message.
(4) Remove LAN cable.

Only for training and service purposes

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

3.4. Model name & Serial number Download

3.4.1. Model name & Serial number D/L

▪ Press "P-ONLY" key of service remote control.

(Baud rate : 115200 bps)

▪ Connect RS-232C Signal to USB Cable to USB.
▪ Write Serial number by use USB port.
▪ Must check the serial number at Instart menu.

3.4.2. Method & notice

(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory
by D-book 4.0.

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes

model name or serial number is initialized.(Not always)

It is impossible to download by bar code scan, so It need

Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name(ex 47LB650V-ZA) or Serial
number like photo.

4) Check the model name Instart menu. → Factory name

displayed. (ex 47LB650V-ZA)

5) Check the Diagnostics.(DTV country only) → Buyer

model displayed. (ex 47LB650V-ZA)

3.5. CI+ Key checking method

(Check the Section 3.1)
Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).

=> Check the Download to CI+ Key value in LGset.

3.5.1. Check the method of CI+ Key value

(1) Check the method on Instart menu
(2) Check the method of RS232C Command

1) Into the main ass’y mode(RS232: aa 00 00)

CMD 1 CMD 2 Data 0

A A 0 0

2) Check the key download for transmitted command
(RS232: ci 00 10)

CMD 1 CMD 2 Data 0

C I 1 0

3) Result value

- Normally status for download : OKx

- Abnormally status for download : NGx

3.5.2. Check the method of CI+ key value(RS232)

1) Into the main ass’y mode(RS232: aa 00 00)

CMD 1 CMD 2 Data 0

A A 0 0

2) Check the mothed of CI+ key by command
(RS232: ci 00 20)

CMD 1 CMD 2 Data 0

C I 2 0

3) Result value
i 01 OK 1d1852d21c1ed5dcx

CI+ Key Value

Only for training and service purposes

3.6. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command

H-freq(kHz) V-freq.(Hz)

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

(2) Check the menu on in-start

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4. Manual Adjustment

4.1. EDID(The Extended Display Identification
Data)/DDC(Display Data Channel) download

4.1.1. Overview

It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information sharing without any necessity
of user input. It is a realization of "Plug and Play".

4.1.2. Equipment

- Since embedded EDID data is used, EDID download JIG,

HDMI cable and D-sub cable are not need.

- Adjustment remote control

4.1.3. Download method

(1) Press "ADJ" key on the Adjustment remote control, then

select "12.EDID D/L", By pressing "Enter" key, enter EDID
D/L menu.

For HDMI EDID

DVI-D to HDMI or HDMI to HDMI

(2) Select "Start" button by pressing "Enter" key, HDMI1/

HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG.

4.1.4. EDID DATA

▪ Reference

- HDMI1 ~ HDMI3

- In the data of EDID, bellows may be different by Input mode.

0 1 2 3 4 5 6 7 8 9 A B C D E F

0x00 00 FF FF FF FF FF FF 00 1E 6D

ⓒ

0x01
0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20
0x07
0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21
0x01 22 15 01 29 3D 06 C0 15 07 50
0x02
0x03
0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18
0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D
0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

ⓓ

ⓕ

10 28 10 E3 05 03 01 02 3A 80 18 71 38

ⓕ

ⓐ Product ID
ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ → ‘01’, Year : ‘2015’ → ‘19’

ⓓ Model Name(Hex): LGTV
ⓔ Checksum(LG TV): Changeable by total EDID data.
ⓕ Vendor Specific(HDMI)

ⓐ ⓑ

ⓕ

ⓓ

ⓔ1

01

ⓔ2

(1) EDID for Non 3D Model

# HDMI 1(C/S: E6 1D) - 3G
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50

A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02
B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20
C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0
D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1D

# HDMI2 (C/S: E6 0D) - 3G
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
A0 09 57 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02
B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20
C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0
D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D

# HDMI3 (C/S: E6 FD) - 3G
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

Only for training and service purposes

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
A0 09 57 07 6E 03 0C 00 30 00 B8 3C 20 00 80 01 02
B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20
C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0
D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FD

* Checksum for Non 3D model (HDMI 1/2/3)

Input FFh (Checksum)

HDMI1 E6 1D

HDMI2 E6 0D

HDMI3 E6 FD

# HDMI 1(C/S : A0 C7) -6G
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 47 F1 58 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
A0 C0 15 07 50 09 57 07 6E 03 0C 00 10 00 B8 3C 20
B0 00 80 01 02 03 04 67 D8 5D C4 01 78 80 03 E3 05
C0 C0 00 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40
D0 70 36 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E
E0 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C7

# HDMI 2(C/S : E6 0D) - 6G
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
A0 09 57 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02
B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20
C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0
D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D

# HDMI 3(C/S : E6 FD) - 6G
EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
A0 09 57 07 6E 03 0C 00 30 00 B8 3C 20 00 80 01 02
B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20
C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0
D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FD

* Checksum for Non 3D model (HDMI 1/2/3)

Input FFh (Checksum)

HDMI1 A0 C7

HDMI2 E6 0D

HDMI3 E6 FD

4.2. White Balance Adjustment

4.2.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation
(2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one
of R/G/B is fixed at 192, and the other two is lowered to
find the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Warm-up time: About 5 Min

3) Surrounding Humidity : 20 % ~ 80 %

4.2.2. Equipment

(1) Color Analyzer: CA-210 (LED Module : CH 14)
(2) Adjustment Computer(During auto adj., RS-232C protocol

is needed)
(3) Adjustment Remote control
(4) Video Signal Generator MSPG-925F 720p/216-Gray

(Model: 204, Pattern: 49)

→ Only when internal pattern is not available

• Color Analyzer Matrix should be calibrated using CS-100.

4.2.3. Equipment connection MAP

Color Analyzer

Probe

RS- 232C

Pattern Generator

Signal Source

* If TV internal pattern is used, not needed

RS-232C

Computer

RS-232C

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.2.4. Adj. Command (Protocol)

<Command Format>

START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP

- LEN: Number of Data Byte to be sent

- CMD: Command

- VAL: FOS Data value

- CS: Checksum of sent data

- A: Acknowledge

Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

4.2.5. Adj. method

(1) Auto adj. method

1) Set TV in adj. mode using POWER ON key.

2) Zero calibrate probe then place it on the center of the
Display.

3) Connect Cable.(RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre
mode. (Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ RS-232C Command used during auto-adjustment.

RS-232C COMMAND

[CMD ID DATA]

wb 00 00 Begin White Balance adjustment

wb 00 10 Gain adjustment(internal white pattern)

wb 00 1f Gain adjustment completed

wb 00 20 Offset adjustment(internal white pattern)

wb 00 2f Offset adjustment completed

wb 00 ff

End White Balance adjustment
(internal pattern disappears)

Explanation

Ex) wb 00 00 → Begin white balance auto-adj.

wb 00 10 → Gain adj.
ja 00 ff → Adj. data

jb 00 c0
...
...

wb 00 1f → Gain adj. completed
*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj.
wb 00 ff → End white balance auto-adj.

▪ Adj. Map

Cool

Medium

Warm

Command

Adj. item

R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

R Cut

G Cut

B Cut

R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

R Cut

G Cut

B Cut

R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

R Cut

G Cut

(lower case ASCII)

CMD1 CMD2 MIN MAX

Data Range

(Hex.)

Default

(Decimal)

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

(2) Manual adjustment. method

1) Set TV in Adj. mode using POWER ON.

2) Zero Calibrate the probe of Color Analyzer, then place it
on the center of LCD module within 10 cm of the surface.

3) Press ADJ key → EZ adjust using adj. R/C → 7. White­Balance then press the cursor to the right(key ►).

(When right key(►) is pressed 216 Gray internal pattern

will be displayed)

4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.

5) Adjustment is performed in COOL, MEDIUM, WARM 3
modes of color temperature.

** G-fix adjustment
Adjust modes (Cool), Fix the G gain to 172 (default data)
and change the others (G/B Gain).
Adjust two modes(Medium / Warm), Fix the one of R/G/B
gain to 192 (default data) and decrease the others.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 7.White Balance, you can select one of 2 Test­pattern: ON, OFF. Default is inner(ON). By selecting OFF,
you can adjust using RF signal in 216 Gray pattern.

▪ Adjustment condition and cautionary items

1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.

2) Probe location
: Color Analyzer(CA-210) probe should be within 10 cm

and perpendicular of the module surface (80° ~ 100°)

3) Aging time

- After Aging Start, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked

using no signal or Full-white pattern.

Only for training and service purposes

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.2.6. Reference (White balance Adj. coordinate and
color temperature)

▪ Luminance : 206 Gray
▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Cool 0.271 0.270 13000 K 0.0000

Medium 0.286 0.289 9300 K 0.0000

Warm 0.313 0.329 6500 K 0.0000

▪

Standard color coordinate and temperature using CA-210(CH 14)

Mode

Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000

Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000

Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000

Coordinate

x y

Coordinate

x y

Temp ∆uv

Temp ∆uv

4.2.7. LED White balance table

▪ Edge & ALEF LED module change color coordinate because

of aging time.

▪ Apply under the color coordinate table, for compensated

aging time.

▪ (Normal line) White balance table

Model : (normal line) LGD

Aging

time

(Min)

1 0-2 282 289 297 308 324 348
2 3-5 281 287 296 306 323 346
3 6-9 279 284 294 303 321 343
4 10-19 277 280 292 299 319 339
5 20-35 275 277 290 296 317 336
6 36-49 274 274 289 293 316 333
7 50-79 273 272 288 291 315 331
8 80-119 272 271 287 290 314 330
9 Over 120 271 270 286 289 313 329

Cool Medium Warm

x y x y x y

271 270 286 289 313 329

4.4. Magic Motion Remote control test

- Equipment : RF Remote control for test, IR-KEY-Code
Remote control for test

- You must confirm the battery power of RF-Remote control
before test(recommend that change the battery per every lot)

- Sequence (test)

1) If you select the ‘start key(OK)’ on the Adjustment remote

control, you can pairing with the TV SET.

2) You can check the cursor on the TV Screen, when select

the "OK" key on the Adjustment remote control.

3) You must remove the pairing with the TV Set by select

‘Mute + OK Key’ on the Adjustment remote control.

4.5. 3D function test

(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
* HDMI mode NO. 872 , pattern No.83
(1) Please input 3D test pattern like below.

(2) When 3D OSD appear automatically, then select green key.

(3) Don't wear a 3D Glasses, Check the picture like below.

▪ AUO, INX, Sharp, CSOT, BOE (Cool is 13000 K)

Cool Medium Warm

x y x y x y

271 270 285 293 313 329

Target 278 280 293 299 320 339

4.3. Local Dimming Function Check

(1) Turn on TV.
(2) At the Local Dimming mode, module Edge Backlight

moving right to left Back light of IOP module moving.
(3) Confirm the Local Dimming mode.
(4) Press “exit” Key.

Only for training and service purposes

4.6. Option selection per country

4.6.1. Overview

- Option selection is only done for models in AJ/JA/IL

4.6.2.Method

(1) Press "ADJ" key on the Adjustment remote control, then

select Country Group Menu.

(2) Depending on destination, select Country Group Code or

Country Group then on the lower Country option, select

US, CA, MX. Selection is done using +, - or ►◄ KEY.

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.7. HDMI ARC Function Inspection

(1) Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

(2) Test method

1) Insert the HDMI Cable to the HDMI ARC port from the
master equipment. (HDMI 2)

2) Check the sound from the TV Set.

5. GND and Internal Pressure check

5.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power Cord is fully inserted to the SET. (If
loose, re-insert)

(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically.

(Remove CORD, A/V form AV JACK BOX.)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.

5.2. Checkpoint

▪ TEST voltage

- GND: 1.5 KV / min at 100 mA

- SIGNAL: 3 KV / min at 100 mA

▪ TEST time: 1 second
▪ TEST POINT

- GND TEST = POWER CORD GND & SIGNAL CABLE

METAL GND

- Internal Pressure TEST = POWER CORD GND & LIVE &

NEUTRAL

▪ LEAKAGE CURRENT: At 0.5 mArms

3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

4.8. Ship-out mode check (In-stop)

- After final inspection, press In-Stop key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.

6. Audio

No. Item Min Typ Max Unit

Audio practical max

1

Output, L/R (Distortion

=10% max Output)

Speaker

2

(6 Ω Impedance)

Measurement condition:
(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms

10 12 W

8.10 10.8 Vrms

10 12 W

EQ Off

AVL Off

Clear Voice Off

EQ On

AVL On

Clear Voice On

Only for training and service purposes

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

7.

USB S/W Download(Service only)

(1) Put the USB Stick to the USB socket.
(2) Automatically detecting update file in USB Stick.

- If your downloaded program version in USB Stick is
Older, it didn't work. But your downloaded version is
Newer, USB data is automatically detecting.(Download

Version High & Power only mode, Set is automatically

Download)

(3) Show the message "Copying files from memory".

(4) Updating is starting.
(5) Updating Completed, The TV will restart automatically.

8. Tool Option selection

▪ Method: Press Adj. key on the Adjustment remote control,

then select Tool option.

(6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)

* If downloading version is more new than your TV have, TV

can lost all channel data. In this case, you have to channel
recover. if all channel data is cleared, you didn't have a
DTV/ATV test on production line.

* After downloading, have to adjust TOOL OPTION again.

1) Push "IN-START" key in service remote control.

2) Select "Tool Option 1" and push "OK" key.

3) Punch in the number. (Each model has their number.)

Only for training and service purposes

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Y

DDR3 1866 X 32

BLOCK DIAGRAM

SUB

ASS

M)

DDR3 1866 X 32

(256MB X 2EA)

(512MB X 2EA)

(256Kb)

EEPROM(NVRA

eMMC

(8GB)

51P

MAIN Audio AMP

(NTP7514)

WIFI/BT Combo

IR / KEY

LOGO LIGHT(Ready)

(RENESAS

Sub Micom

R5F100GEAFB)

X_TAL

32.768KHz

C

I2C 1

B

A

(512MB X 2EA)

DDR3 1866 X 32

X_TAL

24MHz

P_TS

T/C Demod

Analog Demod

P_TS

IF (+/-)

CVBS

Vx1

I2C 6

Mstar

USB

OCP

USB1 (3.0)

LM15U

OCP

USB2 (2.0)

I2C 4

I2S Out

USB_WIFI

HDMI

HDMI1

HDMI2(ARC)

H/P

RS232C

CVBS/YPbPr

AV/COMP

I2C 3

(HW Port)

ETHERNET

SPDIF OUT

LAN

OPTIC

T2/C

TUNER

(T2/C/A)

Air/

Cable

REA

Only for training and service purposes

(S2)

DEMOD

(S2)

TUNER

DVB-S

R

LNB

- 18 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

502

900

500

401

901

400

120

800

121

521

570

540

LV1

530

571

Set + Stand

820

A22 A10

Only for training and service purposes

200

- 19 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

NVRAM

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

Atmel_NVRAM

IC102

AT24C256C-SSHL-T

EAN61133501

A0

1

A1

2

A2

A0’h

3

GND

4

SPI_CK_SOC
SPI_DI_SOC
SPI_DO_SOC

/SPI_CS

FRC_FLASH_SEL

FRC_FLASH_WP

TXOSD_3P
TXOSD_3N
TXOSD_2P
TXOSD_2N
TXOSD_1P
TXOSD_1N
TXOSD_0P
TXOSD_0N

COMPENSATION_DONE

On_RF_Done

OLED_FW_Update

LM15U HW Option

BIT0
BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT9

BIT10

BIT11

BIT12

BIT13

20140701 version

BIT(0/1)

BIT4

BIT5
BIT6

TW/COL

00

CN/HK

01

10

11

Display

Resolution

Model

VCC

8

WP

7

SCL

6

SDA

5

URSA9_CONNECT

L/D_VSYNC_SOC

L/D_CLK_SOC

URSA_RESET_SoC

DVB

EU

AJJA

C103

0.1uF

LOCKAn_OSD

L/D_DI_SOC

BIT0_1

R104 10K

BIT0_0

R103 10K

ATSC

US

KR

BR/PH

Sri Lanka

Low

FHD

LM15U only

+3.3V_NORMAL

Write Protection

- Low : Normal Operation

- High : Write Protection

AR100
33

1

A1

2

A2

3

GND

4

Rohm_NVRAM

VCC

8

WP

7

SCL

6

SDA

5

I2C_SCL1
I2C_SDA1

CHIP CONFIG

IC102-*1

BR24G256FJ-3

A0

LM15U+URSA9

CHIP_CONFIG[3:0]
{LED1, SPI_DI,LED0, PWM_PM}

Value Mode Description
4’b1000 SB51_ExtSPI 51 boot from SPI
4’b1001 HEMCU_ExtSPI ARM boot from SPI
4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC
4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND
4’b1100 DBUS for test only
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication
4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication
4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication;

OLED LM15U_ONLY

DATA_FORMAT_1_SOC

DATA_FORMAT_0_SOC

+3.3V_NORMAL

10K

BIT1_1

R108

10K

BIT1_0

R107

BIT2_1

R110 10K

BIT2_0

R109 10K

JP

JP

High

OLEDLCD

UHD

LM15U+URSA

BIT3_1

R112 10K

BIT3_0

R111 10K

BIT4_1

R116 10K

BIT4_0

R115 10K

R118 10K

OPT

R117 10K

BIT(7/8)

00

01

10

11

BIT7_1

BIT6_1

R120 10K

BIT7_0

BIT6_0

R119 10K

URSA11 4K@60Hz

URSA11 4K@120Hz

R122 10K

R121 10K

B/E(FRC)

NONE

URSA9

BIT8_1

R124 10K

R181 10K

NON_HDMI_EXT_EDID

BIT8_0

R123 10K

R159 10K

HDMI_EXT_EDID

OPT

R183 10K

R182 10K

+3.3V_NORMAL

OPT

OPT

R157 4.7K

R161 4.7K

R163 4.7K

R165 4.7K

OPT

OPT

R158 4.7K

R164 4.7K

R162 4.7K

R166 4.7K

+3.3V_NORMAL

OPT
R155

FRC_FLASH_SEL

OPT

OPT

R185 10K

R156 10K

R188 10K

OPT

R184 10K

R186 10K

R189 10K

EU/CIS

00

T2/C/S2 PIP

01

T2/C/S2

T/C

10

11

4.7K

FRC_FLASH_WP

AJJA

T2/C PIP

T2/C/S2

T2

LED1
SPI_DI_SOC
LED0
PWM_PM

M_RFModule_RESET

FRC_FLASH_SEL

R167

0

+3.3V_NORMAL

R126

10K

OPT

R179

10K

U_SPI_WP_f_SoC

WOL_WAKE_UP

TW/COL

T2/C PIP

T2/C

T/C

T ATSC

WOL_WAKE_UP

CN/HKBIT(2/3)

Default

URSA_RESET_SoC

COMPENSATION_DONE

AVDD_3P3

ATSC NIM+T2

ATSC+T2

ATSC PIP

PWM_DIM

PWM_DIM2

On_RF_Done

AMP_RESET_N

PWM_PM

/USB_OCD2

USB_CTL2

OLED_FW_Update

SPI_CK_SOC
SPI_DI_SOC
SPI_DO_SOC

/SPI_CS

DDCA_CK
DDCA_DA

SOC_TX
SOC_RX

/TU_RESET2

I2C_SCL6
I2C_SDA6

DDTS_TX
DDTS_RX

/TU_RESET1

BIT0
BIT1
BIT2
BIT3

BIT4
BIT12
BIT13

I2C_SCL3
I2C_SDA3

I2C_SCL1
I2C_SDA1

CPU_VID0

CORE_VID0

LED0

R131
10K

LED1

KR

North.AM

R168

0

OPT

R1870

WOL_WAKE_UP

A16

PWM0/GPIO157

C15

PWM1/GPIO158

A15

PWM2/GPIO159

B15

PWM3/GPIO160

C14

PWM4/GPIO161

E4

PWM_PM/GPIO10

H6

SAR0/GPIO50

J6

SAR1/GPIO51

G5

SAR2/GPIO52

J5

SAR3/GPIO53

D1

SAR5

D2

SPI_CK/GPIO1

D3

SPI_DI/GPIO2

E2

SPI_DO/GPIO3

F1

SPI_CZ0/GPIO0

E3

SPI_CZ1/GPIO_PM6/GPIO19

F2

SPI_CZ2/GPIO_PM10/GPIO23

N5

DDCA_CK/UART0_RX/GPIO11

P5

DDCA_DA/UART0_TX/GPIO12

C9

GPIO67/TX1

A10

GPIO68/RX1

E9

GPIO69/TX2

F9

GPIO70/RX2

F10

GPIO71/TX3

G10

GPIO72/RX3

D9

GPIO76/TX4

M7

GPIO77/RX4

P6

GPIO94/TX5

N6

GPIO95/RX5

A12

GPIO62

A13

GPIO63

C12

GPIO64

B12

GPIO65

C11

GPIO66

B10

GPIO73

C10

GPIO74

B11

GPIO75

F6

GPIO81/TX2

F5

GPIO82/RX2

K6

GPIO88/SCK0

L7

GPIO89/SDA0

C16

DDCR_CK/GPIO59

B16

DDCR_DA/GPIO58

D5

VID0/GPIO55

D4

VID1/GPIO56

H4

LED0/GPIO32

H5

LED1/GPIO33

L5

WOL/GPIO57

BR

Default

ISDB PIPDefault

ISDB EXT

ISDB INT

IC100

LGE5331(LM15U)

JP

LVSYNC/VBY0M
LHSYNC/VBY0P

A0M/VBY_OSD_0M
A0P/VBY_OSD_0P
A1M/VBY_OSD_1M
A1P/VBY_OSD_1P
A2M/VBY_OSD_2M

A2P/VBY_OSD_2P
ACKM/VBY_OSD_3M
ACKP/VBY_OSD_3P

A4M/OSD_LOCKN
A4P/OSD_HTPDN

GPIO_PM0/GPIO13
GPIO_PM2/GPIO15
GPIO_PM3/GPIO16
GPIO_PM4/GPIO17
GPIO_PM7/GPIO20
GPIO_PM8/GPIO21
GPIO_PM9/GPIO22

GPIO_PM13/GPIO26
GPIO_PM17/GPIO30
GPIO_PM18/GPIO31

GPIO_PM1/GPIO14
GPIO_PM5/GPIO18

GPIO_PM11/GPIO24
GPIO_PM12/GPIO25

AV_LNK/GPIO9

GPIO112/SPI1_DI
GPIO111/SPI1_CK
GPIO114/SPI2_DI
GPIO113/SPI2_CK

GPIO110/VSYNC_LIKE

GPIO115/DIM0
GPIO116/DIM1
GPIO117/DIM2
GPIO118/DIM3

EXTERNAL EDID

BIT9

FOR HDMI2.0

BIT10

BIT11

BIT12

Reserved

BIT13

LDE/VBY1M
LCK/VBY1P

B0M/VBY2M
B0P/VBY2P
B1M/VBY3M
B1P/VBY3P
B2M/VBY4M

B2P/VBY4P
BCKM/VBY5M
BCKP/VBY5P

B3M/VBY6M

B3P/VBY6P

B4M/VBY7M

B4M/VBY7P

A3M/LOCKN

A3P/HTPDN

TEST

Support

Division

CI+

VID

V-BY-ONE

AB36
AB35
AC36
AC37

AD37
AD36
AD35
AE36
AF36
AF37
AF35
AG37
AG35
AH36
AH35
AJ36

AJ35
AK37
AK36
AK35
AL35
AM36
AM37
AM35
AJ33
AJ34
AJ32
AJ31

R172

10K

AD5
AD6
AE2
AE3
AF4
AG5
AG6
AH6
AJ5
AJ4

K5
L6
M5
M6

L4
J15

A18
B18
C17
B17
C18
D18
E18
F18
E17

Low

EXTERNAL

NON_Division

VID Enable VID Disable

TXVBY1_0N
TXVBY1_0P
TXVBY1_1N
TXVBY1_1P

TXVBY1_2N
TXVBY1_2P
TXVBY1_3N
TXVBY1_3P
TXVBY1_4N
TXVBY1_4P
TXVBY1_5N
TXVBY1_5P
TXVBY1_6N
TXVBY1_6P
TXVBY1_7N
TXVBY1_7P

TXOSD_0N
TXOSD_0P
TXOSD_1N
TXOSD_1P
TXOSD_2N
TXOSD_2P
TXOSD_3N
TXOSD_3P

R173

10K

HTPDAn_OSD_Pull_down

HTPDAn_Video_Pull_down

HTPDAn_Video
HTPDAn_OSD

OPT

COMP1_DET

R1800

3D_EN

AV2_CVBS_DET

PCM_5V_CTL

5V_DET_HDMI_1
5V_DET_HDMI_2
5V_DET_HDMI_3

BIT7
BIT8

/USB_OCD3

USB_CTL3
DATA_FORMAT_0_SOC
DATA_FORMAT_1_SOC

BIT5
BIT6

L/D_DI_SOC

L/D_CLK_SOC
L/D_VSYNC_SOC
BIT11
AV1_CVBS_DET
HP_DET
SC_DET

High

NON_EXTERNAL

4_Division

New CI PathOld CI Path

EB_DATA[0-7]

EB_ADDR[0-14]

C
NXP_VBY1_LOCK_LED_TR

Q100-*1

B

MMBT3906(NXP)

E

LOCKAn_Video
HTPDAn_Video
LOCKAn_OSD
HTPDAn_OSD

+3.3V_NORMAL

LD1 00

VBY1_LOCK_LED

3.3K
R195

19- 21/R 6C-F R1S1 L/3T

VBY1_LOCK_LED

E

Q100
2N3906S-RTK

B

KEC_VBY1_LOCK_LED_TR

C

EMMC_DATA[0-7]

R175
22

R176

1K

+3.3V_NORMAL

URSA9_CONNECT

CAM_IREQ_N

CAM_CD1_N
PCM_RESET
CAM_REG_N

CAM_WAIT_N

TCON_I2C_EN

R177

10K

OPT

R178

10K
OPT

L_DIM_EN

BIT9

BIT10

EB_OE_N
EB_BE_N1
/PCM_CE1

EB_WE_N

EB_BE_N0

EMMC_CMD

EMMC_CLK

EMMC_RST

EMMC_STRB

RF_SWITCH_CTL

EB_DATA[0]
EB_DATA[1]
EB_DATA[2]
EB_DATA[3]
EB_DATA[4]
EB_DATA[5]

EB_DATA[6]
EB_DATA[7]

EB_ADDR[0]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]
EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[6]
EB_ADDR[7]
EB_ADDR[8]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]
EB_ADDR[12]

EB_ADDR[13]
EB_ADDR[14]

EMMC_DATA[6]
EMMC_DATA[7]
EMMC_DATA[2]
EMMC_DATA[1]
EMMC_DATA[0]

EMMC_DATA[3]

EMMC_DATA[4]
EMMC_DATA[5]

R174 0

OPT

R1910

AT13

PCMDATA[0]/GPIO152

AT9

PCMDATA[1]/GPIO153

AR13

PCMDATA[2]/GPIO154

AT17

PCMDATA[3]/GPIO124

AR16

PCMDATA[4]/GPIO125

AT16

PCMDATA[5]/GPIO126

AR21

PCMDATA[6]/GPIO127

AT18

PCMDATA[7]/GPIO128

AU10

PCMADR[0]/GPIO151

AT14

PCMADR[1]/GPIO150

AR10

PCMADR[2]/GPIO148

AT19

PCMADR[3]/GPIO147

AR18

PCMADR[4]/GPIO146

AU19

PCMADR[5]/GPIO144

AT11

PCMADR[6]/GPIO143

AT12

PCMADR[7]/GPIO142

AT20

PCMADR[8]/GPIO136

AU14

PCMADR[9]/GPIO134

AU16

PCMADR[10]/GPIO130

AR20

PCMADR[11]/GPIO132

AR12

PCMADR[12]/GPIO141

AU13

PCMADR[13]/GPIO137

AR19

PCMADR[14]/GPIO138

AU20

PCMIRQA/GPIO140

AT21

PCMOEN/GPIO131

AR15

PCMIORD/GPIO133

AU17

PCMCEN/GPIO129

AR11

PCMWEN/GPIO139

AR17

PCMCD/GPIO156

AU11

PCMRST/GPIO155

AR14

PCMREG/GPIO149

AT15

PCMIOWR/GPIO135

AT10

PCMWAIT/GPIO145

D7

NAND_ALE/GPIO194

F7

NAND_WPZ/GPIO193

G7

NAND_CEZ/EMMC_CMD/GPIO188

E6

NAND_CLE/GPIO190

F8

NAND_REZ/EMMC_CLK/GPIO191

E7

NAND_WEZ/GPIO192

E8

NAND_RBZ/EMMC_RSTN/GPIO195

D6

NAND_CEZ1/GPIO189

D8

NAND_DQS/GPIO196

A6

NAND_AD0/EMMC_D6/GPIO226

C6

NAND_AD1/EMMC_D7/GPIO225

A7

NAND_AD2/EMMC_D2/GPIO224

B7

NAND_AD3/EMMC_D1/GPIO223

C7

NAND_AD4/EMMC_D0/GPIO199

B8

NAND_AD5/EMMC_D3/GPIO198

C8

NAND_AD6/EMMC_D4/GPIO197

B9

NAND_AD7/EMMC_D5/GPIO227

AM4

PCM2_CD/GPIO123

AP4

PCM2_CE/GPIO119

AL5

PCM2_IRQA/GPIO120

AN4

PCM2_WAIT/GPIO121

AL4

PCM2_RESET/GPIO122

IC100

LGE5331(LM15U)

TS2DATA_[7]/VSENSE/GPIO210

TS1DATA_[0]/GPIO187
TS1DATA_[1]/GPIO186
TS1DATA_[2]/GPIO185
TS1DATA_[3]/GPIO184
TS1DATA_[4]/GPIO183
TS1DATA_[5]/GPIO182
TS1DATA_[6]/GPIO181
TS1DATA_[7]/GPIO180

TS1CLK/GPIO177

TS1VALID/GPIO179

TS1SYNC/GPIO178

TS0DATA_[0]/GPIO166
TS0DATA_[1]/GPIO167
TS0DATA_[2]/GPIO168
TS0DATA_[3]/GPIO169
TS0DATA_[4]/GPIO170
TS0DATA_[5]/GPIO171
TS0DATA_[6]/GPIO172
TS0DATA_[7]/GPIO173

TS0CLK/GPIO176

TS0VALID/GPIO174

TS0SYNC/GPIO175

TS2DATA_[0]/GPIO200
TS2DATA_[1]/GPIO204
TS2DATA_[2]/GPIO205
TS2DATA_[3]/GPIO206
TS2DATA_[4]/GPIO207
TS2DATA_[5]/GPIO208
TS2DATA_[6]/GPIO209

TS2CLK/GPIO203

TS2VALID/GPIO201

TS2SYNC/GPIO202

TS3DATA_[0]/GPIO211
TS3DATA_[1]/GPIO212
TS3DATA_[2]/GPIO213
TS3DATA_[3]/GPIO214
TS3DATA_[4]/GPIO215
TS3DATA_[5]/GPIO216
TS3DATA_[6]/GPIO217
TS3DATA_[7]/GPIO218

TS3CLK/GPIO221

TS3VALID/GPIO219

TS3SYNC/GPIO220

VIFP
VIFM

SIFP
SIFM

IF_AGC

TGPIO0/GPIO162
TGPIO1/GPIO163
TGPIO2/GPIO164
TGPIO3/GPIO165

AL6
AM6
AP8
AN7
AM5
AM7
AN5
AN6
AL7
AP5
AP6

AP10
AN10
AM8
AM10
AM11
AM12
AN8
AM9
AN11
AN9
AP9

AM14
AP15
AN12
AN15
AN14
AM16
AN13
AM15
AP13
AP12
AM13

AM18
AP16
AM19
AN18
AP19
AN20
AP18
AN19
AN17
AM17
AN16

AP1
AP2

AN2
AN1

AP3

AR2
AM2
AK5
AK6

/USB_OCD1
USB_CTL1

I2C_SCL7
I2C_SDA7

TPO_DATA[0]
TPO_DATA[1]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[6]
TPO_DATA[7]

TPO_CLK
TPO_VAL
TPO_SOP

TPI_CLK
TPI_VAL
TPI_SOP

FE_DEMOD1_TS_DATA[0]
FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[5]

FE_DEMOD1_TS_DATA[6]
FE_DEMOD1_TS_DATA[7]

FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_SYNC

FE_DEMOD3_TS_DATA

FE_DEMOD3_TS_CLK
FE_DEMOD3_TS_VAL
FE_DEMOD3_TS_SYNC

TPI_DATA[0-7]

TPI_DATA[0]

TPI_DATA[1]
TPI_DATA[2]
TPI_DATA[3]
TPI_DATA[4]
TPI_DATA[5]
TPI_DATA[6]
TPI_DATA[7]

TPI_DATA[0-7]

Close to MSTAR

R140 100 C118 0.1uF

R141 100

C120 0.1uF
C121 0.1uF

ANALOG SIF

Close to MSTAR

R142
10K

TPO_DATA[0-7]

FE_DEMOD1_TS_DATA[0-7]

C119 0.1uF

R144 47

R145 47

PZ1608U121-2R0TF

R143

0

C124
1000pF
OPT

OPT
C122

100pF

R146
300

OPT

+3.3V_NORMAL

L100

C125

0.1uF

C127

0.047uF
25V

OPT
C123
33pF

DTV_IF

IF_P

IF_N

OPT
C126
33pF

TU_SIF

IF_AGC

Mstart Debug

MSTAR_DEBUG_OLD

MSTAR_DEBUG_NEW

P101

12507WS-04L

1

2

DDCA_CK

3

DDCA_DA

4

5

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

P103

12505WS-04A00

1

2

3

4

5

RS232C_Debug

UART_4PIN_WAFER

P102

12507WS-04L

5

+3.5V_ST

1

2

3

4

OPT

R147

1.8K

R148

1.8K

+3.3V_LNA_TU

+3.3V_NORMAL

R128

1.8K

R129

1.8K

R127

1.8K

I2C_SDA_MICOM
I2C_SCL_MICOM

R130

1.8K

+3.3V_TU

R100 10K

SOC_RX

OPT

R101 10K

SOC_TX

I2C PULL UP

R133

1.8K

R134

1.8K

R135

1.8K

AR101
33

R136

1.8K

R106

1.8K

R125

1.8K

I2C_SDA3
I2C_SCL3

R132

1.8K

R139

1.8K

I2C_SDA7
I2C_SCL7

I2C_SDA6
I2C_SCL6
I2C_SDA1
I2C_SCL1
I2C_SDA3
I2C_SCL3

I2C_SDA4
I2C_SCL4

I2C_SDA5
I2C_SCL5

I2C_SDA2
I2C_SCL2

I2C for URSA9 (URSA9 Only)

I2C for LCD Module

I2C for NAVRAM

I2C for Micom

I2C for Main Amp / Woofer AMP

I2C for tuner

I2C for tuner&LNB

GPIO PULL UP

+3.3V_NORMAL

OPT

R171 10K

R149 10K

R153 10K

R151 10K

R152 10K

R150 10K

OPT

R160 10K

R169 10K

R154 10K

R170 10K

/TU_RESET1
RF_SWITCH_CTL
AMP_RESET_N

TCON_I2C_EN

/USB_OCD1

USB_CTL1

/USB_OCD2

USB_CTL2

M_RFModule_RESET

PCM_5V_CTL

DDTS_Debug

DDTS_Debug

P100

12507WS-04L

5

+3.3V_NORMAL

1

2

3

4

OPT

R102 10K

DDTS_RX

OPT

R105 10K

DDTS_TX

2015-02-26LM15U

MAIN1_SYSTEM

1

DVDD_NODIE

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

C200

1uF
25V

VDDC15_M0

DVDD_DDR11

+1.1V_VDDC_CPU

+1.1V_VDDC

AVDDL_MOD11

DVDD_DDR11

AF18
AF19
AF20
AG18
AG19
AG20
AG21
AG22
AH18
AH19
AH20
AH21
AH22

AF14
AF15

AA21
AA27
AA28
AA29
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD27
AD28
AD29
AD30

AF24

AF25

L10
L11
L12
L13
L14
M10
M11
M12
M13
M14
N10
N11
N12
N13
V12
V13
V14
W12
W13
W14
Y12
Y13
Y14

W23
Y23
W24
Y24
Y25
Y26

N14

R22
R24

P22
T24

LGE5331(LM15U)

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36

AVDDL_PREDRV_1
AVDDL_PREDRV_2
AVDDL_MOD_1
AVDDL_MOD_2
AVDD15_MOD_1
AVDD15_MOD_2

AVDDL_USB3_1
AVDDL_USB3_2

VDDC_CPU_1
VDDC_CPU_2
VDDC_CPU_3
VDDC_CPU_4
VDDC_CPU_5
VDDC_CPU_6
VDDC_CPU_7
VDDC_CPU_8
VDDC_CPU_9
VDDC_CPU_10
VDDC_CPU_11
VDDC_CPU_12
VDDC_CPU_13
VDDC_CPU_14
VDDC_CPU_15
VDDC_CPU_16
VDDC_CPU_17
VDDC_CPU_18
VDDC_CPU_19
VDDC_CPU_20
VDDC_CPU_21
VDDC_CPU_22
VDDC_CPU_23
VDDC_CPU_24
VDDC_CPU_25
VDDC_CPU_26
VDDC_CPU_27

DVDD_NODIE

DVDD_DDR_1
DVDD_DDR_2
DVDD_DDR_C
DVDD_DDR_RX_A
DVDD_DDR_RX_B
DVDD_DDR_RX_C

IC100

AVDD_NODIE

AVDDL_MHL3_1

AVDDL_MHL3_2
AVDD3P3_MHL3_1
AVDD3P3_MHL3_2

AVDD3P3_ETH
AVDD3P3_DADC_1
AVDD3P3_DADC_2

AVDD3P3_ADC_1
AVDD3P3_ADC_2
AVDD3P3_USB_1

AVDD3P3_USB_2
AVDD3P3_USB3_1
AVDD3P3_USB3_2

AVDD_AU33

AVDD_EAR33

AVDD3P3_DMPLL

VDDP_1
VDDP_2

AVDD_MOD_1

AVDD_MOD_2
AVDD_LPLL_1
AVDD_LPLL_2

AVDD_PLL_A

AVDD_PLL_B

AVDD_PLL_C

VDDP_3318_A_CAP
VDDP_3318_C_CAP

VDDP_3318_A
VDDP_3318_C

AVDD_DDR_A_CMD_1
AVDD_DDR_A_CMD_2

AVDD_DDR_A_MCK
AVDD_DDR_A_DAT_1
AVDD_DDR_A_DAT_2
AVDD_DDR_A_DAT_3
AVDD_DDR_A_DAT_4
AVDD_DDR_B_CMD_1
AVDD_DDR_B_CMD_2

AVDD_DDR_B_MCK
AVDD_DDR_B_DAT_1
AVDD_DDR_B_DAT_3
AVDD_DDR_B_DAT_4
AVDD_DDR_B_DAT_2
AVDD_DDR_C_CMD_1
AVDD_DDR_C_CMD_2

AVDD_DDR_C_MCK
AVDD_DDR_C_DAT_1
AVDD_DDR_C_DAT_2
AVDD_DDR_C_DAT_3
AVDD_DDR_C_DAT_4

AVDD_DDR_LDO_A

AVDD_DDR_LDO_B

AVDD_DDR_LDO_C

AVDD_HDMI_5V_PA
AVDD_HDMI_5V_PC

GND_EFUSE

AVDD_DDR_VBP_A_1
AVDD_DDR_VBP_A_2

AVDD_DDR_VBN_A_1
AVDD_DDR_VBN_A_2

AVDD_DDR_VBP_B_1
AVDD_DDR_VBP_B_2

AVDD_DDR_VBN_B_1
AVDD_DDR_VBN_B_2

AVDD_DDR_VBP_C_1
AVDD_DDR_VBP_C_2

AVDD_DDR_VBN_C_1
AVDD_DDR_VBN_C_2

V7

T13
T14
L8
M8

W7
AD7
AD8
Y7
Y8
AL10
AL11
AH14
AH15
AH7
AG7
AL12
AK15
AL15

W26
Y27
Y28
Y29

U18
U19
AL18

L17
L15
G8
H7

M20
M21
N21
M22
N22
N23
N24
N25
N26
P25
R25
T25
U25
R26
AE25
AE26
AF26
AE22
AE23
AE24
AF22

N20
P24
AD25

U7
P7

P8

L20
L21

M24
M25

U27
V27

U26
V26

AD21
AD22

AD23
AD24

DVDD_DDR11

AVDD33

VDDC15_M0

VDDC15_M1

OPT

OPT

OPT

OPT

OPT

OPT

AVDD_AU33

AVDD_PLL33

VDDP_NAND

VDDC15_M1

VDDC15_M0

AVDD5V_MHL

VDDC15_M0

C2100.47uF
C2270.47uF

C2110.47uF
C2290.47uF

C2120.47uF
C2300.47uF

C2130.47uF

VDDC15_M1

C2310.47uF

C2140.47uF
C2340.47uF

C2150.47uF
C2400.47uF

AVDD33

AVDD_3P3

4.7uF

C219

C216

0.1uF

C220

4.7uF

C221

0.1uF

WOL POWER ENABLE CONTROL

+3.5V_ST

PZ1608U121-2R0TF

L204

+3.3V_NORMAL

C239

0.1uF

WOL_CTL

+3.5V_WOL

R201
1K
OPT

R2020

+3.5V_WOL

1st layer

C237
10uF
10V

C233 0.1uF

Close to chip side

C205

0.1uF
16V

IC200

AP2151WG-7

IN

5

EN

4

IC201

AP2121N-3.3TRE1

VIN

3

1

2

3

0.1uF

C250

Close to chip side

VOUT

2

1

GND

+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)

+1.1V_VDDC

L226

+3.5V_WOL

OUT

GND

FLG

AVDD_3P3

4th layer

0.1uF

C249

AVDD_3P3

C206
1uF
10V

+1.1V_VDDC

+1.1V_VDDC_CPU

C228

0.1uF

10uF
10V

C232

C235

C261

0.1uF

10uF
10V

C277

C275

1st layer

C263

0.1uF

10uF
10V

C276

C278

Close to chip side

0.1uF

0.1uF

0.1uF

L202

PZ1608U121-2R0TF

2A

AVDDL_MOD11

C264
10uF
10V

C285

0.1uF

C265

0.1uF

PZ1608U121-2R0TF

2A

4th layer

0.1uF

C320

Close to chip side

4th layer

10uF

C322

Close to chip side

C323
10uF
10V

C271
10uF
10V

DVDD_DDR11

0.1uF

C306

C310

0.1uF

4th layer

0.1uF

C324

Close to chip side

+3.3V_Bypass Cap

AVDD_PLL33

L215

PZ1608U121-2R0TF

2A

C256
10uF
10V

1st layer

0.1uF

C274

0.1uF

C286

4th layer

0.47uF

C311

0.47uF

C241

5V_HDMI_3

R200

10

AVDD5V_MHL

+3.3V_NORMAL

C222
10uF
10V

+1.5V_DDR

PZ1608U121-2R0TF

PZ1608U121-2R0TF

PZ1608U121-2R0TF

+1.5V_Bypass Cap

VDDC15_M0

L227

L200

C207

2A

10uF
10V

C209 0.1uF

VDDC15_M1

L201

C208

2A

10uF
10V

C218 0.1uF

1st layer

C201
10uF
10V

Close to chip side

1st layer

C202
10uF
10V

Close to chip side

C203 0.1uF C224 0.1uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C225 0.1uF

C204 0.1uF

C226 0.1uF

Close to chip side

C287 0.1uF

Close to chip side

4th layer

0.47uF

C314

4th layer

C315

0.47uF

C316
10uF
10V

C317
10uF
10V

C223
10uF
10V

C242
10uF
10V

FOR_EMI

C325
20pF
50V

VDDC15_M1

FOR_EMI

C326
20pF
50V

FOR_EMI
C327
20pF
50V

+3.3V_NORMAL

+1.8V

GND JIG POINT

OPT

L222

PZ1608U121-2R0TF

2A

L223

PZ1608U121-2R0TF

2A

JP202

JP204

JP203

JP205

VDDP_NAND

C302
10uF
10V

C304

0.1uF

L203

PZ1608U121-2R0TF

2A

L212

PZ1608U121-2R0TF

2A

Close to chip side

AVDD33

C217
10uF
10V

C238 0.1uF

C244 0.1uF

AVDD_AU33

0.1uF

C236
10uF
10V

C243

LM15U

MAIN2_POWER

0.1uF

C252

Close to chip side

4th layer

0.1uF

C251

C245 0.47uF

Close to chip side

4th layer

0.1uF

C253

Close to chip side

2014-11-26

2

IC100

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

LGE5331(LM15U)

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1

M0_DDR_BA2
M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN
M0_DDR_ODT
M0_DDR_CKE

M0_DDR_RESET_N_1

M0_D_CLK

M0_D_CLKN

M0_DDR_CS1
M0_DDR_CS2

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DM0

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQ8

M0_DDR_DQ9
M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

M0_DDR_DM1
M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23

M0_DDR_DM2
M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

M0_DDR_DM3
M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_RESET_N_1

F21

A_A0

C21

A_A1

E21

A_A2

F22

A_A3

B22

A_A4

E22

A_A5

A21

A_A6

D21

A_A7

C20

A_A8

E20

A_A9

B23

A_A10

B21

A_A11

D24

A_A12

F20

A_A13

B20

A_A14

E24

A_A15

E23

A_BA0

C22

A_BA1

F23

A_BA2

G26

A_RASZ

F25

A_CASZ

E25

A_WEZ

F24

A_ODT

C23

A_CKE

F19

A_RST

A24

A_MCLK

B24

A_MCLKZ

E19

A_CSB1

D19

A_CSB2

C27

A_DQ[0]

B26

A_DQ[1]

B28

A_DQ[2]

C25

A_DQ[3]

B29

A_DQ[4]

C24

A_DQ[5]

C28

A_DQ[6]

B25

A_DQ[7]

C26

A_DQM[0]

A27

A_DQS[0]

B27

A_DQSB[0]

D27

A_DQ[8]/DQU0

D30

A_DQ[9]/DQU1

E26

A_DQ[10]/DQU2

D31

A_DQ[11]/DQU3

F27

A_DQ[12]/DQU4

E30

A_DQ[13]/DQU5

D26

A_DQ[14]/DQU6

E29

A_DQ[15]/DQU7

E28

A_DQM[1]

D28

A_DQS[1]

E27

A_DQSB[1]

C32

A_DQ[16]/DQL0

C30

A_DQ[17]/DQL1

B33

A_DQ[18]/DQL2

A30

A_DQ[19]/DQL3

C33

A_DQ[20]/DQL4

C29

A_DQ[21]/DQL5

A33

A_DQ[22]/DQL6

B30

A_DQ[23]/DQL7

B31

A_DQM[2]

B32

A_DQS[2]

C31

A_DQSB[2]

E33

A_DQ[24]/DQU0

C35

A_DQ[25]/DQU1

E31

A_DQ[26]/DQU2

D35

A_DQ[27]/DQU3

D33

A_DQ[28]/DQU4

D34

A_DQ[29]/DQU5

E32

A_DQ[30]/DQU6

C34

A_DQ[31]/DQU7

B35

A_DQM[3]

A35

A_DQS[3]

B34

A_DQSB[3]

OPT

R4400

M0_DDR_RESET_N

C

R434

NXP_DDR_RES0_TR

1K

Q400

B

MMBT3904(NXP)

B

M1_DDR_RESET_N_1

C

KEC_DDR_RES0_TR
Q400-*1
2N3904S

E

E

R435

10K

M2_DDR_RESET_N_1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

B_A10
B_A11
B_A12
B_A13
B_A14
B_A15
B_BA0
B_BA1

B_BA2
B_RASZ
B_CASZ

B_WEZ

B_ODT

B_CKE

B_RST
B_MCLK

B_MCLKZ

B_CSB1
B_CSB2

B_DQ[0]
B_DQ[1]
B_DQ[2]
B_DQ[3]
B_DQ[4]
B_DQ[5]
B_DQ[6]

B_DQ[7]
B_DQM[0]
B_DQS[0]

B_DQSB[0]

B_DQ[8]/DQU0

B_DQ[9]/DQU1
B_DQ[10]/DQU2
B_DQ[11]/DQU3
B_DQ[12]/DQU4
B_DQ[13]/DQU5
B_DQ[14]/DQU6
B_DQ[15]/DQU7

B_DQM[1]
B_DQS[1]

B_DQSB[1]

B_DQ[16]/DQL0
B_DQ[17]/DQL1
B_DQ[18]/DQL2
B_DQ[19]/DQL3
B_DQ[20]/DQL4
B_DQ[21]/DQL5
B_DQ[22]/DQL6
B_DQ[23]/DQL7

B_DQM[2]
B_DQS[2]

B_DQSB[2]

B_DQ[24]/DQU0
B_DQ[25]/DQU1
B_DQ[26]/DQU2
B_DQ[27]/DQU3
B_DQ[28]/DQU4
B_DQ[29]/DQU5
B_DQ[30]/DQU6
B_DQ[31]/DQU7

B_DQM[3]
B_DQS[3]

B_DQSB[3]

C_A10
C_A11
C_A12
C_A13
C_A14
C_A15
C_BA0
C_BA1

C_BA2
C_RASZ
C_CASZ

C_WEZ

C_ODT

C_CKE

C_RST
C_MCLK

C_MCLKZ

C_CSB1
C_CSB2

C_DQ[0]
C_DQ[1]
C_DQ[2]
C_DQ[3]
C_DQ[4]
C_DQ[5]
C_DQ[6]

C_DQ[7]
C_DQM[0]
C_DQS[0]

C_DQSB[0]

C_DQ[8]/DQU0

C_DQ[9]/DQU1
C_DQ[10]/DQU2
C_DQ[11]/DQU3
C_DQ[12]/DQU4
C_DQ[13]/DQU5
C_DQ[14]/DQU6
C_DQ[15]/DQU7

C_DQM[1]
C_DQS[1]

C_DQSB[1]

C_DQ[16]/DQL0
C_DQ[17]/DQL1
C_DQ[18]/DQL2
C_DQ[19]/DQL3
C_DQ[20]/DQL4
C_DQ[21]/DQL5
C_DQ[22]/DQL6
C_DQ[23]/DQL7

C_DQM[2]
C_DQS[2]

C_DQSB[2]

C_DQ[24]/DQU0
C_DQ[25]/DQU1
C_DQ[26]/DQU2
C_DQ[27]/DQU3
C_DQ[28]/DQU4
C_DQ[29]/DQU5
C_DQ[30]/DQU6
C_DQ[31]/DQU7

C_DQM[3]
C_DQS[3]

C_DQSB[3]

G33

B_A0

J36

B_A1

H34

B_A2

J32

B_A3

J35

B_A4

H33

B_A5

J37

B_A6

G36

B_A7

H37

B_A8

F35

B_A9

K35
H35
K34
F36
H36
L33
K33
K36
J33
M33
M32
K32
L32
L36
F37
M37
L35
F34
E37

R36
N35
R35
N36
T35
M36
T36
M35
P36
R37
P35

N32
T34
N33
T32
P33
U33
N34
T33
R33
R32
P32

Y36
V36
Y35
V37
AA36
U36
AA37
U35
V35
W35
W36

W33
AA32
U32
AA34
V33
AA33
V32
Y32
W32
Y33
W34

AM34

C_A0

AR35

C_A1

AP34

C_A2

AM33

C_A3

AT34

C_A4

AN33

C_A5

AU35

C_A6

AR36

C_A7

AU36

C_A8

AR37

C_A9

AT33
AT35
AP31
AP35
AT37
AN31
AN32
AR34
AM32
AM29
AM30
AN30
AM31
AR33
AP37
AU32
AT32
AN34
AP36

AR29
AT30
AT28
AR31
AT27
AR32
AR28
AT31
AR30
AU29
AT29

AN27
AP25
AN29
AN24
AN28
AN25
AP28
AN26
AM26
AM27
AM28

AR24
AR26
AT23
AU26
AR23
AR27
AU23
AT26
AT25
AT24
AR25

AN23
AN21
AM25
AM21
AM23
AM22
AM24
AT22
AR22
AP21
AP22

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8
M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15
M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2
M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN
M1_DDR_ODT
M1_DDR_CKE
M1_DDR_RESET_N_1
M1_D_CLK
M1_D_CLKN
M1_DDR_CS1
M1_DDR_CS2

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DM0
M1_DDR_DQS0
M1_DDR_DQS_N0

M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15
M1_DDR_DM1
M1_DDR_DQS1
M1_DDR_DQS_N1

M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23
M1_DDR_DM2
M1_DDR_DQS2
M1_DDR_DQS_N2

M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31
M1_DDR_DM3
M1_DDR_DQS3
M1_DDR_DQS_N3

M2_DDR_A0
M2_DDR_A1
M2_DDR_A2
M2_DDR_A3
M2_DDR_A4
M2_DDR_A5
M2_DDR_A6
M2_DDR_A7
M2_DDR_A8
M2_DDR_A9
M2_DDR_A10
M2_DDR_A11
M2_DDR_A12
M2_DDR_A13
M2_DDR_A14
M2_DDR_A15
M2_DDR_BA0
M2_DDR_BA1
M2_DDR_BA2
M2_DDR_RASN
M2_DDR_CASN
M2_DDR_WEN
M2_DDR_ODT
M2_DDR_CKE
M2_DDR_RESET_N_1
M2_D_CLK
M2_D_CLKN
M2_DDR_CS1
M2_DDR_CS2

M2_DDR_DQ0
M2_DDR_DQ1
M2_DDR_DQ2
M2_DDR_DQ3
M2_DDR_DQ4
M2_DDR_DQ5
M2_DDR_DQ6
M2_DDR_DQ7
M2_DDR_DM0
M2_DDR_DQS0
M2_DDR_DQS_N0

M2_DDR_DQ8
M2_DDR_DQ9
M2_DDR_DQ10
M2_DDR_DQ11
M2_DDR_DQ12
M2_DDR_DQ13
M2_DDR_DQ14
M2_DDR_DQ15
M2_DDR_DM1
M2_DDR_DQS1
M2_DDR_DQS_N1

M2_DDR_DQ16
M2_DDR_DQ17
M2_DDR_DQ18
M2_DDR_DQ19
M2_DDR_DQ20
M2_DDR_DQ21
M2_DDR_DQ22
M2_DDR_DQ23
M2_DDR_DM2
M2_DDR_DQS2
M2_DDR_DQS_N2

M2_DDR_DQ24
M2_DDR_DQ25
M2_DDR_DQ26
M2_DDR_DQ27
M2_DDR_DQ28
M2_DDR_DQ29
M2_DDR_DQ30
M2_DDR_DQ31
M2_DDR_DM3
M2_DDR_DQS3
M2_DDR_DQS_N3

OPT

R4410

M1_DDR_RESET_N

C

R436

NXP_DDR_RES1_TR

1K

Q401

B

MMBT3904(NXP)

E

R437

10K

OPT

R4420

M2_DDR_RESET_N

C

R438

NXP_DDR_RES2_TR

1K

B

Q402
MMBT3904(NXP)

E

R439

10K

B

B

C

KEC_DDR_RES1_TR
Q401-*1
2N3904S

E

C

KEC_DDR_RES2_TR
Q402-*1
2N3904S

E

M0_DDR_RESET_N

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DM0
M0_DDR_DM1

M2_DDR_RESET_N

M2_DDR_DQS0

M2_DDR_DQS_N0

M2_DDR_DQS1

M2_DDR_DQS_N1

M2_DDR_DM0
M2_DDR_DM1

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

M2_DDR_A10
M2_DDR_A11
M2_DDR_A12
M2_DDR_A13
M2_DDR_A14
M2_DDR_A15

M2_DDR_BA0
M2_DDR_BA1
M2_DDR_BA2

M2_DDR_CKE

M2_DDR_CS1

M2_DDR_ODT
M2_DDR_RASN
M2_DDR_CASN

M2_DDR_WEN

M2_DDR_DQ0

M2_DDR_DQ1

M2_DDR_DQ2

M2_DDR_DQ3

M2_DDR_DQ4

M2_DDR_DQ5

M2_DDR_DQ6

M2_DDR_DQ7

M2_DDR_DQ8

M2_DDR_DQ9
M2_DDR_DQ10
M2_DDR_DQ11
M2_DDR_DQ12
M2_DDR_DQ13
M2_DDR_DQ14
M2_DDR_DQ15

Hynix_DDR3_4Gb_29n

H5TQ4G63AFR-RDC

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_D_CLK

M0_D_CLKN
M0_DDR_CKE

M0_DDR_CS1
M0_DDR_ODT

M0_DDR_WEN

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7

M0_DDR_DQ8
M0_DDR_DQ9

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap
Close to DDR Power Pin

VDDC15_M0

C402 0.1uF

C400 0.1uF

C401 0.1uF

Hynix_DDR3_4Gb_29n

H5TQ4G63AFR-RDC

M2_DDR_A0

M2_DDR_A1

M2_DDR_A2

M2_DDR_A3

M2_DDR_A4

M2_DDR_A5

M2_DDR_A6

M2_DDR_A7

M2_DDR_A8

M2_DDR_A9

M2_D_CLK

M2_D_CLKN

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap
Close to DDR Power Pin

VDDC15_M1

C493 0.1uF

C492 0.1uF

C482 0.1uF

IC400

EAN63053201

DDR3
4Gbit
(x16)

IC405

EAN63053201

DDR3
4Gbit
(x16)

VREFCA

VREFDQ

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

NC_1
NC_2
NC_3
NC_4

M0_DDR_VREFDQ

M8

H1

L8

R400

ZQ

VDDC15_M0

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C410

0.1uF

C411

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

IC400-*1

IC400-*2

K4B4G1646D-BCMA

H5TQ4G63CFR_RDC

M8

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

N3

VREFCA

VREFCA

A0

P7

A1

P3

A2

H1

N2

H1

VREFDQ

A3

VREFDQ

P8

A4

P2

A5

R8

L8

L8

A6

ZQ

ZQ

R2

A7

T8

A8

R3

B2

B2

A9

VDD_1

VDD_1

L7

D9

D9

A10/AP

VDD_2

VDD_2

R7

G7

G7

A11

VDD_3

VDD_3

K2

N7

K2

A12/BC

VDD_4

VDD_4

K8

T3

K8

VDD_5

A13

VDD_5

T7

N1

N1

A14

VDD_6

VDD_6

N9

N9

M7

VDD_7

VDD_7

NC_5

R1

R1

VDD_8

VDD_8

R9

R9

M2

VDD_9

VDD_9

BA0

N8

BA1

M3

BA2

A1

A1

VDDQ_1

VDDQ_1

A8

A8

J7

VDDQ_2

VDDQ_2

CK

C1

C1

K7

VDDQ_3

VDDQ_3

CK

C9

C9

K9

VDDQ_4

VDDQ_4

CKE

D2

D2

VDDQ_5

VDDQ_5

E9

E9

L2

VDDQ_6

VDDQ_6

CS

F1

F1

K1

VDDQ_7

VDDQ_7

ODT

H2

H2

J3

VDDQ_8

VDDQ_8

RAS

H9

H9

K3

VDDQ_9

VDDQ_9

CAS

L3

WE

J1

J1

NC_1

NC_1

J9

J9

T2

NC_2

NC_2

RESET

L1

L1

NC_3

NC_3

L9

L9

NC_4

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

A9

C7

VSS_1

VSS_1

DQSU

B3

B3

B7

VSS_2

VSS_2

DQSU

E1

E1

VSS_3

VSS_3

G8

G8

E7

VSS_4

VSS_4

DML

J2

J2

D3

VSS_5

VSS_5

DMU

J8

J8

VSS_6

VSS_6

M1

M1

E3

VSS_7

VSS_7

DQL0

M9

M9

F7

VSS_8

VSS_8

DQL1

P1

P1

F2

VSS_9

VSS_9

DQL2

P9

P9

F8

VSS_10

VSS_10

DQL3

T1

T1

H3

VSS_11

VSS_11

DQL4

T9

T9

H8

VSS_12

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

B1

VSSQ_1

VSSQ_1

B9

B9

D7

VSSQ_2

VSSQ_2

DQU0

D1

D1

C3

VSSQ_3

VSSQ_3

DQU1

D8

D8

C8

VSSQ_4

VSSQ_4

DQU2

E2

E2

C2

VSSQ_5

VSSQ_5

DQU3

E8

E8

A7

VSSQ_6

VSSQ_6

DQU4

F9

F9

A2

VSSQ_7

VSSQ_7

DQU5

G1

G1

B8

VSSQ_8

VSSQ_8

DQU6

G9

G9

A3

VSSQ_9

VSSQ_9

DQU7

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_D_CLK

M0_D_CLKN
M0_DDR_CKE

M0_DDR_CS2
M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_DM2
M0_DDR_DM3

M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23

M0_DDR_DQ24

M0_DDR_DQ25

M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

VDDC15_M0

M2_DDR_VREFDQ

M8

H1

L8

R406

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3

M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

C502
C503

SS_DDR3_4Gb_25n

K4B4G1646D-BCMA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13

NC_5

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

240

0.1uF

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

Hynix_DDR3_4Gb_25n

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

H5TQ4G63CFR_RDC

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
NC_5

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

SS_DDR3_2Gb

IC405-*2

IC405-*3

K4B2G1646Q-BCMA

M8

M8

N3

VREFCA

VREFCA

A0

P7

A1

P3

A2

H1

H1

N2

VREFDQ

VREFDQ

A3

P8

A4

P2

A5

L8

R8

L8

ZQ

A6

ZQ

R2

A7

T8

A8

R3

B2

B2

A9

VDD_1

VDD_1

L7

D9

D9

A10/AP

VDD_2

VDD_2

R7

G7

G7

A11

VDD_3

VDD_3

K2

K2

N7

A12/BC

VDD_4

VDD_4

K8

K8

T3

VDD_5

VDD_5

A13

N1

N1

VDD_6

VDD_6

N9

N9

M7

VDD_7

VDD_7

NC_5

R1

R1

VDD_8

VDD_8

R9

R9

M2

VDD_9

VDD_9

BA0

N8

BA1

M3

BA2

A1

A1

VDDQ_1

VDDQ_1

A8

A8

J7

VDDQ_2

VDDQ_2

CK

C1

C1

K7

VDDQ_3

VDDQ_3

CK

C9

C9

K9

VDDQ_4

VDDQ_4

CKE

D2

D2

VDDQ_5

VDDQ_5

E9

E9

L2

VDDQ_6

VDDQ_6

CS

F1

F1

K1

VDDQ_7

VDDQ_7

ODT

H2

H2

J3

VDDQ_8

VDDQ_8

RAS

H9

H9

K3

VDDQ_9

VDDQ_9

CAS

L3

WE

J1

J1

NC_1

NC_1

J9

J9

T2

NC_2

NC_2

RESET

L1

L1

NC_3

NC_3

L9

L9

NC_4

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

A9

C7

VSS_1

VSS_1

DQSU

B3

B3

B7

VSS_2

VSS_2

DQSU

E1

E1

VSS_3

VSS_3

G8

G8

E7

VSS_4

VSS_4

DML

J2

J2

D3

VSS_5

VSS_5

DMU

J8

J8

VSS_6

VSS_6

M1

M1

E3

VSS_7

VSS_7

DQL0

M9

M9

F7

VSS_8

VSS_8

DQL1

P1

P1

F2

VSS_9

VSS_9

DQL2

P9

P9

F8

VSS_10

VSS_10

DQL3

T1

T1

H3

VSS_11

VSS_11

DQL4

T9

T9

H8

VSS_12

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

B1

VSSQ_1

VSSQ_1

B9

B9

D7

VSSQ_2

VSSQ_2

DQU0

D1

D1

C3

VSSQ_3

VSSQ_3

DQU1

D8

D8

C8

VSSQ_4

VSSQ_4

DQU2

E2

E2

C2

VSSQ_5

VSSQ_5

DQU3

E8

E8

A7

VSSQ_6

VSSQ_6

DQU4

F9

F9

A2

VSSQ_7

VSSQ_7

DQU5

G1

G1

B8

VSSQ_8

VSSQ_8

DQU6

G9

G9

A3

VSSQ_9

VSSQ_9

DQU7

IC405-*1

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

ZQ

VDDC15_M1

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

Hynix_DDR3_2Gb

IC405-*4

H5TQ2G63FFR-RDC

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
NC_5

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

M2_DDR_A0
M2_DDR_A1
M2_DDR_A2
M2_DDR_A3
M2_DDR_A4
M2_DDR_A5
M2_DDR_A6
M2_DDR_A7
M2_DDR_A8

M2_DDR_A9
M2_DDR_A10
M2_DDR_A11
M2_DDR_A12
M2_DDR_A13
M2_DDR_A14
M2_DDR_A15

M2_DDR_BA0
M2_DDR_BA1
M2_DDR_BA2

M2_D_CLK

M2_D_CLKN
M2_DDR_CKE

M2_DDR_CS2
M2_DDR_ODT

M2_DDR_RASN
M2_DDR_CASN

M2_DDR_WEN

M2_DDR_RESET_N

M2_DDR_DQS2

M2_DDR_DQS_N2

M2_DDR_DQS3

M2_DDR_DQS_N3

M2_DDR_DM2
M2_DDR_DM3

M2_DDR_DQ16
M2_DDR_DQ17
M2_DDR_DQ18
M2_DDR_DQ19
M2_DDR_DQ20
M2_DDR_DQ21
M2_DDR_DQ22
M2_DDR_DQ23

M2_DDR_DQ24
M2_DDR_DQ25
M2_DDR_DQ26
M2_DDR_DQ27
M2_DDR_DQ28
M2_DDR_DQ29
M2_DDR_DQ30
M2_DDR_DQ31

VDDC15_M1

Hynix_DDR3_4Gb_29n

IC401

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap
Close to DDR Power Pin

C412 0.1uF

C413 0.1uF

C415 0.1uF

Hynix_DDR3_4Gb_29n

H5TQ4G63AFR-RDC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap
Close to DDR Power Pin

C506 0.1uF

C504 0.1uF

C505 0.1uF

4Gbit
(x16)

IC406

EAN63053201

DDR3
4Gbit
(x16)

VREFCA

VREFDQ

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

M0_1_DDR_VREFDQ

M8

H1

L8

R403

ZQ

VDDC15_M0
B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C440

0.1uF

C441

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

IC401-*1

IC401-*2

K4B4G1646D-BCMA

H5TQ4G63CFR_RDC

M8

N3

VREFCA

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

N3

VREFCA

A0

P7

A1

P3

H1

A2

VREFDQ

N2

H1

A3

VREFDQ

P8

A4

P2

L8

A5

ZQ

R8

L8

A6

ZQ

R2

A7

T8

B2

A8

VDD_1

R3

B2

D9

A9

VDD_1

VDD_2

L7

D9

G7

A10/AP

VDD_2

VDD_3

R7

G7

K2

A11

VDD_3

VDD_4

N7

K2

K8

A12/BC

VDD_4

VDD_5

T3

K8

N1

A13

VDD_5

VDD_6

T7

N1

N9

A14

VDD_6

VDD_7

N9

M7

R1

VDD_7

NC_5

VDD_8

R1

R9

VDD_8

VDD_9

R9

M2

VDD_9

BA0

N8

BA1

M3

A1

BA2

VDDQ_1

A1

A8

VDDQ_1

VDDQ_2

A8

J7

C1

VDDQ_2

CK

VDDQ_3

C1

K7

C9

VDDQ_3

CK

VDDQ_4

C9

K9

D2

VDDQ_4

CKE

VDDQ_5

D2

E9

VDDQ_5

VDDQ_6

E9

L2

F1

VDDQ_6

CS

VDDQ_7

F1

K1

H2

VDDQ_7

ODT

VDDQ_8

H2

J3

H9

VDDQ_8

RAS

VDDQ_9

H9

K3

VDDQ_9

CAS

L3

J1

WE

NC_1

J1

J9

NC_1

NC_2

J9

T2

L1

NC_2

RESET

NC_3

L1

L9

NC_3

NC_4

L9

T7

NC_4

NC_6

F3

DQSL

G3

DQSL

A9

VSS_1

A9

C7

B3

VSS_1

DQSU

VSS_2

B3

B7

E1

VSS_2

DQSU

VSS_3

E1

G8

VSS_3

VSS_4

G8

E7

J2

VSS_4

DML

VSS_5

J2

D3

J8

VSS_5

DMU

VSS_6

J8

M1

VSS_6

VSS_7

M1

E3

M9

VSS_7

DQL0

VSS_8

M9

F7

P1

VSS_8

DQL1

VSS_9

P1

F2

P9

VSS_9

DQL2

VSS_10

P9

F8

T1

VSS_10

DQL3

VSS_11

T1

H3

T9

VSS_11

DQL4

VSS_12

T9

H8

VSS_12

DQL5

G2

DQL6

H7

B1

DQL7

VSSQ_1

B1

B9

VSSQ_1

VSSQ_2

B9

D7

D1

VSSQ_2

DQU0

VSSQ_3

D1

C3

D8

VSSQ_3

DQU1

VSSQ_4

D8

C8

E2

VSSQ_4

DQU2

VSSQ_5

E2

C2

E8

VSSQ_5

DQU3

VSSQ_6

E8

A7

F9

VSSQ_6

DQU4

VSSQ_7

F9

A2

G1

VSSQ_7

DQU5

VSSQ_8

G1

B8

G9

VSSQ_8

DQU6

VSSQ_9

G9

A3

VSSQ_9

DQU7

M1_DDR_RESET_N

M1_DDR_DQS0

M1_DDR_DQS_N0

M1_DDR_DQS1

M1_DDR_DQS_N1

M1_DDR_DM0
M1_DDR_DM1

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_D_CLK

M1_D_CLKN
M1_DDR_CKE

M1_DDR_CS1
M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7

M1_DDR_DQ8
M1_DDR_DQ9

M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15

Hynix_DDR3_4Gb_29n

IC403

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap
Close to DDR Power Pin

4Gbit
(x16)

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

NC_1
NC_2
NC_3
NC_4

VDDC15_M0

C444 0.1uF

C445 0.1uF

C446 0.1uF

M2_1_DDR_VREFDQ

M8

H1

L8

R407

ZQ

VDDC15_M1
B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C514

0.1uF

C515

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

IC406-*1

IC406-*2

K4B4G1646D-BCMA

H5TQ4G63CFR_RDC

M8

VREFCA

VREFDQ

ZQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

K4B2G1646Q-BCMA

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

SS_DDR3_2Gb

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

H1

N2

VREFDQ

A3

P8

A4

P2

A5

L8

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

B2

A9

VDD_1

L7

D9

D9

A10/AP

VDD_2

R7

G7

G7

A11

VDD_3

K2

K2

N7

A12/BC

VDD_4

K8

K8

T3

VDD_5

A13

T7

N1

N1

A14

VDD_6

N9

N9

M7

VDD_7

NC_5

R1

R1

VDD_8

R9

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

A1

VDDQ_1

A8

A8

J7

VDDQ_2

CK

C1

C1

K7

VDDQ_3

CK

C9

C9

K9

VDDQ_4

CKE

D2

D2

VDDQ_5

E9

E9

L2

VDDQ_6

CS

F1

F1

K1

VDDQ_7

ODT

H2

H2

J3

VDDQ_8

RAS

H9

H9

K3

VDDQ_9

CAS

L3

WE

J1

J1

NC_1

J9

J9

T2

NC_2

RESET

L1

L1

NC_3

L9

L9

NC_4

T7

F3

DQSL

G3

DQSL

A9

A9

C7

VSS_1

DQSU

B3

B3

B7

VSS_2

DQSU

E1

E1

VSS_3

G8

G8

E7

VSS_4

DML

J2

J2

D3

VSS_5

DMU

J8

J8

VSS_6

M1

M1

E3

VSS_7

DQL0

M9

M9

F7

VSS_8

DQL1

P1

P1

F2

VSS_9

DQL2

P9

P9

F8

VSS_10

DQL3

T1

T1

H3

VSS_11

DQL4

T9

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

B1

VSSQ_1

B9

B9

D7

VSSQ_2

DQU0

D1

D1

C3

VSSQ_3

DQU1

D8

D8

C8

VSSQ_4

DQU2

E2

E2

C2

VSSQ_5

DQU3

E8

E8

A7

VSSQ_6

DQU4

F9

F9

A2

VSSQ_7

DQU5

G1

G1

B8

VSSQ_8

DQU6

G9

G9

A3

VSSQ_9

DQU7

Hynix_DDR3_2Gb

IC406-*3

IC406-*4

H5TQ2G63FFR-RDC

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

L8

R8

ZQ

A6

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_D_CLK

M1_D_CLKN
M1_DDR_CKE

M1_DDR_CS2
M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQS2

M1_DDR_DQS_N2

M1_DDR_DQS3

M1_DDR_DQS_N3

M1_DDR_DM2
M1_DDR_DM3

M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23

M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

Hynix_DDR3_4Gb_29n

IC404

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap
Close to DDR Power Pin

4Gbit
(x16)

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

NC_1
NC_2
NC_3
NC_4

VDDC15_M0

C475 0.1uF

C476 0.1uF

C480 0.1uF

M1_DDR_VREFDQ

DDR_VTT

AR400

M8

H1

L8

R404

ZQ

VDDC15_M0

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C468

0.1uF

C469

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

IC403-*1

IC403-*2

K4B4G1646D-BCMA

H5TQ4G63CFR_RDC

M8

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

N3

VREFCA

VREFCA

A0

P7

A1

P3

A2

H1

N2

H1

VREFDQ

A3

VREFDQ

P8

A4

P2

A5

R8

L8

L8

A6

ZQ

ZQ

R2

A7

T8

A8

R3

B2

B2

A9

VDD_1

VDD_1

L7

D9

D9

A10/AP

VDD_2

VDD_2

R7

G7

G7

A11

VDD_3

VDD_3

K2

N7

K2

A12/BC

VDD_4

VDD_4

K8

T3

K8

VDD_5

A13

VDD_5

T7

N1

N1

A14

VDD_6

VDD_6

N9

N9

M7

VDD_7

VDD_7

NC_5

R1

R1

VDD_8

VDD_8

R9

R9

M2

VDD_9

VDD_9

BA0

N8

BA1

M3

BA2

A1

A1

VDDQ_1

VDDQ_1

A8

A8

J7

VDDQ_2

VDDQ_2

CK

C1

C1

K7

VDDQ_3

VDDQ_3

CK

C9

C9

K9

VDDQ_4

VDDQ_4

CKE

D2

D2

VDDQ_5

VDDQ_5

E9

E9

L2

VDDQ_6

VDDQ_6

CS

F1

F1

K1

VDDQ_7

VDDQ_7

ODT

H2

H2

J3

VDDQ_8

VDDQ_8

RAS

H9

H9

K3

VDDQ_9

VDDQ_9

CAS

L3

WE

J1

J1

NC_1

NC_1

J9

J9

T2

NC_2

NC_2

RESET

L1

L1

NC_3

NC_3

L9

L9

NC_4

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

A9

C7

VSS_1

VSS_1

DQSU

B3

B3

B7

VSS_2

VSS_2

DQSU

E1

E1

VSS_3

VSS_3

G8

G8

E7

VSS_4

VSS_4

DML

J2

J2

D3

VSS_5

VSS_5

DMU

J8

J8

VSS_6

VSS_6

M1

M1

E3

VSS_7

VSS_7

DQL0

M9

M9

F7

VSS_8

VSS_8

DQL1

P1

P1

F2

VSS_9

VSS_9

DQL2

P9

P9

F8

VSS_10

VSS_10

DQL3

T1

T1

H3

VSS_11

VSS_11

DQL4

T9

T9

H8

VSS_12

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

B1

VSSQ_1

VSSQ_1

B9

B9

D7

VSSQ_2

VSSQ_2

DQU0

D1

D1

C3

VSSQ_3

VSSQ_3

DQU1

D8

D8

C8

VSSQ_4

VSSQ_4

DQU2

E2

E2

C2

VSSQ_5

VSSQ_5

DQU3

E8

E8

A7

VSSQ_6

VSSQ_6

DQU4

F9

F9

A2

VSSQ_7

VSSQ_7

DQU5

G1

G1

B8

VSSQ_8

VSSQ_8

DQU6

G9

G9

A3

VSSQ_9

VSSQ_9

DQU7

M1_1_DDR_VREFDQ

M8

H1

L8

R419

ZQ

VDDC15_M0
B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C490

0.1uF

C491

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

IC404-*1

IC404-*2

K4B4G1646D-BCMA

H5TQ4G63CFR_RDC

M8

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

N3

VREFCA

VREFCA

A0

P7

A1

P3

A2

H1

N2

H1

VREFDQ

A3

VREFDQ

P8

A4

P2

A5

R8

L8

L8

A6

ZQ

ZQ

R2

A7

T8

A8

R3

B2

B2

A9

VDD_1

VDD_1

L7

D9

D9

A10/AP

VDD_2

VDD_2

R7

G7

G7

A11

VDD_3

VDD_3

K2

N7

K2

A12/BC

VDD_4

VDD_4

K8

T3

K8

VDD_5

A13

VDD_5

T7

N1

N1

A14

VDD_6

VDD_6

N9

N9

M7

VDD_7

VDD_7

NC_5

R1

R1

VDD_8

VDD_8

R9

R9

M2

VDD_9

VDD_9

BA0

N8

BA1

M3

BA2

A1

A1

VDDQ_1

VDDQ_1

A8

A8

J7

VDDQ_2

VDDQ_2

CK

C1

C1

K7

VDDQ_3

VDDQ_3

CK

C9

C9

K9

VDDQ_4

VDDQ_4

CKE

D2

D2

VDDQ_5

VDDQ_5

E9

E9

L2

VDDQ_6

VDDQ_6

CS

F1

F1

K1

VDDQ_7

VDDQ_7

ODT

H2

H2

J3

VDDQ_8

VDDQ_8

RAS

H9

H9

K3

VDDQ_9

VDDQ_9

CAS

L3

WE

J1

J1

NC_1

NC_1

J9

J9

T2

NC_2

NC_2

RESET

L1

L1

NC_3

NC_3

L9

L9

NC_4

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

A9

C7

VSS_1

VSS_1

DQSU

B3

B3

B7

VSS_2

VSS_2

DQSU

E1

E1

VSS_3

VSS_3

G8

G8

E7

VSS_4

VSS_4

DML

J2

J2

D3

VSS_5

VSS_5

DMU

J8

J8

VSS_6

VSS_6

M1

M1

E3

VSS_7

VSS_7

DQL0

M9

M9

F7

VSS_8

VSS_8

DQL1

P1

P1

F2

VSS_9

VSS_9

DQL2

P9

P9

F8

VSS_10

VSS_10

DQL3

T1

T1

H3

VSS_11

VSS_11

DQL4

T9

T9

H8

VSS_12

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

B1

VSSQ_1

VSSQ_1

B9

B9

D7

VSSQ_2

VSSQ_2

DQU0

D1

D1

C3

VSSQ_3

VSSQ_3

DQU1

D8

D8

C8

VSSQ_4

VSSQ_4

DQU2

E2

E2

C2

VSSQ_5

VSSQ_5

DQU3

E8

E8

A7

VSSQ_6

VSSQ_6

DQU4

F9

F9

A2

VSSQ_7

VSSQ_7

DQU5

G1

G1

B8

VSSQ_8

VSSQ_8

DQU6

G9

G9

A3

VSSQ_9

VSSQ_9

DQU7

* DDR_VTT

VDDC15_M0

DDR_VTT

R443
10K

1/16W
1%

L400

CIS2 1J121

C417

C414

C535

10uF

10uF

10uF

25V

25V

25V

C421
10uF
10V

1%

10K

R444

1/16W

M0_DDR_A14

M0_DDR_A8

M0_DDR_A11

M0_DDR_A6

M0_DDR_A1

M0_DDR_A4
M0_DDR_A12
M0_DDR_BA1

M0_DDR_A13

M0_DDR_A9

M0_DDR_A7

M0_DDR_A2

M0_DDR_A5

M0_DDR_A3

M0_DDR_A0

M0_DDR_BA0
M0_DDR_BA2
M0_DDR_A15
M0_DDR_A10

M0_DDR_WEN

M0_DDR_CASN

M0_DDR_ODT

M0_DDR_RASN

M0_DDR_CKE

M0_D_CLKN

M0_D_CLK

M2_DDR_A14

M2_DDR_A8

M2_DDR_A11

M2_DDR_A6

M2_DDR_A1

M2_DDR_A4
M2_DDR_A12
M2_DDR_BA1

M2_DDR_A13

M2_DDR_A9

M2_DDR_A7

M2_DDR_A2

M2_DDR_A5

M2_DDR_A3

M2_DDR_A0

M2_DDR_BA0
M2_DDR_BA2
M2_DDR_A15
M2_DDR_A10

M2_DDR_WEN

M2_DDR_CASN

M2_DDR_ODT

M2_DDR_RASN

M2_DDR_CKE

M2_D_CLKN

M2_D_CLK

AP2303MPTR-G1

VIN

GND

VREFEN

VOUT

C543

0.1uF
16V

56

AR414
56
1/16W

AR415
56
1/16W

AR416
56
1/16W

AR417
56
1/16W

AR418
56
1/16W

AR419
56
1/16W

AR420
56
1/16W

1/16W

AR401
56
1/16W

AR402
56
1/16W

AR403
56
1/16W

AR404
56
1/16W

AR405
56
1/16W

AR406
56
1/16W

DDR_VTT_1

C424 0.1uF

C425 0.1uF

C426 0.1uF

C427 0.1uF

C428 0.1uF

C429 0.1uF

C430 0.1uF

C431 0.1uF

C432 0.1uF

C433 0.1uF

C434 0.1uF

C435 0.1uF

C436 0.1uF

C437 0.1uF

C520 0.1uF

C521 0.1uF

C522 0.1uF

C523 0.1uF

C524 0.1uF

C525 0.1uF

C526 0.1uF

C527 0.1uF

C528 0.1uF

C529 0.1uF

C530 0.1uF

C531 0.1uF

C532 0.1uF

M1_DDR_A14

M1_DDR_A8

M1_DDR_A11

M1_DDR_A6

M1_DDR_A1

M1_DDR_A4
M1_DDR_A12
M1_DDR_BA1

M1_DDR_A13

M1_DDR_A9

M1_DDR_A7

M1_DDR_A2

M1_DDR_A5

M1_DDR_A3

M1_DDR_A0

M1_DDR_BA0
M1_DDR_BA2
M1_DDR_A15
M1_DDR_A10

M1_DDR_WEN

M1_DDR_CASN

M1_DDR_ODT

M1_DDR_RASN

M1_DDR_CKE

M1_D_CLKN

M1_D_CLK

VDDC15_M0

VDDC15_M0

VDDC15_M1

1K

1K

1K

C533 0.1uF

+3.3V_NORMAL

VDDC15_M0

M0_1_DDR_VREFDQ

R416

1K 1%

C479

0.1uF
C483
1000pF
50V

R417

1K 1%

VDDC15_M0

M1_1_DDR_VREFDQ

R414

1K 1%

C518

0.1uF
C519

1000pF
50V

R415

1K 1%

VDDC15_M1

C544
10uF

L401

10V

DDR_VTT_1

CIS2 1J121

C536
10uF
25V

R446
10K

L402

1/16W
1%

CIS2 1J121

C541

C542

10uF

10uF

1%

25V

25V

1/16W

VDDC15_M0

M0_DDR_VREFDQ

R410

1K 1%

C472

0.1uF
C474
1000pF

R411

50V

1K 1%

VDDC15_M0

M1_DDR_VREFDQ

R408

1K 1%

C516

0.1uF
C517
1000pF

R409

50V

1K 1%

IC402

[EP]

NC_3

1

8

NC_2

9

2

7

THERMAL

VCNTL

3

6

NC_1

4

5

LM15U

AR407
56
1/16W

AR408
56
1/16W

AR409
56
1/16W

AR410
56
1/16W

AR411
56
1/16W

AR412
56
1/16W

AR413
56
1/16W

R405

M0_DDR_RESET_N

R422

R420

C537
10uF
10V

C546

0.1uF

10K

R445

16V

M1_DDR_RESET_N

M2_DDR_RESET_N

VDDC15_M1

R425

1K 1%

R426

1K 1%

VIN

GND

VREFEN

VOUT

DDR_VTT

C453 0.1uF

C454 0.1uF

C455 0.1uF

C456 0.1uF

C457 0.1uF

C458 0.1uF

C459 0.1uF

C460 0.1uF

C461 0.1uF

C462 0.1uF

C463 0.1uF

C464 0.1uF

C465 0.1uF

C466 0.1uF

M0_DDR_CKE

R412
56
1%

R413
56
1%

M1_DDR_CKE

M2_DDR_CKE

M2_DDR_VREFDQ

C470

0.1uF
C471
1000pF
50V

IC407

AP2303MPTR-G1

1

9

2

THERMAL

3

4

C477

0.01uF
50V

R427
56
1%

R428
56
1%

R421
56
1%

R423
56
1%

[EP]

NC_3

8

NC_2

7

VCNTL

6

NC_1

5

1K

R418

M0_D_CLK

M0_D_CLKN

1K

R433

M1_D_CLK

C497

0.01uF
50V

M1_D_CLKN

1K

R424

M2_D_CLK

C534

0.01uF
50V

M2_D_CLKN

VDDC15_M1

R431

1K 1%

R432

1K 1%

+3.3V_NORMAL

2014-12-18

M2_1_DDR_VREFDQ

C473

0.1uF
C478

1000pF
50V

L403

CIS2 1J121

C545
10uF
10V

MAIN3_DDR 4

COMPENSATION_DONE_1

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

DPC_CTRL

12V_ON

OLED

TDI0

TDI0_1

R602
0

R603
0
OPT

+3.3V_NORMAL

Jtag I/F

JTAG

1K

R614

For Main

JTAG

1K

R616

TRST_N0
TDI0
TDO0
TMS0
TCK0
SOC_RESET

Clock for MSD808KWD

MAIN Clock(24Mhz)

5pF

C614

5pF

C615

System Clock for Analog block(24Mhz)

GND_1

2

3

X-TAL_2

X-TAL_1

1

4

GND_2

24MHz

X600

R635

1M

XIN_MAIN

XOUT_MAIN

C600

0.1uF

SW600

JS2235S

1

OPT

2

3

JTAG

6

5

4

R604
0

R605
0
OPT

TDO0

OPT

TDO0_1

JTAG

P600

12505WS-10A00

JTAG

11

1

2

3

4

5

6

7

8

9

10

JTAG

1K

R612

1K

JTAG

R609

MHL Port

TMS0

TDI0_1

D0-_HDMI3
D0+_HDMI3
D1-_HDMI3
D1+_HDMI3
D2-_HDMI3
D2+_HDMI3
CK-_HDMI3
CK+_HDMI3
DDC_SCL_3
DDC_SDA_3

HDMI_HPD_3

I2C_SCL5

D0-_HDMI2
D0+_HDMI2
D1-_HDMI2
D1+_HDMI2
D2-_HDMI2
D2+_HDMI2
CK-_HDMI2
CK+_HDMI2
DDC_SCL_2
DDC_SDA_2

HDMI_HPD_2

I2C_SDA5

I2C_SCL4
I2C_SDA4
CPU_VID1

CORE_VID1

D0-_HDMI1
D0+_HDMI1
D1-_HDMI1
D1+_HDMI1
D2-_HDMI1
D2+_HDMI1
CK-_HDMI1
CK+_HDMI1
DDC_SCL_1
DDC_SDA_1

HDMI_HPD_1

JTAG
R600

SPDIF_OUT

JTAG
R601

0

0

R636 0
R637 0

R607 0

R617 0

T2

RXA0N

T3

RXA0P

U2

RXA1N

U3

RXA1P

V2

RXA2N

V1

RXA2P

R3

RXACKN

T1

RXACKP

W1

DDCDA_CK/GPIO42

W2

DDCDA_DA/GPIO43

V3

HOTPLUGA/GPIO34

W3

CEC/GPIO5

N2

RXB0N

N3

RXB0P

P2

RXB1N

P3

RXB1P

R2

RXB2N

R1

RXB2P

M3

RXBCKN

N1

RXBCKP

V5

DDCDB_CK/GPIO44

V6

DDCDB_DA/GPIO45

U4

HOTPLUGB/GPIO35

W6

CEC_1/GPIO6

G2

RXC0N

G3

RXC0P

H2

RXC1N

H3

RXC1P

J2

RXC2N

J1

RXC2P

F3

RXCCKN

G1

RXCCKP

R5

DDCDC_CK/GPIO46

R6

DDCDC_DA/GPIO47

P4

HOTPLUGC/GPIO36

T6

CEC_2/GPIO7

K2

RXD0N

K3

RXD0P

L2

RXD1N

L3

RXD1P

M2

RXD2N

M1

RXD2P

J3

RXDCKN

K1

RXDCKP

T5

DDCDD_CK/GPIO48

T4

DDCDD_DA/GPIO49

U6

HOTPLUGD/GPIO37

U5

CEC_3/GPIO8

F14

SPDIF_IN/GPIO101

G14

SPDIF_OUT/GPIO102

IC100

LGE5331(LM15U)

I2S_OUT_BCK/GPIO105
I2S_OUT_MCK/GPIO104

I2S_OUT_WS/GPIO103

I2S_OUT_SD/GPIO106
I2S_OUT_SD1/GPIO107
I2S_OUT_SD2/GPIO108
I2S_OUT_SD3/GPIO109

LINE_IN_0L
LINE_IN_0R
LINE_IN_1L
LINE_IN_1R
LINE_IN_2L
LINE_IN_2R
LINE_IN_3L
LINE_IN_3R

LINE_OUT_0L
LINE_OUT_0R
LINE_OUT_2L
LINE_OUT_2R

EARPHONE_OUT_L
EARPHONE_OUT_R

ARC0

AUVAG
AUVRM

I2S_IN_BCK/GPIO99
I2S_IN_SD/GPIO100

I2S_IN_WS/GPIO98

GPIO_PM14/GPIO27
GPIO_PM15/GPIO28
GPIO_PM16/GPIO29

IC100

LGE5331(LM15U)

AG2
AG1
AG3
AH1
AH2
AH3
AJ2
AJ3

AK3
AL1
AL2
AL3

AF2
AF3

Y6

AK2
AK1

C13
B14
B13

F16
F15
E16
D16
E15
D15
E14

AJ6
AH5
AH4

0

JTAG

DPC_CTRL
12V_ON

R6440

MHL_DET_LM15
COMPENSATION_DONE_1
/MHL_OCP

R606

2.2uF

2.2uF

2.2uF

2.2uF

C605 1uF

HP_LOUT

HP_ROUT

TCK0

C601
C602
C603
C604

JTAG

R610
22

R611
22

1K

22pF

C607

COMP1/AV1/DVI_L_IN
COMP1/AV1/DVI_R_IN
SC_L_IN
SC_R_IN

SCART_Lout
SCART_Rout

HP_LOUT

HP_ROUT

HDMI_ARC

C606
10uF
10V

+3.3V_NORMAL

R608

C608
22pF

JTAG

R613
0

R639
100

OPT

R638
100

1uF

C609

R618
22

C635

0.01uF

C636

0.01uF

L60 0

PZ1 608U 121- 2R0T F

JTAG

C611
22pF

TDO0_1

OPT

R615

22K

22K

47K

R640

R641

AUD_SCK

AUD_LRCK
AUD_LRCH

HP_LOUT_MAIN

OPT

HP_ROUT_MAIN

OPT

TRST_N0

TU_CVBS

AV1_CVBS_IN

SC_CVBS_IN

DTV/MNT_V_OUT

SC_R

SC_G

SC_B

SC_ID
SC_FB

COMP1_Pr

COMP1_Y

COMP1_Pb

C612

1000pF

OPT

R623 68
R624 33

68

R625

33

R626
R627 68
R628 33

R629 68
R630 33

68

R631

33

R632
R633 68
R634 33

R619 68

C613 0.047uF

R620 33
R621 33
R622 33

50V

C619

0.047uF
C620

0.047uF

C621

0.047uF

C622

0.047uF

C623

0.047uF

C624

0.047uF

C625

1000pF

0.047uF

C626

0.047uF

C627

0.047uF
C628

0.047uF
C629

0.047uF

C630

0.047uF

C631

1000pF

C632

C616 0.047uF
C617 0.047uF
C618 0.047uF

AB2

RIN0M

AB1

RIN0P

AA3

GIN0M

AA1

GIN0P

Y3

BIN0M

Y2

BIN0P

AA2

SOGIN0

W5

HSYNC0

W4

VSYNC0

AE1

RIN1M

AD3

RIN1P

AD1

GIN1M

AD2

GIN1P

AC2

BIN1M

AB3

BIN1P

AC3

SOGIN1

Y5

HSYNC1

Y4

VSYNC1

AC5

RIN2M

AB4

RIN2P

AB5

GIN2M

AC6

GIN2P

AA6

BIN2M

AA5

BIN2P

AB6

SOGIN2

AC4

HSYNC2

AE4

VCOM

AE5

CVBS0

AF6

CVBS1

AE6

CVBS2

AF5

CVBSOUT1

GPIO80/LED[1]
GPIO79/LED[0]

USB_SSTXP_1

USB_SSTXN_1
USB_DM_PSS_1
USB_DP_PSS_1

USB_SSRXP_1

USB_SSRXN_1

USB_SSTXP_0

USB_SSTXN_0
USB_DM_PSS_0
USB_DP_PSS_0

USB_SSRXP_0

USB_SSRXN_0

HWRESET

XOUT

IRIN

USB0_DM
USB0_DP
USB1_DM
USB1_DP
USB2_DM
USB2_DP

B1

TN

C1

TP

A2

RN

B2

RP

E5
F4

G4

AU2

XIN

AT2

K4

C5
B5
C4
B4
A4
B3
AR4
AT4
AU4
AR5
AU5
AT5
AR7
AT7
AU7
AR8
AU8
AT8

AC-coupling CAP

C633 0.1uF

C634 0.1uF

Place near by MST

EPHY_TDN
EPHY_TDP
EPHY_RDN
EPHY_RDP

0

R642

I2C_SCL2
I2C_SDA2

R6430

SOC_RESET

XIN_MAIN
XOUT_MAIN

WIFI_DM
WIFI_DP
USB_DM2
USB_DP2
USB_DM1
USB_DP1

SSUSB_TXP
SSUSB_TXN
USB_DM3
USB_DP3
SSUSB_RXP
SSUSB_RXN

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Close to Main soc

LM15U

MAIN4_EXT_IN/OUTPUT

2014-11-20

04

AF33

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

AF34

AG8

AG9

AG10

AG11

AG12

AG13

AG16

AG17

AG23

AG24

AG25

AG26

AG27

AG28

AG29

AG30

AG31

AG32

AG33

AG34

AG36

AH8

AH9

AH10

AH11

AH12

AH13

AH16

AH17

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AH31

AH32

AH33

AH34

AJ7

AJ8

AJ9

AJ10

AJ11

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

AJ30

AJ37

AK7

AK8

AK9

AK10

AK11

AK12

AK13

AK14

AK16

AK17

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

AK30

AK31

AK32

AK33

AK34

AL8

AL9

AL13

AL14

AL16

AL17

AL19

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL30

AL31

AL32

AL33

AL34

AL36

AM3

AM20

AN3

AN22

AN35

AN36

AN37

AP7

AP24

AP27

AP30

AP33

AR1

AR3

AR6

AR9

AT1

AT3

AT6

AT36

AU22

AU25

AU28

AU31

AU34

GND_430

GND_431

GND_432

GND_433

GND_434

GND_435

GND_436

GND_437

GND_438

GND_439

GND_440

GND_441

GND_442

GND_443

GND_444

GND_445

GND_446

GND_447

GND_448

GND_449

GND_450

GND_451

GND_452

GND_453

GND_454

GND_455

GND_456

GND_457

GND_458

GND_459

GND_460

GND_461

GND_462

GND_463

GND_464

GND_465

GND_466

GND_467

GND_468

GND_469

GND_470

GND_471

GND_472

GND_473

GND_474

GND_475

GND_476

GND_477

GND_478

GND_479

GND_480

GND_481

GND_482

GND_483

GND_484

GND_485

GND_486

GND_487

GND_488

GND_489

GND_490

GND_491

GND_492

GND_493

GND_494

GND_495

GND_496

GND_497

GND_498

GND_499

GND_500

GND_501

GND_502

GND_503

GND_504

GND_505

GND_506

GND_507

GND_508

GND_509

GND_510

GND_511

GND_512

GND_513

GND_514

GND_515

GND_516

GND_517

GND_518

GND_519

GND_520

GND_521

GND_522

GND_523

GND_524

GND_525

GND_526

GND_527

GND_528

GND_529

GND_530

GND_531

GND_532

GND_533

GND_534

GND_535

GND_536

GND_537

GND_538

GND_539

GND_540

GND_541

GND_542

GND_543

GND_544

GND_545

GND_546

GND_547

GND_548

GND_549

GND_550

GND_551

GND_552

GND_553

GND_554

GND_555

GND_556

GND_557

GND_558

GND_559

GND_560

GND_561

GND_562

GND_563

GND_564

GND_565

GND_566

GND_567

GND_568

GND_569

GND_570

GND_571

V23

GND_279

V24

GND_280

GND_281

V25

GND_282

V28

V29

GND_283

V30

GND_284

GND_285

V31

GND_572

GND_286

W8

GND_287
GND_288
GND_289
GND_290
GND_291
GND_292
GND_293
GND_294
GND_295
GND_296
GND_297
GND_298
GND_299
GND_300
GND_301
GND_302
GND_303
GND_304
GND_305
GND_306
GND_307
GND_308
GND_309
GND_310
GND_311
GND_312
GND_313
GND_314
GND_315
GND_316
GND_317
GND_318
GND_319
GND_320
GND_321
GND_322
GND_323
GND_324
GND_325
GND_326
GND_327
GND_328
GND_329
GND_330
GND_331
GND_332
GND_333
GND_334
GND_335
GND_336
GND_337
GND_338
GND_339
GND_340
GND_341
GND_342
GND_343
GND_344
GND_345
GND_346
GND_347
GND_348
GND_349
GND_350
GND_351
GND_352
GND_353
GND_354
GND_355
GND_356
GND_357
GND_358
GND_359
GND_360
GND_361
GND_362
GND_363
GND_364
GND_365
GND_366
GND_367
GND_368
GND_369
GND_370
GND_371
GND_372
GND_373
GND_374
GND_375
GND_376
GND_377
GND_378
GND_379
GND_380
GND_381
GND_382
GND_383
GND_384
GND_385
GND_386
GND_387
GND_388
GND_389
GND_390
GND_391
GND_392
GND_393
GND_394
GND_395
GND_396
GND_397
GND_398
GND_399
GND_400
GND_401
GND_402
GND_403
GND_404
GND_405
GND_406
GND_407
GND_408
GND_409
GND_410
GND_411
GND_412
GND_413
GND_414
GND_415
GND_416
GND_417
GND_418
GND_419
GND_420
GND_421
GND_422
GND_423
GND_424
GND_425
GND_426
GND_427
GND_428
GND_429

W9
W10
W11
W15
W16
W17
W18
W19
W20
W21
W22
W27
W28
W29
W30
W31
Y9
Y10
Y11
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y30
Y31
Y34
Y37
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA22
AA23
AA24
AA25
AA26
AA30
AA31
AA35
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB30
AB31
AB32
AB33
AB34
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC31
AC32
AC33
AC34
AC35
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD31
AD32
AD33
AD34
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AF7
AF8
AF9
AF10
AF11
AF16
AF17
AF27
AF28
AF29
AF30
AF31
AF32

A3

GND_1

A9

GND_2

A19

GND_3

A22

GND_4

A25

GND_5

A28

GND_6

A31

GND_7

A34

GND_8

A36

GND_9

B6

GND_10

B19

GND_11

B36

GND_12

B37

GND_13

C2

GND_14

C3

GND_15

C19

GND_16

C36

GND_17

C37

GND_18

D10

GND_19

D11

GND_20

D12

GND_21

D13

GND_22

D14

GND_23

D22

GND_24

D25

GND_25

D29

GND_26

D32

GND_27

D36

GND_28

D37

GND_29

E10

GND_30

E11

GND_31

E12

GND_32

E13

GND_33

E34

GND_34

E35

GND_35

E36

GND_36

F11

GND_37

F12

GND_38

F13

GND_39

F17

GND_40

F26

GND_41

F28

GND_42

F29

GND_43

F30

GND_44

F31

GND_45

F32

GND_46

F33

GND_47

G6

GND_48

G9

GND_49

G11

GND_50

G12

GND_51

G13

GND_52

G15

GND_53

G16

GND_54

G17

GND_55

G18

GND_56

G19

GND_57

G20

GND_58

G21

GND_59

G22

GND_60

G23

GND_61

G24

GND_62

G25

GND_63

G27

GND_64

G28

GND_65

G29

GND_66

G30

GND_67

G31

GND_68

G32

GND_69

G35

GND_70

H8

GND_71

H9

GND_72

H10

GND_73

H11

GND_74

H12

GND_75

H13

GND_76

H14

GND_77

H15

GND_78

H16

GND_79

H17

GND_80

H18

GND_81

H19

GND_82

H20

GND_83

H21

GND_84

H22

GND_85

H23

GND_86

H24

GND_87

H25

GND_88

H26

GND_89

H27

GND_90

H28

GND_91

H29

GND_92

H30

GND_93

H31

GND_94

H32

GND_95

J7

GND_96

J8

GND_97

J9

GND_98

J10

GND_99

J11

GND_100

J12

GND_101

J13

GND_102

J14

GND_103

J16

GND_104

J17

GND_105

J18

GND_106

J19

GND_107

J20

GND_108

J21

GND_109

J22

GND_110

J23

GND_111

J24

GND_112

J25

GND_113

J26

GND_114

J27

GND_115

J28

GND_116

J29

GND_117

J30

GND_118

J31

GND_119

K7

GND_120

K8

GND_121

K9

GND_122

K10

GND_123

K11

GND_124

K12

GND_125

K13

GND_126

K14

GND_127

K15

GND_128

K16

GND_129

K17

GND_130

K18

GND_131

K19

GND_132

K20

GND_133

K21

GND_134

K22

GND_135

K23

GND_136

K24

GND_137

K25

GND_138

K26

GND_139

K27

GND_140

K28

GND_141

K29

GND_142

K30

GND_143

GND_144

GND_145L9GND_146

GND_147

GND_148

GND_149

GND_150

GND_151

GND_152

GND_153

GND_154

GND_155

GND_156

GND_157

GND_158

GND_159

GND_160

GND_161M9GND_162

GND_163

GND_164

GND_165

GND_166

K31

L16

L18

L19

L22

L23

L24

L25

L26

L27

L28

L29

L30

L31

L34

GND_167

L37

M15

M16

M17

M18

M19

M26

LGE5331(LM15U)

GND_168

GND_169

GND_170

GND_171

GND_172

GND_173N7GND_174N8GND_175N9GND_176

GND_177

GND_178

GND_179

GND_180

GND_181

GND_182

GND_183

GND_184

GND_185

GND_186P9GND_187

GND_188

GND_189

GND_190

GND_191

GND_192

GND_193

M27

M28

M29

M30

M31

N15

N16

N17

N18

N19

N27

N28

N29

N30

N31

P10

GND_194

P11

P12

P13

P14

P15

P16

P17

P18

IC100

GND_195

GND_196

GND_197

GND_198

GND_199

GND_200

GND_201

GND_202

GND_203

GND_204

GND_205

P19

P20

P21

P27

GND_206R7GND_207R8GND_208R9GND_209

P28

P29

P30

P31

P34

P37

R10

GND_210

R11

R12

GND_211

R13

GND_212

GND_213

R14

R15

GND_214

R16

GND_215

R17

GND_216

GND_217

R18

R19

GND_218

R20

GND_219

GND_220

R21

R27

GND_221

R28

GND_222

R29

GND_223

GND_224

R30

R31

GND_225

GND_226T7GND_227T8GND_228T9GND_229

GND_230

GND_231

GND_232

GND_233

GND_234

GND_235

GND_236

GND_237

GND_238

GND_239

GND_240

GND_241

GND_242

GND_243

GND_244

GND_245

GND_246U8GND_247U9GND_248

GND_249

GND_250

GND_251

GND_252

GND_253

GND_254

GND_255

GND_256

GND_257

GND_258

GND_259

GND_260

GND_261

GND_262

GND_263

GND_264

GND_265

GND_266

GND_267V8GND_268V9GND_269

GND_270

GND_271

GND_272

GND_273

GND_274

GND_275

GND_276

GND_277

T10

T11

T12

T15

T16

T17

T18

T19

T20

T21

T22

T23

T27

T28

T29

T30

T31

U10

U11

U12

U13

U14

U15

U16

U17

U20

U21

U22

U23

U24

U28

U29

U30

U31

U34

U37

V10

V11

GND_278

V15

V16

V17

V18

V19

V20

V21

V22

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LM15U

LM15U_GND

2014-1-21
05

CI Region

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

CI SLOT

+5V_CI_ON

CI_DATA[0-7]

* Option name of this page : CI_SLOT

(because of Hong Kong)

CI TS INPUT

+5V_NORMAL

R900
10K

CI_SLOT

CLOSE TO MSTAR

CI DETECT

/CI_CD2

/CI_CD1

/CI_CD1

TPI_DATA[4]
TPI_DATA[5]
TPI_DATA[6]
TPI_DATA[7]

CI_IORD
CI_IOWR

CI_MDI[0]
CI_MDI[1]
CI_MDI[2]
CI_MDI[3]

CI_MDI[4]
CI_MDI[5]
CI_MDI[6]
CI_MDI[7]

PCM_RESET

CAM_WAIT_N

TPI_CLK
TPI_VAL

TPI_SOP

TPI_DATA[0]
TPI_DATA[1]
TPI_DATA[2]
TPI_DATA[3]

CLOSE TO MSTAR

CI_MISTRT

CI_MIVAL_ERR

CI_MCLKI

GND

REG

CI_SLOT

IC900

74LVC1G32GW

1B 5 VCC

2A

3GND

OR_GATE_CI_TI

IC900-*1

SN74LVC1G32DCKR

1A5

B

2

3

CI_SLOT

R901
R902

CI_SLOT

AR900

/CI_CD2

CI_SLOT

C900
2pF
50V

+3.3V_NORMAL

4 Y

OR_GATE_CI_TOSHIBA

IC900-*2

TOSHIBA ELECTRONICS KOREA CORPORATION

VCC

IN_B

1

IN_A

2

Y

GND

4

3

AR901

33

47
47

33

+5V_NORMAL

CI_SLOT

R906

10K

CI_SLOT

CI_SLOT
CI_SLOT

+5V_NORMAL

VCC

5

OUT_Y

4

CI_SLOT

AR910 33

CI_SLOT

R907

10K

CI_SLOT

R908 10K

CI_SLOT

C901

GND

0.1uF

R909

+3.3V_NORMAL

10K

R910

100

CI_SLOT

R911

10K

CI_SLOT

C902

10uF

10V

CI_SLOT

R912

100

R913
47

CI_SLOT

REG

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]
CI_DATA[3]

CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

AR903 33

CI_SLOT

AR902

R918 33
R919 33
R920 100

CI_SLOT

AR908 33

AR909 33

AR913 33

CI_SLOT

AR904 33

CI_SLOT

AR905 33

33

CI_SLOT

CI_SLOT

AR906

33

CI_SLOT

AR907
33

CI_SLOT

CI_SLOT

CI_SLOT

CI_SLOT

TPO_DATA[7]
TPO_DATA[6]
TPO_DATA[5]

TPO_DATA[4]

TPO_DATA[3]

TPO_DATA[2]

TPO_DATA[1]

TPO_DATA[0]

EB_ADDR[8]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]

EB_ADDR[12]
EB_ADDR[13]
EB_ADDR[14]
CAM_REG_N

EB_OE_N
EB_WE_N

EB_DATA[0]
EB_DATA[1]
EB_DATA[2]
EB_DATA[3]

EB_DATA[4]
EB_DATA[5]
EB_DATA[6]
EB_DATA[7]

EB_ADDR[0]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]

EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[6]
EB_ADDR[7]

EB_BE_N1
EB_BE_N0

TPO_SOP
TPO_VAL
TPO_CLK

EB_DATA[0-7]

TPO_DATA[0-7]

CI_MDI[7]
CI_MDI[6]

CI_SLOT

JK900

10125901-115LF

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

65
66
67
68

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2660
2761
2862
2963
3064
31
32
33
34

G1G2

69

R914

R915

C903

0.1uF

CI_SLOT

47

CI_SLOT

CI_SLOT

100

GND

GND

GND

GND

CI_DATA[3]
CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]

CI_DATA[0-7]

R916

CI_ADDR[10]

CI_ADDR[11]

CI_ADDR[9]

CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[12]

CI_ADDR[7]

CI_ADDR[6]

CI_ADDR[5]

CI_ADDR[4]

CI_ADDR[3]

CI_ADDR[2]

CI_ADDR[1]

CI_ADDR[0]

10K

/PCM_CE1

CI_OE

+5V_NORMAL

R917
10K

CI_SLOT

CI_WE

GND

CI_ADDR[0-14]

CAM_IREQ_N

C904

0.1uF

CI_SLOT

CLOSE TO MSTAR

OLED_CI_SLOT

JK900-*1

10125901-015LF

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

65
66
67
68

69

CI HOST I/F

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2660
2761
2862
2963
3064
31
32
33
34

G1G2

CI_MDI[5]
CI_MDI[4]

CI_MDI[3]
CI_MDI[2]
CI_MDI[1]
CI_MDI[0]

CI_MISTRT

CI_MIVAL_ERR

CI_MCLKI

CI_ADDR[0]
CI_ADDR[1]
CI_ADDR[2]
CI_ADDR[3]

CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]

CI_ADDR[8]

CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]

CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

CI_IORD
CI_IOWR

CI_OE
CI_WE

CAM_CD1_N

CI_DATA[0-7]

CI POWER ENABLE CONTROL

+5V_NORMAL

C905

0.1uF
50V

CI_SLOT

R922

PCM_5V_CTL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

R921
10K

CI_SLOT

100

IN

EN

AP2151WG-7

5

CI_SLOT

4

IC901

CI_DATA[0-7]

EB_DATA[0-7]

+5V_CI_ON

OUT

1

GND

2

FLG

3

C906
1uF
25V

CI_SLOT

R923
10K

CI_SLOT

LM15U

PCMCI

2014-10-17

9

+3.5V_ST

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

RL_ON

+3.3V_NORMAL

INV_CTL

R2314

R2300
10K

1K

R2301
10K

2

R2311100

1

3

1

2

3

Q2300 2N3906S-RTK

KEC_RL_ON_TR

NXP_RL_ON_TR

Q2300-*1 MMBT3906(NXP)

P2300

SMAW200-H12S5K(BK)(LTR)

2

1

4

3

6

5
7

8

9

10
12

11

13

’15 UHD 12.5V sole out power

’Net name +12V means 12.5V power output

+3.3V - eMMC

C2303
22uF
10V

+1.8V

DVDD18_EMMC

L2332

PZ1608U121-2R0TF

C2306

0.1uF
16V

C2308
22uF
10V

+3.3V_NORMAL

PZ1608U121-2R0TF

L2304

3.3V_EMMC

C2302

0.1uF
16V

+1.8V - LM15U, eMMC
& Vx1 pull-up

+3.3V_NORMAL

+1.8V

L2331

MLB-201209-0120P-N2

C23 12

0.1 uF
25V

MLB-201209-0120P-N2

0

R2317

OPT

100

R2304

0

R2318

L2330

C23 13

R2313

4.7 uF
50V

C23 14

0.1 uF

OPT

100

25V

PWM_DIM

PWM_TCON_OUT

+3.3V_NORMAL

PWM_DIM2

C2318

4.7uF

LD2300

R23 15

3.3 K

C2316
10uF
16V

50V

C2319
10uF
16V

A12V

C2320
10uF
16V

L/D_VSYNC

L/D_CLK
L/D_DI

+12V

+12V

L2321

MLB-201209-0120P-N2

PANEL_CTL

+12V

L2309

PZ1608U121-2R0TF

C2325

C2323

0.1uF

10uF
16V

1.0V_DCDC_TI
C2335-*1

3300pF
50V

Switching freq: 700K

PANEL_POWER

L2322

MLB-201209-0120P-N2

C23 26
10u F
25V
OPT

10K

R2361

R2372
10K

C2328

0.1uF
25V

C2329
10uF
10V

C2331

0.01uF
50V

R2329

R2331

DDR +1.5V

R2320

R2321

18K

R1

C2327
100pF

50V

4.7K

1%

1%

R2322
22K

1%

R2

Vout=0.765*(1+R1/R2)=1.554V

10K

1.8K

B

0.1uF

C2374

OPT

C2334

C2336

10uF

10uF

25V

C

Q2321
2N3904S
KEC_PANEL_CTL_TR

E

C

B

E

ROHM_BD9D321_1.5V_DDR_DCDC

R2326

10K

VREG

C2332

C2335

1uF

2200pF

10V

50V

1.0V_DCDC_ROHM

OPT

OPT
C2338
1uF

25V

25V

Q2321-*1
MMBT3904(NXP)

NXP_PANEL_CTL_TR

POWER_ON/OFF2_3

IC2303

BD9D321EFJ

EN

1

FB

2

3

SS

4

3A

9

THERMAL

AOS_PANEL_POWER_FET

AO4447A

S_1

1

S_2

2

S_3

3

G

4

C2341

10uF
25V

OPT

[EP]

VIN

8

BOOT

7

SW

6

GND

5

TYP 6000mA

PANEL_VCC

IC2309

D_4

8

D_3

7

D_2

6

D_1

5

R2359
2K
OPT

R2360
2K

OPT

S_1

S_2

S_3

C23 48
10u F
25V

OPT

ROHM_PANEL_POWER_FET

IC2309-*1

RRH140P03TB

1

2

3

4G5

C2349

0.1uF
25V

D_4

8

D_3

7

D_2

6

D_1

Power_DET

+12V

R2335
14K
1%

R2336

5.6K
1%

RESET_IC_DIODES_NEW_APX803E29

VCC

IC2307-*1
APX803E29

3

1

TP2300

+3.5V_ST

R2354
10K
OPT

POWER_DET_1

POWER_DET

C2370

0.1uF
16V

12.5V-->3.58V

R2349
100K

RESET_IC_ROHM

IC2307

BD48K28G

VDD

C2361

0.1uF
16V

RESET

2

GND

VOUT

2

3

1

GND

+5.0V normal & USB

16V

0.1uF
C2344

PS064T-2R2MS

L2312

2.2uH

C2346

22uF

10V

+1.5V_DDR

C2347
22uF
10V

TI_TPS54327_1.5V_DDR_DCDC

IC2303-*1

TPS54327DDAR

EN

1

VFB

2

THERMAL

VREG5

3

SS

4

ZD2302

2.5V
DCDC_DIODE

C2358

OPT

R23 39 1 6K 1%

RSET228AGND

27

IC2305

6A

9EN10

SW_OUT211SW_OUT1

10K

+5V_USB_1

POWER_ON/OFF1

R23 4215 0K 1%

COMP25RLIM26RSET1

SW_EN213SW_EN1

+5V_USB_2

2200pF
50V

R2344
10K

12

USB_CTL1

USB_CTL2

+12V

[EP]GND

VIN

8

VBST

9

7

SW

6

GND

5

L2314

120-ohm

C2350
10uF
35V

OPT

C2351
10uF
35V

VIN_1

VIN_2

VIN_3

C2353

0.1uF
50V

PGND_1

PGND_2

PGND_3

1uF

25V

C23 52

C2355

0.0068uF

R23 37 1 6K 1%

[EP]

1

THERMAL

2

29

3

4

SN1302001(TPS65286RHDR)

5

6

V7V

7

8

MODE/SYNC

50V

R2338

22SS23FB24

21

20

19

18

17

16

15

14

NFAULT2

/USB_OCD1

C2362

C2359

0.047uF

100pF

25V

50V

LX_3

LX_2

LX_1

BST

SW_IN2

SW_IN1

NFAULT1

Vout=0.6*(1+R1/R2)

5.1V:R1-51K, R2-6.8K

C2364

5%

82pF

50V

L2313

4.7uH

C2363

0.047uF
25V

100K

R2350

1/16W

/USB_OCD2

R2

1%

R1

1%

R2353

1/16W

1/16W

1/16W

6.8K

51K

5%

R2351

R2352

100K

C2365
22uF
10V

C2366
1uF
10V

C2367
22uF
10V

C2368
10uF
10V

+5V_NORMAL

ZD2303

DCDC_DIODE

IC2301

AZ1117EH-ADJTRG1

+12V

L2300

PZ1608U121-2R0TF

C2301
10uF
25V

Switching freq: 700K

OUTIN

ADJ/GND

1%

1/16W

1%

1/16W

+3.3V_NORMAL

R2303

R2302

R2305

R2

10K

1%

51K

15K

1%

C2305
1uF
10V

0.1uF
C2372

C2307

0.015uF
50V

POWER_ON/OFF2_1

R1

C2304
100pF

50V

OPT

75

R2307

33

R2308

EN

VFB

VREG5

SS

R2309
1

C2309
10uF
10V

IC2302

TPS54427DDA

1

9

2

THERMAL

3

4

4A

8

7

6

5

C2310
10uF
10V

[EP]GND

VIN

VBST

SW

GND

0.1uF
C2311

16V

D2302

DCDC_DIODE

PS064T-2R2MS

L2333

2.2uH

C2315

22uF

10V

2.5V

MAX A

+3.3V_NORMAL

3.5V tvs diode default apply

ZD2300

C2317

22uF
10V

Vout=0.765*(1+R1/R2)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+1.1V or +1.15V _CPU CORE

+12V

L2310

PZ1608U121-2R0TF

Placed on SMD-TOP

C2321
10uF
16V

C2322
10uF
16V

C2324

0.1uF
16V
OPT

Vout=0.8*(1+R1/R2)

R1:15K/R2:56K, V=1.00V(CPU_VID0=L,CPU_VID1=L) Voltage drop 0.01V
R1:15K/R2:56K//240K, V=1.05V(CPU_VID0=H,CPU_VID1=L) Voltage drop 0.01V
R1:15K/R2:56K//240K, V=1.05V(CPU_VID0=L,CPU_VID1=H) Voltage drop 0.01V

R1:15K/R2:56K//240K//240K, V=1.10V(CPU_VID0=H,CPU_VID1=H) Voltage drop 0.01V

PGND

VIN

AGND

BD86106EFJ

1

2

3

FB

4

IC2300

EAN62653301

THERMAL

6A

L2311

C2333

0.0068uF
50V

R2325

POWER_ON/OFF2_4

10K

2uH

OPT

C2337
10uF
10V

CPU_VID0

G

DIODEDS_CPU_CORE_VID_FET

[EP]

SW_2

8

SW_1

9

7

EN

6

R2324

6.8K

COMP

5

C2330

0.1uF
16V

C2339
10uF
10V

+3.3V_NORMAL

R2371

10K

R2330

0 5%

D

Q2302-*1
2N7002K

S

OPT

C2340
100uF

R2-1.13V

R2332

20K
1%

R2333
200K
1%

G

OPT

C2343

C2342

10uF

10uF

10V

10V

D

CPU_VID1

S

2N7002KA

Q2302

KEC_CPU_CORE_VID_FET

MAX 2.7A

C2345
47pF
50V

R2-1.13V

+3.3V_NORMAL

R2306
10K

R2310

0 5%

D

Q2303-*1

G

2N7002K

S

DIODEDS_CPU_CORE_VID_FET

R2312

20K
1%

R2316
200K
1%

G

D

S

2N7002KA

Q2303

KEC_CPU_CORE_VID_FET

+1.1V_VDDC_CPU

R2334

15K

1%

R2345
13K

1%

R2346
43K

1%

R2-1.1V

+3.5V_ST

A12V

R1

C2356

C2354

L2305

0.1uF

10uF

25V

R2370

10K

2.5V

ZD2301

DCDC_DIODE

25V

BLM18PG121SN1D

R2

+3.5V_ST

VLS5045EXT-2R2N

C2360

C2357
22uF
10V

22uF

10V

L2306

2.2uH

IC2306

TPS563200

GND

1

SW

2

VIN

3

3A

6

5

4

VBST

EN

VFB

0.1uF

16V

C2369

25V

C2373

0.1uF

R2

R23 23

51K

1/1 6W

1%

Vout=0.765*(1+R1/R2)

1%
1/1 6W

150 K

R23 27

50V

1%
1/1 6W

33K
R23 28

10pF

R1

C2371

LM15 Power SEQUENCE

POWER_ON/OFF1(5V)

POWER_ON/OFF2_1(3.3V)

POWER_ON/OFF2_3(1.5V, 2.5V)

POWER_ON/OFF2_4(1.1V)

LM15U

LM15U_12.5V_Sole out_UF69

2014-11-11

23

CORE_VID1

Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

+3.3V_NORMAL

R2516

10K

R2517

0 5%

POWER_ON/OFF2_4

OPT

C2500

0.1uF
16V

R2-3

R25 18

120 K

1%

1/1 6W

D

G

S

D

G

S

+1.1V or +1.15V _CORE

R2507

1K

R1

1%

R2

1/1 6W

1%

30K

R25 19

CORE_VID0

2N7002KA

Q2501

KEC_CORE_DCDC_FET

Q2501-*1
2N7002K

DIODES_CORE_DCDC_FET

+3.3V_NORMAL

R2500

10K

R2501

0 5%

R2-2

R25 02

1%

G

D

Q2500-*1

G

2N7002K

DIODES_CORE_DCDC_FET

S

120 K

1/1 6W

30K

1/1 6W

D

S

1/1 6W

R2505

12K

12K

R25 06

1%

R25 03

2N7002KA

Q2500

KEC_CORE_DCDC_FET

13K

R25 04

1/16W

1/1 6W

C2501

10V

1%

1%

1uF

R2-1

C2502

0.033uF
50V

R2508
100K

1/16W
1%

R2510
100

1/16W

MP8762HGLE-Z

EN

1

FREQ

2

FB

3

SS

4

AGND

5

10A

PG

6

VCC

7

BST

8

R2509
33

1/16W
5%

1%

IC2501

C2503

0.1uF
16V

16

15

14

13

12

11

10

9

SW_2

SW_1

IN_2

PGND_4

PGND_3

PGND_2

PGND_1

IN_1

1%

1/16W

R2512
220K

1/10W
5%

430K

R2511

LPBN8050T-1R0N

L2500

1.0uH

C2504
10uF
25V

C2506

330pF

50V

C2505
10uF
25V

C2507
22uF
10V

C2508

22uF
10V

L2501

+1.1V_VDDC

C2509
22uF
10V

DCDC_DIODE

+12V

2.5V

ZD2500

Vout=0.611*(1+R1/R2)

R1:13K/R2:22K, V=0.95V(CORE_VID0=L,CORE_VID1=L) Voltage drop 0.02V
R1:13K/R2:22K//150K, V=1.00V(CORE_VID0=H,CORE_VID1=L) Voltage drop 0.02V
R1:13K/R2:22K//150K, V=1.00V(CORE_VID0=L,CORE_VID1=H) Voltage drop 0.02V

R1:13K/R2:22K//150K//150K, V=1.05V(CORE_VID0=H,CORE_VID1=H) Voltage drop 0.02V

MAX 7A

POWER_ON/OFF2_3

+3.3V_NORMAL

TU_JP

C2510

0.1uF
16V

+2.5V

TU_JP/EU_UF77_ESD

R2513

10K

TU_JP/EU_UF77_ESD

TU_JP

IC2502

TJ4220GDP-ADJ

C2512

0.1uF
NC_1

VIN3

1

9

2

EN2

NC4

3

2A

4

EAN62206201

THERMAL

Vout=0.6*(1+R1/R2)

8

7

6

5

[EP]GND

GND

ADJ/SENSE

VOUT

NC_2

TU_JP

R2514

R25 15

22K

R2

R1

TU_JP

47K

C2513
10uF
10V

+2.5V_Normal

TU_JP

OPT

5V

ZD2501

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LM15U

LM15U_PWR_2_ALL

2014-11-26

25