LG 42PN450D-ZA Schematic

Internal Use Only

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Asia/Oceania http://biz.lgservice.com

PLASMA TV

SERVICE MANUAL

CHASSIS : PD31B

MODEL : 42PN450D 42PN450D-ZA

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67682001 (1211-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION ................................................................ 6

BLOCK DIAGRAM .................................................................................. 14

EXPLODED VIEW .................................................................................. 15

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

To Instrument's
exposed
METALLIC PARTS

Good Earth Ground
such as WATER PIPE,
CONDUIT etc.

AC Volt-meter

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental sh orts of the cir cui try that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 M
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Ω and 5.2 MΩ.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied all of the PDP TV with PD31B chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage

: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.

(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with

BOM.

(5) The receiver must be operated for about 5 minutes prior to the adjustment.

3. Test method

(1) Performance: LGE TV test method followed
(2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

.

4. Module General Specification

- 42" 2D HD

No Item Specication Remark

1 Display Screen Device 106 cm (42 inch) wide Color Display Module PDP

2 Aspect Ratio 16:9

3 PDP Module PDP42T4####,

RGB Closed (Well) Type, Glass Filter (38%)
Pixel Format: 1024 horiz. By 768 ver.

4 Operating Environment 1) Temp. : 0 ~ 40 deg

2) Humidity : 20 ~ 80%

5 Storage Environment 1) Temp. : -20 ~ 60 deg

2) Humidity : 10 ~ 90 %

6 Input Voltage AC100 ~ 240V, 50/60Hz Maker LG

LGE SPEC

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Model General Specification

No Item Specication Remark

1 Market Albania, Austria, Belgium, Bosnia, Bulgaria, Coratia,

Czech, Denmark, Estonia, Finland, France, Germany,
Greece, Hungary, Ireland, Italy, Kazakhstan, Latvia,
Lithuania, Luxembourg, Morocco, Netherlands,
Norway, Poland, Portugal, Romania, Russia, Serbia,
Slovenia, Spain, Sweden, Slovakia, Switzerland,
Turkey, Ukraine, UK

Australia, New Zealand, Malaysia, Indonesia,
Singapore, South Africa, Israel, Iran, Vietnam, Kenya,
Asia,Non-EU analog, CHINA(cormmercial)

2 Broadcasting system 1) PAL/SECAM BG

2) PAL/SECAM DK

3) PAL I / II

4) SECAM L/L’

5) DVB T

6) DVB C

7) DVB T2

8) DVB S2

1) PAL/SECAM BG

2) PAL/SECAM DK

3) PAL I

4) NTSC M

5) DVB T

3 Receiving system Analog : Upper Heterodyne

Digital : COFDM

4 Scart Jack (1EA) PAL, SECAM EU ONLY

5 Component Input (1EA) Y/Cb/Cr, Y/ Pb/Pr

6 RGB Input (1EA) RGB-PC Commercial Model ONLY

7 RS232C (1EA) SVC Commercial Model ONLY

8 AV (2EA) CVBS ( Hybrid :1) EU model have 1 AV ( Hybrid)

9 HDMI Input (2 or 3EA) HDMI-PC

HDMI-DTV

10 Audio Input (1EA) DVI Audio, Component L/R Input

11 SPDIF Out (1 EA) SPDIF Out

12 USB (1EA) for SVC, S/W Download, DivX

13 LAN only DVB-T2 (UK, Irend) Model

14 PCMCI (1EA) DVB-T/C Decryption Interface, CI+ EU ONLY

36 Country

Non-EU

Programme Coverage (EU)
Digital TV

- PD31B/C are not support SECAM L/L`

- Only PD31B support DVB-T2

- Only PD31C support DVB-S2
Analogue TV
VHF: E2 to E12, UHF: E21 to E69,
CATV: S1 to S20, HYPER: S21 to S47

Programme Coverage (NON-EU)
Digital TV
VHF 04 to 13, UHF 27 to 69
Analogue TV
VHF/UHF 1 to 78, CATV 01 to 71

HDMI/PC 1, HDMI2

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to PD31B chassis applied PDP TV all
models manufactured in TV factory.

2. Designation

(1) Th e ad justm ent is accord ing to the order whic h is

designated and which must be followed, according to the

plan which can be changed only on agreeing.
(2) Power adjustment : Free Voltage.
(3) Magnetic Field Condition: Nil.
(4) Input signal Unit: Product Specification Standard.
(5) Reserve after operation: Above 5 Minutes (Heat Run)

Temperature : at 25 °C ± 5 °C
Relative humidity : 65 % ± 10 %
Input voltage : 220V, 60Hz

(6) Adjustment equipment s : Color Ana lyzer (CA -210 or

CA-110), DDC Adjustment Jig equipment, SVC remote

controller.
(7) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15

- In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours.

- In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above
15°C for 3 hours.

3. Main PCB check process

* APC - After Manual-Insult, executing APC

* Boot file Download

(1) Execute ISP program “Mstar ISP Utility” and then click

“Config” tab.

(2) Set as below, and then click “Auto Detect” and check “OK”

message

If “Error” is displayed, Check connection between computer,

jig, and set.

(3) Click “Read” tab, and then load download file (XXXX.bin)

by clicking “Read”

(4) Click “Connect” tab. If “Can’t ” is displayed, Check

connection between computer, jig, and set.

■ After RGB Full White in HEAT-RUN Mode, the receiver must

be operated prior to the adjustment.

■ Enter into HEAT-RUN MODE

1) Press the POWER ON KEY on R/C for adjustment.

2) OSD display and screen display PATTERN MODE.

● Set is activated HEAT run without signal generator in this

mode.

● Single color pattern ( WHITE ) of HEAT RUN MODE uses to

check panel.

● Caution : If you turn on a still screen more than 20 minutes

(Especially digital pattern, cross hatch pattern), an
after image may be occur in the black level part of
the screen.

(8) Push The “IN STOP KEY” – For memory initialization.

Case1 : Software version up

1) After downloading S/W by USB , Multi-vision set will reboot

automatically

2) Push “In-stop” key

3) Push “Power on” key

4) Function inspection

5) After function inspection, Push “In-stop” key.

Case2 : Function check at the assembly line

1) When TV set is entering on the assembly line, Push “In-

stop” ke y at rst.

2) Push “Power on” key for turning it on.

-> If you push “Power on” key, TV set will recover channel
information by itself.

3) After function inspection, Push “In-stop” key.

(5) Click “Auto” tab and set as below.
(6) Click "Run".
(7) After downloading, check "OK" message.

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* USB DOWNLOAD(*.epk file download)

(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is Low,

it didn’t work.

- But your downloade d version is High, USB data is

automatically detecting

(3) Show the message “Copying files from memory”

(4) Updating is staring.

(5) Updating C om pl et ed, T he Mu lt i- vi si on will restart

automatically.

(6) If your Multi-vision is turned on, check your updated

version and Tool option. (explain the Tool option, next
stage)

* After downloading, have to adjust TOOL OPTION again.

1) Push "IN-START" key in service remote controller.

2) Select "Tool Option 1" and Push “OK” button.

3) Punch in the number. (Each of mode ls has th eir
number.)

4) Completed selecting Tool option.

42PN450D-Z*

HD/FHD HD

Tool option 1 24576

Tool option 2 21800

Tool option 3 3313

Tool option 4 51846

Tool option 5 42(170)

* UK Model

* Caution : Using ‘power on’ button of the Adjustment R/C ,

power on Multi-vision.

* ADC Calibration Protocol (RS232)

NO Enter

Adjust MODE

Item Adjust ‘Mode In’ ADC Adjust

CMD 1 A A

CMD 2 A D

Data 0 0 1

0 0

When transfer the
‘Mode In’,
Carry the command.

- Adjust Sequence

▪aa 00 00 [Enter Adjust Mode]
▪xb 00 40 [Component1 Input (480i)]
▪ad 00 10 [Adjust 480i Comp1]
▪aa 00 90 End Adjust mode

* Required equipment : Adjustment R/C.

ADC adjust

Automatically adjustment
(The use of a internal
pattern)

3.2. Function Check

3.2.1. Check display and sound

■ Check Input and Signal items. (cf. work instructions)

1) TV

2)AV (SCART/ CVBS)

3) COMPONENT (480i)

4) HDMI

5) PC Audio In
* Display and Sound check is executed
by Remote controller.

* Caution : Not to push the INSTOP KEY after completion if

the function inspection.

3.1. ADC Process

3.1.1. ADC

■ Enter Service Mode by pushing “ADJ” key,

■ Enter Internal ADC mode by pushing “►” key at “5. ADC

Calibration”

Only for training and service purposes

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4. Total Assembly line process

4.1. POWER PCB Assy voltage adjustment

(Vs voltage adjustment)

4.1.1.Test equipment : D.M.M 1EA

4.1.2. Condition for adjustment

- No signal with the snow noise in RF mode

4.1.3. Connection Diagram for Measuring

: refer to g.7

4.1.4. Adjustment method

4.1.4.1 Vs adjustment
(1) Connect + terminal of D. M..M. to Vs TP, connect -terminal

to GND.

(2) After turning VR901, voltage of D.M.M adjustment as same

as Vs voltage which on label of panel right/top ( deviation
; ±0.5V)

4.1.4.2 Va adjustment
(1) Connect + terminal of D. M..M. to Va TP, connect -terminal

to GND.

(2) After turning VR502, voltage of D.M.M adjustment as same

as Va voltage which on label of panel right/top ( deviation
; ±0.5V)

4.2. Adjustment Preparation

● Required Equipment

- Remote controller for adjustment

- Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same
product : CH 11 (PDP)

* Please adjust CA-210, CA-100+ by CS-1000 before measur-

ing

- Auto W/B adjustment instrument(only for Auto adjust­ment)

- 9 Pin D-Sub Jack(RS232C) is connected to the AUTO
W/B EQUIPMENT.

Before Adjust of White Balance, Please press
POWER ONLY key

- Adjust Process will start by execute RS232C Command.

● Color temperature standards according to CSM and Module

CSM PLASMA

Cool 11000K

Medium 9300K

Warm 6500K

● CS-1000/CA-100+/CA-210(CH 10) White balance adjust-

ment coordinates and color temperature.

CSM Color Coordination Temp ± Color

x y

COOL 0.276 0.283 11000K 0.002

MEDIUM 0.285 0.293 9300K 0.002

WARM 0.313 0.329 6500K 0.002

Coordination

* Connecting picture of the measuring instrument (On Auto-

matic control)

- Inside PATTERN is used when W/B is controlled. Con­nect to auto controller or push Adjustment R/C POWER­ON -> Enter the mode of White-Balance, the pattern will
come out.

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* Auto-control interface and directions

1) Adjust in the place where the inux of light like oodlight

around is blocked. (Illumination is less than 100Lux).

2) Adhere closely the Color Analyzer ( CA210 ) to the
module less than 10cm distance, keep it with the surface
of the Module and Color Analyzer’s Prove vertically.
(80~100°).

3) Aging time

- After aging start, keep the power on (no suspension of
power supply) and heat-run over 5 minutes.

- Using ‘no signal’ or ‘full white pattern’ or the others,
check the back light on.

■ Auto adjustment Map(RS-232C)

RS-232C COMMAND

[ CMD ID DATA ]

Wb 00 00 White Balance Start
Wb 00 ff White Balance End

RS-232C

COMMAND

[CMD ID DATA]

Cool Mid Warm Cool Mid Warm

R Gain jg Ja jd 00 172 192 192 192

G Gain jh Jb je 00 172 192 192 192

B Gain ji Jc jf 00 192 192 172 192

R Cut 64 64 64 128

G Cut 64 64 64 128

B Cut 64 64 64 128

* Caution

- Color Temperature : COOL, Medium, Warm.

- One of R Gain/G Gain/ B Gain should be kept on 0xC0,
and adjust other two lower than C0. (when R/G/B Gain
are all C0, it is the FULL Dynamic Range of Module)

* Manual W/B process using adjusts Remote control.

■ After enter Service Mode by pushing “ADJ” key,

■ Enter White Balance by pushing “►” key at “6. White

Balance”.

■ Stick the sensor to the center of the screen and select

each items(Red/Green/Blue Gain) using ▲/▼(CH +/-)

key on R/C.

■ Adjust R/G/B Gain using◄/►(VOL +/-) key on R/C.

■ Adjust three modes all(Cool/Medium/Warm) : Fix the one

of R/G/B Gain and Change the others.

■ When the adjustment is completed, Enter “COPY ALL”.

■ Exit adjustment mode using EXIT key on R/C.

M

I

N

CENTER

(DEFAULT)

M

A
X

* After You nish all adjustments, Press “In-start” button and

compare Tool option and Area option value with its BOM, if it
is correctly same then unplug the AC cable.

If it is not same, then correct it same with BOM and unplug

AC cable.
For correct it to the model’s module from factory JIG model.
* Push The “IN STOP KEY” after completing the function

inspection. And Mechanical Power Switch must be set “ON”

* To check the coordinates of White Balance, you have to

measure at the below conditions.

- Picture mode : Vivid, Energy Saving : Off, Below the Ad-

vanced control, Dynamic Contrast : Off, Dynamic Colour : Off

Colour Temp.

Cool 30

Medium 0

Warm 30

-> Picture Mode change : Vivid -> Vivid(User)

4.3. DDC EDID Write (HDMI 256Byte)

-> Not used any more, Use Auto D/L

■ Connect HDMI Signal Cable to HDMI Jack.

■ Write EDID DATA to EEPROM(24C02) by using DDC2B

protocol.

■ Check whether written EDID data is correct or not.

* For SVC main Ass’y, EDID have to be downloaded to Insert

Process in advance.

4.4. EDID DATA

(1) All Data : HEXA Value
(2) Changeable Data :
* : Serial No : Controlled / Data:01
** : Month : Controlled / Data:00
*** : Year : Controlled
**** : Check sum

4.5. EDID DATA Auto Download

(1) Press Adj. key on the Adj. R/C,
(2) Select EDID D/L menu.
(3) By pressing Enter key, EDID download will begin
(4) If Download is successful, OK is display, but If Download is

failure, NG is displayed.

(5) If Download is failure, Re-try downloads.

Only for training and service purposes

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.6 LNB voltage and 22KHz tone check

(1) Test method

1) Press "Power on" button of a service R/C.(Baud rate :
115200 bps)

2) Connect cable between satellite ANT and test JIG.

3) Connect RS232-C Signal Cable.

4) Write LNB ON control command through RS-232-C.

5) check LED light ‘ON’ at 18V menu.

6) check LED light ‘ON’ at 22KHz tone menu.

7) Write LNB OFF control command through RS-232-C.

8) check LED light ‘OFF’ at 18V menu.

9) check LED light ‘OFF’ at 22KHz tone menu.

(2) RS-232 command for test LNB

Command Set ACK

LNB On [A][I][ ][Set ID][ ][30][Cr] [O][K][x] or NG : [N][G][x]
LNB Off [A][I][ ][Set ID][ ][40][Cr] [O][K][x] or NG : [N][G][x]

(3) Test result

- After send LNB On command, ‘18V LED’ and ‘22KHz

tone LED’ should be ON.

- After send LNB Off command, ‘18V LED’ and ‘22KHz tone

LED’ should be OFF.

k}iTzYGG

4;Y 46Y

4;Y 46Y

4;Y 46Y

55NK}#

55NK}#

55NK}#
W

W

W

rqh RQ

rqh RQ

rqh RQ

55NK}

55NK}

55NK}
Wrqh#Rii

Wrqh#Rii

Wrqh#Rii

k}iTzYGG

ck}iGGGqpnGGe

ck}iGGGqpnGGe

tGi

tGi

{

{

■ Edid data and Model option download (RS232 Zender)

NO Enter

download MODE

EDID data and

Model option download

Item download ‘Mode In’ download

CMD 1 A A

CMD 2 A E

Data 0 0 00

0 10

When transfer the

‘Mode In’,

Carry the command.

Automatically download

(The use of a internal

Data)

- Manual Download
* Caution

● Use the proper signal cable for EDID Download

- Digital EDID : Pin3 exists

* Caution

- Never connect HDMI & D-sub Cable at the same time.

- Use the proper cables below for EDID Writing.

- Download HDMI1, HDMI2 separately because HDMI1 is dif­ferent from HDMI2.

For HDMI EDID

DVI-D to HDMI or HDMI to HDMI

<Remark>
After the measurement conditions witnessed in the last state.

* Caution : Never connect HDMI & D-sub Cable when EDID

downloaded.

No. Item Condition Hex Data

1 Manufacturer ID GSM 1E6D

2 Version Digital : 1 01

3 Revision Digital : 3 03

Only for training and service purposes

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* 2D HD EDID data

- 2D HD HDMI1 EDID data

- 2D HD HDMI2 EDID data

4.7. GND & Hi-pot test

■ GND TEST = POWER CORD GND and SIGNAL CABLE

GND

■ Hi-pot TEST = POWER CORD GND and LIVE&NUETRAL

■ Test Process

1. Check the POWER CABLE and SIGNAL CABLE
insertion condition.

2. Connect the AV JACK Tester

3. Controller(GWS103-4) on

4. GND TEST(Auto)

- If Test is failed, Buzzer operate

- If Test is passed, execute next process(HI-pot test)

- Remove A/V CORD from A/V JACK BOX

5. HI-POT test(Auto)

- If Test is failed, Buzzer operate

- If Test is passed, GOOD Lamp on and move to next
process automatically.

■ Checkpoint

(1) Test voltage

1) 3 Poles

- GND: 1.5KV/min at 100mA

- SIGNAL: 3KV/min at 100mA

2) 2 Poles

- SIGNAL: 3KV/min at 100mA

(2) TEST time: 1 second
(3) TEST POINT

1) 3 Poles

- GND Test = POWER CORD GND and SIGNAL

CABLE GND.

- Hi-pot Test = POWER CORD GND and LIVE &

NEUTRAL.

2) 2 Poles

- Hi-pot Test = Accessible Metal and LIVE & NEUTRAL.

(4) LEAKAGE CURRENT: At 0.5mArms

* Vender ID

Input HEX

HDMI1 10

HDMI2 20

HDMI3 30

* Checksum: Changeable by total EDID data.

EDID C/S data 2D-HD

HDMI

check sum

(Hex)

Only for training and service purposes

Block 0 0x3E

Block 1 0x24(HDMI1)

0x14(HDMI2)

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Model name & Serial number Download

5.1. Model name & Serial number D/L

■ Press “Power on” key of service remocon.(Baud rate :

115200 bps)

■ Connect RS232 Signal Cable to RS-232 Jack.

■ Write Serial number by use RS-232.

■ Must check the serial number at signal test of customer sup-

port. (Refer to below).

5.2. Signal TABLE

CMD LENGTH ADH ADL DATA_1 ... Data_n

CMD: A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 + … + Data_n
Delay : 20ms

CS DELAY

1) Press the ‘instart’ key of ADJ remote controller.

2) Go to the menu ‘5.Model Number D/L’ like below photo.

3) Input the Factory model name or Serial number like
photo.

4) Check the model name Instart menu -> Factory name
displayed.

5) Check the Diagnostics (DTV country only) -> Buyer
model displayed

5.3. Command Set

* Description

No. 1

Adjust mode EEPROM WRITE

CMD(hex) A0h

LENGTH(hex) 84h+n

Description n-bytes Write (n = 1~16)

FOS Default write : <7mode data> write
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart,
0, Phase
Data write : Model Name and Serial Number write in EEP­ROM,.

5.4. Method & Notice

(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory
by D-book 4.0

* Manual Download (Model Name and Serial Number)
If the TV set is downloaded By OTA or Service man,

Sometimes model name or serial number is initialized.( Not
always)

6. Download CI+ Key (EU model only)

* Connect TV SET and PC which download keys Writing pro-

gram by RS232C-Cable

(1) Start “CIKeyl.exe”Program and Click (3) Button to connect

TV and PC.
(2) Click (5) to download CI+ Key.
(3) When download succeed, you can see “OK” on (6)

There is impossible to download by bar code scan, so It need
Manual download.

Only for training and service purposes

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

■ Check the method of RS232C Command

(1) into the main ass’y mode (RS232 : aa 00 00)

CMD1 CMD2 Data 0

A A 0 0

(3) result value

- normally status for download : OKx

- abnormally status for download : NGx

(2) ch eck the key downlo ad for transmi tted command

(RS232 : ci 00 10)

CMD1 CMD2 Data 0

C 1 1 0

(3) result value

- normally status for download : OKx

- abnormally status for download : NGx

■ Check the method of CI+ Key value (RS232)

(1) into the main ass’y mode (RS232 : aa 00 00)

CMD1 CMD2 Data 0

A A 0 0

(2) check the mothed of CI+ key by command
(RS232 : ci 00 20)

CMD1 CMD2 Data 0

C 1 1 0

(3) result value

i 01 OK 1d1852d21c1ed5dcx

└──> CI+ Key Value

7. Download MAC Address, CI+ Key

and widevine Key.

- Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).

-> MAC Address need only DVB-T2 Model (ex.50PA650T-ZA).

8. SW Download Guide.

* Put a *.bin to USB Stick and Turn on TV

(1) Put the USB Stick to the USB socket

(2) Automatically detecting update le in USB Stick

* If your downloaded program version in USB Stick is Low,

it didn’t work.

But your downloaded version is High, USB data is auto-

matically detecting.

(3) Show the message “Copying les from memory”

(4) Updating is staring.
(5) Updating Completed, The TV will restart automatically.
After turn on TV, Please press ‘IN-STOP’ button on ADJ

Remote-control.

* IF you don’t have ADJ R/C, enter ‘Factory Reset’ in OP-

TION MENU.

(6) When TV turn on, check the Updated version on Diagnos-

tics MENU.

* Connect TV SET and PC which download keys Writing

program by RS232C-Cable

1) Start “MAC+CIKeyl.exe”Program and Click (3) Button to
connect TV and PC.

2) Click (4) to download MAC Address.

3) Click (5) to download CI+ Key.

4) When download succeed, you can see “OK” on (6)

* Each Chassis has it’s own MAC Address. Please be careful

of download.

■ Check the method of RS232C Command

(1) into the main ass’y mode (RS232 : aa 00 00)

CMD1 CMD2 Data 0

A A 0 0

(2) ch eck the key downlo ad for transmi tted command

(RS232 : ci 00 10)

CMD1 CMD2 Data 0

C 1 1 0

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

BLOCK DIAGRAM

Only for training and service purposes

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

305

300

206

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

LV1

303

304

207

IMPORTANT SAFETY NOTICE

570

601

301

200

302

205

400

202

201

203

204

120

240

580

590

520

A10

591

A21

A2

900

Only for training and service purposes

- 15 -

910

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

<Full SCART>

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

EU
JK100
PSC008-02

23

SHIELD

22

21

20

19

18

17

16

15

14

13

12

11

10

AV_DET

COM_GND

SYNC_IN

SYNC_OUT

SYNC_GND2

SYNC_GND1

RGB_IO

R_OUT

RGB_GND

R_GND

D2B_OUT

G_OUT

D2B_IN

G_GND

9

ID

8

B_OUT

7

AUDIO_L_IN

6

B_GND

5

AUDIO_GND

4

AUDIO_L_OUT

3

AUDIO_R_IN

2

AUDIO_R_OUT

1

R122

+5V

DTV/MNT_VOUT

R154

5.6K
EU

R152

6.8K
EU

L103

120-ohm

EU

AZ4580MTR-E1

OUT1

1

IN1-

2

IN1+

3

VEE

4

IC101

PDP L13
EAX65071305

JP112

JP113

JP114

P_17V

VCC

8

OUT2

7

IN2-

6

IN2+

5

5.6K
R153

EU

SCART1_Rout

JIG_GND

JP115

+3.3V

R104
10K

R105
1K

EU

R106
75

0

R108
75

R107
75

AV/SC1_DET

AV_DET

SC1_R+/COMP1_Pr+

SC1_G+/COMP1_Y+

SC1_B+/COMP1_Pb+

R113

D100

75

EU

20V

R114
10K

EU

AV_L_IN

AV_R_IN

R118
470K

R119

R120

2.7K

R129
0

EU

R123

C109
27pF

50V

EU

33
EU

R115

470K

R116
470K

C107

5600pF

50V

EU

C108

5600pF

50V

EU

R117

75
EU

EU

75

EU

EU

C102

100uF

16V
EU

R121
10K

R124

10K

C111
220pF

50V

EU

R126
12K

R127
12K

SC1_SOG_IN

AV/SC1_CVBS_IN

SC1_VOUT

SC1_FB

SC1_ID

AV/SC1_L_IN

AV/SC1_R_IN

Q100

MMBT3904(NXP)

EU

MMBT3904(NXP)

R134
100
1/4W
EU

Q101

EU

DTV_R_OUT

Q102

MMBT3904(NXP)

EU

E

B

R136

0

EU

R139

C

330

EU

R138

R137

2K
EU

R140

B

Q103
MMBT3906(NXP)
EU

R141

220

2K

EU

470

EU

C112
10uF
16V

EU

470

EU

C

E

R135

EU

C113
10uF

16V

EU

R144

470

EU

C

Q104

E

MMBT3904(NXP)

EU

R143
180

EU

C114
27pF

50V

EU

R145

6.8K
EU

C115
27pF

50V

EU

B

+3.3V_ST

R146
18K

EU

R147
10K

EU

R149
15K

EU

SCART1_Lout

R148
15K

EU

READY
R189
1K

C116

10uF

16V

EU

SCART1_MUTE

<CI SLOT>

BUF1_FE_TS_DATA[0-7]

BUF1_FE_TS_VAL_ERR

3.3V_CI

+3.3V

L101

120-ohm

EU

C136

0.1uF
16V
READY

BUF1_FE_TS_DATA[7]
BUF1_FE_TS_DATA[6]

BUF1_FE_TS_DATA[4]

BUF1_FE_TS_DATA[3]

BUF1_FE_TS_DATA[2]

BUF1_FE_TS_DATA[1]

BUF1_FE_TS_DATA[0-7]

BUF1_FE_TS_DATA[0]

BUF1_FE_TS_SYN

BUF1_FE_TS_CLK

+3.3V_CI

C137

0.1uF
16V
EU

BUF2_FE_TS_DATA[7]
BUF2_FE_TS_DATA[6]
BUF2_FE_TS_DATA[5]BUF1_FE_TS_DATA[5]
BUF2_FE_TS_DATA[4]

33EU

AR109

BUF2_FE_TS_DATA[3]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[1]
BUF2_FE_TS_DATA[0]

33EU

AR108

AR110

33

EU

BUF2_FE_TS_SYN
BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_CLK

BUF2_FE_TS_DATA[0-7]

BUF2_FE_TS_DATA[0-7]

/CI_CD1

CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

CI_IORD
CI_IOWR

BUF2_FE_TS_SYN

BUF2_FE_TS_DATA[0]
BUF2_FE_TS_DATA[1]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[3]

BUF2_FE_TS_DATA[4]
BUF2_FE_TS_DATA[5]
BUF2_FE_TS_DATA[6]

BUF2_FE_TS_DATA[0-7]

BUF2_FE_TS_DATA[7]

PCM_RST

/PCM_WAIT

REG

CI_TS_CLK
CI_TS_VAL

CI_TS_SYNC

CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]
CI_TS_DATA[3]

R150
10K
EU

+5V

/CI_CD2

+5V

R151

R102

10K

100

EU

EU

AR100 33

R100
R101

EU

R155 100

R156 33

EU

R157 33

EU

AR102 33

R103
100
EU

+5V_CI_ON

C101

C100

0.1uF

22uF

16V

10V

EU

EU

+3.3V_CI

EU

C105

0.1uF

VCC

20

EU

2OE

19

1Y1

18

2A4

17

1Y2

16

2A3

15

1Y3

14

2A2

13

1Y4

12

2A1

11

EU

33

EU

EU

16V

CI_ADDR[0]
PCM_A[7]
CI_ADDR[1]
PCM_A[6]
CI_ADDR[2]

PCM_A[5]

CI_ADDR[3]
PCM_A[4]

/PCM_OE
/PCM_WE
/PCM_IORD
/PCM_IOWR

PCM_A[12]
PCM_A[13]
PCM_A[14]
/PCM_REG

PCM_A[8]
PCM_A[9]
PCM_A[10]
PCM_A[11]

CI_DET

PCM_A[0]

CI_ADDR[7]

PCM_A[1]

CI_ADDR[6]

PCM_A[2]

CI_ADDR[5]

PCM_A[3]

CI_ADDR[4]

CI_OE

CI_WE
CI_IORD
CI_IOWR

CI_ADDR[8]
CI_ADDR[9]

REG

+3.3V_CI

EU

R165

TC74LCX244FT

10K

IC100

1OE

1

1A1

2

2Y4

3

1A2

4

2Y3

5

1A3

6

2Y2

7

1A4

8

2Y1

9

GND

10

AR105

AR106 33

AR107 33

JK102

10067972-000LF

EU

35
36

R111
10K
EU

R112
0

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

65
66
67
68

2

EU

READY

R109
10K

EU

33

EU

33

EU

EU

R110
0
READY

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

R128 0

18

READY

19
20
21
22
23
24
25
2660
2761
2862
2963
3064
31
32
33
34

G1G2

1

69

AR103

33

EU

R130 33 EU
R131 33 EU

R132 100

AR104

33

EU

PCM_D[3]
PCM_D[4]
PCM_D[5]
PCM_D[6]
PCM_D[7]

EU

PCM_D[0]
PCM_D[1]
PCM_D[2]

CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[9]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[12]
CI_ADDR[7]

CI_ADDR[6]
CI_ADDR[5]

CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

PCM_D[0-7]

R133
10K
EU

/PCM_CE

CI_OE

CI_WE
/PCM_IRQA

BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_CLK

CI_ADDR[0-14]

PCM_D[0-7]

CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[10]
CI_ADDR[11]

CI POWER ENABLE CONTROL

PCM_5V_CTL

+5V

R125

4.7K
READY

+5V

R184
10K
READY

+5V

R181
10K
EU

IN

EN

B

AP2151WG-7

5

4

R187
10K
EU

C

Q113
MMBT3904(NXP)
EU

E

IC102

READY

Q114
ZXMP3F30FHTA
EU

OUT

1

GND

2

FLG

3

+5V_CI_ON

L100

120-ohm

EU

D

S

C131

0.1uF

G

16V
READY

READY
C103

4.7uF
10V

C104

0.1uF
16V
EU

R198
10K
READY

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

L13

SCART,CI Slot

2012-09-20

1

7

<HDMI>

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

<IN/OUT>

<HDMI1_SIDE>

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11

CK+

10

D0-

9

D0_GND

8

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

JK201

HDMI1_SIDE

For CEC

CEC_REMOTE

R237
1K

R238

1.8K

R288

10K

+5V

5V_DET_HDMI_3

R244

3.3K

R289
10K

JP207

JP208

R268
100

MMBT3904(NXP)

C

Q202

E

R231
33

R246
33

B

R232
10K

CEC_REMOTE_S7

<HDMI2_REAR>

R209
10K

HPD3

DDC_SDA_3

DDC_SCL_3

CEC_REMOTE

CK-_HDMI3

CK+_HDMI3

D0-_HDMI3

D0+_HDMI3

D1-_HDMI3

D1+_HDMI3

D2-_HDMI3

D2+_HDMI3

HDMI2_REAR

20

JK200

SHIELD

19

18

17

16

15

14

13

12

11
10

SWITCH ADDED

USB1_OCD

R264

R258
33

D206

5.6V
ET_NET

R273
0
ET_NET

R280
0
ET_NET

10K

+3.3V

SIDE_USB_DM

SIDE_USB_DP

TP

TN

RP

RN

IC204

BD82020FVJ

OUT_3

8

OUT_2

7

OUT_1

6

OC

5

<SPDIF>

FIX_POLE

R291
0
ET_NET

R290
0
ET_NET

<COMPONENT>

JK208

PPJ234-02

[GN]E-LUG

6A

[GN]O-SPRING

5A

[GN]CONTACT

GROWTH

JK202

PPJ231-01

4A

[BL]E-LUG-S

7B

[BL]O-SPRING

5B

[RD]E-LUG-S

7C

[RD]O-SPRING_1

5C

[RD]CONTACT_1

4C

5D

[WH]O-SPRING

4E

[RD]CONTACT_2

5E

[RD]O-SPRING_2

6E

[RD]E-LUG

4

5

7

8

6

+5V

5V_DET_HDMI_1

R204

3.3K

JP201

JP202

MMBT3904(NXP)

C

Q200

E

R207
33

R208
33

R202
10K

B

R217
10K

DDC_SDA_1

DDC_SCL_1

HPD1

CEC_REMOTE

CK-_HDMI1

CK+_HDMI1

D0-_HDMI1

D0+_HDMI1

D1-_HDMI1

D1+_HDMI1

D2-_HDMI1

D2+_HDMI1

<AV (Growth & SCA)>

R200
1K

R201

1.8K

R281

R282

10K

10K

CK+

D0-

9

D0_GND

8

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

R251
75

R252
75

R253
75

R203
0

GROWTH

R230

75

GROWTH

GROWTH

VA208

VA210

VA209

R234
0

COMP2_Y+

COMP2_Pb+

COMP2_Pr+

R254

470K

VA216

R255

470K

VA217

+3.3V

R256 10K

R25710K

VA211

R259

10K

R266
1K

R265
10K

R267

1K

R262

12K

R263
12K

AV_R_IN

AV_L_IN

AV_DET

AV/SC1_CVBS_IN

VA212

AV2_DET

COMP2_DET

COMP2_L_IN

COMP2_R_IN

<SIDE USB>

10mm

JK209

USB DOWN STR EAM

C212

C213

0.1uF

10uF

16V

1234

5

10V

3AU04S-305-ZC-(LG)

<ETHERNET (T2 UK)>

JK210

XRJV-01V-0-D12-080

ET_NET

9

9

+2.5V

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

C200

0.1uF
16V
ET_NET

D200

5.6V
ET_NET

D204

5.6V
ET_NET

D205

5.6V
ET_NET

GND

1

IN_1

2

IN_2

3

EN

4

JK204

JST1223-001

1

2

Fiber Optic

3

4

+3.3V

GND

VCC

VINPUT

R270
10K
READY

+5V

C201

0.1uF
16V

R271

33

USB1_CTL

+5V

C219

R285

0.1uF
100

16V

C220
10pF
50V

SPDIF_OUT

<FOR COMMERCIAL>

<RS232C>

READY
R275
0

READY
R274

Q204

Commercial

0

+5V_ST

R228
10K

Commercial

C

E

P_JACK TO RS232C

R226
0

P_JACK TO RS232C

R227

0

JK203

SPG09-DB-009

Commercial

1

6

2

7

3

8

4

9

5

10

MMBT3904(NXP)

+3.3V_ST

JP241

R278

10K

MAX3232

R276 100

MAX3232

R277

100

R229
100K

Commercial

B

R233
100K

Commercial

10K

R279

TX

NON_Commercial

P602

12507WS-04L

5

+3.3V_ST

1

2

3

4

DOU T1

RIN 1

ROU T1

DIN 1

DIN2

ROUT2

R283 22

R284

MAX3232CDR

VCC

16

GND

15

14

13

12

11

10

9

22

IC206

MAX3232

PM_TXD

PM_RXD

1

2

3

4

5

6

7

8

C1+

V+

C1-

C2+

C2-

V-

DOUT2

RIN2

+3.3V_ST

MAX3232

C228

0.1uF
16V

C225

0.1uF

16V

MAX3232

MAX3232

C226

0.1uF
16V

MAX3232

C227

0.1uF
16V

MAX3232

C229

0.1uF
16V

<PHONE JACK>

JK206

PEJ027-04

PHONE JACK

(1) NON-OS Normal : O (RS232 Debug)

(2) NON-OS Commercial : O (PC Audio)
(3) OS Normal : X
(4) OS Commercial : O (PC Audio)

3

6A

7A

4

5

7B

6B

E_SPRING

T_TERMINAL1

B_TERMINAL1

R_SPRING

T_SPRING

B_TERMINAL2

T_TERMINAL2

VA213

Commercial

VA214

Commercial

Commercial

R218
470K

Commercial

Commercial

R219
470K

Commercial

R220
10K

R221
10K

R222
12K

Commercial

R223
12K

Commercial

<RGB PC>

JK205

SPG09-DB-010

Commercial

1

PC_R_IN

PC_L_IN

2

3

4

10

5

GND

<WIRED IR>

VA202

+3.3V

R224

10K

VA203

R225

1K

VA204

VA205

VA206

VA207

DSUB_R+

RGB_DDC_SDA
DSUB_G+

DSUB_HSYNC
DSUB_B+

DSUB_VSYNC

DSUB_DET

RGB_DDC_SCL
PC_SER_DATA

PC_SER_CLK

JK207

PEJ027-04

US_Commercial

E_SPRING

3

T_TERMINAL1

6A

B_TERMINAL1

7A

R_SPRING

4

T_SPRING

5

B_TERMINAL2

7B

T_TERMINAL2

6B

Commercial

Commercial

R213
0
NON_Commercial

R21 0
10
US_Commercial

IR

TX

VA200

+5V_ST

R298

R297

10K

6

7

8

9

RED_GND
GND_2

11

RED
GREEN_GND
DDC_DATA

12

GREEN
BLUE_GND
H_SYNC

13

BLUE
NC
V_SYNC

14

GND_1
SYNC_GND
DDC_CLOCK

15

DDC_GND

16

SHILED

10K

R205
33

R206
33

NON_Commercial

P603

12507WS-04L

5

R214
75

R215
75

R216
75

C203

C202

10pF

10pF

50V

50V

R212
10

R211
10

1

2

3

4

RGB_DDC_SDA

RGB_DDC_SCL

VA201

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

L13

JACK INTERFACE

2012-06-01

2

7

TUNER OPT1

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

OPT2

OPT3

OPT4

TU301

TU302

TU303

TU304

TU305

TU306

+1.25V_TU

C314

10uF

FNIM

6.3V

C315

0.1uF
FNIM

16V

B1

TDSS-G501D
TDSH-G501D

TDSS-H501F ATSC

TDSN-T501F
TDSN_B601F

TDSQ_G605D

Close to Tuner Pin

TU306
TDSQ-G605D

DVB_T2

B1

36

SHIELD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

A1

NC_1

RESET

SCL

SDA

+B1[3.3V]

SIF

+B2[1.8V]

CVBS

NC_2

NC_3

NC_4

NC_5

NC_6

NC_7

GND

ERROR

SYNC

VALID

MCLK

D0

D1

D2

D3

D4

D5

D6

D7

GND_1

GND_2

+B3[1.23V]

T2_RESET

+B4[3.3V]

NC_8

T2_SCL

T2_SDA

A1

TU_GND

DVB-T/C

China

HNIM
HNIM

HNIM

DVB-T_SCA

SBTVD

DVB_T2

TU305
TDSN-B601F

SBTVD

B1

B1

28

C316
68pF

50V

SHIELD

RF_S/W_CTL

1

RESET_TUNER

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

NC_1

9

NC_2

10

NC_3

11

+B3[3.3V]

12

+B4[1.23V]

13

RESET_DEMOD

14

GND

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

27

A1

A1

C317
68pF
50V

R315

R318

TU_GND

R313

1.5K

22

22

R336

0

SBTVD

R335 0
SBTVD

+3.3V_TU

R314

1.5K
T2_SCL

T2_SDA

HNIM
FNIM
FNIM

FE_TS_DATA[0]

FE_TS_DATA[1]

FE_TS_DATA[2]

FE_TS_DATA[3]

FE_TS_DATA[4]

FE_TS_DATA[5]

FE_TS_DATA[6]

FE_TS_DATA[7]

+3.3V_TU

R304

100

FNIM

FE_TS_SYN

R305

10K

FNIM

X
X

X

RF_SW
RF_SW

X

B1

FE_TS_VAL_ERR

FE_TS_CLK

FE_TS_DATA[0-7]

DEMOD_RESET

B1

W/O AD
W/O AD

W/O AD

W/O AD
With AD
With AD

TU304
TDSH-T101F

CO_PANAMA

1

2

3

4

5

6

7

8

9

10

11

A1

12

SHIELD

FE_TS_VAL_ERR

RF_S/W_CTL

RESET

SCL

SDA

+B1[3.3V]

SIF

+B2[1.8V]

CVBS

IF_AGC

DIF[P]

DIF[N]

A1

TU_GND

FE_TS_DATA[2]
FE_TS_DATA[3]

FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]
FE_TS_DATA[7]

FE_TS_SYN

FE_TS_CLK

B1

FE_TS_DATA[0-7]

FE_TS_DATA[0]
FE_TS_DATA[1]

ATSC

B1

12

SHIELD

R323 0 FNIM
R324 0 DVB_T2
R326 0 DVB_T2
R325 0 DVB_T2

R327 0 DVB_T2
R328 0 DVB_T2
R330 0 DVB_T2
R329 0

R331 0 FNIM
R333 0 FNIM
R332 0 FNIM

TU303
TDSS-H501F

NC

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

ALIF_[N]

6

+B2[1.8]

7

ALIF_[P]

8

IF_AGC

9

DIF[P]

10

DIF[N]

11

A1

A1

DVB_T2

CHINA

B1

B1

B2

TU_GND

BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]

BUF1_FE_TS_DATA[4]
BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

BUF1_FE_TS_SYN
BUF1_FE_TS_VAL_ERR
BUF1_FE_TS_CLK

B2

TU302
TDSH-G501D

NC

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

IF_AGC

9

DIF[P]

10

DIF[N]

11

A1

A1

A2

A2

BUF1_FE_TS_DATA[0-7]

TU_GND

RF_SWITCH

R310
1K

+1.8V_TU

+5V

R317
82

E

MMBT3906(NXP)
Q301

C

TU_CVBS

RF_SWITCH_CTL

C311

0.1uF
16V

TU_SIF

C307

0.1uF

16V

RF_SWITCH

+3.3V_TU

TU301
TDSS-G201D

DVB_T/C

B1

B1

12

SHIELD

1

2

3

4

5

6

7

8

9

10

11

A1

NC_1

RESET

SCL

SDA

+B1[3.3V]

NC_2

+B2[1.8V]

NC_3

IF_AGC

DIF[P]

DIF[N]

A1

TU_GND

C302

0.1uF
16V

C303
10uF

16V

16V

0.1uF
C306

C310

C304
68pF

0.1uF
16V

R320

2K

DVB_T/C OPT

430
R319

C305

68pF

50V

50V

Close to Tuner Pin

430

R322

Close to Tuner Pin

TU_GND

0

0

R338

R337

H_NIM

+3.3V_TU

R308

1.5K

R301

100

R307

22

R306

22

Close to Tuner Pin

R3030

A-DEMODE OPT

C308

0.1uF

16V

R339 0

A_DEMODE

+3.3V_TU

R340
220

READY

E

B

C

R309

R311

1.5K

10K
TUNER_RESET

TU_SCL

TU_SDA

IF_AGC_MAIN

IF_P_MSTAR

IF_N_MSTAR

R316
470

R312

B

4.7K

R341

220

READY

Q302

MMBT3906(NXP)

READY

DVB-T2 OPT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TUNER

L13

Tuner block

2012-06-01

3

7

<ANALOG & DIGITAL INPUT>

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

DSUB_R+

DSUB_G+

DSUB_B+

DSUB_HSYNC
DSUB_VSYNC

R420 10K
R421 2.4K

SC1_R+/COMP1_Pr+

SC1_G+/COMP1_Y+

SC1_B+/COMP1_Pb+

SC1_SOG_IN

COMP2_Pr+

COMP2_Y+

COMP2_Pb+

TU_CVBS

AV/SC1_CVBS_IN

COMP2_Y+

R435

68

R436 33 C415
R437 68 C416 0.047uF
R438 33
R428 68 C418 0.047uF
R429 33

R422 22
R423 22

R441 68
R442 33
R430 68
R431 33

R445 68
R446 33
R433 68
R434 33

L409

R439

68

R440 33

R432

READY

0
R443

68

R444 33

A_DEMODE

R424 33

R426 33

R427 68

DTV/MNT_VOUT

C417 0.047uF

C419 0.047uF
C420 1000pF

C423 0.047uF
C424 0.047uF
C425 0.047uF
C426 0.047uF
C427 1000pF

SC1_ID
SC1_FB

C430 0.047uF
C433 0.047uF
C437 0.047uF
C439 0.047uF
C443 1000pF

LGE2111C-MS (PDP_13_MS10)

C414 0.047uF

C421 0.047uF
C422

C428 0.047uF
C429

A_DEMODE

C447 0.047uF
C448 0.047uFR425 33
C449 0.047uF

C413 0.047uF

0.047uF

0.047uF

0.047uF

M1
M2
L3
L2
K2
K1
K3
J2
J3

R3
R1
R2
P3
N3
N2
P2
R7
R5

V1
V2
U3
U2
T2
T1
T3

T5
T4
T6

U4

T7

RIN0M
RIN0P
GIN0M
GIN0P
BIN0M
BIN0P
SOGIN0
HSYNC0
VSYNC0

RIN1M
RIN1P
GIN1M
GIN1P
BIN1M
BIN1P
SOGIN1
HSYNC1
VSYNC1

RIN2M
RIN2P
GIN2M
GIN2P
BIN2M
BIN2P
SOGIN2

CVBS0
CVBS1
CVBS2

VCOM

CVBSOUT2

IC400

MS10

LED0/GPIO55
LED1/GPIO56

USB1_DM
USB1_DP

HWRESET

IRIN/GPIO4

XOUT

A2

RN

B2

RP

B1

TN

C2

TP

A3
C3

AE9
AD9

K4

C6

AE4

XIN

AD4

AV/SC1_DET

R448

49.9

1M

R447

X-TAL_12GND_1

R449

49.9

C450

0.1uF

GND_2

R454

49.9

SIDE_USB_DM
SIDE_USB_DP

SOC_RESET

TX

X-TAL_2

4

3

X400

24MHz

1

R455

49.9

C454

0.1uF

C451 10pF

C452 10pF

#POWER FOR MAIN#

<VDDC 1.05V>

+1.26V_VDDC

10uFC455

10uFC457

10uF

C465

<DDR3 1.5V>

+1.5V_DDR

L402

BLM18PG121SN1D

C432

0.1uF

+3.3V

B51_no_EJ : 4’b0000 Boot from 8051 with SPI flash
SB51_WOS : 4’b0001 Secure B51 without scramble
SB51_WS : 4’b0010 Secure B51 with scramble
MIPS_SPE_NO_EJ : 4’b0100 Boot from MIPS with SPI flash
MIPS_SPI_EJ_1 : 4’b0101 Boot from MIPS with SPI flash
MIPS_SPI_EJ_2 : 4’b0110 Boot from MIPS with SPI flash
MIPS_WOS : 4’b1001 Secure MIPS without scramble

OS

MIPS_WS : 4’b1010 Scerur MIPS with SCRAMBLE

R462 1K

NON_OS

R461 1K

R459 1K

R472 1K

R463 1K

R470 1K

<CHIP Config>
(I2S_OUT_BCK,I2S_OUT_MCK,PAD_PWM1PAD_PWM0)

<CHIP Config(LED_R/BUZZ)>
Boot from SPI CS1N(EXT_FLASH) 1’b0
Boot from SPI_CS0N(INT_FLASH) 1’b1

C467 1uF

C436

C472 1uF

10uF

LED_RED

AUD_SCK

AUD_MASTER_CLK

PWM1

PWM0

0.1uF

0.1uF

0.1uF

C478

C480

C474

AVDD_DDR0:55mA

DECAP READY FOR TEST

C442

AVDD_DDR1:55mA

0.1uF

C482 0.1uF

C4003

0.1uF

C484 0.1uF

C4004

C487 0.1uF

AVDD_MIU

C444

0.1uF

VDDC : 2026mA

0.1uF

4V

C491 0.1uF

DECAP FOR SOC
(HIDDEN - UCC)

READY

1uF

C446

0.1uF

C492

C453

0.1uF
4V

C490 0.1uF

C445

0.1uF

C453 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE

DECAP FOR SOC (HIDDEN - UCC)

READY

4V

4V

0.1uF

C493

0.1uF

C4000

C4000,C4005,C4006 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE

<Normal 2.5V>

+2.5V

L405
BLM18PG121SN1D

L406

BLM18PG121SN1D

BLM18SG121TN1D

+3.3V

FHD

READY

MODEL_OPT_1

R409 1K

R475 1K

RF_SWITCH_CTL

PIN NAME

HD

MODEL_OPT_0
MODEL_OPT_1

R405 1K

R410 1K

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+1.26V_VDDC

READY

READY

4V

4V

4V

0.1uF

0.1uF

C4006

C4005

AVDD2P5

AVDD2P5:172mA

AVDD25_PGA

C477

0.1uF

L407

Close to IC with width trace

AVSS_PGA

<HW_OPT>

MODEL OPTION

PIN NO.

AB3

F4

C485

0.1uF

DECAP FOR SOC (HIDDEN - UCC)

LOW

FHD

<GPIO& LVDS> <VCC &GND>

LGE2111C-MS (PDP_13_MS10)

R473

0

R415 22
R416 22

AA22

PWM0/GPIO66

Y22

PWM1/GPIO67

V24

PWM2/GPIO68

U23

PWM3/GPIO69

T22

PWM4/GPIO70

C7

PWM_PM/GPIO199

E7

SAR0/GPIO31

D7

SAR1/GPIO32

J6

SAR2/GPIO33

D1

SAR3/GPIO34

C1

SAR4/GPIO35

A5

R40733

PM_SPI_SCK/GPIO1

B5

PM_SPI_SDI/GPIO2

B4

R41333

PM_SPI_SDO/GPIO3

C4

R41433

PM_SPI_SCZ1/GPIO_PM[6]/GPIO12

B3

R41222 EU

PM_SPI_SCZ2/GPIO_PM[10]/GPIO16

D3

PM_SPI_CZ0/GPIO_PM[12]/GPIO0

E2

DDCA_CK/UART0_RX

D2

DDCA_DA/UART0_TX

E5

UART1_RX/GPIO44

E4

UART1_TX/GPIO43

U24

UART2_RX/GPIO64

U25

UART2_TX/GPIO65

D4

PM_UART_TX/GPIO_PM[1]/GPIO7

D5

PM_UART_RX/GPIO_PM[5]/GPIO11

AA21

I2C_SCKM2/DDCR_CK/GPIO72

AB21

I2C_SDAM2/DDCR_DA/GPIO71

RN
RP
TN
TP

*H/W opt :
ETHERNET

COMP2_DET

LED_RED

17V_DET

VS_DET

SPI_SCK
SPI_SDI
SPI_SDO
/SPI_CS

SCART1_MUTE

AMP_MUTE

RGB_DDC_SCL
RGB_DDC_SDA

UART_RXD
UART_TXD

PM_RXD
PM_TXD
PM_TXD
PM_RXD

KEY1
KEY2

I2C_SCL
I2C_SDA

PWM0

PWM1

for SYSTEM EEPROM

M5

R411

AC_DET

DISP_EN

1K

RL_ON
VS_ON

/FLASH_WP

5V_ON

R418 100

R417100

GPIO_PM[0]/GPIO6

L7

GPIO_PM[2]/GPIO8

J4

GPIO_PM[4]/GPIO10

L5

GPIO_PM[8]/GPIO14

L6

GPIO_PM[9]/GPIO15

L4

GPIO_PM[11]/GPIO17

<Normal Power 3.3V>

+3.3V

C431 0.1uF

VDD33

L401

BLM18PG121SN1D

10uFC434

10uFC435

<STby 3.3V>

C4001 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE

READY

C4001

C489

0.1uF

0.1uF
4V

4V

+3.3V_ST

AVDD_NODIE

L400

BLM18PG121SN1D

<SOC_RESET>

+3.3V_ST

C497
10uF
10V

HIGH

HD

D400
BAW56 GEANDE

R403

100K

IC400

MS10

DECAP FOR SOC
(HIDDEN - UCC)

READY

C440 0.1uF

C438 0.1uF

C441 0.1uF

C4002 0.1uF

C4002 SHOULD NEAR MAIN IC

AVDD_NODIE:7.362mA

C401

0.1uF

R408

10

C402

0.1uF

SOC_RESET

LVB0M
LVB0P
LVB1M
LVB1P
LVB2M

LVB2P
LVBCKM
LVBCKP

LVB3M

LVB3P

LVB4M

LVB4P

LVA0M

LVA0P

LVA1M

LVA1P

LVA2M

LVA2P
LVACKM
LVACKP

LVA3M

LVA3P

LVA4M

LVA4P

GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO45
GPIO46
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54

W24
V23
W23
W25
Y24
Y25
AA24
Y23
AB24
AA23
AB23
AB25

AC24
AC25
AD24
AD25
AC23
AE24
AD23
AE23
AD22
AC22
AD21
AC21

N5
A6
M6
R4
P5
D6
M4
C8
C5
E6
E3
K5
B7
K7
J5

R464

2.2K

EU

R419

RXB4­RXB4+
RXB3­RXB3+
RXBCK­RXBCK+
RXB2­RXB2+
RXB1­RXB1+
RXB0­RXB0+

RXA4­RXA4+
RXA3­RXA3+
RXACK­RXACK+
RXA2­RXA2+
RXA1­RXA1+
RXA0­RXA0+

22

PCM_D[0-7]

PCM_A[0-14]

+5V

R474

2.2K

5V_DET_HDMI_1

DEMOD_RESET

5V_DET_HDMI_3

AMP_RESET_N
TUNER_RESET
PCM_5V_CTL

CI_DET
AMP_SCL
AMP_SDA
MODEL_OPT_1
RF_SWITCH_CTL
AV2_DET
DSUB_DET

EU

R458
10K

/PCM_IRQA

/PCM_IOWR

/PCM_IORD

R460
10K

/PCM_WAIT

EU

/PF_OE
/PF_WE

PF_ALE

/F_RB

R450

R451

2.2K

2.2K

PCM_D[0-7]

PCM_RST

/PCM_OE

/PCM_CE
/PCM_WE
/CI_CD1

/PCM_REG

/CI_CD2

USB1_OCD
USB1_CTL

/PF_WP
/PF_CE0
/PF_CE1

+3.3V

R452

2.2K

D0-_HDMI1
D0+_HDMI1
D1-_HDMI1
D1+_HDMI1
D2-_HDMI1
D2+_HDMI1
CK-_HDMI1
CK+_HDMI1
DDC_SCL_1
DDC_SDA_1
HPD1

D0-_HDMI3
D0+_HDMI3
D1-_HDMI3
D1+_HDMI3
D2-_HDMI3
D2+_HDMI3
CK-_HDMI3
CK+_HDMI3
DDC_SCL_3
DDC_SDA_3
HPD3

CEC_REMOTE_S7

P_SDA

SPDIF_OUT

PCM_D[0]
PCM_D[1]
PCM_D[2]
PCM_D[3]
PCM_D[4]
PCM_D[5]
PCM_D[6]
PCM_D[7]

PCM_A[0]
PCM_A[1]
PCM_A[2]
PCM_A[3]
PCM_A[4]
PCM_A[5]
PCM_A[6]
PCM_A[7]
PCM_A[8]
PCM_A[9]
PCM_A[10]
PCM_A[11]
PCM_A[12]
PCM_A[13]
PCM_A[14]

R457 22

R456 22EU

AR401

OS

22

R453

2.2K

<HDMI& SOUND>

LGE2111C-MS (PDP_13_MS10)

F2

A_RX0N

G1

A_RX0P

G2

A_RX1N

G3

A_RX1P

H2

A_RX2N

H3

A_RX2P

F3

A_RXCN

F1

A_RXCP

H5

DDCDA_CK/GPIO23

H4

DDCDA_DA/GPIO24

H6

HOTPLUGA/GPIO19

AC6

C_RX0N

AD7

C_RX0P

AC7

C_RX1N

AD8

C_RX1P

AE8

C_RX2N

AC8

C_RX2P

AE6

C_RXCN

AD6

C_RXCP

AC5

DDCDC_CK/GPIO27

AE5

DDCDC_DA/GPIO28

AD5

HOTPLUGC/GPIO21

K6

HOTPLUGD/GPIO22

R6

CEC/GPIO5

B6

R406

M7

SPDIF_IN/GPIO152

SPDIF_OUT/GPIO153

22

<PCM & CI>

LGE2111C-MS (PDP_13_MS10)

AB17

PCMDATA0/GPIO126

AB19

PCMDATA1/GPIO127

Y16

PCMDATA2/GPIO128

AD15

PCMDATA3/GPIO120

AE15

PCMDATA4/GPIO119

AD14

PCMDATA5/GPIO118

AB15

PCMDATA6/GPIO117

AC16

PCMDATA7/GPIO116

Y17

PCMADR0/GPIO125

AA16

PCMADR1/GPIO124

AB16

PCMADR2/GPIO122

AD16

PCMADR3/GPIO121

Y18

PCMADR4/GPIO99

AE20

PCMADR5/GPIO101

Y19

PCMADR6/GPIO102

AC20

PCMADR7/GPIO103

AB18

PCMADR8/GPIO108

AD17

PCMADR9/GPIO110

AC15

PCMADR10/GPIO114

AE17

PCMADR11/GPIO112

AA19

PCMADR12/GPIO104

AA18

PCMADR13/GPIO107

AC19

PCMADR14/GPIO106

AA17

PCM_RESET/GPIO129

AD20

PCMIRQA_N/GPIO105

AC18

PCMIOWR_N/GPIO109

AE14

PCMOE_N/GPIO113

AD18

PCMIORD_N/GPIO111

AC17

PCMCE_N/GPIO115

AD19

PCMWE_N/GPIO197

AE21

PCMCD_N/GPIO130

EU

AE18

C456

22

0.1uF
16V

EU

AR400

OS

PCMREG_N/GPIO123

W16

PCMWAIT_N/GPIO100

Y21

PCM2_CD_N/GPIO135

Y20

PCM2_RESET/GPIO134

AA20

PCM2_CE_N/GPIO131

AB22

PCM2_IRQA_N/GPIO132

AB20

PCM2_WAIT_N/GPIO133

AD10

NF_ALE/GPIO141

Y9

NF_WPZ/GPIO198

AA10

NF_CEZ/GPIO137

Y10

NF_CLE/GPIO136

AB10

NF_REZ/GPIO139

AC9

NF_WEZ/GPIO140

AC10

NF_RBZ/GPIO142

I2C_SDA
I2C_SCL
P_SDA
P_SCL

UART_RXD
UART_TXD

IC400

IC400

MS10

MS10

EARPHONE_OUTL
EARPHONE_OUTR

I2S_IN_BCK/GPIO150

I2S_IN_SD/GPIO151
I2S_IN_WS/GPIO149

I2S_OUT_BCK/GPIO156
I2S_OUT_MCK/GPIO154

I2S_OUT_WS/GPIO155
I2S_OUT_SD/GPIO157

TS1DATA0/GPIO88
TS1DATA1/GPIO89
TS1DATA2/GPIO90
TS1DATA3/GPIO91
TS1DATA4/GPIO92
TS1DATA5/GPIO93
TS1DATA6/GPIO94
TS1DATA7/GPIO95

TS1CLK/GPIO98
TS1VALID/GPI96
TS1SYNC/GPIO97

TS0DATA0/GPIO77
TS0DATA1/GPIO78
TS0DATA2/GPIO79
TS0DATA3/GPIO80
TS0DATA4/GPIO81
TS0DATA5/GPIO82
TS0DATA6/GPIO83
TS0DATA7/GPIO84

TS0CLK/GPIO87

TS0VALID/GPIO85

TS0SYNC/GPIO86

SIFP
SIFM

IF_AGC

GPIO73

GPIO74
I2C_SCKM1/GPIO75
I2C_SDAM1/GPIO76

AUOUTL2
AUOUTR2

AUVRP
AUVAG
AUVRM

IP
IM

AUL1
AUR1
AUL3
AUR3
AUL4
AUR4

Y14
AA14
AD13
Y13
AA13
AD12
AC12
W10
AB13
AC14
W13

AB12
AD11
W9
AE11
AB11
AE12
AC13
AB14
AA11
Y11
AC11

AC3
AD2

AD1
AD3

AC2

AB3
AC4
AE3
AE2

C403 2.2uF

Y3

C404

AA2

C405

AA1
AA3

C406 2.2uF

W3

C407 2.2uF

Y2

C408 2.2uF

AA9
AB9

AB4
AB5

Y5
AA4
AA5

4.7uF
C409

C10
B10

R401

B9

R402

R404
A9
B8
A8
C9

BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]
BUF1_FE_TS_DATA[4]
BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]
CI_TS_DATA[3]
CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

C458
2pF

EU

50V

R466 100

R465 100

AUDIO IN

AV/SC1_L_IN

2.2uF
AV/SC1_R_IN

2.2uF
COMP2_L_IN

COMP2_R_IN
PC_L_IN
PC_R_IN

AUDIO OUT

SCART1_Lout
SCART1_Rout

0.1uF

1uF

C411

C410

T2_SCL

22DVB_T2

T2_SDA

22DVB_T2

P_SCL

22

AUD_SCK
AUD_MASTER_CLK

AUD_LRCK

AUD_LRCH

I2S_I/F

Internal demod out

CI_TS_DATA[0-7]

CI_TS_CLK
CI_TS_VAL
CI_TS_SYNC

from CI SLOT

Close to MSTAR

C462

H_NIM

C461

H_NIM

A_DEMODE
C459 0.1uF
C460 0.1uF

A_DEMODE

ANALOG SIF

Close to MSTAR

TU_SCL
TU_SDA

TUNER_I2C

10uF
C412

L408

BLM18SG121TN1D

T2_I2C

BUF1_FE_TS_DATA[0-7]

BUF1_FE_TS_CLK
BUF1_FE_TS_VAL_ERR
BUF1_FE_TS_SYN

100pF

C463

READY

100pF

C464

READY

0.1uF

H_NIM

0.1uF

H_NIM

A_DEMODE
R467 47
R468 47

A_DEMODE

+3.3V

L410

0.1uF
H_NIM

C468

L13

MAIN

H_NIM

BLM18PG121SN1D

H_NIM
R469
10K

H_NIM
R471

+1.26V_VDDC

+1.26V_VDDC

AVDD2P5

AVDD25_PGA
AVSS_PGA

AVDD_NODIE

VDD33

C466 1uF

AVDD_MIU

DTV_IF

IF_P_MSTAR

IF_N_MSTAR

TU_SIF

NON_A_DEMODE
AGC 1.25V
100 OHM SERIAL
A_DEMODE 0ohm

100

C469

0.047uF
25V

H_NIM

Close to MSTAR

LGE2111C-MS (PDP_13_MS10)

P17
R17
R18
T17
T18
U18

J9

J11

P8

R8
U11
V10

U17

P18

Y8
AA8
AB8

AB1
AB2

W4

W5

W6

Y6
AA6

W7

Y4

J14
J15
J16
K16

J17
L16
L17
M16

J8

K8

R19
R23
T23

U5

U6

V3

V4
V11
V15
V16
V17
V18
V19
V20
V21

W1

W2
W11
W15
W17
W18
W20
W21
W22

Y7
AA7
AB6
AB7

IF_AGC_MAIN

IC400

MS10

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12

AVDDLV

DVDD_DDR

AVDD25_LAN
AVDD2P5_DADC
AVDD_MOD

AVDD25_PGA
AVSS_PGA

AVDD_NODIE
AVDD_DMPLL

AVDD_DVI_USB_MPLL
AVDD_AU33
VDDP
AVDD_PLL

DVDD_NODIE

AVDD_DDR0_C
AVDD_DDR0_D_1
AVDD_DDR0_D_2
AVDD_DDR0_D_3

AVDD_DDR1_C
AVDD_DDR1_D_1
AVDD_DDR1_D_2
AVDD_DDR1_D_3

GND_EFUSE
TEST

GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8

GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90

2012-06-201

4

A15
A17
A20
B14
B16
B18
B21
C11
C12
C13
C20
C23
C25
D23
E17
E18
E20
E23
F4
F5
F6
F7
F18
G4
G5
G6
G7
G10
G12
G15
G19
G20
G24
H7
H10
H12
H13
H14
H15
H19
H25
J1
J7
J12
J13
J19
J20
J24
K12
K13
K14
K15
K18
K19
K25
L8
L12
L13
L14
L15
L18
L19
L20
L24
M3
M8
M12
M13
M14
M15
M17
M18
M19
M24
N1
N7
N13
N14
N15
N16
N17
N18
N19
N20
N25
P13
P14
P19
P21
P24

7

Key/IR

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

Commercial

IR

+3.3V_ST

R540

10K

KEY1

KEY2

LED_RED

NON OS

+3.3V_ST

R515

4.7K

/SPI_CS

SPI_SDO

R542
10K

R516
100

C535

0.1uF

READY

0.1uF

16V

C557

R518
100

R517
100

R514
22

C517
10pF

50V

C534

0.1uF
16V

C520
10pF

50V

+3.3V_ST

READY

R580

10K

0.1uF

D502

D503 20V

D504 20V

+3.3V_ST

C547

16V

D501

MX25L6406EMI-12G

HOLD#

VCC

NC_1

NC_2

NC_3

NC_4

CS#

SO/SIO1

20V

D505

LVDS

P501

12507WR-06L

1

2

3

4

5

6

7

20V

20V

READY
IC506

1

2

3

4

5

6

7

8

SCLK

16

R581

SI/SIO0

NC_8

NC_7

NC_6

NC_5

GND

WP#

33

READY

15

14

13

12

11

10

9

SPI_SCK

SPI_SDI

/FLASH_WP

P503

TF05-51S

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

HD

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

104060-8017

RXA0­RXA0+
RXA1­RXA1+

RXA2­RXA2+

RXACK­RXACK+

RXA3­RXA3+
RXA4­RXA4+

RXB0­RXB0+
RXB1­RXB1+

RXB2­RXB2+

RXBCK­RXBCK+

RXB3­RXB3+
RXB4­RXB4+

P500

FHD

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

81

P_SDA

P_SCL

D500

MMBD6100

R522

+5V

R512

4.7K

READY
R521

0

READY

R513

4.7K

R519
R520 0

C518
470pF
READY

0

A2CA1

2K
R579

RXA0­RXA0+
RXA1­RXA1+

RXA2­RXA2+

RXACK­RXACK+
RXA3­RXA3+
RXA4­RXA4+

RXB0­RXB0+
RXB1­RXB1+

RXB2­RXB2+

RXBCK­RXBCK+
RXB3­RXB3+
RXB4­RXB4+

+5V

R577

4.7K

B

47K
R578

0

P_SDA
DISP_EN
P_SCL

PC_SER_DATA
PC_SER_CLK

C519
470pF
READY

PC_SER_DATA

PC_SER_CLK

C

E

Q500

MMBT3904(NXP)

@optio

UART_RXD

UART_TXD

LD500

NAND Flash
1GBit

/F_RB

/PF_OE

/PF_CE0

/PF_CE1

/PF_WP

R556

OS

3.3K

SERIAL FLASH

OS:8MB

IC505-*1

MX25L8006EM2I-12G

MX_OS

CS#

1

SO/SIO1

2

WP#

3

GND

4

NON_OS:64MB

IC505-*2

W25Q64FVSSIG

Winbond_NON-OS

CS

1

DO[IO1]

2

WP[IO2]

3

GND

4

NVRAM

OS:256KB

NON_OS:512KB

AT24C256C-SSHL-T(Cu)

ATMEL_OS

GND

AT24C512C-SSHD-T

ATMEL_NON-OS

A0

1

A1

2

A2

3

GND

4

A0

A1

A2

IC503-*3

IC503-*1

1

2

3

4



8

7

6

5

PF_ALE

/PF_WE

VCC

8

HOLD#

7

SCLK

6

SI/SIO0

5

8

7

6

5

8

7

6

5

VCC

WP

SCL

SDA

VCC

%HOLD[IO3]

CLK

DI[IO0]

VCC

WP

SCL

SDA

OS

R565
1K

OS

C550

0.1uF

R567

OS

1K

/SPI_CS

SPI_SDO

/FLASH_WP

IC505-*3

MX25L6406EM2I-12G

MX_NON-OS

CS

1

SO/SIO1

2

WP

3

GND

4

IC503-*2

M24256-BRMN6TP

ST_OS

E0

1

E1

2

E2

3

VSS

4

OS

R568

4.7K

+3.3V

8

7

6

5

8

7

6

5

VCC

HOLD

SCLK

SI/SIO0

VCC

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

R/B

NC_7

NC_8

VCC_1

VSS_1

NC_9

NC_10

CLE

ALE

NC_11

NC_12

NC_13

NC_14

NC_15

WC

SCL

SDA

IC504

H27U1G8F2CTR-BC

1

2

3

4

5

6

7

RE

8

CE

9

10

11

12

13

14

15

16

17

WE

18

WP

19

20

21

22

23

24

+3.3V_ST

+3.3V_ST

R569

R564

4.7K

10K

READY

DO[IO1]

%WP[IO2]

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

Winbond_OS

W25Q80BVSSIG

CS

1

2

3

GND

4

M24512-RMN6TP

E0

1

E1

2

ST_NON_OS

E2

3

VSS

4

IC505

IC503

NC_29

NC_28

NC_27

NC_26

I/O7

I/O6

I/O5

I/O4

NC_25

NC_24

NC_23

VCC_2

VSS_2

NC_22

NC_21

NC_20

I/O3

I/O2

I/O1

I/O0

NC_19

NC_18

NC_17

NC_16

8

7

6

5

8

7

6

5

+3.3V

OS

VCC

HOLD[IO3]

CLK

DI[IO0]

VCC

WC

SCL

SDA

AR518

C554
10uF

C555

0.1uF

AR519

0.1uF

OS
22

OS

10V

OS
22

C552

+3.3V_ST

R575
33

+3.3V

PCM_A[7]

PCM_A[6]

PCM_A[5]

PCM_A[4]

PCM_A[3]

PCM_A[2]

PCM_A[1]

PCM_A[0]

C556

0.1uF

SPI_SCK

SPI_SDI

R573
22

R574
22

Toshiba_OS

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

RY/BY

RE

CE

NC_7

NC_8

VCC_1

VSS_1

NC_9

NC_10

CLE

ALE

WE

WP

NC_11

NC_12

NC_13

NC_14

NC_15

PCM_A[0-7]

IC504-*1

TC58NVG0S3ETA0BBBH

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I2C_SCL

I2C_SDA

NC_29

48

NC_28

47

NC_27

46

NC_26

45

I/O8

44

I/O7

43

I/O6

42

I/O5

41

NC_25

40

NC_24

39

NC_23

38

VCC_2

37

VSS_2

36

NC_22

35

NC_21

34

NC_20

33

I/O4

32

I/O3

31

I/O2

30

I/O1

29

NC_19

28

NC_18

27

NC_17

26

NC_16

25

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

* LCI: LVDS Connection Indicator

L13

Memory.LVDS,IR

2012-06-01

5

7

POWER & AMP

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

<ST-BY>

<Power Wafer>

+3.3V_ST

R601

R600

10K

10K

READY
RL_ON
5V_ON

4.7K
R604

<MUTI>

+5V->+3.3V_DDR

+5V

AP1117E33G-13

IN ADJ/GND

C611
10uF
10V

600mA

IC605

OUT

P600

SMAW200-H18S1

1
3
5
7
9

10
12

11

14

13

16

15

18

17

19

2
4
6
8

+3.3V_DDR

R608
1

C627
10uF

6.3V

P_17V

C606

0.1uF
16V

+3.3V_ST

R624

15K

READY

L600

C607

0.1uF
16V

R609

100

120

C633
1000pF
50V

R606

4.7K
R639

VS_DET

10K

--> +1.5V_DDR

+3.3V_DDR

C618
10uF

6.3V

VS_ON

17V_DET

AC_DET

AZ1117BH-ADJTRE1

+5V_ST

C608
10uF
10V

400mA

IC613

INPUT ADJ/GND

OUTPUT

R1

R2

C610

0.1uF
16V

200

R673

1K

R674

+5V_ST

+1.5V_DDR

1%

1%

R675
1

C619
10uF

6.3V

C613
10uF
25V
READY

C620

C621

10uF

0.1uF

25V

50V

RL_ON

+5V->+2.5V

R617
33K
1%

C623
100pF
50V

R1

R619
51K
1%

R648

R2

R607

+5V_ST --> 3.3Vst

+5V

READY

C626
3300pF
50V

TPS54327DDAR

EN

VFB

VREG5

SS

1

2

3

4

10K

100

C624
1uF
10V

IC603

THERMAL

3A

[EP]GND

VIN

8

VBST

9

7

C628

L605

0.1uF
25V

SW

6

GND

5

2.2uH

+1.26V_VDDC

C650
10uF
16V

C629
10uF
16V

C630

0.1uF
16V

C609
10uF
16V

C603
10uF
16V

+5V_ST

C600
10uF
10V

C601

0.1uF
16V

VIN

300mA

IC600

AP2121N-3.3TRE1

2

3

1

GND

VOUT

+3.3V_ST

C604
1uF

6.3V

C634
10uF

6.3V

5V_STBY --> MULTI 5V1.26V Core

R670

0.1uF
16V

+5V

R671
10K
READY

RL_ON

+5V_ST

R657
10K
READY

R659
10K

B

R664

5%

10K

1/1 6W

C

Q603
MMBT3904(NXP)

E

3A

Q604
ZXMP3F30FHTA

D

S

G

READY

C602

2.2uF
10V

R667

0.1uF
16V
READY

L604

120

Vout=0.765*(1+R1/R2)

+5V->+3.3V

->+3.3V_TU

+5V

C605
10uF
10V

TJ1118S-2.5

IN

3

IC601

200mA

1

GND

+2.5V

OUT

2

R612
1

C612
10uF

6.3V

+5V

C616
10uF
10V

600mA

IC608

AP1117E33G-13

IN ADJ/GND

OUT

+3.3V

R662
1

C617
10uF

6.3V

D600

5V

L606

120-ohm

2A

READY

+3.3V_TU

+5V->+1.8V_TU

+5V

AZ1117BH-ADJTRE1

C615
10uF
10V

Vout=1.25*(1+R2/R1)

IC604

INPUT ADJ/GND

OUTPUT

R1

R2

100

220

R613

R614

5%

5%

+1.8V_TU

R621
1

C631
10uF

6.3V

+5V->+1.25V_TU

+5V

C614
10uF
10V
FNIM

400mA80mA

IC602

AP1117EG-13

FNIM

OUTIN

ADJ/GND

R6151FNIM

R618
240
FNIM

R1

R2

Vout=1.25*(1+R2/R1)

+1.25V_TU

R620
1
FNIM

C625
10uF

6.3V
FNIM

<AUDIO AMP>

+3.3V

L601

BLM18PG121SN1D

+3.3V_AMP

AUD_MASTER_CLK

AUD_SCK
AUD_LRCK
AUD_LRCH

AMP_MUTE

AMP_RESET_N

AMP_SDA

AMP_SCL

READY

C632
2pF
50V

R652
22

R653
22

+3.3V_AMP

C622

0.1uF

R628

4.7K

R611
33

C672

0.1uF

C673

2.2uF

AR600
100

R640

4.7K

+3.3V_AMP

16V

10V

+3.3V_AMP

R641

4.7K

NC_13
NC_14

NC_15
VDDDIG1
GNDDIG1

FFX3A

FFX3B

EAPD/FFX4A

TWARNEXT/FFX4B

VREGFILT

AGNDPLL

MCLK

READY

C674
33pF
50V

READY

C675
33pF
50V

25
26
27
28
29
30
31
32
33
34
35
36

NC_ 12

24

STA380BWF

39

37

SDI

BIC KI38LRC KI

NC_ 1023NC_ 11

22

21

IC606

40

RESET

NC_ 9

41

PWDN

NC_ 8

NC_ 7

20

19

42

SDA44SCL

INTLINE

L609

10.0uH

Coil_GET

L611

10.0uH

C681
1uF
50V

C684
330pF
50V

C685
330pF
50V

R636

R637

39

39

C686
1uF
50V

Coil_TAIYO

L602

10.0uH

Coil_GET

L612

10.0uH

Coil_TAIYO

L603

10.0uH

Coil_GET

L614

10.0uH

Coil_TAIYO

Coil_TAIYO

L615

10.0uH

L610

10.0uH

Coil_GET

C687

0.1uF
50V

C688

0.22uF
50V

C689

0.22uF
50V

C690

0.1uF
50V

P_17V

NC_ 6

NC_ 5

NC_ 4

NC_ 3

NC_ 2

NC_ 1

18

17

16

15

14

13

12 GND_REG
11 VDD_REG
10 OUT1A

9 GND1
8 VCC1
7 OUT1B
6 OUT2A
5 VCC2
4 GND2
3 OUT2B

49

THE RMAL

2 VSS_REG

45SA46

TESTMODE

1 VCC_REG

47

[EP]

GNDDIG248VDDDIG2

43

+3.3V_AMP

C677

0.1uF
16V

C678

0.1uF
16V

C679

0.1uF
50V

C680

0.1uF
50V

R632

R633

39

39

C691

0.22uF
50V

C692

0.22uF
50V

C693

0.22uF
50V

C694

0.22uF
50V

L616
CIS21J121

C695
68uF
35V

C696
1000pF
50V

C697
1000pF
50V

C698
1000pF
50V

C699
1000pF
50V

SPK_L+

SPK_L-

SPK_R+

SPK_R-

SPEAKER_L

SPEAKER_R

SPK_L+

SPK_L-

SPK_R+

SPK_R-

P601

WAFER-ANGLE

4

3

2

1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

L13

Power,AMP

2012-06-01

6

7

AVDD_DDR0

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

R1201

R1202

AVDD_DDR0

1K 1%

0.1uF

1K 1%

C1201

A-MVREFDQ

1000pF

C1202

R1204

R1205

1K 1%

0.1uF

1K 1%

C1203

A-MVREFCA

1000pF

C1204

B-MVREFCA

1000pF

OS

C1247

AVDD_DDR0

0.1uF
C1248

OS

AVDD_DDR0

L1202

CIC21J501NE

C1251

AVDD_DDR0

10uF

C1218

C1238

C1241

C1219

1uF

1uF

1uF

1uF

CLose to DDR3

+1.5V_DDR

1000pF

OS

C1249

0.1uF

OS

OS

OS

C1250

R1227

1K 1%

R1228

1K 1%

OS

R1224

1K 1%

B-MVREFDQ

OS

R1225

1K 1%

CLose to DDR3

A-MVREFCA

A-MVREFDQ

AVDD_DDR0

C1205 10uF
C1207 0.1uF
C1208 0.1uF
C1210 0.1uF
C1211 0.1uF
C1212 0.1uF
C1213 0.1uF
C1214 0.1uF
C1215 0.1uF
C1216 0.1uF

A-MA14

CLose to Saturn7M IC

M8

H1

R1203

L8

240

1%

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

EAN61836301

IC1201

K4B1G1646G-BCK0

SS_1G_1600

VREFCA

VREFDQ

ZQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

CLose to Saturn7M IC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

A-MA0
A-MA1
A-MA2
A-MA3
A-MA4
A-MA5
A-MA6
A-MA7
A-MA8
A-MA9
A-MA10
A-MA11
A-MA12
A-MA13

A-MBA0
A-MBA1
A-MBA2

A-MCKE

A-MODT
A-MRASB
A-MCASB
A-MWEB

A-MRESETB

A-MDQSL
A-MDQSLB

A-MDQSU
A-MDQSUB

A-MDML
A-MDMU

A-MDQL0
A-MDQL1
A-MDQL2
A-MDQL3
A-MDQL4
A-MDQL5
A-MDQL6
A-MDQL7

A-MDQU0
A-MDQU1
A-MDQU2
A-MDQU3
A-MDQU4

A-MDQU6
A-MDQU7

R1235

56

R1236

56

R1231
10K

A-MCK

1%

C1209

0.01uF
50V

1%

A-MCKB

AVDD_DDR0

CLose to DDR3

IC1201-*1

H5TQ1G63EFR-PBC

N3

A0

VREFCA

P7

A1

P3

A2

N2

A3

VREFDQ

P8

A4

P2

A5

R8

A6

ZQ

R2

A7

T8

A8

R3

A9

VDD_1

L7

A10/AP

VDD_2

R7

A11

VDD_3

N7

A12/BC

VDD_4

T3

NC_7

VDD_5
VDD_6

M7

NC_5

VDD_7
VDD_8

M2

BA0

VDD_9

N8

BA1

M3

BA2

VDDQ_1

J7

CK

VDDQ_2

K7

CK

VDDQ_3

K9

CKE

VDDQ_4
VDDQ_5

L2

CS

VDDQ_6

K1

ODT

VDDQ_7

J3

RAS

VDDQ_8

K3

CAS

VDDQ_9

L3

WE

NC_1

T2

RESET

NC_2
NC_3
NC_4

F3

DQSL

NC_6

G3

DQSL

C7

DQSU

VSS_1

B7

DQSU

VSS_2
VSS_3

E7

DML

VSS_4

D3

DMU

VSS_5
VSS_6

E3

DQL0

VSS_7

F7

DQL1

VSS_8

F2

DQL2

VSS_9

F8

DQL3

VSS_10

H3

DQL4

VSS_11

H8

DQL5

VSS_12

G2

DQL6

H7

DQL7

VSSQ_1

D7

DQU0

VSSQ_2

C3

DQU1

VSSQ_3

C8

DQU2

VSSQ_4

C2

DQU3

VSSQ_5

A7

DQU4

VSSQ_6

A2

DQU5

VSSQ_7

B8

DQU6

VSSQ_8

A3

DQU7

VSSQ_9

A_DDR3_A0
A_DDR3_A1
A_DDR3_A2
A_DDR3_A3
A_DDR3_A4
A_DDR3_A5
A_DDR3_A6
A_DDR3_A7
A_DDR3_A8
A_DDR3_A9
A_DDR3_A10
A_DDR3_A11
A_DDR3_A12
A_DDR3_A13
A_DDR3_A14
A_DDR3_DQL0
A_DDR3_DQL1
A_DDR3_DQL2
A_DDR3_DQL3
A_DDR3_DQL4
A_DDR3_DQL5
A_DDR3_DQL6
A_DDR3_DQL7
A_DDR3_DQU0
A_DDR3_DQU1
A_DDR3_DQU2
A_DDR3_DQU3
A_DDR3_DQU4
A_DDR3_DQU5
A_DDR3_DQU6
A_DDR3_DQU7
A_DDR3_CASZ
A_DDR3_RASZ
A_DDR3_WEZ
A_DDR3_DQML
A_DDR3_DQMU
A_DDR3_ODT
A_DDR3_BA0
A_DDR3_BA1
A_DDR3_BA2
A_DDR3_RESET
A_DDR3_MCLKE
A_DDR3_MCLK
A_DDR3_MCLKZ
A_DDR3_DQSL
A_DDR3_DQSBL
A_DDR3_DQSU
A_DDR3_DQSBU

IC400

B_DDR3_A0
B_DDR3_A1
B_DDR3_A2
B_DDR3_A3
B_DDR3_A4
B_DDR3_A5
B_DDR3_A6
B_DDR3_A7
B_DDR3_A8

B_DDR3_A9
B_DDR3_A10
B_DDR3_A11
B_DDR3_A12
B_DDR3_A13
B_DDR3_A14

B_DDR3_DQL0
B_DDR3_DQL1
B_DDR3_DQL2
B_DDR3_DQL3
B_DDR3_DQL4
B_DDR3_DQL5
B_DDR3_DQL6
B_DDR3_DQL7
B_DDR3_DQU0
B_DDR3_DQU1
B_DDR3_DQU2
B_DDR3_DQU3
B_DDR3_DQU4
B_DDR3_DQU5
B_DDR3_DQU6
B_DDR3_DQU7
B_DDR3_CASZ
B_DDR3_RASZ

B_DDR3_WEZ

B_DDR3_DQML
B_DDR3_DQMU

B_DDR3_ODT
B_DDR3_BA0
B_DDR3_BA1
B_DDR3_BA2

B_DDR3_RESET
B_DDR3_MCLKE

B_DDR3_MCLK

B_DDR3_MCLKZ

B_DDR3_DQSL

B_DDR3_DQSBL

B_DDR3_DQSU

B_DDR3_DQSBU

E22
G21
F20
E24
K20
F24
J21
F23
H22
G23
L21
G22
J22
G25
H20
P23
L25
R24
K23
T25
J23
T24
K24
N21
P22
L22
R21
P20
R22
M22
N22
D24
B25
F22
L23
R20
C24
D25
K22
E25
E21
M20
H23
H24
P25
N23
N24
M23

B_MA0
B_MA1
B_MA2
B_MA3
B_MA4
B_MA5
B_MA6
B_MA7
B_MA8
B_MA9
B_MA10
B_MA11
B_MA12
B_MA13
B_MA14
B-MDQL0
B-MDQL1
B-MDQL2
B-MDQL3
B-MDQL4
B-MDQL5
B-MDQL6
B-MDQL7
B-MDQU0
B-MDQU1
B-MDQU2
B-MDQU3
B-MDQU4
B-MDQU5
B-MDQU6
B-MDQU7
B_MCASB
B_MRASB
B_MWEB
B-MDML
B-MDMU
B_MODT
B_MBA0
B_MBA1
B_MBA2
B_MRESETB
B_MCKE
B-MCK
B-MCKB
B-MDQSL
B-MDQSLB
B-MDQSU
B-MDQSUB

B-MCK

OS

B-MCKB

AVDD_DDR0

C1240

0.01uF
50V

R1232

10K

OS

B-MA0
B-MA1
B-MA2
B-MA3
B-MA4
B-MA5
B-MA6
B-MA7
B-MA8

B-MA9
B-MA10
B-MA11
B-MA12
B-MA13

OS

56

1%

56

1%

OS

B-MODT

B-MRASB
B-MCASB

B-MWEB

B-MRESETB

B-MDQSL

B-MDQSLB

B-MDQSU

B-MDQSUB

B-MDML
B-MDMU

B-MDQL0
B-MDQL1
B-MDQL2
B-MDQL3
B-MDQL4
B-MDQL5
B-MDQL6
B-MDQL7

B-MDQU0
B-MDQU1
B-MDQU2
B-MDQU3
B-MDQU4
B-MDQU5A-MDQU5
B-MDQU6
B-MDQU7

R1237

B-MCKE
R1238

B-MBA0
B-MBA1
B-MBA2

LGE2111C-MS (PDP_13_MS10)

F9

M8

H1

L8

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

A_MA0
A_MA1
A_MA2
A_MA3
A_MA4
A_MA5
A_MA6
A_MA7
A_MA8

A_MA9
A_MA10
A_MA11
A_MA12
A_MA13
A_MA14

A-MDQL0
A-MDQL1
A-MDQL2
A-MDQL3
A-MDQL4
A-MDQL5
A-MDQL6
A-MDQL7
A-MDQU0
A-MDQU1
A-MDQU2
A-MDQU3
A-MDQU4
A-MDQU5
A-MDQU6
A-MDQU7
A_MCASB
A_MRASB

A_MWEB
A-MDML
A-MDMU
A_MODT
A_MBA0
A_MBA1
A_MBA2

A_MRESETB

A_MCKE

A-MCK
A-MCKB

A-MDQSL

A-MDQSLB

A-MDQSU

A-MDQSUB

MS10

E10

G9
C14
F11
A14
F10
C15
D11
C16
G13
E11
F12
B15
D10
B23
B19
A23
C19
B24
C18
A24
A18
D15
F17
F14
E16
D14
D16
E14
F16
A12
B11

E9
B20
D17
A11
B12
G11
B13

G8
F13
B17
C17
B22
C22
A21
C21

EAN61836301

IC1202

K4B1G1646G-BCK0

OS_SS_1G_1600

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

OS

R1226

240

1%

C1227 10uF

OS

C1228 0.1uF

OS

C1229 0.1uF

OS

C1230 0.1uF

OS

C1231 0.1uF

OS

C1232 0.1uF

OS

C1233 0.1uF

OS

C1234 0.1uF

OS

C1235 0.1uF

OS

C1236 0.1uF

OS

B-MVREFCA

B-MVREFDQ

AVDD_DDR0

B-MA14

H5TQ1G63EFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

NC_7

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

IC1202-*1

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

B-MA12
B-MBA1

B-MA10
B-MCKE

B-MA6
B-MA4

B-MA11

B-MA8

B-MRASB

B-MODT

B-MA1

B-MA14

AR1211 56

AR1203 56

OS

AR1212 56

AR1202 56

B_MA12

OS

B_MA10

OS

B_MCKE

B_MA6
B_MA4

B_MA11

OS

B_MA8

B_MRASB

OS

B_MODT

B_MA1

OS

B_MA14

B-MRESETB

AR1224 56

A-MA12
A-MBA1

A_MA12
A_MBA1

AR1223 56

A-MA10
A-MCKE

A_MA10
A_MCKE

AR1222 56

A-MA6
A-MA4

A_MA6
A_MA4

AR1221 56

A-MA11

A-MA8

A_MA11
A_MA8

A-MRESETB

AR1220 56

A-MRASB

A-MODT

A_MRASB
A_MODT

AR1219 56 AR1204 56

A-MA1

A-MA14

A_MA1
A_MA14

AR1217 56

A-MA13

A-MA9

A_MA13
A_MA9

AR1216 56 AR1207 56

A-MA0

A-MWEB

A_MA0
A_MWEB

AR1214 56

A-MA5
A-MA7

A_MA5
A_MA7

AR1218 56

A-MA2

A_MRESETB
A_MA2

AR1213 56

A-MCASB

A-MBA0

A_MCASB
A_MBA0

AR1215 56

A-MBA2

A-MA3

A_MBA2
A_MA3

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

B-MA13

B-MA9B_MBA1

B-MA0

B-MWEB

B-MA5
B-MA7

B-MA2

B-MCASB

B-MBA0

B-MBA2

B-MA3

AR1206 56

OS

AR1210 56

OS

AR1205 56

OS

AR1209 56

OS

AR1225 56

OS

AR1208 56

OS

B_MA13
B_MA9

B_MA0
B_MWEB

B_MA5
B_MA7

B_MRESETB
B_MA2

B_MCASB
B_MBA0

B_MBA2
B_MA3

<NONE MS10>

NONE_MS10

IC400-*1

LGE2111C (PDP_13_None MS10)

F9

A_DDR3_A0

E10

A_DDR3_A1

G9

A_DDR3_A2

C14

A_DDR3_A3

F11

A_DDR3_A4

A14

A_DDR3_A5

F10

A_DDR3_A6

C15

A_DDR3_A7

D11

A_DDR3_A8

C16

A_DDR3_A9

G13

A_DDR3_A10

E11

A_DDR3_A11

F12

A_DDR3_A12

B15

A_DDR3_A13

D10

A_DDR3_A14

B23

A_DDR3_DQL0

B19

A_DDR3_DQL1

A23

A_DDR3_DQL2

C19

A_DDR3_DQL3

B24

A_DDR3_DQL4

C18

A_DDR3_DQL5

A24

A_DDR3_DQL6

A18

A_DDR3_DQL7

D15

A_DDR3_DQU0

F17

A_DDR3_DQU1

F14

A_DDR3_DQU2

E16

A_DDR3_DQU3

D14

A_DDR3_DQU4

D16

A_DDR3_DQU5

E14

A_DDR3_DQU6

F16

A_DDR3_DQU7

A12

A_DDR3_CASZ

B11

A_DDR3_RASZ

E9

A_DDR3_WEZ

B20

A_DDR3_DQML

D17

A_DDR3_DQMU

A11

A_DDR3_ODT

B12

A_DDR3_BA0

G11

A_DDR3_BA1

B13

A_DDR3_BA2

G8

A_DDR3_RESET

F13

A_DDR3_MCLKE

B17

A_DDR3_MCLK

C17

A_DDR3_MCLKZ

B22

A_DDR3_DQSL

C22

A_DDR3_DQSBL

A21

A_DDR3_DQSU

C21

A_DDR3_DQSBU

B_DDR3_RESET
B_DDR3_MCLKE

B_DDR3_MCLKZ

B_DDR3_DQSBL

B_DDR3_DQSBU

B_DDR3_A0
B_DDR3_A1
B_DDR3_A2
B_DDR3_A3
B_DDR3_A4
B_DDR3_A5
B_DDR3_A6
B_DDR3_A7
B_DDR3_A8

B_DDR3_A9
B_DDR3_A10
B_DDR3_A11
B_DDR3_A12
B_DDR3_A13
B_DDR3_A14
B_DDR3_DQL0
B_DDR3_DQL1
B_DDR3_DQL2
B_DDR3_DQL3
B_DDR3_DQL4
B_DDR3_DQL5
B_DDR3_DQL6
B_DDR3_DQL7
B_DDR3_DQU0
B_DDR3_DQU1
B_DDR3_DQU2
B_DDR3_DQU3
B_DDR3_DQU4
B_DDR3_DQU5
B_DDR3_DQU6
B_DDR3_DQU7
B_DDR3_CASZ
B_DDR3_RASZ
B_DDR3_WEZ
B_DDR3_DQML
B_DDR3_DQMU
B_DDR3_ODT
B_DDR3_BA0
B_DDR3_BA1
B_DDR3_BA2

B_DDR3_MCLK

B_DDR3_DQSL

B_DDR3_DQSU

LGE2111C (PDP_13_None MS10)

AB17

E22

AB19

G21

Y16

F20

AD15

E24

AE15

K20

AD14

F24

AB15

J21

AC16

F23
H22

Y17

G23

AA16

L21

AB16

G22

AD16

J22

Y18

G25

AE20

H20

Y19

P23

AC20

L25

AB18

R24

AD17

K23

AC15

T25

AE17

J23

AA19

T24

AA18

K24

AC19

N21
P22

AA17

L22

AD20

R21

AC18

P20

AE14

R22

AD18

M22

AC17

N22

AD19

D24

AE21

B25

AE18

F22

W16

L23
R20

Y21

C24

Y20

D25

AA20

K22

AB22

E25

AB20

E21
M20

AD10

H23

Y9

H24

AA10

P25

Y10

N23

AB10

N24

AC9

M23

AC10

PCMDATA0/GPIO126
PCMDATA1/GPIO127
PCMDATA2/GPIO128
PCMDATA3/GPIO120
PCMDATA4/GPIO119
PCMDATA5/GPIO118
PCMDATA6/GPIO117
PCMDATA7/GPIO116

PCMADR0/GPIO125
PCMADR1/GPIO124
PCMADR2/GPIO122
PCMADR3/GPIO121
PCMADR4/GPIO99
PCMADR5/GPIO101
PCMADR6/GPIO102
PCMADR7/GPIO103
PCMADR8/GPIO108
PCMADR9/GPIO110
PCMADR10/GPIO114
PCMADR11/GPIO112
PCMADR12/GPIO104
PCMADR13/GPIO107
PCMADR14/GPIO106

PCM_RESET/GPIO129
PCMIRQA_N/GPIO105
PCMIOWR_N/GPIO109
PCMOE_N/GPIO113
PCMIORD_N/GPIO111
PCMCE_N/GPIO115
PCMWE_N/GPIO197
PCMCD_N/GPIO130
PCMREG_N/GPIO123
PCMWAIT_N/GPIO100

PCM2_CD_N/GPIO135
PCM2_RESET/GPIO134
PCM2_CE_N/GPIO131
PCM2_IRQA_N/GPIO132
PCM2_WAIT_N/GPIO133

NF_ALE/GPIO141
NF_WPZ/GPIO198
NF_CEZ/GPIO137
NF_CLE/GPIO136
NF_REZ/GPIO139
NF_WEZ/GPIO140
NF_RBZ/GPIO142

IC400-*1

TS1DATA0/GPIO88
TS1DATA1/GPIO89
TS1DATA2/GPIO90
TS1DATA3/GPIO91
TS1DATA4/GPIO92
TS1DATA5/GPIO93
TS1DATA6/GPIO94
TS1DATA7/GPIO95

TS1CLK/GPIO98
TS1VALID/GPI96
TS1SYNC/GPIO97

TS0DATA0/GPIO77
TS0DATA1/GPIO78
TS0DATA2/GPIO79
TS0DATA3/GPIO80
TS0DATA4/GPIO81
TS0DATA5/GPIO82
TS0DATA6/GPIO83
TS0DATA7/GPIO84

TS0CLK/GPIO87
TS0VALID/GPIO85
TS0SYNC/GPIO86

I2C_SCKM1/GPIO75
I2C_SDAM1/GPIO76

IF_AGC

GPIO73
GPIO74

Y14
AA14
AD13
Y13
AA13
AD12
AC12
W10
AB13
AC14
W13

AB12
AD11
W9
AE11
AB11
AE12
AC13
AB14
AA11
Y11
AC11

AC3

IP

AD2

IM

AD1

SIFP

AD3

SIFM

AC2

AB3
AC4
AE3
AE2

IC400-*1

LGE2111C (PDP_13_None MS10)

F2

A_RX0N

G1

A_RX0P

G2

A_RX1N

G3

A_RX1P

H2

A_RX2N

H3

A_RX2P

F3

A_RXCN

F1

A_RXCP

H5

DDCDA_CK/GPIO23

H4

DDCDA_DA/GPIO24

H6

HOTPLUGA/GPIO19

AC6

C_RX0N

AD7

C_RX0P

AC7

C_RX1N

AD8

C_RX1P

AE8

C_RX2N

AC8

C_RX2P

AE6

C_RXCN

AD6

C_RXCP

AC5

DDCDC_CK/GPIO27

AE5

DDCDC_DA/GPIO28

AD5

HOTPLUGC/GPIO21

K6

HOTPLUGD/GPIO22

I2S_IN_BCK/GPIO150

I2S_IN_SD/GPIO151
I2S_IN_WS/GPIO149

I2S_OUT_BCK/GPIO156
I2S_OUT_MCK/GPIO154
I2S_OUT_WS/GPIO155
I2S_OUT_SD/GPIO157

R6

CEC/GPIO5

B6

SPDIF_IN/GPIO152

M7

SPDIF_OUT/GPIO153

EARPHONE_OUTL
EARPHONE_OUTR

AUOUTL2
AUOUTR2

AUL1
AUR1
AUL3
AUR3
AUL4
AUR4

AUVRP
AUVAG
AUVRM

Y3
AA2
AA1
AA3
W3
Y2

AA9
AB9

AB4
AB5

Y5
AA4
AA5

C10
B10
B9

A9
B8
A8
C9

IC400-*1

LGE2111C (PDP_13_None MS10)

AA22

PWM0/GPIO66

Y22

PWM1/GPIO67

V24

PWM2/GPIO68

U23

PWM3/GPIO69

T22

PWM4/GPIO70

C7

PWM_PM/GPIO199

E7

SAR0/GPIO31

D7

SAR1/GPIO32

J6

SAR2/GPIO33

D1

SAR3/GPIO34

C1

SAR4/GPIO35

A5

PM_SPI_SCK/GPIO1

B5

PM_SPI_SDI/GPIO2

B4

PM_SPI_SDO/GPIO3

C4

PM_SPI_SCZ1/GPIO_PM[6]/GPIO12

B3

PM_SPI_SCZ2/GPIO_PM[10]/GPIO16

D3

PM_SPI_CZ0/GPIO_PM[12]/GPIO0

E2

DDCA_CK/UART0_RX

D2

DDCA_DA/UART0_TX

E5

UART1_RX/GPIO44

E4

UART1_TX/GPIO43

U24

UART2_RX/GPIO64

U25

UART2_TX/GPIO65

D4

PM_UART_TX/GPIO_PM[1]/GPIO7

D5

PM_UART_RX/GPIO_PM[5]/GPIO11

AA21

I2C_SCKM2/DDCR_CK/GPIO72

AB21

I2C_SDAM2/DDCR_DA/GPIO71

M5

GPIO_PM[0]/GPIO6

L7

GPIO_PM[2]/GPIO8

J4

GPIO_PM[4]/GPIO10

L5

GPIO_PM[8]/GPIO14

L6

GPIO_PM[9]/GPIO15

L4

GPIO_PM[11]/GPIO17

W24

LVB0M

V23

LVB0P

W23

LVB1M

W25

LVB1P

Y24

LVB2M

Y25

LVB2P

AA24

LVBCKM

Y23

LVBCKP

AB24

LVB3M

AA23

LVB3P

AB23

LVB4M

AB25

LVB4P

AC24

LVA0M

AC25

LVA0P

AD24

LVA1M

AD25

LVA1P

AC23

LVA2M

AE24

LVA2P

AD23

LVACKM

AE23

LVACKP

AD22

LVA3M

AC22

LVA3P

AD21

LVA4M

AC21

LVA4P

N5

GPIO36

A6

GPIO37

M6

GPIO38

R4

GPIO39

P5

GPIO40

D6

GPIO41

M4

GPIO42

C8

GPIO45

C5

GPIO46

E6

GPIO49

E3

GPIO50

K5

GPIO51

B7

GPIO52

K7

GPIO53

J5

GPIO54

IC400-*1

LGE2111C (PDP_13_None MS10)

M1

RIN0M

M2

RIN0P

L3

GIN0M

L2

GIN0P

K2

BIN0M

K1

BIN0P

LED0/GPIO55

K3

SOGIN0

LED1/GPIO56

J2

HSYNC0

J3

VSYNC0

R3

RIN1M

R1

RIN1P

R2

GIN1M

P3

GIN1P

N3

BIN1M

N2

BIN1P

P2

SOGIN1

R7

HSYNC1

R5

VSYNC1

V1

RIN2M

V2

RIN2P

U3

GIN2M

U2

GIN2P

T2

BIN2M

T1

BIN2P

T3

SOGIN2

T5

CVBS0

T4

CVBS1

T6

CVBS2

U4

VCOM

T7

CVBSOUT2

IC400-*1

LGE2111C (PDP_13_None MS10)

P17

A15

VDDC_1

A2

RN

B2

RP

B1

TN

C2

TP

A3
C3

AE9

USB1_DM

AD9

USB1_DP

K4

HWRESET

C6

IRIN/GPIO4

AE4

XIN

AD4

XOUT

GND_1

R17

A17

VDDC_2

GND_2

R18

A20

VDDC_3

GND_3

T17

B14

VDDC_4

GND_4

T18

B16

VDDC_5

GND_5

U18

B18

VDDC_6

GND_6

J9

B21

VDDC_7

GND_7

J11

C11

VDDC_8

GND_8

P8

C12

VDDC_9

GND_9

R8

C13

VDDC_10

GND_10

U11

C20

VDDC_11

GND_11

V10

C23

VDDC_12

GND_12

C25

GND_13

U17

D23

AVDDLV

GND_14

E17

GND_15

P18

E18

DVDD_DDR

GND_16

E20

GND_17

Y8

E23

AVDD25_LAN

GND_18

AA8

F4

AVDD2P5_DADC

GND_19

AB8

F5

AVDD_MOD

GND_20

F6

GND_21

AB1

F7

AVDD25_PGA

GND_22

AB2

F18

AVSS_PGA

GND_23

G4

GND_24

G5

GND_25

G6

GND_26

W4

G7

AVDD_NODIE

GND_27

W5

G10

AVDD_DMPLL

GND_28

G12

GND_29

G15

GND_30

W6

G19

AVDD_DVI_USB_MPLL

GND_31

Y6

G20

AVDD_AU33

GND_32

AA6

G24

VDDP

GND_33

W7

H7

AVDD_PLL

GND_34

H10

GND_35

Y4

H12

DVDD_NODIE

GND_36

H13

GND_37

J14

H14

AVDD_DDR0_C

GND_38

J15

H15

AVDD_DDR0_D_1

GND_39

J16

H19

AVDD_DDR0_D_2

GND_40

K16

H25

AVDD_DDR0_D_3

GND_41

J1

GND_42

J17

J7

AVDD_DDR1_C

GND_43

L16

J12

AVDD_DDR1_D_1

GND_44

L17

J13

AVDD_DDR1_D_2

GND_45

M16

J19

AVDD_DDR1_D_3

GND_46

J20

GND_47

J24

GND_48

J8

K12

GND_EFUSE

GND_49

K8

K13

TEST

GND_50

K14

GND_51

R19

K15

GND_91

GND_52

R23

K18

GND_92

GND_53

T23

K19

GND_93

GND_54

U5

K25

GND_94

GND_55

U6

L8

GND_95

GND_56

V3

L12

GND_96

GND_57

V4

L13

GND_97

GND_58

V11

L14

GND_98

GND_59

V15

L15

GND_99

GND_60

V16

L18

GND_100

GND_61

V17

L19

GND_101

GND_62

V18

L20

GND_102

GND_63

V19

L24

GND_103

GND_64

V20

M3

GND_104

GND_65

V21

M8

GND_105

GND_66

W1

M12

GND_106

GND_67

W2

M13

GND_107

GND_68

W11

M14

GND_108

GND_69

W15

M15

GND_109

GND_70

W17

M17

GND_110

GND_71

W18

M18

GND_111

GND_72

W20

M19

GND_112

GND_73

W21

M24

GND_113

GND_74

W22

N1

GND_114

GND_75

Y7

N7

GND_115

GND_76

AA7

N13

GND_116

GND_77

AB6

N14

GND_117

GND_78

AB7

N15

GND_118

GND_79

N16

GND_80

N17

GND_81

N18

GND_82

N19

GND_83

N20

GND_84

N25

GND_85

P13

GND_86

P14

GND_87

P19

GND_88

P21

GND_89

P24

GND_90

GP4L_S7LR2

DDR_256

2011/06/03

12

L13 T

raining

M

l

Table of contents

1. L13 Concept(’12 Vs. ’13)

2. L13 Power On/Off sequence

3. L13 Power Block

4. L13 I2C MAP

5. L13 Front End

anua

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

2. L13 Concept(’12 Vs. ’13)

50PN6500/60PN6500

42PA4500/50PA4500
50PA6500/60PA6500

3

1

S7LR3

5

4

4

206mm

2

3

141.5mm

42PN4500/50PN4500
50PN6500/60PN6500

1

S7LR3

141.5mm

4

2

42PN4500/50PN4500

5

206mm

1

2
3 LVDS Wafer

4

5

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

Main processor, DDR, NAND
Tuner

HDMI Block

Tact Key+LED+EYE+IR

1/11

Jack ERRC

1) RGB ,RS-232C and PC-Audio is removed

2) Comp./Comp. Hybrid Æ Comp. Hybrid (EU: 1ea)

3) HDMI 1 Jack is removed

4) Non-EU use Video(AV Jack) intead of SCART Jack

LGE Internal Use Only

3. Power On/Off sequence (AC)

Signal Spec.(min) Measure Graph Remark

RL_On 40ms 0

M_On 80ms 700ms

VS_On 250ms 260ms

VS_DET -

Signal Spec.(min) Measure Graph Remark

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

VS_On 0 40ms
RL_On 200ms 335ms

M_On 30ms 56ms

LGE Internal Use Only

2. Power On/Off sequence (DC)

Signal Spec.(min) Measure Graph Remark

RL_On

M_On 80ms 87ms

VS_On 250ms 280ms

VS_DET

Signal Spec.(min) Measure Graph Remark

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

M_On 2500ms 3000ms

RL_On 30ms 56ms

LGE Internal Use Only

2. Screen On/Off sequence

Signal Spec.(min) Measure Graph Remark

VS_On 250ms 247ms

VS_DET 400ms -

Signal Spec.(min) Measure Graph Remark

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

M_On 2530ms 2600ms

LGE Internal Use Only

4. Power Block.

V

OP-Amp

17.07V

L616

Spec) 850mV↓

20mVrms
356mVpp

17

for SC

Spec) 850mV↓

12mVrms

116mVpp

120 Ohm

5A

2012

17.07V

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

C680

0.1uF
50V

1608

C690

0.1uF
50V

1608

C695
68uF

35V

8PI/6.3H

C686

1uF
50V

C681

1uF
50V

Audio

AMP

LGE Internal Use Only

_

Y

p

3. Power Block.

_

p

p

0.1uF

0.1uF

0.1uF

73.58Vrms

_

Spec) 250mV↓

248mVpp

0.2mA

0.1uF

Input

STB

8.3mA 1.07A 1.12A 1.14A

5.10V

Spec) 250mV↓

69Vrms

245mVpp

+5
V_
ST

Spec) 250mV↓

169mVpp

DTV CompHDMI

L600

120 Ohm

5A

2012

27Vrms

C601

0.1uF
16V

Spec) 250mV↓

5.08V

L604

120 Ohm

2A

1608

DTV Comp HDMI

910mA 900mA 850mA

50Vrms

244mVpp

C608

10uF

10V

Spec) 250mV↓

68Vrms

Input

C610

16V

Q604

MOFET

ZXMP3F30

(3.0A)

Spec) 165mV↓

73.58Vrms

Input

DTV Com

33mA 33mA 33mA

5.07V 3.29V 3.29V

C600
10uF

10V 6.3V

C601

16V

5V to 3.3V

AP2121N-3.3

HDMI

IC600

(0.3A)

C604

1uF

+3.3V_ST

L400

120 Ohm

2A

1608

Spec) 165mV↓

164mVpp

Input

DTV Comp HDMI

230mA 220mA 220mA

Spec) 65mV↓

17Vrms
60mVpp

+1.10V_Vddc

C620

10uF

25V

88Vrms

249mVpp

C621

50V

5.07V

IC603
5V to 1.23V
TPS54231D

(2A)

1.26V

Input

DTV Comp HDMI

750mA 630mA 650mA

X3

10uF

10V

2012

x7

0.1uF
16V

1005

5.08V5.03V5.02V

418mVpp

AVDD

C401

C229

0.1uF
16V

1005

C556

0.1uF
16V

1005

C547

0.1uF
16V

1005

NODIE

3.29V

3.29V

Input

X2
1uF
10V

1005

LM1

RS232C

Serial Flash

SUB Ass’y

STBY

LM1

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

+5V

LGE Internal Use Only

3. Power Block.

+2.5V

DTV

Comp

HDMI

+5

5V to 1.8V

5.00V

1608

1608

1005

V

Spec) 250mV↓ Spec) 125mV↓

27Vrms

169mVpp

5.00V 2.486V 2.476V

10uF

10V

DTV Comp HDMI

102mA 102mA 102mA

IC601

5V to 2.5V

TJ3940S-2.5V

(714mW)

Input

16Vrms

99mVpp

C612C605 C485

10uF

6.3V

1608

102mA 102mA 102mA

120 Ohm

전류안흐름??

120 Ohm

Input

L405

2A

1608

L406

2A

1608

Spec) 250mV↓

27Vrms

169mVpp

C615

10uF

10V

150mA 164mA 164mA

IC604

AP1117BH-ADJ

(850mW)

Input

DTV Comp HDMI

Spec) 90mV↓

5.6Vrms
89mVpp

C631
10uF

6.3V
1608

+1.8V_TU

1.81V

C311

0.1uF
16V

1005

2.478V

0.1uF
16V

1005

C477

0.1uF
16V

1005

Spec) 125mV↓

16Vrms

99mVpp

AVDD2P5

LM1

Spec) 125mV↓

16Vrms

99mVpp

AVDD25_PGA

Tuner

+1.25V_TU

1.245V5.00V

C625
10uF

6.3V

C614
10uF

10V

IC602

5V to 1.25V

AP1117EG-13

(850mW)

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

C315

0.1uF
16V

C314
10uF

6.3V

T2/SBTV

Tuner

LGE Internal Use Only

3. Power Block.

Spec) 250mV↓

Spec) 165mV↓

Spec) 165mV↓

1608

10uF

0.1uF

10uF

DTV

ATV

Comp

HDMI

Audio

120 Ohm

3.275V

3.273V

+5

7Vrms

Spec) 75mV↓

10uF

16V

10V

16V

10V

V

26Vrms

169mVpp

5.02V

C616

0.1uF
10V

5.01V

C611

0.1uF
10V

IC608

5.0V to 3.3V

AP1117E33G

(850mW)

IC605

5.0V to 3.3V

AP1117E33G

(850mW)

5Vrms

69mVpp

C617

6.3V

Spec) 165mV↓

79mVpp

3.27V

C627

10uF

6.3V

+3.3V

+3.3V_TU

3.26V 3.255V

L606

120 Ohm

2A

168mA 194mA 197mA 197mA

+3.3V_AMP

L601

2A

Input(STA380 not working)

DTV Comp HDMI

30mA 30mA 30mA

IC613

3.3V to 1.5V

(850mW)

Input

C618
10uF

6.3V

1608

AP1117BH-ADJ

DTV Comp HDMI

285mA 185mA 185mA

Input

Spec) 165mV↓

7.5Vrms
74mVpp

1.507V

5Vrms

69mVpp

8Vrms

89mVpp

+1.5V_DDR

C619

6.3V

C302

16V

1005

C677

0.1uF
16V

L1202

500 Ohm

3A

2012(?)

Input

DTV Comp HDMI

140mA 85mA 85mA

L402

120 Ohm

C432

0.1uF

2A

1608

C303

16V

C672

0.1uF
16V

1.50V3.26V

C1251

10uF

1.50V

C436

10uF

Spec) 75mV↓

10Vrms

74mVpp

X4

1uF

Spec) 75mV↓

9.8Vrms
74mVpp

X3

0.1uF

Tuner

AMP

DDR

LM1

C446

1uF

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

1005

Input

DTV Comp HDMI

145mA 105mA 105mA

2012

1005

1005

LGE Internal Use Only

3. Power Block.

1.1V(750mA)

V

FET

(

)

5Vst

1.1V

()

1/4

V

V

850mW

In Out Current type

17V

5V ST

5Vst 5Vst 2mA STBY

5Vst 3.3Vst 35mA

17V 17V 1.1A Multi

ULDO

0.3A

60mW

ULDO

17V(1.1A)

5Vst (2mA)

3.3Vst(33mA)

DC-

F
E
T

DC

5V(?)

LDO

LDO

LDO

LDO

LDO(T2)

LDO

2.5V(102mA)

1.8V(164mA)

1.25V(400mA)

3.3V(300mA)

1.5V(300mA)

3.3V

5Vst 5

5V 5V 1A Multi USB 1A

5V 2.5V 102mA

5

5V 1.25V 400mA(?)

5V 3.3V 300mA

5V 3.3V 300mA

3.3V 1.5V 300mA

1.8

910mA + 1A

Input 220mA

750mA 3A

164mA

3A

DCDC

LDO

714mW

LDO

LDO

850mW

LDO

850mW

LDO

850mW

LDO

850mW

255mW

525mW

1500mW

510mW

510mW

480mW

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

5. L13 I2C MAP

GPIO40

AE2T2_SDA

GPIO49

H6E6AMP_SCL

0x1C)

I2C_SDAM2/DDCR_DA/GPIO71

AB21

I2C_SDA

IC503 EEPROM (0xA0)

+3.3V_TU

IC400

I2C_SCKM1/GPIO75
I2C_SDAM1/GPIO76

GPIO39

GPIO50

I2S_IN_WS/GPIO149

SPDIF_IN/GPIO152

AE3
AE2

AE3

B9
B6

TU_SCL

TU_SDA

T2_SCL

AMP_SDA

P_SCL

P_SDA

R308 2.2K

R313 2.2K

R640 4.7K

+3.3V

R450 3.3K

R309 2.2K

+3.3V_TU

R314 2.2K

+3.3V_AMP

R641 4.7K

R451 3.3K

TU301
TDSS-G201D (0x)

TU306
TDSQ-G605D (0x)

IC606
STA380BW (0x)

P500
LVDS
(module

I2C_SCKM2/DDCR_CK/GPIO72

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

AA21

I2C_SCL

+3.3V

R452 2.2K

R453 2.2K

LGE Internal Use Only

5. L13 Front End

But

PCB(T/C_T2/C,S2), f

g

g

g

UseMstar

Block

5815S

TS_ [0:7]

Demod

2012

SI2156 : PLL + ATV Demod

NetCast 4.0 Low model (Mstar) use three kind of tuner as below

we apply 2ea

2013

Tuner

Figure

ATV /
DVB-T/C

2013

Tuner

Diagram

DVB-S

SI2156 : PLL + With out Analog Demod
L13 : DVB-T/C Demod , A.Demod

ATV /
DVB-T/C

T/C T2/C T/C/S2

Diagram

Si2156

Tuner

TDSS-G201D

Diagram

SI2156

SIF/IF

A.Demod

L13 Mstar

SIF/IF

or each tuner and distinguish by circuit option and tool option

Diagram

ATV /
DVB-T/C
DVB-T2

DVB-S

SI2178 : PLL + With Analog Demod
SI2169 : DVB-T2/C/S/S2 Demod

Si2178

Tuner

TDSQ-G605D

IF

CVBS/SIF

Si2169

Diagram

ATV /
DVB-T/C
DVB-T2

SI2176

IF

CVBS/SIF

L13 Mstar

ATV /
DVB-T/C

DVB-S

DVB-S

Si2166B : DVB-S/S2 Demod
RDA5815S : DVB-S/S2 PLL
L13 : DVB-T/C Demod, A.Demod

Si2158

Diagram

RDA

Si2166B

Tuner

TDSQ-G501D

SIF/IF

TS_ [0:7]

L13 Mstar

Tuner

Compare

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

Tuner

TDSS-G201D

L13 : DVB-T/C Demod

L13 Mstar

UseMstar
A.Demod

Demod

CXD2834

Tuner

TDSN-G301D

CXD2834 : DVB-T/C/T2 Demod

TS_ [0:7]

L13 Mstar

LGE Internal Use Only

5. L13 Front End

g

T2/C

A

g

T/C Tuner Area

Use 2ea PCB for each tuner and apply different circuit option and tool option

Tool option4

-T/C
Digital Demod-S : DVB S7
Digital Demod-T/C : DEFAULT
Analog Demod : MST AR_56

­Digital Demod-S : NO_DEMOD
Digital Demod-T/C : DVBS_SI2169
Analog Demod : SI2176

EU/AU/JA

-T/C/S2
Digital Demod-S : DVB_S7
Digital Demod-T/C : DVBS_SI2166B

nalog Demod : MST AR 58

_

_

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

T/C/S Tuner Area
T2/C Tuner Area

Only Setellite

LGE Internal Use Only