Lenovo Skylake-H schematics
5
4
3
2
1
Schematic Block Diagram
VRAM GDDR5
PAGE63‐‐70
D D
DDR4DIMMX4
PAGE12~16
GDDR5
DDR42133MT/S
DUALCHANNEL2DIMM
nVIDIA
dGPU
N16E-GX
PAGE51‐‐62
PCIEGen316X
INTELProcessor
Skylake‐H
4+4e/4+2
BGA
42X28mm
PAGE2‐‐9
DMIX4
8GB/S
eDP
DDID
DDIB
DDIC
MUX
PS8331B
MUX
PS8331B
MUX
PS8331B
MUX
PS8331B
PAGE30
PAGE32
PAGE34
PAGE35
EDPLanesx4
DPLanesx4
DDI
DDI
PCIE4X PORT1
Card Reader
C C
B B
Bayhub OZ620FJ1LN
NGFF WLAN
2230 Conn,
(TYPE E)
WLAN/BT
LAN
Killer
E2400-RIVL-RL
NGFF SSD 1
2280 Conn,
(TYPE M)
NGFF SSD 2
2280 Conn,
(TYPE M)
PAGE41
PAGE27
PAGE42
PAGE42
PCIE1X
PORT6
PCIE1X
PORT7
USB2.0 PORT5
PCIE1X
PORT8
PORT13
PCIE4X
PORT9
PCIE4X
INTELSKYLAKE
PCH‐H
FCBGA
23X23mm
PAGE17‐‐25
PORT3
USB3.0
PORT2
USB2.0
PORT3USB2.0
USB2.0 PORT9
PORT4USB2.0
PORT1USB2.0
PORT6USB2.0
USB Conn,2
W/ CHARGER
HD CAMERA
FPR Conn
Keyboard
USB2.0 Conn,
JUSB3
USB2.0 Conn,
JUSB4
PAGE39
PAGE31
PAGE45
PAGE47
INTEL
ARDP
PANEL
17"FHD/UHD
GSYNC
DISPLAYPORT
PAGE36,37
PAGE31
PAGE33
USB3.1
HDMICONN,HDMI1.4b
PAGE40
TPS65982
PAGE38
USBCONN,1
PAGE39
TYPE‐CCONN,TYPE‐C
PAGE38
HP/MIC COMBO JACK
2.5"SATAHDD/SSD SATA PORT4
PAGE43
SPIBIOS
TOUCHPAD PS2
A A
PAGE45
LC
IT8376VG/CX
PAGE46
TURBObutton
LIDswitch
LED
5
SATARedriver
PS8527C
4
PAGE42
SPI
SMBUS
I2C
I2C
IntKBDDebug
PAGE50
I2C
EC
IT8376VG/CX
PAGE26
SMbus
80PortDebugCard
HDA CODEC
LPCSMBUS
PAGE50
3
PWM
SMBUS
I2C
ALC3268
PAGE28
SMARTAMP
TAS5766DCA
AMP
TPA3113D2PWPR
MIC JACK
PAGE29
PAGE29
SPEAKER CONN,
Subwoofer CONN,
FAN
Battery
THERMALSENSOR
IRsensorsTMP006A
RGBsensorCS5032
DMIC
PAGE73
PAGE44
PAGE44
IO DB
SENSOR DB
LENOVO.CRDN
LENOVO.CRDN
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number
Size Document Number
Size Document Number
Custom
Custom
Custom
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
2
LENOVO.CRDN
Rev
Rev
Rev
V0.3
V0.3
V0.3
199Wednesday, January 27, 2016
199Wednesday, January 27, 2016
199Wednesday, January 27, 2016
of
of
of
1
5
D D
C C
dGPU PEG
BRD Note:
B B
W=12mils;S=15mils;L<=400mils
+VCCIO
1 2
R1 24.9_0402_1%
DMI_IT_MR_0_DP18
DMI_IT_MR_0_DN18
DMI_IT_MR_1_DP18
DMI_IT_MR_1_DN18
DMI_IT_MR_2_DP18
DMI_IT_MR_2_DN18
DMI_IT_MR_3_DP18
DMI_IT_MR_3_DN18
4
PEG_PRX_GTX_P15
PEG_PRX_GTX_N15
PEG_PRX_GTX_P14
PEG_PRX_GTX_N14
PEG_PRX_GTX_P13
PEG_PRX_GTX_N13
PEG_PRX_GTX_P12
PEG_PRX_GTX_N12
PEG_PRX_GTX_P11
PEG_PRX_GTX_N11
PEG_PRX_GTX_P10
PEG_PRX_GTX_N10
PEG_PRX_GTX_P9
PEG_PRX_GTX_N9
PEG_PRX_GTX_P8
PEG_PRX_GTX_N8
PEG_PRX_GTX_P7
PEG_PRX_GTX_N7
PEG_PRX_GTX_P6
PEG_PRX_GTX_N6
PEG_PRX_GTX_P5
PEG_PRX_GTX_N5
PEG_PRX_GTX_P4
PEG_PRX_GTX_N4
PEG_PRX_GTX_P3
PEG_PRX_GTX_N3
PEG_PRX_GTX_P2
PEG_PRX_GTX_N2
PEG_PRX_GTX_P1
PEG_PRX_GTX_N1
PEG_PRX_GTX_P0
PEG_PRX_GTX_N0
PEG_RCOMP
E25
D25
E24
F24
E23
D23
E22
F22
E21
D21
E20
F20
E19
D19
E18
F18
D17
E17
F16
E16
D15
E15
F14
E14
D13
E13
F12
E12
D11
E11
F10
E10
G2
D8
E8
E6
F6
D5
E5
J8
J9
?
PEG_RXP[0]
PEG_RXN[0]
PEG_RXP[1]
PEG_RXN[1]
PEG_RXP[2]
PEG_RXN[2]
PEG_RXP[3]
PEG_RXN[3]
PEG_RXP[4]
PEG_RXN[4]
PEG_RXP[5]
PEG_RXN[5]
PEG_RXP[6]
PEG_RXN[6]
PEG_RXP[7]
PEG_RXN[7]
PEG_RXP[8]
PEG_RXN[8]
PEG_RXP[9]
PEG_RXN[9]
PEG_RXP[10]
PEG_RXN[10]
PEG_RXP[11]
PEG_RXN[11]
PEG_RXP[12]
PEG_RXN[12]
PEG_RXP[13]
PEG_RXN[13]
PEG_RXP[14]
PEG_RXN[14]
PEG_RXP[15]
PEG_RXN[15]
PEG_RCOMP
DMI_RXP[0]
DMI_RXN[0]
DMI_RXP[1]
DMI_RXN[1]
DMI_RXP[2]
DMI_RXN[2]
DMI_RXP[3]
DMI_RXN[3]
SKYLAKE_HALO
BGA1440
U1C
PEG_TXP[0]
PEG_TXN[0]
PEG_TXP[1]
PEG_TXN[1]
PEG_TXP[2]
PEG_TXN[2]
PEG_TXP[3]
PEG_TXN[3]
PEG_TXP[4]
PEG_TXN[4]
PEG_TXP[5]
PEG_TXN[5]
PEG_TXP[6]
PEG_TXN[6]
PEG_TXP[7]
PEG_TXN[7]
PEG_TXP[8]
PEG_TXN[8]
PEG_TXP[9]
PEG_TXN[9]
PEG_TXP[10]
PEG_TXN[10]
PEG_TXP[11]
PEG_TXN[11]
PEG_TXP[12]
PEG_TXN[12]
PEG_TXP[13]
PEG_TXN[13]
PEG_TXP[14]
PEG_TXN[14]
PEG_TXP[15]
PEG_TXN[15]
DMI_TXP[0]
DMI_TXN[0]
DMI_TXP[1]
DMI_TXN[1]
DMI_TXP[2]
DMI_TXN[2]
DMI_TXP[3]
DMI_TXN[3]
B25
A25
B24
C24
B23
A23
B22
C22
B21
A21
B20
C20
B19
A19
B18
C18
A17
B17
C16
B16
A15
B15
C14
B14
A13
B13
C12
B12
A11
B11
C10
B10
B8
A8
C6
B6
B5
A5
D4
B4
3
PCIE ReversedPCIE Reversed
PEG_PTX_GRX_P15
PEG_PTX_GRX_N15
PEG_PTX_GRX_P14
PEG_PTX_GRX_N14
PEG_PTX_GRX_P13
PEG_PTX_GRX_N13
PEG_PTX_GRX_P12
PEG_PTX_GRX_N12
PEG_PTX_GRX_P11
PEG_PTX_GRX_N11
PEG_PTX_GRX_P10
PEG_PTX_GRX_N10
PEG_PTX_GRX_P9
PEG_PTX_GRX_N9
PEG_PTX_GRX_P8
PEG_PTX_GRX_N8
PEG_PTX_GRX_P7
PEG_PTX_GRX_N7
PEG_PTX_GRX_P6
PEG_PTX_GRX_N6
PEG_PTX_GRX_P5
PEG_PTX_GRX_N5
PEG_PTX_GRX_P4
PEG_PTX_GRX_N4
PEG_PTX_GRX_P3
PEG_PTX_GRX_N3
PEG_PTX_GRX_P2
PEG_PTX_GRX_N2
PEG_PTX_GRX_P1
PEG_PTX_GRX_N1
PEG_PTX_GRX_P0
PEG_PTX_GRX_N0
12
C1 0.22U_0402_10V6K
12
C2 0.22U_0402_10V6K
12
C3 0.22U_0402_10V6K
12
C4 0.22U_0402_10V6K
12
C5 0.22U_0402_10V6K
12
C6 0.22U_0402_10V6K
12
C7 0.22U_0402_10V6K
12
C8 0.22U_0402_10V6K
12
C9 0.22U_0402_10V6K
12
C10 0.22U_0402_10V6K
12
C11 0.22U_0402_10V6K
12
C12 0.22U_0402_10V6K
12
C13 0.22U_0402_10V6K
12
C14 0.22U_0402_10V6K
12
C15 0.22U_0402_10V6K
12
C16 0.22U_0402_10V6K
12
C17 0.22U_0402_10V6K
12
C18 0.22U_0402_10V6K
12
C19 0.22U_0402_10V6K
12
C20 0.22U_0402_10V6K
12
C21 0.22U_0402_10V6K
12
C22 0.22U_0402_10V6K
12
C23 0.22U_0402_10V6K
12
C24 0.22U_0402_10V6K
12
C25 0.22U_0402_10V6K
12
C26 0.22U_0402_10V6K
12
C27 0.22U_0402_10V6K
12
C28 0.22U_0402_10V6K
12
C29 0.22U_0402_10V6K
12
C30 0.22U_0402_10V6K
12
C31 0.22U_0402_10V6K
12
C32 0.22U_0402_10V6K
DMI_MT_IR_0_DP
DMI_MT_IR_0_DN 18
DMI_MT_IR_1_DP
DMI_MT_IR_1_DN
DMI_MT_IR_2_DP
DMI_MT_IR_2_DN
DMI_MT_IR_3_DP
DMI_MT_IR_3_DN
PEG_PTX_C_GRX_P15
PEG_PTX_C_GRX_N15
PEG_PTX_C_GRX_P14
PEG_PTX_C_GRX_N14
PEG_PTX_C_GRX_P13
PEG_PTX_C_GRX_N13
PEG_PTX_C_GRX_P12
PEG_PTX_C_GRX_N12
PEG_PTX_C_GRX_P11
PEG_PTX_C_GRX_N11
PEG_PTX_C_GRX_P10
PEG_PTX_C_GRX_N10
PEG_PTX_C_GRX_P9
PEG_PTX_C_GRX_N9
PEG_PTX_C_GRX_P8
PEG_PTX_C_GRX_N8
PEG_PTX_C_GRX_P7
PEG_PTX_C_GRX_N7
PEG_PTX_C_GRX_P6
PEG_PTX_C_GRX_N6
PEG_PTX_C_GRX_P5
PEG_PTX_C_GRX_N5
PEG_PTX_C_GRX_P4
PEG_PTX_C_GRX_N4
PEG_PTX_C_GRX_P3
PEG_PTX_C_GRX_N3
PEG_PTX_C_GRX_P2
PEG_PTX_C_GRX_N2
PEG_PTX_C_GRX_P1
PEG_PTX_C_GRX_N1
PEG_PTX_C_GRX_P0
PEG_PTX_C_GRX_N0
18
18
18
18
18
18
18
2
dGPU PEG
1
PEG_PRX_GTX_N[0..15]
PEG_PRX_GTX_P[0..15]
PEG_PTX_C_GRX_N[0..15]
PEG_PTX_C_GRX_P[0..15]
51
51
51
51
3 OF 14 ?
SKL_H_BGA_BGA
A A
5
4
REV = 1
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
29
29
29
of
of
Rev
Rev
Rev
V0.3
V0.3
V0.3
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
Title
Title
Title
PROCESSOR-PEG/DMI
PROCESSOR-PEG/DMI
PROCESSOR-PEG/DMI
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
3
2
5
D D
DDI B TO AR DPSNK0
C C
DDI C TO AR DPSNK1
DDI D TO DP Port
4
?
SKYLAKE_HALO
4 OF 14
SKL_H_BGA_BGA
BGA1440
CPU_DPB_TX0_DP34
CPU_DPB_TX0_DN34
CPU_DPB_TX1_DP34
CPU_DPB_TX1_DN34
CPU_DPB_TX2_DP34
CPU_DPB_TX2_DN34
CPU_DPB_TX3_DP34
CPU_DPB_TX3_DN34
CPU_DPB_AUX_DP34
CPU_DPB_AUX_DN34
CPU_DPC_TX0_DP35
CPU_DPC_TX0_DN35
CPU_DPC_TX1_DP35
CPU_DPC_TX1_DN35
CPU_DPC_TX2_DP35
CPU_DPC_TX2_DN35
CPU_DPC_TX3_DP35
CPU_DPC_TX3_DN35
CPU_DPC_AUX_DP35
CPU_DPC_AUX_DN35
CPU_DPD_TX0_DP32
CPU_DPD_TX0_DN32
CPU_DPD_TX1_DP32
CPU_DPD_TX1_DN32
CPU_DPD_TX2_DP32
CPU_DPD_TX2_DN32
CPU_DPD_TX3_DP32
CPU_DPD_TX3_DN32
CPU_DPD_AUX_DP32
CPU_DPD_AUX_DN32
K36
K37
J35
J34
H37
H36
J37
J38
D27
E27
H34
H33
F37
G38
F34
F35
E37
E36
F26
E26
C34
D34
B36
B34
F33
E33
C33
B33
A27
B27
DDI1_TXP[0]
DDI1_TXN[0]
DDI1_TXP[1]
DDI1_TXN[1]
DDI1_TXP[2]
DDI1_TXN[2]
DDI1_TXP[3]
DDI1_TXN[3]
DDI1_AUXP
DDI1_AUXN
DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1]
DDI2_TXN[1]
DDI2_TXP[2]
DDI2_TXN[2]
DDI2_TXP[3]
DDI2_TXN[3]
DDI2_AUXP
DDI2_AUXN
DDI3_TXP[0]
DDI3_TXN[0]
DDI3_TXP[1]
DDI3_TXN[1]
DDI3_TXP[2]
DDI3_TXN[2]
DDI3_TXP[3]
DDI3_TXN[3]
DDI3_AUXP
DDI3_AUXN
3
U1D
EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXP
EDP_AUXN
EDP_DISP_UTIL
EDP_RCOMP
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
?
REV = 1
D29
E29
F28
E28
B29
A29
B28
C28
C26
B26
A33
EDP_UTIL
D37
EDP_RCOMP
BRD Note:
W=20mils;S=25mils;L<=100mils
G27
AUD_AZACPU_SCLK
G25
AUD_AZACPU_SDO
G29
AUD_AZACPU_SDI_R
1 2
R2 24.9_0402_1%
CAD Note:
Intergrated Codec for DP/HDMI
1 2
R3 22_0402_5%
CPU_EDP_TX0_DP
CPU_EDP_TX0_DN
CPU_EDP_TX1_DP
CPU_EDP_TX1_DN
CPU_EDP_AUX_DP
CPU_EDP_AUX_DN
1
TP1
+VCCIO
2
30
30
30
30
30
30
AUD_AZACPU_SCLK
AUD_AZACPU_SDO
AUD_AZACPU_SDI
DDI2 TO eDP
19
19
19
1
B B
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
39
39
39
of
of
Rev
Rev
Rev
V0.3
V0.3
V0.3
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
Title
Title
Title
Processor--eDP/TBT/DP
Processor--eDP/TBT/DP
Processor--eDP/TBT/DP
Size Document Number
Size Document Number
Size
Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
D D
M_A_DIM0_CK_DDR0_DP12
M_A_DIM0_CK_DDR0_DN12
M_A_DIM0_CK_DDR1_DN12
M_A_DIM0_CK_DDR1_DP12
M_A_DIM1_CK_DDR2_DP13
M_A_DIM1_CK_DDR2_DN13
M_A_DIM1_CK_DDR3_DP13
M_A_DIM1_CK_DDR3_DN13
M_A_DIM0_CKE012
M_A_DIM0_CKE112
M_A_DIM1_CKE213
M_A_DIM1_CKE313
M_A_DIM0_CS0_N12
M_A_DIM0_CS1_N12
M_A_DIM1_CS2_N13
M_A_DIM1_CS3_N13
M_A_DIM0_ODT012
M_A_DIM0_ODT112
C C
B B
M_A_DIM1_ODT213
M_A_DIM1_ODT313
M_A_BA012,13
M_A_BA112,13
M_A_BG012,13
M_A_A16_RAS_N12,13
M_A_A14_WE_N12,13
M_A_A15_CAS_N12,13
M_A_A012,13
M_A_A112,13
M_A_A212,13
M_A_A312,13
M_A_A412,13
M_A_A512,13
M_A_A612,13
M_A_A712,13
M_A_A812,13
M_A_A912,13
M_A_A10_AP12,13
M_A_A1112,13
M_A_A1212,13
M_A_A1312,13
M_A_BG112,13
M_A_ACT_N12,13
DDR0_A_PARITY12,13
DDR0_A_ALERT_N12,13
M_A_DQS_DN012,13
M_A_DQS_DN112,13
M_A_DQS_DN212,13
M_A_DQS_DN312,13
M_A_DQS_DP412,13
M_A_DQS_DP512,13
M_A_DQS_DP612,13
M_A_DQS_DP712,13
M_A_DQS_DP012,13
M_A_DQS_DP112,13
M_A_DQS_DP212,13
M_A_DQS_DP312,13
M_A_DQS_DN412,13
M_A_DQS_DN512,13
M_A_DQS_DN612,13
M_A_DQS_DN712,13
4
?
SKYLAKE_HALO
AG1
DDR0_CKP[0]
AG2
DDR0_CKN[0]
AK1
DDR0_CKN[1]
AK2
DDR0_CKP[1]
AL3
DDR0_CLKP[2]
AK3
DDR0_CLKN[2]
AL2
DDR0_CLKP[3]
AL1
DDR0_CLKN[3]
AT1
DDR0_CKE[0]
AT2
DDR0_CKE[1]
AT3
DDR0_CKE[2]
AT5
DDR0_CKE[3]
AD5
DDR0_CS#[0]
AE2
DDR0_CS#[1]
AD2
DDR0_CS#[2]
AE5
DDR0_CS#[3]
AD3
DDR0_ODT[0]
AE4
DDR0_ODT[1]
AE1
DDR0_ODT[2]
AD4
DDR0_ODT[3]
AH5
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
AH1
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
AU1
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
AH4
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
AG4
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
AD1
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
AH3
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
AP4
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
AN4
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
AP5
DDR0_MA[3]
AP2
DDR0_MA[4]
AP1
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
AP3
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
AN1
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
AN3
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
AT4
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
AH2
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
AN2
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
AU4
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
AE3
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
AU2
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
AU3
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
AG3
DDR0_PAR
AU5
DDR0_ALERT#
BR5
DDR0_DQSN[0]
BL3
DDR0_DQSN[1]
BG3
DDR0_DQSN[2]/DDR0_DQSN[4]
BD3
DDR0_DQSN[3]/DDR0_DQSN[5]
AB3
DDR0_DQSP[4]/DDR1_DQSP[0]
V3
DDR0_DQSP[5]/DDR1_DQSP[1]
R3
DDR0_DQSP[6]/DDR1_DQSP[4]
M3
DDR0_DQSP[7]/DDR1_DQSP[5]
BP5
DDR0_DQSP[0]
BK3
DDR0_DQSP[1]
BF3
DDR0_DQSP[2]/DDR0_DQSP[4]
BC3
DDR0_DQSP[3]/DDR0_DQSP[5]
AA3
DDR0_DQSN[4]/DDR1_DQSN[0]
U3
DDR0_DQSN[5]/DDR1_DQSN[1]
P3
DDR0_DQSN[6]/DDR1_DQSN[4]
L3
DDR0_DQSN[7]/DDR1_DQSN[5]
AY3
DDR0_DQSP[8]
BA3
DDR0_DQSN[8]
BGA1440
3
U1A
DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]
DDR0_ECC[0]
DDR0_ECC[1]
DDR0_ECC[2]
DDR0_ECC[3]
DDR0_ECC[4]
DDR0_ECC[5]
DDR0_ECC[6]
DDR0_ECC[7]
2
BR6
M_A_DQ0
BT6
M_A_DQ1
BP3
M_A_DQ2
BR3
M_A_DQ3
BN5
M_A_DQ4
BP6
M_A_DQ5
BP2
M_A_DQ6
BN3
M_A_DQ7
BL4
M_A_DQ8
BL5
M_A_DQ9
BL2
M_A_DQ10
BM1
M_A_DQ11
BK4
M_A_DQ12
BK5
M_A_DQ13
BK1
M_A_DQ14
BK2
M_A_DQ15
BG4
M_A_DQ16
BG5
M_A_DQ17
BF4
M_A_DQ18
BF5
M_A_DQ19
BG2
M_A_DQ20
BG1
M_A_DQ21
BF1
M_A_DQ22
BF2
M_A_DQ23
BD2
M_A_DQ24
BD1
M_A_DQ25
BC4
M_A_DQ26
BC5
M_A_DQ27
BD5
M_A_DQ28
BD4
M_A_DQ29
BC1
M_A_DQ30
BC2
M_A_DQ31
AB1
M_A_DQ32
AB2
M_A_DQ33
AA4
M_A_DQ34
AA5
M_A_DQ35
AB5
M_A_DQ36
AB4
M_A_DQ37
AA2
M_A_DQ38
AA1
M_A_DQ39
V5
M_A_DQ40
V2
M_A_DQ41
U1
M_A_DQ42
U2
M_A_DQ43
V1
M_A_DQ44
V4
M_A_DQ45
U5
M_A_DQ46
U4
M_A_DQ47
R2
M_A_DQ48
P5
M_A_DQ49
R4
M_A_DQ50
P4
M_A_DQ51
R5
M_A_DQ52
P2
M_A_DQ53
R1
M_A_DQ54
P1
M_A_DQ55
M4
M_A_DQ56
M1
M_A_DQ57
L4
M_A_DQ58
L2
M_A_DQ59
M5
M_A_DQ60
M2
M_A_DQ61
L5
M_A_DQ62
L1
M_A_DQ63
BA2
BA1
AY4
AY5
BA5
BA4
AY1
AY2
12,13
M_A_DQ0
M_A_DQ1
12,13
12,13
M_A_DQ2
12,13
M_A_DQ3
M_A_DQ4
12,13
12,13
M_A_DQ5
M_A_DQ6
12,13
M_A_DQ7
12,13
12,13
M_A_DQ8
M_A_DQ9
12,13
M_A_DQ10
12,13
12,13
M_A_DQ11
M_A_DQ12
12,13
12,13
M_A_DQ13
12,13
M_A_DQ14
M_A_DQ15
12,13
12,13
M_A_DQ16
M_A_DQ17
12,13
M_A_DQ18
12,13
12,13
M_A_DQ19
12,13
M_A_DQ20
12,13
M_A_DQ21
12,13
M_A_DQ22
M_A_DQ23
12,13
M_A_DQ24
12,13
12,13
M_A_DQ25
M_A_DQ26
12,13
12,13
M_A_DQ27
12,13
M_A_DQ28
M_A_DQ29
12,13
12,13
M_A_DQ30
M_A_DQ31
12,13
M_A_DQ32
12,13
12,13
M_A_DQ33
M_A_DQ34
12,13
M_A_DQ35
12,13
12,13
M_A_DQ36
M_A_DQ37
12,13
12,13
M_A_DQ38
12,13
M_A_DQ39
M_A_DQ40
12,13
12,13
M_A_DQ41
M_A_DQ42 12,13
M_A_DQ43
12,13
12,13
M_A_DQ44
12,13
M_A_DQ45
M_A_DQ46
12,13
12,13
M_A_DQ47
M_A_DQ48
12,13
M_A_DQ49
12,13
12,13
M_A_DQ50
M_A_DQ51
12,13
12,13
M_A_DQ52
12,13
M_A_DQ53
M_A_DQ54
12,13
M_A_DQ55
12,13
M_A_DQ56
12,13
M_A_DQ57
12,13
M_A_DQ58
12,13
M_A_DQ59 12,13
12,13
M_A_DQ60
M_A_DQ61
12,13
M_A_DQ62 12,13
12,13
M_A_DQ63
1
DDR CHANNEL A
?
A A
5
4
1 OF 14
SKL_H_BGA_BGA
REV = 1
3
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
49
49
49
of
of
of
Rev
Rev
Rev
V0.3
V0.3
V0.3
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
Title
Title
Title
PROCESSOR-MEM_CH A
PROCESSOR-MEM_CH A
PROCESSOR-MEM_CH A
Document Number
Size Document Number
Size Document Number
Size
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
2
5
4
3
2
1
D D
M_B_DIM0_CK_DDR0_DP14
M_B_DIM0_CK_DDR0_DN14
M_B_DIM0_CK_DDR1_DN14
M_B_DIM0_CK_DDR1_DP14
M_B_DIM1_CK_DDR2_DP15
M_B_DIM1_CK_DDR2_DN15
M_B_DIM1_CK_DDR3_DP15
M_B_DIM1_CK_DDR3_DN15
M_B_DIM0_CKE014
M_B_DIM0_CKE114
M_B_DIM1_CKE215
M_B_DIM1_CKE315
M_B_DIM0_CS0_N14
M_B_DIM0_CS1_N14
M_B_DIM1_CS2_N15
M_B_DIM1_CS3_N15
M_B_DIM0_ODT014
M_B_DIM0_ODT114
M_B_DIM1_ODT215
M_B_DIM1_ODT315
M_B_A16_RAS_N14,15
M_B_A14_WE_N14,15
M_B_A15_CAS_N14,15
M_B_BA014,15
M_B_BA114,15
M_B_BG014,15
C C
B B
+V_CPU_VREF_CA
+V_CPU_VREF_DQ_CHB
M_B_A014,15
M_B_A114,15
M_B_A214,15
M_B_A314,15
M_B_A414,15
M_B_A514,15
M_B_A614,15
M_B_A714,15
M_B_A814,15
M_B_A914,15
M_B_A10_AP14,15
M_B_A1114,15
M_B_A1214,15
M_B_A1314,15
M_B_BG114,15
M_B_ACT_N14,15
DDR1_B_PARITY14,15
DDR1_B_ALERT_N14,15
M_B_DQS_DN014,15
M_B_DQS_DN114,15
M_B_DQS_DN214,15
M_B_DQS_DN314,15
M_B_DQS_DN414,15
M_B_DQS_DN514,15
M_B_DQS_DN614,15
M_B_DQS_DN714,15
M_B_DQS_DP014,15
M_B_DQS_DP114,15
M_B_DQS_DP214,15
M_B_DQS_DP314,15
M_B_DQS_DP414,15
M_B_DQS_DP514,15
M_B_DQS_DP614,15
M_B_DQS_DP714,15
1
+V_CPU_VREF_DQ_CHA
TP124
AM9
DDR1_CKP[0]
AN9
DDR1_CKN[0]
AM8
DDR1_CKN[1]
AM7
DDR1_CKP[1]
AM11
DDR1_CLKP[2]
AM10
DDR1_CLKN[2]
AJ10
DDR1_CLKP[3]
AJ11
DDR1_CLKN[3]
AT8
DDR1_CKE[0]
AT10
DDR1_CKE[1]
AT7
DDR1_CKE[2]
AT11
DDR1_CKE[3]
AF11
DDR1_CS#[0]
AE7
DDR1_CS#[1]
AF10
DDR1_CS#[2]
AE10
DDR1_CS#[3]
AF7
DDR1_ODT[0]
AE8
DDR1_ODT[1]
AE9
DDR1_ODT[2]
AE11
DDR1_ODT[3]
AH10
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
AH11
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AF8
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
AH8
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
AH9
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
AR9
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
AJ9
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
AK6
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
AK5
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
AL5
DDR1_MA[3]
AL6
DDR1_MA[4]
AM6
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
AN7
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
AN10
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
AN8
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
AR11
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
AH7
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
AN11
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
AR10
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
AF9
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
AR7
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
AT9
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
AJ7
DDR1_PAR
AR8
DDR1_ALERT#
BP9
DDR1_DQSN[0]/DDR0_DQSN[2]
BL9
DDR1_DQSN[1]/DDR0_DQSN[3]
BG9
DDR1_DQSN[2]/DDR0_DQSN[6]
BC9
DDR1_DQSN[3]/DDR0_DQSN[7]
AC9
DDR1_DQSN[4]/DDR1_DQSN[2]
W9
DDR1_DQSN[5]/DDR1_DQSN[3]
R9
DDR1_DQSN[6]
M9
DDR1_DQSN[7]
BR9
DDR1_DQSP[0]/DDR0_DQSP[2]
BJ9
DDR1_DQSP[1]/DDR0_DQSP[3]
BF9
DDR1_DQSP[2]/DDR0_DQSP[6]
BB9
DDR1_DQSP[3]/DDR0_DQSP[7]
AA9
DDR1_DQSP[4]/DDR1_DQSP[2]
V9
DDR1_DQSP[5]/DDR1_DQSP[3]
P9
DDR1_DQSP[6]
L9
DDR1_DQSP[7]
AW9
DDR1_DQSP[8]
AY9
DDR1_DQSN[8]
BN13
DDR_VREF_CA
BP13
DDR0_VREF_DQ
BR13
DDR1_VREF_DQ
?
?
SKYLAKE_HALO
BGA1440
2 OF 14 REV = 1
U1B
DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_DQ[2]/DDR0_DQ[18]
DDR1_DQ[3]/DDR0_DQ[19]
DDR1_DQ[4]/DDR0_DQ[20]
DDR1_DQ[5]/DDR0_DQ[21]
DDR1_DQ[6]/DDR0_DQ[22]
DDR1_DQ[7]/DDR0_DQ[23]
DDR1_DQ[8]/DDR0_DQ[24]
DDR1_DQ[9]/DDR0_DQ[25]
DDR1_DQ[10]/DDR0_DQ[26]
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_DQ[12]/DDR0_DQ[28]
DDR1_DQ[13]/DDR0_DQ[29]
DDR1_DQ[14]/DDR0_DQ[30]
DDR1_DQ[15]/DDR0_DQ[31]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_DQ[17]/DDR0_DQ[49]
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[23]/DDR0_DQ[55]
DDR1_DQ[24]/DDR0_DQ[56]
DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58]
DDR1_DQ[27]/DDR0_DQ[59]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQ[47]/DDR1_DQ[31]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]
DDR1_ECC[0]
DDR1_ECC[1]
DDR1_ECC[2]
DDR1_ECC[3]
DDR1_ECC[4]
DDR1_ECC[5]
DDR1_ECC[6]
DDR1_ECC[7]
DDR CHANNEL B
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
SKL_H_BGA_BGA
BT11
BR11
BT8
BR8
BP11
BN11
BP8
BN8
BL12
BL11
BL8
BJ8
BJ11
BJ10
BL7
BJ7
BG11
BG10
BG8
BF8
BF11
BF10
BG7
BF7
BB11
BC11
BB8
BC8
BC10
BB10
BC7
BB7
AA11
AA10
AC11
AC10
AA7
AA8
AC8
AC7
W8
W7
V10
V11
W11
W10
V7
V8
R11
P11
P7
R8
R10
P10
R7
P8
L11
M11
L7
M8
L10
M10
M7
L8
AW11
AY11
AY8
AW8
AY10
AW10
AY7
AW7
G1
H1
J2
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6 14,15
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53 14,15
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
R4 121_0402_1%
R5 75_0402_1%
R6 100_0402_1%
12
12
12
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
BRD Note:DDR_RCOMP*
W=15mils;S=20mils;L<=500mils
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
59
59
59
of
of
of
Rev
Rev
Rev
V0.3
V0.3
V0.3
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
Title
Title
Title
PROCESSOR-MEM_CH B
PROCESSOR-MEM_CH B
PROCESSOR-MEM_CH B
Size
Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
4
3
2
1
+1.0V_VCCST
12
R8
R7
56.2_0402_1%
100_0402_1%
1 2
D D
C C
CPU_SVIDALERT_N83,86
CPU_SVIDCLK83,86
CPU_SVIDDATA83,86
+1.0V_VCCSTG
+1.0V_VCCST
12
R11 1K_0402_5%
12
R14 1K_0402_5%
12
R15 1K_0402_5%
BRD Note: SVID
S=18mils;Z=50ohm
1 2
R9 220_0402_5%
1 2
R46 0_0402_5%
1 2
R48 0_0402_5%
H_PROCHOT_N
H_VCCST_PWRGD
H_THRMTRIP_N
CPU_SVID_ALERT_N
CPU_SVID_CLK
CPU_SVID_DATA
?
SKYLAKE_HALO
BCLKP
BCLKN
PCI_BCLKP
PCI_BCLKN
CLK24P
CLK24N
VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#
DDR_VTT_CNTL
VCCST_PWRGD
PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#
SKTOCC#
PROC_SELECT#
CATERR#
5 OF 14
SKL_H_BGA_BGA
BGA1440
BH31
BH32
BH29
BR30
BT13
BT31
BP35
BM34
BP31
BT34
BR33
BM30
B31
A32
D35
C36
E31
D31
H13
J31
BN1
CK_CPU_BCLK_P22
CK_CPU_BCLK_N22
CK_CPU_PCIBCLK_P22
CK_CPU_PCIBCLK_N22
CK_CPU_24M_P22
CK_CPU_24M_N22
CPU_SVID_ALERT_N
CPU_SVID_CLK
CPU_SVID_DATA
12
TP115
TP4
H_PROCHOT_N_R
DDR_VTT_PG_CTRL
H_VCCST_PWRGD_R
H_PWRGD
CPU_PLTRST_N
H_PM_SYNC
H_PM_DOWN_R
H_PECI
H_THRMTRIP_N
1
H_SKTOCC_N
PROC_SELECT_N
1
H_CATERR_N
H_PROCHOT_N44
DDR_VTT_PG_CTRL49
H_VCCST_PWRGD49
H_PWRGD19
CPU_PLTRST_N20
H_PM_SYNC20
H_PM_DOWN20
H_PECI20,26
H_THRMTRIP_N20,71
R13 499_0402_1%
1 2
R17 60.4_0402_1%
1 2
R18 22_0402_5%
1 2
R21 0_0402_5%@
PROC_TDO
PROC_TMS
PROC_TCK
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
CFG_RCOMP
REV = 1
U1E
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[17]
CFG[16]
CFG[19]
CFG[18]
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
PROC_TDI
?
BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19
BN23
BP23
BP22
BN22
BR27
BT27
BM31
BT30
BT28
BL32
BP28
BR28
BP30
BL30
BP27
BT25
CFG0
CFG0
CFG1
CFG1
CFG2
CFG2
CFG3
CFG3
CFG4
CFG4
CFG5
CFG5
CFG6
CFG6
CFG7
CFG7
CFG8
CFG8 50
CFG9
CFG9
CFG10
CFG10
CFG11
CFG11
CFG12
CFG12
CFG13
CFG13
CFG14
CFG14
CFG15
CFG15
CFG17
CFG17
CFG16
CFG16
CFG19
CFG19
CFG18
1
1
R22
49.9_0402_1%
CFG18
XDP_BPM0_N
XDP_BPM1_N
TP2
TP3
XDP_TDO
XDP_TDI
XDP_TMS
XDP_TCK
XDP_TRST_N
XDP_PREQ_N
XDP_PRDY_N
12
XDP_BPM0_N
XDP_BPM1_N
XDP_BPM2_N
XDP_BPM3_N
CFG_RCOMP
BRD Note:
Placed near CPU within 1.1 inch
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
PROCESSOR CFG STRAPS
CFG0
Stall reset sequence after PCU
PLL lock until de-asserted
CFG0
CFG2
PEG16x Static Lane Reversal Strap
CFG2
CFG4
12
R10 1K_0402_5%@
1:Normal(Default)
0:Stall
12
R12 1K_0402_5%
1:Normal
0:Reversed(Default)
12
R23 1K_0402_5%
*
*
Embedded Display Port Presence Strap
CFG4
1:Disable
0:Enable(Default)
*
?
BN35
BN33
AE29
AA14
BR35
BR31
BH30
BR1
BL34
D1
E1
E3
E2
BT2
J24
H24
N29
R14
A36
A37
H23
J23
F30
E30
B30
C30
G3
J3
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PROC_TRIGIN
PROC_TRIGOUT
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SKL_H_BGA_BGA
1
TP_SKL_D1
TP5
1
TP_SKL_E1
TP7
1
TP_SKL_E3
TP9
1
TP_SKL_E2
B B
A A
BRD Note:
Placed within 1.1 inch of CPU pins
+1.0V_VCCST
12
R24 51_0402_5%
12
R25 51_0402_5%@
12
R27 51_0402_5%
12
R29 51_0402_5%@
H_PWRGD
1
R30
C33
@
@
10K_0402_5%
100P_0402_50V8J
2
1 2
5
XDP_TDO
XDP_PREQ_N
XDP_TCK
XDP_TRST_N
CAD Note:
CRB use 30R;DG use 0R
PCH_2_CPU_TRIGGER23
CPU_2_PCH_TRIGGER23
4
R31 33_0402_5%
TP10
1
TP_SKL_BR1
TP11
1
TP_SKL_BT2
TP12
PCH_2_CPU_TRIGGER
12
CPU_2_PCH_TRIGGER_R CFG7
11 OF 14
3
SKYLAKE_HALO
BGA1440
REV = 1
U1K
BM33
RSVD_TP
BL33
RSVD_TP
BJ14
RSVD_TP
BJ13
RSVD_TP
BK28
RSVD
BJ28
RSVD
BJ18
VSS
BJ16
RSVD_TP
BK16
RSVD_TP
BK24
RSVD_TP
BJ24
RSVD_TP
BK21
RSVD
BJ21
RSVD
BT17
RSVD
BR17
RSVD
BK18
VSS
BJ34
RSVD_TP
BJ33
RSVD_TP
G13
RSVD
AJ8
RSVD
BL31
RSVD
B2
NCTF
B38
NCTF
BP1
NCTF
BR2
NCTF
C1
NCTF
C38
?
NCTF
TP_SKL_BM33
TP_SKL_BL33
TP_SKL_BJ14
TP_SKL_BJ13
TP_SKL_BJ16
TP_SKL_BK16
TP_SKL_BK24
TP_SKL_BJ24
TP_SKL_BJ34
TP_SKL_BJ33
1
TP6
1
TP8
1
TP13
1
TP14
1
TP20
1
TP22
1
TP25
1
TP27
1
TP35
1
TP37
PEG TRAINNING
CFG7
2
CFG6
CFG5
PEG CONFIG Straps
CFG[6:5]
1: follow RESET# deassertion
0: Wait for BIOS for training
Title
Title
Title
Size Document Number
Size Document Number
Size
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
12
R26 1K_0402_5%@
12
R28 1K_0402_5%@
11: x16 (Default))
10: x8, x8
01: Reserved
00: x8,x4,x4
12
R32 1K_0402_5%@
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
PROCESSOR-CLK/PM/STRAP/TP
PROCESSOR-CLK/PM/STRAP/TP
PROCESSOR-CLK/PM/STRAP/TP
Document Number
Skylake-H
Skylake-H
Skylake-H
1
*
*
Rev
Rev
Rev
V0.3
V0.3
V0.3
69
69
69
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
of
of
5
4
3
2
1
D D
C C
B B
FOR H4+4e
BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21
BM17
BN17
BJ23
BJ26
BJ27
BK23
BK26
BK27
BL23
BL24
BL25
BL26
BL27
BL28
BM24
BL15
BM16
BL22
BM22
BP15
BR15
BT15
BP16
BR16
BT16
BN15
BM15
BP17
BN16
BM14
BL14
BJ35
BJ36
AT13
AW13
AU13
AY13
BT29
BR25
BP25
?
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCOPC_SENSE
VSSOPC_SENSE
RSVD
RSVD
VCCEOPIO
VCCEOPIO
VCCEOPIO
RSVD
RSVD
RSVD
VCCEOPIO_SENSE
VSSEOPIO_SENSE
RSVD
RSVD
VCC_OPC_1P8
VCC_OPC_1P8
RSVD
RSVD
ZVM#
MSM#
ZVM2#
MSM2#
OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2
SKL_H_BGA_BGA
SKYLAKE_HALO
BGA1440
U1J
REV = 1
?
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
SKYLAKE_HALO
BGA1440
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
7 OF 14
SKL_H_BGA_BGA
U1G
VCC_SENSE
VSS_SENSE
REV = 1
V32
VCC
V33
VCC
V34
VCC
V35
VCC
V36
VCC
V37
VCC
V38
VCC
W13
VCC
W14
VCC
W29
VCC
W30
VCC
W31
VCC
W32
VCC
W35
VCC
W36
VCC
W37
VCC
W38
VCC
Y29
VCC
Y30
VCC
Y31
VCC
Y32
VCC
Y33
VCC
Y34
VCC
Y35
VCC
Y36
VCC
L14
VCC
P29
VCC
P30
VCC
P31
VCC
P32
VCC
P33
VCC
P34
VCC
P35
VCC
P36
VCC
R13
VCC
R31
VCC
R32
VCC
R33
VCC
R34
VCC
R35
VCC
R36
VCC
R37
VCC
R38
VCC
T29
VCC
T30
VCC
T31
VCC
T32
VCC
T35
VCC
T36
VCC
T37
VCC
T38
VCC
U29
VCC
U30
VCC
U31
VCC
U32
VCC
U33
VCC
U34
VCC
U35
VCC
U36
VCC
V13
VCC
V14
VCC
V31
VCC
P14
VCC
AG37
AG38
?
CPU_CORE
CPU_VCORE_VCC_SENSE
CPU_VCORE_VSS_SENSE
CPU_VCORE_VCC_SENSE
CPU_VCORE_VSS_SENSE
83
83
CPU_CORE
?10 OF 14
CPU_VCORE_VSS_SENSE
R59
@
49.9_0402_1%
CPU_VCORE_VCC_SENSE
A A
5
4
3
2
1 2
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
79
79
79
of
of
of
Rev
Rev
Rev
V0.3
V0.3
V0.3
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
Title
Title
Title
PROCESSOR-POWER
PROCESSOR-POWER
PROCESSOR-POWER
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
1
+VCCGT
83
83
89
89
?
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
9 OF 14
SKL_H_BGA_BGA
SKYLAKE_HALO
U1I
BGA1440
VCCPLL_OC
VCCPLL_OC
VCCSA_SENSE
VSSSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
REV = 1
R53 0_0603_5%
R54 0_0603_5%
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC
VCCST
VCCSTG
VCCSTG
VCCPLL
VCCPLL
?
12
12
D D
C C
B B
+VCCSA
+VCCIO
J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
+1.0V_VCCST_VCCSFR
AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12
BH13
G11
H30
H29
G30
H28
J28
M38
M37
H14
J14
+1.0V_VCCST
+1.0V_VCCSFR
+1.2V_CPU_VDDQ
PJ15 JUMP_43X118
+VCCVDDQ_CLK
CPU_VCCSA_VCC_SENSE
CPU_VCCSA_VSS_SENSE
CPU_VCCIO_VCC_SENSE
CPU_VCCIO_VSS_SENSE
@
2
+1.0V_VCCST
+1.0V_VCCSTG
+1.0V_VCCSFR
112
+VCCSFR_OC
CPU_VCCSA_VCC_SENSE
CPU_VCCSA_VSS_SENSE
CPU_VCCIO_VCC_SENSE
CPU_VCCIO_VSS_SENSE
+1.2V_VDDQ
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
?
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
SKL_H_BGA_BGA
SKYLAKE_HALO
BGA1440
FOR H4+4e
U1N
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGT_SENSE
VSSGT_SENSE
VCCGTX_SENSE
VSSGTX_SENSE
?14 OF 14
REV = 1
AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14
AH38
AH37
AH36
AH35
CPU_VCCGT_VCC_SENSE
CPU_VCCGT_VSS_SENSE
CPU_VCCGT_VCC_SENSE
CPU_VCCGT_VSS_SENSE
?
SKYLAKE_HALO
BG34
VCCGT
BG35
VCCGT
BG36
VCCGT
BH33
VCCGT
BH34
VCCGT
BH35
VCCGT
BH36
VCCGT
BH37
VCCGT
BH38
VCCGT
BJ37
VCCGT
BJ38
VCCGT
BL36
VCCGT
BL37
VCCGT
BM36
VCCGT
BM37
VCCGT
BN36
VCCGT
BN37
VCCGT
BN38
VCCGT
BP37
VCCGT
BP38
VCCGT
BR37
VCCGT
BT37
VCCGT
BE38
VCCGT
BF13
VCCGT
BF14
VCCGT
BF29
VCCGT
BF30
VCCGT
BF31
VCCGT
BF32
VCCGT
BF35
VCCGT
BF36
VCCGT
BF37
VCCGT
BF38
VCCGT
BG29
VCCGT
BG30
VCCGT
BG31
VCCGT
BG32
VCCGT
BG33
VCCGT
BC36
VCCGT
BC37
VCCGT
BC38
VCCGT
BD13
VCCGT
BD14
VCCGT
BD29
VCCGT
BD30
VCCGT
BD31
VCCGT
BD32
VCCGT
BD33
VCCGT
BD34
VCCGT
BD35
VCCGT
BD36
VCCGT
BE31
VCCGT
BE32
VCCGT
BE37
VCCGT
86
86
SKL_H_BGA_BGA
BGA1440
U1H
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
REV = 1
+VCCGT+VCCGT
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36
?8 OF 14
+VCCVDDQ_CLK+1.2V_CPU_VDDQ
1 2
R52 0_0402_5%
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
89
89
89
of
of
Rev
Rev
Rev
V0.3
V0.3
V0.3
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
Title
Title
Title
PROCESSOR-POWER
PROCESSOR-POWER
PROCESSOR-POWER
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
4
3
2
1
D D
C C
B B
Y38
Y37
Y14
Y13
Y11
Y10
Y9
Y8
Y7
W34
W33
W12
W5
W4
W3
W2
W1
V30
V29
V12
V6
U38
U37
U6
T34
T33
T14
T13
T12
T11
T10
T9
T8
T7
T5
T4
T3
T2
T1
R30
R29
R12
P38
P37
P12
P6
N34
N33
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
M14
M13
M12
M6
L34
L33
L30
L29
K38
K11
K10
K9
K8
K7
K5
K4
K3
K2
SKL_H_BGA_BGA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
?
SKYLAKE_HALO
BGA1440
6 OF 14
U1F
NCTFVSS
REV = 1
K1
VSS
J36
VSS
J33
VSS
J32
VSS
J25
VSS
J22
VSS
J18
VSS
J10
VSS
J7
VSS
J4
VSS
H35
VSS
H32
VSS
H25
VSS
H22
VSS
H18
VSS
H12
VSS
H11
VSS
G28
VSS
G26
VSS
G24
VSS
G23
VSS
G22
VSS
G20
VSS
G18
VSS
G16
VSS
G14
VSS
G12
VSS
G10
VSS
G9
VSS
G8
VSS
G6
VSS
G5
VSS
G4
VSS
F36
VSS
F31
VSS
F29
VSS
F27
VSS
F25
VSS
F23
VSS
F21
VSS
F19
VSS
F17
VSS
F15
VSS
F13
VSS
F11
VSS
F9
VSS
F8
VSS
F5
VSS
F4
VSS
F3
VSS
F2
VSS
E38
VSS
E35
VSS
E34
VSS
E9
VSS
E4
VSS
D33
VSS
D30
VSS
D28
VSS
D26
VSS
D24
VSS
D22
VSS
D20
VSS
D18
VSS
D16
VSS
D14
VSS
D12
VSS
D10
VSS
D9
VSS
D6
VSS
D3
VSS
C37
VSS
C31
VSS
C29
VSS
C27
VSS
D38
?
BT32
BT26
BT24
BT21
BT18
BT14
BT12
BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12
BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12
BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12
BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12
BL29
BK29
BK15
BK14
BJ32
BJ31
BJ25
BJ22
BH14
BH12
BG38
BG13
BG12
BF33
BF12
BE29
BC34
BC12
BB12
C17
C13
C9
BT9
BT5
BR7
BP7
BN9
BN7
BN4
BN2
BM9
BM6
BM2
BH9
BH8
BH5
BH4
BH1
BE6
BD9
SKYLAKE_HALO
?
BGA1440
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA
U1L
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
REV = 1
?
SKYLAKE_HALO
BGA1440
BB4
VSS
BA38
BA37
BA12
BA11
BA10
AY34
AY33
AY14
AY12
AW30
AW29
AW12
AV38
AV37
AU34
AU33
AU12
AU11
AU10
AT30
AT29
AR38
AR37
AR14
AR13
AP34
AP33
AP12
AP11
AP10
AN30
AN29
AN12
AM38
AM37
AM12
AL34
AL33
AL14
AL12
AL10
BB3
BB2
BB1
BA9
BA8
BA7
BA6
AW5
AW4
AW3
AW2
AW1
AU9
AU8
AU7
AU6
AT6
AR5
AR4
AR3
AR2
AR1
AP9
AP8
AN6
AN5
AM5
AM4
AM3
AM2
AM1
AL9
AL8
AL7
AL4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
13 OF 14
SKL_H_BGA_BGA
C25
VSS
C23
VSS
C21
VSS
C19
VSS
C15
VSS
C11
VSS
C8
VSS
C5
VSS
BM29
VSS
BM25
VSS
BM18
VSS
BM11
VSS
BM8
VSS
BM7
VSS
BM5
VSS
BM3
VSS
BL38
VSS
BL35
VSS
BL13
VSS
BL6
VSS
BK25
VSS
BK22
VSS
BK13
VSS
BK6
VSS
BJ30
VSS
BJ29
VSS
BJ15
VSS
BJ12
VSS
BH11
VSS
BH10
VSS
BH7
VSS
BH6
VSS
BH3
VSS
BH2
VSS
BG37
VSS
BG14
VSS
BG6
VSS
BF34
VSS
BF6
VSS
BE30
VSS
BE5
VSS
BE4
VSS
BE3
VSS
BE2
VSS
BE1
VSS
BD38
VSS
BD37
VSS
BD12
VSS
BD11
VSS
BD10
VSS
BD8
VSS
BD7
VSS
BD6
VSS
BC33
VSS
BC14
VSS
BC13
VSS
BC6
VSS
BB30
VSS
BB29
VSS
BB6
VSS
BB5
VSS
C2
BT36
BT35
BT4
BT3
BR38
U1M
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
REV = 1
AK30
VSS
AK29
VSS
AK4
VSS
AJ38
VSS
AJ37
VSS
AJ6
VSS
AJ5
VSS
AJ4
VSS
AJ3
VSS
AJ2
VSS
AJ1
VSS
AH34
VSS
AH33
VSS
AH12
VSS
AH6
VSS
AG30
VSS
AG29
VSS
AG11
VSS
AG10
VSS
AG8
VSS
AG7
VSS
AG6
VSS
AF14
VSS
AF13
VSS
AF12
VSS
AF4
VSS
AF3
VSS
AF2
VSS
AF1
VSS
AE34
VSS
AE33
VSS
AE6
VSS
AD30
VSS
AD29
VSS
AD12
VSS
AD11
VSS
AD10
VSS
AD9
VSS
AD8
VSS
AD7
VSS
AD6
VSS
AC38
VSS
AC37
VSS
AC12
VSS
AC6
VSS
AC5
VSS
AC4
VSS
AC3
VSS
AC2
VSS
AC1
VSS
AB34
VSS
AB33
VSS
AB6
VSS
AA30
VSS
AA29
VSS
AA12
VSS
A30
VSS
A28
VSS
A26
VSS
A24
VSS
A22
VSS
A20
VSS
A18
VSS
A16
VSS
A14
VSS
A12
VSS
A10
VSS
A9
VSS
A6
VSS
B37
B3
A34
A4
A3
?
?12 OF 14
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
99
99
99
of
of
Rev
Rev
Rev
V0.3
V0.3
V0.3
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
9Wednesday, January 27, 2016
Title
Title
Title
PROCESSOR-VSS
PROCESSOR-VSS
PROCESSOR-VSS
Size Document Number
Size Document Number
Size
Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
D D
C C
+1.2V_CPU_VDDQ 4X0603(22UF) 10X0402(10UF)
BRD Note:
Placed backside
+1.2V_CPU_VDDQ +1.2V_CPU_VDDQ
1
1
1
1
C916
22U
_0603_6.3V6M
C917
22U
2
_0603_6.3V6M
1
C918
22U
2
_0603_6.3V6M
C915
22U
2
2
B B
_0603_6.3V6M
1
C919
10U
2
_0402_6.3V6M
C920
10U
2
_0402_6.3V6M
1
C921
10U
2
_0402_6.3V6M
1
C922
10U
2
_0402_6.3V6M
4
1
C923
10U_0402_6.3V6M
2
1
C924
10U
2
_0402_6.3V6M
1
C925
10U
2
_0402_6.3V6M
1
C926
10U
2
_0402_6.3V6M
1
C927
10U
2
_0402_6.3V6M
1
C928
10U
2
_0402_6.3V6M
3
+VCCSA
BOTTOM:1X0805(47UF), 8X0402(10UF), 3X0201(1UF);
TOP:2XBULK(220UF),1X0805(22UF)
BRD Note:
Placed backside
+VCCSA +VCCSA +VCCSA +VCCSA
1
C931
10U
2
_0402_6.3V6M
1
C932
10U
2
_0402_6.3V6M
C933
10U
_0402_6.3V6M
1
1
C929
47U
1 2
_0805_6.3V6-M
C930
10U
2
_0402_6.3V6M
2
1
C934
10U
2
_0402_6.3V6M
2
1
C935
10U
2
_0402_6.3V6M
1
C936
10U
2
_0402_6.3V6M
1
C937
10U
2
_0402_6.3V6M
2
C938
1u_0201_10V6M
1
2
C939
1u_0201_10V6M
1
2
C940
1u_0201_10V6M
1
1
BRD Note:
Placed TOP BGA EDGE
1
1
C942
C941
+
+
@
330U_B2_2.5VM_R9M
330U
_B2_2.5VM_R9M
2
C312
47U
1 2
2
_0805_6.3V6-M
BRD Note:
Placed backside
+1.0V_VCCSTG
2
C944
1u_0201_10V6M
A A
1
+1.0V_VCCST +1.0V_VCCSFR +1.0V_VCCSTG
2
C945
1u_0201_10V6M
1
5
2
C946
1u_0201_10V6M
1
2
C947
1u_0201_10V6M
1
2
C948
1u_0201_10V6M
1
4
1
C949
10U
2
_0402_6.3V6M
+VCCSFR_OC+VCCVDDQ_CLK
2
2
C950
C951
1u_0201_10V6M
1u_0201_10V6M
1
1
+VCCIO 2x0805(47UF) 3X0402(10UF)
C311
47U_0805_6.3V6-M
BRD Note:
Placed backside
+VCCIO
1
C871
10U
2
_0402_6.3V6M
BRD Note:
Placed TOP BGA EDGE
+VCCIO
C240
47U
1 2
1 2
_0805_6.3V6-M
3
1
C872
10U
2
_0402_6.3V6M
1
C873
10U
2
_0402_6.3V6M
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
10
10
10
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
PROCESSOR Decoupling 1/2
PROCESSOR Decoupling 1/2
PROCESSOR Decoupling 1/2
Size Document Number
Size Document Number
Document Number
Size
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
2
5
CPU_CORE
BOTTOM:3XBULK(220UF),8x0603(22U),30X0402(10UF), 69X0201(1UF);
TOP:3XBULK(220UF),4X0805(47UF)
4
3
+VCCGT
BOTTOM:4XBULK(220UF),8X0603(22U),36X0402(10UF), 69X0201(1UF);
TOP:4XBULK(220UF),6X0805(47UF)
2
1
CPU_CORE CPU_CORE
1
1
+
2
CPU_CORE
1
2
CPU_CORE
1
2
CPU_CORE
2
1
CPU_CORE
C952
330U
_B2_2.5VM_R9M
C974
10U
_0402_6.3V6M
C1007
10U
_0402_6.3V6M
C1040
1u_0201_10V6M
D D
C C
C953
+
330U
_B2_2.5VM_R9M
2
1
C975
10U
2
_0402_6.3V6M
1
C1008
10U
2
_0402_6.3V6M
2
C1041
1u_0201_10V6M
1
1
C954
+
2
1
C976
10U
2
_0402_6.3V6M
1
C1009
10U
2
_0402_6.3V6M
2
C1042
1u_0201_10V6M
1
330U
_B2_2.5VM_R9M
1
C977
10U
2
_0402_6.3V6M
1
C1010
10U
2
_0402_6.3V6M
2
1
1
C978
10U
2
_0402_6.3V6M
1
C1011
10U
2
_0402_6.3V6M
2
C1044
C1043
1u_0201_10V6M
1u_0201_10V6M
1
1
2
1
C979
10U
2
_0402_6.3V6M
1
C1012
10U
2
_0402_6.3V6M
2
C1045
1u_0201_10V6M
1
C955
22U
_0603_6.3V6M
1
C980
10U
2
_0402_6.3V6M
1
C1013
10U
2
_0402_6.3V6M
2
C1046
1u_0201_10V6M
1
1
2
C956
22U
_0603_6.3V6M
1
C981
10U
2
_0402_6.3V6M
1
C1014
10U
2
_0402_6.3V6M
2
C1047
1u_0201_10V6M
1
1
C957
22U
2
_0603_6.3V6M
1
C982
2
1
C1015
2
2
1
10U
_0402_6.3V6M
10U
_0402_6.3V6M
1
C958
22U
2
_0603_6.3V6M
1
C983
10U
2
_0402_6.3V6M
1
C1016
10U
2
_0402_6.3V6M
2
C1048
C1049
1u_0201_10V6M
1u_0201_10V6M
1
1
C959
22U
2
_0603_6.3V6M
1
C984
10U
2
_0402_6.3V6M
1
C1017
10U
2
_0402_6.3V6M
2
1
1
C960
22U
2
_0603_6.3V6M
1
C985
10U
2
_0402_6.3V6M
1
C1018
10U
2
_0402_6.3V6M
2
C1051
C1050
1u_0201_10V6M
1u_0201_10V6M
1
1
C961
22U
2
_0603_6.3V6M
1
C986
2
1
C1019
2
2
1
10U
_0402_6.3V6M
10U
_0402_6.3V6M
1
C962
22U
2
_0603_6.3V6M
1
C987
10U_0402_6.3V6M
2
1
C1020
10U_0402_6.3V6M
2
2
C1052
C1053
1u_0201_10V6M
1u_0201_10V6M
1
1
C988
2
1
C1021
2
2
1
10U
_0402_6.3V6M
10U
_0402_6.3V6M
2
C1054
1u_0201_10V6M
1
BRD Note:
Placed backside
2
C1055
C1056
1u_0201_10V6M
1u_0201_10V6M
1
2
C1057
1u_0201_10V6M
1
2
C1058
1u_0201_10V6M
1
2
C1059
1u_0201_10V6M
1
2
C1060
1u_0201_10V6M
1
2
C1061
1u_0201_10V6M
1
2
1
+VCCGT +VCCGT
1
1
C963
C964
+
+
330U
330U
_B2_2.5VM_R9M
_B2_2.5VM_R9M
2
2
+VCCGT
1
1
C990
C989
10U
10U
2
2
_0402_6.3V6M
_0402_6.3V6M
+VCCGT
1
1
C1022
C1023
10U
10U
2
2
_0402_6.3V6M
_0402_6.3V6M
+VCCGT
2
2
+VCCGT
C1063
1u_0201_10V6M
1
C1064
1u_0201_10V6M
1
C1062
1u_0201_10V6M
1
C965
+
330U_B2_2.5VM_R9M
2
1
C991
10U
2
_0402_6.3V6M
1
C1024
10U
2
_0402_6.3V6M
2
C1065
1u_0201_10V6M
1
1
C992
10U
2
_0402_6.3V6M
1
C1025
10U
2
_0402_6.3V6M
2
C1066
1u_0201_10V6M
1
1
C993
10U
2
_0402_6.3V6M
1
C1026
10U
2
_0402_6.3V6M
2
C1067
1u_0201_10V6M
1
1
2
1
C994
10U
2
_0402_6.3V6M
1
C1027
10U
2
_0402_6.3V6M
2
C1068
1u_0201_10V6M
1
C966
22U
_0603_6.3V6M
1
C995
10U
2
_0402_6.3V6M
1
C1028
10U
2
_0402_6.3V6M
2
C1069
1u_0201_10V6M
1
1
C967
22U_0603_6.3V6M
2
1
C996
10U
2
_0402_6.3V6M
1
C1029
10U
2
_0402_6.3V6M
2
C1070
1
1
C968
22U_0603_6.3V6M
2
1
C997
10U
2
_0402_6.3V6M
1
C1030
10U
2
_0402_6.3V6M
2
C1071
1u_0201_10V6M
1u_0201_10V6M
1
1
C969
2
1
2
1
2
2
1
22U
_0603_6.3V6M
C998
C1031
1
C970
22U
2
_0603_6.3V6M
1
C999
10U
10U
2
_0402_6.3V6M
_0402_6.3V6M
1
C1032
10U
10U
2
_0402_6.3V6M
_0402_6.3V6M
2
C1072
C1073
1u_0201_10V6M
1
1
C971
22U
2
_0603_6.3V6M
1
C1000
10U
2
_0402_6.3V6M
1
C1033
10U
2
_0402_6.3V6M
2
C1074
1u_0201_10V6M
1u_0201_10V6M
1
1
C972
22U_0603_6.3V6M
2
1
C1001
2
1
C1034
2
2
1
1
C973
22U_0603_6.3V6M
2
1
C1002
10U
10U
2
_0402_6.3V6M
_0402_6.3V6M
1
C1035
10U
10U
2
_0402_6.3V6M
_0402_6.3V6M
2
C1075
1u_0201_10V6M
1
1
C1003
10U
2
_0402_6.3V6M
1
C1036
10U
2
_0402_6.3V6M
2
C1077
C1076
1u_0201_10V6M
1u_0201_10V6M
1
BRD Note:
Placed backside
1
1
C1004
C1005
10U
2
2
_0402_6.3V6M
1
1
C1037
C1038
10U
2
2
_0402_6.3V6M
2
2
C1078
1u_0201_10V6M
1
1
1
C1006
10U
10U
2
_0402_6.3V6M
_0402_6.3V6M
1
C1039
10U
10U
2
_0402_6.3V6M
_0402_6.3V6M
2
C1079
1u_0201_10V6M
1
2
C1080
C1081
1u_0201_10V6M
1u_0201_10V6M
1
2
C1082
1u_0201_10V6M
1
2
C1083
1u_0201_10V6M
1
2
C1084
1u_0201_10V6M
1
2
C1085
1u_0201_10V6M
1
2
C1086
1u_0201_10V6M
1
2
C1132
1u_0201_10V6M
1
C1178
330U
_B2_2.5VM_R9M
2
2
C1088
C1087
1u_0201_10V6M
1u_0201_10V6M
1
1
2
2
C1134
C1133
1u_0201_10V6M
1u_0201_10V6M
1
1
BRD Note:
Placed TOP BGA EDGE
1
1
C1179
C1180
+
+
330U
330U
_B2_2.5VM_R9M
_B2_2.5VM_R9M
2
2
2
B B
1
CPU_CORE
2
1
CPU_CORE
A A
1
+
2
2
C1090
C1089
1u_0201_10V6M
1u_0201_10V6M
1
2
C1136
C1135
1u_0201_10V6M
1u_0201_10V6M
1
C1181
47U
1 2
1 2
_0805_6.3V6-M
5
C1182
2
1
2
1
47U
_0805_6.3V6-M
C1092
C1091
1u_0201_10V6M
1u_0201_10V6M
1
2
C1138
C1137
1u_0201_10V6M
1u_0201_10V6M
1
C1183
47U
1 2
1 2
_0805_6.3V6-M
C1184
2
1
2
1
47U
_0805_6.3V6-M
2
C1094
C1093
1u_0201_10V6M
1u_0201_10V6M
1
2
C1140
C1139
1u_0201_10V6M
1u_0201_10V6M
1
2
C1095
1u_0201_10V6M
1
2
C1141
1u_0201_10V6M
1
2
1
2
1
2
C1096
C1097
1u_0201_10V6M
1u_0201_10V6M
1
2
C1143
C1142
1u_0201_10V6M
1u_0201_10V6M
1
2
C1098
1u_0201_10V6M
1
2
C1144
1u_0201_10V6M
1
2
C1099
1u_0201_10V6M
1
2
C1145
1u_0201_10V6M
1
4
2
C1100
1u_0201_10V6M
1
2
C1146
1u_0201_10V6M
1
2
1
2
1
2
2
C1101
C1102
1u_0201_10V6M
1u_0201_10V6M
1
2
C1148
C1147
1u_0201_10V6M
1u_0201_10V6M
1
2
C1103
1u_0201_10V6M
1
2
C1149
1u_0201_10V6M
1
2
C1104
1u_0201_10V6M
1
2
C1150
1u_0201_10V6M
1
2
C1105
1u_0201_10V6M
1
2
C1151
1u_0201_10V6M
1
2
C1106
1u_0201_10V6M
1
2
C1152
1u_0201_10V6M
1
2
C1107
1u_0201_10V6M
1
2
C1153
1u_0201_10V6M
1
2
C1108
1u_0201_10V6M
1
2
C1154
1u_0201_10V6M
1
2
C1109
1u_0201_10V6M
1
2
C1155
1u_0201_10V6M
1
C1185
330U
_B2_2.5VM_R9M
2
2
C1111
C1110
1u_0201_10V6M
1u_0201_10V6M
1
1
2
2
C1157
C1156
1u_0201_10V6M
1u_0201_10V6M
1
1
BRD Note:
Placed TOP BGA EDGE
1
1
C1186
C1187
+
+
330U
330U_B2_2.5VM_R9M
_B2_2.5VM_R9M
2
2
2
1
+VCCGT
2
1
+VCCGT
1
+
2
3
2
C1113
C1112
1u_0201_10V6M
1u_0201_10V6M
1
2
C1159
C1158
1u_0201_10V6M
1u_0201_10V6M
1
1
C1188
+
@
330U_B2_2.5VM_R9M
1 2
2
C1189
2
1
2
1
47U
_0805_6.3V6-M
2
C1114
C1115
1u_0201_10V6M
1u_0201_10V6M
1
2
C1161
C1160
1u_0201_10V6M
1u_0201_10V6M
1
C1190
47U
1 2
1 2
_0805_6.3V6-M
C1191
2
1
2
1
47U
_0805_6.3V6-M
2
C1116
C1117
1u_0201_10V6M
1u_0201_10V6M
1
2
C1163
C1162
1u_0201_10V6M
1u_0201_10V6M
1
C1192
47U_0805_6.3V6-M
1 2
1 2
C1193
2
2
1
2
1
47U
_0805_6.3V6-M
2
C1118
C1119
1u_0201_10V6M
1u_0201_10V6M
1
2
C1165
C1164
1u_0201_10V6M
1u_0201_10V6M
1
C1194
47U
1 2
_0805_6.3V6-M
2
C1120
1u_0201_10V6M
1
2
C1166
1u_0201_10V6M
1
2
C1121
1u_0201_10V6M
1
2
C1167
1u_0201_10V6M
1
2
2
2
2
2
C1122
C1123
1u_0201_10V6M
1u_0201_10V6M
1
1
1
2
1
2
2
C1168
C1169
1u_0201_10V6M
1u_0201_10V6M
1
1
Title
Title
Title
Size Document Number
Size Document Number
Size Document Number
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
2
C1124
C1125
1u_0201_10V6M
1u_0201_10V6M
1
1
2
2
C1170
C1171
1u_0201_10V6M
1u_0201_10V6M
1
1
PROCESSOR Decoupling 2/2
PROCESSOR Decoupling 2/2
PROCESSOR Decoupling 2/2
Skylake-H
Skylake-H
Skylake-H
C1127
C1126
1u_0201_10V6M
1u_0201_10V6M
1
2
C1172
C1173
1u_0201_10V6M
1u_0201_10V6M
1
2
1
2
1
1
C1128
1u_0201_10V6M
C1174
1u_0201_10V6M
2
2
C1130
C1129
1u_0201_10V6M
1u_0201_10V6M
1
1
2
2
C1176
C1175
1u_0201_10V6M
1u_0201_10V6M
1
1
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
11
11
11
2
1
2
1
of
of
of
C1131
1u_0201_10V6M
C1177
1u_0201_10V6M
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
5
4
3
2
1
DDR4 SODIMM CHANNEL - A BOTTOM REV DIMM0 (5.2 MM HEIGHT CONNECTOR)
JDIMM1A
M_A_DIM0_CK_DDR0_DP4
M_A_DIM0_CK_DDR0_DN4
M_A_DIM0_CK_DDR1_DP4
M_A_DIM0_CK_DDR1_DN4
D D
C C
BRD Note:
Connect individually to +VDDQ_MEM
B B
M_A_DIM0_CKE04
M_A_DIM0_CKE14
M_A_DIM0_CS0_N4
M_A_DIM0_CS1_N4
M_A_DIM0_ODT04
M_A_DIM0_ODT14
M_A_BG04,13
M_A_BG14,13
M_A_BA04,13
M_A_BA14,13
M_A_A04,13
M_A_A14,13
M_A_A24,13
M_A_A34,13
M_A_A44,13
M_A_A54,13
M_A_A64,13
M_A_A74,13
M_A_A84,13
M_A_A94,13
M_A_A10_AP4,13
M_A_A114,13
M_A_A124,13
M_A_A134,13
M_A_A14_WE_N4,13
M_A_A15_CAS_N4,13
M_A_A16_RAS_N4,13
M_A_ACT_N4,13
DDR0_A_PARITY4,13
DDR0_A_ALERT_N4,13
TP126
DDR4_DRAMRST_N13,14,15,16
+V_DIM_VREF_CA_CHA
DIMM_SMB_DAT13,14,15,16
DIMM_SMB_CLK13,14,15,16
1
DIMM0_CHA_EVENT_N
DDR4_DRAMRST_N
DIMM_SMB_DAT
DIMM_SMB_CLK
+1.2V_VDDQ
137
CK0_T
139
CK0_C
138
CK1_T
140
CK1_C
109
CKE0
110
CKE1
149
S0#
157
S1#
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALEART#
134
EVENT#
108
RESET#
164
VREFCA
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
12
DM0#/DBI0#
33
DM1#/DB1I#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
162
S2#/C0
165
S3#/C1
SO-DIMM-DDR4-260P SD-80886-2021 5.2MM
SPD ADDRESS:0xA0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0_T
DQS1_T
DQS2_T
DQS3_T
DQS4_T
DQS5_T
DQS6_T
DQS7_T
DQS8_T
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS4_C
DQS5_C
DQS6_C
DQS7_C
DQS8_C
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
28
DQ8
29
DQ9
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246
13
34
55
76
179
200
221
242
97
11
32
53
74
177
198
219
240
95
M_A_DQ5
4,13
4,13
M_A_DQ0
M_A_DQ2
4,13
4,13
M_A_DQ3
4,13
M_A_DQ1
M_A_DQ4
4,13
M_A_DQ6
4,13
4,13
M_A_DQ7
M_A_DQ8
4,13
M_A_DQ12
M_A_DQ14
M_A_DQ11
4,13
M_A_DQ9
M_A_DQ13
M_A_DQ10
M_A_DQ15
M_A_DQ16 4,13
M_A_DQ20
M_A_DQ22
M_A_DQ23
M_A_DQ17
M_A_DQ21
M_A_DQ19
M_A_DQ18
M_A_DQ25
M_A_DQ28
M_A_DQ30
M_A_DQ31
M_A_DQ24
M_A_DQ29
M_A_DQ27
M_A_DQ26
M_A_DQ32
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ36
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ44
M_A_DQ45
M_A_DQ42
M_A_DQ43
M_A_DQ41
M_A_DQ40
M_A_DQ46
M_A_DQ47
M_A_DQ49
M_A_DQ48
M_A_DQ55
M_A_DQ53
M_A_DQ50
M_A_DQ52
M_A_DQ54
M_A_DQ51
M_A_DQ63
M_A_DQ61
M_A_DQ58
M_A_DQ62
M_A_DQ57
M_A_DQ56
M_A_DQ60
M_A_DQ59 4,13
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4 4,13
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7 4,13
+1.2V_VDDQ +0.6V_VTT
BYTE 0
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
4,13
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
JDIMM1B
163
VDD
160
VDD
159
VDD
154
VDD
153
VDD
148
VDD
147
VDD
142
VDD
141
VDD
136
VDD
135
VDD
130
VDD
129
VDD
124
VDD
123
VDD
118
VDD
117
VDD
112
VDD
111
VDD
251
VSS
247
VSS
243
VSS
239
VSS
235
VSS
231
VSS
227
VSS
223
VSS
217
VSS
213
VSS
209
VSS
205
VSS
201
VSS
197
VSS
193
VSS
189
VSS
185
VSS
181
VSS
175
VSS
171
VSS
167
VSS
107
VSS
103
VSS
99
VSS
93
VSS
89
VSS
85
VSS
81
VSS
77
VSS
73
VSS
69
VSS
65
VSS
61
VSS
57
VSS
51
VSS
47
VSS
43
VSS
39
VSS
35
VSS
31
VSS
27
VSS
23
VSS
19
VSS
15
VSS
9
VSS
5
VSS
1
VSS
262
MT2
261
MT1
SO-DIMM-DDR4-260P SD-80886-2021 5.2MM
VDDSPD
VPP2
VPP1
258
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+2.5V_MEM
259
257
+3V
255
252
248
244
238
234
230
226
222
218
214
210
206
202
196
192
188
184
180
176
172
168
106
102
98
94
90
86
82
78
72
68
64
60
56
52
48
44
40
36
30
26
22
18
14
10
6
2
C35
1 2
0.1U
_0402_25V6
C36
2.2U
_0402_6.3V6M
Decoupling Caps
BRD Note:
+V_DIM_VREF_CA_CHA
C38
C37
@
0.1U
2.2U
1 2
_0402_25V6
_0402_6.3V6M
A A
5
4
+1.2V_VDDQ
1
+
2
C39
330U
_D2_2V_Y
12
C40
10U
_0603_10V
1
C55
1U
_0402_10V6K
2
12
C41
10U
_0603_10V
1
C56
1U
_0402_10V6K
2
12
C42
10U
_0603_10V
1
C57
1U
_0402_10V6K
2
placed close to CHA DIMM0
12
12
12
C43
C44
C45
10U
10U_0603_10V
1
2
3
1
C59
1U_0402_10V6K
2
10U
_0603_10V
C60
1U
_0402_10V6K
_0603_10V
1
C58
1U
_0402_10V6K
2
12
C46
10U
_0603_10V
1
C61
1U
_0402_10V6K
2
12
C47
10U
_0603_10V
1
C62
1U
_0402_10V6K
2
12
C48
10U
_0603_10V
1
C63
1U
_0402_10V6K
2
12
C49
10U
_0603_10V
1
C64
1U
_0402_10V6K
2
+2.5V_MEM
12
+0.6V_VTT
12
C50
10U
_0603_10V
C65
10U_0603_10V
12
12
C51
10U
_0603_10V
C66
10U_0603_10V
2
1
C52
1U_0402_10V6K
2
1
C67
1U
_0402_10V6K
2
1
C53
1U_0402_10V6K
2
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
12
12
12
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
of
Title
Title
Title
DDR4 CHA DIMM0
DDR4 CHA DIMM0
DDR4 CHA DIMM0
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
1
DDR4 SODIMM CHANNEL - A TOP STD DIMM1 (4 MM HEIGHT CONNECTOR)
JDIMM2A
M_A_DIM1_CK_DDR2_DP4
M_A_DIM1_CK_DDR2_DN4
M_A_DIM1_CK_DDR3_DP4
M_A_DIM1_CK_DDR3_DN4
D D
C C
B B
M_A_DIM1_CKE24
M_A_DIM1_CKE34
M_A_DIM1_CS2_N4
M_A_DIM1_CS3_N4
M_A_DIM1_ODT24
M_A_DIM1_ODT34
M_A_BG04,12
M_A_BG14,12
M_A_BA04,12
M_A_BA14,12
M_A_A04,12
M_A_A14,12
M_A_A24,12
M_A_A34,12
M_A_A44,12
M_A_A54,12
M_A_A64,12
M_A_A74,12
M_A_A84,12
M_A_A94,12
M_A_A10_AP4,12
M_A_A114,12
M_A_A124,12
M_A_A134,12
M_A_A14_WE_N4,12
M_A_A15_CAS_N4,12
M_A_A16_RAS_N4,12
M_A_ACT_N4,12
DDR0_A_PARITY4,12
DDR0_A_ALERT_N4,12
TP127
DDR4_DRAMRST_N12,14,15,16
+V_DIM_VREF_CA_CHA
DIMM_SMB_DAT12,14,15,16
DIMM_SMB_CLK12,14,15,16
+3V
1
DIMM1_CHA_EVENT_N
DDR4_DRAMRST_N
DIMM_SMB_DAT
DIMM_SMB_CLK
+1.2V_VDDQ
137
CK0_T
139
CK0_C
138
CK1_T
140
CK1_C
109
CKE0
110
CKE1
149
S0#
157
S1#
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALEART#
134
EVENT#
108
RESET#
164
VREFCA
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
12
DM0#/DBI0#
33
DM1#/DB1I#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
162
S2#/C0
165
S3#/C1
SO-DIMM-DDR4-260P SD-80888-1021 4MM
SPD ADDRESS:0xA2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0_T
DQS1_T
DQS2_T
DQS3_T
DQS4_T
DQS5_T
DQS6_T
DQS7_T
DQS8_T
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS4_C
DQS5_C
DQS6_C
DQS7_C
DQS8_C
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
28
DQ8
29
DQ9
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246
13
34
55
76
179
200
221
242
97
11
32
53
74
177
198
219
240
95
M_A_DQ5
4,12
4,12
M_A_DQ0
M_A_DQ2
4,12
4,12
M_A_DQ3
4,12
M_A_DQ1
M_A_DQ4
4,12
M_A_DQ6
4,12
4,12
M_A_DQ7
M_A_DQ8
4,12
M_A_DQ12
M_A_DQ14
M_A_DQ11
4,12
M_A_DQ9
M_A_DQ13
M_A_DQ10
M_A_DQ15
M_A_DQ16 4,12
M_A_DQ20
M_A_DQ22
M_A_DQ23
M_A_DQ17
M_A_DQ21
M_A_DQ19
M_A_DQ18
M_A_DQ25
M_A_DQ28
M_A_DQ30
M_A_DQ31
M_A_DQ24
M_A_DQ29
M_A_DQ27
M_A_DQ26
M_A_DQ32
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ36
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ44
M_A_DQ45
M_A_DQ42
M_A_DQ43
M_A_DQ41
M_A_DQ40
M_A_DQ46
M_A_DQ47
M_A_DQ49
M_A_DQ48
M_A_DQ55
M_A_DQ53
M_A_DQ50
M_A_DQ52
M_A_DQ54
M_A_DQ51
M_A_DQ63
M_A_DQ61
M_A_DQ58
M_A_DQ62
M_A_DQ57
M_A_DQ56
M_A_DQ60
M_A_DQ59 4,12
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4 4,12
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7 4,12
+1.2V_VDDQ +0.6V_VTT
BYTE 0
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
4,12
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
JDIMM2B
163
VDD
160
VDD
159
VDD
154
VDD
153
VDD
148
VDD
147
VDD
142
VDD
141
VDD
136
VDD
135
VDD
130
VDD
129
VDD
124
VDD
123
VDD
118
VDD
117
VDD
112
VDD
111
VDD
251
VSS
247
VSS
243
VSS
239
VSS
235
VSS
231
VSS
227
VSS
223
VSS
217
VSS
213
VSS
209
VSS
205
VSS
201
VSS
197
VSS
193
VSS
189
VSS
185
VSS
181
VSS
175
VSS
171
VSS
167
VSS
107
VSS
103
VSS
99
VSS
93
VSS
89
VSS
85
VSS
81
VSS
77
VSS
73
VSS
69
VSS
65
VSS
61
VSS
57
VSS
51
VSS
47
VSS
43
VSS
39
VSS
35
VSS
31
VSS
27
VSS
23
VSS
19
VSS
15
VSS
9
VSS
5
VSS
1
VSS
262
MT2
261
MT1
SO-DIMM-DDR4-260P SD-80888-1021 4MM
VDDSPD
VPP2
VPP1
258
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+2.5V_MEM
259
257
+3V
255
252
248
244
238
234
230
226
222
218
214
210
206
202
196
192
188
184
180
176
172
168
106
102
98
94
90
86
82
78
72
68
64
60
56
52
48
44
40
36
30
26
22
18
14
10
6
2
C68
1 2
0.1U
_0402_25V6
C69
2.2U
_0402_6.3V6M
Decoupling Caps
BRD Note:
+1.2V_VDDQ
+V_DIM_VREF_CA_CHA
C54
C70
@
0.1U
2.2U
1 2
_0402_25V6
A A
5
_0402_6.3V6M
4
1
+
2
C72
@
330U
_D2_2V_Y
12
C73
10U
_0603_10V
1
C88
1U
_0402_10V6K
2
12
C74
10U
_0603_10V
1
C89
1U
_0402_10V6K
2
12
C75
10U
_0603_10V
1
C90
1U
_0402_10V6K
2
placed close to CHA DIMM0
12
12
C76
10U
_0603_10V
1
C91
1U
_0402_10V6K
2
1
2
3
12
C77
10U_0603_10V
1
C92
1U_0402_10V6K
2
C78
10U
_0603_10V
C93
1U
_0402_10V6K
12
C79
10U
_0603_10V
1
C94
1U
_0402_10V6K
2
12
C80
10U
_0603_10V
1
C95
1U
_0402_10V6K
2
12
C81
10U
_0603_10V
1
C96
1U
_0402_10V6K
2
12
C82
10U
_0603_10V
1
C97
1U
_0402_10V6K
2
+2.5V_MEM
12
+0.6V_VTT
12
C83
10U
_0603_10V
C98
10U_0603_10V
12
12
C84
10U
_0603_10V
C99
10U_0603_10V
2
1
C85
1U_0402_10V6K
2
1
C100
1U
_0402_10V6K
2
1
C86
1U_0402_10V6K
2
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
13
13
13
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
of
Title
Title
Title
DDR4 CHA DIMM1
DDR4 CHA DIMM1
DDR4 CHA DIMM1
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
1
DDR4 SODIMM CHANNEL - B BOTTOM STD DIMM0 (5.2 MM HEIGHT CONNECTOR)
JDIMM3A
M_B_DIM0_CK_DDR0_DP5
M_B_DIM0_CK_DDR0_DN5
M_B_DIM0_CK_DDR1_DP5
M_B_DIM0_CK_DDR1_DN5
D D
C C
B B
M_B_DIM0_CKE05
M_B_DIM0_CKE15
M_B_DIM0_CS0_N5
M_B_DIM0_CS1_N5
M_B_DIM0_ODT05
M_B_DIM0_ODT15
M_B_BG05,15
M_B_BG15,15
M_B_BA05,15
M_B_BA15,15
M_B_A05,15
M_B_A15,15
M_B_A25,15
M_B_A35,15
M_B_A45,15
M_B_A55,15
M_B_A65,15
M_B_A75,15
M_B_A85,15
M_B_A95,15
M_B_A10_AP5,15
M_B_A115,15
M_B_A125,15
M_B_A135,15
M_B_A14_WE_N5,15
M_B_A15_CAS_N5,15
M_B_A16_RAS_N5,15
M_B_ACT_N5,15
DDR1_B_PARITY5,15
DDR1_B_ALERT_N5,15
TP102
DDR4_DRAMRST_N12,13,15,16
+V_DIM_VREF_CA_CHB
DIMM_SMB_DAT12,13,15,16
DIMM_SMB_CLK12,13,15,16
+3V
1
DIMM0_CHB_EVENT_N
DDR4_DRAMRST_N
DIMM_SMB_DAT
DIMM_SMB_CLK
+1.2V_VDDQ
137
CK0_T
139
CK0_C
138
CK1_T
140
CK1_C
109
CKE0
110
CKE1
149
S0#
157
S1#
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALEART#
134
EVENT#
108
RESET#
164
VREFCA
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
12
DM0#/DBI0#
33
DM1#/DB1I#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
162
S2#/C0
165
S3#/C1
SO-DIMM-DDR4-260P SD-80888-2021 5.2MM
SPD ADDRESS:0xA4
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0_T
DQS1_T
DQS2_T
DQS3_T
DQS4_T
DQS5_T
DQS6_T
DQS7_T
DQS8_T
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS4_C
DQS5_C
DQS6_C
DQS7_C
DQS8_C
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
28
DQ8
29
DQ9
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246
13
34
55
76
179
200
221
242
97
11
32
53
74
177
198
219
240
95
M_B_DQ4
5,15
5,15
M_B_DQ0
M_B_DQ6
5,15
5,15
M_B_DQ7
5,15
M_B_DQ2
M_B_DQ5
5,15
M_B_DQ1
5,15
5,15
M_B_DQ3
M_B_DQ10
M_B_DQ14
M_B_DQ13
M_B_DQ15
5,15
M_B_DQ9
M_B_DQ8
5,15
M_B_DQ11
M_B_DQ12
M_B_DQ18 5,15
M_B_DQ22
M_B_DQ20
M_B_DQ21
M_B_DQ17
M_B_DQ16
M_B_DQ19
M_B_DQ23
M_B_DQ30
M_B_DQ31
M_B_DQ24
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ25
M_B_DQ26
M_B_DQ39
M_B_DQ35
M_B_DQ37
M_B_DQ33
M_B_DQ34
M_B_DQ38
M_B_DQ32
M_B_DQ36
M_B_DQ41
M_B_DQ45
M_B_DQ42
M_B_DQ47
M_B_DQ40
M_B_DQ44
M_B_DQ46
M_B_DQ43
M_B_DQ54
M_B_DQ51
M_B_DQ53
M_B_DQ55
M_B_DQ52
M_B_DQ48
M_B_DQ50
M_B_DQ49
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ56
M_B_DQ57
M_B_DQ59
M_B_DQ58
M_B_DQ63 5,15
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4 5,15
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7 5,15
+1.2V_VDDQ +0.6V_VTT
BYTE 0
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
JDIMM3B
163
VDD
160
VDD
159
VDD
154
VDD
153
VDD
148
VDD
147
VDD
142
VDD
141
VDD
136
VDD
135
VDD
130
VDD
129
VDD
124
VDD
123
VDD
118
VDD
117
VDD
112
VDD
111
VDD
251
VSS
247
VSS
243
VSS
239
VSS
235
VSS
231
VSS
227
VSS
223
VSS
217
VSS
213
VSS
209
VSS
205
VSS
201
VSS
197
VSS
193
VSS
189
VSS
185
VSS
181
VSS
175
VSS
171
VSS
167
VSS
107
VSS
103
VSS
99
VSS
93
VSS
89
VSS
85
VSS
81
VSS
77
VSS
73
VSS
69
VSS
65
VSS
61
VSS
57
VSS
51
VSS
47
VSS
43
VSS
39
VSS
35
VSS
31
VSS
27
VSS
23
VSS
19
VSS
15
VSS
9
VSS
5
VSS
1
VSS
262
MT2
261
MT1
SO-DIMM-DDR4-260P SD-80888-2021 5.2MM
VDDSPD
VPP2
VPP1
258
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+2.5V_MEM
259
257
+3V
255
252
248
244
238
234
230
226
222
218
214
210
206
202
196
192
188
184
180
176
172
168
106
102
98
94
90
86
82
78
72
68
64
60
56
52
48
44
40
36
30
26
22
18
14
10
6
2
C101
1 2
0.1U
_0402_25V6
C102
2.2U
_0402_6.3V6M
Decoupling Caps
BRD Note:
+V_DIM_VREF_CA_CHB
C103
C104
@
0.1U
2.2U
1 2
_0402_25V6
_0402_6.3V6M
A A
5
4
+1.2V_VDDQ
1
+
2
C105
@
330U
_D2_2V_Y
12
C106
10U
_0603_10V
1
C121
1U
_0402_10V6K
2
12
C107
10U
_0603_10V
1
C122
1U
_0402_10V6K
2
12
C108
10U
_0603_10V
1
C123
1U
_0402_10V6K
2
placed close to CHA DIMM0
12
C109
10U
_0603_10V
1
C124
1U
_0402_10V6K
2
1
2
3
12
C110
10U_0603_10V
1
C125
1U_0402_10V6K
2
C111
10U
_0603_10V
C126
1U
_0402_10V6K
12
12
C112
10U
_0603_10V
1
C127
1U
_0402_10V6K
2
12
C113
10U
_0603_10V
1
C128
1U
_0402_10V6K
2
12
C114
10U
_0603_10V
1
C129
1U
_0402_10V6K
2
12
C115
10U
_0603_10V
1
C130
1U
_0402_10V6K
2
+2.5V_MEM
12
+0.6V_VTT
12
C116
10U
_0603_10V
C131
10U_0603_10V
12
12
C117
10U
_0603_10V
C132
10U_0603_10V
2
1
C118
1U_0402_10V6K
2
1
C133
1U
_0402_10V6K
2
1
C119
1U_0402_10V6K
2
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
14
14
14
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
of
Title
Title
Title
DDR4 CHB DIMM0
DDR4 CHB DIMM0
DDR4 CHB DIMM0
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
1
DDR4 SODIMM CHANNEL - B TOP REV DIMM1 (4.0 MM HEIGHT CONNECTOR)
JDIMM4A
M_B_DIM1_CK_DDR2_DP5
M_B_DIM1_CK_DDR2_DN5
M_B_DIM1_CK_DDR3_DP5
M_B_DIM1_CK_DDR3_DN5
D D
C C
B B
M_B_DIM1_CKE25
M_B_DIM1_CKE35
M_B_DIM1_CS2_N5
M_B_DIM1_CS3_N5
M_B_DIM1_ODT25
M_B_DIM1_ODT35
M_B_BG05,14
M_B_BG15,14
M_B_BA05,14
M_B_BA15,14
M_B_A05,14
M_B_A15,14
M_B_A25,14
M_B_A35,14
M_B_A45,14
M_B_A55,14
M_B_A65,14
M_B_A75,14
M_B_A85,14
M_B_A95,14
M_B_A10_AP5,14
M_B_A115,14
M_B_A125,14
M_B_A135,14
M_B_A14_WE_N5,14
M_B_A15_CAS_N5,14
M_B_A16_RAS_N5,14
M_B_ACT_N5,14
DDR1_B_PARITY5,14
DDR1_B_ALERT_N5,14
TP128
DDR4_DRAMRST_N12,13,14,16
+V_DIM_VREF_CA_CHB
DIMM_SMB_DAT12,13,14,16
DIMM_SMB_CLK12,13,14,16
+3V
1
DIMM1_CHB_EVENT_N
DDR4_DRAMRST_N
DIMM_SMB_DAT
DIMM_SMB_CLK
+1.2V_VDDQ
137
CK0_T
139
CK0_C
138
CK1_T
140
CK1_C
109
CKE0
110
CKE1
149
S0#
157
S1#
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALEART#
134
EVENT#
108
RESET#
164
VREFCA
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
12
DM0#/DBI0#
33
DM1#/DB1I#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
162
S2#/C0
165
S3#/C1
SO-DIMM-DDR4-260P SD-80886-1021 4MM
SPD ADDRESS:0xA6
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0_T
DQS1_T
DQS2_T
DQS3_T
DQS4_T
DQS5_T
DQS6_T
DQS7_T
DQS8_T
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS4_C
DQS5_C
DQS6_C
DQS7_C
DQS8_C
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
28
DQ8
29
DQ9
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246
13
34
55
76
179
200
221
242
97
11
32
53
74
177
198
219
240
95
M_B_DQ4
5,14
5,14
M_B_DQ0
M_B_DQ6
5,14
5,14
M_B_DQ7
5,14
M_B_DQ2
M_B_DQ5
5,14
M_B_DQ1
5,14
5,14
M_B_DQ3
M_B_DQ10
M_B_DQ14
M_B_DQ13
M_B_DQ15
5,14
M_B_DQ9
M_B_DQ8
5,14
M_B_DQ11
M_B_DQ12
M_B_DQ18 5,14
M_B_DQ22
M_B_DQ20
M_B_DQ21
M_B_DQ17
M_B_DQ16
M_B_DQ19
M_B_DQ23
M_B_DQ30
M_B_DQ31
M_B_DQ24
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ25
M_B_DQ26
M_B_DQ39
M_B_DQ35
M_B_DQ37
M_B_DQ33
M_B_DQ34
M_B_DQ38
M_B_DQ32
M_B_DQ36
M_B_DQ41
M_B_DQ45
M_B_DQ42
M_B_DQ47
M_B_DQ40
M_B_DQ44
M_B_DQ46
M_B_DQ43
M_B_DQ54
M_B_DQ51
M_B_DQ53
M_B_DQ55
M_B_DQ52
M_B_DQ48
M_B_DQ50
M_B_DQ49
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ56
M_B_DQ57
M_B_DQ59
M_B_DQ58
M_B_DQ63 5,14
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4 5,14
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7 5,14
+1.2V_VDDQ +0.6V_VTT
BYTE 0
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
JDIMM4B
163
VDD
160
VDD
159
VDD
154
VDD
153
VDD
148
VDD
147
VDD
142
VDD
141
VDD
136
VDD
135
VDD
130
VDD
129
VDD
124
VDD
123
VDD
118
VDD
117
VDD
112
VDD
111
VDD
251
VSS
247
VSS
243
VSS
239
VSS
235
VSS
231
VSS
227
VSS
223
VSS
217
VSS
213
VSS
209
VSS
205
VSS
201
VSS
197
VSS
193
VSS
189
VSS
185
VSS
181
VSS
175
VSS
171
VSS
167
VSS
107
VSS
103
VSS
99
VSS
93
VSS
89
VSS
85
VSS
81
VSS
77
VSS
73
VSS
69
VSS
65
VSS
61
VSS
57
VSS
51
VSS
47
VSS
43
VSS
39
VSS
35
VSS
31
VSS
27
VSS
23
VSS
19
VSS
15
VSS
9
VSS
5
VSS
1
VSS
262
MT2
261
MT1
SO-DIMM-DDR4-260P SD-80886-1021 4MM
VDDSPD
VPP2
VPP1
258
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+2.5V_MEM
259
257
+3V
255
252
248
244
238
234
230
226
222
218
214
210
206
202
196
192
188
184
180
176
172
168
106
102
98
94
90
86
82
78
72
68
64
60
56
52
48
44
40
36
30
26
22
18
14
10
6
2
C134
1 2
0.1U
_0402_25V6
C135
2.2U
_0402_6.3V6M
Decoupling Caps
BRD Note:
+V_DIM_VREF_CA_CHB
C120
C136
@ C152
0.1U
2.2U
1 2
_0402_25V6
_0402_6.3V6M
A A
5
4
+1.2V_VDDQ
1
+
2
C138
330U
_D2_2V_Y
12
C139
10U
_0603_10V
1
C154
1U
_0402_10V6K
2
12
C140
10U
_0603_10V
1
C155
1U
_0402_10V6K
2
12
C141
10U
_0603_10V
1
C156
1U
_0402_10V6K
2
placed close to CHA DIMM0
12
12
12
C142
1
C157
2
C143
10U
_0603_10V
1
C158
1U
_0402_10V6K
2
3
C144
10U_0603_10V
1
C159
1U_0402_10V6K
2
10U
_0603_10V
1U
_0402_10V6K
12
C145
10U
_0603_10V
1
C160
1U
_0402_10V6K
2
12
C146
10U
_0603_10V
1
C161
1U
_0402_10V6K
2
12
C147
10U
_0603_10V
1
C162
1U
_0402_10V6K
2
12
C148
10U
_0603_10V
1
C163
1U
_0402_10V6K
2
+2.5V_MEM
12
+0.6V_VTT
12
C149
10U
_0603_10V
C164
10U_0603_10V
12
12
C150
10U
_0603_10V
C165
10U_0603_10V
2
1
C151
1U_0402_10V6K
2
1
C166
1U
_0402_10V6K
2
1
1U_0402_10V6K
2
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
15
15
15
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
DDR4 CHB DIMM1
DDR4 CHB DIMM1
DDR4 CHB DIMM1
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
1
D D
DDR VREF
BRD Note:
VREF trace width 20mils;spacing 20 mils to other signal/planes
+1.2V_VDDQ
R89
1K_0402_1%
+V_CPU_VREF_CA
1 2
R90 2.2_0402_1%
2
C C
B B
C172
0.022U_0402_25V7K
1
R92
24.9_0402_1%
1 2
+V_CPU_VREF_DQ_CHB
2
C175
0.022U_0402_25V7K
1
R96
24.9_0402_1%
1 2
1 2
R94 2.2_0402_1%
1 2
1 2
+1.2V_VDDQ
1 2
1 2
R91
1K_0402_1%
R93
1K_0402_1%
R95
1K_0402_1%
C171
0.1U_0402_25V6
1 2
C173
0.1U_0402_25V6
1 2
C174
0.1U_0402_25V6
1 2
C176
0.1U_0402_25V6
1 2
+V_DIM_VREF_CA_CHA
+V_DIM_VREF_CA_CHB
PCH_SMB_CLK19,45,50
PCH_SMB_DAT19,45,50
DRAM_CRESET_N19 DDR4_DRAMRST_N
1 2
R81 0_0402_5%
1 2
R82 0_0402_5%
+1.2V_VDDQ
R84
470_0402_5%
1 2
1 2
R86 0_0402_5%
C170
@
0.1U_0402_25V6
1 2
DIMM_SMB_CLK
DIMM_SMB_DAT
DIMM_SMB_CLK
DIMM_SMB_DAT
12,13,14,15
12,13,14,15
12,13,14,15
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
16
16
16
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
DDR4-VREF
DDR4-VREF
DDR4-VREF
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
+3VALW_PCH
1 2
R534 49.9K_0402_1%
1 2
R266 49.9K_0402_1%
+3VALW_PCH
D D
C C
1 2
R535 49.9K_0402_1%
1 2
R536 49.9K_0402_1%
+3V
R106 1K_0402_5%
R107 1K_0402_5%
+3V
R109 1K_0402_5%
R111 1K_0402_5%
+3VALW_SPI
12
12
12
12
CAD Note
：
Reserve for PCH strpping
1 2
R931 10K_0402_5%@
1 2
R936 10K_0402_5%@
1 2
R937 10K_0402_5%@
1 2
R938 10K_0402_5%@
PCH_UART2_TXD
PCH_UART2_RXD
PCH_UART2_CTS_N
PCH_UART2_RTS_N
PCH_I2C_CLK1
PCH_I2C_DATA1
PCH_I2C_CLK0
PCH_I2C_DATA0
PCH_SI
PCH_SO
PCH_CS0_N
PCH_SCK
LED Controller
SMART AMP
GSPI1_MOSI19
GSPI0_MOSI19
PCH_UART2_TXD50
PCH_UART2_RXD50
PCH_I2C_CLK146
PCH_I2C_DATA146
PCH_I2C_CLK028
PCH_I2C_DATA028
PCH_SI50
PCH_WP_N50
4
GSPI1_MOSI
GSPI0_MOSI
PCH_UART2_CTS_N
PCH_UART2_RTS_N
PCH_UART2_TXD
PCH_UART2_RXD
PCH_I2C_CLK1
PCH_I2C_DATA1
PCH_I2C_CLK0
PCH_I2C_DATA0
PCH_SI
PCH_SO
PCH_CS0_N
PCH_SCK
PCH_WP_N
PCH_HOLD_N
U2K
AT29
GPP_B22/GSPI1_MOSI
AR29
GPP_B21/GSPI1_MISO
AV29
GPP_B20/GSPI1_CLK
BC27
GPP_B19/GSPI1_CS#
BD28
GPP_B18/GSPI0_MOSI
BD27
GPP_B17/GSPI0_MISO
AW27
GPP_B16/GSPI0_CLK
AR24
GPP_B15/GSPI0_CS#
AV44
GPP_C9/UART0_TXD
BA41
GPP_C8/UART0_RXD
AU44
GPP_C11/UART0_CTS#
AV43
GPP_C10/UART0_RTS#
AU41
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
AT44
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AT43
GPP_C13/UART1_TXD/ISH_UART1_TXD
AU43
GPP_C12/UART1_RXD/ISH_UART1_RXD
AN43
GPP_C23/UART2_CTS#
AN44
GPP_C22/UART2_RTS#
AR39
GPP_C21/UART2_TXD
AR45
GPP_C20/UART2_RXD
AR41
GPP_C19/I2C1_SCL
AR44
GPP_C18/I2C1_SDA
AR38
GPP_C17/I2C0_SCL
AT42
GPP_C16/I2C0_SDA
AM44
GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
AJ44
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL
SPT_PCH_H
REV = 1.3
U2A
BD17
GPP_A11/PME#
AG15
RSVD
AG14
RSVD
AF17
RSVD
AE17
RSVD
AR19
TP2
AN17
TP1
BB29
SPI0_MOSI
BE30
SPI0_MISO
BD31
SPI0_CS0#
BC31
SPI0_CLK
AW31
SPI0_CS1#
BC29
SPI0_IO2
BD30
SPI0_IO3
AT31
SPI0_CS2#
AN36
GPP_D1/SPI1_CLK
AL39
GPP_D0/SPI1_CS#
AN41
GPP_D3/SPI1_MOSI
AN38
GPP_D2/SPI1_MISO
AH43
GPP_D22/SPI1_IO3
AG44
GPP_D21/SPI1_IO2
SPT_PCH_H
REV = 1.3
3
?
SPT-H_PCH
GPP_D16/ISH_UART0_CTS#
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
?
SPT-H_PCH
GPP_D15/ISH_UART0_RTS#
GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
11 OF 12
?
GPP_B13/PLTRST#
GPP_G16/GSXCLK
GPP_G12/GSXDOUT
GPP_G13/GSXSLOAD
GPP_G14/GSXDIN
GPP_G15/GSXSRESET#
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_H18/SML4ALERT#
GPP_H17/SML4DATA
GPP_H16/SML4CLK
GPP_H15/SML3ALERT#
GPP_H14/SML3DATA
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
GPP_H11/SML2DATA
GPP_H10/SML2CLK
INTRUDER#
1 OF 12
?
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7
BB27
P43
R39
R36
R42
R41
AF41
AE44
BC23
BD24
BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
BE11
GPP_D9
GPP_D10
GPP_D11
GPP_D12
DGPU_PWROK_N
AL44
AL36
AL35
AJ39
AJ43
AL43
AK44
AK45
BC38
BB38
BD38
BE39
BC22
BD18
BE21
BD22
BD21
BB22
BC19
R270 0_0402_5%@
DISPLAY_SELECT
PCH_INTRUDER_N
1 2
PCH_I2C_CLK2
PCH_I2C_DATA2
2
26
26
PCH_PLTRST_N
FPBACK
LC_INT0_N
CAM_PWR_EN
DGPU_PWROK
EC_INT_N
RF_KILL_BT_N
RF_KILL_WIFI_N
GPU_EVENT_N
GC6_FB_EN
1
+3V
EC
49
31
46
90
51,71,80
26
41
41
59
59,60,71
PCH_I2C_CLK2
PCH_I2C_DATA2
FPBACK
CAM_PWR_EN
RF_KILL_WIFI_N
RF_KILL_BT_N
GPU_EVENT_N
PCH_INTRUDER_N
CAD Note
CRB use 330KR;DG use 1MR
12
R548 1K_0402_5%
12
R549 1K_0402_5%
12
R97 100K_0402_5%@
1 2
R103 10K_0402_5%
1 2
R99 10K_0402_5%
1 2
R102 10K_0402_5%
1 2
R112 10K_0402_5%@
12
R114 1M_0402_5%
：
+3V
+3V
+VCC_RTC
PLT_RST_N Buffer
PLT_RST_NPCH_PLTRST_N
R123
100K_0402_5%
EC/SSD/LAN/WLAN/CR/XDP
PLT_RST_N
26,27,36,38,41,42,48,49,59
DISPLAY_MUX_SW Buffer
R127
10K_0402_5%
DISPLAY_MUX_SWDISPLAY_SELECT
R779
@
100_0402_5%
Title
Title
Title
Size Document Number
Size Document Number
Size Document Number
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
CAD Note：DISPLAY_MUX_SW
L=CPU output selected
H=dGPU output selected(default)
DISPLAY_MUX_SW
PCH-SPI/I2C/GPIO
PCH-SPI/I2C/GPIO
PCH-SPI/I2C/GPIO
C
C
C
Skylake-H
Skylake-H
Skylake-H
1
30,31,32,34,35,58
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
17
17
17
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
2
A
5
NC
1
B
1 2
R117 0_0402_5%@
2
5
1
+3V
2
C179
0.1U_0402_25V6
1
6
U4
Vcc
4
Y
Gnd
74AUP1G08GF_SOT891-6_1X1
3
AND Gate
+3V
2
C474
@
0.1U_0402_25V6
1
6
U49
Vcc
A
4
R545 0_0402_5%@
Y
NC
B
Gnd
74AUP1G08GF_SOT891-6_1X1
3
AND Gate
@
2
1 2
PLT_RST_NPCH_PLTRST_N
+3V
1 2
1 2
1 2
SPI ROM
B B
A A
+3VALW_PCH
R115 0_0603_5%
PCH_SO
PCH_WP_N
R119 15_0402_5%
R121 15_0402_5%
PCH_SCK_R26
PCH_CS0_N26
PCH_SI_R26
PCH_SO_R26
5
+3VALW_SPI
12
12
12
1
C177
10U_0402_6.3V6M
2
PCH_CS0_N
PCH_SO_R
PCH_WP_N_R PCH_SCK
PCH_SCK_R
PCH_CS0_N
PCH_SI_R
PCH_SO_R
2
C178
0.1U_0402_25V6
1
U3
1
CS
2
DO
3
WP
GND4DI
W25R128FVSIQ_SO8
16MB
+3VALW_SPI
R116 1K_0402_5%
R118 1K_0402_5%
R126 1K_0402_5%@
CAD Note:PCH_HOLD_N(PCH SPI0_IO3)
PD:INTEL MOW for SKL-H Pre-ES1/ES1 sample
+3VALW_SPI
8
VCC
7
PCH_HOLD_N_R
HOLD
6
PCH_SCK_R
CLK
5
PCH_SI_R
R125 10K_0402_5%@
CAD Note:PCH_SI
PD:For EC Mirror Code feature
12
12
12
R120 15_0402_5%
R122 15_0402_5%
R124 15_0402_5%
12
4
12
12
12
PCH_WP_N
PCH_HOLD_N_R
PCH_HOLD_N
PCH_SI
PCH_HOLD_N
PCH_SI
1
C180
@
100P_0402_50V8J
2
1
C218
@
100P_0402_50V8J
2
3
5
Flexible I/O Configuration
I / O High Speed Signals GEN
Port 7
USB3_7 / PCIE 1
D D
C C
B B
Port 8
USB3_8 / PCIE 2
Port 9
USB3_9 / PCIE 3
Port 10
USB3_10 / PCIE 4
Port 11
Port 12
Port 13
Port 14
BRD Note: PCIE_RCOMP*
W=15mils;S=15mils;
4 mils PIPE GND shiedling required;
Avoid routing next to clock
Lenght matched within 1%
Card Reader
WLAN
LAN
PCIE 5
PCIE 6
PCIE 7
PCIE 8
PCIE_CR_TX_C_DN48
PCIE_CR_TX_C_DP48
PCIE_WLAN_TX_C_DN41
PCIE_WLAN_TX_C_DP41
PCIE_LAN_TX_C_DN27
PCIE_LAN_TX_C_DP27
BRD Note：PCIE BUS
All the AC-coupling caps placed close to device down or connector;
Non-interleaved breakout is required
Configuration DEVICE
AR (L0)
AR (L1)
AR (L2)
AR (L3)
NC
Card Reader
WLAN
LAN
PCIE1_TBT_RX_DN036
PCIE1_TBT_RX_DP036
PCIE1_TBT_TX_DN036
PCIE1_TBT_TX_DP036
PCIE2_TBT_TX_DN136
PCIE2_TBT_TX_DP136
PCIE2_TBT_RX_DN136
PCIE2_TBT_RX_DP136
PCIE3_TBT_RX_DN236
PCIE3_TBT_RX_DP236
PCIE3_TBT_TX_DN236
PCIE3_TBT_TX_DP236
PCIE4_TBT_RX_DN336
PCIE4_TBT_RX_DP336
PCIE4_TBT_TX_DN336
PCIE4_TBT_TX_DP336
PCIE_CR_RX_DN48
PCIE_CR_RX_DP48
PCIE_WLAN_RX_DN41
PCIE_WLAN_RX_DP41
PCIE_LAN_RX_DN27
PCIE_LAN_RX_DP27
DMI_MT_IR_0_DN2
DMI_MT_IR_0_DP2
DMI_IT_MR_0_DN2
DMI_IT_MR_0_DP2
DMI_MT_IR_1_DN2
DMI_MT_IR_1_DP2
DMI_IT_MR_1_DN2
DMI_IT_MR_1_DP2
DMI_MT_IR_2_DN2
DMI_MT_IR_2_DP2
DMI_IT_MR_2_DN2
DMI_IT_MR_2_DP2
DMI_MT_IR_3_DN2
DMI_MT_IR_3_DP2
DMI_IT_MR_3_DN2
DMI_IT_MR_3_DP2
R129 100_0402_1%
1 2
C181 0.1U_0402_16V7K
1 2
C182 0.1U_0402_16V7K
1 2
C183 0.1U_0402_16V7K
1 2
C184 0.1U_0402_16V7K
1 2
C185 0.1U_0402_16V7K
1 2
C186 0.1U_0402_16V7K
U2005
(Intel
AR
DP）
U3001
JWLAN1
U6
1 2
4
PCIE 1x Gen2
PCIE 1x Gen2
PCIE1x Gen1
PCIE_CR_TX_DP
PCIE_WLAN_TX_DN
PCIE_WLAN_TX_DP
PCIE_LAN_TX_DN
PCIE_LAN_TX_DP
PCIE_RCOMPN
PCIE_RCOMPP
U2B
L27
DMI_RXN0
N27
DMI_RXP0
C27
DMI_TXN0
B27
DMI_TXP0
E24
DMI_RXN1
G24
DMI_RXP1
B28
DMI_TXN1
A28
DMI_TXP1
G27
DMI_RXN2
E26
DMI_RXP2
B29
DMI_TXN2
C29
DMI_TXP2
L29
DMI_RXN3
K29
DMI_RXP3
B30
DMI_TXN3
A30
DMI_TXP3
B18
PCIE_RCOMPN
C17
PCIE_RCOMPP
H15
PCIE1_RXN/USB3_7_RXN
G15
PCIE1_RXP/USB3_7_RXP
A16
PCIE1_TXN/USB3_7_TXN
B16
PCIE1_TXP/USB3_7_TXP
B19
PCIE2_TXN/USB3_8_TXN
C19
PCIE2_TXP/USB3_8_TXP
E17
PCIE2_RXN/USB3_8_RXN
G17
PCIE2_RXP/USB3_8_RXP
L17
PCIE3_RXN/USB3_9_RXN
K17
PCIE3_RXP/USB3_9_RXP
B20
PCIE3_TXN/USB3_9_TXN
C20
PCIE3_TXP/USB3_9_TXP
E20
PCIE4_RXN/USB3_10_RXN
G19
PCIE4_RXP/USB3_10_RXP
B21
PCIE4_TXN/USB3_10_TXN
A21
PCIE4_TXP/USB3_10_TXP
K19
PCIE5_RXN
L19
PCIE5_RXP
D22
PCIE5_TXN
C22
PCIE5_TXP
G22
PCIE6_RXN
E22
PCIE6_RXP
B22
PCIE6_TXN
A23
PCIE6_TXP
L22
PCIE7_RXN
K22
PCIE7_RXP
C23
PCIE7_TXN
B23
PCIE7_TXP
K24
PCIE8_RXN
L24
PCIE8_RXP
C24
PCIE8_TXN
B24
PCIE8_TXP
SPT_PCH_H
REV = 1.3
SPT-H_PCH
DMI
PC
Ie/USB 3
?
3
USB 2.0
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7
USB2_COMP
USB2_VBUSSENSE
RSVD_AB13
GPD7/RSVD
2 OF 12
?
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14
USB2_ID
AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
AJ11
AJ13
AD43
AD42
AD39
AC44
Y43
Y41
W44
W43
AG3
USB2_COMPPCIE_CR_TX_DN
AD10
USB_OTG_VBUSSENSE
AB13
AG2
USB2_OTG_ID
BD14
USB_OC_N
R130 113_0402_1%
R62 1K_0402_5%
R63 1K_0402_5%
USB2.0 Configuration
USB2 # Assignment
JUSB3(I
USB2 1
JUSB2
USB2 2
HD camera
USB2 3
USB2 4
KB
USB2 5
BT
USB2 6
JUSB4(IO DB)
USB2 7
NC
NC
USB2 8
Finger print
USB2 9
NC
USB2 10
USB2 11
NC
USB2 12
NC
USB2 13
NC
USB2 14
NC
USB_OC0_N 48
USB_OC1_N
USB_OC2_N
USB_OC3_N
1 2
12
12
2
OCx #
O DB）
USB_OC0_N
USB_OC1_N
USB_OC3_N
USB2_DN1
48
USB2.0 PORT (IO)
48
USB2_DP1
USB2_DN2
39
USB3.0 PORT
39
USB2_DP2
31
USB2_DN3
USB2_DP3
USB2_DN4
USB2_DP4
USB2_DN5
USB2_DP5
USB2_DN6
USB2_DP6
USB2_DN9
USB2_DP9
HD CAMERA
31
47
KB
47
41
BT
41
48
USB2.0 PORT (IO)
48
45
FPR
45
39
39
48
BRD Note: USB2_COMP
Total length within 1 inch;
S=15mils;
4 mils PIPE GND shiedling suggested
USB_OC0_N
USB_OC2_N
USB_OC1_N
USB_OC3_N
USB_OC_N
1
RP1
1 8
2 7
3 6
4 5
10K_8P4R_5%
12
R875 10K_0402_5%
+3VALW_PCH
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
18
18
18
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
PCH-DMI/PCIE/USB2.0
PCH-DMI/PCIE/USB2.0
PCH-DMI/PCIE/USB2.0
Size Document Number
Size Document Number
Size
Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
：
PCH_GPP_B23
12
12
12
12
12
12
HDA_BCLK28
HDA_SYNC28
HDA_SDOUT28
HDA_RST_N28
CAD Note：HDA_RST_N
Reserve and use the codec internal RST# default
D D
AUD_AZACPU_SDO3
AUD_AZACPU_SCLK3
+3VALW_PCH
R150 1K_0402_5%
R151 1K_0402_5%
R153 1K_0402_5%
R155 1K_0402_5%
R158 1K_0402_5%
C C
R159 1K_0402_5%
R131 33_0402_5%
R132 33_0402_5%
R134 33_0402_5%
R135 33_0402_5%@
R140 33_0402_5%
R141 33_0402_5%
1 2
R147 10K_0402_5%@
1 2
R149 10K_0402_5%
1 2
R547 10K_0402_5%@
CAD Note
Reserve for PCH strpping
12
12
12
12
12
12
PM_PCH_PWROK
PM_RSMRST_N
PCH_GPP_B23
SML0_CLK
SML0_DATA
SMB_CLK
SMB_DATA
SML1_CLK
SML1_DATA
HDA_BCLK_R
HDA_SYNC_R
HDA_SDOUT_R
HDA_RST_N_R
AUD_AZACPU_SDO_R
AUD_AZACPU_SCLK_R
HDA_SDIN28
AUD_AZACPU_SDI3
PM_PCH_PWROK26
PM_RSMRST_N26
SMB_CLK76
SMB_DATA76
4
HDA_BCLK_R
HDA_RST_N_R
HDA_SDIN
HDA_SDOUT_R
HDA_SYNC_R
AUD_AZACPU_SDO_R
AUD_AZACPU_SDI
AUD_AZACPU_SCLK_R
RTCRST_N
SRTCRST_N
SMBALERT_N
SMB_CLK
SMB_DATA
SML0ALERT_N
SML0_CLK
SML0_DATA
PCH_GPP_B23
SML1_CLK
SML1_DATA
U2D
BA9
HDA_BCLK
BD8
HDA_RST#
BE7
HDA_SDI0
BC8
HDA_SDI1
BB7
HDA_SDO
BD9
HDA_SYNC
BD1
RSVD_BD1
BE2
RSVD_BE2
AM1
DISPA_SDO
AN2
DISPA_SDI
AM2
DISPA_BCLK
AL42
GPP_D8/I2S0_SCLK
AN42
GPP_D7/I2S0_RXD
AM43
GPP_D6/I2S0_TXD
AJ33
GPP_D5/I2S0_SFRM
AH44
GPP_D20/DMIC_DATA0
AJ35
GPP_D19/DMIC_CLK0
AJ38
GPP_D18/DMIC_DATA1
AJ42
GPP_D17/DMIC_CLK1
BC10
RTCRST#
BB10
SRTCRST#
AW11
PCH_PWROK
BA11
RSMRST#
AV11
DSW_PWROK
BB41
GPP_C2/SMBALERT#
AW44
GPP_C0/SMBCLK
BB43
GPP_C1/SMBDATA
BA40
GPP_C5/SML0ALERT#
AY44
GPP_C3/SML0CLK
BB39
GPP_C4/SML0DATA
AT27
GPP_B23/SML1ALERT#/PCHHOT#
AW42
GPP_C6/SML1CLK
AW45
GPP_C7/SML1DATA
SPT_PCH_H
REV = 1.3
AUDIO
3
?
SPT-H_PCH
GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
GPP_G17/ADR_COMPLETE
GPP_A13/SUSWARN#/SUSPWRDNACK
SM
BUS
JTAG
4 OF 12
?
GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#
DRAM_RESET#
GPP_B2/VRALERT#
GPP_B1
GPP_B0
GPP_B11
SYS_PWROK
WAKE#
GPD6/SLP_A#
SLP_LAN#
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD8/SUSCLK
GPD0/BATLOW#
GPP_A15/SUSACK#
GPD2/LAN_WAKE#
GPD1/ACPRESENT
SLP_SUS#
GPD3/PWRBTN#
SYS_RESET#
GPP_B14/SPKR
PROCPWRGD
ITP_PMODE
JTAGX
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
BB17
AW22
PCH_CLKRUN_N
AR15
AV13
BC14
DRAM_CRESET_N
BD23
PCH_VRALERT_N
AL27
AR27
N44
AN24
MPHY_EXT_PWR_GATE_N
AY1
SYS_PWROK
BC13
PCIE_WAKE_N
BC15
AV15
BC26
AW15
SLP_S3_N_R
BD15
SLP_S4_N_R
BA13
SLP_S5_N
AN15
SUSCLK
BD13
PM_BATLOW_N
BB19
SUSACK_N
BD19
SUSPWRDNACK
BD11
PCH_LAN_WAKE_N
BB15
AC_PRESENT
BB13
SLP_SUS_N
AT13
PCH_PWRBTN_N
AW1
SYS_RESET_N
BD26
HDA_SPKR
AM3
H_PWRGD
AT2
PCH_ITP_PMODE
AR3
PCH_JTAGX
AR2
PCH_JTAG_TMS
AP1
PCH_JTAG_TDO
AP2
PCH_JTAG_TDI
AN3
PCH_JTAG_TCK
2
CAD Note：PCH_VRALERT_N
ICC max throttling indicator for the
PCH voltage regulators
DRAM_CRESET_N
1
TP76
SYS_PWROK
PCIE_WAKE_N
1 2
R144 0_0402_5%
1 2
R145 0_0402_5%
1
TP71
1
TP72
1
TP73
1
TP74
1 2
R178 0_0402_5%@
1
TP79
SLP_S3_N
SLP_S4_N
SUSCLK
AC_PRESENT
PCH_PWRBTN_N
FP_RST_N
HDA_SPKR
H_PWRGD
PCH_ITP_PMODE
PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_CLKRUN_N
16
26
36,41
26,36
26,76
41
26
26,50
50
28
6
50
50
50
50
50
SYS_RESET_N
PCH_VRALERT_N
PCIE_WAKE_N
PM_BATLOW_N
AC_PRESENT
PCH_LAN_WAKE_N
PCH_PWRBTN_N
SYS_PWROK
SUSCLK
：
PCH_PWRBTN_N
CAD Note
PCH internal PU and 16ms de-bounce
1
12
R136 8.2K_0402_5%
1 2
R143 10K_0402_5%
1 2
R137 10K_0402_5%@
1 2
R138 10K_0402_5%
12
R139 8.2K_0402_5%
1 2
R142 10K_0402_5%
1 2
R288 10K_0402_5%
12
R381 100K_0402_5%
1 2
R146 10K_0402_5%@
1 2
R148 10K_0402_5%@
+3V
+3VALW_PCH
PCH Straps
+VCC_RTC
CAD Note
：
CRB use 30.1KR;DG use 20KR
12
R160 20K_0402_1%
12
R163 20K_0402_1%
B B
A A
+3V
+3VALW_PCH
+3V
+3V
+3V
+3V
R164 1K_0402_5%@
R167 1K_0402_5%@
R168 1K_0402_5%@
1 2
R169 4.7K_0402_5%@
R170 1K_0402_5%@
R372 20K_0402_1%@
R171 1K_0402_5%@
R506 20K_0402_1%@
12
12
12
12
12
12
12
5
SRTCRST_N
1
C187
1U_0402_10V6K
2
1
RTCRST_N
1
C188
1U_0402_10V6K
2
1
HDA_SPKR
HDA_SDOUT
GSPI0_MOSI 17
SMBALERT_N
SML0ALERT_N
GSPI1_MOSI
TP77
TP78
ME RESET
SRTCRST_N
1:SAVE ME (Default)
0:CLEAR ME
CMOS RESET
RTCRST_N
1:SAVE CMOS (Default)
0:CLEAR CMOS
Top Swap MODE
HDA_SPKR
1:Enabled
0:Disabled(Default),Internal PD
Flash Descriptor Security Override
HDA_SDOUT
1:Disabled
0:Enabled(Default),Internal PD
TCO Timer System No Reboot mode
GSPI0_MOSI
1:Enable "No reboot" mode
0:Disable (Default),Internal PD
Intel ME TLS cipher suite
SMBALERT_N
1:Enabled
0:Disabled(Default),Internal PD
eSPI or LPC bus for EC
SML0ALERT_N
Boot BIOS Destination Bit 10
17
GSPI1_MOSI
1:eSPI
0:LPC(Default),Internal PD
1:LPC
0:SPI(Default),Internal PD
4
*
*
SMB_CLK
SMB_DATA
3 4
Q1B
AO5804EL_SC89-6
*
*
SML1_CLK
SML1_DATA
3 4
Q2B
AO5804EL_SC89-6
*
*
：
EC_CLEAR_CMOS
CAD Note
LOW:Keep CMOS
Hi:Clear CMOS
EC_CLEAR_CMOS26
EC_CLEAR_CMOS
*
*
3
SMBus Isolation
2.2K_0402_5%
2
6 1
5
Q1A
AO5804EL_SC89-6
2.2K_0402_5%
2
6 1
5
Q2A
AO5804EL_SC89-6
EC Clear CMOS
1
R428
100K_0402_5%
2
C401
@
0.1U
_0402_25V6
2
2
12
+3V+3V
12
R161
+3V+3V
12
R165
RTCRST_N
1
Q12
DMG1012T-7_SOT523-3
3
12
R162
2.2K_0402_5%
12
R166
2.2K_0402_5%
PCH_SMB_CLK
16,45,50
SODIMM/TP/XDP
PCH_SMB_DAT
EC_SMB_CLK1
16,45,50
26,44,59
EC
EC_SMB_DAT1
Title
Title
Title
PCH-HDA/PM/SMBUS/STRAP
PCH-HDA/PM/SMBUS/STRAP
PCH-HDA/PM/SMBUS/STRAP
Size Document Number
Size Document Number
Size Document Number
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
Skylake-H
Skylake-H
Skylake-H
26,44,59
1
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
19
19
19
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
of
5
D D
+3VALW_PCH
12
R172 100K_0402_5%@
1 2
R413 10K_0402_5%@
12
R105 100K_0402_5%@
12
C C
B B
R414 100K_0402_5%@
+3V
1 2
R173 10K_0402_5%
POA_RESET_N
POA_ENABLE_N
POA_POWERREQ
POA_ACTIVE
EC_SCI_N
SATA HDD
POA_ENABLE_N45
POA_POWERREQ 45
POA_ACTIVE45
EC_SCI_N26
POA_RESET_N45
SATA_TX_DP043
SATA_TX_DN043
SATA_RX_DP043
SATA_RX_DN043
4
POA_ENABLE_N
POA_POWERREQ
POA_ACTIVE
EC_SCI_N
POA_RESET_N
SATA_TX_DP0
SATA_TX_DN0
SATA_RX_DP0
SATA_RX_DN0
U2C
AV2
CL_CLK
AV3
CL_DATA
AW2
CL_RST#
R44
GPP_G8/FAN_PWM_0
R43
GPP_G9/FAN_PWM_1
U39
GPP_G10/FAN_PWM_2
N42
GPP_G11/FAN_PWM_3
U43
GPP_G0/FAN_TACH_0
U42
GPP_G1/FAN_TACH_1
U41
GPP_G2/FAN_TACH_2
M44
GPP_G3/FAN_TACH_3
U36
GPP_G4/FAN_TACH_4
P44
GPP_G5/FAN_TACH_5
T45
GPP_G6/FAN_TACH_6
T44
GPP_G7/FAN_TACH_7
AB33
GPP_F10/SCLOCK
AB35
GPP_F11/SLOAD
AA44
GPP_F13/SDATAOUT0
AA45
GPP_F12/SDATAOUT1
J45
PCIE20_TXP/SATA7_TXP
K44
PCIE20_TXN/SATA7_TXN
N38
PCIE20_RXP/SATA7_RXP
N39
PCIE20_RXN/SATA7_RXN
G44
PCIE18_TXP/SATA5_TXP
G45
PCIE18_TXN/SATA5_TXN
G37
PCIE18_RXP/SATA5_RXP
K37
PCIE18_RXN/SATA5_RXN
F45
PCIE17_TXP/SATA4_TXP
E45
PCIE17_TXN/SATA4_TXN
H40
PCIE17_RXP/SATA4_RXP
H42
PCIE17_RXN/SATA4_RXN
AB44
GPP_F4/SATAXPCIE7/SATAGP7
AC43
GPP_F3/SATAXPCIE6/SATAGP6
AD38
GPP_F2/SATAXPCIE5/SATAGP5
AD31
GPP_F1/SATAXPCIE4/SATAGP4
AD35
GPP_F0/SATAXPCIE3/SATAGP3
AG39
GPP_E2/SATAXPCIE2/SATAGP2
AG35
GPP_E1/SATAXPCIE1/SATAGP1
AG36
GPP_E0/SATAXPCIE0/SATAGP0
SPT_PCH_H
REV = 1.3
CLINK
SPT-H_PCH
?
FAN
PC
Ie/SATA
HOST
3
PCIE19_RXN/SATA6_RXN
PCIE19_RXP/SATA6_RXP
PCIE19_TXN/SATA6_TXN
PCIE19_TXP/SATA6_TXP
GPP_E8/SATALED#
PCIE13_RXN/SATA0B_RXN
PCIE13_RXP/SATA0B_RXP
PCIE13_TXN/SATA0B_TXN
PCIE13_TXP/SATA0B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP
PCIE14_TXN/SATA1B_TXN
PCIE14_TXP/SATA1B_TXP
PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN
PCIE9_TXP/SATA0A_TXP
PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP
GPP_F21/EDP_BKLTCTL
GPP_F20/EDP_BKLTEN
GPP_F19/EDP_VDDEN
PLTRST_PROC#
3 OF 12
?
PCIE11_RXN
PCIE11_RXP
PCIE11_TXN
PCIE11_TXP
PCIE12_RXN
PCIE12_RXP
PCIE12_TXN
PCIE12_TXP
THERMTRIP#
PM_SYNC
PM_DOWN
PECI
L37
L39
H43
H44
AD44
G35
E35
C36
B36
D39
E37
B38
C38
F41
E41
B39
A39
D43
E42
A41
A40
G31
H31
C31
B31
G29
E29
C32
B32
L31
K31
C33
B33
G33
H33
B35
A35
W36
W35
W42
AJ3
AL3
AJ4
AK2
AH2
Flexible I/O Configuration
I / O
Port 15
Port 16
Port 17
Port 18
Port 19
Port 20
Port 21
Port 22
Port 23
Port 24
Port 25
Port 26
PCH_GPP_E8
PCIE13_SSD1_RX_DN0
PCIE13_SSD1_RX_DP0
PCIE13_SSD1_TX_DN0
PCIE13_SSD1_TX_DP0
PCIE14_SSD1_RX_DN1
PCIE14_SSD1_RX_DP1
PCIE14_SSD1_TX_DN1
PCIE14_SSD1_TX_DP1
PCIE15_SSD1_RX_DN2
PCIE15_SSD1_RX_DP2
PCIE15_SSD1_TX_DN2
PCIE15_SSD1_TX_DP2
PCIE16_SSD1_RX_DN3
PCIE16_SSD1_RX_DP3
PCIE16_SSD1_TX_DN3
PCIE16_SSD1_TX_DP3
PCIE9_SSD2_RX_DN0
PCIE9_SSD2_RX_DP0
PCIE9_SSD2_TX_DN0
PCIE9_SSD2_TX_DP0
PCIE10_SSD2_RX_DN1
PCIE10_SSD2_RX_DP1
PCIE10_SSD2_TX_DN1
PCIE10_SSD2_TX_DP1
PCIE11_SSD2_RX_DN2
PCIE11_SSD2_RX_DP2
PCIE11_SSD2_TX_DN2
PCIE11_SSD2_TX_DP2
PCIE12_SSD2_RX_DN3
PCIE12_SSD2_RX_DP3
PCIE12_SSD2_TX_DN3
PCIE12_SSD2_TX_DP3
PCH_EDP_BL_PWM
PCH_EDP_BL_EN
PCH_EDP_VDD_EN
PCH_THERMTRIP_N
PCH_PECI
H_PM_SYNC_R
CPU_PLTRST_N_R
H_PM_DOWN
2
High Speed Signals GEN
SATA 0A / PCIE 9
SATA 1A / PCIE 10
/ PCIE 11
/ PCIE 12
SATA 0B / PCIE 13
SATA 1B / PCIE 14
SATA 2 / PCIE 15
SATA 3 / PCIE 16
SATA 4 / PCIE 17
SATA 5 / PCIE 18
SATA6 / PCIE 19
SATA7 / PCIE 20
1
TP160
R287 604_0402_1%
R174 12.1_0402_5%
R175 33_0402_5%
R176 0_0402_5%
12
R177
@
10K_0402_5%
M.2 SSD2 (L0) / SATA0
M.2 SSD2 (L1)
M.2 SSD2 (L2)
M.2 SSD2 (L3)
M.2 SSD12(L0)
M.2 SSD1 (L1)
M.2 SSD1 (L2)
M.2 SSD1 (L3)
SATA HDD
NC
NC
NC
1 2
1 2
1 2
1 2
Configuration
DEVICE
JSSD2
JSSD1
U14
PCIE13_SSD1_RX_DN0
PCIE13_SSD1_RX_DP0
PCIE13_SSD1_TX_DN0
PCIE13_SSD1_TX_DP0
PCIE14_SSD1_RX_DN1
PCIE14_SSD1_RX_DP1
PCIE14_SSD1_TX_DN1
PCIE14_SSD1_TX_DP1
PCIE15_SSD1_RX_DN2
PCIE15_SSD1_RX_DP2
PCIE15_SSD1_TX_DN2
PCIE15_SSD1_TX_DP2
PCIE16_SSD1_RX_DN3
PCIE16_SSD1_RX_DP3
PCIE16_SSD1_TX_DN3
PCIE16_SSD1_TX_DP3
PCIE9_SSD2_RX_DN0
PCIE9_SSD2_RX_DP0 42
PCIE9_SSD2_TX_DN0
PCIE9_SSD2_TX_DP0
PCIE10_SSD2_RX_DN1
PCIE10_SSD2_RX_DP1
PCIE10_SSD2_TX_DN1
PCIE10_SSD2_TX_DP1
PCIE11_SSD2_RX_DN2
PCIE11_SSD2_RX_DP2
PCIE11_SSD2_TX_DN2
PCIE11_SSD2_TX_DP2
PCIE12_SSD2_RX_DN3
PCIE12_SSD2_RX_DP3
PCIE12_SSD2_TX_DN3
PCIE12_SSD2_TX_DP3 42
PCH_EDP_BL_PWM
PCH_EDP_BL_EN
PCH_EDP_VDD_EN
H_THRMTRIP_N
H_PECI
6,26
H_PM_SYNC
CPU_PLTRST_N
H_PM_DOWN
6
6
PCIE 4x Gen 3
/SATA Gen 3
PCIE 4 x Gen 3
SATA Gen 3
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
31
31
31
6,71
6
1
Gen3
PCIE SSD1
Gen3
PCIE SSD2
BRD Note：PCIE BUS
All the AC-coupling caps placed close to connector side;
Non-interleaved breakout is required
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
20
20
20
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
PCH-PCIE/SATA/HOST
PCH-PCIE/SATA/HOST
PCH-PCIE/SATA/HOST
Size Document Number
Size Document Number
Size
Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
D D
4
3
2
Flexible I/O Configuration
I / O
High Speed Signals Configuration DEVICE
Port 1 USB3 1 Capable of OTG
Port 2
USB2 3 / SSIC 1
Port 3
USB3 3 / SSIC 2
Port 4
USB3 4
USB3 5
Port 5
USB3 6
Port 6
NC
NC
USB3.0 JUSB2 USB_OC1_N
NC
NC
NC
1
OCx #
+3V
12
R179 10K_0402_5%
12
R180 10K_0402_5%
1 2
R181 10K_0402_5%
1 2
R182 10K_0402_5%
+3V
12
R303 10K_0402_5%
C C
B B
SERIRQ
H_A20GATE
KBRST_N
EC_SMI_N
PCH_GPP_G18
CAD Note
：
LPC:24M Hz
eSPI:20/30/60M Hz
LPC_AD0_ESPI_IO026
LPC_AD1_ESPI_IO126
LPC_AD2_ESPI_IO226
LPC_AD3_ESPI_IO326
LPC_FRAME_N_ESPI_CS_N26
SERIRQ26
H_A20GATE26
KBRST_N26
LPC_PD_N_ESPI_RST_N26
CK_LPC/ESPI_CLK26
EC_SMI_N26
1 2
R183 22_0402_5%
TP184
TP122
TP169
TP168
TP171
TP170
1
1
1
1
1
1
CK_LPC/ESPI_CLK_R
CK_LPC1
PCH_GPP_G18
BOARD_ID2
BOARD_ID1
BOARD_ID0
PCH_GPP_F9
PCH_GPP_F8
PCH_GPP_F7
PCH_GPP_F6
U2F
AT22
GPP_A1/LAD0/ESPI_IO0
AV22
GPP_A2/LAD1/ESPI_IO1
AT19
GPP_A3/LAD2/ESPI_IO2
BD16
GPP_A4/LAD3/ESPI_IO3
BE16
GPP_A5/LFRAME#/ESPI_CS0#
BA17
GPP_A6/SERIRQ/ESPI_CS1#
AW17
GPP_A7/PIRQA#/ESPI_ALERT0#
AT17
GPP_A0/RCIN#/ESPI_ALERT1#
BC18
GPP_A14/SUS_STAT#/ESPI_RESET#
BC17
GPP_A9/CLKOUT_LPC0/ESPI_CLK
AV19
GPP_A10/CLKOUT_LPC1
M45
GPP_G19/SMI#
N43
GPP_G18/NMI#
AE45
GPP_E6/DEVSLP2
AG43
GPP_E5/DEVSLP1
AG42
GPP_E4/DEVSLP0
AB39
GPP_F9/DEVSLP7
AB36
GPP_F8/DEVSLP6
AB43
GPP_F7/DEVSLP5
AB42
GPP_F6/DEVSLP4
AB41
GPP_F5/DEVSLP3
SPT_PCH_H
REV = 1.3
6 OF 12
?
SATA
?
SPT-H_PCH
LPC/eSPI
USB3_1_TXN
USB3_1_TXP
USB3_1_RXN
USB3_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_6_TXN
USB3_6_TXP
US
USB3_6_RXN
B
USB3_6_RXP
USB3_5_TXN
USB3_5_TXP
USB3_5_RXN
USB3_5_RXP
USB3_3_TXP/SSIC_2_TXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_RXN/SSIC_2_RXN
USB3_4_TXP
USB3_4_TXN
USB3_4_RXP
USB3_4_RXN
C11
B11
B7
A7
B12
A12
C8
B8
B15
C15
K15
K13
B14
C14
BRD Note:USB3.0
G13
Non-interleaved breakout is required
H13
D13
C13
A9
B10
B13
A14
G11
E11
USB3_TX_DP3
USB3_TX_DN3
USB3_RX_DP3
USB3_RX_DN3
39
39
39
39
USB3.0 PORT
+3V
3
BOARD_ID1
BOARD_ID0 Description
00
0
1
01
11
00
01
10
11
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
21
21
21
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
PCH-USB3.0/LPC
PCH-USB3.0/LPC
PCH-USB3.0/LPC
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
2
R185
1 2
10K_0402_5%
10K_0402_5%
R187
@
1 2
10K_0402_5%
10K_0402_5%
R186
1 2
R188
@
1 2
10K_0402_5%
10K_0402_5%
BOARD_ID2
BOARD_ID1
BOARD_ID0
R856
1 2
R855
A A
5
@
1 2
4
BOARD_ID2
0
0
0
0
1
1
1
1
5
4
3
2
1
+3V
D D
C C
+3V
+3V
BRD Note: XCLK_BIASREF
Ground reference;Max via:2
Isolation spacing:20mils
Segment Length:100mils;Total length:1000mils
VSS shield recommened;S:W:S=6:4:6
RP2
1 8
2 7
3 6
4 5
10K_8P4R_5%
1 2
R787 10K_0402_5%
1 2
R304 10K_0402_5%
1 2
R309 10K_0402_5%
CK_REQ_PEG1_N
CK_REQ_SSD2_N
CK_REQ_LAN_N
CK_REQ_CR_N
CK_REQ_WLAN_N
CK_REQ_SSD1_N
CK_REQ_TBT_N
CK_CPU_24M_P6
CK_CPU_24M_N6
CK_CPU_BCLK_P6
CK_CPU_BCLK_N6
+VCCF24_1P0_L
CK_REQ_PEG1_N51
CK_REQ_WLAN_N41
CK_REQ_CR_N48
CK_REQ_SSD2_N42
CK_REQ_LAN_N27
CK_REQ_TBT_N36
CK_REQ_SSD1_N42
12
R189 2.7K_0402_0.5%
PCH_XTAL24_OUT
PCH_XTAL24_IN
PCH_RTC_X1
PCH_RTC_X2
XCLK_BIASREF
U2G
AR17
GPP_A16/CLKOUT_48
G1
CLKOUT_CPUNSSC_P
F1
CLKOUT_CPUNSSC
G2
CLKOUT_CPUBCLK_P
H2
CLKOUT_CPUBCLK
A5
XTAL24_OUT
A6
XTAL24_IN
E1
XCLK_BIASREF
BC9
RTCX1
BD10
RTCX2
BC24
GPP_B5/SRCCLKREQ0#
AW24
GPP_B6/SRCCLKREQ1#
AT24
GPP_B7/SRCCLKREQ2#
BD25
GPP_B8/SRCCLKREQ3#
BB24
GPP_B9/SRCCLKREQ4#
BE25
GPP_B10/SRCCLKREQ5#
AT33
GPP_H0/SRCCLKREQ6#
AR31
GPP_H1/SRCCLKREQ7#
BD32
GPP_H2/SRCCLKREQ8#
BC32
GPP_H3/SRCCLKREQ9#
BB31
GPP_H4/SRCCLKREQ10#
BC33
GPP_H5/SRCCLKREQ11#
BA33
GPP_H6/SRCCLKREQ12#
AW33
GPP_H7/SRCCLKREQ13#
BB33
GPP_H8/SRCCLKREQ14#
BD33
GPP_H9/SRCCLKREQ15#
R13
CLKOUT_PCIE_N15
R11
CLKOUT_PCIE_P15
P1
CLKOUT_PCIE_N14
R2
CLKOUT_PCIE_P14
W7
CLKOUT_PCIE_N13
Y5
CLKOUT_PCIE_P13
U2
CLKOUT_PCIE_N12
U3
CLKOUT_PCIE_P12
SPT_PCH_H
REV = 1.3
SPT-H_PCH
?
CLKOUT_CPUPCIBCLK
CLKOUT_CPUPCIBCLK_P
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_PCIE_N6
CLKOUT_PCIE_P6
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
CLKOUT_PCIE_N8
CLKOUT_PCIE_P8
CLKOUT_PCIE_N9
CLKOUT_PCIE_P9
CLKOUT_PCIE_N10
CLKOUT_PCIE_P10
CLKOUT_PCIE_N11
CLKOUT_PCIE_P11
7 OF 12
?
L1
L2
J1
J2
N7
N8
L7
L5
D3
F2
E5
G4
D5
E6
D8
D7
R8
R7
U5
U7
W10
W11
N3
N2
P3
P2
R3
R4
CK_XDP_N
50
CK_XDP_P
50
CK_CPU_PCIBCLK_N
CK_CPU_PCIBCLK_P
CK_PEG1_N
CK_PEG1_P
CK_WLAN_N
CK_WLAN_P
CK_CR_N
48
CK_CR_P
48
CK_PCIE_SSD2_N
CK_PCIE_SSD2_P
CK_LAN_N
CK_LAN_P
CK_TBT_N
CK_TBT_P
CK_PCIE_SSD1_N
CK_PCIE_SSD1_P 42
27
27
36
36
6
6
51
51
41
41
42
42
42
dGPU
WLAN
Card Reader
PCIE SSD2
LAN
TBT
PCIE SSD1
B B
BRD Note:
Z0=50 ohm +-15%;Ground reference;Max via:2
Group spacing:15mils;Isolation spacing:20mils
Segment Length:100mils;Total length:1000mils;Length match:100mils
：
CAD Note
Max crystal ESR 50K ohm
C205
10P_0402_50V8J
C208
10P_0402_50V8J
A A
5
12
Y1
32.768KHZ_9PF_CM8V-T1A
4
PCH_RTC_X1
R192
10M_0402_5%
1 2
PCH_RTC_X2
3
VSS shield recommened;S:W:S=6:4:6
12
R190 1M_0402_5%
Y2
1423
1
C206
10P_0402_50V8J
2
24MHZ_8PF_EXS00A-CS07257
2
PCH_XTAL24_OUTPCH_XTAL24_IN
1
C207
10P_0402_50V8J
2
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
22
22
22
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
of
Title
Title
Title
PCH-CLOCK
PCH-CLOCK
PCH-CLOCK
Document Number
Size Document Number
Size Document Number
Size
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
D D
CPU_DPB_HPD34
CPU_DPC_HPD35
CPU_DPD_HPD32
CPU_EDP_HPD30
C C
4
Hi Active
Hi Active
Hi Active
Hi Active
AW4
GPP_I0/DDPB_HPD0
AY2
GPP_I1/DDPC_HPD1
AV4
GPP_I2/DDPD_HPD2
BA4
GPP_I3/DDPE_HPD3
BD7
GPP_I4/EDP_HPD
SPT_PCH_H
REV = 1.3
3
U2E
SPT-H_PCH
?
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
5 OF 12
?
GPP_F14
GPP_F23
GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23
BB3
CPU_DPC_CTRL_CLK CPU_DPB_CTRL_CLK
BD6
CPU_DPC_CTRL_DATA
BA5
CPU_DPB_CTRL_CLK
BC4
CPU_DPB_CTRL_DATA
BE5
CPU_DPD_CTRL_CLK
BE6
CPU_DPD_CTRL_DATA
Y44
V44
W39
L43
L44
U35
R35
BD36
2
CPU_DPB_CTRL_CLK
CPU_DPB_CTRL_DATA
CPU_DPD_CTRL_CLK
CPU_DPD_CTRL_DATA
DGPU_HOLD_RST_N
DGPU_PWR_EN
GPU_ALL_PGOOD
TBT_CIO_PLUG_EVENT_N
TBT_USB_PWR_EN
TBT_FORCE_PWR
TBT_CIO_PWR_EN
71,80
71
36,38
1
CAD Note：DP*_CTRL_DATA(Internal 20K PD)
NC:Disable DP Port
CPU_DPC_CTRL_CLK
CPU_DPC_CTRL_DATA
34
34
32
32
59
36
36
36
CPU_DPB_CTRL_DATA
CPU_DPD_CTRL_CLK
CPU_DPD_CTRL_DATA
DGPU_PWR_EN
DGPU_HOLD_RST_N
GPU_ALL_PGOOD
R194 2.2K_0402_5%@
R196 2.2K_0402_5%@
R198 2.2K_0402_5%@
R199 2.2K_0402_5%@
R860 2.2K_0402_5%@
R861 2.2K_0402_5%@
R108 10K_0402_5%
1 2
R110 10K_0402_5%
1 2
R113 10K_0402_5%@
+3V
12
12
+3V
12
12
+3V
12
12
+3V
12
B B
A A
5
4
BD45
BD44
BE44
BD2
D45
A42
B45
B44
A4
A3
B2
A2
B1
BB1
BC1
A44
C1
D1
U2J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
RSVD
SPT_PCH_H
REV = 1.3
SPT-H_PCH
?
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PREQ#
PRDY#
CPU_TRST#
PCH_TRIGOUT
PCH_TRIGIN
10 OF 12
?
AR22
W13
U13
P31
N31
P27
R27
N29
P29
AN29
R24
P24
AT3
PCH_XDP_PREQ_N
AT4
PCH_XDP_PRDY_N
AY5
PCH_TRST_N
AL2
PCH_2_CPU_TRIGGER_R
AK1
CPU_2_PCH_TRIGGER
3
R203 33_0402_5%
12
PCH_XDP_PREQ_N
PCH_XDP_PRDY_N
PCH_TRST_N
PCH_2_CPU_TRIGGER 6
CPU_2_PCH_TRIGGER
2
50
50
50
CAD Note:
CRB use 30R;DG use 0R
6
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
23
23
23
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
PCH-DISPLAY/RSVD
PCH-DISPLAY/RSVD
PCH-DISPLAY/RSVD
Size Document Number
Size Document Number
Size Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
1
+1.0VALW
+1.0VALW +1.0VALW_PCH
D D
+1.0VALW
R205 0_0402_5%@
+1.0VALW_PCH
R207 0_0402_5%
R209 0_0402_5%
R212 0_0402_5%
R214 0_0603_5%
CAD Note:
May change to 2.2UH inductor
C C
B B
A A
and 2*22UF caps filter
+1.0VALW_PCH
R305 0_0603_5%
3.53A
+VCCMPHY_1P0 +VCCAMPHYPLL_1P0
R234 0_0603_5%
+1.0VALW_PCH
R223 0_0603_5%
BRD Note:
Placed 1~3mm within PCH package edge
+1.0VALW_PCH
1 2
+V3.3A_VCCPGPPEF +V3.3A_VCCPGPPG +VCCPHVC_3P3
1 2
@
2
PJ16 JUMP_43X118
112
@
PJ17
12
12
12
12
12
1 2
1 2
1 2
C545
47U
_0805_6.3V6-M
C223
@
0.1U_0402_25V6
1
C213
@
2
1
C217
@
2
1
C210
2
+3VALW_PCH +1.8VALW_PCH
C546
47U
1 2
_0805_6.3V6-M
C224
@
0.1U_0402_25V6
1 2
5
22U
_0603_6.3V6M
22U
_0603_6.3V6M
22U
_0603_6.3V6M
1
C214
@
22U
2
_0603_6.3V6M
1
C319
@
22U
2
_0603_6.3V6M
1
C211
22U
2
_0603_6.3V6M
+VCCPRIM_1P0
+VCCDSW_1P0
+VCC19P2_1P0
+VCCF135_1P0
+VCCF100OC_1P0
+VCCF100_1P0
1
C215
@
1U
_0402_10V6K
2
1
C316
1U
_0402_10V6K
2
C547
@
47U
1 2
_0805_6.3V6-M
2.899A
0.0454A
0.0348A
0.0237A
0.0327A
0.205A
12
R224 0_0402_5%
12
R226 0_0402_5%
+VCCDSW_1P0
1
C212
1U_0402_10V6K
2
+V3.3S_VCCATS
C225
@
0.1U_0402_25V6
1 2
1
C399
1U
_0402_10V6K
2
+VCCMPHY_1P0
1
C216
2
1
C222
1U_0402_10V6K
2
+VCC19P2_1P0
+VCCF135_1P0
+VCCF100OC_1P0
+VCCF100_1P0
+VCCF24_1P0_L
+VCCMPHY_1P0
+VCCAMPHYPLL_1P0
+VCCAPLLEBB_1P0
+VCCDUSB_1P0
+VCCAUSB_1P0_L
+VCCAAZPLL_1P0_L
+V3.3A_VCCPAZIO
+VCCPUSBDSW_3P3
+VCCF24_1P0_L
0.006
0.08A
+VCCAUSB_1P0_L
0.013A
+VCCAAZPLL_1P0_L
0.008A
2
C398
0.1U
1
_0402_25V6
1
C314
1U
22U
_0402_10V6K
2
_0603_6.3V6M
+VCCPRTCPRIM_3P3
1
2
+VCCDUSB_1P0
C226
1U
_0402_10V6K
1 2
4
+VCCDSW_1P0
+VCCMPHY_1P0
+1.0VALW_PCH
+3VALW_PCH
1
C219
1U_0402_10V6K
2
C227
0.1U
_0402_25V6
+VCCPRIM_1P0
NO CAP
AA23
AA26
AA28
AC23
AC26
AC28
AE23
AE26
Y23
Y25
BA29
NO CAP
N17
NO CAP
R19
NO CAP
U20
NO CAP
V17
R17
K2
K3
U21
U23
U25
U26
V26
A43
B43
C44
C45
NO CAP
V28
AC17
AJ5
AL5
NO CAP
AN19
BA15
W15
12
R218 0_0402_5%
1 2
R221 0_0603_5%
1 2
R229 0_0603_5%
12
R227 0_0402_5%
+VCCPUSBDSW_3P3 +V3.3A_VCCPGPPBCH
1
C220
1U_0402_10V6K
2
+VCCPRTC_3P3
1
C229
C228
0.1U
1U
_0402_10V6K
1 2
2
_0402_25V6
U2H
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
DCPDSW_1P0
VCCCLK1
VCCCLK3
VCCCLK4
VCCCLK2
VCCCLK2
VCCCLK5
VCCCLK5
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHYPLL_1P0
VCCMPHYPLL_1P0
VCCPCIE3PLL_1P0
VCCPCIE3PLL_1P0
VCCAPLLEBB_1P0
VCCPRIM_1P0
VCCUSB2PLL_1P0
VCCUSB2PLL_1P0
VCCHDAPLL_1P0
VCCHDA
VCCDSW_3P3
SPT_PCH_H
REV = 1.3
+VCCAPLLEBB_1P0
+VCCDUSB_1P0
2
1
C221
@
0.1U_0402_25V6
1 2
SPT-H_PCH
0.09A
0.533A
+VCCPUSBDSW_3P3
0.233A
+V3.3A_VCCPAZIO
0.075A
2
C400
C405
4.7U
0.1U_0402_25V6
_0402_6.3V6M
1
?
CORE
V
CCGPIO
VCCRTCPRIM_3P3
MPHY
USB
VCCPRIM_1P0
VCCDSW_3P3
VCCPGPPA
VCCPGPPBCH
VCCPGPPBCH
VCCPGPPEF
VCCPGPPEF
VCCPGPPG
VCCPRIM_3P3
VCCPRIM_1P0
VCCATS
VCCRTC
DCPRTC
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCSPI
VCCSPI
VCCSPI
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
8 OF 12
?
AL22
BA24
BA31
BC42
BD40
AJ41
AL41
AD41
AN5
AD15
AD13
BA20
BA22
BA26
AJ20
AJ21
AJ23
AJ25
BE41
BE43
BE42
BC44
BA45
BC45
BB45
BD3
BE3
BE4
NO CAP
NO CAP
VCC_RTCEXT_CAP
NO CAP
NO CAP
NO CAP
+VCCFHV_2P8
+VCCPDSW_3P3
+V3.3A_1.8A_VCCPGPPA
+V3.3A_VCCPGPPBCH
+V3.3A_VCCPGPPEF
+V3.3A_VCCPGPPG
+VCCPHVC_3P3
+VCCDTS_1P0
+V3.3S_VCCATS
+VCCPRTCPRIM_3P3
+VCCPRTC_3P3
+VCCPRIM_1P0
+V3.3A_VCCPSPI
+V3.3A_VCCPGPPD
+VCCPFUSE_3P3
PCH POWER RAIL TABLE
POWER RAIL
+VCCPRIM_1P0
+VCC19P2_1P0 0.021
+VCCF100_1P0
+VCCF135_1P0 1.0 0.051
+VCCAMPHYPLL_1P0 0.081.0
+VCCAUSB_1P0_L 1.0 0.013
+V3.3A_VCCPGPPA 3.3 0.084
+V3.3A_VCCPGPPBCH 3.3 0.259
+V3.3A_VCCPGPPD 3.3 0.101
+V3.3A_VCCPGPPEF 3.3 0.134
+V3.3A_VCCPGPPG 3.3 0.125
+V3.3A_VCCPSPI 3.3 0.012
+V3.3S_VCCATS 3.3 0.007
+V3.3A_V1.8A_VCCPAZIO3.3 0.06
+VCCPFUSE_3P3 3.3 0.3
+VCCPUSBDSW_3P3 3.3 0.233
+VCCPRTCPRIM_3P3 3.3 0.001
+VCCPRTC_3P3 3.3 0.001
3
LEVEL
(v)
1.0 2.899
1.0
1.0 0.138
1.0
C209
0.1U_0402_25V6
1 2
IccMAX
current
(A)
0.024+VCCF100OC_1P0
3.53+VCCMPHY_1P0 1.0
0.008+VCCAAZPLL_1P0_L 1.0
2
EDS
+3VALW_PCH +3VALW
+VCCFHV_2P8
0.0908A
0.403A
+V3.3A_1.8A_VCCPGPPA
0.0879A
+V3.3A_VCCPGPPBCH
0.27262A
+V3.3A_VCCPGPPEF
0.14107A
+V3.3A_VCCPGPPG
0.1318A
0.2875A
+VCCDTS_1P0
0.0061A
+V3.3S_VCCATS
0.0066A
0.0002A
+VCCPRTC_3P3
0.0002A
0.0121A
+V3.3A_VCCPGPPD
0.0395A
+VCCPFUSE_3P3
0.0811A
Title
Title
Title
Size Document Number
Size Document Number
Size
Document Number
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
R204 0_0402_5%
R206 0_0603_5%
R208 0_0603_5%
R290 0_0603_5%@
R210 0_0603_5%
R211 0_0603_5%
R213 0_0603_5%
R217 0_0402_5%
R219 0_0402_5%
R222 0_0402_5%
R225 0_0402_5%
R228 0_0402_5%
R230 0_0603_5%
R231 0_0603_5%
PCH-POWER
PCH-POWER
PCH-POWER
Skylake-H
Skylake-H
Skylake-H
@
PJ18
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R215 0_0603_5%
12
12
12
12
12
1 2
1 2
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
1
+3VALW_PCH+VCCPDSW_3P3
+3VALW_PCH
+1.8VALW_PCH
+3VALW_PCH
+3VALW_PCH+VCCPHVC_3P3
+3VALW_PCH+VCCPRTCPRIM_3P3
+3VALW_PCH+V3.3A_VCCPSPI
24
24
24
+1.0VALW_PCH
+1.0VALW_PCH
+3V
+VCC_RTC
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
5
D D
4
3
2
1
U2I
SPT-H_PCH
AC18
VSS
AN4
VSS
AN10
VSS
BE14
VSS
BE18
VSS
BE23
VSS
BE28
VSS
BE32
VSS
BE37
VSS
BE40
VSS
BE9
VSS
C10
VSS
C2
VSS
C28
VSS
C37
VSS
J7
VSS
K10
VSS
K27
VSS
K33
VSS
K36
VSS
K4
VSS
K42
VSS
K43
VSS
L12
VSS
L13
VSS
L15
VSS
L4
VSS
AA17
AA18
AA20
AA21
AA25
AA29
AA42
AB10
L41
L8
M35
M42
N10
N15
N19
N22
N24
N35
N36
N4
N41
N5
P17
P19
P22
P45
R10
R14
R22
R29
R33
R38
R5
T1
T2
T4
Y18
Y20
Y21
Y26
Y28
Y29
A18
A25
A32
A37
AA4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
REV = 1.3
C C
B B
?
AR5
VSS
AR7
VSS
U15
VSS
AL4
VSS
AE29
VSS
AE4
VSS
AE42
VSS
AF18
VSS
AF20
VSS
AF21
VSS
AF23
VSS
AF25
VSS
AF26
VSS
AF28
VSS
AF29
VSS
AG11
VSS
AG13
VSS
AG31
VSS
AG32
VSS
AG33
VSS
AG38
VSS
AG4
VSS
AH1
VSS
AH17
VSS
AH18
VSS
AH20
VSS
AH21
VSS
AH23
VSS
AH25
VSS
AH26
VSS
AH28
VSS
AH29
VSS
AH45
VSS
AJ10
VSS
AJ14
VSS
AJ15
VSS
AJ17
VSS
AJ18
VSS
AJ26
VSS
AJ28
VSS
AJ29
VSS
AJ31
VSS
AJ32
VSS
AJ36
VSS
AK4
VSS
AK42
VSS
AU7
VSS
AV17
VSS
AV24
VSS
AV27
VSS
AV31
VSS
AV33
VSS
AV6
VSS
AW13
VSS
AW19
VSS
AW29
VSS
AW37
VSS
AW9
VSS
AY38
VSS
AY45
VSS
B25
VSS
B3
VSS
B37
VSS
B40
VSS
B6
VSS
BA1
VSS
BB11
VSS
BB16
VSS
BB21
VSS
BB25
VSS
BB30
VSS
BB34
VSS
BC2
VSS
BD43
VSS
9 OF 12
?
C42
D10
D12
D15
D16
D17
D19
D21
D24
D25
D27
D29
D30
D31
D33
D35
D36
E13
E15
E31
E33
F44
G42
H17
H19
H22
H24
H27
H29
H35
J10
J11
J39
T42
U10
U11
U14
U17
U18
U28
U29
U31
U32
U33
U38
V18
V20
V21
V23
V25
V29
V45
W14
W31
W32
W33
W38
W4
W8
Y17
F8
G9
H3
J3
J5
U4
U8
V3
SPT-H_PCH
U2L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
REV = 1.3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12 OF 12
?
AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4
?
A A
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
25
25
25
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
PCH-VSS
PCH-VSS
PCH-VSS
Size Document Number
Size Document Number
Size
Document Number
C
C
C
Skylake-H
Skylake-H
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
4
3
2
5
BRD Note:
+3VLP_EC and RTCVCC trace width 12mils
0.1u placed close to each VCC-GND pair
+3VLP
1 2
L1
BLM15BD221SN1D_2P
+3VALW
D D
@
1 2
L2
BLM15BD221SN1D_2P
+3VLP_EC
1
C230
10U_0402_6.3V
2
6M
2
C231
0.1U_0402_25V
1
6
2
C232
0.1U_0402_25V
1
6
2
C233
0.1U_0402_25V
1
6
2
C234
0.1U_0402_25V
1
6
2
C235
0.1U_0402_25V
1
6
2
C236
0.1U_0402_25V
1
6
2
1
C237
0.1U_0402_25V
6
4
+3VLP_EC
R232 0_0402_5%
1 2
+VSTBY0_EC
C238
2.2U_0402_6.3V
6M
2
C239
0.1U_0402_25V
1
6
+3V
1 2
R233 0_0402_5%
+1.8V
1 2
R291 0_0402_5%@
CAD Note
：
IT8376 Reserve
For eSPI bus 1.8V
3
2
C242
0.1U_0402_25V6
1
+3VALW
R297 0_0402_5%
1 2
+3VALW_EC_FSPI
2
1
C308
0.1U_0402_25V6
+3V_1.8V_EC
2
+VBAT_EC
1 2
R235
0_0402_5%
+3VLP_EC
1 2
L3
BLM15BD221SN1D_2P
+3VLP_EC_AVCC
2
C241
0.1U_0402_25V6
1
EC_AGND
1
SM BUS
GPIO
0
E1
EC_AGND
+VBAT_EC
J4
E9
C
AVC
PS2
FAN
3
+VSTBY0_EC+3V_1.8V_EC
A1
VBAT
Vstby0
SMCLK0/GPF2
SMDAT0/GPF3
SMCLK1/GPC1
CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1
CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2
L80HLAT/BAO/WUI24/SMCLK4/GPE0
SMDAT1/GPC2
L80LLAT/WUI7/SMDAT4/GPE7
PWM4/SMCLK5/GPA4
PWM5/SMDAT5/GPA5
PS2CLK0/TMB0/CEC/GPF0
PS2DAT0/TMB1/GPF1
TACH0A/GPD6
TACH1A/TMA1/GPD7
PWM2/GPA2
PWM3/GPA3
PWM0/GPA0
PWM1/GPA1
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7
CTX0/TMA0/GPB2
XLP_OUT/GPB4
CRX0/GPC0
TMRI0/WUI2/GPC4
TMRI1/WUI3/GPC6
RI1#/WUI0/GPD0
RI2#/WUI1/GPD1
GINT/CTS0#/GPD5
EGAD/WUI25/GPE1
EGCS#/WUI26/GPE2
EGCLK/WUI27/GPE3
RTS1#/WUI5/GPE5
PS2CLK2/WUI20/SMINT10/GPF4
PS2DAT2/WUI21/SMINT11/GPF5
PECIRQT#/WUI23/SMDAT2/GPF7
SSCE1#/GPG0
DTR1#/SBUSY/GPG1/ID7
SSCE0#/GPG2
DSR0#/GPG6
CLKRUN#/WUI16/GPH0/ID0
WUI19/GPH3/ID3/YM
GPH4/ID4/YP
GPH5/ID5/DM
GPH6/ID6/DP
IT8376VG-128/CX
J1
1 2
JUMPER
EC_AGND
GPE4
A10
B10
B3
B2
E8
D7
N2
M3
K6
J6
A11
B11
M11
M12
M6
N6
5VT 16mA
M5
5VT 16mA
N5
5VT 16mA
M7
5VT 16mA
K7
D2
A2
D1
C2
E1
N1
N3
N7
EC_ON_R
A13
A12
B12
E2
N8
D9
B9
ALL_SYS_PWRGD
C1
PM_PCH_PWROK_R
E6
A5
NOVO_BTN_N_R
E7
EC_TEST1
D6
SYS_PWROK_R
D8
A9
B8
A8
USB_STATUS_N_R
B7
1 2
R256 0_0402_5%
1 2
R257 0_0402_5%
1 2
R260 0_0402_5%
1 2
R262 0_0402_5%
1 2
R265 0_0402_5%
1 2
R263 0_0402_5%
1 2
R539 0_0402_5%@
1 2
R527 0_0402_5%@
1 2
R540 0_0402_5%
EC_SMB_CLK0
EC_SMB_DAT0
EC_SMB_CLK1
EC_SMB_DAT1
EC_I2C_CLK3
EC_I2C_DATA3 46,90
PCH_I2C_CLK2
PCH_I2C_DATA2
EC_I2C_CLK5
EC_I2C_DATA5
TP_PS2_CLK 45
TP_PS2_DAT
EC_FAN_TACH1
EC_FAN_TACH2
EC_FAN_PWM1
EC_FAN_PWM2
48
PWR_LED_W
BATT_LOW_LED_A
AC_CHARGED_LED_W
AC_CHARGING_LED_A
EC_THERM_ALERT_N
USB_CHG_EN
USB_CHG_CLT1 39
USB_CHG_CLT3
PWR_LEVEL
59
PM_RSMRST_N 19
EC_ON
75,77,92
19,76
SLP_S4_N
SLP_S3_N
19,36
AR_HOLD_RST_N
SUSON
39,47,48,76,90,92
VDDQ_PWRGD
MAINON
49,78,90,91,92
CPU_VR_PWRGD
PM_PCH_PWROK 19
CODEC_PD_N
48
SYS_PWROK
19
BIOS_ONEKEY_N
VRAM_VDDQ_ADJ
ALL_SYS_PWRGD_PMIC
49
CPU_VR_ON
USB_CHG_STATUS_N
27
LAN_WAKE_N
2
39
28,29
76
45
44
44
44
44
39
38,50,73,74
38,50,73,74
19,44,59
19,44,59
46,90
17
28,31,44
28,31,44
48
38
83,86
47
59,79
39
17
45
45
45
49,83,86
BATT/CHARGER/TI
PCH/TS/dGPU/MXM
LC/Switch
PCH
AMP/SENSOR
TOUCH PAD
EC_SMB_CLK0
EC_SMB_DAT0
EC_I2C_CLK3
EC_I2C_DATA3
EC_I2C_CLK5
EC_I2C_DATA5
CAD Note:
I2C polling mode default
TP_PS2_CLK
TP_PS2_DAT
ACOK
CHG_PROCHOT_N_R
NOVO_BTN_N
NBSWON_N
SUSON
MAINON
EC_ON
BIOS_ONEKEY_N
USB_STATUS_N_R
EC_FAN_TACH1
EC_FAN_TACH2
PWR_LEVEL
EC_INT_N
EC_THERM_ALERT_N
EC_KSO16
EC_KSO17
CAD Note
GPG0,GPG2,GPG6 reserved for
Hardware strapping
EC_TEST1
ACOK_R
ALL_SYS_PWRGD
CK_LPC/ESPI_CLK
R264
Title
Title
Title
Size Document Number
Size Document Number
Size
Document Number
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
12
R236 2.2K_0402_5%
12
R243 2.2K_0402_5%
12
R563 2.2K_0402_5%
12
R564 2.2K_0402_5%
12
R238 2.2K_0402_5%
12
R244 2.2K_0402_5%
1 2
R241 4.7K_0402_5%
1 2
R242 4.7K_0402_5%
12
R245 100K_0402_5%
12
R247 100K_0402_5%
12
R249 100K_0402_5%
12
R250 100K_0402_5%
12
R258 100K_0402_5%@
12
R299 100K_0402_5%@
12
R251 100K_0402_5%
12
R268 100K_0402_5%
12
R379 100K_0402_5%
12
R253 100K_0402_5%
12
R254 100K_0402_5%
1 2
R255 10K_0402_5%@
12
R566 100K_0402_5%
1 2
R337 10K_0402_5%@
12
R267 100K_0402_5%@
12
R324 100K_0402_5%@
：
1 2
R259 10K_0402_5%
@
1 2
C71 100P_0402_50V8J
12
C246 0.1U_0402_25V6
12
C247
EC IT8376VG
EC IT8376VG
EC IT8376VG
Skylake-H
Skylake-H
Skylake-H
1
10P_0402_50V8J
33_0402_5%
+3VLP_EC
+3VLP_EC
+3VLP_EC
+3V
+3VLP_EC
+3V
+3VLP_EC
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
26
26
26
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
of
D4
Lenov
VSS
H5
+3VLP_EC_AVCC+3VLP_EC
D10
E4
K10
BY
BY
BY
BY
VST
VST
VSTBYK4VST
VST
o
VSSE5VSSF4VSSG5VSSG4AVSS
VSS
F5
+3VALW_EC_FSPI
U5
J5
D5
C
VC
BY_FSPI
VST
LPC
IT8376VG
FSPI
KB MX
GPIO
CLOCK
ORE
VC
K5
1
C310
0.1U_0402_25V
2
6
EC_WRST_N
EC_PECI
ACOK_R
EC_SCK
EC_CS_N
EC_SI
EC_SO
EC_KSO16
EC_KSO17
AC_PRESENT_R
LC_INT1_N_R
EC_INT_N_R
EC_CK32K/GPJ6
R261
@
10K_0402_5%
1 2
CAD Note:
IT8371 Stuff
K1
EIO0/LAD0/GPM0
J2
EIO1/LAD1/GPM1
J1
EIO2/LAD2/GPM2
H2
EIO3/LAD3/GPM3
H1
ECS#/LFRAME#/GPM5
K2
ESCK/LPCCLK/GPM4
M4
ERST#/LPCRST#/WUI4/GPD2
G2
ALERT#/SERIRQ/GPM6
F1
GA20/GPB5
M1
LPCPD#/WUI6/GPE6
L2
ECSMI#/GPD4
N4
ECSCI#/GPD3
H4
KBRST#/GPB6
M2
RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/WUI38/GPC7
B4
PWRSW#/GPB3
L1
WRST#
B1
PECI/WUI22/SMCLK2/GPF6
A3
LID_SW#/GPB1
A4
AC_IN#/GPB0
B5
FSCK/GPG7
A7
FSCE#/GPG3
B6
FMOSI/GPG4
A6
FMISO/GPG5
J12
KSI0/STB#
J13
KSI1/AFD#
J9
KSI2/INIT#
H12
KSI3/SLIN#
H9
KSI4
H10
KSI5
H13
KSI6
G9
KSI7
M8
KSO0/PD0
J7
KSO1/PD1
N9
KSO2/PD2
M9
KSO3/PD3
K8
KSO4/PD4
J8
KSO5/PD5
N10
KSO6/PD6
M10
KSO7/PD7
N11
KSO8/ACK#
K9
KSO9/BUSY
N12
KSO10/PE
N13
KSO11/ERR#
M13
KSO12/SLCT
L12
KSO13
L13
KSO14
K12
KSO15
K13
KSO16/SMOSI/GPC3
J10
KSO17/SMISO/GPC5
C12
DAC5/RIG0#/GPJ5
B13
DAC4/DCD0#/GPJ4
C13
DAC3/TACH1B/SMINT7/GPJ3
D12
DAC2/TACH0B/SMINT6/GPJ2
D13
SMINT5/GPJ1
E12
TACH2/SMINT4/GPJ0
E13
ADC7/CTS1#/WUI31/GPI7
F12
ADC6/DSR1#/WUI30/GPI6
F10
ADC5/DCD1#/WUI29/GPI5
F13
ADC4/WUI28/SMINT3/GPI4
F9
ADC3/SMINT2/GPI3
G12
ADC2/SMINT1/GPI2
G13
ADC1/SMINT0/GPI1
G10
ADC0/GPI0
G1
VCORE2(CK32KE)
F2
GPJ6(CK32K)
LPC_AD0_ESPI_IO021
LPC_AD1_ESPI_IO121
LPC_AD2_ESPI_IO221
LPC_AD3_ESPI_IO321
LPC_FRAME_N_ESPI_CS_N21
CK_LPC/ESPI_CLK21
PLT_RST_N17,27,36,38,41,42,48,49,59
SERIRQ21
H_A20GATE21
2
C245
@
47P_0402_25V8J
1
EC_SCK
EC_SO
EC_SI
EC_CS_N
EC_PECI
LPC_PD_N_ESPI_RST_N21
PCH_PWRBTN_N19,50
NBSWON_N48,50
MXLID_N31
C C
+3VLP_EC
H_PECI6,20
PCH_SCK_R17
PCH_SO_R17
PCH_SI_R17
PCH_CS0_N17
B B
Note 1 : Since all GPIO belong to VSTBY power domain, and
there are some special considerations below:
(1) If it is output to external VCC derived power domain
circuit, this signal should be isolated by a diode such as
A A
KBRST# and GA20.
(2) If it is input from external VCC derived power domain
circuit, this external circuit must consider not to float
the GPIO input.
Note 2 :
(1) Each input pin should be driven or pulled.
：
EC_WRST_N
CAD Note
Trstpw=50ms;Twrstw=10us
1 2
R246 100K_0402_5%
R252 33_0402_5%
4 5
3 6
2 7
1 8
CAD Note:
Reserve TPC for SMBus flash
1
TP147
1
TP152
EC_WRST_N
1
C244
1U_0402_10V6K
2
12
RP4
0_0804_8P4R_5%
MX6
MX7
CAD Note:
ADC VIN range 0~3.0V
1 2
R237 0_0402_5%
1 2
R294 0_0402_5%
1 2
R239 0_0402_5%
1 2
R240 0_0402_5%
2 1
D1 SDM10U45LP-7_DFN1006-2-2
EC_SMI_N21
EC_SCI_N20
KBRST_N21
ACOK74
CHG_PROCHOT_N_R44,59,74
2 1
D4 SDM10U45LP-7_DFN1006-2-2
2 1
D2 SDM10U45LP-7_DFN1006-2-2
2 1
D3 SDM10U45LP-7_DFN1006-2-2
1 2
R248 0_0402_5%
MX050
MX150
MX250
MX350
MX450
MX550
MX650
MX750
MY050
MY150
MY250
MY350
MY450
MY550
MY650
MY750
MY850
MY950
MY1050
MY1150
MY1250
MY1350
MY1450
MY1550
1 2
LC_KSO1646
LC_KSO1746
AC_PRESENT19
VCOUT1_PROCHOT44
EC_ADP_ID_ON_N73
LC_INT1_N46
EC_INT_N17
VBL_INT_N90 NOVO_BTN_N
TURBO_GPIO149
PSYS74,83
BMON74
AMON74
ADAPTER_ID73
VCIN0_PT144
MBAT_PRES_N50,73,74
EC_CLEAR_CMOS19
TURBO_GPIO349
R578 0_0402_5%
1 2
R579 0_0402_5%
2 1
D5 SDM10U45LP-7_DFN1006-2-2
1 2
R308 0_0402_5%
1 2
R370 0_0402_5%
1 2
R777 0_0402_5%@
1 2
R546 0_0402_5%
1 2
R523 0_0402_5%
1 2
R526 0_0402_5%
CAD Note:
IT8371 NC
EC_VCORE2/CK32KE
1
C243
0.1U_0402_25V
2
6
EC_RST_N
SERIRQ_R
H_A20GATE_R
LPC_PD_N_R
EC_SMI_N_R
EC_SCI_N_R
KBRST_N_R
PCH_PWRBTN_N_R
MX6
MX7
(2) Each output-drain output pin should be pulled.
5
4
5
4
3
2
1
+3VALW
1 2
Q35A AO5804EL_SC89-6@
6 1
：
R281 1M_0402_5%@
D6
1
I/O1
2
GND
3
I/O2
AZC099-04S.R7G
D7
1
I/O1
2
GND
3
I/O2
AZC099-04S.R7G
12
12
2
R477
100K_0402_5%
1 2
PECLK
12
Y4
1423
25MHZ_8PF_EXS00A-CS07258
I/O3
VDD
I/O4
I/O3
VDD
I/O4
1
2
1
2
4
5
6
4
5
6
R271 0_0603_5%
12
12
C251
C250
10U
10U
_0603_10V
_0603_10V
D D
R273 0_0603_5%
+VDD33_LAN LAN_WAKE_N_R
C C
B B
A A
CK_REQ_LAN_N22,27
5
10P_0402_50V8J
MDI_P2 MDI_P3
MDI_N3 MDI_N2
R275 10K_0402_5%
3
Q35B
@
AO5804EL_SC89-6
4
CAD Note
Clock must be valid within 3ms
after the VDD33 reach 2.0V level
1
C276
2
5
2
C252
1U
_0402_10V6K
1
2
C268
1U
_0402_10V6K
1
LAN_CK_REQ_N
+VDD33_LAN
MDI_P1MDI_P0
MDI_N0MDI_N1
C253
0.1U
_0402_25V6
C269
0.1U
_0402_25V6
0.152A
+VDD33_LAN
2
C254
1000P_0402_50V7K
1
+AVDD33_LAN
2
C270
1000P_0402_50V7K
1
XTAL_LAN_OUTXTAL_LAN_IN
1
C277
10P_0402_50V8J
2
：
LX_LAN
CAD Note
SWR MODE DEFAULT
LAN_LX +AVDDL_LAN
BRD Note:
W=40mils;S=40mils;
Keep L2 within200mils;
Keep LAN_LX on internal layer of PCB
and GND coverd
CK_REQ_LAN_N22,27
PCIE_LAN_TX_C_DN18
PCIE_LAN_TX_C_DP18
PCIE_LAN_RX_DN18
PCIE_LAN_RX_DP18
1
2
C282
@
1U
_0402_10V6K
2
1
4
L4
1 2
4.7uH NRS4012T4R7MDGJ 1.5A
BRD Note:
Placed close
to Pin9
1 2
R272 0_0402_5%
2
1
C272
C271
0.1U
1U
_0402_10V6K
1
2
_0402_25V6
CAD Note
Keep low 100ms after the VDD33 valid
1 2
PLT_RST_N17,26,36,38,41,42,48,49,59
LAN_WAKE_N26
CK_LAN_N22
CK_LAN_P22
C283
@
1000P_0402_50V7K
R274 0_0402_5%
R276 0_0402_5%
R277 0_0402_5%
C274 0.1U_0402_16V7K
C275 0.1U_0402_16V7K
R278 0_0402_5%
R279 0_0402_5%
2
12
12
C285
C284
@
1000P_0402_50V7K
0.1U
1
_0402_25V6
1 2
1 2
1 2
1 2
1 2
1 2
C286
0.1U
_0402_25V6
：
PERSTn
2
12
C287
@
1000P_0402_50V7K
1
BRD Note:
Placed close
to L2
12
C255
10U
_0603_10V
BRD Note:
Placed close
to Pin22
2.7V
+AVDDH_LAN+AVDDHREG_LAN
2
C273
0.1U
1
_0402_25V6
PCIE_LAN_RX_C_DN
PCIE_LAN_RX_C_DP
2
12
C288
C289
@
0.1U
1000P_0402_50V7K
1
_0402_25V6
+DVDDL_LAN
2
2
C256
0.1U
1
1
_0402_25V6
LAN_RST_N
LAN_WAKE_N_R
LAN_CK_REQ_N
XTAL_LAN_IN
XTAL_LAN_OUT
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
C290
0.1U
_0402_25V6
1.1V
C257
1000P_0402_50V7K
2
3
4
36
35
29
30
32
33
8
7
38
39
23
BRD Note:
Placed close
to Pin37
BLM18KG601SN1_600 ohm 1.3A
1
2
C258
C259
1U_0402_10V6K
0.1U
2
1
_0402_25V6
_LAN
VDD33_LAN
AVDD33_LAN
+
+
+DVDDL
1
16
37
U6
DD33
V
VDD33
A
PERSTn
WAKEn
CLKREQn
RX_N
RX_P
TX_N
TX_P
REFCLK_N
REFCLK_P
XTLI
XTLO
LED[0]
LED[1]
LED[2]
TL1
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
TD4-12MX4-
GST5009-E LF
2nd:MHPC NS892407(SP05000680J)
3
L5
1 2
AVDDL_LAN
+
6
DDL_REG
DV
41
MCT1
MX1+
MCT2
MX2+
MCT3
MX3+
MCT4
MX4+
AVDDL_REG
GND
MX1-
MX2-
MX3-
+AVDDL_LAN
13
31
VDDL
A
AVDDL
BRD Note:
Placed close
to Pin6
LAN
LAN
LAN
+AVDDH_
+AVDDHREG_
+AVDDVCO_
9
19
22
34
VDDL
VDDH
A
A
VDDVCO
A
VDDH_REG
A
TRXP0
TRXN0
TRXP1
TRXN1
TRXP2
TRXN2
TRXP3
TRXN3
RBIAS
DEBUGMODE[0]
TESTMODE[0]
TESTMODE[1]
TESTMODE[2]
E2400-RIVL-RL_QFN40
24
MCT1_TL
23
MDO_P0
22
MDO_N0
21
20
MDO_P1
19
MDO_N1
18
17
MDO_P2
16
MDO_N2
15
14
MDO_P3
13
MDO_N3
1
C260
1U_0402_10V6K
2
LX
PPS
NC
2
C261
1
40
11
12
14
15
17
18
20
21
10
24
5
25
26
27
28
CHASSIS1_GND
BRD Note:
Placed close
to Pin13,19,31
2
2
C262
0.1U
_0402_25V6
LAN_RBIAS
LAN_PPS
R282 30K_0402_1%
C263
0.1U
0.1U
1
1
_0402_25V6
_0402_25V6
LAN_LX
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
1 2
R280 2.37K_0402_1%
1
TP90
1 2
12
R283
75_0805_5%
12
C291
1000P_1206_2KV7-K
2
C264
1
1
2
2
0.1U
_0402_25V6
DL1
1
PDT5061
2
1 2
BLM18KG601SN1_600 ohm 1.3A
+VDD33_LAN
BRD Note:
Placed close
L6
BRD Note：MDI*
Trace lengh between E-2011B and Transformer
be 1.5~10inch
BRD Note
Keep away from other signals 25mils;
placed on the other side is possible
CAD Note：PPS
1 Hz clock output for IEEE1588 timing sync
to Pin34
1
2
：
LAN_RBIAS
1
MDO_P0
2
MDO_N0
3
MDO_P1
4
MDO_P2
5
MDO_N2
6
MDO_N1
7
MDO_P3
8
MDO_N3
Title
Title
Title
Document Number
Size Document Number
Size Document Number
Size
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
+AVDDVCO_LAN
2
1
C265
@
4.7U
_0402_6.3V6M
JRJ1
Foxconn_JM3611-RS800003-7H
C267
C266
@
0.1U
1U
1
2
_0402_25V6
_0402_10V6K
PR1+
PR1PR2+
PR3+
PR3PR2PR4+
PR4-
1 2
C278 0.1U_0402_25V6
1 2
C279 0.1U_0402_25V6
1 2
C280 0.1U_0402_25V6
1 2
C281 0.1U_0402_25V6
LAN-E-E2400-RIVL
LAN-E-E2400-RIVL
LAN-E-E2400-RIVL
Skylake-H
Skylake-H
Skylake-H
1
GND
GND
CHASSIS1_GND
9
CHASSIS1_GND
10
CHASSIS1_GND
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
27
27
27
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
of
5
4
3
2
1
+5VD_AUD+5V
L7
1 2
BLM15PX121SN1D_2P
2
12
C292
C293
1
_0603_10V
D D
C C
B B
10U
0.1u_0402_16V7K
EC
PCH
CODEC_PD_N_R29
HP_JD48
MIC_JD48
HDA_SPKR19
EC_I2C_CLK526,31,44
EC_I2C_DATA526,31,44
PCH_I2C_CLK017
PCH_I2C_DATA017
HP_JD
R313 1K_0402_5%
POST_I2S_MCLK
POST_I2S_BCLK
POST_I2S_LRCLK
POST_I2S_OUT
POST_I2S_IN
2
12
C295
C294
1
_0603_10V
10U
0.1u_0402_16V7K
1 2
R319 0_0402_5%
1 2
R318 0_0402_5%
1 2
R321 0_0402_5%@
1 2
R320 0_0402_5%@
CODEC_PD_N_R
1 2
R311 200K_0402_1%
R312 100K_0402_1%
12
12
12
R314
1K_0402_5%
12
C333
J
22P_0402_50V8-
C330
1
C331
@
2
12
C334
J
22P_0402_50V8-
12
C296
10U
_0603_10V
+3VD_AUD
R310
100K_0402_1%
1 2
2
C332
@
1
12
0.1u_0402_16V7K
100P_0402_50V8J
12
12
C335
J
22P_0402_50V8-
BLM15PX121SN1D_2P
2
C297
0.1u_0402_16V7K
1
POST_I2C_CLK
POST_I2C_DATA
0.1u_0402_16V7K
C336
J
22P_0402_50V8-
L8
1 2
HDA_JD2MIC_JD
PC_BEEP
12
C337
J
22P_0402_50V8-
+5VA_AUD+5V
2
12
C298
C299
10U
0.1u_0402_16V7K
1
_0603_10V
AGND AGND AGND AGND
CODEC/AMP
+1.8V
1.8Vpowerrailshouldbesuppliedbylinearregulator,
notswitchingregulator.ifswitchingregulatoris
unavoidable,Plsmakesurethatswitchingfrequency
operatesatout‐band(Over20KHz).
+3VD_AUD
+3VD_AUD
CODEC_PD_N26,29
R284 0_0603_5%
CAD Note：HD_I2C SEL
Hi: HDA mode; POR strap
R289 100K_0402_5%
SPK_R+29
SPK_R-29
R292 10K_0402_5%
D8 SDM10U45LP-7_DFN1006-2-2
DMIC_CLK31
DMIC_DATA31
POST_I2S_MCLK29
POST_I2S_BCLK29
POST_I2S_LRCLK29
POST_I2S_OUT29
POST_I2S_IN29
POST_I2C_DATA29
POST_I2C_CLK29
HDA_BCLK19
HDA_SYNC19
HDA_RST_N19
HDA_SDIN19
HDA_SDOUT19
MIC1_VREF_R
R845 2.2K_0402_5%
MIC1_VREF_L
R846 2.2K_0402_5%
MIC1R_SLEEVE
MIC1L_RING2
+1.8VA_AUD
12
12
12
21
1 2
R293 22_0402_5%
1 2
R295 0_0402_5%
1 2
R296 22_0402_5%
1 2
R298 22_0402_5%
1 2
R301 22_0402_5%
1 2
R302 22_0402_5%
R307 33_0402_5%
1 2
1 2
2
C300
2.2U
1
_0402_6.3V6M
HDA_I2S_SEL
TP91
TP92
TP103
TP93
TP94
TP95
12
2
C328
1
_0402_6.3V6M
4.7U
2
C301
0.1u_0402_16V7K
1
1
1
1
1
1
1
2
C329
1
0.1u_0402_16V7K
SPK_R+
SPK_RSPK_L+
SPK_L-
CODEC_PD_N_R
DMIC_CLK_R
DMIC_DATA_R
SPDIF_OUT
HDA_I2S_SEL
HDA_JD1
HDA_JD2
HDA_SDIN_R
+1.2V
R285 0_0603_5%
+5VD_AUD
U7
51
47
SPK-OUT-LP
48
SPK-OUT-LN
49
SPK-OUT-RN
50
SPK-OUT-RP
52
EAPD+PD#/GPIO_11
53
DMIC-CLK1
54
DMIC-DATA1
55
I2S_MCLK
56
I2S_BCLK
1
I2S_LRCLK
2
GPIO_1/DMIC_CLK2
3
I2S_OUT
4
GPIO_2/DMIC DATA2
5
I2S_IN
6
HD-I2S SEL
8
GPI-JD1
9
GPI-JD2
11
I2C -SDA
12
I2C-SCL
13
MHDA BCLK
14
MHDA SYNC
15
MHDA RESET
O
16
MHDA SDATA In
I
17
MHDA SDATA OUT
18
LDO3-CAP
57
TPAD
MIC1R_SLEEVE
MIC1L_RING2
+3VD_AUD+3V +3VALW_AUD+3VALW
12
+3VD_AUD +3VALW_AUD
7
19
46
10
DD
VDD1
VDD2
DV
P
P
DVDD-IO
VD33STB
ALC3268-CG
48
48
2
2
C302
2.2U_0402_6.3V6M
1
1
Mic1-VREFO-R/AGPO-1
C303
0.1u_0402_16V7K
+5VA_AUD
45
VDD1
A
LDO1-CAP
MIC1-CAP
Line1-VREFO
Mic1-Vref_O-L
Mic1-R/Sleeve
Mic1-L/Ring2
Line1-L
Line1-R
HP_Out-R
HP_Out-L
CPVEE
CPVREF
CPVPP
CBN1
CBP1
CBP2
CBN2
CPVDD/AVDD2
PCBEEP
LDO2-CAP
VBG_OUT
AVSS1
AVSS2
43
+2.25V
EF
VR
R286 0_0603_5%
+4.5V
44
41
40
MIC2_VREF
39
MIC1_VREF_R
38
MIC1_VREF_L
37
MIC1R_SLEEVE
36
MIC1L_RING2
35
MIC2L
34
MIC2R
33
HP_OUTR
32
HP_OUTL
-1.8V
31
C315 2.2U_0402_6.3V6M
0V
30
+1.8V
29
C317 2.2U_0402_6.3V6M
28
C318 2.2U_0402_6.3V6M
27
26
25
24
23
+1.5V
22
+0.45V
21
2
42
20
1
AGND AGND AGND
12
2
C307
C306
2.2U
0.1u_0402_16V7K
1
_0402_6.3V6M
AGND AGND
1 2
10U_0402_6.3V6M
C309
1 2
C313
10U_0402_6.3V6M
1 2
1 2
1 2
1 2
C321 2.2U_0402_6.3V6M
PC_BEEP
1
2
C325
C324
@
2
C326
1
0.1u_0402_16V7K
C327
_0402_6.3V6M
4.7U
1
AGNDAGND
0.1u_0402_16V7K
2
2
2
C305
C304
0.1u_0402_16V7K
2.2U_0402_6.3V6M
1
1
AGND
AGND
HP_OUTR
HP_OUTL
AGND
AGND
AGND
+1.8VA_AUD
1
2
C323
C322
2
1
AGNDAGND
0.1u_0402_16V7K
_0402_6.3V6M
10U
1 2
J2 JUMPER@
1 2
J3 JUMPER@
1 2
R315 0_0402_5%
1 2
R316 0_0402_5%
1 2
R317 0_0402_5%
_0402_6.3V6M
10U
48
48
AGND
A A
HDA_BCLK
12
C339
@
22P_0402_50V8-J
5
DMIC_CLK
C338
10P_0402_50V8J
4
MIC2_VREF
MIC2L
MIC2R
2 1
D9
SDM10U45LP-7_DFN1006-2-2
D10
SDM10U45LP-7_DFN1006-2-2
C510
4.7U_0805_25V6K
C511
4.7U_0805_25V6K
2 1
1 2
1 2
R849
R850
R847 2.2K_0402_5%
R848 2.2K_0402_5%
1 2
1 2
1K_0402_5%
1K_0402_5%
3
LENOVO.CRDN
LENOVO.CRDN
1
LENOVO.CRDN
28
28
28
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
Title
Title
Title
CODEC-ALC3268
CODEC-ALC3268
CODEC-ALC3268
Size Document Number
Size Document Number
Size
Document Number
C
C
C
Skylake-H
Skylake-H
12
MIC2L_C
12
MIC2R_C
MIC2L_C
MIC2R_C
48
48
2
Skylake-H
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
5
CAD Note
：
POST_I2C*
connect to PCH default and reserve to EC
PU at PCH or EC side
D D
POST_I2C_DATA28
POST_I2C_CLK28
CAD Note
：
POST_I2S_MCLK
Use TAS5766M internal MCLK default
POST_I2S_IN28
POST_I2S_MCLK28
POST_I2S_BCLK28
POST_I2S_OUT28
POST_I2S_LRCLK28
C C
1 2
R322 22_0402_5%
1 2
C358 1U_0402_25V6K
1 2
C360 1U_0402_25V6K
1 2
C361 1U_0402_25V6K
12
C362 0.22U_0402_25V6K
12
C363 0.22U_0402_25V6K
12
C364 0.22U_0402_25V6K
12
C365 0.22U_0402_25V6K
+PVCC_AMP
U8
16
SDA
17
SCL
18
GPIO1
19
GPIO2
21
GPIO3
22
MCLK
23
BCLK
24
DIN
TAS5766M
25
LRCLK
28
LDOO
32
CAPP
34
CAPM
35
VNEG
36
DACL
37
INPL
38
INNL
11
INNR
12
INPR
13
DACR
6
7
C
PVC
41
42
43
C
C
C
C
PVC
AVC
PVC
PVC
4
+3VA_AMP +3VD_AMP
30
31
14
D
DD
PVDD
AVD
DV
C
+GVDD_AMP
+6.9V
8
DD
GV
BSPR
OUTPR
OUTNR
BSNR
BSNL
OUTNL
OUTPL
BSPL
XSMT/UVP
GAIN/FSW
FAULTZ
ADR1
ADR2
GND
GND
GND
GND
GND
GND
GND
TGND
1 2
C340 1U_0402_25V6K
5
4
2
1
48
47
45
44
27
9
40
26
20
3
10
15
29
33
39
46
49
12
C351 0.22U_0402_25V6K
12
C352 0.22U_0402_25V6K
12
C353 0.22U_0402_25V6K
12
C354 0.22U_0402_25V6K
AMP_PD_N_R
AMP_GAIN/FSW
AMP_SPK_R+
AMP_SPK_R-
AMP_SPK_LAMP_SPK_L+
AMP_PD_N_R
AMP_GAIN/FSW
3
BRD Note:
placed near to Pin6&7
and Pin41&42&43 seperately
B+
+3VD_AMP
+GVDD_AMP
+PVCC_AMP
@
PJ4
12
C341
@
10U_0805_25V6K
separate to two group and place need to Pin6&7 and Pin42&43;
R323
CAD Note
@
Low active to mute,
10K_0402_5%
1 2
12
12
Tr/Tf less than 20ns
@
2 1
D19 SDM10U45LP-7_DFN1006-2-2
1 2
R338 0_0402_5%
R325
75K_0402_1%
R328
47K_0402_5%
12
C342
@
10U
_0805_25V6K
AMP_SPK_R+
AMP_SPK_RAMP_SPK_L+
AMP_SPK_L-
：
AMP_PD_R_N
12
12
C343
C344
10U
10U
_0805_25V6K
_0805_25V6K
R66 0_0603_5%
R67 0_0603_5%
R68 0_0603_5%
R69 0_0603_5%
CODEC_PD_N
CODEC_PD_N_R
2
+3VA_AMP+3V +3VD_AMP+3V
L11
1 2
BLM15PX121SN1D_2P
12
C347
10U
_0603_10V
SPK_CON_R+
SPK_CON_RSPK_CON_L+
SPK_CON_L-
2
C348
0.1u_0402_16V7K
1
12
12
C346
C345
0.1U
0.1U_0402_25V6
_0402_25V6
BRD Note:
Route 40 mils width and As short as possible
12
12
12
12
26,28
28
2
1
2
2
C359
1000P_0402_50V7K
1
1
C349
1U
_0402_10V6K
2
C355
C356
1000P_0402_50V7K
1000P_0402_50V7K
1
1 2
BLM15PX121SN1D_2P
Internal
Speaker
JSPKR1
4
4
3
3
2
2
1
1
ACES_ 50281-00401-001
2
C357
1000P_0402_50V7K
1
1
L12
2
C350
1U
_0402_10V6K
1
6
GND
5
GND
I2C ADDRESS:0x 1001_100x
12
R329 10_0603_5%
1 2
C366 1U_0402_25V6K
AMP_PD_N_R
R330 1K_0402_5%
1 2
C373 1U_0402_25V6K
R331
20K_0402_1%
B B
SWF_AVDD AMP_MONO
12
R339 3.3K_0402_1%
SPK_R-28
A A
12
R343 3.3K_0402_1%
SPK_R+28
5
12
1 2
C375 1U_0402_25V6K
1 2
R335 100K_0402_5%
SWF_AVDD
12
SWF_SD_N
SWF_VCLAMP
R332
62K_0402_1%
SWF_PLIMIT
SWF_RINN
SWF_RINP
SWF_GAIN0
SWF_GAIN1
R340 3.3K_0402_1%
2
C382
680P_0402_50V7K
1
R344 3.3K_0402_1%
U9
7
AVDD
1
SD#
2
FLAG#
9
TPA3113D2PWPR
12
VCLAMP
10
PLIMIT
3
LINP
4
LINN
11
RINN
12
RINP
14
MONO
5
GAIN0
6
GAIN1
12
12
2
C383
680P_0402_50V7K
1
12
R346
2.2K_0402_5%
4
12
C381 1U_0402_10V6K
C384 1U_0402_10V6K
R347
2.2K_0402_5%
1 2
1 2
LPVDD
LPVDD
RPVDD
RPVDD
LBSP
LOUTP
LOUTN
LBSN
RBSN
ROUTN
ROUTP
RBSP
AGND
PGND
PGND
TGND
27
28
15
16
26
25
23
22
21
20
18
17
13
NC
8
19
24
29
+VCC_SWF
1 2
C374 0.47U_0402_25V6K
1 2
C376 0.47U_0402_25V6K
SWF_RINN
SWF_RINP
SWF_R+
SWF_R-
：
CAD Note
00:Gain=20dB,RI=60k ohm(Default)
01:Gain=26dB,RI=30k ohm
00:Gain=32dB,RI=15k ohm
00:Gain=38dB,RI=9k ohm
3
SWF_GAIN[1::0]
SWF_GAIN0
SWF_GAIN1
SWF_RSWF_R+
12
R333
@
33_0402_5%
12
C379
@
22P_0402_50V8-
J
+5V
R341
@
10K_0402_5%
1 2
R345
10K_0402_5%
1 2
@
PJ7
R70 0_0603_5%
R71 0_0603_5%
12
R334
@
33_0402_5%
12
C380
@
22P_0402_50V8-
J
R342
@
10K_0402_5%
1 2
R348
10K_0402_5%
1 2
2
+VCC_SWF+12V_SWF_BOOST+VCC_SWF
12
12
12
C370
C369
@
@
10U
10U
_0805_25V6K
_0805_25V6K
12
12
12
C371
C372
_0805_25V6K
10U
BRD Note:
Route 40 mils width
2
C377
1000P_0402_50V7K
1
Title
Title
Title
Size Document Number
Size Document Number
Size Document Number
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet of
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
obtained without the expressed written consent of LENOVO PND."
12
_0805_25V6K
10U
SWF_CON_RSWF_CON_R+
2
C378
1000P_0402_50V7K
1
AMP
AMP
AMP
Skylake-H
Skylake-H
Skylake-H
C367
0.1U_0402_25V6
12
C368
_0402_25V6
0.1U
Sub Woofer
JSWF1
1
1
2
2
3
GND
4
GND
ACES_50271-00201-001
1
LENOVO.CRDN
LENOVO.CRDN
LENOVO.CRDN
29
29
29
Rev
Rev
Rev
V0.3
V0.3
V0.3
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
99Wednesday, January 27, 2016
of
of
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