Lenovo S540-14API Schematic
A
1 1
B
C
D
E
Compal Confidential
2 2
M/B Schematics Document
AMD Picasso FP5 APU with DDR4
EL4C2/EL452
LA-H091P
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
Rev : 1.0
2018-12-20
Compal Secret Data
Compal Secret Data
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-H091P
LA-H091P
LA-H091P
1 41Thursday, December 20, 2018
1 41Thursday, December 20, 2018
1 41Thursday, December 20, 2018
E
1.0
1.0
1.0
For Compal DFB review
A
B
C
D
E
NGFF (Key M)
PCIE/SATA SSD
2242/2280 conn.
1 1
NGFF (Key E)
WLAN/BT
2230 conn.
NGFF (Key M)
PCIE SSD
2242 conn.
For S540-14 only
eDP Panel
FHD LCD
QHD For S540-14
HDMI Conn.
2 2
HDMI1.4b
PCIe x4 , Gen3 8Gb/s , SATA x1 , Gen3 6Gb/s
PCIe x1 , Gen1 2.5Gb/s
USB2.0 x1, 480Mb/s
PCIe x2 , Gen3 8Gb/s
eDP x4 HBR2 5.4Gb/s
Parade
PS8407A
DDI x4 , 2.97GT/s
AMD Picasso Ridge
1140pin BGA
USB2.0 x1, 480Mb/s
USB3.1 x1, 5Gb/s USB3.1 x1, Gen1 5Gb/s
USB3.1 x1, 5Gb/s
USB2.0 x1, 480Mb/s
USB2.0 x1, 480Mb/s
USB2.0 x1, 480Mb/s
I2C
PCIe x1 , Gen1 2.5Gb/s
DDR4 2400MHz
VBus
Type-C Conn.
USB3.1 Gen1
3 3
CC/Vconn
USB3.1x1, Gen1
5V Switch
MUX/CC
Realtek RTS5448
I2C_3VLP
USB2.0 x1, 480Mb/s
EC
USB3 redriver
Parade PS8713B
HDA
USB3.1x1, Gen1
I2C
SPI
CH-A on board RAM x4
CH-B DDR4-SO-DIMM X1
USB Charger
TI SN1702001RTER
USB3 redriver
Parade PS8713B
USB3 redriver
Parade PS8713B
Int. Camera
USB2.0 Hub
For C340-14
For S540-14
FingerPrint
Card Reader
Realtek RTS5232S
TouchPanel
Audio Codec
Synaptics CX11880
TouchPad
SPI ROM
8MB
USB2.0 x1, 480Mb/s
USB3.1 x1, Gen1 5Gb/s
SDIO
SPK
DMIC
USB3.0 Conn.
with AOU
USB3.0 Conn.
On Sub Board
SD Card Conn.
On Sub Board
Combo Jack
Int. Speaker
Int. Array Mic *2
LPC
G- Sensor x2
For C340-14 only
4 4
Hall Sensor x2
S540-14 used one
Int. KBD
KBC
ENE KB9022
LED
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
Compal Secret Data
Compal Secret Data
Compal Secret Data
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
D
D
D
LA-H091P
LA-H091P
LA-H091P
Date: Sheet
Date: Sheet
Date: Sheet
E
2 41Monday, December 17, 2018
2 41Monday, December 17, 2018
2 41Monday, December 17, 2018
of
of
of
For Compal DFB review
1.0
1.0
1.0
A
B
C
D
E
Voltage Rails
Power Plane
VIN
B+
+APU_CORE
+APU_CORE_SOC
1 1
+RTC_APU
+3VALW
+3VS
+1.8VALW
+1.8VS
+0.8VALW
+0.8VS
+1.2V_DDR
+2.5V_MEM
+0.6VS_VTT
+5VALW
+5VS
Description
Adapter power supply
AC or battery power rail for power circuit.
Core voltage for APU
Core voltage for APU
RTC power
3.3V always on power rail
3.3V switched power rail
1.8V always on power rail
1.8V switched power rail
0.95V always on power rail
0.95V switched power rail
1.2V power rail for APU and DDR
2.5V power rail for DDR
0.6V switched power rail for DDR terminator
5V always on power rail
5V switched power rail
S0 S3 S5
ON ON ON
OFF
ON
OFF OFF
ON
ONON
OFF OFF
ON
ON ONON
OFF OFF
ON
ON
ON ON
OFF OFF
ON
ON
ON
ON ON
OFFONOFF
ON
ON ON
OFF OFF
ON
STATE
Full ON
ONONON
OFF
S3 (Suspend to RAM)
S4 (Suspend to Disk)
ONON ON
ON
S5 (Soft OFF) LOW
CPU
OFF
OFF
APU_R7@
APU_R5@
SIGNAL
SLP_S3# SLP_S5# +VALW +V +VS Clock
HIGH HIGH
HIGH
LOW
UC1
SA0000C7640
S IC RYZEN7 YM3700C4T4MFG 2.2G BGA 1140 APU
UC1
SA0000CCR20
S IC RYZEN5 YM3500C4T4MFG 2G BGA 1140 APU
HIGH
HIGH
PCB
ON
ON ON O N
ON
ON
OFF
ON
ON
ZZZ
DA8001H5010
PCB 2GB LA-H091P REV1 M/B 3, A.2
ZZZ
45@
RO0000003HM
HDMI Logo
OFF
OFFLOW
OFF
OFF
EMC X4E
ZZZ
X4EAF738L51
SMT EMC FOR EE AH091 EL452
SMBUS Control Table
2 2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK4
EC_SMB_DA4
SOURCE
KB902 2
+3VALW
KB902 2
+3VS
KB902 2
+3VS
APU
BATT KB9022 SODIMM
X V XV
+3VALW
V
+1.8VS
X
X X
X X X X V
+3VALW
V
+3VALW
EC SM Bus1 address EC SM Bus2 address
Device
Smart Battery
Charger 0001 0010 b
3 3
Address
0001 011x b
HEX
16H
12H
Device
APU
G-SEN (M/B)
G-SEN (S/B)
Thermal sensor
Address
1001 100X b
0001 1000 b
0001 1001 b
1001 101xb
WLAN
X
X
HEX
98H
18H
19H
9AH
G-sensor
THM-sensor
X
X
+3VS
X
V
+3VS
X
USB OC MAPPING
0
1
2
3
USB PortOC#
USB2_0_p ort1
USB2_0_p ort2
USB3_0_p ort1
USB3_0_p ort2
X4EUMA@
DDR X76
ZZZ
X7680638L51
Hynix 1G onboard RAM
X76DDR4H@
ZZZ
X7680638L52
Micron 1G onboard RAM
X76DDR4M@
ZZZ
X7680638L53
Samsung 1G onboard RAM
X76DDR4S@
BOM Structure Table
BOM Structure Item
RAVE N7@
OFF
OFF
OFF
RAVE N5@
RAVE N3@ RAVEN3 CPU
X76DDR4H@
X76DDR4M@
X76DDR4S@
X76R AM@
X4EU MA@
ME@
EMI@
@EMI @
ESD@
@ESD @
20V_PRTCT@
X76_ PA@
X76_ PE@
X76_ TI@
PA@
PE@
TI@
RF@
@RF@
RAVEN7 CPU
RAVEN5 CPU
Onboard RAM HYNIX
Onboard RAM MICRON
Onboard RAM SAMSUNG
Onboard RAM couple cap
EMC component for UMA
ME part
EMI pop componemt
EMI Unpop component
ESD pop component
ESD Unpop component
20V protection circuit
Pericom USB re-driver
Parade USB re-driver
TI USB re-driver
Pericom U SB re-driver couple cap
Parade USB re-driver couple cap
TI USB re-driver couple cap
RF pop componemt
RF Unpop component
GPP Port Table
Devi cePort
GPP0
CardReader (PCIe)
GPP1
GPP2
GPP3
GPP4
GPP5
GPP6
GPP7
WLAN (PCIe)
SSD x 2 (PCIe)
SSD x 4 (PCIe)
BOM Structure Item
X76G L@
X76R T@
HDT@
FP@
KBL@
@
SDP@
DDP@
C340 @
S540 @
G_SE N@
QHD@
LS@
DisplayPort Table
Port
Devi ce
0
eDP
1
HDMI
3
2
O2 Card Reader
Realtek Card Reader
For HDT Debug used
Finger Print Component
KeyBoard Backlight
Unpop
DDR SDP Component
DDR DDP Component
C340 SKU
S540 SKU
G-sensor Component
QHD panel component
Level shift Component
APU I2C Bus address
Device
Port
G-sensor (Reserve)
I2C 1
DDR so-DIMM
I2C 2
Touch Panel (Wacom)
Touch Pad (Synaptics)
I2C 3
Touch Pad (Elan)
G-sensor
4 4
Address
1010 001Xb
For Compal DFB review
A
HEX
A2H
0X0A
$2C
0X15
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
USB3.0 Port Table
Port
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0
1
2
3
4
Devi ce
Type C Right
USB3.0 Left-1
USB3.0 Left-2
D
USB2.0 Port Table
Port
Devi ce
0
Type C Right
1
USB3.0 Left-1
2
USB3.0 Left-2
3
Camera
4
USB Hub
5
NGFF_BT
4-1
Touch Screen
4-2
Finger Print
4-3
4-4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
NOTES LIST
NOTES LIST
Document Number Re v
Document Number Re v
Document Number Re v
NOTES LIST
LA-H091P
LA-H091P
LA-H091P
E
1.0
1.0
3 41Thursday, December 20, 2018
3 41Thursday, December 20, 2018
3 41Thursday, December 20, 2018
1.0
of
of
of
A
B
C
D
E
Power Sequence
1 1
EC Pin 110 Intput
EC Pin 112 Output
AC Plug
EC Pin 114 Intput
EC Pin 100 Output
EC Pin 122 Output
2 2
EC Pin 123 Intput
EC Pin 6 Intput
EC Pin 95 Output
EC Pin 116 Output
EC Pin 98 Output
3 3
EC Pin 121 Output
EC Pin 32 Output
EC Pin 13 Intput
VCIN 1_AC_I N
+3VL P
EC_O N
+5VA LW
+3VA LW
3V/5 VALW_P G
+1.8 VALW
+0.8 VALW
ON/O FF#
EC_R SMRST#
RTC_ CLK
PBTN _OUT#
PM_S LP_S5#
PM_S LP_S3#
SYSO N
+2.5 V
+1.2 V
SUSP #
0.8V S_PWR_ EN
+5VS
+3VS
+1.8 VS
+0.8 VS
+0.6 VS
VR_O N
+APU _CORE
+APU _CORE_ SOC
VGAT E
PCH_ PWROK
APU_ PWRGD
PLT_ RST#
PCIE _RST#
APU_ RST#
CLK_ PCIE
T1_Min : 10ms
Boot
T2 : 15ms~26ms
T3 : 30us~64us
T5_Min : 1ms
T8 : 15ms~17ms
T9 : 12ms~14.6ms
Shut
Down
VCIN 1_AC_I N
+3VL P
EC_O N
+5VA LW
+3VA LW
3V/5 VALW_P G
+1.8 VALW
+0.8 VALW
ON/O FF#
EC_R SMRST#
RTC_ CLK
PBTN _OUT#
PM_S LP_S5#
PM_S LP_S3#
SYSO N
+2.5 V_MEM
+1.2 V_DDR
SUSP #
0.8V S_PWR_ EN
+5VS
+3VS
+1.8 VS
+0.8 VS
+0.6 VS
VR_O N
+APU _CORE
+APU _CORE_ SOC
VGAT E
PCH_ PWROK
APU_ PWRGD
PLT_ RST#
PCIE _RST#
APU_ RST#
CLK_ PCIE
4 4
Security Classification
Security Classification
For Compal DFB review
A
B
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Power Sequence
Power Sequence
Document Number Re v
Document Number Re v
Document Number Re v
Power Sequence
LA-H091P
LA-H091P
LA-H091P
E
4 41Monday, December 17, 2018
4 41Monday, December 17, 2018
4 41Monday, December 17, 2018
1.0
1.0
1.0
of
of
of
Main Func = CPU
A
B
C
D
E
1 1
DDR_A_MA[13..0][12]
DDR_A_WE#[12]
DDR_A_CAS#[12]
DDR_A_RAS#[12]
DDR_A_BA0[12]
DDR_A_BA1[12]
DDR_A_BG0[12]
DDR_A_BG1[12]
DDR_A_ACT#[12]
DDR_A_DM[7..0][12]
2 2
DDR_A_DQS0[12]
DDR_A_DQS0#[12]
DDR_A_DQS1[12]
DDR_A_DQS1#[12]
DDR_A_DQS2[12]
DDR_A_DQS2#[12]
DDR_A_DQS3[12]
DDR_A_DQS3#[12]
DDR_A_DQS4[12]
DDR_A_DQS4#[12]
DDR_A_DQS5[12]
DDR_A_DQS5#[12]
DDR_A_DQS6[12]
DDR_A_DQS6#[12]
DDR_A_DQS7[12]
DDR_A_DQS7#[12]
DDR_A_CLK0[12]
DDR_A_CLK0#[12]
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_BG0
DDR_A_BG1
DDR_A_ACT#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_CS0#[12]
3 3
DDR_A_CKE0[12]
DDR_A_ODT0[12]
DDR_A_ALERT#[12]
DDR_A_RST#[12]
AF25
AE23
AD27
AE21
AC24
AC26
AD21
AC27
AD22
AC21
AF22
AA24
AC23
AJ25
AG27
AG23
AG26
AF21
AF27
AA21
AA27
AA22
AL24
AN27
AW25
AT21
AM26
AM27
AN24
AN25
AU23
AT23
AV20
AW20
AD25
AD24
AE26
AE27
AG21
AJ27
AG24
AJ22
AA25
AE24
F21
G27
N24
N23
T27
F22
G22
H27
H26
N27
N26
R21
P21
V24
V23
Y23
Y26
Y24
UC1A @
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13_BANK2
MA_WE_L_ADD14
MA_CAS_L_ADD15
MA_RAS_L_ADD16
MA_BANK0
MA_BANK1
MA_BG0
MA_BG1
MA_ACT_L
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
RSVD_36
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
RSVD_41
RSVD_40
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CS_L0
MA_CS_L1
MA_CKE0
MA_CKE1
MA_ODT0
MA_ODT1
MA_ALERT_L
MA_EVENT_L
MA_RESET_L
FP5_BGA1140~D
MEMORY A
FP5 REV 0.90
PART 1 OF 13
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
RSVD_34
RSVD_35
RSVD_51
RSVD_52
RSVD_27
RSVD_28
RSVD_43
RSVD_42
MA_PAROUT
J21
H21
F23
H23
G20
F20
J22
J23
G25
F26
L24
L26
L23
F25
K25
K27
M25
M27
P27
R24
L27
M24
P24
P25
M22
N21
T22
V21
L21
M20
R23
T21
AL27
AL25
AP26
AR27
AK26
AK24
AM24
AP27
AM23
AM21
AR25
AU27
AL22
AL21
AP24
AP23
AW26
AV25
AV22
AW22
AU26
AV27
AW23
AT22
AW21
AU21
AP21
AN20
AR22
AN22
AT20
AR20
T24
T25
W25
W27
R26
R27
V27
V26
AF24
DDR_A_DQ0
DDR_A_DQ1
DDR_A_DQ2
DDR_A_DQ3
DDR_A_DQ4
DDR_A_DQ5
DDR_A_DQ6
DDR_A_DQ7
DDR_A_DQ8
DDR_A_DQ9
DDR_A_DQ10
DDR_A_DQ11
DDR_A_DQ12
DDR_A_DQ13
DDR_A_DQ14
DDR_A_DQ15
DDR_A_DQ16
DDR_A_DQ17
DDR_A_DQ18
DDR_A_DQ19
DDR_A_DQ20
DDR_A_DQ21
DDR_A_DQ22
DDR_A_DQ23
DDR_A_DQ24
DDR_A_DQ25
DDR_A_DQ26
DDR_A_DQ27
DDR_A_DQ28
DDR_A_DQ29
DDR_A_DQ30
DDR_A_DQ31
DDR_A_DQ32
DDR_A_DQ33
DDR_A_DQ34
DDR_A_DQ35
DDR_A_DQ36
DDR_A_DQ37
DDR_A_DQ38
DDR_A_DQ39
DDR_A_DQ40
DDR_A_DQ41
DDR_A_DQ42
DDR_A_DQ43
DDR_A_DQ44
DDR_A_DQ45
DDR_A_DQ46
DDR_A_DQ47
DDR_A_DQ48
DDR_A_DQ49
DDR_A_DQ50
DDR_A_DQ51
DDR_A_DQ52
DDR_A_DQ53
DDR_A_DQ54
DDR_A_DQ55
DDR_A_DQ56
DDR_A_DQ57
DDR_A_DQ58
DDR_A_DQ59
DDR_A_DQ60
DDR_A_DQ61
DDR_A_DQ62
DDR_A_DQ63
DDR_A_PAR
DDR_A_DQ[63..0] [12]
DDR_A_PAR [12]
UC1I @
DDR_B_MA[13..0][13]
DDR_B_WE#[13]
DDR_B_CAS#[13]
DDR_B_RAS#[13]
DDR_B_BA0[13]
DDR_B_BA1[13]
DDR_B_BG0[13]
DDR_B_BG1[13]
DDR_B_ACT#[13]
DDR_B_DM[7..0][13]
DDR_B_DQS0[13]
DDR_B_DQS0#[13]
DDR_B_DQS1[13]
DDR_B_DQS1#[13]
DDR_B_DQS2[13]
DDR_B_DQS2#[13]
DDR_B_DQS3[13]
DDR_B_DQS3#[13]
DDR_B_DQS4[13]
DDR_B_DQS4#[13]
DDR_B_DQS5[13]
DDR_B_DQS5#[13]
DDR_B_DQS6[13]
DDR_B_DQS6#[13]
DDR_B_DQS7[13]
DDR_B_DQS7#[13]
DDR_B_CLK0[13]
DDR_B_CLK0#[13]
DDR_B_CLK1[13]
DDR_B_CLK1#[13]
DDR_B_CS0#[13]
DDR_B_CS1#[13]
DDR_B_CKE0[13]
DDR_B_CKE1[13]
DDR_B_ODT0[13]
DDR_B_ODT1[13]
DDR_B_ALERT#[13]
DDR_B_EVENT#[13]
DDR_B_RST#[13]
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG0
DDR_B_BG1
DDR_B_ACT#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_EVENT#
AG30
AC32
AC30
AB29
AB31
AA30
AA29
AA31
AH29
AL30
AK30
AK32
AJ30
AH31
AG32
AP30
AW31
BB26
BD22
AR29
AR31
AW30
AW29
BC25
BA25
BC22
BA22
AC31
AD30
AD29
AD31
AE30
AE32
AF29
AF31
AJ31
AM31
AJ29
AM29
AL31
AM32
AL29
AM30
AG29
Y30
W29
Y32
W31
V31
V29
V30
C21
C25
E32
K30
N32
D22
B22
D25
B25
F29
F30
K31
K29
N31
N29
U29
T30
V32
U31
W30
T31
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13_BANK2
MB_WE_L_ADD14
MB_CAS_L_ADD15
MB_RAS_L_ADD16
MB_BANK0
MB_BANK1
MB_BG0
MB_BG1
MB_ACT_L
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
RSVD_21
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
RSVD_20
RSVD_18
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB1_CS_L1
MB0_CKE0
MB0_CKE1
MB1_CKE0
MB1_CKE1
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB1_ODT1
MB_ALERT_L
MB_EVENT_L
MB_RESET_L
FP5_BGA1140~D
MEMORY B
FP5 REV 0.90
PART 9 OF 13
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
RSVD_17
RSVD_19
RSVD_26
RSVD_29
RSVD_16
RSVD_15
RSVD_25
RSVD_24
MB_PAROUT
B21
D21
B23
D23
A20
C20
A22
C22
D24
A25
D27
C27
C23
B24
C26
B27
C30
E29
H29
H31
A28
D28
F31
G30
J29
J31
L29
L31
H30
H32
L30
L32
AP29
AP32
AT29
AU32
AN30
AP31
AR30
AT31
AU29
AV30
BB30
BA28
AU30
AU31
AY32
AY29
BA27
BC27
BA24
BC24
BD28
BB27
BB25
BD25
BC23
BB22
BC21
BD20
BB23
BA23
BB21
BA21
M31
N30
P31
R32
M30
M29
P30
P29
AG31
DDR_B_DQ0
DDR_B_DQ1
DDR_B_DQ2
DDR_B_DQ3
DDR_B_DQ4
DDR_B_DQ5
DDR_B_DQ6
DDR_B_DQ7
DDR_B_DQ8
DDR_B_DQ9
DDR_B_DQ10
DDR_B_DQ11
DDR_B_DQ12
DDR_B_DQ13
DDR_B_DQ14
DDR_B_DQ15
DDR_B_DQ16
DDR_B_DQ17
DDR_B_DQ18
DDR_B_DQ19
DDR_B_DQ20
DDR_B_DQ21
DDR_B_DQ22
DDR_B_DQ23
DDR_B_DQ24
DDR_B_DQ25
DDR_B_DQ26
DDR_B_DQ27
DDR_B_DQ28
DDR_B_DQ29
DDR_B_DQ30
DDR_B_DQ31
DDR_B_DQ32
DDR_B_DQ33
DDR_B_DQ34
DDR_B_DQ35
DDR_B_DQ36
DDR_B_DQ37
DDR_B_DQ38
DDR_B_DQ39
DDR_B_DQ40
DDR_B_DQ41
DDR_B_DQ42
DDR_B_DQ43
DDR_B_DQ44
DDR_B_DQ45
DDR_B_DQ46
DDR_B_DQ47
DDR_B_DQ48
DDR_B_DQ49
DDR_B_DQ50
DDR_B_DQ51
DDR_B_DQ52
DDR_B_DQ53
DDR_B_DQ54
DDR_B_DQ55
DDR_B_DQ56
DDR_B_DQ57
DDR_B_DQ58
DDR_B_DQ59
DDR_B_DQ60
DDR_B_DQ61
DDR_B_DQ62
DDR_B_DQ63
DDR_B_PARDDR_A_EVENT#
DDR_B_DQ[63..0] [13]
DDR_B_PAR [13]
DDR_B_RST#
EVENT# pull high
+1.2V
4 4
1 2
RC1 1K_0402_5%
1 2
RC2 1K_0402_5%
MD@
For Compal DFB review
A
DDR_B_EVENT#
DDR_A_EVENT#
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
1 2
CC85
100P_0402_50V8J
@ESD@
ESD
Compal Secret Data
Compal Secret Data
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FP5 DDR4 MEMORY I/F
FP5 DDR4 MEMORY I/F
FP5 DDR4 MEMORY I/F
Document Number Re v
Document Number Re v
Document Number Re v
LA-H091P
LA-H091P
LA-H091P
E
5 41Wednesday, December 19, 2018
5 41Wednesday, December 19, 2018
5 41Wednesday, December 19, 2018
1.0
1.0
1.0
A
B
C
D
E
Main Func = CPU
UC1B
J11
P8
P9
N6
N7
M8
M9
H6
H7
G6
F7
G8
F8
L6
L7
@
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
PCIE
N1
P_GFX_TXP0
N3
P_GFX_TXN0
M2
P_GFX_TXP1
M4
P_GFX_TXN1
L2
P_GFX_TXP2
L4
P_GFX_TXN2
L1
P_GFX_TXP3
L3
P_GFX_TXN3
K2
P_GFX_TXP4
K4
P_GFX_TXN4
J2
P_GFX_TXP5
J4
P_GFX_TXN5
H1
P_GFX_TXP6
H3
P_GFX_TXN6
H2
P_GFX_TXP7
H4
P_GFX_TXN7
1 1
K11
2 2
CardRead er
WLAN
2nd_SSD
Mai n_SS D
3 3
4 4
PCIE_ARX_DTX_P0[22]
PCIE_ARX_DTX_N0[22]
PCIE_ARX_DTX_P1[17]
PCIE_ARX_DTX_N1[17]
PCIE_ARX_DTX_P2[19]
PCIE_ARX_DTX_N2[19]
PCIE_ARX_DTX_P3[19]
PCIE_ARX_DTX_N3[19]
PCIE_ARX_DTX_P4[18]
PCIE_ARX_DTX_N4[18]
PCIE_ARX_DTX_P5[18]
PCIE_ARX_DTX_N5[18]
PCIE_ARX_DTX_P6[18]
PCIE_ARX_DTX_N6[18]
SATA_ARX_DTX_P1[18]
SATA_ARX_DTX_N1[18]
PCIE_ARX_DTX_P0
PCIE_ARX_DTX_N0
PCIE_ARX_DTX_P1
PCIE_ARX_DTX_N1
PCIE_ARX_DTX_P2
PCIE_ARX_DTX_N2
PCIE_ARX_DTX_P3 PCIE_ATX_C_DRX_P3
PCIE_ARX_DTX_N3
PCIE_ARX_DTX_P4
PCIE_ARX_DTX_N4
PCIE_ARX_DTX_P5
PCIE_ARX_DTX_N5
PCIE_ARX_DTX_P6
PCIE_ARX_DTX_N6
SATA_ARX_DTX_P1
SATA_ARX_DTX_N1
For Compal DFB review
A
N10
M11
P12
P11
R10
B
P_GPP_RXP0
N9
P_GPP_RXN0
L10
P_GPP_RXP1
L9
P_GPP_RXN1
L12
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
V6
P_GPP_RXP4
V7
P_GPP_RXN4
T8
P_GPP_RXP5
T9
P_GPP_RXN5
R6
P_GPP_RXP6/SATA_RXP0
R7
P_GPP_RXN6/SATA_RXN0
R9
P_GPP_RXP7/SATA_RXP1
P_GPP_RXN7/SATA_RXN1
FP5 REV 0.90
FP5_BGA1140~D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PART 2 OF 13
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_GPP_TXP4
P_GPP_TXN4
P_GPP_TXP5
P_GPP_TXN5
P_GPP_TXP6/SATA_TXP0
P_GPP_TXN6/SATA_TXN0
P_GPP_TXP7/SATA_TXP1
P_GPP_TXN7/SATA_TXN1
C
PCIE_ATX_DRX_P0
N2
PCIE_ATX_DRX_N0
P3
PCIE_ATX_DRX_P1
P4
PCIE_ATX_DRX_N1
P2
PCIE_ATX_DRX_P2
R3
PCIE_ATX_DRX_N2
R1
PCIE_ATX_DRX_P3
T4
PCIE_ATX_DRX_N3
T2
PCIE_ATX_DRX_P4
W2
PCIE_ATX_DRX_N4
W4
PCIE_ATX_DRX_P5
W3
PCIE_ATX_DRX_N5
V2
PCIE_ATX_DRX_P6
V1
PCIE_ATX_DRX_N6
V3
SATA_ATX_DRX_P1
U2
SATA_ATX_DRX_N1
U4
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1 2
CC9 0.1U_0201_10V6K
1 2
CC10 0.1U_0201_10V6K
1 2
CC11 0.1U_0201_10V6K
1 2
CC12 0.1U_0201_10V6K
1 2
CC13 0.22U_0402_6.3V6K
1 2
CC14 0.22U_0402_6.3V6K
1 2
CC15 0.22U_0402_6.3V6K
1 2
CC16 0.22U_0402_6.3V6K
1 2
CC1 0.22U_0402_6.3V6K
1 2
CC2 0.22U_0402_6.3V6K
1 2
CC3 0.22U_0402_6.3V6K
1 2
CC4 0.22U_0402_6.3V6K
1 2
CC5 0.22U_0402_6.3V6K
1 2
CC6 0.22U_0402_6.3V6K
1 2
CC7 0.22U_0402_6.3V6K
1 2
CC8 0.22U_0402_6.3V6K
D
PCIE_ATX_C_DRX_P0 [22]
PCIE_ATX_C_DRX_N0 [22]
PCIE_ATX_C_DRX_P1 [17]
PCIE_ATX_C_DRX_P2
PCIE_ATX_C_DRX_N2
PCIE_ATX_C_DRX_N3
PCIE_ATX_C_DRX_P4
PCIE_ATX_C_DRX_N4
PCIE_ATX_C_DRX_P5
PCIE_ATX_C_DRX_N5
PCIE_ATX_C_DRX_P6
PCIE_ATX_C_DRX_N6
SATA_ATX_C_DRX_P1
SATA_ATX_C_DRX_N1
Title
Title
Title
Size
Size
Size
Document Numbe r Re v
Document Numbe r Re v
Document Numbe r Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
PCIE_ATX_C_DRX_N1 [17]
PCIE_ATX_C_DRX_P2 [19]
PCIE_ATX_C_DRX_N2 [19]
PCIE_ATX_C_DRX_P3 [19]
PCIE_ATX_C_DRX_N3 [19]
PCIE_ATX_C_DRX_P4 [18]
PCIE_ATX_C_DRX_N4 [18]
PCIE_ATX_C_DRX_P5 [18]
PCIE_ATX_C_DRX_N5 [18]
PCIE_ATX_C_DRX_P6 [18]
PCIE_ATX_C_DRX_N6 [18]
SATA_ATX_C_DRX_P1 [18]
SATA_ATX_C_DRX_N1 [18]
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
FP5 PCIE/UMI
FP5 PCIE/UMI
FP5 PCIE/UMI
LA-H091P
LA-H091P
LA-H091P
E
6 41Monday, December 17, 2018
6 41Monday, December 17, 2018
6 41Monday, December 17, 2018
CardRead er
WLAN
2nd_SSD
Mai n_SS D
NGFF_SATANGFF_SATA
1.0
1.0
1.0
A
B
C
D
E
Main Func = CPU
DP0: eDP
DP1: HDMI
DP2: N/A
DP3: N/A
UC1C @
DISPLAY/SVI2/JTAG/T EST
C8
EDP_TXP0[14]
1 1
eDP
HDMI
EDP_TXN0[14]
EDP_TXP1[14]
EDP_TXN1[14] EDP_AUXP [14]
EDP_TXP2[14]
EDP_TXN2[14]
EDP_TXP3[14]
EDP_TXN3[14]
APU_DP1_P0[15]
APU_DP1_N0[15]
APU_DP1_P1[15]
APU_DP1_N1[15]
APU_DP1_P2[15]
APU_DP1_N2[15]
APU_DP1_P3[15]
APU_DP1_N3[15]
DP0_TXP0
A8
DP0_TXN0
D8
DP0_TXP1
B8
DP0_TXN1
B6
DP0_TXP2
C7
DP0_TXN2
C6
DP0_TXP3
D6
DP0_TXN3
E6
DP1_TXP0
D5
DP1_TXN0
E1
DP1_TXP1
C1
DP1_TXN1
F3
DP1_TXP2
E4
DP1_TXN2
F4
DP1_TXP3
F2
DP1_TXN3
DP_BLON
DP_DIGON
DP_VARY_BL
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
DP3_AUXP
DP3_AUXN
DP_STEREOSYNC
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
RSVD_4
RSVD_3
RSVD_2
G15
F15
L14
D9
B9
C10
G11
F11
G13
J12
H12
K13
J10
H10
K8
K15
F14
F12
F10
ENBKL_R
ENVDD
INVTPWM_R
DP_STEREOSYNC
ENVDD [14]
EDP_AUXN [14]
EDP_HPD [14]
APU_DP1_CTRL_CLK [15]
APU_DP1_CTRL_DAT [15]
APU_DP1_HPD [15]
+LCDVDD_CONN PWR switch enable pin VIH=1.2V
eDP
HDMI
ENBKL_R
INVTPWM_R
+1.8VS
QC1
2
Gate
Drain
3
Source
LBSS139WT1G_SC70-3
U19
NC1VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
1
Y
ENBKL [14,28]
+1.8VS
5
4
INVTPWM [14]
INVTPWM
ENBKL
ENBKL_R
ENVDD
INVTPWM_R
EDP_HPD
1 2
RC4 4.7K_0402_5%
1 2
RC5 2.2K_0402_5%
1 2
RC6 100K_0402_5%
1 2
RC8 100K_0402_5%
1 2
RC9 100K_0402_5%
1 2
RC10 100K_0402_5%
+3VS
APU_TEST4
AP14
TEST4
APU_TEST5
AN14
TEST5
APU_TEST6
F13
TEST6
APU_TEST14
G18
TEST14
APU_TEST15
H19
2 2
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
APU_RST#
APU_PWRGD[38]
EC_SMB_CK2[26,28]
EC_SMB_DA2[26,28]
EC_THERMTRIP#[28] APU_VDDP_RUN_FB_H [37]
H_PROCHOT#[28]
APU_SVC[38]
APU_SVD[38]
APU_SVT[38]
3 3
+1.8VS
1 2
RC24 300_0402_5%
1 2
RC25 300_0402_5%
+3VS
1 2
RC31 1K_0201_5%
1 2
RC28 1K_0201_5%
1 2
RC29 1K_0201_5%
1 2
RC30 220_0402_5%@
RC21 0_0402_5%@
APU_RST#
APU_PWRGD
APU_ALERT#
H_PROCHOT#
THERMTRIP#
APU_PWRGD
1 2
APU_PWRGD
APU_ALERT#
THERMTRIP#
AW3
AW4
AW2
AP16
AU2
AU4
AU1
AU3
AV3
H14
J14
J15
L19
F16
H16
J16
TDI
TDO
TCK
TMS
TRST_L
DBREQ_L
RESET_L
PWROK
SIC
SID
ALERT_L
THERMTRIP_L
PROCHOT_L
SVC0
SVD0
SVT0
FP5_BGA1140~D
APU_RST#_EC[28]
FP5 REV 0.90
PART 3 OF 13
TEST15
TEST16
TEST17
TEST31
TEST41
TEST470
TEST471
SMU_ZVDD
CORETYPE
VDDP_SENSE
VDDCR_SOC_SENSE
VDDCR_SENSE
VSS_SENSE_A
VSS_SENSE_B
1
NC
2
A
RC111 0_0402_5%@
F18
F19
W24
AR11
AJ21
AK21
V4
AW11
AN11
J19
K18
J18
AM11
+3VS
5
UC22
P
4
Y
G
74AUP1G07GW_SC70-5
3
@
12
APU_TEST16
APU_TEST17
APU_TEST31
APU_TEST41
APU_TEST470
APU_TEST471
SMU_ZVDDP
CORETYPE
APU_VDDP_RUN_FB_H
APU_VDD_RUN_FB_L
APU_VDDP_RUN_FB_L
Reserve for sequence tuning
ESD
1 2
4 4
CC17 100P_0402_50V8JESD@
1 2
CC18 100P_0402_50V8JESD@
1 2
CC19 100P_0402_50V8JESD@
H_PROCHOT#
APU_PWRGD
APU_RST#
APU_RST#
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
APU_VDDSOC_SEN [38]
APU_VDDCR_SEN [38]
T15
APU_VDD_RUN_FB_L [38]
APU_VDDP_RUN_FB_L [37]
APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
APU_TEST31
DP_STEREOSYNC
1 2
RC11 10K_0402_5%@
1 2
RC12 10K_0402_5%@
1 2
RC13 10K_0402_5%@
1 2
RC14 10K_0402_5%@
1 2
RC15 1K_0402_5%@
1 2
RC16 1K_0402_5%@
1 2
RC17 1K_0402_5%
1 2
RC18 1K_0402_5%@
Stereosync need to High to enable HDMI functionality,
SMU_ZVDDP
CORETYPE
1 2
RC22 196_0402_1%
1 2
RC23 1K_0402_5%@
HDT+ (debug + HDT@)
+1.8VALW
1 2
RHDT6 33_0402_5%@
1 2
RHDT7 10K_0402_5%@
1 2
RHDT8 10K_0402_5%@
1 2
RHDT9 10K_0402_5%@
JHDT1
1
1
3
3
5
5
7
APU_TRST#_RAPU_TRST#
7
9
9
11
11
13
13
15
15
17
17
19
19
SAMTE_ASP-136446-07-B
ME@
APU_TCK
2
2
APU_TMS
4
4
APU_TDI
6
6
APU_TDO
8
8
APU_PWRGD
10
10
APU_RST#
12
12
14
14
APU_DBREQ#
16
16
18
18
20
20
APU_TRST#
APU_TCK
APU_TMS
APU_TDI
APU_DBREQ#
APU_TDI
APU_DBREQ#
APU_TRST#
1 2
RHDT1 1K_0402_5%@
1 2
RHDT2 1K_0402_5%@
1 2
RHDT3 1K_0402_5%@
1 2
RHDT4 1K_0402_5%@
1 2
RHDT5 1K_0402_5%@
1 2
CHDT1 0.01U_0402_16V7K
1 2
CHDT2 0.01U_0402_16V7K
1 2
CHDT3 0.01U_0402_16V7K
+1.8VS
+1.8VS
+1.8VS
+0.8VS
+3VALW
+1.8VALW
@
@
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
For Compal DFB review
A
B
C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FP5 DISP/MISC/HDT
FP5 DISP/MISC/HDT
FP5 DISP/MISC/HDT
Document Number Re v
Document Number Re v
Document Number Re v
LA-H091P
LA-H091P
LA-H091P
E
7 41Wednesday, December 19, 2018
7 41Wednesday, December 19, 2018
7 41Wednesday, December 19, 2018
1.0
1.0
1.0
Main Func = CPU
A
B
C
D
E
+1.8VALW
1 2
RC36 22K_0402_5%
1 1
2 2
3 3
4 4
HDA_RST#_AUDIO[20]
HDA_BITCLK_AUDIO[20]
HDA_SDOUT_AUDIO[20]
HDA_SYNC_AUDIO[20]
CC23 100P_0402_50V8J
CC24 100P_0201_25V8J
+3VALW
+3VS
I2C_1_SCL_R[28]
I2C_1_SDA_R[28]
I2C_3_SCL_R[27]
I2C_3_SDA_R[27]
RC108 33_0402_5%
RC67 33_0402_5%EMI@
RC68 33_0402_5%
RC69 33_0402_5%
RC70 1K_0201_5%
RC71 1K_0201_5%
@ESD@
1 2
ESD@
1 2
1 2
RC45 10K_0201_5%
1 2
RC47 10K_0201_5%
1 2
RC48 10K_0402_5%@
1 2
RC109 2.2K_0402_5%
1 2
RC110 2.2K_0402_5%
1 2
RC61 2.2K_0402_5%
1 2
RC62 2.2K_0402_5%
1 2
RC56 2.2K_0402_5%
1 2
RC57 2.2K_0402_5%
1 2
RC50 1K_0201_5%
1 2
RC53 10K_0402_5%@
1 2
RC54 10K_0402_5%@
1 2
CC93 150P_0201_50V8G@
1 2
CC94 150P_0201_50V8G@
1 2
CC95 150P_0402_50V8J@
1 2
CC96 150P_0402_50V8J@
1 2
CC97 150P_0402_50V8J@
1 2
CC98 150P_0402_50V8J@
1 2
1 2
1 2
1 2
1 2
1 2
EC_RSMRST#
SYS_RESET#
PCIE_DET
PBTN_OUT#
APU_PCIE_WAKE#
I2C_1_SCL
I2C_1_SDA
I2C_3_SCL
I2C_3_SDA
I2C_2_SCL
I2C_2_SDA
HDA_RST#
HDA_SDIN0
HDA_BIT_CLK
I2C_1_SCL
I2C_1_SDA
I2C_2_SCL
I2C_2_SDA
I2C_3_SCL
I2C_3_SDA
+3VS
G
S
G
2
QC2B
2N7002KDW_SOT363-6
S
61
D
QC2A
2N7002KDW_SOT363-6
+3VS
G
S
G
2
QC3B
2N7002KDW_SOT363-6
S
61
D
QC3A
2N7002KDW_SOT363-6
EC_RSMRST# [28]
ESD
5
34
D
5
34
D
HDA_RST#
HDA_BIT_CLK
HDA_SDOUT
HDA_SYNC
EMI
CC21
150P_0402_50V8J
RC121 0_0201_5%@
RC122 0_0201_5%@
RC123 0_0201_5%
RC124 0_0201_5%
RC125 0_0201_5%@
RC126 0_0201_5%@
RC127 0_0201_5%
RC128 0_0201_5%
RC42
10K_0201_5%
NO_MD@
RC41
10K_0201_5%
UC1D @
SYS_PWRGD_EC
APU_PCIE0_RST#
APU_PCIE1_RST#APU_PCIE_RST#_R
EC_RSMRST#
PBTN_OUT#
APU_FCH_PWRGD_R
SYS_RESET#
APU_PCIE_WAKE#
PM_SLP_S3#
PM_SLP_S5#
HDA_BIT_CLK
HDA_SDIN0
HDA_RST#
HDA_SYNC
HDA_SDOUT
1 2
RC34 33_0402_5%
1 2
RC35 33_0402_5%@
CC20
1
2
150P_0402_50V8J
@
2
1
12
12
12
12
PBTN_OUT#[28]
PM_SLP_S3#[28]
PM_SLP_S5#[28,33,36]
Internal Pull-down required by SW
HDA_SDIN0[20]
check list discuss unconnected if no used
SYS_PWRGD_EC[28]
I2C_1_SCL
I2C_1_SDA
I2C_3_SCL
I2C_3_SDA
BD5
PCIE_RST0_L/EGPIO26
BB6
PCIE_RST1_L/EGPIO27
AT16
RSMRST_L
AR15
PWR_BTN_L/AGPIO0
AV6
PWR_GOOD
AP10
SYS_RESET_L/AGPIO1
AV11
WAKE_L/AGPIO2
AV13
SLP_S3_L
AT14
SLP_S5_L
AR8
S0A3_GPIO/AGPIO10
AT10
AC_PRES/AGPIO23
AN6
LLB_L/AGPIO12
AW8
EGPIO42
AR2
AZ_BITCLK/TDM_BCLK_MIC
AP7
AZ_SDIN0/CODEC_GPI
AP1
AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK
AP4
AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK
AP3
AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC
AR4
AZ_SYNC/TDM_FRM_MIC
AR3
AZ_SDOUT/TDM_FRM_PLAYBACK
AT2
SW_MCLK/TDM_BCLK_BT
AT4
SW_DATA0/TDM_DOUT_BT
AR6
AGPIO7/FCH_ACP_I2S_SDIN_BT
AP6
AGPIO8/FCH_ACP_I2S_LRCLK_BT
FP5_BGA1140~D
+3VALW +3VALW
5
UC7
1
P
NC
4
Y
2
A
G
74AUP1G07GW_SC70-5
3
SA00007WE00
@
12
RC64 0_0402_5%@
12
RC55
8.2K_0402_5%
APU_FCH_PWRGD_R
ACPI/AUDIO/I2C/GPIO/MIS C
FP5 REV 0.90
PART 4 OF 13
I2C0_SCL/SFI0_I2C_SCL/EGPIO151
I2C0_SDA/SFI0_I2C_SDA/EGPIO152
I2C1_SCL/SFI1_I2C_SCL/EGPIO149
I2C1_SDA/SFI1_I2C_SDA/EGPIO150
3.3VALW Domain
3.3VALW Domain
3.3VALW Domain
3.3VALW Domain
3.3VS Domain
3.3VALW Domain
3.3VALW Domain
3.3VS Domain
3.3VS Domain
3.3VS Domain
3.3VALW Domain
3.3VS Domain
3.3VS Domain
3.3VS Domain
3.3VS Domain
APU_PCIE_RST#_R
EGPIO41/SFI_S5_EGPIO41
AGPIO39/SFI_S5_AGPIO39
I2C2_SCL/EGPIO113/SCL0
I2C2_SDA/EGPIO114/SDA0
I2C3_SCL/AGPIO19/SCL1
I2C3_SDA/AGPIO20/SDA1
PSA_I2C_SCL
PSA_I2C_SDA
AGPIO3
AGPIO4/SATAE_IFDET
AGPIO5/DEVSLP0
AGPIO6/DEVSLP1
SATA_ACT_L/AGPIO130
AGPIO9
AGPIO40
AGPIO69
AGPIO86
INTRUDER_ALERT
SPKR/AGPIO91
BLINK/AGPIO11
GENINT1_L/AGPIO89
GENINT2_L/AGPIO90
FANIN0/AGPIO84
FANOUT0/AGPIO85
12
RC72
@
10K_0402_5%
AW12
AU12
AR13
AT13
I2C_1_SCL
AN8
I2C_1_SDA
AN9
I2C_2_SCL_R
BC20
BA20
AM9
AM10
L16
M16
AT15
AW10
AP9
AU10
AV15
AU7
AU6
AW13
AW15
AU14
AU16
AV8
AW16
BD15
AR18
AT18
RC117 0_0402_5%@
I2C_2_SDA_R
RC118 0_0402_5%@
I2C_3_SCL
I2C_3_SDA
PCIE_DET
MEM_ID0
MEM_ID1
Internal Pull-down required by SW
MODEL_ID0
SENSOR_EC_INT#
HDA_SPKR
MEM_ID2
TS_I2C_RESET#
TS_INT#
MODEL_ID1
TP_INT#
+3VALW
5
2
P
B
1
A
G
3
1 2
RC73 0_0402_5%@
T22
T21
1 2
1 2
PCIE_DET [18]
SENSOR_EC_INT# [28]
HDA_SPKR [20]
TS_I2C_RESET# [14]
TS_INT# [14]
TP_INT# [27]
1
@
CC26
0.1U_0201_10V6K
2
UC8
MC74VHC1G08DFT2G SC70 5P
4
Y
@
Internal Pull-down required by SW
Internal Pull-down required by SW
I2C_2_SCL
I2C_2_SDA
I2C_2_SCL [13,14]
I2C_2_SDA [13,14]
APU_PCIE_RST# [17,18,22]
EC(G-Sens or)
DDR4/Touch Panel
TouchPad
EC(G-Sens or)
NO_MD@
RC43
10K_0201_5%
NO_MD@
MEM_ID
MODEL ID0
S540
MODEL ID
MODEL_ID1
Reserve
APU_SPI_CLK_R[9]
Strap pin
STRAP
SPI_CLK
12
12
12
12
SYS_RST#
MEM_ID2
RAM vender
Hynix
Micron
Samsung
No onboard
1 1 1
1 1
1 1
0 0
+3VALW
RC37
10K_0201_5%
X76RAM@
MEM_ID0
MEM_ID1
MEM_ID2
RC42
10K_0201_5%
X76RAM@
Detect
0
1C340
Detect
0
1
SYS_RESET#
1 2
1 2
RC38
10K_0201_5%
X76RAM@
RC41
10K_0201_5%
X76RAM@
RC59
10K_0201_5%
RC65
2K_0402_5%
@
DEFINITION
1 : Use 48MHZ Crystal Clock and Generate both internal
and external clocks (Default)
0 : Use 100MHZ PCIE clock as reference clock
and generate internal clocks only
1 : Normal reset mode ( Default)
0 : short reset mode
MEM_ID1
RC112
10K_0201_5%
C340@
MODEL_ID0
RC115
10K_0201_5%
S540@
RC113
10K_0201_5%
@
MODEL_ID1
RC116
10K_0201_5%
@
MEM_ID0
0
0
0
RC39
10K_0201_5%
X76RAM@
1 2
1 2
RC43
10K_0201_5%
X76RAM@
1 2
1 2
+3VS
1 2
1 2
+3VS
1 2
1 2
+3VALW+1.8VALW
RC60
10K_0201_5%
1 2
1 2
12
12
RC66
2K_0402_5%
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
For Compal DFB review
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
D
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
FP4 GPIO/AZ/MISC/STRAPS
FP4 GPIO/AZ/MISC/STRAPS
FP4 GPIO/AZ/MISC/STRAPS
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
Custom
Custom
Custom
LA-H091P
LA-H091P
Date: Sheet
Date: Sheet
Date: Sheet
LA-H091P
E
8 41Monday, December 17, 2018
8 41Monday, December 17, 2018
8 41Monday, December 17, 2018
1.0
1.0
1.0
of
of
of
Main Func = CPU
A
B
C
D
E
48MHz CRYSTAL
1 1
48M_X1_R 48M_X1
12
RC75 1M_0402_5%
2
2
3
3
1
CC27
4.7P_0402_50V8B
2
1
1
4
4
1
2
RC74 33_0402_5%EMI@
RC76 33_0402_5%EMI@
YC1
48MHZ_8PF_7V48000010
CC28
4.7P_0402_50V8B
1 2
1 2
48M_X248M_X2_R
EMI
2nd_SSD
Main_ SSD
CardR eader
WLAN
CLKREQ_SSD2#[19]
CLKREQ_SSD1#[18]
CLKREQ_SD#[22]
CLKREQ_WLAN#[17]
APU_BT_OFF#[17]
CLK_PCIE_SSD2[19]
CLK_PCIE_SSD2#[19]
CLK_PCIE_SSD1[18]
CLK_PCIE_SSD1#[18]
CLK_PCIE_SD[22]
CLK_PCIE_SD#[22]
CLK_PCIE_WLAN[17]
CLK_PCIE_WLAN#[17]
32.768KHz CRYSTAL
32K_X1
1
CC31
10P_0402_50V8J
2
CLKREQ_SSD2#
CLKREQ_SSD1#
CLKREQ_SD#
CLKREQ_WLAN#
USB_OC0#
USB_OC1#
32K_X2
USB20_P0[25]
USB20_N0[25]
USB20_P1[22]
USB20_N1[22]
USB20_P2[22]
USB20_N2[22]
USB20_P3[14]
USB20_N3[14]
USB20_P4[21]
USB20_N4[21]
USB20_P5[17]
USB20_N5[17]
USB_OC0#[22]
USB_OC1#[22]
Internal Pull-HIgh required by SW
USB20_P0
USB20_N0
USB20_P1
USB20_N1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
USB20_P4
USB20_N4
USB20_P5
USB20_N5
USB_OC0#
USB_OC1#
AE7
AE6
AG10
AG9
AF12
AF11
AE10
AE9
AJ12
AJ11
AD9
AD8
AM6
AM7
AK10
AK9
AL9
AL8
AW7
AT12
UC1J @
USB_0_DP0
USB_0_DM0
USB_0_DP1
USB_0_DM1
USB_0_DP2
USB_0_DM2
USB_0_DP3
USB_0_DM3
USB_1_DP0
USB_1_DM0
USB_1_DP1
USB_1_DM1
USBC_I2C_SCL
USBC_I2C_SDA
USB_OC0_L/AGPIO16
USB_OC1_L/AGPIO17
USB_OC2_L/AGPIO18
USB_OC3_L/AGPIO24
AGPIO14/USB_OC4_L
AGPIO13/USB_OC5_L
FP5_BGA1140~D
FP5 REV 0.90
PART 10 OF 13
USB
RC87 22 +-5% 0402@
USBC0_A2/USB_0_TXP0/DP3_TXP2
USBC0_A3/USB_0_TXN0/DP3_TXN2
USBC0_B11/USB_0_RXP0/DP3_TXP3
USBC0_B10/USB_0_RXN0/DP3_TXN3
USBC1_A2/USB_0_TXP3/DP2_TXP2
USBC1_A3/USB_0_TXN3/DP2_TXN2
USBC1_B11/USB_0_RXP3/DP2_TXP3
USBC1_B10/USB_0_RXN3/DP2_TXN3
RTC_CLK_R[17]
12
2 2
+3VS
3 3
RC86 20M_0402_5%
1
CC30
10P_0402_50V8J
2
RC88 10K_0201_5%
RC89 10K_0201_5%
RC90 10K_0201_5%
RC91 10K_0201_5%
USB3.1 Type-C
YC2
1 2
32.768KHZ_9PF_X1A000141000200
12
12
12
12
USB3.1 Type-A port1
USB3.1 Type-A port2
Camera
USB2.0 Hub
NGFF_BT
+3VALW
4 4
1 2
RC98 100K_0201_5%
1 2
RC99 100K_0201_5%
CLKREQ_SSD2#
CLKREQ_SSD1#
CLKREQ_SD#
CLKREQ_WLAN#
Internal Pull-down required by SW
Internal Pull-down required by SW
APU_BT_OFF#
CLK_PCIE_SSD2
CLK_PCIE_SSD2#
CLK_PCIE_SSD1
CLK_PCIE_SSD1#
CLK_PCIE_SD
CLK_PCIE_SD#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
48M_X1
48M_X2
RTC_CLK
12
32K_X1
32K_X2
USB3_ATX_DRX_P0
AD2
USB3_ATX_DRX_N0
AD4
USB3_ARX_DTX_P0
AC2
USB3_ARX_DTX_N0
AC4
AF4
USBC0_B2/DP3_TXP1
AF2
USBC0_B3/DP3_TXN1
AE3
USBC0_A11/DP3_TXP0
AE1
USBC0_A10/DP3_TXN0
USBC1_B2/DP2_TXP1
USBC1_B3/DP2_TXN1
USBC1_A11/DP2_TXP0
USBC1_A10/DP2_TXN0
USB_0_TXP1
USB_0_TXN1
USB_0_RXP1
USB_0_RXN1
USB_0_TXP2
USB_0_TXN2
USB_0_RXP2
USB_0_RXN2
USB_1_TXP0
USB_1_TXN0
USB_1_RXP0
USB_1_RXN0
AG3
AG1
AJ9
AJ8
AG4
AG2
AG7
AG6
AA2
AA4
Y1
Y3
AC1
AC3
AB2
AB4
AH4
AH2
AK7
AK6
USB3_ATX_DRX_P1
USB3_ATX_DRX_N1
USB3_ARX_DTX_P1
USB3_ARX_DTX_N1
USB3_ATX_DRX_P2
USB3_ATX_DRX_N2
USB3_ARX_DTX_P2
USB3_ARX_DTX_N2
UC1E @
AV18
CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
AN19
CLK_REQ1_L/AGPIO115
AP19
CLK_REQ2_L/AGPIO116
AT19
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
AU19
CLK_REQ4_L/OSCIN/EGPIO132
AW18
CLK_REQ5_L/EGPIO120
AW19
CLK_REQ6_L/EGPIO121
AK1
GPP_CLK0P
AK3
GPP_CLK0N
AM2
GPP_CLK1P
AM4
GPP_CLK1N
AM1
GPP_CLK2P
AM3
GPP_CLK2N
AL2
GPP_CLK3P
AL4
GPP_CLK3N
AN2
GPP_CLK4P
AN4
GPP_CLK4N
AN3
GPP_CLK5P
AP2
GPP_CLK5N
AJ2
GPP_CLK6P
AJ4
GPP_CLK6N
AJ3
48M_OSC
BB3
X48M_X1
BA5
X48M_X2
AF8
RSVD_76
AF9
RSVD_77
AW14
RTCCLK
AY1
X32K_X1
AY4
X32K_X2
FP5_BGA1140~D
CLK/LPC/EMMC/SD/SPI/eSPI/UART
FP5 REV 0.90
PART 5 OF 13
USB3_ATX_DRX_P0 [23]
USB3_ATX_DRX_N0 [23]
USB3_ARX_DTX_P0 [23]
USB3_ARX_DTX_N0 [23]
USB3_ATX_DRX_P1 [22]
USB3_ATX_DRX_N1 [22]
USB3_ARX_DTX_P1 [22]
USB3_ARX_DTX_N1 [22]
USB3_ATX_DRX_P2 [22]
USB3_ATX_DRX_N2 [22]
USB3_ARX_DTX_P2 [22]
USB3_ARX_DTX_N2 [22]
EGPIO70/SD_CLK
LPC_PD_L/SD_CMD/AGPIO21
LAD0/SD_DATA0/EGPIO104
LAD1/SD_DATA1/EGPIO105
LAD2/SD_DATA2/EGPIO106
LAD3/SD_DATA3/EGPIO107
LPCCLK0/EGPIO74
LPC_CLKRUN_L/AGPIO88
LPCCLK1/EGPIO75
SERIRQ/AGPIO87
LFRAME_L/EGPIO109
LPC_RST_L/SD_WP_L/AGPIO32
AGPIO68/SD_CD
LPC_PME_L/SD_PWR_CTRL/AGPIO22
SPI_ROM_REQ/EGPIO67
SPI_ROM_GNT/AGPIO76
ESPI_RESET_L/KBRST_L/AGPIO129
ESPI_ALERT_L/LDRQ0_L/EGPIO108
SPI_CLK/ESPI_CLK
SPI_DI/ESPI_DATA
SPI_DO
SPI_WP_L/ESPI_DAT2
SPI_HOLD_L/ESPI_DAT3
SPI_CS1_L/EGPIO118
SPI_CS2_L/ESPI_CS_L/AGPIO30
SPI_CS3_L/AGPIO31
SPI_TPM_CS_L/AGPIO29
UART0_RXD/EGPIO136
UART0_TXD/EGPIO138
UART0_RTS_L/UART2_RXD/EGPIO137
UART0_CTS_L/UART2_TXD/EGPIO135
UART0_INTR/AGPIO139
EGPIO141/UART1_RXD
EGPIO143/UART1_TXD
EGPIO142/UART1_RTS_L/UART3_RXD
EGPIO140/UART1_CTS_L/UART3_TXD
AGPIO144/UART1_INTR
TYPEC Right
Type-A left port1
Type-A left port2
BD13
BB14
LPCPD#
LPC_AD0_R
BB12
LPC_AD1_R
BC11
LPC_AD2_R
BB15
LPC_AD3_R
BC15
LPC_CLK0
BA15
BC13
CLKRUN#
BB13
Internal Pull-down required by SW
BC12
BA12
LPC_RST#_R
BD11
BA11
BA13
BC8
BB8
BB11
BC6
APU_SPI_CLK
BB7
APU_SPI_MISO
BA9
APU_SPI_MOSI
BB10
APU_SPI_WP#
BA10
APU_SPI_HOLD#
BC10
APU_SPI_CS1#
BC9
BA8
Internal Pull-down required by SW
BA6
Internal Pull-down required by SW
BD8
UART_0_ARXD_DTXD
BA16
UART_0_ATXD_DRXD
BB18
BC17
BA18
BD18
BC18
BA17
SSD_RST#
BC16
BB19
APU_WL_OFF#
BB16
Internal Pull-down required by SW
T17
12
RC77 10_0402_5%
12
RC78 10_0402_5%
12
RC79 10_0402_5%
12
RC80 10_0402_5%
12
RC81 22_0402_5%
12
RC82 33_0402_5%
12
RC84 10_0402_1%EMI@
EMI
T18
T19
T20
+1.8VALW
RC92 10K_0402_5%@
RC93 10K_0402_5%
RC94 10K_0402_5%
RC96 10K_0402_5%
RC95 10K_0402_5%
RC97 10_0402_5%@EMI@
1
CC33
10P_0402_50V8J
@EMI@
2
12
12
12
12
12
12
EMI
LPC_AD0 [28]
LPC_AD1 [28]
LPC_AD2 [28]
LPC_AD3 [28]
LPC_CLK0_EC [28]
CLKRUN# [28]
SERIRQ [28]
LPC_FRAME# [28]
LPC_RST# [28]
EC_SCI# [28]
KB_RST# [28]
APU_SPI_CLK_R [8]
UART_0_ARXD_DTXD [17]
UART_0_ATXD_DRXD [17]
SSD_RST# [18]
APU_WL_OFF# [17]
APU_SPI_MOSI
APU_SPI_MISO
APU_SPI_WP#
APU_SPI_HOLD#
APU_SPI_CS1#
APU_SPI_CLK
LPC_RST#
KB_RST#
12
RC83 100K_0402_5%@
12
CC29 150P_0402_50V8J
12
RC85 10K_0402_5%@
8MB SPI ROM
UC2
APU_SPI_CS1#
1
APU_SPI_MISO
APU_SPI_WP# APU_SPI_CLK_R
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
GD25LB64CSIGR SOP 8P
HOLD#(IO3)
DI(IO0)
8
VCC
APU_SPI_HOLD#
7
6
CLK
APU_SPI_MOSI
5
+1.8VALW
1
2
+3VS
CC32
0.1U_0201_10V6K
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
For Compal DFB review
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
D
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
FP5 SATA/CLK/USB/SPI
FP5 SATA/CLK/USB/SPI
FP5 SATA/CLK/USB/SPI
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
Custom
Custom
Custom
LA-H091P
LA-H091P
LA-H091P
Date: Sheet
Date: Sheet
Date: Sheet
E
9 41Monday, December 17, 2018
9 41Monday, December 17, 2018
9 41Monday, December 17, 2018
1.0
1.0
1.0
of
of
of
A
B
C
D
E
Main Func = CPU
+1.2V
1 1
CC36
22U_0603_6.3V6M
CC35
22U_0603_6.3V6M
1
1
2
2
All BU(on bottom side under SOC)
CC52
CC37
22U_0603_6.3V6M
10U_0402_6.3V6M
1
1
2
2
10U_0402_6.3V6M
CC38
CC91
10U_0402_6.3V6M
1
2
@
CC92
10U_0402_6.3V6M
CC39
10U_0402_6.3V6M
CC40
1
1
2
2
@
10U_0402_6.3V6M
1
1
2
2
CC41
10U_0402_6.3V6M
1
2
CC87
10U_0402_6.3V6M
CC42
10U_0402_6.3V6M
1
2
CC88
10U_0402_6.3V6M
CC89
1
2
@
10U_0402_6.3V6M
1
1
2
2
@
@
CC43
1U_0201_6.3V6M
CC90
10U_0402_6.3V6M
1
1
2
2
@
CC45
180P_0402_50V8J
CC44
1U_0201_6.3V6M
1
1
2
2
Across VDDIO & VSS split.
CC46
180P_0402_50V8J
CC47
1
2
180P_0402_50V8J
1
1
2
2
.22U 6.3V K X5R 0402
CC48
.22U 6.3V K X5R 0402
1
2
CC49
CC50
.22U 6.3V K X5R 0402
CC51
1
2
.22U 6.3V K X5R 0402
1
2
+APU_CORE_SOC
TDC :10A
EDC: 13A
+1.2V
+0.8VS
+VDDP_ALW
CC62
CC56
1U_0201_6.3V6M
CC55
CC53
22U_0603_6.3V6M
1
2 2
2
1U_0201_6.3V6M
CC54
22U_0603_6.3V6M
1
2
1
1
2
2
1U_0201_6.3V6M
CC57
1U_0201_6.3V6M
1
2
1
1
2
2
CC60
1U_0201_6.3V6M
1
2
CC59
1U_0201_6.3V6M
CC58
1U_0201_6.3V6M
CC61
1U_0201_6.3V6M
1
1
2
2
CC63
220P_0201_25V7K
1
2
1U_0201_6.3V6M
CC64
22U_0603_6.3V6M
1
1
2
2
+0.8VALW
+1.8VS
1 2
CC67
CC65
1U_0201_6.3V6M
CC66
1U_0201_6.3V6M
1
1
2
2
RC101 0_0402_5%@
VDDIO_AUDIO
1
CC68
10U_0402_6.3V6M
2
CC83
CC69
1U_0201_6.3V6M
2
2
1
1
1
1
CC86
CC84
1U_0201_6.3V6M
1U_0201_6.3V6M
@
2
2
TDC :6A
10U_0402_6.3V6M
BO BU
+1.8VALW +3VS+1.8VS
CC70
22U_0603_6.3V6M
1
1
@
2
2
3 3
BO BU BO BU
CC72
1U_0201_6.3V6M
CC71
1U_0201_6.3V6M
1
2
EC_CLEAR_CMOS#[28]
CC73
22U_0603_6.3V6M
1
2
RC106 0_0402_5%@
C1
1U_0201_6.3V6M
1
2
1 2
1
2
0.22U_0402_6.3V6K
+3VALW
CC78
CC74
1U_0201_6.3V6M
CC75
22U_0603_6.3V6M
CC76
1U_0201_6.3V6M
CC77
1
@
2
1U_0201_6.3V6M
1
1
2
2
10U_0402_6.3V6M
1
2
CC80
1U_0201_6.3V6M
CC79
1U_0201_6.3V6M
1
1
2
2
Note : Cap placemet need to close APU
+RTC_APU
RC107 10K_0402_5%
@
12
1
CLRP1
CC99
@
SHORT PADS
2
1 2
3
CC81
2
AP2138N-1.5TRG1_SOT23-3
0.22U_0402_6.3V6K
1
2
1.5VW>=15mils
UC11
Vout
GND
Vin
W>=15mils
+RTCBATT
1
1U_0201_6.3V6M
12
CC82
+0.8VALW
+3VALW
+3VS
+1.8VALW
VDDIO_AUDIO
+1.8VS
+0.8VS
+RTC_APU
TDC :0.2A
TDC :0.25A
TDC :2A
TDC :0.5A
TDC :0.25A
TDC :1A
TDC :4A
TDC :4.5uA
W18
W20
W28
W32
AA20
AA23
AA26
AA28
AA32
AC20
AC22
AC25
AC28
AD23
AD26
AD28
AD32
AE20
AE22
AE25
AE28
AF23
AF26
AF28
AF32
AG20
AG22
AG25
AG28
AJ20
AJ23
AJ26
AJ28
AJ32
AK28
AL28
AL32
AP12
AL18
AM17
AL20
AM19
AL19
AM18
AL17
AM16
AL14
AL15
AM14
AL13
AM12
AM13
AN12
AN13
AT11
M15
M18
M19
N16
N18
N20
P17
P19
R18
R20
T19
U18
U20
V19
Y19
T32
V28
Y22
Y25
Y28
UC1F
@
VDDCR_SOC_1
VDDCR_SOC_2
VDDCR_SOC_3
VDDCR_SOC_4
VDDCR_SOC_5
VDDCR_SOC_6
VDDCR_SOC_7
VDDCR_SOC_8
VDDCR_SOC_9
VDDCR_SOC_10
VDDCR_SOC_11
VDDCR_SOC_12
VDDCR_SOC_13
VDDCR_SOC_14
VDDCR_SOC_15
VDDCR_SOC_16
VDDCR_SOC_17
VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35
VDDIO_MEM_S3_36
VDDIO_MEM_S3_37
VDDIO_MEM_S3_38
VDDIO_MEM_S3_39
VDDIO_MEM_S3_40
VDDIO_AUDIO
VDD_33_1
VDD_33_2
VDD_18_1
VDD_18_2
VDD_18_S5_1
VDD_18_S5_2
VDD_33_S5_1
VDD_33_S5_2
VDDP_S5_1
VDDP_S5_2
VDDP_S5_3
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDBT_RTC_G
FP5_BGA1140~D
POWER
FP5 REV 0.90
PART 6 OF 13
VDDCR_1
VDDCR_2
VDDCR_3
VDDCR_4
VDDCR_5
VDDCR_6
VDDCR_7
VDDCR_8
VDDCR_9
VDDCR_10
VDDCR_11
VDDCR_12
VDDCR_13
VDDCR_14
VDDCR_15
VDDCR_16
VDDCR_17
VDDCR_18
VDDCR_19
VDDCR_20
VDDCR_21
VDDCR_22
VDDCR_23
VDDCR_24
VDDCR_25
VDDCR_26
VDDCR_27
VDDCR_28
VDDCR_29
VDDCR_30
VDDCR_31
VDDCR_32
VDDCR_33
VDDCR_34
VDDCR_35
VDDCR_36
VDDCR_37
VDDCR_38
VDDCR_39
VDDCR_40
VDDCR_41
VDDCR_42
VDDCR_43
VDDCR_44
VDDCR_45
VDDCR_46
VDDCR_47
VDDCR_48
VDDCR_49
VDDCR_50
VDDCR_51
VDDCR_52
VDDCR_53
VDDCR_54
VDDCR_55
VDDCR_56
VDDCR_57
VDDCR_58
VDDCR_59
VDDCR_60
VDDCR_61
VDDCR_62
VDDCR_63
VDDCR_64
VDDCR_65
VDDCR_66
VDDCR_67
VDDCR_68
VDDCR_69
VDDCR_70
VDDCR_71
VDDCR_72
VDDCR_73
VDDCR_74
VDDCR_75
VDDCR_76
VDDCR_77
VDDCR_78
VDDCR_79
VDDCR_80
VDDCR_81
VDDCR_82
VDDCR_83
G7
G10
G12
G14
H8
H11
H15
K7
K12
K14
L8
M7
M10
N14
P7
P10
P13
P15
R8
R14
R16
T7
T10
T13
T15
T17
U14
U16
V13
V15
V17
W7
W10
W14
W16
Y8
Y13
Y15
Y17
AA7
AA10
AA14
AA16
AA18
AB13
AB15
AB17
AB19
AC14
AC16
AC18
AD7
AD10
AD13
AD15
AD17
AD19
AE8
AE14
AE16
AE18
AF7
AF10
AF13
AF15
AF17
AF19
AG14
AG16
AG18
AH13
AH15
AH17
AH19
AJ7
AJ10
AJ14
AJ16
AJ18
AK13
AK15
AK17
AK19
TDC: 35A
EDC: 45A
+APU_CORE
4 4
Security Classification
Security Classification
For Compal DFB review
A
B
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
FP4 PWR
FP4 PWR
Document Number Re v
Document Number Re v
Document Number Re v
FP4 PWR
LA-H091P
LA-H091P
LA-H091P
E
of
of
of
10 41Monday, December 17, 2018
10 41Monday, December 17, 2018
10 41Monday, December 17, 2018
1.0
1.0
1.0
A
B
C
D
E
Main Func = CPU
@
@
1 1
2 2
3 3
UC1G
N12
VSS_316
A3
VSS_1
A5
VSS_2
A7
VSS_3
A10
VSS_4
A12
VSS_5
A14
VSS_6
A16
VSS_7
A19
VSS_8
A21
VSS_9
A23
VSS_10
A26
VSS_11
A30
VSS_12
C3
VSS_13
C32
VSS_14
D16
VSS_15
D18
VSS_16
D20
VSS_17
E7
VSS_18
E8
VSS_19
E10
VSS_20
E11
VSS_21
E12
VSS_22
E13
VSS_23
E14
VSS_24
E15
VSS_25
E16
VSS_26
E18
VSS_27
E19
VSS_28
E20
VSS_29
E21
VSS_30
E22
VSS_31
E23
VSS_32
E25
VSS_33
E26
VSS_34
E27
VSS_35
F5
VSS_36
F28
VSS_37
G1
VSS_38
G5
VSS_39
G16
VSS_40
G19
VSS_41
G21
VSS_42
G23
VSS_43
G26
VSS_44
G28
VSS_45
G32
VSS_46
H5
VSS_47
H13
VSS_48
H18
VSS_49
H20
VSS_50
H22
VSS_51
H25
VSS_52
H28
VSS_53
K1
VSS_54
K5
VSS_55
K16
VSS_56
K19
VSS_57
K21
VSS_58
K22
VSS_59
K26
VSS_60
K28
VSS_61
FP5_BGA1140~D
GND
FP5 REV 0.90
PART 7 OF 13
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
K32
L5
L13
L15
L18
L20
L25
L28
M1
M5
M12
M21
M23
M26
M28
M32
N4
N5
N8
N11
N13
N15
N17
N19
N22
N25
N28
P1
P5
P14
P16
P18
P20
P23
P26
P28
P32
R5
R11
R12
R13
R15
R17
R19
R22
R25
R28
R30
T1
T5
T14
T16
T18
T20
T23
T26
T28
U13
U15
U17
U19
V5
W13
W15
W17
W19
W23
W26
AA13
AA15
AA17
AA19
AB14
AB16
AB18
AB20
AC11
AC12
AC13
AC15
AC17
AC19
AD14
AD16
AD18
AD20
AE11
AE12
AE13
AE15
AE17
AE19
AF14
AF16
AF18
AF20
UC1H
V8
VSS_124
V11
VSS_125
V12
VSS_126
V14
VSS_127
V16
VSS_128
V18
VSS_129
V20
VSS_130
V22
VSS_131
V25
VSS_132
W1
VSS_133
W5
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
Y5
VSS_141
Y11
VSS_142
Y12
VSS_143
Y14
VSS_144
Y16
VSS_145
Y18
VSS_146
Y20
VSS_147
AA1
VSS_148
AA5
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
AC5
VSS_158
AC8
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
AD1
VSS_166
AD5
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
AE5
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
AF1
VSS_179
AF5
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
AG5
VSS_185
FP5_BGA1140~D
@
FP5 REV 0.90
PART 8 OF 13
GND
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
AG8
AG11
AG12
AG13
AG15
AG17
AG19
AH14
AH16
AH18
AH20
AJ1
AJ5
AJ13
AJ15
AJ17
AJ19
AK5
AK8
AK11
AK12
AK14
AK16
AK18
AK20
AK22
AK25
AL1
AL5
AL7
AL10
AL12
AL16
AL23
AL26
AM5
AM8
AM15
AM20
AM22
AM25
AM28
AN1
AN5
AN7
AN10
AN15
AN18
AN21
AN23
AN26
AN28
AN32
AP5
AP8
AP13
AP15
AP18
AP20
AP25
AP28
AR1
AR12
AR14
AR16
AR19
AR21
AR26
AR28
AR32
AU11
AU13
AU15
AU18
AU20
AU22
AU25
AU28
AV10
AV12
AV14
AV16
AV19
AV21
AV23
AV26
AV28
AV32
AW28
AY10
AY11
AY12
AY13
AY14
AY15
AY16
AY18
AY19
AY20
AY21
AY22
AY23
AY25
AY26
AY27
BB20
BB32
BD10
BD12
BD14
UC1K
AR5
VSS_248
AR7
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
AU5
VSS_258
AU8
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
AV1
VSS_268
AV5
VSS_269
AV7
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
AW5
VSS_281
VSS_282
AY6
VSS_283
AY7
VSS_284
AY8
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
BB1
VSS_302
VSS_303
VSS_304
BD3
VSS_305
BD7
VSS_306
VSS_307
VSS_308
VSS_309
FP5_BGA1140~D
@
GND/RSVD
FP5 REV 0.90
PART 11 OF 13
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
RSVD_1
RSVD_5
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_22
RSVD_23
RSVD_30
RSVD_31
RSVD_37
RSVD_44
RSVD_49
RSVD_50
RSVD_57
RSVD_58
RSVD_59
RSVD_60
RSVD_69
RSVD_70
RSVD_71
RSVD_74
RSVD_75
RSVD_78
RSVD_79
RSVD_80
RSVD_81
RSVD_82
RSVD_83
RSVD_87
RSVD_88
RSVD_14
RSVD_84
RSVD_85
RSVD_86
BD16
BD19
BD21
BD23
BD26
BD30
B20
G3
J20
K3
K6
K20
M3
M6
M13
P6
P22
T3
T6
T29
W6
W21
W22
Y21
Y27
AA3
AA6
AC29
AD3
AD6
AF3
AF6
AF30
AJ6
AJ24
AK23
AK27
AL3
AN29
AN31
M14
AL6
AL11
AN16
T11
AC7
Y10
W11
W12
V10
AA12
AC10
UC1M @
A18
CAM0_CSI2_CLOCKP
C18
CAM0_CSI2_CLOCKN
A15
CAM0_CSI2_DATAP0
C15
CAM0_CSI2_DATAN0
B16
CAM0_CSI2_DATAP1
C16
CAM0_CSI2_DATAN1
C19
CAM0_CSI2_DATAP2
B18
CAM0_CSI2_DATAN2
B17
CAM0_CSI2_DATAP3
D17
CAM0_CSI2_DATAN3
D12
CAM1_CSI2_CLOCKP
B12
CAM1_CSI2_CLOCKN
C13
CAM1_CSI2_DATAP0
A13
CAM1_CSI2_DATAN0
B11
CAM1_CSI2_DATAP1
C12
CAM1_CSI2_DATAN1
J13
RSVD_6
FP5_BGA1140~D
UC1L
RSVD_32
RSVD_66
Y9
RSVD_55
RSVD_56
RSVD_47
RSVD_48
V9
RSVD_38
RSVD_39
RSVD_64
RSVD_68
FP5_BGA1140~D
RSVD
FP5 REV 0.90
PART 12 OF 13
CAMERAS
FP5 REV 0.90
PART 13 OF 13
AA9
RSVD_62
AA8
RSVD_61
AC6
RSVD_65
AD11
RSVD_72
AC9
RSVD_67
AA11
RSVD_63
T12
RSVD_33
AD12
RSVD_73
Y6
RSVD_53
Y7
RSVD_54
W8
RSVD_45
W9
RSVD_46
CAM0_CLK
CAM0_I2C_SCL
CAM0_I2C_SDA
CAM0_SHUTDOWN
CAM1_CLK
CAM1_I2C_SCL
CAM1_I2C_SDA
CAM1_SHUTDOWN
CAM_PRIV_LED
CAM_IR_ILLU
B15
D15
C14
B13
B10
A11
C11
D11
D13
D10
4 4
Security Classification
Security Classification
Security Classification
2018/08/24 2018/05/25
2018/08/24 2018/05/25
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
2018/08/24 2018/05/25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
Compal Electronics, Inc.
FP5 GND
FP5 GND
FP5 GND
LA-H091P
LA-H091P
LA-H091P
E
1.0
1.0
1.0
11 41Monday, December 17, 2018
11 41Monday, December 17, 2018
11 41Monday, December 17, 2018
For Compal DFB review
A
Memory Down
B
C
D
E
DDR_A_DQ[63..0]
DDR_A_DM[7..0]
1 1
+1.2V
RD1 1K_0402_5%
+0.6VS
1 2
1 2
MD@
@
RD2 39_0402_5%
+1.2V
CD3 0.1U_0201_10V6K
CD4 0.1U_0201_10V6K
DDR_A_DQ[63..0] [5]
DDR_A_DM[7..0] [5]
1 2
MD@
1 2
MD@
1 2
RD28 39_0402_5%
MD@
1 2
RD29 39_0402_5%
MD@
DDR_A_ALERT#
DDR_A_PAR
DDR_A_CLK0
DDR_A_CLK0#
+1.2V
0.1U_0201_10V6K
2
@
CD5
1
0.1U_0201_10V6K
2
2 2
VREF traces should be at least 20mils wide
20mils spacing to other signals
3 3
4 4
CD6
MD@
1
Memory Side
RD32
1K_0402_1%
MD@
1 2
RD37
1K_0402_1%
MD@
1 2
1
CD8
MD@
2
DDR_A_DQS4#[5]
DDR_A_DQS4[5]
DDR_A_DQS5#[5]
DDR_A_DQS5[5]
RD40 240_0201_1%
+0.6V_DDRA_VREFCA
2
CD7
0.1U_0201_10V6K
MD@
1
.047U_0402_16V7K
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_WE# DDR_A_WE#
DDR_A_BA0
DDR_A_BA1
DDR_A_DM4
DDR_A_DM5
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CKE0
DDR_A_ODT0 DDR_A_ODT0
DDR_A_CS0# DDR_A_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_RST#
1 2
MD@
DDR_A_BG0
DDR_A_ALERT#
DDR_A_PAR
+2.5V
+0.6V_DDRA_VREFCA +0.6V_DDRA_VREFCA
.047U_0402_16V7K
1
CD2
MD@
DDR_A_MA0[5]
DDR_A_MA1[5]
DDR_A_MA2[5]
2
DDR_A_MA3[5]
DDR_A_MA4[5]
DDR_A_MA5[5]
DDR_A_MA6[5]
DDR_A_MA7[5]
DDR_A_MA8[5]
DDR_A_MA9[5]
DDR_A_MA10[5]
DDR_A_MA11[5]
DDR_A_MA12[5]
DDR_A_MA13[5]
DDR_A_WE#[5]
DDR_A_BA0[5]
DDR_A_BA1[5]
DDR_A_CLK0[5]
DDR_A_CLK0#[5]
DDR_A_CKE0[5]
DDR_A_ODT0[5]
DDR_A_CS0#[5]
DDR_A_RAS#[5]
DDR_A_CAS#[5]
DDR_A_DQS0#[5]
DDR_A_DQS0[5]
DDR_A_DQS1#[5]
DDR_A_DQS1[5]
DDR_A_RST#[5]
RD35 240_0201_1%
DDR_A_ACT#[5]
DDR_A_BG0[5]
DDR_A_ALERT#[5]
DDR_A_PAR[5]
1 2
MD@
DDR_A_DM0
DDR_A_DM1
+2.5V
UD3
M1
VREFCA
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
A14/WE
N2
BA0
N8
BA1
E2
DMU/DBIU
E7
DML/DBIL
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
L8
RAS
M8
CAS
A7
DQSU_c
B7
DQSU_t
F3
DQSL_c
G3
DQSL_t
P1
RESET
F9
ZQ
L3
ACT
M2
BG0
N9
TEN
P9
ALERT
T3
PAR
T7
NC
B1
VPP
R9
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
@
DDR_A_DQ43
G2
DQL0
DDR_A_DQ44
F7
DQL1
DDR_A_DQ47
H3
DQL2
DDR_A_DQ45
H7
DQL3
DDR_A_DQ46
H2
DQL4
DDR_A_DQ40
H8
DQL5
DDR_A_DQ42
J3
DQL6
DDR_A_DQ41
J7
DQL7
DDR_A_DQ38
A3
DQU0
DDR_A_DQ36
B8
DQU1
DDR_A_DQ34
C3
DQU2
DDR_A_DQ37
C7
DQU3
DDR_A_DQ39
C2
DQU4
DDR_A_DQ32
C8
DQU5
DDR_A_DQ35
D3
DQU6
DDR_A_DQ33
D7
DQU7
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
1 2
RD38 0_0201_5%DDP@
DDR_A_BG1_R
+1.2V
UD1
M1
VREFCA
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
A14/WE
N2
BA0
N8
BA1
E2
DMU/DBIU
E7
DML/DBIL
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
L8
RAS
M8
CAS
A7
DQSU_c
B7
DQSU_t
F3
DQSL_c
G3
DQSL_t
P1
RESET
F9
ZQ
L3
ACT
M2
BG0
N9
TEN
P9
ALERT
T3
PAR
T7
NC
B1
VPP
R9
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
@
DDR_A_DQ14
G2
DQL0
DDR_A_DQ12
F7
DQL1
DDR_A_DQ11
H3
DQL2
DDR_A_DQ9
H7
DQL3
DDR_A_DQ10
H2
DQL4
DDR_A_DQ13
H8
DQL5
DDR_A_DQ15
J3
DQL6
DDR_A_DQ8
J7
DQL7
DDR_A_DQ6
A3
DQU0
DDR_A_DQ4
B8
DQU1
DDR_A_DQ3
C3
DQU2
DDR_A_DQ5
C7
DQU3
DDR_A_DQ7
C2
DQU4
DDR_A_DQ1
C8
DQU5
DDR_A_DQ2
D3
DQU6
DDR_A_DQ0
D7
DQU7
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
+0.6V_DDRA_VREFCA+0.6V_DDRA_VREFCA
CD9
.047U_0402_16V7K
1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
MD@
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_BA0
DDR_A_BA1
DDR_A_DM6
DDR_A_DM7
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CKE0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_DQS6#[5]
DDR_A_DQS6[5]
DDR_A_DQS7#[5]
DDR_A_DQS7[5]
DDR_A_RST#
1 2
RD41 240_0201_1%
MD@
DDR_A_ACT#DDR_A_ACT#
DDR_A_BG0
DDR_A_ALERT#
DDR_A_PAR
+2.5V
+1.2V
1 2
RD33 0_0201_5%DDP@
DDR_A_BG1_R DDR_A_BG1_R
UD4
M1
VREFCA
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
A14/WE
N2
BA0
N8
BA1
E2
DMU/DBIU
E7
DML/DBIL
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
L8
RAS
M8
CAS
A7
DQSU_c
B7
DQSU_t
F3
DQSL_c
G3
DQSL_t
P1
RESET
F9
ZQ
L3
ACT
M2
BG0
N9
TEN
P9
ALERT
T3
PAR
T7
NC
B1
VPP
R9
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
@
UD2
M1
.047U_0402_16V7K
1
DDR_A_MA0
CD1
DDR_A_MA1
MD@
DDR_A_MA2
2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_WE#
DDR_A_BA0
DDR_A_BA1
DDR_A_DM2
DDR_A_DM3
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CKE0
DDR_A_ODT0
DDR_A_CS0#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_DQS2#[5]
DDR_A_DQS2[5]
DDR_A_DQS3#[5]
DDR_A_DQS3[5]
DDR_A_RST#
1 2
RD36 240_0201_1%
MD@
DDR_A_ACT#
DDR_A_BG0
DDR_A_ALERT#
DDR_A_PAR
+2.5V
DDR_A_DQ62
G2
DQL0
DDR_A_DQ60
F7
DQL1
DDR_A_DQ59
H3
DQL2
DDR_A_DQ61
H7
DQL3
DDR_A_DQ63
H2
DQL4
DDR_A_DQ57
H8
DQL5
DDR_A_DQ58
J3
DQL6
DDR_A_DQ56
J7
DQL7
DDR_A_DQ54
A3
DQU0
DDR_A_DQ53
B8
DQU1
DDR_A_DQ55
C3
DQU2
DDR_A_DQ52
C7
DQU3
DDR_A_DQ51
C2
DQU4
DDR_A_DQ49
C8
DQU5
DDR_A_DQ50
D3
DQU6
DDR_A_DQ48
D7
DQU7
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
1 2
RD39 0_0201_5%DDP@
DDR_A_BG1_R
+1.2V
VREFCA
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
A14/WE
N2
BA0
N8
BA1
E2
DMU/DBIU
E7
DML/DBIL
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
L8
RAS
M8
CAS
A7
DQSU_c
B7
DQSU_t
F3
DQSL_c
G3
DQSL_t
P1
RESET
F9
ZQ
L3
ACT
M2
BG0
N9
TEN
P9
ALERT
T3
PAR
T7
NC
B1
VPP
R9
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
@
DDR_A_DQ30
G2
DQL0
DDR_A_DQ29
F7
DQL1
DDR_A_DQ27
H3
DQL2
DDR_A_DQ25
H7
DQL3
DDR_A_DQ31
H2
DQL4
DDR_A_DQ28
H8
DQL5
DDR_A_DQ26
J3
DQL6
DDR_A_DQ24
J7
DQL7
DDR_A_DQ18
A3
DQU0
DDR_A_DQ21
B8
DQU1
DDR_A_DQ23
C3
DQU2
DDR_A_DQ16
C7
DQU3
DDR_A_DQ19
C2
DQU4
DDR_A_DQ20
C8
DQU5
DDR_A_DQ22
D3
DQU6
DDR_A_DQ17
D7
DQU7
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
+2.5V +2.5V +2.5V +2.5V
MD@
1
2
1U_0201_6.3V6M
RD34 0_0201_5%DDP@
CD42
1
MD@
2
1 2
CD43
1U_0201_6.3V6M
MD@
+1.2V
CD44
10U 6.3V M X5R 0402
1
2
Closed to UD1 Closed to UD2 Closed to UD3
+1.2V
CD10 0.22U_0402_6.3V6K
CD11 0.22U_0402_6.3V6K
CD12 0.22U_0402_6.3V6K
1
1
MD@
MD@
MD@
2
2
+1.2V
CD33 0.22U_0402_6.3V6K
CD35 0.22U_0402_6.3V6K
CD37 0.22U_0402_6.3V6K
CD39 0.22U_0402_6.3V6K
CD41 0.22U_0402_6.3V6K
CD45
1U_0201_6.3V6M
1
1
MD@
MD@
2
2
+0.6VS
1 2
RD3 39_0402_5%MD@
1 2
RD4 39_0402_5%MD@
1 2
RD5 39_0402_5%MD@
1 2
RD6 39_0402_5%MD@
1 2
RD7 39_0402_5%MD@
1 2
RD8 39_0402_5%MD@
1 2
RD9 39_0402_5%MD@
1 2
RD10 39_0402_5%MD@
1 2
RD11 39_0402_5%MD@
1 2
RD12 39_0402_5%MD@
1 2
RD13 39_0402_5%MD@
1 2
RD14 39_0402_5%MD@
1 2
RD15 39_0402_5%MD@
1 2
RD16 39_0402_5%MD@
1 2
RD17 39_0402_5%MD@
1 2
RD18 39_0402_5%MD@
1 2
RD19 39_0402_5%MD@
1 2
RD20 39_0402_5%MD@
1 2
RD21 39_0402_5%MD@
1 2
RD22 39_0402_5%MD@
1 2
RD23 39_0402_5%MD@
1 2
RD24 39_0402_5%MD@
1 2
RD25 39_0402_5%MD@
1 2
RD26 39_0402_5%MD@
1 2
RD27 39_0402_5%DDP@
1 2
RD31 0_0201_5%SDP@
DRAM DOWN DECOUPLING
CD19 0.22U_0402_6.3V6K
CD20 0.22U_0402_6.3V6K
CD15 0.22U_0402_6.3V6K
CD16 0.22U_0402_6.3V6K
CD17 0.22U_0402_6.3V6K
CD18 0.22U_0402_6.3V6K
1
1
1
1
1
MD@
@
MD@
MD@
MD@
MD@
2
2
2
2
2
+0.6VS
CD47
10U 6.3V M X5R 0402
CD48
1U_0201_6.3V6M
1
MD@
2
MD@
1 2
1 2
1 2
1 2
1 2
CD13 0.22U_0402_6.3V6K
CD14 0.22U_0402_6.3V6K
1
1
1
@
2
2
2
MD@
MD@
MD@
MD@
MD@
CD46
1U_0201_6.3V6M
1
MD@
2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_ODT0
DDR_A_CS0#
DDR_A_CKE0
DDR_A_ACT#
DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
DDR_A_BG1_R
CD21 0.22U_0402_6.3V6K
CD22 0.22U_0402_6.3V6K
1
1
1
MD@
MD@
MD@
2
2
2
+0.6V_DDRA_VREFCA
1U_0201_6.3V6M
1
MD@
2
RD30 0_0201_5%DDP@
CD23 0.22U_0402_6.3V6K
CD24 0.22U_0402_6.3V6K
CD25 0.22U_0402_6.3V6K
CD26 0.22U_0402_6.3V6K
1
1
1
1
MD@
MD@
MD@
MD@
2
2
2
2
CD34 0.1U_0201_10V6K
CD36 0.1U_0201_10V6K
CD38 0.1U_0201_10V6K
CD40 0.1U_0201_10V6K
CD49
CD50
10U 6.3V M X5R 0402
1
MD@
2
1 2
CD27 0.22U_0402_6.3V6K
1
MD@
2
1 2
MD@
1 2
MD@
1 2
MD@
1 2
MD@
1
MD@
2
Closed to UD4
+0.6VS
1U_0201_6.3V6M
DDR_A_BG1 [5]
CD32 0.22U_0402_6.3V6K
CD28 0.22U_0402_6.3V6K
CD29 0.22U_0402_6.3V6K
CD30 0.22U_0402_6.3V6K
CD31 0.22U_0402_6.3V6K
1
1
1
1
1
@
MD@
MD@
MD@
2
2
2
2
2
+1.2V
CD52
1U_0201_6.3V6M
CD51
CD53
10U 6.3V M X5R 0402
1
1
MD@
MD@
2
2
Security Classification
Security Classification
For Compal DFB review
A
B
C
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
D
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDR4_CHA Onboard
DDR4_CHA Onboard
DDR4_CHA Onboard
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
LA-H091P
LA-H091P
LA-H091P
Date: She et
Date: She et
Date: She et
E
12 41Monday, December 17, 2018
12 41Monday, December 17, 2018
12 41Monday, December 17, 2018
1.0
1.0
1.0
of
of
of
Main Func = DIMM2
A
B
C
D
E
JDIMM1A
DDR_B_CLK0[5]
DDR_B_CLK0#[5]
DDR_B_CLK1[5]
DDR_B_CLK1#[5]
DDR_B_CKE0[5]
+1.2V
1
2
1
2
ESD
CD56
10U 6.3V M X5R 0402
CD82
10U 6.3V M X5R 0402
RF@
DDR_B_CKE1[5]
DDR_B_CS0#[5]
DDR_B_CS1#[5]
DDR_B_ODT0[5]
DDR_B_ODT1[5]
DDR_B_BG0[5]
DDR_B_BG1[5]
DDR_B_BA0[5]
DDR_B_BA1[5]
DDR_B_WE#[5]
DDR_B_CAS#[5]
DDR_B_RAS#[5]
DDR_B_ACT#[5]
DDR_B_PAR[5]
DDR_B_ALERT#[5]
DDR_B_EVENT#[5]
DDR_B_RST#[5]
I2C_2_SDA[8,14]
I2C_2_SCL[8,14]
+3VS
CD57
10U 6.3V M X5R 0402
CD58
10U 6.3V M X5R 0402
1
1
2
2
CD83
10U 6.3V M X5R 0402
CD84
10U 6.3V M X5R 0402
1
1
RF@
RF@
2
2
1 1
2 2
DDR_B_RST#
3 3
4 4
+1.2V
@
10U 6.3V M X5R 0402
1
2
1 2
CD69
100P_0402_50V8J
CD55
10U 6.3V M X5R 0402
CD54
1
2
ESD@
RF@
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS0#
DDR_B_CS1#
DDR_B_ODT0
DDR_B_ODT1
DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_WE#
DDR_B_CAS#
DDR_B_RAS#
DDR_B_ACT#
DDR_B_PAR
DDR_B_ALERT#
DDR_B_EVENT#
DDR_B_RST#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
CD59
10U 6.3V M X5R 0402
1
2
@
CD61
1U_0201_6.3V6M
CD60
1U_0201_6.3V6M
12
12
12
RF reserve
CD86
0.1U_0201_10V6K
CD87
CD85
10U 6.3V M X5R 0402
1
RF@
2
0.1U_0201_10V6K
1
1
1
RF@
2
RF@
2
2
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
LOTES_ADDR0206-P001A
ME@
CD62
1U_0201_6.3V6M
1U_0201_6.3V6M
12
0.1U_0201_10V6K
CD88
0.1U_0201_10V6K
1
RF@
2
REVERSE
CD63
CD89
DDR_B_DQ4
8
DQS0(T)
DQS0#(C)
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS1(T)
DQS1#(C)
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS2(T)
DQS2#(C)
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS3(T)
DQS3#(C)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4(T)
DQS4#(C)
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS5(T)
DQS5#(C)
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS6(T)
DQS6#(C)
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS7(T)
DQS7#(C)
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DDR_B_DQ0
7
DDR_B_DQ2
20
DDR_B_DQ6
21
DDR_B_DQ1
4
DDR_B_DQ5
3
DDR_B_DQ7
16
DDR_B_DQ3
17
DDR_B_DQS0
13
DDR_B_DQS0#
11
DDR_B_DQ8
28
DDR_B_DQ9
29
DDR_B_DQ14
41
DDR_B_DQ11
42
DDR_B_DQ12
24
DDR_B_DQ13
25
DDR_B_DQ10
38
DDR_B_DQ15
37
DDR_B_DQS1
34
DDR_B_DQS1#
32
DDR_B_DQ21
50
DDR_B_DQ16
49
DDR_B_DQ23
62
DDR_B_DQ19
63
DDR_B_DQ17
46
DDR_B_DQ20
45
DDR_B_DQ22
58
DDR_B_DQ18
59
DDR_B_DQS2
55
DDR_B_DQS2#
53
DDR_B_DQ25
70
DDR_B_DQ28
71
DDR_B_DQ26
83
DDR_B_DQ27
84
DDR_B_DQ24
66
DDR_B_DQ29
67
DDR_B_DQ30
79
DDR_B_DQ31
80
DDR_B_DQS3
76
DDR_B_DQS3#
74
DDR_B_DQ36
174
DDR_B_DQ33
173
DDR_B_DQ35
187
DDR_B_DQ38
186
DDR_B_DQ37
170
DDR_B_DQ32
169
DDR_B_DQ34
183
DDR_B_DQ39
182
DDR_B_DQS4
179
DDR_B_DQS4#
177
DDR_B_DQ44
195
DDR_B_DQ45
194
DDR_B_DQ46
207
DDR_B_DQ43
208
DDR_B_DQ41
191
DDR_B_DQ40
190
DDR_B_DQ42
203
DDR_B_DQ47
204
DDR_B_DQS5
200
DDR_B_DQS5#
198
DDR_B_DQ49
216
DDR_B_DQ53
215
DDR_B_DQ54
228
DDR_B_DQ50
229
DDR_B_DQ48
211
DDR_B_DQ52
212
DDR_B_DQ55
224
DDR_B_DQ51
225
DDR_B_DQS6
221
DDR_B_DQS6#
219
DDR_B_DQ57
237
DDR_B_DQ60
236
DDR_B_DQ59
249
DDR_B_DQ62
250
DDR_B_DQ61
232
DDR_B_DQ56
233
DDR_B_DQ58
245
DDR_B_DQ63
246
DDR_B_DQS7
242
DDR_B_DQS7#
240
DDR_B_DQS0 [5]
DDR_B_DQS0# [5]
DDR_B_DQS1 [5]
DDR_B_DQS1# [5]
DDR_B_DQS2 [5]
DDR_B_DQS2# [5]
DDR_B_DQS3 [5]
DDR_B_DQS3# [5]
DDR_B_DQS4 [5]
DDR_B_DQS4# [5]
DDR_B_DQS5 [5]
DDR_B_DQS5# [5]
DDR_B_DQS6 [5]
DDR_B_DQS6# [5]
DDR_B_DQS7 [5]
DDR_B_DQS7# [5]
+1.2V
CD64
1U_0201_6.3V6M
CD65
1U_0201_6.3V6M
12
12
@
CD67
1U_0201_6.3V6M
CD66
1U_0201_6.3V6M
12
1
12
+
@
CD68
330U_D3_2.5VY_R6M
2
DDR_B_DQ[0..63]
DDR_B_DM[0..7]
DDR_B_MA[0..13]
Layout Note:
Place near JDIMM1.257,259
+2.5V
CD70
10U 6.3V M X5R 0402
1
1
@
2
2
CD71
10U 6.3V M X5R 0402
DDR_B_DQ[0..63] [5]
DDR_B_DM[0..7] [5]
DDR_B_MA[0..13] [5]
+VREFB_CA
CD72
1U_0201_6.3V6M
1
12
@
2
JDIMM1B
REVERSE
111
VDD1
112
117
118
+3VS
CD81
1000P_0402_50V7K
1
2
+0.6VS
CD73
0.1U_0201_10V6K
123
124
129
130
135
136
255
164
1
2
5
6
9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98
262
Layout Note:
Place near JDIMM1.258
CD75
10U 6.3V M X5R 0402
CD74
1U_0201_6.3V6M
1
1
@
2
2
VDD11
VDD2
VDD12
VDD3
VDD13
VDD4
VDD14
VDD5
VDD15
VDD6
VDD16
VDD7
VDD17
VDD8
VDD18
VDD9
VDD19
VDD10
VDDSPD
VTT
VREFCA
VPP1
VPP2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
GND
LOTES_ADDR0206-P001A
ME@
CD76
10U 6.3V M X5R 0402
1
2
+1.2V+1.2V
141
142
147
148
153
154
159
160
163
258
257
259
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
261
+3VS
2
1
+0.6VS
+2.5V
+1.2V
DIMM Side
+VREFB_CA
CD78
2.2U_0402_6.3V6M
CD77
0.1U_0201_10V6K
2
1
0.1U_0201_10V6K
2
1
+VREFB_CA
CD79
2
1
RD42
1K_0402_1%
1 2
CD80
0.1U_0201_10V6K
RD43
1K_0402_1%
1 2
Security Classification
Security Classification
For Compal DFB review
A
B
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2018/08/24 2018/05/25
2018/08/24 2018/05/25
2018/08/24 2018/05/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDR4 So-DIMM
DDR4 So-DIMM
DDR4 So-DIMM
Document Number Re v
Document Number Re v
Document Number Re v
LA-H091P
LA-H091P
LA-H091P
E
13 41Monday, December 17, 2018
13 41Monday, December 17, 2018
13 41Monday, December 17, 2018
1.0
1.0
1.0
of
of
of
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