Lenovo S530-13 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

S530 (ELZ02)

DIS M/B Schematics Document

Intel Whiskey Lake U Processor with LPDDR3

N17S-LG (Geforce MX150) (23x23mm)

3 3

2018-5-21

LA-G651P

R E V

：

：：

0 . 2

4 4

Security Classification

Issued Date

Compal For Lenovo

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/2/5 2019/2/5

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Cover Page

LA-G651P

0.2

o f

1 52Friday, May 18, 2018

E

5

4

3

2

1

D D

N17S-LG (MX150)

VRAM(GDDR5)*2

PCIe x4 2 Lanes

2GB

eDP Panel

FHD LCD

HDMI CONN

eDP x1 2 Lanes

DDI x1

Channel A/B

(1866 MT/s)

USB3.0

USB2.0

USB3.0

USB2.0

On board X 4

LPDDR3

USB3.0 Connector

(USB charger port)

USB3.0 redriver

TI SN65 LVPE50 2A

Camera

USB3.0 Connector

IO/B

Intel WHL-U_15W

C C

Wireless LAN WIFI /BT combo

NGFF

Type-C DP/USB3 Switch

Type-C Conn

B B

Realtek RTS5455

Touch Pad

PCIE x1

GEN1 : 2.5G

USB2.0 x1

DDI x1

USB 3.0

USB 2.0

I2C

4+2

1528 pin BGA

USB2.0

PCIE x4

HDA

Finger print

SSD CONN

NGFF

Audio Codec

Realtek ALC3240

Int. Speaker

Int. Array Mic x2

MIC B

Combo Jack

IO/B

EC

ENE KB9022

LPC

SPI

SPI ROM

16 MB

Sub-Board

IO/B

USB3.0 *1 Combo Jack *1

A A

Int. KBD

Hall Sensor x1

MIC B

Int. Array Mic x2

Security Classification

Issued Date

Compal For Lenovo

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

BLOCK DIAGRAM

Size

Document Number Re v

Custom

Date : Sheet

Date : Sheet of

LA-G651P

1

2 52Friday, May 18, 2018

0.2

of

1

Voltage Rails

State

S0

S3

S5 S4/AC

power plane

SIGNAL

B+

O

X

SLP_S1#

LOW

HIGH HIGH HIGH

LOW

LOW LOW LOW

LOWLOW

+5VALW

+3VALW

+1.8VALW

+1.05VAL W

O

+1.2V +2.5V

O O

O

X

SLP_S4#SLP_S3# +V+VALWSLP_S5# Clock+VS

HIGHHIGHHIGH

HIGH

LOWLOW

X

ONONON

ON

OFF

A A

B B

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

C C

SMBUS Control Table

SOURCE

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SMB_CLK PCH_SMB_DATA

I2C1_SCL_TS I2C1_SDA_TS

I2C0_SCL_TP

D D

I2C0_SDA_TP

Address

KB9022QD

+3VL

KB9022QD

+3VS

PCH

+3VS

PCH

+3VS

PCH

+3VS

Write Read

VGA

X

V

X X X

0X9E

BATT

V X

X

X X X

CHARGER

V

X X X X

2

+5VS

+3VS

+VCCPLL_ OC

+VCCCORE

+VCCGT

+1.05V_V CCST

+1.05VS_V CCIO

+1.8VS

+1.8V_ME M

X

XX

X

XXX

ONON

ON

LOW

OFF

Thermal Sensor

Reserve

X X X

0X4C

Touch Pad

X

X X

X

V

0X2C

3

BOM Structure Table

Ite m

For DIS DIS@ For UMA UMA@ For GPU GC6 No GPU GC6 For Ke yboard backlight KBL @ No Keyboa rd backlight NOKB L@ For RF RF@ No RF @RF @ For EMI

For ESD No ESD

For Samsung VRAM For Micron VRAM For Hynix VRAM For samsung 4G DRAM S4G @ For samsung 8G DRAM S8G @ For samsu ng 16G DRAM S16 G@ For Hynix 4G DRAM H4G @ For Hynix 8G DRAM

For Micron 4G DRAM For Micron 8G DRAM

X4E for UMA X4E_ UMA X4E for DIS X4E_ DIS For CNVi interface CNV i@ Non CNVi interface NONC NVi @ For XDP CMC@ For Thermal Sensor EX_T HM@ For 8G_16G DRAM CHA @

UC1

SA0000C1510 S IC FJ8068403999819 QQAT W0 1.8G C38 I7@

UC1

SA0000C1610 S IC FJ8068404000016 QQAU W0 1.6G C38 I5@

BOM Structure

GC6 @ NOGC 6@

EMI @ @EM I@No EMI ESD @ @ES D@ ME@Conne ct or S2G @ M2G @ H2G @

H8G @ H16 G@For Hynix 16G DRAM M4G @ M8G @ M16 G@For Micron 16G DRAM

ZZZ

DA8001FP000

PCB 2D5 LA-G651P REV0 M/B 2

CPU MB

ZZZ

PCH

X

V

X X X

TypeC-Mux

X

Reserve

X

V

X

0X5C

HDMI Logo

RO0000003HM

HDMI Logo

4

5

USB 2.0 Port Table

Por t

1

USB2/3 (re-driver) ( I/O BD)

2

USB2/3 (Charger)

3

Type-C

4 5

Camera

6

FP

7 8 9 10

NGFF WLAN+BT(CNVi)

USB 3.0 Port Table

Por t

1

USB2/3 (re-driver) (I/O SB)

2

USB2/3 (for charger)

3

Type-C

4 5 6

PCIE Port Table

Por t

Lan e

1 2 3 4 5 6 7 8

0

9

3

10

2

11

1

12

0

13

0

14

1

15

2

16

3

NGFF WLAN+BT

SSD

GPU

UMA DiscreteEMC/ESD

ZZZ

X4E_UMA@

X4E_UMA

X4EADO38L02

ZZZ

X4E_DIS@

X4E_DIS

X4EADO38L01

LPDDR3 Onboard RAM

ZZZ

X76@ ZZZ

4G

LPDDR3_S4G

8G

X7679138L01

ZZZ

X76@

LPDDR3_S8G

X7679138L04

ZZZ

X76@

LPDDR3_S16G

X7679138L07

45@

16G

X76@

LPDDR3_H4G

X7679138L02

X76@

LPDDR3_H8G

X7679138L05

ZZZ

X76@

LPDDR3_H16G

X7679138L08

X76@

LPDDR3_M4G

X7679138L03

ZZZ

X76@ZZZ

LPDDR3_M8G

X7679138L06

ZZZ

X76@

LPDDR3_M16G

X7679138L09

Security Classification

Compal For Lenovo

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Notes List

Size

Document Number Re v

C

Date: Sheet

LA-G651P

5

3 52Friday, May 18, 2018

0.2

of

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Compal For Lenovo

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2018/2/5 2019/2/5

Deciphered Date

2

Compal Elect ronics, Inc.

Title

Power MAP

Size Document Number Rev

Date : Sheet o f

1

4 52Friday, May 18, 201 8

0.2

5

[ELZ02-PWR Sequence]

4

3

2

1

G3->S0 S0->S3 ->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.05V_MPHYPLL

+1.05V_PRIM_CORE

+1.05V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

C C

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

VCCST

+1.2V_VDDQ/+1.2V_VCCSFR_OC

PM_SLP_S3#

SUSP#

VCCSTG

VCCIO

B B

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

DDR_VTT_PG_CT RL

+0.6VS

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

tPCH01_Min : 9 ms

tPCH06_Min : 200 us

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

tPCH43_Min : 95 ms

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

tPCH18_Min : 90 us

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 10msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

tCPU16 Min : 0 ns

/DS3 DS3S0/

S0->S5

+3VL_RTC

SOC_RTCRST#

B+

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.05V_MPHYPLL

+1.05V_PRIM_CORE

+1.05V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

VCCST

+1.2V_VDDQ/+1.2V_VCCSFR_OC

PM_SLP_S3#

SUSP#

VCCSTG

VCCIO

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

DDR_VTT_PG_CT RL

+0.6VS

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

Security Classification Compal Secret Data

Issued Date

Compal For Lenovo

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/2/5 2019/2/5

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power Sequence

1

5 52Friday, May 1 8, 2018

0.2

A

1 1

2 2

+3VS

B

HDMI

MUX

For HDMI 1.4

C

UC1A

CPU_DP1_N 0<29> CPU_DP1_P0<29> CPU_DP1_N 1<29> CPU_DP1_P1<29> CPU_DP1_N 2<29> CPU_DP1_P2<29> CPU_DP1_N 3<29> CPU_DP1_P3<29>

CPU_DP2_N 0<30> CPU_DP2_P0<30> CPU_DP2_N 1<30> CPU_DP2_P1<30> CPU_DP2_N 2<30> CPU_DP2_P2<30> CPU_DP2_N 3<30> CPU_DP2_P3<30>

EDP_COMP

CPU_DP1_C TRL_CLK<29> CPU_DP1_C TRL_DATA<29>

CPU_DDPC_ CTRL_DATA

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

WHL-U42 _BGA1528

1 of 20

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 EDP_TXN_2 EDP_TXP_2 EDP_TXN_3 EDP_TXP_3

EDP_AUX_N EDP_AUX_P

DISP_UTILS

DDI1_AUX_N DDI1_AUX_P DDI2_AUX_N DDI2_AUX_P DDI3_AUX_N DDI3_AUX_P

GPP_E13/DDPB_HPD0/DISP_MISC0 GPP_E14/DDPC_HPD1/DISP_MISC1 GPP_E15/DPPD_HPD2/DISP_MISC2 GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

AG4 AG3 AG2 AG1 AJ4 AJ3 AJ2 AJ1

AH4 AH3

AM7

AC7 AC6 AD4 AD3 AG7 AG6

CN6 CM6 CP7 CP6 CM7

CK11 CG11 CH11

D

EDP_TXN0 <28> EDP_TXP0 <28>

EC_SCI#

EDP_TXN1 <28> EDP_TXP1 <28>

EDP_AUXN <28> EDP_AUXP <2 8>

CPU_DP2_AUXN <30> CPU_DP2_AUXP <30>

CPU_DP1_H PD <29> CPU_DP2_H PD <30>

EC_SCI# <34> EDP_HPD <28>

ENBKL <28,34> PCH_ENVDD <28> INVPWM <28>

eDP

From eDP

MUX

From HDMI From MUX

EC_SCI#

E

1 2

RC480 10K_04 02_5%

+3VS

B

+1.05VS_VCCSTG

12

RC4 1K_0402_5%

RC6 499_0402_ 1%

If routed MS, PECI requires 18 mils spacing to other signals

CATERR# H_PECI

H_PECI<34>

1 2

RC7 49.9_0402 _1% RC8 49.9_0402 _1% RC9 49.9_0402_1%@

RC10 49.9_0402_ 1%@

12 12 12

12

H_PROCHOT# _R H_THERMT RIP#

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP

EOPIO_RCOMP

UC1D

AA4

CATERR#

AR1

PECI

Y4

PROCHOT#

BJ1

THRMTRIP#

U1

BPM#_0

U2

BPM#_1

U3

BPM#_2

U4

BPM#_3

CE9

GPP_E3/CPU_GP0

CN3

GPP_E7/CPU_GP1

CB34

GPP_B3/CPU_GP2

CC35

GPP_B4/CPU_GP3

BP27

PROC_POPIRCOMP

BW25

PCH_OPIRCOMP

L5

OPCE_RCOMP

N5

OPC_RCOMP

WHL-U42 _BGA1528

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

4 of 20

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI PCH_TDO PCH_TMS

PCH_TRST# PCH_JTAGX

PROC_PREQ# PROC_PRDY#

CPU_XDP_TCK 0

T6

SOC_XDP_TDI

U6

SOC_XDP_TDO

Y5

SOC_XDP_TMS

T5

SOC_XDP_TRST #

AB6

W6

SOC_XDP_TDI

U5

SOC_XDP_TDO

W5

SOC_XDP_TMS

P5

SOC_XDP_TRST #

Y6

CPU_XDP_TCK 0

P6

W2 W1

2017/5/3 2017/6/2

DCI

T2402TP@

DCI

T2403TP@ T2404TP@

Compal Secret Data

Deciphered Date

D

< PU/PD for CMC Debug >

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK 0

1 2

RC11 51_0402_5 %CMC@

1 2

RC12 51_0402_5 %CMC@

1 2

RC13 51_0402_5 %

1 2

RC14 51_0402_5 %

Compal Electronics, Inc.

Title

Size D ocument Number R ev

Date : Sheet of

Compal Electronics, Inc.

WHL-U(1/12)DDI,EDP,MISC,CMC

Custom

+1.05VS_VCCSTG

LA-G651P

E

0.2

6 52Friday, May 18, 2018

0.2

RC436 2.2K_02 01_5%

12

CPU_DDPC_ CTRL_DATA

H_PROCHOT#<34>

< Compensation PU For eDP >

+1.05VS_VCCIO

EDP_COMP

1 2

RC3

3 3

4 4

Trace width=20 mils, Spacing=25mil, Max length=600mils

+1.05V_VCCST

RC5 1K_0402_5%

RC19 4 9.9_0402_1%

1 2

@

24.9_0201_1 %

H_THERMT RIP#

12

CATERR#

Compal For Lenovo

A

5

4

3

2

1

Non- Interleaved Memory

D D

DDR_A_D[16..31]<19>

DDR_A_D[48..63]<19>

DDR_B_D[16..31]<20>

DDR_B_D[48..63]<20>

AN35 AN34 AR35 AR34 AN37 AN36 AR36 AR37 AU35

AU34 AW35 AW34

AU37

AU36 AW36 AW37

BA35

BA34

BC35

BC34

BA37

BA36

BC36

BC37

BE35

BE34

BG35

BG34

BE37

BE36

BG36

BG37

NC1VCC

A

GND

SA00005U600

UC1B

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

DDR0_DQ_15/DDR0_DQ_15

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47 DDR0_DQ_32/DDR1_DQ_0 DDR0_DQ_33/DDR1_DQ_1 DDR0_DQ_34/DDR1_DQ_2 DDR0_DQ_35/DDR1_DQ_3 DDR0_DQ_36/DDR1_DQ_4 DDR0_DQ_37/DDR1_DQ_5 DDR0_DQ_38/DDR1_DQ_6 DDR0_DQ_39/DDR1_DQ_7 DDR0_DQ_40/DDR1_DQ_8 DDR0_DQ_41/DDR1_DQ_9 DDR0_DQ_42/DDR1_DQ_10 DDR0_DQ_43/DDR1_DQ_11 DDR0_DQ_44/DDR1_DQ_12 DDR0_DQ_45/DDR1_DQ_13 DDR0_DQ_46/DDR1_DQ_14 DDR0_DQ_47/DDR1_DQ_15 DDR0_DQ_48/DDR1_DQ_32 DDR0_DQ_49/DDR1_DQ_33 DDR0_DQ_50/DDR1_DQ_34 DDR0_DQ_51/DDR1_DQ_35 DDR0_DQ_52/DDR1_DQ_36 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQ_58/DDR1_DQ_42 DDR0_DQ_59/DDR1_DQ_43 DDR0_DQ_60/DDR1_DQ_44 DDR0_DQ_61/DDR1_DQ_45 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQ_63/DDR1_DQ_47

WHL-U42_BGA1528

UC2

5

4

Y

DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_1/DDR0_CKN_1 DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1

DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2

DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8

DDR0_CAA_1/DDR0_MA_9 DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15 DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1

DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT#

DDR0_CAA_9/DDR0_BG_1

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQSP_7/DDR1_DQSP_5

2 of 20

1

CC1

0.1U_0201_10V6K

@

2

DDR0_CKE_2/NC DDR0_CKE_3/NC

NC/DDR0_ODT_1

NC/DDR0_MA_3 NC/DDR0_MA_4

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ_0 DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CNTL

+3VS+1.2V

12

RC132

100K_0402_5%

V32 V31 T32 T31

U36 U37 U34 U35

AE32 AF32 AE31 AF31

AC37 AC36 AC34 AC35 AA35 AB35 AA37 AA36 AB34 W36 Y31 W34 AA34 AC32

AC31 AB32 Y32

W32 AB31 V34

V35 W35

C27 D27 D31 C31 J35 J34 P34 P35 AP35 AP34 AV34 AV35 BB35 BB34 BF34 BF35

W37 W31 F36 D35 D37 E36 C35

follow CRB

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0

DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3

DDR_A_CS#0

DDR_A_CS#1

DDR_A_ODT0

DDR_A_CAB9

DDR_A_CAB8

DDR_A_CAB5

DDR_A_CAA0

DDR_A_CAA2

DDR_A_CAA4

DDR_A_CAA3

DDR_A_CAA1

DDR_A_CAB7

DDR_A_CAA7

DDR_A_CAA6

DDR_A_CAB0

DDR_A_CAB2

DDR_A_CAB1

DDR_A_CAB3

DDR_A_CAB4

DDR_A_CAB6

DDR_A_CAA5

DDR_A_CAA8

DDR_A_CAA9

DDR_A_DQS#0

DDR_A_DQS0

DDR_A_DQS#1

DDR_A_DQS1 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5

+VREF_CA_C +V_DDR_REFA_C

+V_DDR_REFB_C DDR_PG_CTRL

DDR_VTT_PG_CTRL <43>

DDR_A_CLK#0 <19> DDR_A_CLK0 <19> DDR_A_CLK#1 <19> DDR_A_CLK1 <19>

DDR_A_CKE0 <19> DDR_A_CKE1 <19> DDR_A_CKE2 <19> DDR_A_CKE3 <19>

DDR_A_CS#0 <19> DDR_A_CS#1 <19> DDR_A_ODT0 <19>

DDR_A_CAB9 <19> DDR_A_CAB8 <19> DDR_A_CAB5 <19>

DDR_A_CAA0 <19> DDR_A_CAA2 <19> DDR_A_CAA4 <19> DDR_A_CAA3 <19> DDR_A_CAA1 <19> DDR_A_CAB7 <19> DDR_A_CAA7 <19> DDR_A_CAA6 <19> DDR_A_CAB0 <19>

DDR_A_CAB2 <19> DDR_A_CAB1 <19> DDR_A_CAB3 <19>

DDR_A_CAB4 <19> DDR_A_CAB6 <19> DDR_A_CAA5 <19>

DDR_A_CAA8 <19> DDR_A_CAA9 <19>

DDR_A_DQS#0 <19> DDR_A_DQS0 <19> DDR_A_DQS#1 <19> DDR_A_DQS1 <19> DDR_A_DQS#4 <19> DDR_A_DQS4 <19> DDR_A_DQS#5 <19> DDR_A_DQS5 <19> DDR_B_DQS#0 <20> DDR_B_DQS0 <20> DDR_B_DQS#1 <20> DDR_B_DQS1 <20> DDR_B_DQS#4 <20> DDR_B_DQS4 <20> DDR_B_DQS#5 <20> DDR_B_DQS5 <20>

+VREF_CA_C +V_DDR_REFA_C

+V_DDR_REFB_C

Trace width/Spacing >= 20mils

DDR_A_D[0..15]<19>

DDR_A_D[32..47]<19>

C C

DDR_B_D[0..15]<20>

DDR_B_D[32..47]<20>

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

< For ODT & VTT Power Control >

DDR_VTT_CNTL to DDR VTT supplied ramped <35u S (tCPU 18)

DDR_PG_CTRL

2

3

74AUP1G07GW_TSSOP5

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHL-U42_BGA1528

DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_1/DDR1_CKN_1 DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/NC DDR1_CKE_3/NC

DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT#

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQSP_7/DDR1_DQSP_7

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_COMP_0 DDR_COMP_1 DDR_COMP_2

3 of 20

AF28 AF29 AE28 AE29

T28 T29 V28 V29

AL37 AL35 AL36 AL34 AG36 AG35 AF34 AG37 AE35 AF35 AE37 AC29 AE36 AB29 AG34 AC28 AB28 AK35

AJ35 AK34 AJ34

AJ37 AJ36 W29

Y28 W28

H24 G24 C23 D23 G30 H30 L30 N30 AL31 AL30 AU31 AU30 BC31 BC30 BH31 BH30

Y29 AE34 BU31

BN28 BN27 BN29

DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0

DDR_B_CAB9 DDR_B_CAB8 DDR_B_CAB5

DDR_B_CAA0 DDR_B_CAA2 DDR_B_CAA4 DDR_B_CAA3 DDR_B_CAA1 DDR_B_CAB7 DDR_B_CAA7 DDR_B_CAA6 DDR_B_CAB0

DDR_B_CAB2 DDR_B_CAB1 DDR_B_CAB3

DDR_B_CAB4 DDR_B_CAB6 DDR_B_CAA5

DDR_B_CAA9 DDR_B_CAA8

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR_B_CLK#0 <20> DDR_B_CLK0 <20> DDR_B_CLK#1 <20> DDR_B_CLK1 <20>

DDR_B_CKE0 <20> DDR_B_CKE1 <20> DDR_B_CKE2 <20> DDR_B_CKE3 <20>

DDR_B_CS#0 <20> DDR_B_CS#1 <20> DDR_B_ODT0 <20>

DDR_B_CAB9 <20> DDR_B_CAB8 <20> DDR_B_CAB5 <20>

DDR_B_CAA0 <20> DDR_B_CAA2 <20> DDR_B_CAA4 <20> DDR_B_CAA3 <20> DDR_B_CAA1 <20> DDR_B_CAB7 <20> DDR_B_CAA7 <20> DDR_B_CAA6 <20> DDR_B_CAB0 <20>

DDR_B_CAB2 <20> DDR_B_CAB1 <20> DDR_B_CAB3 <20>

DDR_B_CAB4 <20> DDR_B_CAB6 <20> DDR_B_CAA5 <20>

DDR_B_CAA9 <20>

DDR_B_CAA8 <20>

DDR_A_DQS#2 <19> DDR_A_DQS2 <19> DDR_A_DQS#3 <19> DDR_A_DQS3 <19> DDR_A_DQS#6 <19> DDR_A_DQS6 <19> DDR_A_DQS#7 <19> DDR_A_DQS7 <19> DDR_B_DQS#2 <20> DDR_B_DQS2 <20> DDR_B_DQS#3 <20> DDR_B_DQS3 <20> DDR_B_DQS#6 <20> DDR_B_DQS6 <20> DDR_B_DQS#7 <20> DDR_B_DQS7 <20>

1 2

RC246 200_0402_1% RC247 80.6_0201_1%

1 2 1 2

RC40 162_0402_1%

Trace width=12~15 mil, Spacing=20 mils Max trace length= 500 mil

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/02/06 202 0/5/17

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

WHL-U(2/12)LPDDR3

Size Document Number Rev

Custom

Date: Sheet of

Friday, May 18, 2018

LA-G651P

1

52

7

0.2

Compal For Lenovo

5

4

3

2

1

+3VALW

1 2

RC437 100K_02 01_5%

1 2

RC438 100K_02 01_5%

1 2

RC439 100K_02 01_5%

SOC_SPI_0 _SI SOC_SPI_0 _IO2 SOC_SPI_0 _IO3

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

D D

SOC_SPI_0 _CLK SOC_SPI_0 _SO SOC_SPI_0 _SI

SPI ROM

+3VS

1 2

RC25 8.2K_040 2_5%

C C

+3VS

1 2

RC112 10K_040 2_5%

SERIRQ

SERIRQ<34>

KB_RST#

SOC_SPI_0 _IO2 SOC_SPI_0 _IO3 SOC_SPI_0 _CS#0

SERIRQ

RPC1, RPC3 an d RC30 are clo se to UC3

SOC_SPI_0 _SO SOC_SPI_0 _CLK SOC_SPI_0_CLK_R SOC_SPI_0 _SI

From SOC

B B

From EC

EC_SPI_CL K<34> EC_SPI_MO SI<34> EC_SPI_CS 0#<34>

EC_SPI_MISO<34>

SOC_SPI_0 _IO3

SOC_SPI_0 _IO2

EC_SPI_CL K EC_SPI_MO SI SOC_SPI_0 _SI_R EC_SPI_CS 0# EC_SPI_MISO

1 2

RC469 33_0402 _5%

1 2

RC470 33_0402 _5%EMI@

1 2

RC471 33_0402 _5%

1 2

RC472 33_0402 _5%

1 2

RC30 33_0402 _5%

1 2

RC473 33_0402 _5%EMI@

1 2

RC474 33_0402 _5%

1 2

RC475 33_0402 _5%

1 2

RC476 33_0402 _5%

SOC_SPI_0 _IO2_R

SOC_SPI_0 _SO_R

SOC_SPI_0 _SI_R SOC_SPI_0 _IO3_R

SOC_SPI_0 _CLK_R

SOC_SPI_0 _CS#0 SOC_SPI_0 _SO_R

UC1E

CH37

SPI0_CLK

CF37

SPI0_MISO

CF36

SPI0_MOSI

CF34

SPI0_IO2

CG34

SPI0_IO3

CG36

SPI0_CS0#

CG35

SPI0_CS1#

CH34

SPI0_CS2#

CF20

GPP_D1/SPI1_CLK/BK1/SBK1

CG22

GPP_D2/SPI1_MISO_IO1/BK2/SBK2

CF22

GPP_D3/SPI1_MOSI_IO0/BK3/SBK3

CG23

GPP_D21/SPI1_IO2

CH23

GPP_D22/SPI1_IO3

CG20

GPP_D0/SPI1_CS0#/BK0/SBK0

CH7

CL_CLK

CH8

CL_DATA

CH9

CL_RST#

BV29

GPP_A0/RCIN#/TIME_SYNC1

BV28

GPP_A6/SERIRQ

WHL -U42_BGA1528

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

5 of 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

CK14 CH15 CJ15

CH14 CF15 CG15

CN15 CM15 CC34

CA29 BY29 BY27 BV27 CA28 CA27

BV32 BV30 BY30

PCH_SMB _CLK PCH_SMB _DATA

SOC_SML 0CLK SOC_SML 0DATA

EC_SMB_ CK2 EC_SMB_ DA2

SOC_SML 1ALERT#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRA ME#

LPC_CLK 0

PM_CLKR UN#KB_RST#

1 2

RC26 22_0402 _5%EMI@

1

2

Close to RC26

CC3865

33P_0402_50V8J

@RF@

EC_SMB_ CK2 <24,30,34 ,36>

EC_SMB_ DA2 <24,30,34 ,36>

LPC_AD0 <34> LPC_AD1 <34> LPC_AD2 <34> LPC_AD3 <34>

LPC_FRA ME# <34>

PM_CLKR UN# <3 4>

EC_SMB_ CK2

EC_SMB_ DA2

SOC_SML 1ALERT#

PCH_SMB _CLK PCH_SMB _DATA SOC_SML 0CLK SOC_SML 0DATA

PM_CLKR UN#

SMB

(Link to DDR)

SML1

(Link to EC,DGPU,Thermal IC)

CLK_LPC _EC <3 4>

1 2

RC28 1K_0402 _5%

1 2

RC29 1K_0402 _5%

1 2

@

RC113 150K_04 02_5%

1 2

12 12 12 12

RC465 1K_0402 _5% RC466 1K_0402 _5% RC467 1K_0402 _5% RC468 1K_0402 _5%

RC31 8.2K_0402_5%

+3VS

< SPI ROM - 16M >

SOC_SPI_0 _CS#0

SOC_SPI_0 _IO2_R

A A

UC3

1

CS#

2

DO(IO1)

3

IO2

4

GND

XM25QH1 28AHIG SOP 8P

Compal For Lenovo

5

VCC

CLK

DI(IO0)

IO

8 7 6 5

+3VALW

@

1 2

CC2 0.1U_0201 _10V6K

SOC_SPI_0 _IO3_RSOC_SPI_0 _SO_R SOC_SPI_0 _CLK_R SOC_SPI_0 _SI_R

1

CC3 10P_040 2_50V8J

2

@EMI@

Security Classification

2017/5/3 2017/6/2

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2017/5/3 2017/6/2

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

WHL-U(3/12)SPI,SMB,LPC,ESPI

LA-G651P

8 52Friday, May 18, 2018

1

0.2

5

Vender ID

Samsung

Hynix

Micron

D D

DRAM Capacity

4GB 8GB 16GB

< HD AUDIO >

HDA_BIT_CLK_R<33>

HDA_SYNC_R<33> HDA_SDOUT_R<33>

C C

CPU_GPP_G7 CPU_GPP_G6

SDRAM_ID4 SDRAM_ID3

0 0 0 1

CPU_GPP_G5 CPU_GPP_G4

SDRAM_ID2 SDRAM_ID1

1 0

0 0 0 1

HDA_SDOUT reserve 500 ohm PD for Audio lost issue

1 2

RC477 33_040 2_5%EMI@

1 2

RC478 33_040 2_5%

1 2

RC479 33_040 2_5%

1

Close to RC477

2

1 0

HDA_BIT_CLK HDA_SYNC HDA_SDOUT

12

RC3945

@

499_0402_ 1%

CC3866

33P_0402_50V8J

@RF@

CPU Memory down vender control table

CPU_GPP_G7

0 0

1 0 0 1

HDA_SDIN0<33>

< To Enable ME Override >

CNV_RF_RESET #<3 2>

CLKREQ_CNV#<32>

ME_EN< 34>

DGPU

B B

RC116 0_0402 _5%

GC6_FB_EN<24,25>

GPU_EVENT#<24>

1 2

12

GC6_FB_EN GC6_FB_EN1V8

GPU_EVENT# SOC_GPP_C10

CNV_RF_RESET #

RC390775K_0 402_5% CNVi@

HDA_SDOUT

RC463 0_0402 _5%

RC464 0_0402 _5%

12

1 2

HDA_SPKR<33 >

CLK_CNV_CRX_D TX_N<32> CLK_CNV_CRX_D TX_P<32> CLK_CNV_CT X_DRX_N<32> CLK_CNV_CT X_DRX_P<32>

Follow Jefferson Peak schematic check list.

+3VS

1 2

RC487 10K_0402_5%@

1 2

A A

RC33 2.2K_0402 _5%@

WLBT_OFF#

HDA_SPKR

4

CPU_GPP_G4CPU_GPP_G5CPU_GPP_G6

SDRAM_ID2SDRAM_ID3SDRAM_ID4

Vende r

Samsung K4E6E304EC-EG CG

0

Hynix

Micron

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

CNV_RF_RESET #

CLKREQ_CNV#

HDA_SPKR

1 2

COEX3<32>

1 2

10K_0402_5 %

CNV_CRX_DTX_N0 CNV_CRX_DTX_P0

CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 CNV_CTX_DRX_N0 CNV_CTX_DRX_P0

CNV_CTX_DRX_N1 CNV_CTX_DRX_P1

CLK_CNV_CRX_D TX_N CLK_CNV_CRX_D TX_P CLK_CNV_CT X_DRX_N CLK_CNV_CT X_DRX_P

RC443150_040 2_1% C NVi@

SOC_GPP_C10 WLBT_OFF#

CNV_CRX_DTX_N0<32> CNV_CRX_DTX_P0<32>

CNV_CRX_DTX_N1<32> CNV_CRX_DTX_P1<32>

CNV_CTX_DRX_N0<32> CNV_CTX_DRX_P0<32>

CNV_CTX_DRX_N1<32> CNV_CTX_DRX_P1<32>

TP_INT#<35>

WLBT_OFF#<32>

COEX1<32> COEX2<32>

RC444

SDRAM_ID1

0

1 1 1 0 0 010 1 1 1 0 0

MD size

0 1 0

8GB

16GB

4GB

4GB 1 0

8GB

16GB

4GB

8GB 01

1 1

UC1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

WHL-U42 _BGA1528

CNV_WT_R COMP

COEX3

GC6_FB_EN1V8

COEX1 COEX2

SOC_A4WP_PR ESENT

16GB

4GB

UC1I

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP32

CNV_WT_RCOMP_0

CR32

CNV_WT_RCOMP_1

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

WHL-U42 _BGA1528

3

Vender desciption

K4E8E324EB-EGC G4GB

K4EBE304EC -EGCG K4E6E304EC -EGCG(CH B-ONLY) H9CCNNN8GTALAR-NV D H9CCNNNBJTALAR-NVD H9CCNNNCLGALAR-NVD H9CCNNNBJ TALAR-NVD(C HB-ONLY) MT52L256M32D1PF-093WT:B MT52L512M32D2PF-093WT:B MT52L1G32D4PG-093WT:B MT52L512M32D2PF-093WT:B(CHB-ONLY)

GPP_G0/SD_CMD GPP_G1/SD3_DATA0 GPP_G2/SD3_DATA1 GPP_G3/SD3_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

7 of 20

GPP_D4/IMGCLKOUT0/BK4/SBK4

9 of 20

GPP_A16/SD_1P8_SEL

SD_1P8_RCOMP SD_3P3_RCOMP

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_H21 GPP_H22 GPP_H23 GPP_F10

GPD7

GPP_F3

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0 GPP_F13/EMMC_DATA1 GPP_F14/EMMC_DATA2 GPP_F15/EMMC_DATA3 GPP_F16/EMMC_DATA4 GPP_F17/EMMC_DATA5 GPP_F18/EMMC_DATA6 GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

GPP_H21 XTAL frequency selected. 0: 38.4/19.2Mhz 1: 24MHz XTAL selected

SOC_C10_GATE#

CN27

CM27

SOC_GPP_H21

CF25 CN26 CM26 CK17

SOC_GPD7

BV35 CN20

XTAL INPUT MODE (HVM ONLY)

CG25

LOW: XTAL INPUT IS SINGLE ENDED

CH25

HIGH: XTAL IS ATTACHED

CR20 CM20 CN19 CM19 CN18 CR18 CP18 CM18

CM16 CP16 CR16 CN16

SOC_SD_RCOM P

CK15

BOM Conf i g

Vende r

Samsung

Hynix

Micron

CH36 CL35 CL36 CM35

SDRAM_ID1

CN35

SDRAM_ID2

CH35

SDRAM_ID3

CK36

SDRAM_ID4

CK34

BW36 BY31

CK33

SOC_SD_RCOM P

CM34

RC441 4.7K_0402_5 %

RC442 100K_0 201_5%

SDRAM_ID4 SDRAM_ID3 SDRAM_ID2 SDRAM_ID1

MD size

4GB

8GB

16GB

4GB

8GB

16GB

4GB

8GB

16GB

1 2

RC440 200_040 2_1%

SOC_C10_GATE# <13>

1 2

2

RC435

RC433

S4G@

RC435

S8G@

RC435

S16G@

RC435

H4G@

RC435

H8G@

RC435

H16G@

RC434

M4G@

RC434

M8G@

RC434

M16G@

S4G@

RC433

S8G@

RC433

S16G@

RC432

H4G@

RC432

H8G@

RC432

H16G@

RC433

M4G@

RC433

M8G@

RC433

M16G@

RC248

RC249

S4G@

RC89

S8G@

RC248

S16G@

RC248

H4G@

RC89

H8G@

RC248

H16G@

RC248

M4G@

RC89

M8G@

RC248

M16G@

RC249

S8G@

RC88

S16G@

RC249

H4G@

RC249

H8G@

RC88

H16G@

RC249

M4G@

RC249

M8G@

RC88

M16G@

UD1 S8G@

SA0000AZT20

UD1 S16G@

SA00008VV20

UD1 H8G@

SA0000ALP00

UD1 H16G@

SA00009ZL00

UD1 M8G@

SA0000AM400

UD1 M16G@

SA00009ZN00

LPDDR3

UD2 S8G@

SA0000AZT20

UD2 S16G@

SA00008VV20

UD2 H8G@

SA0000ALP00

UD2 H16G@

SA00009ZL00

UD2 M8G@

SA0000AM400

UD2 M16G@

SA00009ZN00

1

UD3 S4G@

SA0000AZT20

UD3 S8G@

SA0000AZT20

UD3 S16G@

SA00008VV20

UD3 H4G@

SA0000ALP00

UD3 H8G@

SA0000ALP00

UD3 H16G@

SA00009ZL00

UD3 M4G@

SA0000AM400

UD3 M8G@

SA0000AM400

UD3 M16G@

SA00009ZN00

UD4 S4G@

SA0000AZT20

UD4 S8G@

SA0000AZT20

UD4 S16G@

SA00008VV20

UD4 H4G@

SA0000ALP00

UD4 H8G@

SA0000ALP00

UD4 H16G@

SA00009ZL00

UD4 M4G@

SA0000AM400

UD4 M8G@

SA0000AM400

UD4 M16G@

SA00009ZN00

Memory Strap Resistors

+3VS +3VS +3VS + 3VS

+3VALW

SDRAM_ID1 SDRAM_ID2 SDRAM_ID3 SDRAM_ID4

12

RC249 10K_0201_5 %

@

RC88 10K_0201_5 %

@

12

RC248 10K_0201_5 %

@

RC89 10K_0201_5 %

@

12

RC432 10K_0201_5 %

12

RC433 10K_0201_5 %

12

RC434

@

10K_0201_5 %

12

RC435 10K_0201_5 %

@

SPKR ( Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode.

Compal For Lenovo

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size D ocument Number R ev

Custom

Date : Sheet of

Compal Electronics, Inc.

WHL-U(4/12)HDA,EMMC,SDIO,CSI2

LA-G651P

Friday, May 18, 2018

LA-G651P

1

52

9

0.2

5

< PCH PLTRST Buf f er >

+3VS

1 2

RC481 10K_04 02_5%

1 2

RC482 10K_04 02_5%

1 2

RC483 10K_04 02_5%

CLKREQ_PCIE#0

12

RC140

@

D D

10K_0402_5 %

CLKREQ_PCIE#0 CLKREQ_PCIE#2 CLKREQ_PCIE#4

DGPU

NGFF WL+BT(KEY E)

SSD

+3VL_RTC

WAKE#

SOC_SRTCRS T#

CLR CMOS

SM_INTRUDER#

PCH_PWR OK EC_RSMRST# SYS_RESET#

+1.05V_VCCST

12

RC52 1K_0402_5%

RC53 60.4_0402_ 1%

CC126

100P_0402_50V8J

1

ESD@

2

EC_CLEAR_CMO S# <34>

1 2

RC36 20K_0402_ 5%

12

CC6 1U_0201_6 .3V6M

1 2

RC37 20K_0402_ 5%

12

CC7 1U_0201_6 .3V6M

1 2

CLRP2 SHORT PADS

1 2

C C

B B

RC39 1M_0402_5 %

+3VALW

RC484 10K_04 02_5% RC485 10K_04 02_5% RC486 10K_04 02_5%

1 2

ESD@

CC97 100P_0402_ 50V8J

1 2

ESD@

CC94 100P_0402_ 50V8J

1 2

ESD@

CC95 100P_0402_ 50V8J

+3VALW

1 2

1 2 1 2 1 2

RC54

1K_0402_5%

SYS_RESET#

EC_RSMRST#

SYS_PWROK

From EC (Open-Drain)

VCCST_PWR GD<34>

EC_VCCST_PG

4

UC1J

CLK_PCIE_N0< 21> CLK_PCIE_P0<21> CLKREQ_PCIE#0<2 1>

CLK_PCIE_N2< 32> CLK_PCIE_P2<32> CLKREQ_PCIE#2<3 2>

CLK_PCIE_N4< 32> CLK_PCIE_P4<32> CLKREQ_PCIE#4<3 2>

EC_RSMRST#<34>

T31 T P@

SYS_PWROK<34>

PCH_PWR OK<34>

CLKREQ_PCIE#0

CLKREQ_PCIE#2

CLKREQ_PCIE#4

SOC_PLTRST # SYS_RESET# EC_RSMRST#

EC_VCCST_PG

SYS_PWROK PCH_PWR OK EC_RSMRST#

WAKE#

AW2

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

CLKOUT_PCIE_P_4

CE30

GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N_5

BE2

CLKOUT_PCIE_P_5

CF31

GPP_B10/SRCCLKREQ5#

WHL-U42 _BGA1528

SOC_PLTRST #

UC1K

BJ35

GPP_B13/PLTRST#

CN10

SYS_RESET#

BR36

RSMRST#

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

CR10

SYS_PWROK

BP31

PCH_PWROK

BP30

DSW_PWROK

BV34

GPP_A13/SUSWARN#/SUSPWRDACK

BY32

GPP_A15/SUSACK#

BU30

WAKE#

BU32

GPD2/LAN_WAKE#

BU34

GPD11/LANPHYPC

WHL-U42 _BGA1528

3

10 of 20

TC7SH08FU F_SSOP5

GPP_B11/EXT_PWR_GATE#

11 of 20

XTAL_IN

XTAL_OUT

CLK_BIASREF

CLKIN_XTAL

RTCX1 RTCX2

SRTCRST#

RTCRST#

UC4

P

4

Y

G

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD6/SLP_A#

GPD0/BATLOW#

INTRUDER#

INPUT3VSEL

AU1 AU2

BT32

CK3 CK2

CJ1 CM3

BN31 BN32

BR37 BR34

12

RC44

100K_0402_5%

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

1 2

RC55 0_0402_5%

+3VS

5

1

B

2

A

3

@

GPP_B12/SLP_S0#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPP_B2/VRALERT#

SUSCLK

33E_SOC_XTAL24 _IN_R

33E_SOC_XTAL24 _OUT_R

XCLK_BIASREF CLKIN_XTAL

SOC_RTCX1 SOC_RTCX2

SOC_SRTCRS T# EC_CLEAR_CMO S#

12

CC8 100P_0402_ 50V8J

ESD@

BJ37

PM_SLP_S3#

BU36

PM_SLP_S4#

BU27

PM_SLP_S5#

BT29

BU29 BT31 BT30 BU37

PBTN_OUT#

BU28

AC_PRESENT_R

BU35

PM_BATLOW#

BV36

SM_INTRUDER#

BR35

CC37

SOC_VRALERT#

CC36

SOC_INPUT3VSEL

BT27

PCI_RST# <21,32,34>

RC103 0_0402 _5%

SUSCLK <32>

CLKIN_XTAL < 32>

PM_SLP_S3# <34 > PM_SLP_S4# <34 ,41>

T131TP@

1 2

2

33E_SOC_XTAL24 _IN_R

33E_SOC_XTAL24 _OUT_R

RC58 47_0201_5 %

LC99

1

4

DLM0NSN90 0HY2D_4P

RC63 47_0201_5 %EMI@

PBTN_OUT# < 34> AC_PRESENT <24,34 >

1 2

EMI@

@EMI@

1 2

XCLK_BIASREF

RC110 60.4_04 02_1%

CLKIN_XTAL

RC245 10K_04 02_5%

33E_SOC_XTAL24 _IN

2

3

33E_SOC_XTAL24 _OUT

SOC_RTCX2

SOC_RTCX1

PM_BATLOW#

AC_PRESENT_R

SOC_VRALERT#

SOC_INPUT3VSEL

1

1 2

RC38 200K_0402 _1%

YC3

SJ10000UJ00

24MHZ_18PF_XRC GB24M000F2P51R0

3

CC19

27P_0402_50V8J

1

2

RC41 10M_0402_ 5%

32.768KHZ_9P F_X1A000141000200

1

CC9

6.8P_0402_5 0V8C

2

RC46 8.2K_0402_ 5%

RC48 10K_0402_ 5%

RC50 10K_0402_ 5%

RC445 4.7K_0402 _5%

RC446 4.7K_0402 _5%

1 2

YC2

1 2

@

1 2

@

1 2

@

1 2

NC

2

4

1

CC10

6.8P_0402_5 0V8C

2

+3VALW

CC20

27P_0402_50V8J

1

2

A A

Security Classification

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

WHL-U(5/12)CLK,PM,GPIO

Size D ocument Number R ev

Custom

Date : Sheet of

2

Date : Sheet of

LA-G651P

1

10 52Friday, May 18, 2018

0.2

5

4

3

2

1

GSPI0_MOSI (Internal Pu ll Down):

No Reboot

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot feature). This funct i on is usef ul when running ITP/XDP.

D D

GSPI1_MOSI (Internal Pu ll Down):

Boot BIOS Strap Bit

0 = SPI Mode ==> Default

1 = LPC Mode

+3VS

C C

1 2

RC59 4.7K_0402 _5%@

1 2

RC60 150K_040 2_5%@

1 2

RC83 49.9K_040 2_1%

1 2

RC84 49.9K_040 2_1%

1 2

RC3941 2.2K_040 2_5%

1 2

RC3942 2.2K_040 2_5%

1 2

RC488 10K_04 02_5%DIS@

1 2

RC489 10K_04 02_5%

1 2

RC42 2.2K_0402 _5%

1 2

RC43 2.2K_0402 _5%

1 2

RC447 10K_04 02_5%@

1 2

RC448 10K_04 02_5%DIS@

GSPI0_MOSI

GSPI1_MOSI

UART0_RX UART0_TX I2C_1_SDA I2C_1_SCL

DGPU_PWR _EN

SOC_GPP_A7 I2C_0_SDA

I2C_0_SCL DGPU_HOLD_R ST# DGPU_HOLD_R ST#

Touch Pad

UCM

CNV_BRI_CRX_DTX<32> CNV_RGI_CTX_DRX<32> CNV_BRI_CTX_DRX<32> CNV_RGI_CRX_DTX<32>

I2C_0_SDA<35> I2C_0_SCL<35>

I2C_1_SDA<30> I2C_1_SCL<30>

T2406

SOC_GPP_A7 GPP_B16

GSPI0_MOSI

TP@

GSPI1_MOSI

CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX CNV_RGI_CRX_DTX

UART0_RX<32,35 >

UART0_TX<32,35>

UC1F

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHL-U42 _BGA1528

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK GPP_D11/ISH_SPI_MISO/GSPI2_MISO GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

6 of 20

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

CN22 CR22 CM22 CP22

CK22 CH20

CH22 CJ22

CJ27 CJ29

CM24 CN23 CM23 CR24

CG12 CH12 CF12 CG14

BW35 BW34 CA37 CA36 CA35 CA34 BW37

GPP_H11

DGPU_PWR _EN DGPU_HOLD_R ST# GPU_ALL_PGOOD DGPU_PRSNT #

T2405TP@

DGPU_PWR _EN <24,26,34> DGPU_HOLD_R ST# <21> GPU_ALL_PGOOD < 21>

Funct i on

DIS

UMA Only

DGPU_PRSNT #

DGPU

DGPU_PRSNT# (GPP_C1 5)

0

1

+3VS

12

R7310K_0402_5 % UMA@

12

R7410K_0402_5 % DIS@

B B

Place close to PCH

+1.8VALW

CNV_RGI_CRX_DTX CNV_BRI_CRX_DTX

A A

1 2

RC3939 20K_020 1_5%@

1 2

RC3938 20K_020 1_5%@

Security Classification

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number R ev

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

WHL-U(6/12)GPIO,I2C,GSPI

LA-G651P

1

11 52Friday, May 18, 2018

0.2

5

4

3

2

1

D D

PCIE_CRX_ DTX_N8<3 2>

NGFF WLAN+BT

C C

SSD

dGPU

B B

PCIE_CRX_ DTX_P8<32>

PCIE_CTX_ DRX_N8<3 2> PCIE_CTX_ DRX_P8<32>

PCIE_CRX_ DTX_N9<3 2> PCIE_CRX_ DTX_P9<32> PCIE_CTX_ DRX_N9<3 2> PCIE_CTX_ DRX_P9<32>

PCIE_CRX_ DTX_N10<32> PCIE_CRX_ DTX_P10<32> PCIE_CTX_ DRX_N10<32> PCIE_CTX_ DRX_P10<32>

PCIE_CRX_ DTX_N11<32> PCIE_CRX_ DTX_P11<32> PCIE_CTX_ DRX_N11<32> PCIE_CTX_ DRX_P11<32>

PCIE_CRX_ DTX_N12<32> PCIE_CRX_ DTX_P12<32> PCIE_CTX_ DRX_N12<32> PCIE_CTX_ DRX_P12<32>

PCIE_CRX_DTX_N13<21> PCIE_CRX_DTX_P13<21>

PCIE_CTX_ C_DRX_N13<21> PCIE_CTX_ C_DRX_P13<21>

PCIE_CRX_DTX_N14<21>

PCIE_CRX_DTX_P14<21> PCIE_CTX_ C_DRX_N14<21> PCIE_CTX_ C_DRX_P14<21>

PCIE_CRX_DTX_N15<21> PCIE_CRX_DTX_P15<21>

PCIE_CTX_ C_DRX_N15<21> PCIE_CTX_ C_DRX_P15<21>

PCIE_CRX_DTX_N16<21> PCIE_CRX_DTX_P16<21>

PCIE_CTX_ C_DRX_N16<21> PCIE_CTX_ C_DRX_P16<21>

1 2

CC114 0.22U_02 01_6.3V6MDIS@

1 2

CC149 0.22U_02 01_6.3V6MDIS@

1 2

CC188 0.22U_02 01_6.3V6MDIS@

1 2

CC187 0.22U_02 01_6.3V6MDIS@

1 2

CC185 0.22U_02 01_6.3V6MDIS@

1 2

CC186 0.22U_02 01_6.3V6MDIS@

1 2

CC184 0.22U_02 01_6.3V6MDIS@

1 2

CC183 0.22U_02 01_6.3V6MDIS@

1 2

RC71 100_0402_1%

Near UC1

PCIE_CTX_ DRX_N13 PCIE_CTX_ DRX_P13

PCIE_CTX_ DRX_N14 PCIE_CTX_ DRX_P14

PCIE_CTX_ DRX_N15 PCIE_CTX_ DRX_P15

PCIE_CTX_ DRX_N16 PCIE_CTX_ DRX_P16

PCIE_RCOM PN PCIE_RCOM PP

UC1H

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCIE7_TXN

BU1

PCIE7_TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCIE8_TXN

BT3

PCIE8_TXP

BP5

PCIE9_RXN

BP6

PCIE9_RXP

BR2

PCIE9_TXN

BR1

PCIE9_TXP

BN6

PCIE10_RXN

BN5

PCIE10_RXP

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN10

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE6

PCIE_RCOMP_N

CE5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2/CFG_0

CP28

GPP_H13/M2_SKT2/CFG_1

CN28

GPP_H14/M2_SKT2/CFG_2

CM28

GPP_H15/M2_SKT2/CFG_3

WHL -U42_BGA1528

When PCIE16/SATA2 is used as SATA Port 1 (ODD), then PCIE15/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

8 of 20

PCIE1_RXN/USB31_1_RXN

PCIE1_RXP/USB31_1_RXP PCIE1_TXN/USB31_1_TXN PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

PCIE3_RXN/USB31_3_RXN

PCIE3_RXP/USB31_3_RXP PCIE3_TXN/USB31_3_TXN PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN

PCIE4_RXP/USB31_4_RXP PCIE4_TXN/USB31_4_TXN PCIE4_TXP/USB31_4_TXP

GPP_E9/USB2_OC0#/GP_BSSB_CLK

GPP_E10/USB2_OC1#/GP_BSSB_DI

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

USB2_1N USB2_1P

USB2_2N USB2_2P

USB2_3N USB2_3P

USB2_4N USB2_4P

USB2_5N USB2_5P

USB2_6N USB2_6P

USB2_7N USB2_7P

USB2_8N USB2_8P

USB2_9N USB2_9P

USB2_10N USB2_10P

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

UFS_RESET#

CB5 CB6 CA4 CA3

BY8 BY9 CA2 CA1

BY7 BY6 BY4 BY3

BW6 BW5 BW2 BW1

CE3 CE4

CE1 CE2

CG3 CG4

CD3 CD4

CG5 CG6

CC1 CC2

CG8 CG9

CB8 CB9

CH5 CH6

CC3 CC4

CC5 CE8 CC6

CK6 CK5 CK8 CK9

CP8 CR8 CM8

CN8 CM10 CP10

CN7

AR3

USB20_N 1 USB20_P 1

USB20_N 2 USB20_P 2

USB20_N 3 USB20_P 3

USB20_N 5 USB20_P 5

USB20_N 6 USB20_P 6

USB20_N 10 USB20_P 10

USB2_CO MP USB2_ID USB2_SE NSE

USB_OC0 # USB_OC1 # USB_OC2 # USB_OC3 #

WL_ OFF#

USB3_CR X_DTX_N1 <37> USB3_CR X_DTX_P1 <37> USB3_CT X_DRX_N1 <37> USB3_CT X_DRX_P1 <37>

USB3_CR X_DTX_N2 <37> USB3_CR X_DTX_P2 <37> USB3_CT X_DRX_N2 <37> USB3_CT X_DRX_P2 <37>

USB3_CR X_MTX_N3 < 30> USB3_CR X_MTX_P3 <30 > USB3_CT X_MRX_N3 < 30> USB3_CT X_MRX_P3 <30 >

USB20_N 1 <37> USB20_P 1 <3 7>

USB20_N 2 <37> USB20_P 2 <3 7>

USB20_N 3 <31> USB20_P 3 <3 1>

USB20_N 5 <28> USB20_P 5 <2 8>

USB20_N 6 <35> USB20_P 6 <3 5>

USB20_N 10 <32> USB20_P 10 < 32>

1 2

RC70 113_040 2_1%

1 2

RC104 0_0402_ 5%@

1 2

RC105 1K_0402 _5%@

WL_ OFF# <32>

USB_OC2 # USB_OC0 # USB_OC3 # USB_OC1 #

USB2/3 (re-driver) (I/O SB)

USB2/3 (for charger)

Type-C

USB2/3 (re-driver) ( I/O BD)

USB2/3 (Charger)

Type-C

Camera

FP

CNVi

Trace length max: 450mils

RC490 10K_040 2_5% RC491 10K_040 2_5% RC492 10K_040 2_5% RC493 10K_040 2_5%

12 12 12 12

+3VALW

+3VS

A A

Security Classification

2017/5/3 2017/6/2

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/5/3 2017/6/2

3

Compal Secret Data

Deciphered Date

2

WL_ OFF#

Title

WHL-U(7/12)PCIE,USB,SATA

Size Document Number Re v

Custom

Date : Sheet o f

RC131 10K_040 2_5%

Compal Electronics, Inc.

@

1 2

LA-G651P

0.2

12 52Friday, May 18, 2018

1

5

+VL +1.05VS_ VCCIO

+1.05VALW TO +1.05V_VCCST

+1.8VALW TO +1.8VS

D D

C C

SYSON<34,43,44 >

SUSP#<34,38,4 3>

1 2

RC450 0_0402_ 5%

1 2

RC452 0_0402_ 5%

+VL

0.1U_0201_10V6K

CC30

1

@

2

SUSP#

+1.05VAL W

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

CC150

+1.05VALW TO +1.05VS_VCCIO

CC32

+1.05VAL W

+1.8VALW

EN_1.0V_ VCCSTU

EN_1.8VS

I(Max) : 3.675 A(+1.05VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

UC6

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

EM5201V _DFN8_3X3

4

I(Max) : 0.16 A(+1.05V_VCCST) RON(Max) : 25 mohm V drop : 0.004 V

UC7

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 DFN 14P

I(Max) : 0.2 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.005 V

+1.05VS_ VCCIO_STG

6

VOUT

5

GND

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

@

1 2

CC33

0.1U_0201_10V6K

1

2

RC451

RC453

1 2

0_0402_ 5%

+1.05V_V CCST_R

1 2

CC152 8200P_0 402_25V7K

1 2

CC153 1000P_0 402_50V7K

+1.8VS_R

Follow 543977_SKL_PDDG_ Rev0_91 CC24 10PF ->22us(Spec:<= 65us)

+1.05VS_ VCCIO

RC79

1 2

0_0805_ 5%

3

+1.05V_V CCST

+1.8VS

2

+1.2V

UC1N

AD36

3.3 A

CC151

0.1U_0201_10V6K

1

@

2

+1.05V_V CCST

+VCCPLL _OC

+1.05VS_ VCCSTG

0.0 2A

PSC Side

@

CC28

1

2

0.1 2A

10U_0402_6.3V6M

CC34

10U_0402_6.3V6M

1

CC31

2

CC154

0.1U_0201_10V6K

1

@

2

1uF X1

0.1uF X1

+1.05V_V CCST

10U_0402_6.3V6M

1

@

CC41

2

0.1 9A

10U_0402_6.3V6M

1

CC159

2

AH32 AH36

AM36

AN32

AW32

AY36 BE32 BH36

R32

Y36

BC28

BP11

BP2

BG1 BG2

BL27

BM26

BR11 BT11

WHL -U42_BGA1528

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11

RSVD1

VCCST1 VCCST2

VCCSTG1 VCCSTG2

VCCPLL_OC1 VCCPLL_OC2

VCCPLL1 VCCPLL2

+VCCPLL _OC

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 of 20

1U_0201_6.3V6M

12

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16

VCCSA2 VCCSA1 VCCSA3 VCCSA5 VCCSA6 VCCSA4 VCCSA9 VCCSA7

VCCSA8 VCCSA13 VCCSA14 VCCSA10 VCCSA11 VCCSA12 VCCSA15 VCCSA16

PSC Side

CC29

AK24 AK26 AL24 AL25 AL26 AL27 AM25 AM27 BH24 BH25 BH26 BH27 BJ24 BJ26 BP16 BP18

BG8 BG10 BH9 BJ8 BJ9 BJ10 BK8 BK25 BK27 BL8 BL9 BL10 BL24 BL26 BM24 BN25

BP28 BP29

BE7 BG7

1

3.67 9A

+VCCSA

6A

Trace Length Match < 25 mils

VSSSA_S ENSE VCCSA_S ENSE

+1.05VS_ VCCSTG

12

PSC Side

1U_0201_6.3V6M

CC35

VSSSA_S ENSE <46> VCCSA_S ENSE <46>

Close to BP11 & BP2 Close to BG1 & BG2

+1.05VS_ VCCIO

10P_0402_50V8J

1

12

CC3867

B B

RF@

2

change package of 1U from 0201 to 0402

PSC SideBSC Side BSC SidePSC Side

10U_0402_6.3V6M

1U_0201_6.3V6M

12

CC39

1U_0201_6.3V6M

1

12

CC40

12

CC37

CC38

@

1

CC160

2

10U_0402_6.3V6M

@

1

CC36

1

CC161

2

+1.2V

10U_0402_6.3V6M

@

CC189

10U_0402_6.3V6M

1

CC163

CC164

2

Close to CPU Unde rneath CPU

+1.05VALW TO +1.05VS_VCCSTG

+VL

+1.05VAL W

1U_0201_6.3V6M

0.1U_0201_10V6K

CC174

1

12

2

@

A A

S0_C10_ GATE#

+1.05VS_ VCCIO_STG +1.05VS_ VCCSTG_R

I(Max) : 20m A(+1.05VS_VCCSTG) RON(Max) : 6.2 mohm V drop : 0.019 V

CC175

UC8

@

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS2296 1DNYR_WSON8

VOUT

GND

+1.05VS_ VCCSTG_R

6

5

RC455

1 2

0_0402_ 5%

+1.05VS_ VCCSTG

Compal For Lenovo

1 2

RC458 0_0402_ 5%

5

4

CPU C10 Save Power

UC9

SOC_C10 _GATE#<9>

1

CC180

0.1U_020 1_10V6K

2

SOC_C10 _GATE#

SUSP#

@

74LVC1G 08FZ4-7_X2-DFN 1410-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

1

A

2

B

3

GND

1 2

RC457 0_0402_ 5%@

VCC

NC

+VL

0.1U_0201_10V6K

CC178

+3VALW

CC177

0.1U_020 1_10V6K

1 2

6

5

4

Y

2017/5/3 2017/6/2

3

@

S0_C10_ GATE#

Compal Secret Data

1

@

2

Deciphered Date

Close to BR11 & BT11

Close to BM26

change package of 1U from 0201 to 0402

10U_0402_6.3V6M

4.7U_0402_6.3V6M

@

1

CC47

2

+1.2V

1U_0201_6.3V6M

12

@

S0_C10_ GATE#

1

2

CC176

10U_0402_6.3V6M

@

CC44

1

2

CC173

CC172

2

1U_0201_6.3V6M

12

@

+1.2V TO +VCCPLL_OC

I(Max) : 120m A(+VCCPLL_OC) RON(Max) : 6.2 mohm V drop : 0.019 V

UC10

1 2

7

3

4

2

@

VIN1 VIN2

VIN thermal

VBIAS

ON

TPS2296 1DNYR_WSON8

6

VOUT

5

GND

Title

Size Document Number Re v

Custom

Date : Sheet o f

1U_0201_6.3V6M

12

CC167

1U_0201_6.3V6M

12

CC45

CC46

@

Close to CPUUnderneath CPU

RC454 0_0402_ 5%

+VCCPLL _OC_R

Compal Electronics, Inc.

WHL-U(8/12)Power

RC456

1 2

0_0402_ 5%

LA-G651P

12

1U_0201_6.3V6M

CC49

1 2

+VCCPLL _OC

1

1U_0201_6.3V6M

12

CC50

1

CC179

@

0.1U_020 1_10V6K

2

13 52Friday, May 18, 201 8

+VCCPLL _OC+1.2V

0.2

Saf t y s uggest i on r emove EE si de , Keep PWR s i de

+1.05VALW

12

5

1U_0201_6.3V6M

CC66

@

+1.05VALW

12

1U_0201_6.3V6M

CC56

4

3

2

1

Close to BP20Close to BV18

D D

1U_0201_6.3V6M

12

CC68

Close to BV2

+1.05VALW+1.05VALW

1

CC169

4.7U_0402_6.3 V6M

2

Close to BV12

1

CC171 10U_0402_6 .3V6M

2

+1.8VALW

Imax : 0.702A

+3VALW

Imax : 0.21A

+1.8VALW

1U_0201_6.3V6M

12

CC181

Close to CP17

C C

+3VALW

1U_0201_6.3V6M

12

CC57

@

1

@

CC79

0.1U_0201_10 V6K

2

Close to BT24

12

CC55 1U_0 201_6.3V6M

Close to CP29

+3VALW

1U_0201_6.3V6M

CC157

12

@

+3VALW

+3V_1.8V_HDA

Close to BR24

+3VALW

B B

RF@

LC4

1 2

BLM15BB221SN 1D_2P

+3V_1.8V_HDA

RF@

1

CC52

0.1U_0201_10 V6K

2

close to BP20

A A

Imax : 4.982A

Internal LDO

+DCPDSW

+1.05VALW

UC1P

BP20

VCCPRIM_1P05_1

BW16

VCCPRIM_1P05_9

BW18

VCCPRIM_1P05_10

BW19

VCCPRIM_1P05_11

BY16

VCCPRIM_1P05_12

CA14

VCCPRIM_1P05_14

CC15

VCCPRIM_1P8_1

CD15

VCCPRIM_1P8_4

CD16

VCCPRIM_1P8_5

CP17

VCCPRIM_1P8_8

CB22

VCCPRIM_3P3_4

CB23

VCCPRIM_3P3_5

CC22

VCCPRIM_3P3_6

CC23

VCCPRIM_3P3_7

CD22

VCCPRIM_3P3_8

CD23

VCCPRIM_3P3_9

CP29

VCCPRIM_3P3_10

BU15

VCCPRIM_CORE1

BU22

VCCPRIM_CORE2

BV15

VCCPRIM_CORE3

BV16

VCCPRIM_CORE4

BV18

VCCPRIM_CORE5

BV19

VCCPRIM_CORE6

BV20

VCCPRIM_CORE7

BV22

VCCPRIM_CORE8

BW20

VCCPRIM_CORE9

BW22

VCCPRIM_CORE10

CA12

VCCPRIM_CORE11

CA16

VCCPRIM_CORE12

CA18

VCCPRIM_CORE13

CA19

VCCPRIM_CORE14

CA20

VCCPRIM_CORE15

CB12

VCCPRIM_CORE16

CB14

VCCPRIM_CORE17

CB15

VCCPRIM_CORE18

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05_4

BV12

VCCPRIM_MPHY_1P05_1

BW12

VCCPRIM_MPHY_1P05_3

BW14

VCCPRIM_MPHY_1P05_4

BY12

VCCPRIM_MPHY_1P05_5

BY14

VCCPRIM_MPHY_1P05_6

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05_2

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P3_1

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05_4

BT19

VCCPRIM_1P05_5

BU18

VCCPRIM_1P05_7

BU19

VCCPRIM_1P05_8

BT22

VCCPRIM_1P05_6

BP22

VCCPRIM_1P05_2

BV14

VCCPRIM_MPHY_1P05_2

WHL-U42_ BGA1528

K12

VCCOPC1

K14

VCCOPC2

K15

VCCOPC3

K17

VCCOPC4

K18

VCCOPC5

K20

VCCOPC6

L25

VCCOPC7

M24

VCCOPC8

M26

VCCOPC9

P24

VCCOPC10

P26

VCCOPC11

R24

VCCOPC12

R25

VCCOPC13

R26

VCCOPC14

W25

VCC_OPC_1P8_2

V24

VCC_OPC_1P8_1

Y25

VCC_OPC_1P8_4

Y24

VCC_OPC_1P8_3

WHL-U42_ BGA1528

VCCOPC and VCCEOPIO for CFL U43e only

UC1O

16 of 20

VCCEOPIO_SENSE VSSEOPIO_SENSE

15 of 20

VCCPRIM_3P3_3

VCCPRIM_1P05_13

VCCPRIM_1P05_3

VCCAPLL_1P05_3

VCCA_BCLK_1P05

VCCAPLL_1P05_1

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24_2 VCCDPHY_1P24_4

VCCDPHY_1P24_1 VCCDPHY_1P24_3

VCCDPHY_EC_1P24

VCCDSW_3P3_2

VCCA_19P2_1P05

VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_9

VCCPRIM_3P3_2

VCCPRIM_3P3_1

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

VCCEOPIO1 VCCEOPIO2 VCCEOPIO3 VCCEOPIO4 VCCEOPIO5 VCCEOPIO6 VCCEOPIO7 VCCEOPIO8

VCCRTC

DCPRTC

AA24 AA26 AB25 AC24 AC25 AC26 AD24 AD26

V25 T25

CB16

BR23

BY20 BP24

BR20

BT12

BP14

BR14

BU12

CP5

BY24 CA24

BY23 CA23 CP25

BT23

BR12

CC18 CC19 CD18 CD19 CP23

BW23

BP23

CB36 CB35

+1.05VALW

+3VALW

+DCPRTC

Intenal LDO

VCCDPHY_EC_1P24

Imax : 0.702A

+3VL_RTC

@

1 2

CC62 1U_0201_ 6.3V6M

Close to BP24

+VCCDPHY_1.24V

Close to CP25

1 2

CC182 4.7U _0402_6.3V6M

+1.05VALW

+1.8VALW

PD_INT# < 30,34>

+1.8VALW

1U_0201_6.3V6M

CC59

12

@

Close to CP23

RTC Bat t er y

+3VL_RTC +RTCBATT

W=20mil s

1 2

RC90 0 _0402_5%

1U_0201_6.3V6M

12

CC82

Close to BR23

+1.05VALW

CC3868

10P_0402_50V8J

1U_0201_6.3V6M

CC155

1 2

R3248 0_0201_ 5%CNVi@

1

RF@

2

Close to BP14

+VCCDPHY_1.24V

12

Close to CP5

VCCDPHY_EC_1P24

When CNVi is not used in the design: VCCDPHY_1P24 pin shall be disconnected from the VCCLDOSRAM_IN_1P24 pin. The decoupling capacitor shall remain connected to the VCCDPHY_1P24 pin.

Security Classific ation

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

WHL-U(9/12)Power

Size D ocument Number R ev

Custom

Date : Sheet o f

2

Date : Sheet o f

LA-G651P

14 5 2Friday, May 18, 2018

1

14 5 2Friday, May 18, 2018

0.2

5

+VCCCOR E +VCCCOR E

UC1L

AN9

VCCCORE5

AN10

VCCCORE1

D D

C C

AN24 AN26 AN27

AP2

AP9 AP24 AP26

AR5

AR6

AR7

AR8 AR10 AR25 AR27

AT9 AT24 AT26

AU5

AU6

AU7

AU8

AU9 AU24 AU25 AU26 AU27

AV2

AV5

AV7 AV10 AV27

AW5 AW6 AW7 AW8 AW9

AW10

BB9 BC24

AY9 BB24

WHL -U42_BGA1528

VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE6 VCCCORE9 VCCCORE7 VCCCORE8 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE19 VCCCORE17 VCCCORE18 VCCCORE24 VCCCORE25 VCCCORE26 VCCCORE27 VCCCORE28 VCCCORE20 VCCCORE21 VCCCORE22 VCCCORE23 VCCCORE30 VCCCORE32 VCCCORE33 VCCCORE29 VCCCORE31 VCCCORE39 VCCCORE40 VCCCORE41 VCCCORE42 VCCCORE43 VCCCORE34

RSVD3 RSVD4 RSVD1 RSVD2

SVID ALERT

B B

12 of 20

+1.05V_V CCST

12

VCCCORE35 VCCCORE36 VCCCORE37 VCCCORE38 VCCCORE44 VCCCORE45 VCCCORE48 VCCCORE49 VCCCORE50 VCCCORE46 VCCCORE47 VCCCORE51 VCCCORE52 VCCCORE56 VCCCORE57 VCCCORE58 VCCCORE59 VCCCORE53 VCCCORE54 VCCCORE55 VCCCORE63 VCCCORE64 VCCCORE60 VCCCORE61 VCCCORE62 VCCCORE69 VCCCORE65 VCCCORE66 VCCCORE67 VCCCORE68 VCCCORE70 VCCCORE73 VCCCORE71 VCCCORE72 VCCCORE74

VCC_SENSE VSS_SENSE

VIDALERT#

AW24 AW25 AW26 AW27 AY24 AY26 BA5 BA7 BA8 BA25 BA27 BB2 BB26 BC5 BC6 BC7 BC9 BC10 BC26 BC27 BD5 BD8 BD10 BD25 BD27 BE9 BE24 BE25 BE26 BE27 BF2 BF9 BF24 BF26 BG27

AN6 AN5

AA3

AA1

VIDSCK

AA2

VIDSOUT

Y3

RSVD5

BG3

VCCSTG1

Place the PU resistors close to CPU

RC94 56_0402 _5%

4

SOC_SVID_ ALERT#

VR_SVID_C LK

VR_SVID_D ATA

VCCCORE _SENSE <4 6>

VSSCORE _SENSE <46>

VR_SVID_C LK <46>

+1.05VS_ VCCSTG

3

Trace Length Match < 25 mils

+VCCCOR E

2

+VCC_GT +VCC_GT

UC1M

A5

VCCGT8

A6

VCCGT9

A8

VCCGT10

A11

VCCGT1

A12

VCCGT2

A14

VCCGT3

A15

VCCGT4

A17

VCCGT5

A18

VCCGT6

A20

VCCGT7

AA9

VCCGT11

AB2

VCCGT13

AB8

VCCGT14

AB9

VCCGT15

AB10

VCCGT12

AC8

VCCGT16

AD9

VCCGT17

AE8

VCCGT19

AE9

VCCGT20

AE10

VCCGT18

AF2

VCCGT22

AF8

VCCGT23

AF10

VCCGT21

AG8

VCCGT24

AG9

VCCGT25

AH9

VCCGT26

AJ8

VCCGT28

AJ10

VCCGT27

AK2

VCCGT29

AK9

VCCGT30

AL8

VCCGT32

AL9

VCCGT33

AL10

VCCGT31

AM8

VCCGT34

B3

VCCGT39

B4

VCCGT40

B6

VCCGT41

B8

VCCGT42

B11

VCCGT35

B14

VCCGT36

B17

VCCGT37

B20

VCCGT38

C2

VCCGT49

C3

VCCGT51

C6

VCCGT52

C7

VCCGT53

C8

VCCGT54

C11

VCCGT43

C12

VCCGT44

C14

VCCGT45

C15

VCCGT46

C17

VCCGT47

C18

VCCGT48

C20

VCCGT50

D4

VCCGT62

D7

VCCGT63

D11

VCCGT55

D12

VCCGT56

D14

VCCGT57

Y10

VCCGT119

WHL -U42_BGA1528

VCCGT_SENSE VSSGT_SENSE

13 of 20

VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT64 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT87 VCCGT88 VCCGT89 VCCGT90 VCCGT80 VCCGT81 VCCGT82 VCCGT83 VCCGT84 VCCGT85 VCCGT86 VCCGT95 VCCGT96 VCCGT91 VCCGT92 VCCGT93 VCCGT94 VCCGT98

VCCGT97 VCCGT100 VCCGT101

VCCGT99 VCCGT102 VCCGT104 VCCGT105 VCCGT106 VCCGT103 VCCGT107 VCCGT108 VCCGT109 VCCGT111 VCCGT112 VCCGT110 VCCGT114 VCCGT113 VCCGT115 VCCGT116 VCCGT117 VCCGT118 VCCGT120

D15 D17 D18 D20 E4 F5 F6 F7 F8 F11 F14 F17 F20 G11 G12 G14 G15 G17 G18 G20 H5 H6 H7 H8 H11 H12 H14 H15 H17 H18 H20 J7 J8 J11 J14 J17 J20 K2 K11 L7 L8 L10 M9 N7 N8 N9 N10 P2 P8 R9 T8 T9 T10 U8 U10 V2 V9 W8 W9 Y8

VCCGT_S ENSE

E3

VSSGT_S ENSE

D2

1

VCCGT_S ENSE <4 6> VSSGT_S ENSE <46>

Trace Length Match < 25 mils

SOC_SVID_ ALERT#

SVID DATA

VR_SVID_D ATA

A A

5

1 2

RC95 220_ 0402_5%

+1.05V_V CCST

Place the PU resistors close to CPU

12

RC96 100_040 2_1%

VR_ALER T# <46>

VR_SVID_D ATA <46>

Compal For Lenovo

4

(To VR)

Security Classification

2017/5/3 2017/6/2

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/5/3 2017/6/2

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

WHL-U(10/12)Power,SVID

LA-G651P

15 52Friday, May 18, 201 8

1

0.2

5

D D

UC1R

CR34

VSS_1

BT5

VSS_2

BY5

VSS_3

CP35

VSS_4

CM37

VSS_5

CK37

VSS_6

AW1

VSS_7

CM1

VSS_8

BD6

VSS_9

AY4

VSS_10

B34

VSS_11

E35

VSS_12

A4

VSS_13

AE24

VSS_14

AE26

VSS_15

AF25

VSS_16

AG24

VSS_17

AG26

VSS_18

AH24

VSS_19

AH25

VSS_20

B2

VSS_21

B36

VSS_22

C36

VSS_23

C37

C C

B B

CN1 CN2

CN37

CP2

D1

A32

F33

A3

BJ7

CJ36

A36

BK10

CJ4

AB27

BK2 CK1

AB3 BK28 AB30

BK3

CK4 AB33 BK33

CK7 AB36

BK4

CL2

AB4

BK7

CM13

AB7 BL25

CM17

AC10 BL28

CM21

AC27 BL29

CM25

AC30 BL30

CM29

BL31

CM31

AD33 BL32

CM33

AD35

WHL -U42_BGA1528

VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72

17 of 20

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144

BL7 AE25 BM33 CM5 AE27 BM35 CM9 AE30 BM36 CN13 AE7 BM9 CN17 AF27 BN30 CN21 AF3 BN7 CN25 AF30 CN29 AF33 BP15 AF36 AF4 CN5 AF7 BP25 CN9 AG10 BP3 CP1 BP32 CP11 AH27 BP33 CP13 AH28 BP4 CP15 AH29 BP7 CP19 AH30 CP21 AH31 BR19 CP27 AH33 BR25 AH35 CP37 AJ25 BT15 AJ28 BT16 CP9 AJ7 CR2 AK3 CR36 AK33 D21 AK36 BT25 D25 AK4 BT28 AL28 BT33 D5 AL29

4

UC1S

BT35

VSS_145

D6

VSS_146

AL32

VSS_147

BT36

VSS_148

D8

VSS_149

AL7

VSS_150

D9

VSS_151

AM10

VSS_152

BU11

VSS_153

E23

VSS_154

AM28

VSS_155

E27

VSS_156

AM33

VSS_157

BU23

VSS_158

E29

VSS_159

AM35

VSS_160

BU24

VSS_161

E31

VSS_162

BU25

VSS_163

E33

VSS_164

AN25

VSS_165

BU7

VSS_166

E9

VSS_167

AN28

VSS_168

BV11

VSS_169

F12

VSS_170

AN29

VSS_171

F15

VSS_172

AN30

VSS_173

F18

VSS_174

AN31

VSS_175

BV3

VSS_176

F2

VSS_177

AN7

VSS_178

BV31

VSS_179

F21

VSS_180

AN8

VSS_181

BV33

VSS_182

F24

VSS_183

BV4

VSS_184

F3

VSS_185

AP3

VSS_186

BW11

VSS_187

F4

VSS_188

AP33

VSS_189

BW15

VSS_190

G21

VSS_191

AP36

VSS_192

G27

VSS_193

AP4

VSS_194

G33

VSS_195

AR28

VSS_196

G35

VSS_197

G36

VSS_198

AT33

VSS_199

BW24

VSS_200

G9

VSS_201

AT35

VSS_202

H21

VSS_203

AT36

VSS_204

BW7

VSS_205

H27

VSS_206

AT4

VSS_207

BY11

VSS_208

AU10

VSS_209

BY15

VSS_210

H9

VSS_211

AU28

VSS_212

BY22

VSS_213

J12

VSS_214

AU29

VSS_215

J15

VSS_216

WHL -U42_BGA1528

18 of 20

VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289

3

BY25 J18 AU32 BY28 J21 AV25 BY33 J24 AV28 BY35 J33 AV3 BY36 J36 AV33 J6 AV36 C1 K21 AV4 C21 K22 AV6 C25 K24 AV8 C29 K25 AW28 C33 K27 AW29 C4 K28 AW3 C9 K29 AW30 CA11 K3 AW31 CA15 K30 AY33 CA22 K31 AY35 K32 B12 K4 B15 CA25 K9 B18 CB11 L27 B21 L33 B23 L35 B25 CB18 L36 B27 CB19 L6 B29 CB2 N25 B31 CB20 N27 CB25

2

UC1T

N6

VSS_290

B37

VSS_291

CB3

VSS_292

P10

VSS_293

B5

VSS_294

CB33

VSS_295

P3

VSS_296

B7

VSS_297

CB4

VSS_298

P33

VSS_299

B9

VSS_300

CB7

VSS_301

P36

VSS_302

BA10

VSS_303

CC11

VSS_304

P4

VSS_305

BA28

VSS_306

P7

VSS_307

BA3

VSS_308

CC20

VSS_309

R27

VSS_310

BB3

VSS_311

CC25

VSS_312

R28

VSS_313

BB33

VSS_314

CC28

VSS_315

R29

VSS_316

BB36

VSS_317

CC31

VSS_318

R30

VSS_319

BB4

VSS_320

CC7

VSS_321

R31

VSS_322

BC25

VSS_323

CD11

VSS_324

T27

VSS_325

CD12

VSS_326

T30

VSS_327

BC29

VSS_328

CD14

VSS_329

T33

VSS_330

T35

VSS_331

BC32

VSS_332

CD24

VSS_333

T36

VSS_334

CD25

VSS_335

T7

VSS_336

BC8

VSS_337

CE33

VSS_338

U26

VSS_339

BD28

VSS_340

CE35

VSS_341

U7

VSS_342

BD33

VSS_343

CE36

VSS_344

V26

VSS_345

BD35

VSS_346

CE7

VSS_347

V27

VSS_348

BD36

VSS_349

CF11

VSS_350

V3

VSS_351

BE10

VSS_352

CF14

VSS_353

V30

VSS_354

BE28

VSS_355

CF19

VSS_356

V33

VSS_357

BE29

VSS_358

CF2

VSS_359

V36

VSS_360

BE3

VSS_361

WHL -U42_BGA1528

19 of 20

VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433

CF23 V4 BE30 CF28 W10 BE31 CF3 W27 CF4 W30 BF3 CG33 W7 BF33 CG7 BF36 Y26 BF4 CH31 Y27 BG25 Y30 BG28 CJ11 Y33 CJ14 Y35 BH28 CJ19 Y7 BH29 CJ23 BH32 CJ28 BH33 CJ33 BH35 CJ35 BP19 BR16 BY18 BY19 CC16 BU16 CC14 BR22 BU20 CD20 BT14 BP12 CB24 CC24 J5 U24 BD7 AR4 AU4 AW4 BA6 BC4 BE4 BE8 BA4 BD4 BG4 CJ2 CJ3 AM5 CM4 AC5 AG5 CR6

1

A A

Security Classification

2017/5/3 2017/6/2

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/5/3 2017/6/2

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

WHL-U(11/12)GND

LA-G651P

1

0.2

16 52Friday, May 18, 201 8

5

+1.05VS_ VCCIO

D D

4

3

2

1

1 2

RC459 10K_040 2_5%@

1 2

@

RC460 1K_040 2_5%

C C

B B

RC100 49.9_04 02_1%

RC101 1K_040 2_5%

1 2

CFG0

CFG3

CFG_RCO MP

CFG4

CFG0

CFG3 CFG4

CFG_RCO MP

T4

CFG_0

R4

CFG_1

T3

CFG_2

R3

CFG_3

J4

CFG_4

M4

CFG_5

J3

CFG_6

M3

CFG_7

R2

CFG_8

N2

CFG_9

R1

CFG_10

N1

CFG_11

J2

CFG_12

L2

CFG_13

J1

CFG_14

L1

CFG_15

L3

CFG_16

N3

CFG_18

L4

CFG_17

N4

CFG_19

AB5

CFG_RCOMP

W4

ITP_PMODE

CG2

RSVD25

CG1

RSVD24

H4

RSVD34

H3

RSVD33

BV24

RSVD22

BV25

RSVD23

G3

VSS_436

G4

VSS_437

BK36

RSVD17

BK35

RSVD16

W3

RSVD35

AM4

RSVD7

AM3

RSVD6

A35

RSVD1

D34

RSVD30

G2

RSVD32

G1

RSVD31

WHL -U42_BGA1528

UC1Q

20 of 20

RSVD_TP5 RSVD_TP4

IST_TRIG

RSVD_TP3

RSVD15 RSVD14

TP_1 TP_3

RSVD21 RSVD20

RSVD18 RSVD19

RSVD29

RSVD26 RSVD27

RSVD12 RSVD13

RSVD8 RSVD9

RSVD11 RSVD10

RSVD3 RSVD2

RSVD5 RSVD4

TP1 TP_2 TP_4

VSS_435

RSVD_TP1 RSVD_TP2

RSVD28

ZVM# MSM#

SKTOCC#

F37 F34

CP36 CN36

BJ36 BJ34

BK34 BR18

BT9 BT8

BP8 BP9

CR4

CP3 CR3

AT3 AU3

AN1 AN2

AN4 AN3

AL2 AL1

AL4 AL3

BP34 BP36 BP35

C34

A34 B35

CR35

AH26 AJ27

E1

SOC_TP2

1 2

@

RC462 0_0402 _5%

Need connect to GND for WHL/CNL

RSVD28

T2407TP@

Follow Intel suggetion reserve TP

DFX Privacy Strap

1 : Disabled;

CFG3

A A

Set DFX disable bit in debug interface MSR

0 : Enabled; Set DFX enable bit in debug interface MSR

UC1. G3 UC1. G4 UC1.C34

NC for WHL/CNL Connect to GND for CFL-U43e

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port at t ached t o E mbedded Di spl ay port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

Compal For Lenovo

5

4

Security Classification

2017/5/3 2017/6/2

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/5/3 2017/6/2

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

WHL-U(12/12)CFG,RSVD

LA-G651P

17 52Friday, May 18, 201 8

1

0.2

5

<LPDDR3_A_DQ>

D D

<LPDDR3_B_DQ>

C C

+VREFDQ _A

+VREFDQ _B

+1.2V

RD71

8.2K_040 2_1%

RD74

8.2K_040 2_1%

+1.2V

RD79

8.2K_040 2_1%

RD81

8.2K_040 2_1%

12

RD72

1 2

10_0402 _1%

RD80

1 2

10_0402 _1%

4

1

CD9

0.022U_0 402_25V7K

2

12

RD76

24.9_040 2_1%

1

CD11

0.022U_0 402_25V7K

2

12

RD82

24.9_040 2_1%

+V_DDR_ REFA_C

+V_DDR_ REFB_C

<CPU>

3

<CPU>

+1.2V

+VREF_C A_C

1

+

2

@

CD10

0.022U_0 402_25V7K

24.9_040 2_1%

CD12 330U_D3 _2.5VY_R6M

RD77

1

2

12

RD75

1 2

5.11_040 2_1%

+1.2V

2

12

RD73

8.2K_040 2_1%

12

RD78

8.2K_040 2_1%

+VREFCA

1

<LPDDR3_A_CA>

<LPDDR3_B_CA>

Update Cap Q'ty to follow Intel 561280_KBL UY PDG Rev2_0

Close to RAM

CD60

1U_0201_6.3V6M

12

Close to RAM

1U_0201_6.3V6M

CD94

1

2

1

2

+1.8V_ME M

CD33

10P_0402_50V8J

1

RF@

2

CD93

10P_0402_50V8J

RF@

CD34

10U_0402_6.3V6M

2019/2/5

VDD1 DECAPS (10UF * 5 / 1UF * 8)VTT DECAPS (22UF * 2 / 1UF * 8)

CD39

CD38

10U_0402_6.3V6M

CD36

CD35

1

2

+1.2V

2

10U_0402_6.3V6M

CD37

10U_0402_6.3V6M

1

2

1

2

VDDCA DECAPS 10UF * 3 / 1UF * 8

CD62

CD61

1

@

2

CD81

12

10U_0402_6.3V6M

1U_0201_6.3V6M

CD63

10U_0402_6.3V6M

1

@

2

CD82

CD83

1U_0201_6.3V6M

12

@

Title

Size Document Number Re v

Date : Sheet o f

1U_0201_6.3V6M

12

@

CD85

CD84

1U_0201_6.3V6M

12

Compal Electronics, Inc.

Friday, May 18, 2018

CD41

CD40

1U_0201_6.3V6M

12

@

CD86

1U_0201_6.3V6M

12

LPDDR3 VREF

LA-G651P

CD31

CD42

1U_0201_6.3V6M

12

@

CD87

CD88

1U_0201_6.3V6M

12

@

1

CD77

CD32

1U_0201_6.3V6M

12

@

1U_0201_6.3V6M

0.2

5218

+1.2V

B B

A A

VDDQ DECAPS (10UF * 5 / 1UF *12 / 0.1UF *8)

CD18

CD19

CD15

CD14

CD13

10U_0402_6.3V6M

1

@

CD69

2

CD43

1U_0201_6.3V6M

12

@

CD70

0.1U_0201_10V6K

1

2

+1.2V

12

10U_0402_6.3V6M

1

@

2

CD44

CD45

1U_0201_6.3V6M

12

@

CD71

0.1U_0201_10V6K

1

2

CD89

CD90

1U_0201_6.3V6M

12

@

CD17

CD16

10U_0402_6.3V6M

1

@

2

CD47

CD46

1U_0201_6.3V6M

12

@

CD73

CD72

0.1U_0201_10V6K

1

2

CD92

CD91

1U_0201_6.3V6M

12

1U_0201_6.3V6M

10U_0402_6.3V6M

12

CD48

CD49

1U_0201_6.3V6M

12

CD75

CD74

0.1U_0201_10V6K

1

2

1U_0201_6.3V6M

CD20

1U_0201_6.3V6M

12

Close to RAM

CD50

1U_0201_6.3V6M

12

@

CD76

0.1U_0201_10V6K

1

2

Compal For Lenovo

5

4

+0.6VS

CD23

CD24

CD21

CC3869

10P_0402_50V8J

1

RF@

2

CD51

1U_0201_6.3V6M

12

22U_0603_6.3V6M

CD22

22U_0603_6.3V6M

1

@

2

+1.2V

CD52

1U_0201_6.3V6M

12

@

+1.2V +1.2V

CD64

10U_0402_6.3V6M

1

2

1U_0201_6.3V6M

12

@

VDD2 DECAPS 1UF * 12 / 10UF * 5

CD53

1U_0201_6.3V6M

12

CD66

CD65

10U_0402_6.3V6M

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CD25

1U_0201_6.3V6M

12

@

CD54

CD55

1U_0201_6.3V6M

12

@

10U_0402_6.3V6M

CD67

10U_0402_6.3V6M

1

2

CD27

CD28

CD29

CD26

1U_0201_6.3V6M

12

CD56

1U_0201_6.3V6M

12

@

CD68

10U_0402_6.3V6M

1

@

2

2018/2/5

3

1U_0201_6.3V6M

12

@

CD57

1U_0201_6.3V6M

12

CD30

1U_0201_6.3V6M

12

@

CD59

CD58

1U_0201_6.3V6M

12

@

CD79

CD78

1U_0201_6.3V6M

12

Compal Secret Data

Deciphered Date

CD80

12

5

4

3

2

1

+0.6VS+1.8V_MEM

+0.6VS

+1.2V

+1.8V_MEM

UD2

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JT MLAR-NTM_FBGA178~D

Vref_DQ Vref_CA

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0 DQS1 DQS2 DQS3

DQS0# DQS1# DQS2# DQS3#

CKE0 CKE1

CS0# CS1#

P9

DQ0

N9

DQ1

N10

DQ2

N11

DQ3

M8

DQ4

M9

DQ5

M10

DQ6

M11

DQ7

F11

DQ8

F10

DQ9

F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

L10 G10 P10 D10

L11 G11 P11 D11

L8

DM0

G8

DM1

P8

DM2

D8

DM3

B3

RD30 2 43_0402_1%

ZQ0

B4

RD32 2 43_0402_1%

ZQ1

K3 K4

L3 L4

J3

CK

J2

CK#

J8

ODT

J11 H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

DDR_A_CAA0 DDR_A_CAA1 DDR_A_CAA2 DDR_A_CAA3 DDR_A_CAA4 DDR_A_CAA5 DDR_A_CAA6 DDR_A_CAA7 DDR_A_CAA8 DDR_A_CAA9

1 2

CHA@

1 2

CHA@

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_CLK0DDR_A_CLK1

DDR_A_ODT0

+VREFDQ_A +VREFCA

+VREFCA

+VREFDQ_A

DDR_A_D1 <7> DDR_A_D7 <7> DDR_A_D2 <7> DDR_A_D5 <7> DDR_A_D3 <7> DDR_A_D6 <7> DDR_A_D4 <7> DDR_A_D0 <7> DDR_A_D24 <7> DDR_A_D29 <7> DDR_A_D31 <7> DDR_A_D30 <7> DDR_A_D25 <7> DDR_A_D28 <7> DDR_A_D26 <7> DDR_A_D27 <7> DDR_A_D13 <7> DDR_A_D9 <7> DDR_A_D12 <7> DDR_A_D15 <7> DDR_A_D8 <7> DDR_A_D10 <7> DDR_A_D11 <7> DDR_A_D14 <7> DDR_A_D16 <7> DDR_A_D18 <7> DDR_A_D20 <7> DDR_A_D17 <7> DDR_A_D19 <7> DDR_A_D23 <7> DDR_A_D21 <7> DDR_A_D22 <7>

DDR_A_CAA0 <7> DDR_A_CAA1 <7> DDR_A_CAA2 <7> DDR_A_CAA3 <7> DDR_A_CAA4 <7> DDR_A_CAA5 <7> DDR_A_CAA6 <7> DDR_A_CAA7 <7> DDR_A_CAA8 <7> DDR_A_CAA9 <7>

DDR_A_DQS0 <7> DDR_A_DQS3 <7> DDR_A_DQS1 <7> DDR_A_DQS2 <7>

DDR_A_DQS#0 < 7> DDR_A_DQS#3 < 7> DDR_A_DQS#1 < 7> DDR_A_DQS#2 < 7>

DDR_A_CKE0 <7> DDR_A_CKE1 <7>

DDR_A_CS#0 <7>

DDR_A_CS#1 <7>

DDR_A_CLK0 <7> DDR_A_CLK#0 < 7>

DDR_A_ODT0 <7>

1

2

1

2

.047U_0402_16V7K

CD2

.047U_0402_16V7K

CD4

CHA@

CHA_Group{0}

CHA_Group{3}

CHA_Group{1}

CHA_Group{2}

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3

DDR_A_CLK#0

DDR_A_CLK0

DDR_A_CLK#1

DDR_A_CLK1

DDR_A_CAA0 DDR_A_CAA1 DDR_A_CAA2 DDR_A_CAA3 DDR_A_CAA4 DDR_A_CAA5 DDR_A_CAA6 DDR_A_CAA7 DDR_A_CAA8 DDR_A_CAA9 DDR_A_CAB0 DDR_A_CAB1 DDR_A_CAB2 DDR_A_CAB3 DDR_A_CAB4 DDR_A_CAB5 DDR_A_CAB6 DDR_A_CAB7 DDR_A_CAB8 DDR_A_CAB9

RD21 80.6_0201_1%CHA@ RD22 80.6_0201_1%CHA@ RD23 80.6_0201_1%CHA@ RD24 80.6_0201_1%CHA@ RD25 80.6_0201_1%CHA@ RD26 80.6_0201_1%CHA@ RD27 80.6_0201_1%CHA@

RD28

CHA@

37.4_0201_1%

RD33

CHA@

37.4_0201_1%

RD34

CHA@

37.4_0201_1%

RD35

CHA@

37.4_0201_1%

RD1 68_02 01_1%CHA@ RD2 68_02 01_1%CHA@ RD3 68_02 01_1%CHA@ RD4 68_02 01_1%CHA@ RD5 68_02 01_1%CHA@ RD6 68_02 01_1%CHA@ RD7 68_02 01_1%CHA@ RD8 68_02 01_1%CHA@ RD9 68_02 01_1%CHA@ RD10 6 8_0201_1%C HA@ RD11 6 8_0201_1%C HA@ RD12 6 8_0201_1%C HA@ RD13 6 8_0201_1%C HA@ RD14 6 8_0201_1%C HA@ RD15 6 8_0201_1%C HA@ RD16 6 8_0201_1%C HA@ RD17 6 8_0201_1%C HA@ RD18 6 8_0201_1%C HA@ RD19 6 8_0201_1%C HA@ RD20 6 8_0201_1%C HA@

12 12 12 12 12 12 12

12

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

+0.6VS

UD1

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

D D

+1.2V

C C

+1.2V +1.2V

B B

A A

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JT MLAR-NTM_FBGA178~D

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0 DQS1 DQS2 DQS3

DQS0# DQS1# DQS2# DQS3#

CKE0 CKE1

CS0# CS1#

Vref_DQ

Vref_CA

P9

DQ0

N9

DQ1

N10

DQ2

N11

DQ3

M8

DQ4

M9

DQ5

M10

DQ6

M11

DQ7

F11

DQ8

F10

DQ9

F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

DDR_A_CAB0

R2

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

DM0 DM1 DM2 DM3

ZQ0 ZQ1

CK#

ODT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR_A_CAB1

P2

DDR_A_CAB2

N2

DDR_A_CAB3

N3

DDR_A_CAB4

M3

DDR_A_CAB5

F3

DDR_A_CAB6

E3

DDR_A_CAB7

E2

DDR_A_CAB8

D2

DDR_A_CAB9

C2

L10 G10 P10 D10

L11 G11 P11 D11

L8 G8 P8 D8

1 2

B3

RD29 2 43_0402_1%CHA@

B4

1 2

RD31 2 43_0402_1%CHA@

DDR_A_CKE2

K3

DDR_A_CKE3

K4

DDR_A_CS#0

L3

DDR_A_CS#1

L4

J3

CK

DDR_A_CLK#1 DDR_A_CLK#0

J2

DDR_A_ODT0

J8

J11 H4

B2 B5 C5 E4 E5 F5 H2 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5

DDR_A_D46 <7> DDR_A_D43 <7> DDR_A_D41 <7> DDR_A_D40 <7> DDR_A_D47 <7> DDR_A_D42 <7> DDR_A_D45 <7> DDR_A_D44 <7> DDR_A_D34 <7> DDR_A_D38 <7> DDR_A_D37 <7> DDR_A_D36 <7> DDR_A_D35 <7> DDR_A_D39 <7> DDR_A_D33 <7> DDR_A_D32 <7> DDR_A_D53 <7> DDR_A_D49 <7> DDR_A_D55 <7> DDR_A_D54 <7> DDR_A_D52 <7> DDR_A_D48 <7> DDR_A_D51 <7> DDR_A_D50 <7> DDR_A_D60 <7> DDR_A_D61 <7> DDR_A_D62 <7> DDR_A_D59 <7> DDR_A_D57 <7> DDR_A_D56 <7> DDR_A_D63 <7> DDR_A_D58 <7>

DDR_A_CAB0 <7> DDR_A_CAB1 <7> DDR_A_CAB2 <7> DDR_A_CAB3 <7> DDR_A_CAB4 <7> DDR_A_CAB5 <7> DDR_A_CAB6 <7> DDR_A_CAB7 <7> DDR_A_CAB8 <7> DDR_A_CAB9 <7>

DDR_A_CKE2 <7> DDR_A_CKE3 <7>

DDR_A_CLK1 <7> DDR_A_CLK#1 < 7>

+VREFDQ_A +VREFCA

+VREFCA

+VREFDQ_A

DDR_A_DQS5 <7> DDR_A_DQS4 <7> DDR_A_DQS6 <7> DDR_A_DQS7 <7>

DDR_A_DQS#5 < 7> DDR_A_DQS#4 < 7> DDR_A_DQS#6 < 7> DDR_A_DQS#7 < 7>

1

2

1

2

CHA_Group{5}

CHA_Group{4}

CHA_Group{6}

CHA_Group{7}

.047U_0402_16V7K

CD1

.047U_0402_16V7K

CD3

CHA@

Security Classific ation

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number R ev

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

LPDDR3_A

LA-G651P

1

19 5 2Friday, May 18, 2018

0.2

5

4

3

2

1

+1.8V_MEM +1.8V_MEM

D D

+1.2V

C C

+1.2V +1.2V

B B

A A

UD3

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JT MLAR-NTM_FBGA178~D

Vref_DQ

Vref_CA

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0 DQS1 DQS2 DQS3

DQS0# DQS1# DQS2# DQS3#

DM0

DM1

DM2

DM3

CKE0 CKE1

CS0# CS1#

ODT

VSS

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

L10 G10 P10 D10

L11 G11 P11 D11

L8 G8 P8 D8

B3

ZQ0

B4

ZQ1

K3 K4

L3 L4

J3

CK

J2

CK#

J8

J11 H4

B2 B5 C5 E4 E5 F5 H2 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5

UD4

@

DDR_B_D42 <7> DDR_B_D47 <7> DDR_B_D44 <7> DDR_B_D41 <7> DDR_B_D43 <7> DDR_B_D46 <7> DDR_B_D40 <7> DDR_B_D45 <7> DDR_B_D51 <7> DDR_B_D55 <7> DDR_B_D49 <7> DDR_B_D53 <7> DDR_B_D50 <7> DDR_B_D54 <7> DDR_B_D48 <7> DDR_B_D52 <7> DDR_B_D32 <7> DDR_B_D36 <7> DDR_B_D39 <7> DDR_B_D34 <7> DDR_B_D33 <7> DDR_B_D37 <7> DDR_B_D35 <7> DDR_B_D38 <7> DDR_B_D56 <7> DDR_B_D60 <7> DDR_B_D58 <7> DDR_B_D63 <7> DDR_B_D57 <7> DDR_B_D61 <7> DDR_B_D59 <7>

DDR_B_CAB0 DDR_B_CAB1 DDR_B_CAB2 DDR_B_CAB3 DDR_B_CAB4 DDR_B_CAB5 DDR_B_CAB6 DDR_B_CAB7 DDR_B_CAB8 DDR_B_CAB9

1 2

RD63 243_04 02_1%

1 2

RD64 243_04 02_1%

DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1

DDR_B_CLK1 DDR_B_CLK#1 DDR_B_CLK#0

DDR_B_ODT0

DDR_B_D62 <7>

DDR_B_CAB0 <7> DDR_B_CAB1 <7> DDR_B_CAB2 <7> DDR_B_CAB3 <7> DDR_B_CAB4 <7> DDR_B_CAB5 <7> DDR_B_CAB6 <7> DDR_B_CAB7 <7> DDR_B_CAB8 <7> DDR_B_CAB9 <7>

DDR_B_DQS5 <7> DDR_B_DQS6 <7> DDR_B_DQS4 <7> DDR_B_DQS7 <7>

DDR_B_DQS#5 <7 > DDR_B_DQS#6 <7 > DDR_B_DQS#4 <7 > DDR_B_DQS#7 <7 >

DDR_B_CKE2 <7> DDR_B_CKE3 <7>

DDR_B_CLK1 <7> DDR_B_CLK0 <7 > DDR_B_CLK#1 <7>

+VREFDQ_B +VREFCA

+VREFCA

+VREFDQ_B

.047U_0402_16V7K

1

CD5

2

.047U_0402_16V7K

1

CD7

2

CHB_Group{5}

+1.2V+1.2V

CHB_Group{6}

CHB_Group{4}

CHB_Group{7}

+1.2V

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JT MLAR-NTM_FBGA178~D

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0 DQS1 DQS2 DQS3

DQS0# DQS1# DQS2# DQS3#

CKE0 CKE1

CS0# CS1#

Vref_DQ Vref_CA

P9

DQ0

N9

DQ1

N10

DQ2

N11

DQ3

M8

DQ4

M9

DQ5

M10

DQ6

M11

DQ7

F11

DQ8

F10

DQ9

F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

DDR_B_CAA0

R2

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

DM0 DM1 DM2 DM3

ZQ0 ZQ1

CK#

ODT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR_B_CAA1

P2

DDR_B_CAA2

N2

DDR_B_CAA3

N3

DDR_B_CAA4

M3

DDR_B_CAA5

F3

DDR_B_CAA6

E3

DDR_B_CAA7

E2

DDR_B_CAA8

D2

DDR_B_CAA9

C2

L10 G10 P10 D10

L11 G11 P11 D11

L8 G8 P8 D8

B3

RD67 243_04 02_1%

B4

RD65 243_04 02_1%

DDR_B_CKE0

K3

DDR_B_CKE1

K4

DDR_B_CS#0

L3

DDR_B_CS#1

L4

DDR_B_CLK0

J3

CK

J2

DDR_B_ODT0

J8

J11 H4

B2 B5 C5 E4 E5 F5 H2 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5

1 2 1 2

+VREFDQ_B +VREFCA

DDR_B_D17 <7> DDR_B_D16 <7> DDR_B_D18 <7> DDR_B_D19 <7> DDR_B_D22 <7> DDR_B_D23 <7> DDR_B_D21 <7> DDR_B_D20 <7> DDR_B_D30 <7> DDR_B_D26 <7> DDR_B_D25 <7> DDR_B_D24 <7> DDR_B_D31 <7> DDR_B_D27 <7> DDR_B_D29 <7> DDR_B_D28 <7> DDR_B_D4 <7> DDR_B_D1 <7> DDR_B_D3 <7> DDR_B_D7 <7> DDR_B_D0 <7> DDR_B_D5 <7> DDR_B_D6 <7> DDR_B_D2 <7> DDR_B_D9 <7> DDR_B_D13 <7> DDR_B_D14 <7> DDR_B_D10 <7> DDR_B_D12 <7> DDR_B_D8 <7> DDR_B_D15 <7> DDR_B_D11 <7>

DDR_B_CAA0 <7> DDR_B_CAA1 <7> DDR_B_CAA2 <7> DDR_B_CAA3 <7> DDR_B_CAA4 <7> DDR_B_CAA5 <7> DDR_B_CAA6 <7> DDR_B_CAA7 <7> DDR_B_CAA8 <7> DDR_B_CAA9 <7>

DDR_B_DQS2 <7 > DDR_B_DQS3 <7 > DDR_B_DQS0 <7 > DDR_B_DQS1 <7 >

DDR_B_DQS#2 < 7> DDR_B_DQS#3 < 7> DDR_B_DQS#0 < 7> DDR_B_DQS#1 < 7>

DDR_B_CKE0 <7> DDR_B_CKE1 <7>

DDR_B_CS#0 <7> DDR_B_CS#1 <7>

DDR_B_CLK#0 <7>

DDR_B_ODT0 <7>

+VREFCA

+VREFDQ_B

CHB_Group{2}

CHB_Group{3}

CHB_Group{0}

CHB_Group{1}

.047U_0402_16V7K

1

CD6

2

.047U_0402_16V7K

1

CD8

2

DDR_B_CAA0 DDR_B_CAA1 DDR_B_CAA2 DDR_B_CAA3 DDR_B_CAA4 DDR_B_CAA5 DDR_B_CAA6 DDR_B_CAA7 DDR_B_CAA8 DDR_B_CAA9 DDR_B_CAB0 DDR_B_CAB1 DDR_B_CAB2 DDR_B_CAB3 DDR_B_CAB4 DDR_B_CAB5 DDR_B_CAB6 DDR_B_CAB7 DDR_B_CAB8 DDR_B_CAB9

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CLK#0

DDR_B_CLK0

DDR_B_CLK#1

DDR_B_CLK1

RD66

37.4_0201_1%

12

RD68

37.4_0201_1%

12

RD69

37.4_0201_1%

12

RD70

37.4_0201_1%

12

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

12 12 12 12 12 12 12

RD36 6 8_0201_1% RD37 6 8_0201_1% RD38 6 8_0201_1% RD39 6 8_0201_1% RD40 6 8_0201_1% RD41 6 8_0201_1% RD42 6 8_0201_1% RD43 6 8_0201_1% RD44 6 8_0201_1% RD45 6 8_0201_1% RD46 6 8_0201_1% RD47 6 8_0201_1% RD48 6 8_0201_1% RD49 6 8_0201_1% RD50 6 8_0201_1% RD51 6 8_0201_1% RD53 6 8_0201_1% RD52 6 8_0201_1% RD54 6 8_0201_1% RD55 6 8_0201_1%

RD56 80.6_0201_1% RD57 80.6_0201_1% RD58 80.6_0201_1% RD59 80.6_0201_1% RD60 80.6_0201_1% RD61 80.6_0201_1% RD62 80.6_0201_1%

+0.6VS

Security Classific ation

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number R ev

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

LPDDR3_B

LA-G651P

1

20 5 2Friday, May 18, 2018

0.2

1

PLT_RST_VGA#

CLKREQ_PCIE#0_R

A A

PCIE CLK

PCIE X4 Bus

CLK_PCIE_P0<10> CLK_PCIE_N0<10>

PCIE_CRX_DTX_P13<12> PCIE_CRX_DTX_N13<12>

PCIE_CTX_C_DRX_P13<12> PCIE_CTX_C_DRX_N13<12 >

PCIE_CRX_DTX_P14<12> PCIE_CRX_DTX_N14<12>

PCIE_CTX_C_DRX_P14<12> PCIE_CTX_C_DRX_N14<12 >

PCIE_CRX_DTX_P15<12> PCIE_CRX_DTX_N15<12>

PCIE_CTX_C_DRX_P15<12> PCIE_CTX_C_DRX_N15<12 >

PCIE_CRX_DTX_P16<12> PCIE_CRX_DTX_N16<12>

PCIE_CTX_C_DRX_P16<12> PCIE_CTX_C_DRX_N16<12 >

CV11 0.22U_0201_6.3V6MDIS@ CV12 0.22U_0201_6.3V6MDIS@

CV13 0.22U_0201_6.3V6MDIS@ CV14 0.22U_0201_6.3V6MDIS@

CV15 0.22U_0201_6.3V6MDIS@ CV16 0.22U_0201_6.3V6MDIS@

CV17 0.22U_0201_6.3V6MDIS@ CV18 0.22U_0201_6.3V6MDIS@

Near U V1

B B

Reset Control

1.8V AND GATE

C C

(From PC H)

PCI_RST#<10,32,34 >

DGPU_HOLD_RS T#<11>

PCI_RST#

DGPU_HOLD_RS T#

CLK_ REQ

+3VS

UV11

DIS@

TC7SH09FU_S SOP5

5

Open Drain

DGPU_PWROK<25,49 >

+1.35VGS_PGOOD< 50>

D D

2

QV3B

@

G

2N7002KDW _SOT363-6

61

S

D

1

B

VCC

2

A

G

3

CLKREQ_PCIE#0_R

4

Y

+1.8VS_DGPU_AON

RV68 10K_0402_5%

Compal For Lenovo

1

+1.8VS_DGPU_AON

1

IN B

2

IN A

GPU_ALL_PGOOD

12

DIS@

VGS(Max) : 0.95 V

UV12

DIS@

5

NL17SZ08DFT2 G_SC70-5

VCC

4

OUT Y

GND

3

+3VS

12

RV17 10K_0402_5%

+1.8VS_DGPU

12

RV18 10K_0402_5%

2

G

61

S

D

QV147B 2N7002KDW _SOT363-6

DIS@

PLT_RST_VGA#

12

RV378 10K_0402_5%

DIS@

1 2 1 2

DIS@

2

PCIE_CRX_C_DTX_P13 PCIE_CRX_C_DTX_N1 3

PCIE_CRX_C_DTX_P14 PCIE_CRX_C_DTX_N1 4

PCIE_CRX_C_DTX_P15 PCIE_CRX_C_DTX_N1 5

PCIE_CRX_C_DTX_P16 PCIE_CRX_C_DTX_N1 6

PLT_RST_VGA# <24 >

GPU_ALL_PGOOD <11>

CLKREQ_PCIE#0 <10>

(To SOC)

UV1A

COMMON

1/14 PCI_EXPRESS

AB6

PEX_WAKE#

AC7

PEX_RST#

AC6

PEX_CLKREQ#

AE8

PEX_REFCLK

AD8

PEX_REFCLK#

AC9

PEX_TX0

AB9

PEX_TX0#

AG6

PEX_RX0

AG7

PEX_RX0#

AB10

PEX_TX1

AC10

PEX_TX1#

AF7

PEX_RX1

AE7

PEX_RX1#

AD11

PEX_TX2

AC11

PEX_TX2#

AE9

PEX_RX2

AF9

PEX_RX2#

AC12

PEX_TX3

AB12

PEX_TX3#

AG9

PEX_RX3

AG10

PEX_RX3#

AB13

PEX_TX4

AC13

PEX_TX4#

AF10

PEX_RX4

AE10

PEX_RX4#

AD14

PEX_TX5

AC14

PEX_TX5#

AE12

PEX_RX5

AF12

PEX_RX5#

AC15

PEX_TX6

AB15

PEX_TX6#

AG12

PEX_RX6

AG13

PEX_RX6#

AB16

PEX_TX7

AC16

PEX_TX7#

AF13

PEX_RX7

AE13

PEX_RX7#

AD17

PEX_TX8

AC17

PEX_TX8#

AE15

PEX_RX8

AF15

PEX_RX8#

AC18

PEX_TX9

AB18

PEX_TX9#

AG15

PEX_RX9

AG16

PEX_RX9#

AB19

PEX_TX10

AC19

PEX_TX10#

AF16

PEX_RX10

AE16

PEX_RX10#

AD20

PEX_TX11

AC20

PEX_TX11#

AE18

PEX_RX11

AF18

PEX_RX11#

AC21

PEX_TX12

AB21

PEX_TX12#

AG18

PEX_RX12

AG19

PEX_RX12#

AD23

PEX_TX13

AE23

PEX_TX13#

AF19

PEX_RX13

AE19

PEX_RX13#

AF24

PEX_TX14

AE24

PEX_TX14#

AE21

PEX_RX14

AF21

PEX_RX14#

AG24

PEX_TX15

AG25

PEX_TX15#

AG21

PEX_RX15

AG22

PEX_RX15#

N17S-G1-A1_FCBGA_595 P

DIS@

NC FOR GM108

3

NC FOR GF119

PEX_PLL_HVDD PEX_PLL_HVDD

PEX_SVDD_3V3

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

VDD_SENSE

GND_SENSE

AA22 AB23 AC24 AD25 AE26 AE27

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

AA8 AA9

AB8

F2

F1

AF22 AE22

Place near balls

1U_0201_6.3V6M

CV202

12

DIS@

Place near balls Place near BGA

AA10 AF27AB22AA16

1U_0201_6.3V6M

CV201

CV200

12

Place near ball

T9@

VDD_SENSE_GPU

GND_SENSE_GPU

T5@ T6@

12

DIS@

@

0.1U_0201_10V6K

CV207

1

DIS@

2

4

AE27AA22

4.7U_0402_6.3V6M CV205

1

DIS@

2

1U_0201_6.3V6M

CV391

CV390

12

DIS@

+1.8VS_DGPU

VDD_SENSE_GPU <49>

GND_SENSE_GPU <49>

NC FOR GF117/GK208/GM108

AA14

PEX_PLLVDD

AA15

PEX_PLLVDD

AD9

TESTMODE

AF25

PEX_TERMP

Security Classific ation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

T7@ T8@

GPU_TESTMODE

PEX_TERMP

2018/2/5 2019/2/5

GPU_TESTMODE <24>

12

RV376

2.49K_0402_1 %

DIS@

Compal Secret Data

Deciphered Date

4

Place near BGA

4.7U_0402_6.3V6M CV2

1

@

2

4.7U_0402_6.3V6M CV393

1

@

2

Midway GPU & VR

4.7U_0402_6.3V6M

CV392

CV3

1

@

2

To POWER

trace width: 16mils differential voltage sensing. differential signal routing.

5

+1.0VS_DGPU

22U_0603_6.3V6M

CV9

1

CV204

CV199

2

DIS@

10U_0402_6.3V6M

1

2

CV198

DIS@

10U_0402_6.3V6M

Title

Size Document Numb er Rev

Date : Sheet o f

DIS@

2

DIS@

10U_0402_6.3V6M

CV10

CV719

1

2

CV203

DIS@

NV(1/5)-PCIE

LA-G651P

1

DIS@

2

10U_0402_6.3V6M

Compal Electronics, Inc.

+1.8VS_DGPU

10U_0402_6.3V6M

CV724

1

@

2

5

21 5 2Friday, May 18, 2018

0.2

1

2

3

4

5

UV1G

COMMON

4/14 IFPAB

AA6

7/14 IFPEF

IFPEF_PLLVDD

IFPEF_RSET

IFPAB_RSET

V7

IFPAB_PLLVDD

W7

IFPAB_PLLVDD

W6

IFPA_IOVDD

Y6

IFPB_IOVDD

IFPAB

N17S-G1-A1_FCBGA_595 P

DIS@

A A

B B

+VGA_CORE

C C

J7

K7

K6

UV1J

COMMON

IFPE

H6

IFPE_IOVDD

J6

IFPF_IOVDD

IFPF

D D

N17S-G1-A1_FCBGA_595 P

DIS@

Compal For Lenovo

1

NC FOR GF117/GK208/GM108

IFPA/B

NC FOR GF117/GM108

IFPE/F

DVI-DL

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1

NC FOR GF117/GM108

TXD2 TXD2

HPD_E

DVI-DL

TXD3 TXD3

TXD4 TXD4

NC FOR GF117/GM108

TXD5 TXD5

NC FOR GF117/GM108

GF117

NC

GF119/GK208

DVI-SL/H DMI

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1TXD1 TXD1

TXD2 TXD2

NC FOR GK208

HPD_E

NC FOR GF117

GF119/GK208

DVI-SL/H DMI

I2CZ_SDA I2CZ_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

NC FOR GK208

HPD_F

NC FOR GF117

IFPA_TXC# IFPA_TXC

IFPA_TXD0# IFPA_TXD0

IFPA_TXD1# IFPA_TXD1

IFPA_TXD2# IFPA_TXD2

IFPA_TXD3# IFPA_TXD3

IFPB_TXC# IFPB_TXC

IFPB_TXD4# IFPB_TXD4

IFPB_TXD5# IFPB_TXD5

IFPB_TXD6# IFPB_TXD6

IFPB_TXD7# IFPB_TXD7

GPIO14

AC4 AC3

Y3 Y4

AA2 AA3

AA1 AB1

AA5 AA4

AB4 AB5

AB2 AB3

AD2 AD3

AD1 AE1

AD5 AD4

B3

IFPE_AUX# IFPE_AUX

IFPF_AUX# IFPF_AUX

DP

IFPE_L3# IFPE_L3

IFPE_L2# IFPE_L2

IFPE_L1# IFPE_L1

IFPE_L0# IFPE_L0

GPIO18

DP

IFPF_L3# IFPF_L3

IFPF_L2# IFPF_L2

IFPF_L1# IFPF_L1

IFPF_L0# IFPF_L0

GPIO19

+VGA_CORE

Note: IFPC/D/E/F interface are XVDDs pin for N17S GPU, and connect them to NVVDD power for improving NVVDD power rail routing

+VGA_CORE

J3 J2

J1 K1

K3 K2

M3 M2

M1 N1

C2

H4 H3

J5 J4

K5 K4

L4 L3

M5 M4

F7

2

UV1H

COMMON

5/14 IFPC

T6

IFPC_RSET

M7

IFPC_PLLVDD

N7

IFPC_PLLVDD

P6

IFPC_IOVDD

N17S-G1-A1_FCBGA_595 P

DIS@

NC FOR GF117/GM108

+1.8VS_DGPU_PLLVDD

IFPC IFPD

IFPC

GF119/GK208

DVI/HDMI

I2CW_SDA I2CW_SCL

TXC TXC

TXD0

NC FOR GF117/GM108

TXD0

TXD1 TXD1

TXD2 TXD2

Place near balls

L6 M6 N6

0.1U_0201_10V6K

CV31

1

DIS@

2

Security Classific ation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GF117

1

2

DP

IFPC_AUX# IFPC_AUX

IFPC_L3# IFPC_L3

IFPC_L2# IFPC_L2

IFPC_L1# IFPC_L1

IFPC_L0# IFPC_L0

GPIO15

NC

0.1U_0201_10V6K

CV34

1

DIS@

2

+VGA_CORE

N5 N4

N3 N2

R3 R2

R1 T1

T3 T2

C3

UV1M

COMMON

L6

PLLVDD

M6

SP_PLLVDD

N6

CV60

RV21

DIS@

2018/2/5 2019/2/5

DIS@

10K_0402_1%

VID_PLLVDD

GF119/GK208

12

A10

XTALSSIN

C11

XTALIN

N17S-G1-A1_FCBGA_595 P

DIS@

2

CV210

DIS@

18P_0402_50 V8J

1

Compal Secret Data

Deciphered Date

UV1I

U6

T7

R7

R6

W5

AE2

AF2

9/14 XTAL_PLL

YV1 27MHZ_10PF_XRCGB2 7M000F2P18R0

4

COMMON

6/14 IFPD

IFPD_RSET

IFPD_PLLVDD

IFPD

IFPD_IOVDD

N17S-G1-A1_FCBGA_595 P

DIS@

UV1K

COMMON

3/14 DACA

DACA_VDD

DACA_VREF

DACA_RSET

N17S-G1-A1_FCBGA_595 P

DIS@

GF117/GM108 GF117

TSEN_VREF

X'TAL

NC

GF117/GM108

SJ10000UI00DIS@

1

NC

2

4

NC FOR GF117/GM108

DAC_A

NC

XTALOUTBUFF

3

+VGA_CORE+VGA_CORE

GF119/GK208

DVI/HDMI

I2CX_SDA I2CX_SCL

NC FOR GF117/GM108

GM108/GK208

I2CA_SCL

NC

I2CA_SDA

NC

DACA_HSYNC

NC

DACA_VSYNC

NC

DACA_RED

NC

DACA_GREEN

NC

DACA_BLUE

NC

GM108

GK208

GF117

XTAL_OUTBUFF

C10

B10

XTALOUT

Title

NV(2/5)-IFP_ABCDEF_DAC_XTAL

Size Document Numb er Rev

LA-G651P

Date : Sheet o f

DP

P4

IFPD_AUX#

P3

IFPD_AUX

R5

IFPD_L3#

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

GF117

NC

B7 A7

AE3 AE4

AG3

AF4

AF3

12

2

1

Compal Electronics, Inc.

IFPD_L3

IFPD_L2# IFPD_L2

IFPD_L1# IFPD_L1

IFPD_L0# IFPD_L0

GPIO17

RV23 10K_0402_1%

1 2

RV20 10K_0402_1%

1 2

RV22

DIS@

470_0201_5 %

CV209

DIS@

18P_0402_50 V8J

5

R4

T5 T4

U4 U3

V4 V3

D4

@

DIS@

+1.8VS_DGPU_AON

22 5 2Friday, May 18, 2018

0.2

1

2

3

4

5

+1.35VS_VRAM

Place near BGA Place near balls

A A

1

CV405

@

2

22U_0603_6.3V6M

CV45

CV406

@

2

22U_0603_6.3V6M

1

2

CV403

CV44

2

DIS@

10U_0402_6.3V6M

H24 J2 1 W21 L 24

M21

1

CV404

2

DIS@

10U_0402_6.3V6M

12

CV217

DIS@

10U_0402_6.3V6M

12

CV38

CV218

DIS@

1U_0201_6.3V6M

Place near balls

G19E2 6L26

12

CV399

DIS@

B B

12

CV401

CV400

DIS@

1U_0201_6.3V6M

G16G1 3

12

CV221

CV402

DIS@

1U_0201_6.3V6M

UV1D

COMMON

12/14 FBVDDQ

B26

FBVDDQ

C25

FBVDDQ

E23

FBVDDQ

E26

FBVDDQ

F14

FBVDDQ

F21

FBVDDQ

G13

FBVDDQ

G14

FBVDDQ

G15

FBVDDQ

G16

FBVDDQ

G18

FBVDDQ

G19

FBVDDQ

G20

FBVDDQ

G21

FBVDDQ

L22

FBVDDQ

L24

FBVDDQ

L26

FBVDDQ

M21

FBVDDQ

N21

FBVDDQ

R21

FBVDDQ

T21

FBVDDQ

V21

FBVDDQ

W21

FBVDDQ

H24

FBVDDQ_AON

H26

FBVDDQ_AON

J21

FBVDDQ_AON

K21

FBVDDQ_AON

N17S-G1-A1_FCBGA_595 P

DIS@

GF117 GF119

GK208

FBVDDQ FBVDDQ FBVDDQ FBVDDQ

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

D22

C24

B25

Near Ball

1 2

RV41 40.2_0402_1%DIS@

RV42 40.2_0402_1%DIS@

RV43 60.4_0402_1%DIS@

12

+1.35VS_VRAM

GPU_Decoupling CAPs @ Power Page

+VGA_CORE

Voltage by GPU SKU

K10 K12 K14 K16 K18

L11 L13 L15

L17 M10 M12 M14 M16 M18 N11 N13 N15 N17 P10 P12 P14 P16 P18 R11 R13 R15 R17

T10

T12

T14

T16

T18 U11 U13 U15 U17 V10 V12 V14 V16 V18

UV1E

COMMON

11/14 NVVDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

N17S-G1-A1_FCBGA_595 P

DIS@

H2 NC

H5 NC

L2 NC

C C

UV1F

COMMON

13/14 GND

A2

GND

AB17

GND

AB20

GND

AB24

GND

AC2

GND

AC22

GND

AC26

GND

AC5

GND

AC8

GND

AD12

GND

AD13

GND

A26

GND

AD15

GND

AD16

GND

AD18

GND

AD19

GND

AD21

GND

AD22

GND

AE11

GND

AE14

GND

AE17

GND

AE20

GND

AB11

GND

AF1

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF5

GND

AF8

GND

AG2

GND

AG26

GND

AB14

GND

B1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B27

GND

B5

GND

B8

GND

E11

GND

E14

GND

E17

GND

E2

GND

E20

GND

E22

GND

E25

GND

E5

GND

E8

GND

H2

GND

H23

GND

H25

GND

H5

GND

K11

GND

K13

GND

K15

GND

K17

GND

L10

GND

L12

GND

L14

GND

L16

GND

L18

GND

L2

GND

L23

GND

L25

GND

L5

GND

M11

GND

N17S-G1-A1_FCBGA_595 P

DIS@

M13

GND

M15

GND

M17

GND

N10

GND

N12

GND

N14

GND

N16

GND

N18

GND

P11

GND

P13

GND

P15

GND

P17

GND

P2 NC

P2

GND

P23

GND

P26

GND

P5

P5 NC

GND

R10

GND

R12

GND

R14

GND

R16

GND

R18

GND

T11

GND

T13

GND

T15

GND

T17

GND

U10

GND

U12

GND

U14

GND

U16

GND

U18

GND

U2

U2 NC

GND

U23

GND

U26

GND

U5

U5 NC

GND

V11

GND

V13

GND

V15

GND

V17

GND

Y2

GND

Y23

GND

Y26

GND

Y5

GND

AA7

GND

AB7

GND

+VGA_CORE

+1.8VS_DGPU +1.8VS_DGPU_PLLVDD

1 2

LV10

DIS@ SM01000NV00

HCB1005KF-300 T25_2P

D D

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

CV722

@

CV396

CV720

1

@

DIS@

2

Under GPUNear GPU F11

4.7U_0402_6.3V6M

0.1U_0201_10V6K

CV395

1

2

CV394

1

DIS@

@

2

AD10

AD7

F11

V5 V6

G1 G2 G3 G4 G5 G6 G7

V1 V2

UV1C

COMMON

14/14 XVDD/VDD33

NC NC

GM108

3V3_AON 3V3_AON

3V3AUX_NC

FERMI_RSVD1_NC FERMI_RSVD2_NC

CONFIGURABLE

POWER CHANNELS

* nc on substrate

XPWR_G1 XPWR_G2 XPWR_G3 XPWR_G4 XPWR_G5 XPWR_G6 XPWR_G7

XPWR_V1 XPWR_V2

VDD33 VDD33 VDD33 VDD33

Under GPU Near GPU

G8 G9 G10 G12

G8 G9

1

CV220

2

DIS@

G10 G 12

1

CV397

2

DIS@

+1.8VS_DGPU

1

CV211

2

DIS@

0.1U_0201_10V6K

1

12

CV216

CV219

2

DIS@

4.7U_0402_6.3V6M

1U_0201_6.3V6M

+1.8VS_DGPU_AON

Near GPUUnder GPU

1

CV214

2

@

0.1U_0201_10V6K

1

12

CV213

CV212

2

@

DIS@

4.7U_0402_6.3V6M

1U_0201_6.3V6M

** XPWR pins are configurable.

These pins are not connected on the substrate.

Therefore, XPW R pins can be assigned as needed,

to improve Top layer routing, power delivery.

Compal For Lenovo

1

2

W1

XPWR_W1

W2

XPWR_W2

W3

XPWR_W3

W4

XPWR_W4

N17S-G1-A1_FCBGA_595 P

DIS@

Security Classific ation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date : Sheet o f

Compal Electronics, Inc.

NV(3/5)-POWER

LA-G651P

5

23 5 2Friday, May 18, 2018

0.2

1

UV1N

COMMON

E12

THERMDN

F12

GPU_JTAG_TCK

T231 @

GPU_JTAG_TMS

T232 @ T242 @ T243 @

GPU_JTAG_TDI

GPU_JTAG_TDO

GPU_JTAG_TRST#

A A

THERMDP

AE5

JTAG_TCK

AD6

JTAG_TMS

AE6

JTAG_TDI

AF6

JTAG_TDO

AG4

JTAG_TRST#

N17S-G1-A1_FCBGA_595P

DIS@

8/14 MISC1

GPIO

GM108

GPIO16 GPIO20 GPIO21

GPIO8

GPIO16 GPIO20

GK208

GPIO8

GF117

NC NC

GK208

GM108 OVERT

GF117 GF119

NC NC

D9

I2CS_SCL

D8

I2CS_SDA

A9

I2CC_SCL

B9

I2CC_SDA

C9

I2CB_SCL

C8

I2CB_SDA

C6

GPIO0

B2

GPIO1

D6

GPIO2

C7

GPIO3

F9

GPIO4

A3

GPIO5

A4

GPIO6

B6

GPIO7

A6

GPIO8

F8

GPIO9

C5

GPIO10

E7

GPIO11

D7

GPIO12

B4

GPIO13

D5

GPIO16

NC

E6

GPIO20

NC

C4

GPIO21

NC

E9

NC

I2CS_SCL I2CS_SDA

I2CC_SCL I2CC_SDA

I2CB_SCL I2CB_SDA

GPU_VID0 GPIO0_GC6_FB_EN GPU_EVENT#_D

DGPU_MAIN_EN

PSI

GPIO8_OVERT# GPIO9_ALERT# MEM_VREF

VGA_AC_DET

2

RV203 2.2K_0402_5%DIS@ RV204 2.2K_0402_5%DIS@

RV205 2.2K_0402_5%DIS@ RV206 2.2K_0402_5%DIS@

RV208 2.2K_0402_5%DIS@ RV207 2.2K_0402_5%DIS@

RV202 0_0402_5%@ DV1 RB751V-40_SOD323-2DIS@

DV2 RB751V40_SC76-2@

1 2 1 2

1 2

12

To DGPU VR

+1.8VS_DGPU_AON

I2CS SMBUS: 0x9E and 0x9C Debug Address: 0x96

GPU_VID0 <49> GC6_FB_EN <9,25> GPU_EVENT# < 9>

DGPU_MAIN_EN <26>

PSI <49>

MEM_VREF <27>

AC_PRESENT <10,34>

3

DGPU_MAIN_EN

PSI

VGA_AC_DET

GPU_EVENT#_D

GPIO8_OVERT#

GPIO9_ALERT#

GPU_JTAG_TRST#

MEM_VREF

GC6_FB_EN

GPU_TESTMODE<21>

GPU_TESTMODE

1 2

RV90 2K_0402_1%DIS@

1 2

RV91 10K_0402_5%DIS@

1 2

RV92 10K_0402_5%DIS@

1 2

RV72 10K_0402_5%GC6@

1 2

RV69 100K_0402_5%DIS@

1 2

RV93 10K_0402_5%DIS@

1 2

RV94 10K_0402_5%DIS@

1 2

RV102 100K_0402_5%DIS@

1 2

RV88 10K_0402_5%GC6@

1 2

RV71 10K_0402_5%DIS@

4

+1.8VS_DGPU_AON

5

UV1L

COMMON

10/14 MISC2

E10

VMON_IN0_NC

F10

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

STRAP5

VMON_IN1_NC

D1

STRAP0

D2

STRAP1

E4

STRAP2

E3

STRAP3

D3

STRAP4

C1

STRAP5_NC

F6

MULTISTRAP_REF0_GND

F4

MULTISTRAP_REF1_GND

F5

MULTISTRAP_REF2_GND

N17S-G1-A1_FCBGA_595P

DIS@

+1.8VS_DGPU_AON

12

@

RV398

100K_0402_5%

12

DIS@

RV399

100K_0402_5%

NC FOR

GM108

GF117

GK208

GM108

NC

12

@

RV61

RV389

100K_0402_5%

12

DIS@

RV387

RV385

100K_0402_5%

12

@

12

@

B B

+VGA_CORE

1 2

RV6 100_0402_1%@

STRAP

C C

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5

D D

ROM_CS#

ROM_SI

ROM_SO

ROM_SCLK

BUFRST#

PGOOD

NC

GF119GF117

RAM Config

@

RV382

100K_0402_5%

@

RV388

100K_0402_5%

D12

ROM_SI

B12

ROM_SO

A12

ROM_SCLK

C12

D11

D10

12

@

RV51

RV384

100K_0402_5%

12

@

RV383

RV390

100K_0402_5%

Compal For Lenovo

1

EXPOSED STRAP

+1.8VS_DGPU_AON

DIS@

ROM_SI ROM_SO ROM_SCLK

@

RAM_CF G

0x00(LLL )

0x01(LLH )

0x02(LHL )

0x03(LHH )

0x04(HLL )

0x05(HLH )

0x06(HHL )

0x07(HHH )

0x08(LLM )

2

12

RV84

100K_0402_5%

12

RV65

100K_0402_5%

S2G

M2G

H2G

12

DIS@

RV81

100K_0402_5%

12

@

DIS@

RV64

100K_0402_5%

X76 STRAP2 STR AP1 STRAP 0

ZZZ

X76V@

ZZZ

X76V@

ZZZ

X76V@

RV80

100K_0402_5%

RV381

100K_0402_5%

RV388

S2G@

RV382

M2G@

RV382

H2G@

Internal Thermal S ensor

RV74

PLT_RST_VGA#<21>

+3VALW

12

RV106 100K_0402_5%

61

DGPU_MAIN_EN

QV7B

RV390

RV383

S2G@

RV390

M2G@

RV390

H2G@

UV6 S2G@

S2G@

SA000092D10

UV6 M2G@

RV383

SA00009TV60

M2G@

RV384

UV6 H2G@

H2G@

SA00009U150

3

UV7 S2G@

SA000092D10

UV7 M2G@

SA00009TV60

UV7 H2G@

SA00009U150

2N7002KDW_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

D

G

2

S

DIS@

DGPU_PWR_EN<11,26,34>

1 2

I2CS_SDA

PLT_RST_VGA# PLT_RST_VGA#

1 2

12

RV260 0_0402_5%@

+3VS

12

DIS@

RV108 10K_0402_5%

1.8VSDGPU_MAIN

34

D

G

5

S

QV7A

DIS@

2N7002KDW_SOT363-6

2018/2/5 2019/2/5

DIS@

10K_0402_5%

S

RV76

@

10K_0402_5%

SGD

UV10

DIS@

NL17SZ08DFT2G_SC70-5

1

2

RV256

@

100K_0402_5%

1 2

Compal Secret Data

Deciphered Date

4

2

QV2B

DIS@

G

2N7002KDW_SOT363-6

61

D

5

QV3A

@

2N7002KDW_SOT363-6

34

+3VS

5

IN B

VCC

OUT Y

IN A

GND

3

4

PLT_RST_VGA#PLT_RST_VGA#

EC_SMB_DA2 < 8,30,34,36>

Enable: Vh:2.1V Vl:1V Enable: Vh:1.5V Vl:0.7V

GPUCORE_EN

RV254 100K_0402_5%

1 2

DV4 RB751S-40_SOD523-2

RV105

@

40.2K_0402_1%

DV5 RB751S-40 SOD-523

RV103 56K_0402_1%

RV75

1 2

I2CS_SCL

1 2

GPIO9_ALERT#GPIO8_OVERT# GPIO8_OVERT#_R

DIS@

1 2

DIS@

1 2

DIS@

1 2

DIS@

1 2

Title

Size

Date : Sheet of

DIS@

10K_0402_5%

5

SGD

RV77

DIS@

10K_0402_5%

5

SGD

1

CV197

2

0.1U_0201_10V6K

1

@

2

CV196

Compal Electronics, Inc.

NV(4/5)-GPIO/Strap

Document Number Rev

LA-G651P

5

QV2A

DIS@

2N7002KDW_SOT363-6

34

QV147A

DIS@

2N7002KDW_SOT363-6

34

DIS@

@

RV255

1 2

0.1U_0201_10V6K

Link to PCH SML 1

PU @ PCH SIDE

EC_SMB_CK2 <8,30,3 4,36>

GPU_PROHOT# <34,36>GPU_OVERT# <34>

VGA_CORE_EN <49>

1.0VS_DGPU_EN <26 ,45>

delay 1.33ms

100K_0402_1%

24 52Friday, May 18, 2018

0.2

1

2

3

4

5

For GC6

UV1B

COMMON

FB_A_D[0..31]<27>

A A

FB_A_D[32..63]<27>

B B

FB_A_DBI[3..0]<27>

FB_A_DBI[7..4]<27>

C C

D D

FB_A_EDC[3..0]<27>

FB_A_EDC[7..4]<27>

For VRAM DEBUG using

T2401 @

FB_A_D0 FB_A_D1 FB_A_D2 FB_A_D3 FB_A_D4 FB_A_D5 FB_A_D6 FB_A_D7 FB_A_D8 FB_A_D9 FB_A_D10 FB_A_D11 FB_A_D12 FB_A_D13 FB_A_D14 FB_A_D15 FB_A_D16 FB_A_D17 FB_A_D18 FB_A_D19 FB_A_D20 FB_A_D21 FB_A_D22 FB_A_D23 FB_A_D24 FB_A_D25 FB_A_D26 FB_A_D27 FB_A_D28 FB_A_D29 FB_A_D30 FB_A_D31 FB_A_D32 FB_A_D33 FB_A_D34 FB_A_D35 FB_A_D36 FB_A_D37 FB_A_D38 FB_A_D39 FB_A_D40 FB_A_D41 FB_A_D42 FB_A_D43 FB_A_D44 FB_A_D45 FB_A_D46 FB_A_D47 FB_A_D48 FB_A_D49 FB_A_D50 FB_A_D51 FB_A_D52 FB_A_D53 FB_A_D54 FB_A_D55 FB_A_D56 FB_A_D57 FB_A_D58 FB_A_D59 FB_A_D60 FB_A_D61 FB_A_D62 FB_A_D63

FB_A_DBI0 FB_A_DBI1 FB_A_DBI2 FB_A_DBI3 FB_A_DBI4 FB_A_DBI5 FB_A_DBI6 FB_A_DBI7

FB_A_EDC0 FB_A_EDC1 FB_A_EDC2 FB_A_EDC3 FB_A_EDC4 FB_A_EDC5 FB_A_EDC6 FB_A_EDC7

FB_VREF

2/14 FBA

E18

FBA_D0

F18

FBA_D1

E16

FBA_D2

F17

FBA_D3

D20

FBA_D4

D21

FBA_D5

F20

FBA_D6

E21

FBA_D7

E15

FBA_D8

D15

FBA_D9

F15

FBA_D10

F13

FBA_D11

C13

FBA_D12

B13

FBA_D13

E13

FBA_D14

D13

FBA_D15

B15

FBA_D16

C16

FBA_D17

A13

FBA_D18

A15

FBA_D19

B18

FBA_D20

A18

FBA_D21

A19

FBA_D22

C19

FBA_D23

B24

FBA_D24

C23

FBA_D25

A25

FBA_D26

A24

FBA_D27

A21

FBA_D28

B21

FBA_D29

C20

FBA_D30

C21

FBA_D31

R22

FBA_D32

R24

FBA_D33

T22

FBA_D34

R23

FBA_D35

N25

FBA_D36

N26

FBA_D37

N23

FBA_D38

N24

FBA_D39

V23

FBA_D40

V22

FBA_D41

T23

FBA_D42

U22

FBA_D43

Y24

FBA_D44

AA24

FBA_D45

Y22

FBA_D46

AA23

FBA_D47

AD27

FBA_D48

AB25

FBA_D49

AD26

FBA_D50

AC25

FBA_D51

AA27

FBA_D52

AA26

FBA_D53

W26

FBA_D54

Y25

FBA_D55

R26

FBA_D56

T25

FBA_D57

N27

FBA_D58

R27

FBA_D59

V26

FBA_D60

V27

FBA_D61

W27

FBA_D62

W25

FBA_D63

D19

FBA_DQM0

D14

FBA_DQM1

C17

FBA_DQM2

C22

FBA_DQM3

P24

FBA_DQM4

W24

FBA_DQM5

AA25

FBA_DQM6

U25

FBA_DQM7

E19

FBA_DQS_WP0

C15

FBA_DQS_WP1

B16

FBA_DQS_WP2

B22

FBA_DQS_WP3

R25

FBA_DQS_WP4

W23

FBA_DQS_WP5

AB26

FBA_DQS_WP6

T26

FBA_DQS_WP7

F19

FBA_DQS_RN0

C14

FBA_DQS_RN1

A16

FBA_DQS_RN2

A22

FBA_DQS_RN3

P25

FBA_DQS_RN4

W22

FBA_DQS_RN5

AB27

FBA_DQS_RN6

T27

FBA_DQS_RN7

D23

FB_VREF_PROBE

N17S-G1-A1_FCBGA_595 P

DIS@

GF117/GF119

GK208

FBA_DEBUG0 FBA_DEBUG1

FB_PLLAVDD

F3

FB_CLAMP

NC

GF119

C27

FBA_CMD0

C26

FBA_CMD1

E24

FBA_CMD2

F24

FBA_CMD3

D27

FBA_CMD4

D26

FBA_CMD5

F25

FBA_CMD6

F26

FBA_CMD7

F23

FBA_CMD8

G22

FBA_CMD9

G23

FBA_CMD10

G24

FBA_CMD11

F27

FBA_CMD12

G25

FBA_CMD13

G27

FBA_CMD14

G26

FBA_CMD15

M24

FBA_CMD16

M23

FBA_CMD17

K24

FBA_CMD18

K23

FBA_CMD19

M27

FBA_CMD20

M26

FBA_CMD21

M25

FBA_CMD22

K26

FBA_CMD23

K22

FBA_CMD24

J23

FBA_CMD25

J25

FBA_CMD26

J24

FBA_CMD27

K27

FBA_CMD28

K25

FBA_CMD29

J27

FBA_CMD30

J26

FBA_CMD31

B19

NC

GF119

GF117

FBA_CMD32

F22

FBA_CMD34

J22

FBA_CMD35

D24

FBA_CLK0

D25

FBA_CLK0#

N22

FBA_CLK1

M22

FBA_CLK1#

D18

FBA_WCK01

C18

FBA_WCK01#

D17

FBA_WCK23

D16

FBA_WCK23#

T24

FBA_WCK45

U24

FBA_WCK45#

V24

FBA_WCK67

V25

FBA_WCK67#

F16

FB_PLLAVDD

NC

FB_PLLAVDD

FB_DLLAVDD

P22

H22

1 2

RV5 10 0_0402_1%@

FB_A_CMD0 FB_A_CMD1 FB_A_CMD2 FB_A_CMD3 FB_A_CMD4 FB_A_CMD5 FB_A_CMD6 FB_A_CMD7 FB_A_CMD8 FB_A_CMD9 FB_A_CMD10 FB_A_CMD11 FB_A_CMD12 FB_A_CMD13 FB_A_CMD14 FB_A_CMD15 FB_A_CMD16 FB_A_CMD17 FB_A_CMD18 FB_A_CMD19 FB_A_CMD20 FB_A_CMD21 FB_A_CMD22 FB_A_CMD23 FB_A_CMD24 FB_A_CMD25 FB_A_CMD26 FB_A_CMD27 FB_A_CMD28 FB_A_CMD29 FB_A_CMD30 FB_A_CMD31

1 2

RV82 60.4_0402_1%@

1 2

RV83 60.4_0402_1%@

FB_A_CLK0 FB_A_CLK#0 FB_A_CLK1 FB_A_CLK#1

FB_A_WCK0 FB_A_WCK#0 FB_A_WCK1 FB_A_WCK#1 FB_A_WCK2 FB_A_WCK#2 FB_A_WCK3 FB_A_WCK#3

+1.8VS_PLLAVDD

CV55

0.1U_0201_10V6K

1

DIS@

2

FBA_CKE_L FBA_CKE_H

FBA_RST_L FBA_RST_H

GDDR5 design

FBVDDQ_GPU

+1.35VS_VRAM

1.35V

FB_A_WCK0 <27> FB_A_WCK#0 <27> FB_A_WCK1 <27> FB_A_WCK#1 <27> FB_A_WCK2 <27> FB_A_WCK#2 <27> FB_A_WCK3 <27> FB_A_WCK#3 <27>

CV52

0.1U_0201_10V6K

2

DIS@

1

FB_A_CMD[0..31] <27>

FB_A_CMD14 FB_A_CMD30

FB_A_CMD13 FB_A_CMD29

FB_A_CLK0 <27> FB_A_CLK#0 <27> FB_A_CLK1 <27> FB_A_CLK#1 <27>

CV53

CV398

0.1U_0201_10V6K

1

DIS@

2

GC6_FB_EN<9,24>

DGPU_PWROK<21,49 >

RV2439 10K_0201_1%DIS@ RV2440 10K_0201_1%DIS@

RV2437 10K_0201_1%DIS@ RV2438 10K_0201_1%DIS@

Near GPUP22 H 22F16 Bal l

10U_0402_6.3V6M

CV723

1

DIS@

2

1 2 1 2

10U_0402_6.3V6M

CV51

1

@

2

1

2

CV223

0.1U_0201_10 V6K

GC6_FB_EN

1 2

LV7 HCB1005KF-300 T25_2P

10U_0402_6.3V6M

SM01000NV00

CV721

@

+1.8VS_DGPU_AON

1

@

2

RV201 0_ 0402_5%

1.8V OR GATE

UV23

@

5

74AUP1G32GW_ TSSOP5

2

SA000054300

A

4

Vcc

Y

1

B

G

3

1 2

NOGC6@

Stuff RV201 if not support GC6

From DG-07158-001_v05_secured(NVDIA Spec)

+1.35VS_VRAM

+1.8VS_DGPU

DIS@

1.35V_PWR_EN <5 0>

GC6_FB_EN

DGPU_PWROK

DV3

GC6@

2

3

BAV70W_SOT323 -3

1.35V_PWR_EN

1

12

RV12

16.5K_0402_5 %

GC6@

Security Classific ation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Compal For Lenovo

1

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date : Sheet o f

4

Date : Sheet o f

Compal Electronics, Inc.

NV(5/5)-MEMORY FBA

LA-G651P

5

0.2

25 5 2Friday, May 18, 2018

0.2

5

4

3

2

1

+5VALW

+1.8VS to +1.8VS_DGPU

1.8VSDGPU_MAIN_EN_R

D D

+1.8VS to +1.8VS_DGPU_AON

DGPU_PWR_EN<11,24,34>

C C

DGPU_PWR_EN_18ON

1U_0201_6.3V6M

CV322

12

DIS@

DV8

DIS@

RB751S-40 SOD-523

12

RV245

@

1K_0402_5%

1 2

DGPU_MAIN_EN<24>

1

2

+1.8VALW

1.8VSDGPU_MAIN_EN_R

RV257

DIS@

40.2K_0402_1%

+1.8VS_DGPU

1

CV324

2

@

10U_0402_6.3V6M

+1.8VS_DGPU_AON

1

CV325

2

@

10U_0402_6.3V6M

1.8VSDGPU_MAIN_EN_R

2

G

12

RV2008 100K_0402_5%

1.8VSDGPU_MAIN_EN#_R

61

D

QV146A 2N7002KDW_SOT363-6

SB00000EO00

S

+1.0VS_DGPU Discharge+1.8VS_DGPU Discharge

+1.0VS_DGPU+ 5VALW+3VALW +1.8VS_DGPU

5

G

12

RV2009 10_0603_5%

34

D

QV146B 2N7002KDW_SOT363-6

SB00000EO00

S

DIS@

1.0VS_DGPU_EN<24,45>

1.0VS_DGPU_EN

DIS@

2

G

12

RV2007 100K_0402_5%

1.0VS_DGPU_EN#_R

61

D

QV145A 2N7002KDW_SOT363-6

SB00000EO00

S

DIS@

5

G

12

RV2006 10_0603_5%

34

D

QV145B 2N7002KDW_SOT363-6

SB00000EO00

S

DIS@

UV2

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

1U_0201_6.3V6M

CV328

1U_0201_6.3V6M

12

@

DGPU_PWR_EN_18ON

CV206

DIS@

RV252 100K_0402_1%

1 2

0.1U_0201_10V6K

VIN2

CV323

G2898KD1U TDFN 14P LOAD SWITCH

@

SA0000BKC00

DIS@

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

DV9

DIS@

RB751S-40 SOD-523

12

RV246

@

0_0402_5%

1 2

14 13

12

CV326 1200P _0402_50V7KDIS@

11

10

CV327 2200P _0402_25V7KDIS@

9 8

15

1

2

1 2

CV224

@

0.1U_0201_10V6K

1 2

B B

A A

Security Classification

Issued Date

Compal For Lenovo

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DGPU_DC/DC Interface

Size

Document Number Rev

LA-G651P

Date : Sheet of

1

26 52Friday, May 18, 2018

0.2

5

4

3

2

1

Memory Partition A

MF=0

UV6

@

FB_A_EDC0 FB_A_EDC1 FB_A_EDC2 FB_A_EDC3

FB_A_DBI0<25>

D D

RV1

40.2_0402_1%

1 2

RV3

40.2_0402_1%

1 2

2

G

DIS@

RV200 931_0402_1%DIS@

13

D

QV50 L2N7002WT1G_SC-70-3

S

FB_A_CMD[0..15]

FB_A_CMD[16..31]

FB_A_D[0..63]

FB_A_EDC[7..0]

RV2

40.2_0402_1%

1 2

1

CV4

0.01U_0402_16V7K

2

RV4

40.2_0402_1%

1 2

1

CV5

0.01U_0402_16V7K

2

1 2

DIS@

+1.35VS_VRAM

12

RV125

DIS@

549_0402_1%

+FBA_VREFC0

W=16mils

CV158

820P_0402_25V7

RV127

1.33K_0402_1%

12

DIS@

CV159

820P_0402_25V7

1

DIS@

2

FB_A_CMD[0..15]<25>

C C

FB_A_CMD[16..31]<25>

FB_A_D[0..63]<25>

FB_A_EDC[7..0]<25>

FB_A_CLK0 FB_A_CLK#0

Near to UV6

FB_A_CLK1 FB_A_CLK#1

Near to UV7

B B

MEM_VREF<24>

Place near pin J14 of each vram

FB_A_DBI1<25> FB_A_DBI2<25> FB_A_DBI3<25>

FB_A_CLK0<25> FB_A_CLK#0<25>

RV116 1K_0402_1%DIS@ RV118 1K_0402_1%DIS@ RV120 121_0402_1%DIS@

FB_A_WCK#0<25> FB_A_WCK0<25>

FB_A_WCK#1<25> FB_A_WCK1<25>

+1.35VS_VRAM

FB_A_CLK0 FB_A_CLK#0 FB_A_CMD14

FB_A_CMD2 FB_A_CMD4 FB_A_CMD3 FB_A_CMD1

FB_A_CMD6 FB_A_CMD11 FB_A_CMD10 FB_A_CMD7 FB_A_CMD9

12 12 12

FB_A_CMD8 FB_A_CMD12 FB_A_CMD0 FB_A_CMD15 FB_A_CMD5

FB_A_WCK#0 FB_A_WCK0

FB_A_WCK#1 FB_A_WCK1

+FBA_VREFC0

FB_A_CMD13

+1.35VS_VRAM

2

DIS@

1

CV601

22U_0603_6.3V6M

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2

DIS@

1

CV602

22U_0603_6.3V6M

1

CV603

2

DIS@

10U_0402_6.3V6M

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

K4G80325FB-HC03_FBGA170 ~D

Near ballNear VRAM Near VRAM Near ball

1

2

1

CV604

DIS@

CV605

2

DIS@

10U_0402_6.3V6M

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

FB_A_D0

A4

FB_A_D1

A2

FB_A_D2

B4

FB_A_D3

B2

FB_A_D4

E4

FB_A_D5

E2

FB_A_D6

F4

FB_A_D7

F2

FB_A_D8

A11

FB_A_D9

A13

FB_A_D10

B11

FB_A_D11

B13

FB_A_D12

E11

FB_A_D13

E13

FB_A_D14

F11

FB_A_D15

F13

FB_A_D16

U11

FB_A_D17

U13

FB_A_D18

T11

FB_A_D19

T13

FB_A_D20

N11

FB_A_D21

N13

FB_A_D22

M11

FB_A_D23

M13

FB_A_D24

U4

FB_A_D25

U2

FB_A_D26

T4

FB_A_D27

T2

FB_A_D28

N4

FB_A_D29

N2

FB_A_D30

M4

FB_A_D31

M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1

VSSQ

C1

VSSQ

E1

VSSQ

N1

VSSQ

R1

VSSQ

U1

VSSQ

H2

VSSQ

K2

VSSQ

A3

VSSQ

C3

VSSQ

E3

VSSQ

N3

VSSQ

R3

VSSQ

U3

VSSQ

C4

VSSQ

R4

VSSQ

F5

VSSQ

M5

VSSQ

F10

VSSQ

M10

VSSQ

C11

VSSQ

R11

VSSQ

A12

VSSQ

C12

VSSQ

E12

VSSQ

N12

VSSQ

R12

VSSQ

U12

VSSQ

H13

VSSQ

K13

VSSQ

A14

VSSQ

C14

VSSQ

E14

VSSQ

N14

VSSQ

R14

VSSQ

U14

VSSQ

1

CV607

CV606

2

DIS@

10U_0402_6.3V6M

+1.35VS_VRAM

1

CV608

2

DIS@

10U_0402_6.3V6M

BYTE0

BYTE1

BYTE2

BYTE3

FB_A_DBI4<25> FB_A_DBI5<25> FB_A_DBI6<25> FB_A_DBI7<25>

FB_A_CLK1<25> FB_A_CLK#1<25>

RV117 1K_04 02_1%DIS@ RV119 1K_04 02_1%DIS@ RV121 121 _0402_1%DIS@

FB_A_WCK#2<25> FB_A_WCK2<25>

FB_A_WCK#3<25> FB_A_WCK3<25>

+1.35VS_VRAM

FB_A_EDC4 FB_A_EDC5 FB_A_EDC6 FB_A_EDC7

FB_A_CLK1 FB_A_CLK#1 FB_A_CMD30

FB_A_CMD18 FB_A_CMD20 FB_A_CMD19 FB_A_CMD17

FB_A_CMD22 FB_A_CMD27 FB_A_CMD26 FB_A_CMD23 FB_A_CMD25

12 12 12

FB_A_CMD24 FB_A_CMD28 FB_A_CMD16 FB_A_CMD31 FB_A_CMD21

FB_A_WCK#2 FB_A_WCK2

FB_A_WCK#3 FB_A_WCK3

+FBA_VREFC0

FB_A_CMD29

+1.35VS_VRAM

2

1

DIS@

CV701

UV7

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

SGRAM GDDR5

2

DIS@

1

22U_0603_6.3V6M

CV702

22U_0603_6.3V6M

MF=0

@

MF=0 MF=1 MF=0MF=1

170-BALL

K4G80325FB-HC03_FBGA170 ~D

1

CV704

CV703

2

DIS@

10U_0402_6.3V6M

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

1

CV705

2

DIS@

10U_0402_6.3V6M

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FB_A_D32

A4

FB_A_D33

A2

FB_A_D34

B4

FB_A_D35

B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

1

CV707

CV706

2

DIS@

10U_0402_6.3V6M

FB_A_D36 FB_A_D37 FB_A_D38 FB_A_D39 FB_A_D40 FB_A_D41 FB_A_D42 FB_A_D43 FB_A_D44 FB_A_D45 FB_A_D46 FB_A_D47 FB_A_D48 FB_A_D49 FB_A_D50 FB_A_D51 FB_A_D52 FB_A_D53 FB_A_D54 FB_A_D55 FB_A_D56 FB_A_D57 FB_A_D58 FB_A_D59 FB_A_D60 FB_A_D61 FB_A_D62 FB_A_D63

10U_0402_6.3V6M

+1.35VS_VRAM

1

CV708

2

DIS@

10U_0402_6.3V6M

BYTE4

BYTE5

BYTE6

BYTE7

+1.35VS_VRAM +1.35VS_VRAM

Near ball

12

A A

12

DIS@

CV610

CV609

1U_0201_6.3V6M

Compal For Lenovo

5

4

12

DIS@

CV613

CV612

CV611

1U_0201_6.3V6M

12

DIS@

CV614

CV615

1U_0201_6.3V6M

12

DIS@

CV618

CV617

CV616

1U_0201_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/2/5 2019/2/5

Compal Secret Data

2

12

DIS@

CV709

1U_0201_6.3V6M

Deciphered Date

Near ball

12

DIS@

CV710

1U_0201_6.3V6M

12

DIS@

CV712

CV711

1U_0201_6.3V6M

DIS@

CV714

CV713

1U_0201_6.3V6M

Title

Size Document Number Rev

Date: Sheet of

DIS@

CV716

CV715

1U_0201_6.3V6M

Compal Electronics, Inc.

N16P_GDDR5_A

LA-G651P

DIS@

CV718

CV717

1U_0201_6.3V6M

0.2

27 52Friday, May 18, 2018

1

27 52Friday, May 18, 2018

12

5

LCD Power Circuit

4

3

2

1

+3VS +LCDVDD_ CONN

W=60mils

12

1U_0201_6.3V6M

C1220

DMIC_CLK

PCH_ENV DD<6>

1

@RF@

C1211

2

10P_0402_50V8J

D D

C C

U5

5

OUT

IN

GND

4

OC

EN

EM5203A J-20 SOT23 5P

SA00008 R900

EDP_HPD<6>

1

2

3

+LCDVDD

R3208

1 2

0_0805_ 5%

1 2

R126 0_040 2_5%@

Close to JEDP1

B B

W=60mils

1

2

4.7U_0402_6.3V6M

1

C96

C128

2

RF@

Close to R320 8

EDP_HPD _R

10P_0402_50V8J

+LEDVDD

1 2

R3213 0_0805_ 5%

B+

C133

4.7U_0603_25V6K

C53

RF@

Close to JEDP1

1 2 1 2

1

2

10P_0402_50V8J

EDP_TXN 1_C EDP_TXP 1_C

EDP_TXN 0_C EDP_TXP 0_C

EDP_AUX P_C EDP_AUX N_C

EDP_HPD _R

USB20_N 5<12>

USB20_P 5<12>

JeDP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26 27 28 29 30

CVILU_CVS 3302M1RE-NH

31

26

G1

32

27

G2

33

28

G3

34

29

G4

35

30

G5

eDP

Camera

DMIC

EDP_TXN 1<6> EDP_TXP 1<6>

EDP_TXN 0<6> EDP_TXP 0<6>

EDP_AUX P<6> EDP_AUX N<6>

+LCDVDD _CONN

BKOFF#<34 > INVPWM<6 >

DMIC_CLK<33> DMIC_DAT<33>

1

@

2

C139 0.1U_0201 _10V6K C138 0.1U_0201 _10V6K

C137 0.1U_0201 _10V6K C136 0.1U_0201 _10V6K

C135 0.1U_0201 _10V6K C134 0.1U_0201 _10V6K

W=60mils

+3VS

Place close to JeDP1

DA5

ESD@

3

I/O2

2

GND

DMIC_CLK

1 2

A A

ENBKL<6 ,34>

Compal For Lenovo

5

RC494 100K_04 02_5%

EDP_HPD

RC495 100K_04 02_5%

PCH_ENV DD

RC496 100K_04 02_5%

1 2 1 2

Security Classification

2018/2/5 2019/2/5

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2018/2/5 2019/2/5

3

Compal Secret Data

Deciphered Date

1

I/O1

L30ESDL 5V0C6-4_SOT23 -6

2

I/O4

VDD

I/O3

DMIC_DATUSB20_N 5

6

5

USB20_P 5

4

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

eDP / Camera

LA-G651P

28 52Friday, May 18, 201 8

1

0.2

5

4

3

2

1

HDMI

EMI

1 2

CPU_DP1_P3<6>

D D

CPU_DP1_N 3<6>

CPU_DP1_P2<6>

CPU_DP1_N 2<6>

CPU_DP1_P1<6>

CPU_DP1_N 1<6>

CH13 0.1U _0201_10V6K

1 2

CH14 0.1U _0201_10V6K

1 2

CH15 0.1U _0201_10V6K

1 2

CH16 0.1U _0201_10V6K

1 2

CH17 0.1U _0201_10V6K

1 2

CH18 0.1U _0201_10V6K

HDMI_CLKP

HDMI_CLKN

HDMI_TX_P0

HDMI_TX_N0

HDMI_TX_P1

HDMI_TX_N1

1 2

RH11 8.2_0402_1%EMI@

1 2

RH15 8.2_0402_1%EMI@

1 2

RH17 8.2_0402_1%EMI@

1 2

RH18 8.2_0402_1%EMI@

1 2

RH19 8.2_0402_1%EMI@

1 2

RH20 8.2_0402_1%EMI@

HDMI_L_CLKP

HDMI_L_CLKN

HDMI_L_TX_P0

HDMI_L_TX_N0

HDMI_L_TX_P1

HDMI_L_TX_N1

HDMI_L_CLKP HDMI_L_CLKN

HDMI_L_TX_P0 HDMI_L_TX_N0

HDMI_L_TX_P1 HDMI_L_TX_N1

HDMI_L_TX_P2 HDMI_L_TX_N2

EMI

1 2

RH12 150_0402_ 1%EMI@

1 2

RH13 150_0402_ 1%EMI@

1 2

RH14 150_0402_ 1%EMI@

1 2

RH16 150_0402_ 1%EMI@

+3VS

0.1U_0201_ 10V6K

@

CH12

+5VS

1

2

For HDMI

UH11

1

IN

AP2330W-7_ SC59-3

SA00004ZA00

OUT

GND

+5V_Display

CH11

0.1U_0201_10V6K

Close to UH11

1

CH21

2

RF@

10P_0402_50V8J

W=40mils

3

2

G

5

+3VS

HDMI_L_TX_P2

HDMI_L_TX_N2

ESD

12

RH23

1M_0402_5 %

CPU_DP1_H PD<6 >

2N7002KDW _SOT363-6

DH11

HDMI_CTRL_D AT H DMI_CTRL_DAT HDMI_L_TX_N0

HDMI_CTRL_C LK HDMI_CTRL_C LK

+5V_Display +5V_Display

@ESD@

9

10

8

9

7

6

L05ESDL5V0NA-4 _SLP2510P8-10-9

1

2

4

5

3

8

S

QH14A

G

2

D

61

12

RH24 20K_0402_5 %

HDMI_L_TX_N2

HDMI_L_TX_P2

HDMI_HPD

+5V_Display

HDMI_CTRL_D AT HDMI_CTRL_C LK

HDMI_L_CLKN

HDMI_L_CLKP HDMI_L_TX_N0

HDMI_L_TX_P0 HDMI_L_TX_N1

HDMI_L_TX_P1 HDMI_L_TX_N2

HDMI_L_TX_P2

DH12

@ESD@

HDMI_L_TX_N1HDMI_L_TX_N1

9

10

8

9

7

6

L05ESDL5V0NA-4 _SLP2510P8-10-9

1

2

4

5

3

8

1

2

4

5

3

HDMI_L_TX_P1HDMI_L_TX_P1

HDMI_L_TX_N2

HDMI_L_TX_P2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

LOTES_AHDM00 64-P001A

DC232007B 00 ME@

CPU_DP1_C TRL_CLK

HDMI_L_TX_P0

HDMI_L_CLKN HDMI_L_CL KNHDMI_HPD HDMI_HPD

HDMI_L_CLKP HDMI_L_ CLKP

23

GND

22

GND

21

GND

20

GND

1

CH22

2

@RF@

10P_0402_50V8J

DH13

9

10

8

9

7

6

L05ESDL5V0NA-4 _SLP2510P8-10-9

@ESD@

1

2

4

5

3

8

1

2

4

5

3

HDMI_L_TX_N0

HDMI_L_TX_P0

1 2

C C

CPU_DP1_P0<6>

CPU_DP1_N 0<6>

CH19 0 .1U_0201_10V6K

1 2

CH20 0 .1U_0201_10V6K

HDMI_TX_P2

HDMI_TX_N2

1 2

RH21 8.2_0402_1%EMI@

1 2

RH22 8.2_0402_1%EMI@

Near JHDMI1

1 2

RC498 470_02 01_5%

1 2

RC499 470_02 01_5%

1 2

RC500 470_02 01_5%

1 2

RC501 470_02 01_5%

1 2

RC502 470_02 01_5%

1 2

RC503 470_02 01_5%

1 2

RC504 470_02 01_5%

1 2

RC505 470_02 01_5%

34

D

QH14B

2N7002KDW _SOT363-6

B B

+3VS+3VS +5V_Display

2.2K_0402_5%

12

RH25

RH26

CPU_DP1_C TRL_CLK<6>

CPU_DP1_C TRL_DATA<6>

A A

2

5

3

4

QH15B 2N7002KDW _SOT363-6

QH15A 2N7002KDW _SOT363-6

61

S

2.2K_0402_5%

12

RH27

RH28

HDMI_CTRL_C LK

HDMI_CTRL_D AT

Security Classific ation

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number R ev

Custom

Date : Sheet o f

2

Date : Sheet o f

HDMI

LA-G651P

1

0.2

29 52Friday, May 18, 2018

0.2

5

UCM trace

EC_SMB_DA2_R

EC_SMB_CK2_R

D D

+5VALW

Close to Pin10

C C

B B

A A

From USB3

From DP

TO SOC

USB3_CRX_C_MTX_P3 USB3_CRX_C_MTX_N3

USB3_CTX_C_MRX_P3 USB3_CTX_C_MRX_N3

CPU_DP2_P0_C CPU_DP2_N0_C

CPU_DP2_P1_C CPU_DP2_N1_C

CPU_DP2_P2_C CPU_DP2_N2_C

CPU_DP2_P3_C CPU_DP2_N3_C

5

1 2

R3239 0_0402_5%

1 2

R3240 0_0402_5%@

1 2

R3241 0_0402_5%

1 2

R3242 0_0402_5%@

1 2

R3234 0_0603_5%@

4.7U_0402_6.3V6M

USB3_CRX_MTX_P3<12> USB3_CRX_MTX_N3<12>

USB3_CTX_MRX_P3<12> USB3_CTX_MRX_N3<12>

CPU_DP2_P0<6>

CPU_DP2_N0<6>

CPU_DP2_P1<6>

CPU_DP2_N1<6>

CPU_DP2_P2<6>

CPU_DP2_N2<6>

CPU_DP2_P3<6>

CPU_DP2_N3<6>

CPU_DP2_AUXP<6>

CPU_DP2_AUXN< 6>

CPU_DP2_HPD<6>

+LDO_3V3_5455

1 2

R3216 750k_0201_1%@

1 2

R3217 750k_0201_1%@

1 2

R3219 750k_0201_1%@

1 2

R3218 750k_0201_1%@

1 2

R3221 750k_0201_1%@

1 2

R3220 750k_0201_1%@

1 2

R3223 750k_0201_1%@

1 2

R3222 750k_0201_1%@

1 2

R3225 750k_0201_1%@

1 2

R3224 750k_0201_1%@

1 2

R3227 750k_0201_1%@

1 2

R3226 750k_0201_1%@

Compal For Lenovo

C167

R171

100K_0402_5%

10U_0402_6.3V6M

C158

1

@

2

+LDO_3V3_5455

12

C170 0.22U_0201_ 6.3V6M C171 0.22U_0201_ 6.3V6M

C173 0.22U_0201_ 6.3V6M C175 0.22U_0201_ 6.3V6M

C300 0.1 U_0201_10V6K C301 0.1 U_0201_10V6K

C302 0.1 U_0201_10V6K C303 0.1 U_0201_10V6K

C304 0.1 U_0201_10V6K C305 0.1 U_0201_10V6K

C306 0.1 U_0201_10V6K C307 0.1 U_0201_10V6K

C2179 0.1U_0201_10V6K C2180 0.1U_0201_10V6K

12

10U_0402_6.3V6M

1 2 1 2

C310

I2C_1_SDA <11>

EC_SMB_DA2 <8,24,3 4,36>

I2C_1_SCL <11>

EC_SMB_CK2 <8,24,3 4,36>

PD_INT#< 14,34>

6.2K_0402_1%

+3.3V_IN_5455

USB3_CRX_C_MTX_P3 USB3_CRX_C_MTX_N3

USB3_CTX_C_MRX_P3 USB3_CTX_C_MRX_N3

CPU_DP2_P0_C CPU_DP2_N0_C

CPU_DP2_P1_C CPU_DP2_N1_C

CPU_DP2_P2_C CPU_DP2_N2_C

CPU_DP2_P3_C CPU_DP2_N3_C

CPU_DP2_AUXP_C CPU_DP2_AUXN_C

EC_SMB_DA2_R EC_SMB_CK2_R

R164

4

3

2

1

VBUS Discharge

+USBC_VBUS

12

R168 100_1206_5%@

13

VBUS_DSCHG

R3203

100K_0402_5%

@

Dead battery funct ion Cfig. pin. Tie t o GND to disable dead battery ‘ Rd’ .

U16

MUX

10

VCON_IN

25

5V_IN

26

LDO_3V3

39

SSRX_1P/2N

40

SSRX_1N/2P

41

SSTX_1P/2N

42

SSTX_1N/2P

35

DP0_1P/2N

36

DP0_1N/2P

43

DP1_1P/2N

44

DP1_1N/2P

45

DP2_1P/2N

46

DP2_1N/2P

37

DP3_1P/2N

38

DP3_1N/2P

1

AUX_P/MGPIO4

2

AUX_N/MGPIO5

34

HPD

5

H_DP/DCI_DATA/MGPIO2

6

H_DM/DCI_CLK/MGPIO3

31

SM_SDA/GPIO6

32

SM_SCL/GPIO5

33

SM_INT/GPIO4

24

REXT

12

47

E-PAD

4

Realte k RTS545 5

10Gps 3:2 MUX

Low Speed MUX

BC1.2 Switch

MGPIO10/

LOC_PWR_MON

RTS5455-GR_QFN46_6P5X4P5

Floating to ena ble dead battery ‘ Rd’

DB_CFG

1 2

20

9 11

USB3_DP2_MTX_DRX_P2

15

USB3_DP2_MTX_DRX_N2

14

USB3_DP2_MRX_DTX_P2

19

USB3_DP2_MRX_DTX_N2

18

USB3_DP2_MTX_DRX_P1

13

USB3_DP2_MTX_DRX_N1

12

USB3_DP2_MRX_DTX_P1

17

USB3_DP2_MRX_DTX_N1

16

3 4

7

VBUS_DSCHG

8

30 29 28 27

22 21

LOC_PWR_MON

23

R157 0_0402_5%

1 2

C168 220 P_0402_50V8J

1 2

C169 220 P_0402_50V8J

C2204 0.33U_0201_6.3V6M C2203 0.33U_0201_6.3V6M

C2202 0.33U_0201_6.3V6M C2201 0.33U_0201_6.3V6M

VMON_5455

3

C2193 0.1U_0201_10V6K C2194 0.1U_0201_10V6K

C2195 0.1U_0201_10V6K C2196 0.1U_0201_10V6K

DP2_AUXP_SBU1 <31> DP2_AUXN_SBU2 <31>

USBC_EN < 31>

DB_CFG

C_TX2_1P/2N C_TX2_1N/2P

C_RX2_1P/2N C_RX2_1N/2P

C_TX1_1P/2N C_TX1_1N/2P

C_RX1_1P/2N C_RX1_1N/2P

SBU1/MGPIO6 SBU2/MGPIO7

C_DP/BB_DP

C_DM/BB_DM

I2C_SCL/GPIO7 I2C_SDA/GPIO8

I2C_INT/GPIO9

I2C_EN/GPIO10

MGPIO8/

IMON

MGPIO9/

VMON

CC1 CC2

ISP Channel via CCs

PD_CC1 <31 > PD_CC2 <31 >

1 2 1 2

DP2_AUXP_SBU1

DP2_AUXN_SBU2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

USB3_DP2_MTX_C_DRX_P2 <31> USB3_DP2_MTX_C_DRX_N2 <31>

USB3_DP2_MRX_C_DTX_P2 <31> USB3_DP2_MRX_C_DTX_N2 <31>

USB3_DP2_MTX_C_DRX_P1 <31> USB3_DP2_MTX_C_DRX_N1 <31>

USB3_DP2_MRX_C_DTX_P1 <31> USB3_DP2_MRX_C_DTX_N1 <31>

12

R163

1M_0402_5%

R165 1M_0402_5%

@

Compal Secret Data

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

2

USB3_DP2_MRX_C_DTX_P2 USB3_DP2_MRX_C_DTX_N2

USB3_DP2_MRX_C_DTX_P1 USB3_DP2_MRX_C_DTX_N1

+USBC_VBUS

12

R169 200K_0402_1%

12

R3202 10K_0402_1%

@

1 2

R3228 220K_0201_1%

@

1 2

R3229 220K_0201_1%

@

1 2

R3232 220K_0201_1%

@

1 2

R3233 220K_0201_1%

Title

Size

Custom

Date : Sheet of

D

2

Q9

@

G

IRLML2030TRPBF_SOT23-3

SB00001J300

12

S

+LDO_3V3_5455 +5VALW

LOC_PWR_MONV MON_5455

CPU_DP2_AUXN_C

CPU_DP2_AUXP_C

12

R303 590K_0402_1%

SD034590380

R302 10K_0402_5%

1 2

+LDO_3V3_5455

30 52Friday, May 18, 2018

12

100K_0402_5%

R113

R3204 100K_0402_5%

1 2

12

R221

@

10K_0402_5%

12

R222

10K_0402_5%

0314_Add Connect 'LOC_PWR' net to local power for F/W to decide if C port can become provider via PR_SWAP. Leave floating if no local power exists in the system or in the application that 545x can only be powered on by local power.

Compal Electronics, Inc.

Type-C_RTS5455

Document Number Rev

LA-G651P

1

0.2

5

4

3

2

1

+USBC_VBUS

JUSBC1

A1

GND_A1

USB3_DP2_MTX_C_DRX_P1<30> USB3_DP2_MTX_C_DRX_N1<30>

D D

DP2_AUXP_SBU1<30>

USB3_DP2_MRX_C_DTX_N2<30> USB3_DP2_MRX_C_DTX_P2<30>

C C

1 2

C311 0.47U_0402_25V6K@

PD_CC1< 30> DP2_AUXN_SBU2 <30>

USB20_P3_R USB20_N3_R

1 2

C313 0.47U_0402_25V6K

@

A2

TX1+

A3

TX1-

A4

VBUS_A4

A5

CC1

A6

D+_A6

A7

D-_A7

A8

SBU1

A9

VBUS_A9

A10

RX2-

A11

RX2+

A12

GND_A12

1

GND1

2

GND2

3

GND3

JAE_DX07SL24JJ2

ME@

GND_B12

VBUS_B9

TOP

Bottom

VBUS_B4

GND_B1

RX1+

SBU2

D-_B7

D+_B6

TX2+

GND4 GND5 GND6

+USBC_VBUS

B12

B11 B10

RX1-

B9

B8

B7 B6

B5

CC2

B4

B3

TX2-

B2

B1

4 5 6

USB20_N3_R USB20_P3_R

C312 0.47U_0402_25V6K@

C314 0.47U_0402_25V6K

@

1 2

PD_CC2 <30>

USB3_DP2_MRX_C_DTX_P1 <30> USB3_DP2_MRX_C_DTX_N1 <30>

USB3_DP2_MTX_C_DRX_N2 <30> USB3_DP2_MTX_C_DRX_P2 <30>

DT245

ESD@

L30ESD24VC3-2_SOT23-3

2

3

1

USB20_P3<12>

USB20_N3<12>

USB3_DP2_MTX_C_DRX_P2

USB3_DP2_MTX_C_DRX_N2 USB3_DP2_MTX_C_DRX_N2

USB3_DP2_MTX_C_DRX_P1 USB3_DP2_MTX_C_DRX_P1

USB3_DP2_MTX_C_DRX_N1 USB3_DP2_MTX_C_DRX_N1

USB3_DP2_MRX_C_DTX_P2

USB3_DP2_MRX_C_DTX_N2

USB3_DP2_MRX_C_DTX_P1

USB3_DP2_MRX_C_DTX_N1

ESD for USBC1 Lines and Control

lines

USB20_P3_R

L5

EMI@

1

4

DLM0NSN900HY2D_4P

D44

ESD@

D46

ESD@

I/O2

VDD

GND

I/O1

2

3

10

9

7

6

10

9

7

6

D45

I/O4

I/O3

4

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

SC300001Y00

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

SC300001Y00

3

2

1

L30ESDL5V0C6-4_SOT23-6

2

3

USB3_DP2_MTX_C_DRX_P2

9

8

7

6

USB3_DP2_MRX_C_DTX_P2

9

USB3_DP2_MRX_C_DTX_N2

8

USB3_DP2_MRX_C_DTX_P1

7

USB3_DP2_MRX_C_DTX_N1

6

5

+5VALW

USB20_N3_R

4

USB20_P3_R

USB20_N3_R

+5VALW

3A/Active High

U65

1

OUT

IN

2

GND

SET

FLAG3EN

B B

A A

1

RF@

2

C2177

USBC_EN<30> ILIM_select <34>

2

C2174

10P_0402_50V8J

0.1U_0201_10V6K

100K_0402_5%

ILIM_R

R2029

6

5

4

AP22615AWU-7 TSOT26

12

+USBC_VBUS

W=80mils

1

2

C2176

1

2

C2175

@

C2207

C2208

470P_0402_50V7K

22U_0603_6.3V6M

100U_1206_6.3V6M

22U_0603_6.3V6M

Compal For Lenovo

5

4

ILIM_R

12

R3243

2.2K_0402_5%

1 2

R3245 0_0402_5%

13

12

R3244

2.2K_0402_5%

ILIM = 680 0/ RSET ILIM_select = L , ILIM = 3 A ILIM_select = F , ILIM = 1.5 A

D

2

G

S

Q145

@

2N7002KW_SOT323-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2

DP2_AUXP_SBU1

DP2_AUXN_SBU2

PD_CC1

PD_CC2

D52

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

ESD@ SC300001Y00

9

10

8

9

7

6

Title

Type-C_RTS5455_CONN

Size

Document Number Re v

C

Date: Sheet

DP2_AUXP_SBU1

DP2_AUXN_SBU2

PD_CC1

PD_CC2

Compal Electronics, Inc.

LA-G651P

1

of

31 52Friday, May 18, 2018

of

31 52Friday, May 18, 2018

of

31 52Friday, May 18, 2018

0.2

A

B

C

D

E

F

G

H

SSD(Key M)

1 1

SSD PCIE

2 2

PCIE_CRX_DTX_N9<12> PCIE_CRX_DTX_P9<12 >

PCIE_CTX_DRX_N9<12> PCIE_CTX_DRX_P9<12 >

PCIE_CRX_DTX_N10<12> PCIE_CRX_DTX_P10<12>

PCIE_CTX_DRX_N10<12> PCIE_CTX_DRX_P10<12>

PCIE_CRX_DTX_N11<12> PCIE_CRX_DTX_P11<12>

PCIE_CTX_DRX_N11<12> PCIE_CTX_DRX_P11<12>

PCIE_CRX_DTX_N12<12> PCIE_CRX_DTX_P12<12>

PCIE_CTX_DRX_N12<12> PCIE_CTX_DRX_P12<12>

CLK_PCIE_N4<10> CLK_PCIE_P4<10>

NGFF WLAN /BT(Key E)

1

CC3870

CW6

4.7U_0402_6.3V6M

2

@RF@

10P_0402_50V8J

GND +3P3A

USB_D- LED#1

GND WGR_D1N WGR_D1P

GND WGR_D0N WGR_D0P

GND WGR_CLKN WGR_CLKP

GND

PETp0

PETn0

GND

PERp0

PERn0

GND

REFCLKP0 REFCLKN0

GND

CLKREQ0# PEWake0 #

GND

WT_D1N WT_D1P

GND

WT_D0N WT_D0P

GND

WT_CLKN WT_CLKP

GND

PCIE_CTX_DRX_P8<12 > PCIE_CTX_DRX_N8<12>

PCIE_CRX_DTX_P8<12 > PCIE_CRX_DTX_N8<12>

CLK_PCIE_P2<10>

CLK_PCIE_N2<10>

CLKREQ_PCIE#2<10>

EC_PCIE_WAKE#<34>

USB20_P10<12>

USB20_N10<12>

CNV_CRX_DTX_N1 CNV_CRX_DTX_P1

CNV_CRX_DTX_N0 CNV_CRX_DTX_P0

CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P

CNV_CTX_DRX_N1 CNV_CTX_DRX_P1

CNV_CTX_DRX_N0 CNV_CTX_DRX_P0

CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P

1 2

RW6 0_0201_5%@

1 2

RW8 0_0201_5%@

1 2

RW10 0_0201_5%@

1 2

RW11 0_0201_5%@

1 2

RW12 0_0201_5%@

1 2

RW14 0_0201_5%@

Near JWLAN1

CC116 CC117

RWL158 0_0402_5% RWL162 0_0402_5%@

1 2

RW26 0_0201_5%@

1 2

RW27 0_0201_5%@

1 2

RW29 0_0201_5%@

1 2

RW30 0_0201_5%@

1 2

RW31 0_0201_5%@

1 2

RW32 0_0201_5%@

1 2 1 2

0.1U_0201_10V6K

CNV_CRX_R_DTX_N1 CNV_CRX_R_DTX_P1

CNV_CRX_R_DTX_N0 CNV_CRX_R_DTX_P0

CLK_CNV_CRX_R_DTX_N CLK_CNV_CRX_R_DTX_P

PCIE_CTX_C_DRX_P8 PCIE_CTX_C_DRX_N8

CLKREQ_PCIE#2_R WAKE#_R

CNV_CTX_R_DRX_N1 CNV_CTX_R_DRX_P1

CNV_CTX_R_DRX_N0 CNV_CTX_R_DRX_P0

CLK_CNV_CTX_R_DRX_N CLK_CNV_CTX_R_DRX_P

BT

CNV_CRX_DTX_N1<9> CNV_CRX_DTX_P1<9>

CNV_CRX_DTX_N0<9> CNV_CRX_DTX_P0<9>

CLK_CNV_CRX_DTX_N<9> CLK_CNV_CRX_DTX_P<9>

3 3

WLAN

CNV_CTX_DRX_N1<9>

CNV_CTX_DRX_P1<9>

CNV_CTX_DRX_N0<9>

CNV_CTX_DRX_P0<9>

CLK_CNV_CTX_DRX_N<9> CLK_CNV_CTX_DRX_P<9>

4 4

1

CW7

CNVi@

0.1U_0201_10V6K

CNVi@

2

Close to KEY E p in72,74 Clo se to KEY E pin2,4

CNVi Module PIN Def i ne

JWLAN1

1

GND_1

3

USB_D+

5

USB_D-

7

GND_7

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DAT0

15

SDIO_DAT1

17

SDIO_DAT2

19

SDIO_DAT3

21

SDIO_WAKE

23

SDIO_RST

33

GND_33

35

PET_RX_P0

37

PET_RX_N0

39

GND_39

41

PER_TX_P0

43

PER_TX_N0

45

GND_45

47

REFCLK_P0

49

REFCLK_N0 GND_51 CLKREQ0# PEWAKE0# GND_57 RSVD/PCIE_RX_P1 RSVD/PCIE_RX_N1 GND_63 RSVD/PCIE_TX_P1 RSVD/PCIE_TX_N1 GND_69 RSVD_71 RSVD_73 GND_75

GND2

LOTES_APCI0147-P007A

SP07001GF00

ME@

SUSCLK(32KHz)

51 53 55 57 59 61 63 65 67 69 71 73 75

77

Note: The real beh avior of BT_DISABLE are BT_DISABLE=LOW, BT=OFF

BT_DISABLE=HIGH, BT=ON

Near JSSD1

1 2

C2182 0.22U_0201_6.3V6M

1 2

C2181 0.22U_0201_6.3V6M

1 2

C2185 0.22U_0201_6.3V6M

1 2

C2186 0.22U_0201_6.3V6M

1 2

C2183 0.22U_0201_6.3V6M

1 2

C2184 0.22U_0201_6.3V6M

1 2

C2188 0.22U_0201_6.3V6M

1 2

C2187 0.22U_0201_6.3V6M

+3VS_WLAN +3VS_WLAN

1

CW8

0.01U_0402_16V7K

CNVi@

2

+3VS_WLAN

2

3.3VAUX_2

4

+3P3AUSB_D+

3.3VAUX_4

6

LED1#

8

PCM_CLK

10

RF_RESET_B

PCM_SYNC

12

PCM_IN

PCM_OUT

14

CLKREQ0

PCM_IN

16

LED2#

18

GND/LNA_EN

GND_18

20

UART WAKE#

UART_WAKE

22

BRI_RSP

UART_TX

32

RGI_DT

UART_RX

34

RGI_RSP

UART_RTS

36

BRI_DT

UART_CTS

38

Clink RESET

CLink_RST

40

Clink DATA

CLink_DATA

42

Clink CLK

CLink_CLK

44

COEX3

46

COEX_RXD

COEX2

48

COEX_TXD

COEX1

50

C_P32K

52

PERST0#

54

I2C_DAT

I2C_CLK

I2C_IRQ RSVD_64 RSVD_66 RSVD_68 RSVD_70

3.3VAUX_72

3.3VAUX_74

GND1

W_DISABLE2#

56

W_DISABLE1#

58

A4WP_I2C_DATA

60

A4WP_I2C_C LK

62

A4WP_IRQ#

64

REFCLK0

66

PERST1#

68

CLKREQ1#

70

PEWake1 #

72

+3P3A

74

+3P3A

76

GND

W_DISABLE2# W_DISABLE1#

PCIE_CTX_C_DRX_N9 PCIE_CTX_C_DRX_P9

PCIE_CTX_C_DRX_N10 PCIE_CTX_C_DRX_P10

PCIE_CTX_C_DRX_N11 PCIE_CTX_C_DRX_P11

PCIE_CTX_C_DRX_N12 PCIE_CTX_C_DRX_P12

1

CW1

4.7U_0402_6.3V6M

2

Jefferson Peak:1360mA@peak current Thunder_Peak_2:1100mA@peak current

CNV_RF_RESET#_R

CLKREQ_CNV#_R

CNV_BRI_CRX_R_DTX

CNV_RGI_CTX_R_DRX CNV_RGI_CRX_R_DTX CNV_BRI_CTX_R_DRX

WLAN_COEX3

RW41 0_0201_5%@

WLAN_COEX2

RW42 0_0201_5%@

WLAN_COEX1

RW43 0_0201_5%@

CLKIN_XTAL

1

CW2

0.1U_0201_10V6K

CNVi@

2

1 2

RW7 33_0201_5%CNVi@

1 2

RW9 33_0201_5%CNVi@

1 2

RW44 0_0201_5%NONCNVi@

1 2

RW39 22_0402_5%CNVi@

1 2

RW45 0_0201_5%NONCNVi@

1 2

RW40 75_0402_5%CNVi@

1 2

RW16 22_0402_5%CNVi@

1 2

RW33 75_0402_5%CNVi@

1 2 1 2 1 2

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57

67 69 71 73 75

77

JSSD1

1

GND

3

GND

5

PERn3

7

PERp3

9

GND PETn3 PETp3 GND PERn2 PERp2 GND PETn2 PETp2 GND PERn1 PERp1 GND PETn1 PETp1 GND PERn0/SATA B+ PERp0/SATA BGND PETn0/SATA APETp0/SATA A+ GND REFCLKn REFCLKp GND

N/C PEDET GND GND GND

MTG77

LOTES_APCI0146-P008A

SP07001GE00

ME@

1

2

EC_TX <34,35>

EC_RX <34,35>

+3VS

100 MIL

1 2

R3210 0_0805_5%

3.3VAUX

DAS/DSS#

3.3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK

3.3VAUX

MTG76

1

RF@

CW3

2

10P_0402_50V8J

CC3871

CNVi@

0.01U_0402_16V7K

CNV_RF_RESET# <9>

CLKREQ_CNV# <9>

UART0_RX <11,35> CNV_BRI_CRX_DTX <11>

UART0_TX <11,35>

CNV_RGI_CTX_DRX <11>

CNV_RGI_CRX_DTX <11>

CNV_BRI_CTX_DRX <11>

COEX3 <9> COEX2 <9> COEX1 <9> SUSCLK <10>

PCI_RST# < 10,21,34>

WLBT_OFF# < 9>

WL_OFF# <12>

CLKIN_XTAL <10>

+3VS_SSD

2 4 6

N/C

8

N/C

10 12 14 16 18 20

N/C

22

N/C

24

N/C

26

N/C

28

N/C

30

N/C

32

N/C

34

N/C

36

N/C

38 40

N/C

42

N/C

44

N/C

46

N/C

48

N/C

50 52 54 56

N/C

58

N/C

68 70 72 74

76

PCI_RST#

NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi]

For Power consumption Measurement

+3VALW

The connect ivity module power s upply pin shall be connected d irectly to thr rail DSW. From 5672 40_In tel_W irele ss_AC _956 0_Jef ferso n_Pea k_EP S_ Rev 1.1

CNV_RGI_CTX_R_DRX

CNV_BRI_CTX_R_DRX

CNVi_PWR_EN<3 4>

+3VS_SSD

0.01U_0402_16V7K

C1176

1

C92

@

2

RF@

10P_0402_50V8J

CLKREQ_PCIE#4 <10>

NONCNVi@

1 2

RW46 0_0603_5%

422.18mA

1 2

RW47 0_0603_5%@

PCH EDS : M.2 CNV Mode Select

GPP_F6/CNV_ RGI_DT

0 = Integrated CNVi enable.

1 = Integrated CNVi disable.

1 2

RC449 20K_0201_5%

1 2

RC3940 20K_0201_5%@

EC_TX

12

RW23100K_0402_5%

1 2

CLKREQ_CNV#

RW3571.5K_0402_1% CNVi@

CNVi_PWR_EN CNV i_PWR_EN_R

RC3937 0_0402_5%

1

2

+3VS_WLAN+3VS

Imax : 2.0 A

1 2

CNVi@

0.1U_0201_10V6K

C1177

+3VALW

1

C1179

C1178

2

@

10U_0402_6.3V6M

+1.8VALW

Need to stuff for CNVi power sequence control

1U_0201_6.3V6M

CC3861

12

+3VS_WLAN

UC13

CNVi@

5

VIN

4

EN

1U_0201_6.3V6M

CC3864

12

EM5203AJ-20 SOT23-5

CNVi@

I (Max) : 2.0 A(+3VS_WLAN) RDS(Typ) : 70 mohm V drop : 0.14 V

Active Low

CNVi_PWR_EN

+3VS_WLAN +3VALW

QWL1

123

DGS

@

PJ2301 1P SOT23-3

SB00000T900

+3VS_WLAN

Imax : 2.0 A

1

CC3863

CNVi@

0.1U_0201_10V6K

2

1

VOUT

2

GND

3

/OC

1 2

RC3943 10K_0402_5%@

Security Classification

Issued Date

Compal For Lenovo

A

B

C

D

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

E

2018/2/5 2019/2/5

Compal Secret Data

F

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet of

G

NGFF SSD/WLAN

Document Number Rev

LA-G651P

0.2

32 52Friday, May 18, 2018

H

0.2

A

ALC3240

+3VDD_CODEC

+1.8VS

@

1 1

12

HDA_SDIN0<9>

Place RA10 & CA12 on AGND moat

wide 40MIL

2 2

EMI

+MIC2-VREFO

CA1222P_0402_50V8J @EMI@

1 2

RA6 2.2K_0402_5%

1 2

AGND

RA7

AGND AGND

RA1233_0402_5%

HDA_SDOUT_R<9>

HDA_BIT_CLK_R<9>

2.2K_0402_5% CA19 2.2U_0201_6.3V6M

PC_BEEP

EXT_MIC_RING2 EXT_MIC_SLEEVE

1 2

SPK_L2+ SPK_L1SPK_R1SPK_R2+

1 2

HDA_SYNC_R<9>

HDA_SDIN0_AUDIO

12

RA1033_0402_5% @EMI@

CA262.2U_0201_6.3V6M

LDO1 LDO2

CA162.2U_0201_6.3V6M

LDO3

CA132.2U_0201_6.3V6M

4.7U_0402_6.3V6M

11

13 14 15 23

35 36 37 38

21 32

10

2

CA17

1

UA1

7

SDATA-IN

4

SDATA-OUT

PCBEEP

5

BCLK

MIC2-L(PORT-F-L)/RING MIC2-R(PORT-F-R)/SLEEVE MIC2-CAP MIC2-VREFO

SPK-OUT-LP SPK-OUT-LN SPK-OUT-RN SPK-OUT-RP

LDO1-CAP LDO2-CAP

6

LDO3-CAP

DC DET

9

SYNC

+5VDDA_CODEC

B

Place near Pin34

2

CA1

1

4.7U_0402_6.3V6M

1

34

29

39

DVDD

HPOUT-L(PORT-I-L)

PVDD1

PVDD2

CPVDD

HPOUT-R(PORT-I-R)

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

LINE1-VREFO-L

HP/ LINE1-JD(JD1)

GPIO0/DMIC-DATA12

GPIO1/DMIC-CLK

AVDD2

AVSS2

AVDD120AVSS1

VD33STB

33

31

19

16

+3VALW

AGND

Moat

+1.8VS_codec

1 2

RA5

1 2

CA8 1U_0201_6.3V6M

Place near Pin33

+5VS_PVDD

1

CA3

2

0.1U_0201_10V6K

VREF

CPVEE

DVDD-IO

THERMAL PAD

0_0402_5%@

CA32

25 26

22 27

17 18 24 12

2 3

8

28

CBN

30

CBP

40

PDB

41

+1.8VS

RA1 0_0805_5%

1

2

CA2

2

1

4.7U_0402_6.3V6M

Place near Pin39

VREF CPVEE

DMIC_DAT_R DMIC_CLK_R

EC_MUTE#_R

AGND

0.1U_0201_10V6K

HP_OUTL HP_OUTR

LINE1-R LINE1-L

PLUG_IN_R

12

Headp ho ne

+LINE1-VREFO-R

LA1

+IOVDD_CODEC

2

@

1

1 2

+5VS

1 2

CA15 1U_0402_16V6K

RA110_0402_5% @

RA8 10K_0402_5%

12

RA140_0402_5% @

BLM15EG221SN1D_2PEMI@

@

C

EMI

1

CA98 1U_0201_6.3V6M

2

12

VREF

CPVEE

External DMIC

DMIC_DAT <28> DMIC_CLK <28>

EC_MUTE# <34>

AGND

1

@

2

CA94

CA27

1U_0402_16V6K

1

@

2

CA95

CA20

1U_0402_16V6K

Head Phone Input

place close audio codec

+3VDD_CODEC

1U_0201_6.3V6M

PLUG_IN_R

Audio Combo Jack

W=40mils W=40mils

1U_0201_6.3V6M

For Universal Audio J ack

LINE1-L

LINE1-R

+LINE1-VREFO-R

Speaker

RA51 100K_0402_1%

1 2

RA13 200K_0402_1%

EXT_MIC_SLEEVE EXT_MIC_RING2 HP_OUTL HP_OUTR

1 2

CA96 1U_0201_6.3V6M

1 2

CA21 1U_0402_16V6K@

1 2

CA22 1U_0402_16V6K@

1 2

CA97 1U_0201_6.3V6M

1 2

RA29 4.7K_0402_5%

1 2

RA32 4.7K_0402_5%

D

PLUG_IN <37>

RA19 BLM15BD121SN1D_2P SM010009U00EMI@ RA20 BLM15BD121SN1D_2P SM010009U00EMI@

12 12

@

RA26

10K_0402_5%

AGND AGND AGND AGND AGND AGND

EMI

1 2

RA22 47_0402_5%EMI@

1 2

RA23 47_0402_5%EMI@

SD028470A80 SD028470A80

@

RA27

1 2

10K_0402_5%

@EMI@

CA33

470P_0402_50V7K

E

HGNDB <37> HGNDA <37> HPOUT_L <37> HPOUT_R <37>

1

2

1

@EMI@

2

CA34

470P_0402_50V7K

@EMI@

2

CA35

CA36

470P_0402_50V7K

+3VS to +3VDD_CODEC +5VS to +5VDDA_CODEC +3VS to +IOVDD_CODEC

EMI

SPEAK 4 ohm: 40MIL SPEAK 8 ohm: 20MIL

SPK_R1-

3 3

RA2 0_0603_5%

Place near Pin1

+3VDD_CODEC+3VS +5VS

12

@

1U_0201_6.3V6M

1

12

CA5

CC91

CA4

2

0.1U_0201_10V6K

@RF@

RA4 0_0603_5%

1

2

Place RA4 on AGND moat

10P_0402_50V8J

12

@

PC Beep

EC Beep APU Beep

4 4

BEEP#<34>

HDA_SPKR<9>

1 2

RA41 47K_0402_5%

1 2

RA40 47K_0402_5%

BEEP_N

1

2

AGND

CA40

100P_0402_50V8J

12

@ESD@

RA39 27K_0402_5%

update from 4K7 to 27K

Compal For Lenovo

A

+5VDDA_CODEC +IOVDD_CODEC+3VS

1U_0201_6.3V6M

1

CA93

2

@RF@

10P_0402_50V8J

CA11

12

AGND

Place near Pin20

1

CA7

2

0.1U_0201_10V6K

place close to audio codec

1 2

CA37 0.1U_0201_10V6K

B

PC_BEEP

@

12

RA3 0_0603_5%

1

Place near Pin8

At least one R-Short short close to UA1

1 2

RA42 0_0402_5%

@

1 2

RA43 0_0402_5%

@

1 2

RA44 0_0402_5%

@

1 2

RA45 0_0402_5%

@

Moat

CA6

2

0.1U_0201_10V6K

AGNDGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SPK_R2+

SPK_L2+ SPK_L1-

ESD protection needs to be placed near connector side

ESD

Compal Secret Data

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

1 2

R3247 0_0603_5%

1 2

R3246 0_0603_5%

SPK_R2+

SPK_R1-

D

3

L03ESDL5V0CC3-2_SOT23-3

1

CA30

CA31

2

1000P_0402_50V7K

EMI@

SPK_L2+_R SPK_L1-_R

1

CA29

CA28

2

1000P_0402_50V7K

EMI@

SPK_L2+_R

SPK_L1-_R

2

DA3

@ESD@

1

Title

Size

C

Date: Sheet

EMI@

1

2

1000P_0402_50V7K

2

3

DA4

@ESD@

1

L03ESDL5V0CC3-2_SOT23-3

Compal Electronics, Inc.

HD Audio Codec_ALC3240

Document Number Re v

1000P_0402_50V7K

LA-G651P

E

JSPK1

1

2

3

G1

4

G2

ACES_50278-00201-001

SP02000EZ10 ME@

JSPK2

1

2

3

G1

4

G2

ACES_50278-00201-001

SP02000EZ10 ME@

0.2

of

33 52Friday, May 18, 2018

of

33 52Friday, May 18, 2018

of

33 52Friday, May 18, 2018

+3VALW_EC

1 2

+3VS

RC3944 10K_0402_5%DIS@

R201

R202

2.2K_0402_5%

1 2

+3VALW_EC

EC_SMB_CK1

EC_SMB_DA1

L20

1 2

BLM15AX601SN1D_2P

SM01000KL00

L21

1 2

BLM15AX601SN1D _2P

SM01000KL00

+3VALW_EC

GPU_PROHOT#

EMI

C184

0.1U_0201_10V6K

@EMI@

C186 22P_0402_50V8J

1 2

R192 47K_0402_5%@

0.1U_0201_10V6K

+3VL +3VL

R189 0_0603_5%@

+EC_VCCA

1

2

ECAGND

@EMI@

12

R190

12

10_0402_1%

2

PM_CLKRUN#<8>

C187

1

@

KSO[0..15]<35>

KSI[0..7]<35>

C180

0.1U_0201_10V6K

PD_INT#<14,30>

SERIRQ<8>

LPC_FRAME#<8>

LPC_AD3<8> LPC_AD2<8> LPC_AD1<8> LPC_AD0<8>

CLK_LPC_EC<8>

PCI_RST#<10,21,32>

EC_SCI#<6>

KB_MUTLI_KEY<35> GPU_PROHOT#<24,36>

EC_SMB_CK1<40,41> EC_SMB_DA1<40,41> EC_SMB_CK2<8,24,30,36> EC_SMB_DA2<8,24,30,36>

PM_SLP_S3#<10>

USB_CHG_CTL1<37>

EC_CLEAR_CMOS#<10>

USB_CHG_CTL3<37>

USB_CHG_EN<37>

USB_CHG_CTL2<37>

USB_CHG_STATUS#<37>

KB_BL_PWM<35>

EC_FAN_SPEED1<36>

EC_TX<32,35> EC_RX<32,35>

PCH_PWROK<10>

VR_PWRGD<46>

PBTN_OUT#<10>

PM_SLP_S4#<10,41>

1 2

+3VALW_EC

C181

0.1U_0201_10V6K

1

2

U11

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC & MISC

LPC_AD0

12

CLK_PCI_EC

13

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

EC_RST#

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CLK1/GPIO44

78

EC_SMB_DAT1/GPIO45

79

EC_SMB_CLK2/GPIO46

80

EC_SMB_DAT2/GPIO47

6

PM_SLP_S3#/GPIO04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESENT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEED1/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

PBTN_OUT#/GPIO5D

123

PM_SLP_S4#/GPIO5E

Int. K/B Matrix

+EC_VCCA

9

22

33

96

111

125

VCC

VCC0

VCC_LPC

PWM Output

VCIN1_BATT_TEMP/AD0/GPIO38

VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

SM Bus

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA07

GPIO

GPO

GPI

GND

11

24

35

94

113

67

AVCC

EC_VCCST_PG/GPIO0F

BEEP#/GPIO10

EC_FAN_PWM/GPIO12

AC_OFF/GPIO13

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

AD4/GPIO42 AD5/GPIO43

DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA2/GPIO3E DA3/GPIO3F

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

PSCLK2/GPIO4C PSDAT2/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH1/GPXIOD00

MISO/GPIO5B MOSI/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

EC_CIR_RX/AD6/GPIO40

SYS_PWROK/AD7/GPIO41

GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

DPWROK_EC/GPIO59

EC_RSMRST#/GPXIOA03

GPXIOA04

BKOFF#/GPXIOA08

GPXIOA09

PCH_PWR_EN/GPXIOA10

PWR_VCCST_PG/GPXIOA11

VCIN1_AC_IN/GPXIOD01

EC_ON/GPXIOD02 ON/OFF#/GPXIOD03 LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

PECI/GPXIOD07

V18R/VCC_IO2

AGND

KB9022QD_LQFP128_14X14

69

SA000075S30

ECAGND

21 23 26 27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

1 2

PECI

R208 43_0402_1%

124

4.7U_0402_6.3V6M

1

C192

2

VCCST_PWRGD <10> BEEP# <33> EC_FAN_PWM1 <36> ILIM_select <31>

VCIN1_BATT_TEMP <40,41>

ADP_I <41> CUST_TEMP3 <36>

GPU_OVERT# <24>

CUST_TEMP2 <36>

NOVO# <35> TP_DISABLE# <35> DGPU_PWR_EN <11,24,26> USB_EN# <37>

USB_CHG_ILIM_SEL <37>

ENBKL <6,28>

SYS_PWROK <10>

ME_EN <9>

VCIN0_PH1 <40>

EC_SPI_MISO <8> EC_SPI_MOSI <8> EC_SPI_CLK <8> EC_SPI_CS0# <8>

CUST_TEMP1 <36>

EC_MUTE# <33> BATT_CHG_LED# <37> CAPS_LED# <35> PWR_LED# <35,37> BATT_LOW_LED# <37>

SYSON <13,43,44>

VR_ON <46>

AC_PRESENT <10,24>

EC_RSMRST# <10>

3V/5VALW_PG <37,38,42,44>

VCOUT1_PROCHOT# <41>

VCOUT0_MAIN_PWR_ON <42>

BKOFF# <28>

CNVi_PWR_EN <32>

EC_PCIE_WAKE# <32>

VCIN1_AC_IN <41>

EC_ON <42>

ON/OFF# <35,36>

LID_SW# <37>

SUSP# <13,38,43>

H_PECI <6>

+3VALW_EC

USB_EN#

EC_MUTE#

LID_SW#

KB_MUTLI_KEY

EC_SPI_CS0#

VCIN1_BATT_TEMP

VCIN1_AC_IN

SUSP#

BKOFF#

EC_FAN_SPEED1

GPU_OVERT#

PD_INT#

ON/OFF#

1 2

R194 10K_0402_5%

R198 10K_0402_5%@

1 2

R1665 100K_0402_5%

1 2

RC507 10K_0402_5%

1 2

R3235 100K_0402_5%

Follow ENE suggestion for Auto load

EC_PCIE_WAKE#

R212 4.7K_0402_5%@

PBTN_OUT#

R195 10K_0402_5%@

R1664 100K_0402_5%@

R3238 100K_0402_5%

RC508 10K_0402_5%

RC509 10K_0402_5%DIS@

RC506 10K_0402_5%

R3236 100K_0402_5%

C189 100P_0402_50V8J

C190 100P_0402_50V8J

1 2

12

ESD

0.1U_0201_10V6K

1 2

+5VALW

+3VALW

12

1

@ESD@

C197

2

+3VS

12

+3VL

Keyboard BackLight_SELECT

KB_BL_PWM

10K_0402_5%

NOKBL@

KBL_ID

R325

0

12

Funct i on

KBL 1

NO KBL

PH on KB side

Compal For Lenovo

PROHOT#

VCOUT1_PROCHOT#

VR_HOT#<46>

@

R204 0_0402_5%

1 2

@

1 2

R205 0_0402_5%

1

@

C191 47P_0402_50V8J

2

H_PROCHOT# <6>

ESD

PCI_RST#

ESD@

0.1U_0201_10V6K C188

1

2

Pin 13 Pin 32 Pin 36 Pin 21 Pin 95

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

VR_PWRGD

PCH_PWROK

C2178

100P_0402_50V8J

1

2

100P_0402_50V8J

1

ESD@

2

Title

Size Document Number Rev

Custom

Date: Sheet of

VCCST_PWRGD

C124

C123

ESD@

100P_0402_50V8J

1

@ESD@

2

Compal Electronics, Inc.

EC KB9022QD

LA-G651P

SYSON

1

2

C193

0.1U_0201_10V6K

@ESD@

0.2

34 52Friday, May 18, 2018

0.2

Finger printer

UART0_RX<11,32>

UART0_TX<11,32>

EC_TX<32,34>

EC_RX<32,34>

USB20_P6<12> USB20_N6<12>

Touch Pad

TP_DISABLE#<34>

GTW-0902-00-ASSY-V1.pdf

PD4SB_BL_KB_Darfon_2D_X07_20170731

Keyboard

JFP1

1

2

3

4

9

4

GND

10

55GND

6

7

+3VS

3

ESD@

DFP6

PESD5V0U2BT_SOT23-3

CFP166

0.1U_0201_10V6K

2

1

8

ACES_51580-00841-P01

SP01002GM00

ME@

ESD

@

1

2

+3VS

@

CTP165 100P_0402_50V8J

@

CTP163

0.1U_0201_10V6K

3

@ESD@

DTP5

PACDN042Y3R_SOT23-3

JTP1

1

2

3

4

5

6

7

G1

8

G2

SP01002DQ00

JXT_FP201CH-006G10M

ME@

2

1

+3VS

12

R280

4.7K_0402_5%

I2C_0_SCL<11> I2C_0_SDA<11> TP_INT#<9>

CTP164

100P_0402_50V8J

KSI[0..7]

KSO[0..15]

KSI[0..7] <34>

KSO[0..15] <34>

PWR Button

ON/OFF#<34,36>

+5VS

SN111005800

SKRBAAE010_4P

2

ME@

SP011509010

ACES_51510-0320N-P01

34

GND

33

CAPS_LED#<34>

1

SW2

C1378 0.1U_0201_10V6K

1

@ESD@

2

KB_MUTLI_KEY<34>

KSO15 KSO10 KSO11 KSO14 KSO13 KSO12

KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1

CAPS_LED#_R

12

R263 470_0201_5%

GND

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JKB1

Keyboard Backlight

RKBL5

1 2

30K_0402_1%

KBL@

+5VS

KBL@

QKBL121

S

G

2

D

13

ME2301DC-G_SOT23-3

1

KBL@

CKBL907

0.01U_0402_16V7K

2

+5VALW

12

KBL@

RKBL1 10K_0402_5%

KB_BL_PWM<34>

Compal For Lenovo

ESD

4

PN 510-004411-01 Rev 1

3

Novo Button

+3VL

R172

ME@ SP01001UE00

ACES_50524-00401-P01

4

+5VS_KBL

1

2

CKBL908

2

1

CKBL906

KBL@

@

0.1U_0201_10V6K

10U_0402_6.3V6M

G264

5

33G1

2

1

JKBL1

NOVO#<34>

100K_0402_5%

NOVO# NOVO#

1 2

1

SW1

2

43

TCHC2QR_2P

ON/OFF#

2

3

D23

ESD@

L03ESDL5V0CC3-2_SOT23-3

1

ESD

PWR LED

Power (White) (TOP)

LED2

PWR_LED#<34,37>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

21

LTW-C193TS5-C_WHITE

SC50000BB10

1 2

R173 412_0402_1%

Title

KB/KBL/LED/TP/FP Conn.

Size

Document Number R ev

C

Date: Sheet of

+VL

Compal Electronics, Inc.

LA-G651P

0.2

35 52Friday, May 18, 2018

0.2

5

4

3

2

1

Thermal Sensor

1

EX_THM@

CTS1

D D

2200P_0402_50V7K

2

+3V_Thermal

REMOT E1+ /-: Trace width/space:10/10 mil Trace leng th:<8"

+3VS

R390

0_0402_5%

1 2

+3V_Thermal

REMOTE1+

REMOTE1-

1 2

RTS340 4.7K_0402_5%

EX_THM@

CPU

UTS1

EX_THM@

ALERT#

8

SCL

7

SDA

6

5

1

VDD

2

D+

3

D-

T_CRIT#4GND

NCT7718W_MSOP8

SMB Address: 1001100x

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 <8, 24,30,34>

EC_SMB_DA2 <8, 24,30,34>

GPU_PROHOT# <24,34>

REMOTE1+

EX_THM@

100P_0402_50V8J

REMOTE1-

CTS2

1

2

B

2

Close to GPUClose to UTS1

C

QTS1

EX_THM@

MMST3904-7-F_SOT323-3

E

3 1

THERMISTOR

C C

CHARGER GPU CHOKE CPU CHOKE

+EC_VCCA

12

R364

16.5K_0402_1%

12

R366 100K +-1% 0402 B25/50 4250K

SL200002H00

ECAGND

+EC_VCCA

12

R365

16.5K_0402_1%

12

R367 100K +-1% 0402 B25/50 4250K

SL200002H00

ECAGND

DIS@

CUST_TEMP3<34>CUST_TEMP1<34> CUST_TEMP2<34>

DIS@

+EC_VCCA

12

R368

16.5K_0402_1%

12

R369 100K +-1% 0402 B25/50 4250K

SL200002H00

ECAGND

add. thermistors_by JC

FAN

B B

+5VS

1 2

R3214 0_0603_5%@

EC_FAN_SPEED1<34>

1

2

CF162

10U_0402_6.3V6M

A A

EC_FAN_PWM1<34>

+5VS_FAN1

JFAN1

4

6

4

GND

3

5

3

GND

2

1

JXT_FP202DH-004M10M

SP010022U00 ME@

Compal For Lenovo

5

4

ON/OFF# SHORT PADS

J1

BOT Side

TOP Side

1 2

SHORT PADS

J2

1 2

SHORT PADS

ON/OFF# <34, 35>

LASER BARCODE

ZZZ1

@

BARCODE_8X8

ZZZ2

@

BARCODE_20X4

IRON SHEET

H25

@

1

MB_SUP_BRK_25X5

ZZZ3

BARCODE_12X4

ZZZ4

BARCODE_10X10

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Issued Date

CPU VGA

H1 HOLEA

1

H_3P3

H7 HOLEA

@

1

H_3P8

FD1

1

FAN

H2 HOLEA

1

H_3P3

H8 HOLEA

1

H_3P2

FD2

FD3

1

2018/2/5 2019/2/5

H4

H3

HOLEA

1

H_3P3

H11

H10

H9 HOLEA

H_2P5

1

FD4

1

HOLEA

1

H_3P8

H_2P5

H17 HOLEA

1

H_5P0X2P5N

Compal Secret Data

H5 HOLEA

1

H_3P3

H15 HOLEA

1

H_2P5

H18 HOLEA

1

H_5P0X2P5N

Deciphered Date

H16 HOLEA

H_4P5

H6 HOLEA

1

H_3P3

1

H19 HOLEA

1

H_2P5N

2

H20 HOLEA

H_6P0N

1

Shielding Clip Larger

CLIP10 HOLEA

Smaller

CLIP1 HOLEA

CLIP17 HOLEA

CLIP12

CLIP11

HOLEA

@

1

CLIP2

CLIP3

HOLEA

@

1

@ 1

Title

Size

C

Date: Sheet of

CLIP14

CLIP13

HOLEA

@ 1

Compal Electronics, Inc.

Document Number R ev

@

1

CLIP5

CLIP4

HOLEA

@

1

FAN / Thermal Senser

CLIP15

CLIP16

HOLEA

@

1

CLIP7

CLIP6

HOLEA

@

1

LA-G651P

1

CLIP8 HOLEA

@ 1

CLIP9 HOLEA

@

1

0.2

36 52Friday, May 18, 2018

0.2

5

USB Charger

Down USB charger Iout ripple must under 2 0mA on DC S5

1

12

C225

C224

2

D D

C C

2

10U_0402_6.3V6M

@

USB_CHG_STATUS#<34>

USB_CHG_ILIM_SEL<34>

USB_CHG_EN<34> USB_CHG_CTL1<34> USB_CHG_CTL2<34> USB_CHG_CTL3<34>

12

C226

C227

10U_0402_6.3V6M

C239

22U_0603_6.3V6M

47U_0805_6.3V6M

22U_0603_6.3V6M

@

12

+5VALW

12

C238

C228

22U_0603_6.3V6M

47U_0805_6.3V6M

@

DM_IN

DM_OUT

DP_OUT

ILIM_LO

ILIM_HI

DP_IN

T-PAD

80mil

12

OUT

10 11 2 3 15 16 14

GND

17

+5V_CHGUSB+5VALW_USBCH

R3211 2.7M_0402_1% R3212 24.9K_0402_1%

1

C195

2

Near JUSB1

+3VL

12

C2190

22U_0603_6.3V6M

1 9

13

4 5 6 7 8

1

2

C2192

22U_0603_6.3V6M

U12

IN STATUS# FAULT# ILIM_SEL EN CTL1 CTL2 CTL3

TPS2546RTER_QFN16_ 3X3

SA000064O00

RC510

10K_0402_5%

RC511

10K_0402_5%

1

RC512

10K_0402_5%

2

C2189

22U_0603_6.3V6M

1 2 1 2

1

2

100U_1206_6.3V6M

CHR_USB20_P2 CHR_USB20_N2

1

2

C2210

22U_0603_6.3V6M

C2211

22U_0603_6.3V6M

4

4.7U_0402_6.3V6M

3V/5VALW_PG<34,38,42,44>

1

2

C2212

RF@

10P_0402_50V8J

+VL

1

C454

2

USB20_N2 <1 2> USB20_P2 <12>

+5VALW_USBCH

1 2

R215

0_0603_5%

@

+VL

100K_0402_5%

R339

3V/5VALW_PG_R

1 2

@

0_0402_5%

2

@

C457

0.1U_0201_10V6K

1

USB3.0 With USB2.0 Fo r Charge

L59

BLM15PX331SN1D_2P

L60

BLM15PX331SN1D_2P

R130

1 2

3

+5VALW

D

S

12

2

G

Q29

13

G

2

1

2

1

2

ME2301DC-G_SOT23-3

@

C90

0.1U_0201_10V6K

C453

4.7U_0402_6.3V6M

USB3.0_Port

Q28

2N7002KW_SOT323-3

13

D

S

ESD

USB3_CRX_L_DTX_N2 U SB3_CRX_L_DTX_N2

USB3_CTX_L_DRX_N2

USB3_CTX_L_DRX_P2

Intel_PCH_USB 2.0

CHR_USB20_N2 CHR_USB20_N 2_R

CHR_USB20_P2 CHR_USB2 0_P2_R

9

10

8

9

7

6

AZ1045-04F_DFN25 10P10E-10-9

Intel_PCH_USB 3.0

USB3_CRX_DTX_N2<12>

USB3_CRX_DTX_P2<12>

C156

0.1U_0201_10V6K

USB3_CTX_C_DRX_N 2

USB3_CTX_DRX_N2<12>

USB3_CTX_DRX_P2<12>

1 2

C157

0.1U_0201_10V6K

1 2

USB3_CTX_C_DRX_P2

ESD@

2

D7

1

USB3_CRX_L_DTX_P2USB3_CRX_L_DT X_P2

2

USB3_CTX_L_DRX_N2

4

USB3_CTX_L_DRX_P2

5

3

8

EMI

L12

1

DLM0NSN900HY2D_4P

R223 0_0402_ 5%

R224 0_0402_ 5%

R225 0_0402_ 5%

R226 0_0402_ 5%

EMI@

1

443

1

D9

CHR_USB20_P2_R

2

3

USB3_CRX_L_DTX_N2

12

USB3_CRX_L_DTX_P2

12

USB3_CTX_L_DRX_N2

12

USB3_CTX_L_DRX_P2

12

ESD@

3

I/O2

2

VDD

GND

1

I/O1

L30ESDL5V0C6-4_SOT 23-6

I/O4

I/O3

6

5

+5V_CHGUSB

CHR_USB20_N2_R

4

USB3.0 CONN (for charger)

W=80mils

+5V_CHGUSB

CHR_USB20_N2_R CHR_USB20_P2_R

USB3_CRX_L_DTX_N2 USB3_CRX_L_DTX_P2

USB3_CTX_L_DRX_N2 USB3_CTX_L_DRX_P2

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

STDA_SSRX-

6

STDA_SSRX+

7

GND

8

STDA_SSTX-

9

STDA_SSTX+

SANTA_375145-1

ME@

10

GND

11

GND

12

GND

13

GND

Place TX AC coupling Cap (C156,157). Close to connector

To I/O Board

W=80mil s

1

G524B2T11U_SOT23- 5

2

2A/Active Low

U20

OUT

5

IN

GND

4

EN

OCB

SA00007BW00

EMI

L16

EMI@

1

443

DLM0NSN900HY2D_4P

W=80mil s

1

2

3

1

C2213

C178

@

100U_1206_6.3V6M

C179

2

C2205

@

RF@

10P_0402_50V8J

22U_0603_6.3V6M

USB3.0

Near JIO1

2

USB20_P1_R

3

4

3

USB20_N1_R

2

Audio Jack

USB3_CTX_DRX_N1<12> USB3_CTX_DRX_P1<12>

USB3_CRX_DTX_N1<12> USB3_CRX_DTX_P1<12>

BATT_CHG_LED#<34> BATT_LOW_LED#<34>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LID_SW#<34>

PWR_LED#<34,35>

HGNDA<33>

HPOUT_R<33>

HPOUT_L<33>

HGNDB<33>

PLUG_IN<33>

Issued Date

LID_SW#

USB3_CTX_DRX_N1 USB3_CTX_DRX_P1

USB3_CRX_DTX_N1 USB3_CRX_DTX_P1

USB20_N1_R USB20_P1_R

BATT_CHG_LED# BATT_LOW_LED# PWR_LED#

HGNDA HPOUT_R

HPOUT_L

HGNDB

PLUG_IN

+5VALW +USB3_ VCCA

USB_EN#<34>

B B

0.1U_0201_10V6K

C196

Intel_PCH_USB 2.0

USB20_N1<12>

USB20_P1<12 >

A A

Compal For Lenovo

5

I/O CONN

+USB3_VCCA

+VL

+3VALW

HGNDA

HGNDB

2018/2/5 2019 /2/5

2

SP01001AO00 ME@

ACES_51522-02601- 001

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5

AGND

4 3 2 1

JIO1

AGND

Compal Secret Data

Deciphered Date

GND GND 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Title

USB3 / IO Board

Size

Document N umber Rev

Custom

LA-G651P

Date: Sheet o f

1

37 52Friday, May 18, 2018

0.2

A

B

C

D

E

+3VALW

+VL

+3VALW to +3VS

U13

1

VOUT1

VIN1

2

VOUT1

VIN1

3

4

5

6 7

G2898KD1U TDFN 14P LOAD SWITCH

ON1

VBIAS

ON2

VIN2 VIN2

SA0000BKC00

VOUT2 VOUT2

GPAD

CT1

GND

CT2

14

+3VALW_3VS

13

1 2

12

C383 S CER CAP 1000P 50V K X7R 0402

11

10

9 8

15

SE074102K80

1 2

C386 220P_0402_50V7K

+5VALW_5VS

@

+5VALW

0.1U_0201_10V6K

0.1U_0201_10V6K C205

1

2

SUSP#<13,34,43>

C214

1

2

1 1

2

+5VALW to +5VS

2 2

J4

112

JUMP_43X79

J5

112

JUMP_43X79

+3VS

+5VS

0.1U_0201_10V6K C212

1

CC60

Close to J4

C218

Close to J5

@RF@

2

6.8P_0402_50V8C

1

CC162

@RF@

2

6.8P_0402_50V8C

2

0.1U_0201_10V6K

1

2

For +1.8VALW Discharge For +0.6VS Discharge

+1.8VALW

+5VALW

2

G

12

R2004

@

100K_0402_5%

61

D

Q143A

2N7002KDW_SOT363-6

S

1.8VALW_PWR_EN#

@

3 3

3V/5VALW_PG<34,37,42,44>

5

G

12

R2005 22_0603_5%@

34

D

Q143B

@

2N7002KDW_SOT363-6

S

100K_0402_5%

SUSP#

2

G

+5VALW

12

R230

61

D

S

@

SUSP

@

Q144A 2N7002KDW_SOT363-6

R228

470_0402_5%

5

G

+0.6VS

12

@

34

D

@

Q144B

2N7002KDW_SOT363-6

S

4 4

Security Classification

Compal For Lenovo

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/2/5 2019/2/5

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

C

Date: Sheet

Compal Electronics, Inc.

DC to DC

Document Number Re v

DC to DC

LA-G651P

E

38 52Friday, May 18, 2018

0.2

of

5

4

3

2

1

D D

C C

B B

ACES_50278-00401-001

+RTCBATT

@

G2 G1

JDCIN1

6 5 4

APDIN

4

3

2

1

PD302

1

LRB715FT1G_SOT32 3-3

PF101

7A_32VDC_0437007.W RML

3

2

21

PR106

45.3K_0603_1%

1 2

+19V_APDIN

+CHGRTC

12

PC101

1000P_0402_50V7K

EMI@

PR108

1.5K_0603_5%

1 2

+RTCBATT_R

1 2

PL102

EMI@

S SUPPRE_ 5A Z80 20M 0805

PC102

100P_0402_50V8J

EMI@

+3VLP

12

PC103

EMI@

+19V_VIN

12

PC104

100P_0402_50V8J

1000P_0402_50V7K

EMI@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Compal For Lenovo

4

2016/6/2 2017/6/2

3

Compal Secret Data

Deciphered Date

Title

PWR- DCIN / Vin Detector

Size

Document Number R ev

B

Date : Sheet o f

2

Date : Sheet o f

39 54Friday, May 18, 2018

1

2.0

5

CONN@

JBAT1

1

2

3

4

5

6

7

8

9

GND

D D

10

GND

11

GND

12

SUYIN_125022HB008M200ZL

GND

VMB2

TH

EC_SMDA

PF201

F1206HB12V024TM 12A 24V UL FAST

EC_SMCA

12

PR201

100_0402_1%12PR202

100_0402_1%

1 2

200K_0402_1%

PR203

1 2

10K_0402_5%

PR205

21

4

VMB

12

PC201 1000P_0402_50V7K

EC_SMB_CK1 <34,41>

EC_SMB_DA1 <34,41>

+3VLP

VCIN1_BATT_TEMP <34,41>

+RTCBATT_R

PL201

EMI@

S SUPPRE_ 5A Z80 20M 0805

1 2

PL202

EMI@

S SUPPRE_ 5A Z80 20M 0805

1 2

EMI@

12

BATT+

PC202

EMI@

0.01U_0402_25V7K

3

PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

2

1

+EC_VCCA

C C

VCIN0_PH1<34>

12

PR206

16.5K_0402_1%

12

PH201 100K +-1% 0402 B25/50 4250K

ECAGND

B B

A A

Security Cl assification

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/6/2 2017/6/2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR- BATTERY CONN/OTP

Size Document Number Re v

Custom

SKL

Date: Sheet o f

2

Date: Sheet o f

1

40 54Friday, May 18, 2018

2.0

0x3CH <BIT9 > PSYS cur rent gain Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 10m Ω an d Rs2 = 10mΩ BIT0 = 1 .14uA/W BIT1 = 0.285uA/W ===== ==== ===== ===== ===== ==== ===== ===== ===== ===== ==== == === Rs1 = 20mΩ and Rs2 = 10mΩ or R s1 = 20mΩ and R s2 = 20mΩ BIT0 = 2 .28uA/W BIT1 = 0 .57uA/W

Ipsys = KP SYS x ( VAD P x IAD P + VBA T x IBAT ) R_Psys = 1.2V / Ipsys KPSYS = 1.14uA/W adapter wattag e = 45W Battery wat tage = 40W h

1 1

Ipsys = 1.14 x (45+40) = 96.9u A R_Psys = 1.2V / 96.9u A = 12.3K-ohm. ===== ==== ===== ===== ===== ==== ===== === = adapter wattag e = 65W Battery wat tage = 40W h Ipsys = 1.14 x (65+40) = 11 9.7uA R_Psys = 1.2V / 96.9u A = 10K-ohm.

  

Need check the SOA for inrush

+19V_VIN

2 2

A

Protection for reverse input

Vgs = 20V Vds = 60V Id = 250mA

1 2

PR301

1M_0402_1%

3M_0402_5% EMB04N03H_EDFN5X6-8-5 PQ302

5

12

PR306 392K_0402_1%

1 2

PR302

4

ASGATE_CHG_R

13

D

2

PQ301

G

2N7002KW_SOT323-3

S

1 2 3

12

PR729 and PR732 are ACDET set t i ng base on y our proj ect to set.

12

PR310

48.7K_0402_1%

VDD_CHG

12

PR311

VCIN1_AC_IN<34>

3 3

4 4

(Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 20m Ω a nd Rs2 = 10mΩ). CC_LIM = Vc cLIM / 64 x Rs2 ===== ==== ===== ===== ===== ==== ===== ===== ===== ===== ==== ==== == === (Rs1 = 10mΩ a nd Rs2 = 10 mΩ o r Rs1 = 20m Ω and Rs2 = 20mΩ). CC_LIM = Vc cLIM / 32 x Rs2 ===== ==== ===== ===== ===== ==== ===== ===== ===== ===== ==== ==== == === AC_LIM = Vac_LIM / 32 x Rs 1

Compal For Lenovo

A

Adapter current limim ed: For U22(45W)_adp: PR337 =53. 6k For U23e(65W) and DIS_a dp: PR337 =76. 8k

100K_0402_1%

12

PR314

158K_0402_1%

VCOUT1_PROCHOT#<34>

ACIN_CHG BST_CHG_R

EC_SMB_DA1<34,40>

EC_SMB_CK1<34,40>

ADP_I<34>

PC218

1000P_0402_25V8J

12

PR326 0_0402_5%

Close to EC.

VCIN1_AC_IN

L2N7002WT1G_SC70-3

Battery cur rent limimed by CCLIm ~ 5 .7A(115K). Adapter cur rent limimed by ACL Im ~ 3.3A(53.6K). (PR779 and PQ741 are for c hange ACLIm when AC in)

PR307 4.02K_0402_1%

PC208

2200P_0402_50V7K

support Turbo boost : 22 00P no support Turbo boo st : 0.1u

PR313

PR318 0_0402_5%

PR320

PR321

PC219

@

12

1000P_0402_25V8J

Follow adapter and battery wattage in Vsys current source. Base on CPU Core VR design . The resistor is pop o n CPU VR schemati c.

VDD=5 V

@

PR332

76.8K_0402_1%

1 2

@

PQ310

13

D

2

G

S

B

Rds(on) = 15.8mohm max Vgs = 20V Vds = 30V ID = 10.5A (Ta=70C)

+19V_P1

PQ303

AON7506_DFN33-8-5

1 2 3 5

4

PR308 4.02K_0402_1%

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

VDD_CHG

12

PR329

PR328

PR337

200K_0402_1%

12

PR338 115K_0402_1%

76.8K_0402_1%

Hybrid boos t power mode Cell = 4s( 1:1)

B

CMSRC_CHG

ASGATE_CHG

AMON_ISL95520

BMON_ISL95520

ACLIM_CHG

+19V_P2

CCLIM_CHG

PROG_CHG

12

PR335

1

2

3

4

5

6

7

8

150K_0402_1%

PR304

0_0402_5%

@

ACIN

ACOK

SDA

SCL

PROCHOT#

AMON

BMON

PSYS

AGND

33

COMP_CHG

12

PC222

@

1

2

CSIP_CHG_R

12

CSIP_CHG

32

CSIP

PROG

9

560P_0402_50V7K

PR303

0.01_1206_1%

PC207

1 2

0.1U_0402_25V6

0.22U_0402_16V7K PC209

CSIN_CHG

30

31

CSIN

ASGATE

CCLIM11COMP

10

12

PR333

100_0402_1%

12

PC223

0.022U_0402_25V7K

max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W CSR rating: 1W VCSIP-VCSIN spec < 81mV

4

3

CSIN_CHG_R

12

Co-lay jump and ISN choke.

PR305

2_0402_5%

12

BGATE_CHG

OPCP_CHG

OPCN_CHG

VBAT_CHG

28

25

26

27

29

VBAT

QPCP

OPCN

CMSRC

FSET12BATGONE13CSON14CSOP

15

16

12

PR325

FSET_CHG

10K_0402_1%

Fs=729KHZ ~ +/- 15%

12

PR334

0_0402_5%

@

BATGO NE(B ATT_T EMP ) logic high: above 2.4 V logic low: under 0.8V

PC224 10P_0402_25V8J

1 2

C

EMI@

12

@EMI@

12

PC204

PC203

10U_0603_25V6M

PR309

100_0402_1%

1 2

PU301 S IC ISL88739AHRZ-T QFN 32P CHARGER

@

PR312 0_0603_5%

BST_CHG

BGATE

24

BOOT

UGATE

PHASE

LGATE

VDDP

VDD

DCIN

NTC

ACLIM

CSOP_CHG

CSON_CHG

Security Classification

1 2

UG_CHG

23

LX_CHG

22

LG_CHG

21

VDDP_CHG

20

VDD_CHG

19

18

17

12

VCIN1_BATT_TEMP <34,40>

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR323 100K_0402_1%

PR324 10_1206_5%

PC220

1 2

1U_0603_25V6

12

1 2

VF = 0.38V

BATT+

Rds(on) = 32mohm max Vgs = 20V Vds = 30V ID = 8A (Ta=70C)

PC211

0.47U_0603_25V7K

1 2

PR3194.7_0402_5%

1 2

12

PC215

PC11221

@

1U_0402_6.3V7K

1U_0201_6.3V6M

PD102

1

LRB715FT1G_SOT323-3

1 2

PR331 2_0402_5%

12

PC221

0.1U_0402_25V6

1 2

@

PR336 0_0402_5%

2017/11/09 2018/11/09

C

PC205

10U_0603_25V6M

0.1U_0402_25V7K

PC216

1 2

1U_0402_6.3V7K

3

2

Compal Secret Data

PC206

2200P_0402_25V7K

12

PC11222

@

1U_0201_6.3V6M

+19V_VIN

CSOP_CHG_R

Rds(on) = 32mohm max Vgs = 20V Vds = 30V ID = 8A (Ta=70C)

PQ305

AON7408L_DFN8-5

3 5

241

12

5

PQ306

4

CSON_CHG_R

Deciphered Date

12

123

AON7752_DFN3X3EP8-5

A31 connect to BA Other team connect to bat t conn

PQ304 AON7506_DFN33-8-5

PR317

4.7_1206_5%

RF@

PC217

RF@

680P_0402_50V7K

BA

**Design Notes** For 45W/65W /90W system, 2S/3S/4S battery Maximum Charging current 3.5A Maximum Battery discharge power 55W #Register Setting

1. 0X3DH bit10 set 0 (default 1) to enable turbo boost funct ion

2. Disable turbo when AC only #Circuit Design

1. ACLIM and CCLIM are devider voltage control.

2. Use 7X7 choke and 3X3 H/L side MOSFET Charge current 3A Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) Power density : 0.61 (23X16) #Protect function

1. ACOVP : VCC voltage > 24V

2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(def aul t).

3. ACOC : OX3CH bit4 set1 release adapter limit function (default :Ena ble) .

4. CHGOCP : based on charge current setting

5. BATOVP : 4.6V/Cell

6. BATLOWV : No.

B+

7. TSHUT : 150C

D

Module model information

ISL9 552 0_Hy brid _Bo ost_ V2.m dd

1 2 35

4

PC210

@

1 2

0.1U_0402_25V7K

Support max charge 3.5A Power loss: 0.245W CSR rating: 1W

7X7X 3 Isat: 6.5A DCR: 28mohm

PL302

3

4

4.7UH_5.5A _20%_7X7X3_M

+17.4V_BATT_CHG

2

1

VCSPP-VCSON spec < 81mV

PR315

0.01_1206_1%

1

4

3

2

12

2

PQ311

12

PC213

PC225

PC214

@

10U_0805_25V6K

PQ307

2

13

41 54Friday, May 18, 2018

PC212

10U_0805_25V6K

LMUN5113T1G_SOT323-3

PM_SLP_S4#<10,34>

LTC015EUBFS8TL_UMT3F

Turn off Charger IC on battery only. Depend on customer design for system power consumption.

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : She et

Date : She et of

Compal Electronics, Inc.

PWR_CHARGER

LA-F971P

D

BATT+

12

PC226

@

10U_0805_25V6K

PR3360

1 2

@

1 3

BA

2.0

of

0_0402_5%

A

B

C

D

E

Module model information

SY82 86B_V1. mdd

keep short pad, snubber is for EMI only.

1 1

B+

EMI@

PL902

1 2

S SUPPRE_ 5A Z80 20M 0805

12

PC401

PC11147

10P_0402_25V8J

EMI@

0.1U_0402_25V6

@RF@

12

PC403

PC404

2200P_0402_50V7K

EMI@

10U_0603_25V6M

+3VLP

Check pull up resistor of SPOK at HW side

100K_0402_5%

3V/5VALW_PG<34,37,38,44>

EN1 and EN2 dont't be floating.

2 2

EN :H>0.8V ; L<0.4V

12

PR401

ENLDO_3V5V

LX_3V

6

7

8

9

10

5V_3V_EN

PU401 SY8286BRAC_QFN20_3X3

5

LX

GND

PG

NC

IN3IN4IN

EN112EN2

FF13OUT14NC

11

Fsw : 600K Hz

BST_3V

2

1

IN

BS

LX

GND

LDO

NC

GND

15

PC411 1000P_0402_25V8J

1 2

PR402

@

0_0402_5%

1 2

20

19

18

3.3V LDO 150mA~300mA

17

12

16

21

PC409

4.7U_0402_6.3V6M

PR404

1K_0402_1%

3V_FB_13V_FB

1 2

BST_3V_R+19VB_3V

+3VLP

PC402

0.1U_0402_25V7K

1 2

LX_3V

Use 7x7x3 size when the layout space is enough.

PL401

1.5UH_6A_20%_5X5X3_M

1

2

12

PR403

4.7_1206_5%

RF@

3V_SN

12

RF@

PC410

680P_0603_50V7K

4

3

12

PC406

PC405

22U_0603_6.3V6M

Vout is 3.234V~3.366V

+3VALWP

12

PC407

22U_0603_6.3V6M

12

PC408

PC11154

@

22U_0603_6.3V6M

10P_0402_25V8J

22U_0603_6.3V6M

@RF@

Module model information

SY828 6C_V2_s ing le.mdd SY8286C_ V2_ dual.md d

2 Cell battery : Cin=10uF*2pcs

B+

PL903

EMI@

1 2

S SUPPRE_ 5A Z80 20M 0805

PR406 499K_0402_1%

B+

3 3

1 2

VCOUT0_MAIN_PWR_ON<34>

4 4

PR408

150K_0402_1%

EC_ON<34>

ENLDO_3V5V

12

PC11155 1U_0201_6.3V6M

2.2K_0402_5%

1 2

PR411

0_0402_5%

PR410

PC11146

@RF@

12

10P_0402_25V8J

PR413

1M_0402_1%

+19VB_5V

12

PC413

10U_0603_25V6M

5V_3V_EN

12

PC427

3 Cell ~ 4 Cell battery : Cin=10uF*1pcs

+19VB_5V BST_5V

PC415

2200P_0402_50V7K

EMI@

12

PC416

0.1U_0402_25V6

EMI@

3V/5VALW_PG

12

ENLDO_3V5V

12

PC414

10U_0603_25V6M

EN1 and EN2 dont't be floating. EN :H>0.8V ; L<0.4V

4.7U_0402_6.3V6M

PU402 SY8288CRAC_QFN20_3X3

LX_5V

6

LX

7

GND

8

GND

9

PG

10

NC

5V_3V_EN

5

11

EN112EN2

IN3IN4IN

FF13OUT14LDO

2

1

IN

15

1000P_0402_25V8J

BS

GND

VCC

GND

PC426

1 2

LX

NC

keep short pad, snubber is for EMI only.

@

PR405

0_0402_5%

1 2

20

LX_5V

19

18

VCC_5V

17

16

21

12

1 2

+5VLP

5V LDO 150mA~300mA

PC424

4.7U_0402_6.3V6M

PR412

1K_0402_1%

5V_FB_15V_FB

1 2

BST_5V_R

PC417

4.7U_0402_6.3V6M

PC412

0.1U_0402_25V7K

1 2

PL402

1

2

12

PR407

RF@

4.7_1206_5%

5V_SN

12

PC425

RF@

680P_0603_50V7K

4

3

3.3UH_6.3A_20%_7X7X3_M

12

PC418

PC422

22U_0603_6.3V6M

PC423

22U_0603_6.3V6M

12

PC419

22U_0603_6.3V6M

Vout is 4.998V~5.202V

TDC=6A

Iocp=10 A

PC420

22U_0603_6.3V6M

PJP402

@

2

112

JUMP_43X118

PJP403

@

JUMP_43X39

112

2

+3VALW+3VALWP

+3VL+3VLP

+5VALWP

12

PC421

22U_0603_6.3V6M

PJP405

@

2

112

JUMP_43X118

PJP406

@

JUMP_43X39

112

2

+5VALW+5VALWP

+VL+5VLP

Security Cl assification

Issued Date

Compal For Lenovo

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/6/2 2017/6/2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR- 3VALW/5VALW-SY8286B&C

Size Document Number Re v

Custom

Date: Sheet o f

D

Date: Sheet o f

42 54Friday, May 18, 2018

E

2.0

A

B

C

D

E

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0.675V sequence question,

B+

1 2

1 1

PC11148

RF@

10P_0402_25V8J

+1.2VP

12

PC511

PC510

PC509

22U_0603_6.3V6M

2 2

Mode Level +0.675VSP VTTREF_1.35V S5 L off off S3 L off on S0 H on on

Note: S3 - sleep ; S5 - power off

+19VB_DDR

12

PC501

0.1U_0402_25V6

@EMI@

12

PC513

PC514

PC512

22U_0603_6.3V6M

12

PC502

EMI@

12

22U_0603_6.3V6M

MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

L/S Rds(on): 19mohm(Typ), 23.5mohm(Max) Idsm: 11A@Ta=25C, 8.8A@Ta=70C

Choke: 7x7x3 Rdc=6.7mohm(Typ), 7.4mohm(Max)

Switching Frequency:540kHz Ipeak=8A Iocp~9.6A OVP: 113%~120% VFB=0.75V, Vout=1.203V

PC503

10U_0603_25V6M

2200P_0402_50V7K

4

3

1UH_6.6A_20%_5X5X3_M

PL502

PC504

10U_0603_25V6M

1

2

RF@

4.7_1206_5%

RF@

680P_0402_50V7K

PC515

LX_DDR

PR503

12

SNB_1.2VP

12

10

4

D1

S25G2

3

D2/S1

S26S2

7

PQ501

1

AONH36334_DFN3X3A8-10

D12D1

G1

9

8

12

PC505

0.1U_0402_25V7K

+5VALW

PR504

5.1_0603_5%

1 2

1U_0402_10V6K

PC517

BST_DDR_R

12

DDR_VTT_PG_CTRL<7>

PR502

8.06K_0402_1%

1 2

+5VALW

PR501

2.2_0603_5%

1 2

1U_0402_10V6K

1 2

VDD_DDR

PR505

1 2

5.1_0603_5%

SYSON<13,34,44>

SUSP#<13,34 ,38>

LG_DDR

CS_DDR

PC508

+19VB_DDR

PL501

EMI@

S SUPPRE_ 5A Z80 20M 0805

you can change from +1.35VP to +1.35VS.

BST_DDR

UG_DDR

LX_DDR

16

18

17

19

BOOT

PHASE

UGATE

RT8207PGQW_WQFN20_3X3

S5

PGOOD

TON

8

7

9

10

EN_DDR

TON_DDR

EN_0.6VSP

12

PC518

@

PR511

PR518

12

0_0402_5%

VLDOIN

S3

0.1U_0402_10V7K

VDDP_DDR

PR508 470K_0402_1%

1 2

PR510 0_0402_ 5%

15

14

13

12

11

1 2

PU501

LGATE

PGND

CS

VDDP

VDD

0.1U_0402_10V7K

@

0_0402_1%

1 2

+1.2VP

12

PR507

1 2

6.04K_0402_1%

+1.2VP

@

JUMP_43X118

PJ503

12

PC506

PJ501

112

@

112

JUMP_43X39

10U_0402_6.3V6M

2

PC507

10U_0402_6.3V6M

12

PC516

0.033U_0402_16V7K

+1.2VP

20

21

VTT

PAD

1

VTTGND

2

VTTSNS

3

GND

VTTREF_DDR

4

VTTREF

5

VDDQ

FB

6

FB_DDR

12

PR509 10K_0402_1%

+1.2VP +1.2V

PC519

@

+0.6VSP +0.6VS

+0.6VSP

12

PC11212

@

10U_0402_6.3V6M

0.675Volt +/- 5% TDC 0.7A Peak Current 1A

3 3

4 4

Security Classification

Issued Date

Compal For Lenovo

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/6/2 2017/6/2

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

+1.2VP/+0.6VSP/+2.5VP

Size Document Number Rev

Custom

SKL

Date: Sheet of

43 54Friday, May 18, 2018

E

2.0

A

+3VALW

+5VALW

B

C

D

1

@

PC602

12

PJ701

@

1

2

12

PC604

1 2

0.1U_0402_16V7K

JUMP_43X79

1 1

PR604

10U_0402_6.3V6M

12

PR601 0_0402_5%

3V/5VALW_PG<34,37,38,42>

1 2

1M_0402_5%

PR3345 100K_0402_5%

12

PC601

1U_0402_6.3V7K

PU601 G9661MF11U_SO8

4

VPP

3

VIN

2

VEN

1

POK

GND

9

+3VALW

PGOOD <45>

2 2

+3VALW

JUMP_43X79

PJ702

@

PC11206

10U_0402_6.3V6M

0_0402_5%

PR3351

SYSON<13,34,43>

3 3

1 2

1M_0402_5%

PR3353

12

PC11202

@

0.1U_0402_16V7K

+5VALW

1

2

12

PC11203

4 3 2 1

1U_0402_6.3V7K

PU904 G9661MF11U_SO8

VPP VIN VEN POK

GND

9

Ultra Low Dropout 0.23V(typical) at 3A Output Current

5

NC

6

VO

7

ADJ

8

GND

Ultra Low Dropout 0.23V(typical) at 3A Output Current

5

NC

GND

ADJ

6

VO

7 8

Rup

Rdown

12

PR603

PC603

12.4K_0402_1%

12

PR605

10K_0402_1%

12

0.01U_0402_25V7K

+1.8VALWP

PC605

22U_0603_6.3V6M

Vout=0.8V* (1+Rup/Rdown)

PC11204

22U_0603_6.3V6M

+1.8VP_MEM

Rup

Rdown

12

PR3354

PC11205

12.4K_0402_1%

12

PR3352

10K_0402_1%

12

0.01U_0402_25V7K

PJP602

@

+1.8VALWP + 1.8VALW

PJP904

@

2

112

JUMP_43X39

112

JUMP_43X39

2

+1.8V_MEM

Vout=0.8V* (1+Rup/Rdown) =0.8*(1+(12.7/10))

Vout=1.816V

4 4

Security Cl assification

Compal For Lenovo

A

B

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/6/2 2017/6/2

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Re v

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

+1.8V_PRIM

D

2.0

of

44 54Friday, May 18, 2018

5

D D

4

3

2

1

Module model information

SY828 6_V1 _sin gl e.m dd SY828 6_V1 _du al. mdd

+19VB_1.05V

PJP701

@

2

112

B+

JUMP_43X79

PR701

C C

PGOOD<44>

0_0402_5%

1M_0402_1%

PR705

12

@

0.1U_0402_25V6

PC11149

@RF@

12

10P_0402_25V8J

PC712

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at HW side, please delete PR601.

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

B B

PR3356

0_0402_5%

1.0VS_DGPU_EN<24,26>

A A

1 2

VGA@

1M_0402_5%

PR3358

PJ703

@VGA@

JUMP_43X39

VGA@

PC11211

10U_0402_6.3V6M

12

+3VALW

PC11207

VGA@

0.1U_0402_16V7K

12

PC701

EMI@

2200P_0402_50V7K

LDO_3V

1 2

1

2

12

PC703

0.1U_0402_25V6

EMI@

PR707 0_0402_5%

+5VALW

PC705

@

12

10U_0603_25V6M

+3VALW

PC11208

1U_0402_6.3V7K

G9661MF11U_SO8

4

VPP

3

VIN

2

VEN

1

POK

+19VB_1.05V

PU905VGA@

GND

9

PU701

EN_1.05V

ILMT_1.05V

12

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

PC713

1U_0402_6.3V7K

SY8286RAC_QFN20_3X3

9

PG

1

BS

LX_1.05V

6

LX

19

LX

20

LX

FB_1.05V

14

FB

LDO_3V

17

VCC

10

NC

12

NC

16

NC

21

PAD

12

Ultra Low Dro pout 0.23V(typical) at 3A Output Current

5

NC

6

VO

7

ADJ

8

GND

Rup

Rdo wn

12

PR3359

10K_0402_1%

VGA@

12

PR3357

38.3K_0402_1%

VGA@

12

PC11209

0.01U_0402_25V7K

VGA@

keep short pad, snubber is for EMI only.

PR703

@

0_0402_5%

1 2

12

PC711

PC11213

1U_0402_6.3V7K

+1.0VS

PC11210

22U_0603_6.3V6M

VGA@

PC704

0.1U_0402_25V7K

BST_1.05V_RBST_1.05V

1 2

Vout=0.6V* (1+R1/R2) =0.6*(1+(15/20))

Vout=1.05V

RF@

4.7_1206_5%

1 2

PR702

SNUB_1.05V

RF@

680P_0603_50V7K

1 2

PC702

Use 7x7x3 size when the layout space is enough.

PL701

1 2

1UH_MMD-05AHN1R0M-X2L_8A_20%

+1.0VS

FB=0.6V

@VGA@

12

R1

12

R2

PJP905

112

JUMP_43X39

PR704

15K_0402_1%

PR706 20K_0402_1%

2

12

PC706

330P_0402_50V7K

12

PC707

22U_0603_6.3V6M

+1.0VS_DGPU

+1.05VALWP

12

22U_0603_6.3V6M

+1.05VALWP

12

PC709

PC710

22U_0603_6.3V6M

PJP702

@

JUMP_43X118

2

112

+1.05VALW

PC708

Vout=0.8V* (1+Rup/Rdown) =0 .8*(1+(10/38.3))

Vout=1.008V

Compal For Lenovo

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/6/2 2017/6/2

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Document Number Re v

C

Date: Sheet

+1.0VS

Z_SKL

1

45 54Friday, May 18, 2018

2.0

of

1

2

3

4

5

Close IC

RT3602_VREF

12

A A

B B

PRZ2

6.19K_0402_1%

12

PRZ5

6.19K_0402_1%

12

PRZ17

1.37K_0402_1%

12

PRZ28

1.37K_0402_1%

VCCCORE_SENSE<15>

PRZ41 and PRZ21 are for debug only. VCCCORE_SENSE and VSSCORE_ SENSE need other resistor at HW s ide.

Vref= 0.6V

12

PRZ4

PRZ3

19.1K_0402_1%

6.19K_0402_1%

12

PRZ6

PRZ11

RT3602_SET1 RT3602_SET2

19.1K_0402_1%

6.19K_0402_1%

RT3602_SET3

VR_PSYS

12

PRZ18

PRZ19

PRZ20

@

12

10K_0402_1%

1.37K_0402_1%

9.09K_0402_1%

12

PRZ29

PRZ30

1.37K_0402_1%

9.09K_0402_1%

0.1U_0402_2 5V6

12

Close IC

+VCCCORE

PCZ7

@

PRZ41 100_0402_ 1%

1 2

PRZ47 0_0402_5%

1 2

VSSSA_SENSE< 13>

VSEN_CORE

12

0.1U_0402_2 5V6

VCCSA_SENSE<13>

RGND_MAIN

@

12

0.1U_0402_2 5V6

PCZ196

@

PCZ204

Ra Rb/Rc

U22

N/A

Stuf f

U42

C C

N/AStuf f

+VCCSA

@

RT3602_VREF

PCZ8

@

PRZ40

@

0.1U_0402_1 0V6K

10K_0402_ 1%

1 2

PRZ43 10K_0402_ 1%

1 2

150P_0402 _50V8J

PCZ11

TSEN_CORE_R TSEN_GT_R

PRZ1

@

100_0402_ 1%

1 2

PRZ15

1 2

0_0402_5%

PRZ94

Close IC

0_0402_5%

1 2

PRZ22

1 2

100_0402_ 1%

Close CORE1 choke

PRZ107

1 2

43.2K_0402 _1%

PRZ45

31.6K_0402 _1%

1 2

PCZ12 82 P_0402_50 V8J

1 2

ISENSE1N_CORE<47>

ISENSE2N_CORE<47>

+5VALW

RT3602_VREF

12

PRZ64

PRZ63

8.06K_0402_1%

6.49K_0402_1%

12

PRZ68

PRZ67

8.06K_0402_1%

6.49K_0402_1%

12

PRZ71

PRZ70

8.66K_0402_1%

11.8K_0402_1%

12

PRZ74

PRZ73

8.66K_0402_1%

11.8K_0402_1%

VCCSA_SENSE_R

12

PCZ200

@

0.1U_0402_2 5V6

12

0.1U_0402_2 5V6

100K_0402 _1%_B25/5 0 4250K

PHZ1_R1

Rb

1 2

PRZ105 10K_04 02_1%U22@

PRZ68

U22@

1K_0402_1 %

PRZ71

U22@

71.5K_0402 _1%

@

PHZ1

PRZ1 and PRZ22 are for debug only. VCCSSA_SENSE and VSSSA_SEN SE need other resistor at HW side.

PRZ35

Ra

ISEN1N_MAIN

Rc

PRZ52

1.65K_0402 _1%

1 2

PRZ72

@

PRZ75

PCZ6 68P_0402_ 50V8J

FB_SAFB_SA

Close IC

PRZ95

0_0402_5%

1 2

IMON_CORE RT3602_SET1

COMP_CORE RT3602_SET2 RT3602_SET3

TSEN_CORE

12

PRZ53

2.2_0805_1%

+19VB_CPU

PRZ10 100K_0402 _1%

1 2

@

PRZ21

1 2

100_0402_ 1%

12

PCZ201

@

0.1U_0402_2 5V6

1

IMON_MAIN

2

FB_CORE

SET1

3

FB_MAIN

4

COMP_MAIN

5

SET2

6

SET3

7

ISEN1N_MAIN

8

ISEN2N_MAIN

9

ISEN2P_MAIN

10

ISEN1P_MAIN

11

RT3602_VIN

TSEN_MAIN

12

VIN

12

PCZ19

0.22U_0402_25VAK

+5VALW

PRZ65

8.2_0402_ 1%

1 2

4.7U_0402_6 .3V6M

Close GT MOSFET

RGND_MAIN

PCZ23

ISENSE1N_SA<47>

VSEN_CORE

VR_PSYS

46

47

48

49

GND

VSEN_MAIN

RGND_MAIN

13

16

RT3602_VCC

12

PRZ8 10K_0402_ 1%

1 2

PCZ5 390P_0402 _50V7K

PCZ1

@

PRZ16

@

0.1U_0402_1 0V6K

VSSCORE_SENSE<15>

IMON_CORE<47>

1 2

PRZ26 0_0402_5%

1 2

IMON_CORE_R

PRZ51 110K_0402 _1%

1 2

10K_0402_ 1%

1 2

732_0402_ 1%

PCZ9

@

0.1U_0402_1 0V6K

1 2

PRZ106

U42@

1 2

0_0402_5%

1 2

PRZ104 10K_04 02_1%U22@

PHZ2

100K_0402 _1%_B25/5 0 4250K

12

PCZ203

@

0.1U_0402_2 5V6

PCZ199

PHZ1_R

1 2

PRZ33 24K_0402_ 1%

PCZ13

0.1U_0402_5 0V7K

1 2

U42@

PCZ16 0.1U_0402 _50V7K

ISENSE2P_CORE_R1<47>

+5VALW

ISENSE1P_CORE_R1<47>

TSEN_CORE_R

Close CORE1 MOSFET

+5VALW

12

10K_0402_ 5%

DRVEN_SET

12

10K_0402_ 5%

Set DRVEN output function at PS4. Set to 5V DRVEN is floating, and set to GND DRVEN is low at PS4.

FB_SA

PSYS

PWM_CORE2

RGND_SA

45

FB_SA

PWM1_MAIN17PWM2_MAIN

DRVEN_SET

PWM_CORE1

COMP_SA

43

44

RGND_SA

PHZ3

100K_0402_1%_B25/50 4250K

12

PCZ193

12

PRZ24

3.9_0402_1%

RT3602_VREF

40

41

42

39

ISENP_SA

ISENN_SA

COMP_SA

VREF06/PSET

NC21NC20NC19DRVEN_SET18NC15NC14VCC

PWM_AUXI22TSEN_AUXI

23

TSEN_GT

PWM_GT

12

TSEN_GT_R

PCZ3

0.1U_0402_5 0V7K

ISENSE1P_SA_R1 <47>

PCZ4

@

0.47U_0402_ 25V6K

1 2

PRZ13

28K_0402_ 1%

0.47U_0402_25V6K

PRZ23 100K_0402 _1%

1 2

IMON_SA

@

0.1U_0402_2 5V6

1 2

RT3602_EN

PUZ1

37

38

RT3602AJGQW_W QFN48_6X6

EN

IMON_SA

PWM_SA

VR_READY

DRVEN

VCLK

ALERT

VDIO

VR_HOT

IMON_AUXI ISENP_AUXI ISENN_AUXI

VSEN_AUXI COMP_AUXI RGND_AUXI

FB_AUXI

24

FB_GT

<47>

PRZ66 110K_0402 _1%

PRZ69

1.65K_0402 _1%

PRZ25 0_0402_5%

PCZ206

36 35 34 33 32 31 30 29 28 27 26 25

PRZ98 49.9_04 02_1%

VSEN_GT

1 2

PRZ14

0_0402_5%

+3VS

VR_PWRGD <34>

1 2

PRZ99 10_04 02_1%

IMON_GT

COMP_GT

RGND_AUXI

Module model information

RT3602AE_U22_RU42_colay_V1A.md d for IC porti on

RT3602AE_U22_RU42_colay_V1B.md d for SW porti on

RT3602_VREF

EN High: > 0.7V Low: < 0.3V

VR_ON <34>

+1.05V_VCCST

12

100_0402_1%

PRZ38

1 2

PCZ20 82P_040 2_50V8J

PRZ39

75_0402_1%

PCZ194

0.1U_0402_25V6

1 2

PRZ54

37.4K_0402 _1%

1 2

VR_SVID_CLK <15> VR_ALERT# <15> VR_SVID_DATA <15>

PRZ48

23.7K_0402 _1%

VR_HOT# <34>

FB_GT

RT3602_VREF

PRZ49 0_0402 _5%

1 2

ISENSE1P_GT_R1 <4 7> ISENSE1N_GT <47>

PRZ56 10K_0402_ 1%

1 2

PCZ21

270P_0402 _50V7K

1 2

PRZ61

@

10K_0402_ 1%

PRZ59 and PRZ60 are for debug only. VCCGT_SENSE and VSSGT_SENSE need othe r resistor at HW s ide.

PRZ37

110_0402_1%

@

PRZ36

45.3_0402_1%

PWM_SA <47> DRVEN_CPU <47>

1 2

PRZ100 100_04 02_1%

1 2

PCZ18

0.1U_0402_2 5V6

PCZ15 0.47U_0 402_25V6K@

PCZ22

@

0.1U_0402_1 0V6K

0.1U_0402_2 5V6

VSEN_GT

12

@

0.1U_0402_2 5V6

PCZ197

@

PRZ50 0_0402_5%

1 2

@

100_0402_ 1%

1 2

@

0.1U_0402_2 5V6

PCZ202

12

Close IC

PRZ59

PCZ198

+VCC_GT

12

Close IC

PRZ93

1 2

0_0402_5%

PRZ60

@

100_0402_ 1%

VCCGT_SENSE <15 >

VSSGT_SENSE <15>

D D

Security Classification Compal Secret Data

Security Classification

Issued Date

Compal For Lenovo

1

2

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2019/09/012016/09/01

Title

CPU_CORE

Size Do cument Number Rev

Date: Sheet of

Friday, May 1 8, 2018

Date: Sheet of

Friday, May 1 8, 2018

Date: Sheet of

Friday, May 1 8, 2018

5

0.2

5446

5

4

3

2

1

PUZ2

15 16 17 18 19 20 21

12

PCZ214 1U_0402_10V6K

+5VALW

22 23 24 25 26 27 28

D D

+5VALW

PRZ108

1 2

5.1_0402_1%

12

PCZ207 1U_0402_10V6K

C C

+5VALW

PRZ112

1 2

5.1_0402_1%

B B

VSWH

VSWH VSWH

VSWH

PGND

VSWH VSWH VSWH

VSWH

GL PGND

BOOT

PVCC NC

VCC

NC

FCCM

GL

PWM

AGND

AOZ5038QI_QFN31_5X5

PWM_CORE1<46>

1 2

PRZ80

5.1_0402_1%

VIN VIN

NC

14 13 12 11 10 9 8 7 6 5 4 3 2 1

DRVEN_CPU<46>

12

PCZ40 1U_0402_10V6K

PUZ4

15

VSWH

16

VSWH

17

VSWH

18

VSWH

19

VSWH

20

VSWH

21

VSWH

22

GL

23

PGND

24

PVCC

25

NC

26

NC

27

GL

28

AGND

AOZ5038QI_QFN31_5X5

+5VALW

<46>

VSWH VSWH VSWH VSWH PGND

VSWH

BOOT

FCCM

PWM

1 2

PRG1

5.1_0402_1%

VIN VIN

VCC

PRZ76

NC

PCZ28

0.1U_0402_25V6

1 2

IMON_CORE

14 13 12 11 10 9 8 7 6 5 4 3 2 1

PWM_GT<46>

VCC_GT

12

2.2_0603_5%

PRZ113

1M_0402_1%

PCZ218

47P_0402_50V8J

DRVEN_CPU

PCG1 1U_0402_10V6K

12

PCZ30

PCZ29

EMI@

0.1U_0402_25V6

@EMI@

ISENSE1P_CORE

12

PRZ82

Can be closed to choke

4.7_1206_5%

@EMI@

1 2

PRZ85 619_0603_1%

CORE1_SNUB

12

PCZ44

@EMI@

680P_0603_50V7K

PCG2

0.1U_0402_25V6

PRG2

1 2

2.2_0603_5%

12

2200P_0402_50V7K

Rdc=0. 9moh m

12

PCZ31

PCZ32

10U_0603_25V6M

PLZ1

134

2

0.15UH_NA__35A_20%

ISENSE1P_CORE_R

GT_LX

12

1 2

PRZ102 619_0603_1%

12

PCG3

PCG4

EMI@

0.1U_0402_25V6

@EMI@

12

PRG4

4.7_1206_5%

@EMI@

GT_SNUB

Can be closed to choke

12

PCG9

@EMI@

680P_0603_50V7K

+19VB_CPU

1

+

2

+VCCCORE

0.1U_0402_25V6

PCZ215

33U_D1_25VM_R6M

PCZ42

1 2

PRZ88

536_0402_1%

1 2

1

+

2

PCZ216

33U_D1_25VM_R6M

@

PJZ1

112

JUMP_43X118

1

+

PCZ217

2

33U_D1_25VM_R6M

1

+

2

ISENSE1N_CORE <46>

ISENSE1P_CORE_R1 <46>

+19VB_CPU

PCG5

PCG6

12

10U_0603_25V6M

2200P_0402_50V7K

Rdc=0.9 mohm

PLG1

ISENSE1P_GT_R

134

2

0.15UH_NA__35A_20%

PRG9

604_0402_1%

1 2

ISENSE1P_GT ISENSE1N_GT

PRG6

604_0402_1%

1 2

B+

2

+5VALW

1

+

PCZ213

PCZ211

2

330U_B2_2.5VM_R9M

+VCC_GT

PCG8

0.1U_0402_25V6

1 2

PRG7

330_0402_1%

255_0402_1%

1 2

AVGT1_R

PHG1

1K_0402_5%_TSM0B102J3652RE

PRZ111

1 2

5.1_0402_1%

12

PCZ210 1U_0402_10V6K

330U_D1_2VY_R9M

VCC_C ORE FSW=4 50kH z Choke= 0.15 uH DCR=0.9mohm +/- 5%

U22 LL=2.4 mohm TDC=2 1A ICCMA X=32 A OCP=4 0A

U42 LL=2.4 mohm TDC=4 2A ICCMA X=64 A

1

OCP=7 0A

+

PCZ212

2

PRG8

330U_D1_2VY_R9M

Close GT choke

ISENSE1N_GT <46>

ISENSE1P_GT_R1 <46>

PUZ3

15 16 17 18 19 20 21 22 23 24 25 26 27 28

AOZ5038QI_QFN31_5X5

+5VALW

VSWH VSWH VSWH VSWH VSWH VSWH VSWH GL PGND PVCC NC NC GL AGND

PRZ110

1 2

5.1_0402_1%

VSWH VSWH VSWH VSWH PGND

VSWH

BOOT

FCCM

14 13 12 11 10 9

VIN

8

VIN

7 6

NC

5 4

NC

3

VCC

2 1

PWM

PWM_CORE2<46>

12

PCZ209 1U_0402_10V6K

PCZ208

0.1U_0402_25V6

1 2

12

PRZ109

DRVEN_CPU

2.2_0603_5%

PRZ114

1M_0402_1%

1 2

PCZ219

47P_0402_50V8J

IMON_CORE

VCC_G T FSW=4 50kH z Choke= 0.15 uH DCR=0.9 mohm +/- 5%

U22 LL=3.1 mohm TDC=1 8A ICCMA X=31 A OCP=3 9A

U42 LL=3.1 mohm TDC=1 2A ICCMA X=31 A OCP=3 9A

12

PRZ84

4.7_1206_5%

@EMI@

619_0603_1%

1 2

CORE2_SNUB

12

PCZ45

Can be closed to choke

@EMI@

680P_0603_50V7K

VCC_S A FSW=6 00kH z DCR=6.2 mohm +/- 5%

U22 LL=10.3 mohm TDC=4 A ICCMAX =4.5 A OCP=9 .5A

U42 LL=10.3 mohm TDC= ICCMA X=6A OCP=9 .5A

12

PCZ36

0.1U_0402_25V6

@EMIU42@

ISENSE2P_CORE

PRZ87

ISENSE2P_CORE_R

PCZ37

12

PCZ33

EMIU42@

2200P_0402_50V7K

PCZ34

12

10U_0603_25V6M

Rdc=0.9 mohm

PLZ2

134

2

0.15UH_NA__35A_20%

PRZ103

U42@

619_0603_1%

0.1U_0402_25V6

1 2

+19VB_CPU

PCZ43

1 2

PRZ90

536_0402_1%

1 2

+VCCCORE

ISENSE2N_CORE <46>

ISENSE2P_CORE_R1 <46>

PRA2

SA_BST

PWM_SA<46>

DRVEN_CPU

+5VALW

VCC_SA

1 2

PRA1 5.1_0402_1%

12

PCA1 1U_0402_10V6K

A A

2.2_0603_5%

1 2

PUA1

4

BOOT

UGATE

5

PWM

PHASE

1

EN

PGND

8

VCC

LGATE

GND

RT9610CGQW_WDFN8_2X2

SA_BST_R

12

PCA3

SA_UG

3

SA_LX

2

6

7 9

0.1U_0402_25V6

SA_LG

1

3

D12D1

G1

9

D2/S1

S26S2

7

8

4

D1

S25G2

PQA1 AONH36334_DFN3X3A8-10

10

12

PCA4

PCA5

10U_0603_25V6M

12

PRA4

4.7_1206_5%

@EMI@

SA_SNUB

12

PCA8

@EMI@

680P_0402_50V7K

Compal For Lenovo

5

4

+19VB_CPU

12

PCA2

PCA6

@EMI@

EMI@

0.1U_0402_25V6

2200P_0402_50V7K

ISENSE1P_SA

Can be closed to choke

ISENSE1P_SA_R

1 2

PRA6 422_0603_1%

Rdc=6.2 mohm

PLA1

134

2

0.47UH_MHCI05012B-R47M-R8A_7A_20%

1 2

PRA9 422_0603_1%

3

+VCCSA

PCA7

0.1U_0402_25V6

1 2

PRA7

PRA8

280_0402_1%

300_0402_1%

1 2

AVCCSA_R

PHA1

1K_0402_5%_TSM0B102J3652RE

3650K

Close SA choke

ISENSE1N_SA <46>

ISENSE1P_SA_R1 <46>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2019/09/012016/09/01

Title

CPU Power stage

Size

Document N umber Re v

Date: Sheet of

Friday, May 18, 2018

Date: Sheet of

Friday, May 18, 2018

Date: Sheet of

Friday, May 18, 2018

1

0.2

5447

5

VCC_CORE Place on CPU Back Side @ V0 9 22U_0603 * 12 pcs+10U_0402* 26 pcs +1U_0201*35 pcs

4

3

2

VCC_GT Place on CPU Back Side. 22U_0603 * 20pcs10U_0402*38 pcs +1U_0201*8pcs+ 0.47U_0201*4 pcs

1

+VCCCORE

1

D D

1

PC2001

2

22U_0603_6.3V6M

1

PC2002

PC2003

2

22U_0603_6.3V6M

12

PC2007

2

22U_0603_6.3V6M

12

PC2010

PC2008

10U_0402_6.3V6M

1

12

PC2011

10U_0402_6.3V6M

12

PC2012

PC1367

2

10U_0402_6.3V6M

22U_0603_6.3V6M

12

PC1369

PC1368

PC1370

PC11156

10U_0402_6.3V6M

12

PC11158

PC11157

10U_0402_6.3V6M

12

PC11159

10U_0402_6.3V6M

12

PC11161

PC11160

PC11162

10U_0402_6.3V6M

12

PC11227

PC11226

10U_0402_6.3V6M

12

PC11223

PC11224

PC11225

10U_0402_6.3V6M

+VCC_GT

12

PC2042

PC1323

10U_0402_6.3V6M

12

PC2043

PC2044

10U_0402_6.3V6M

12

PC2045

PC2046

10U_0402_6.3V6M

12

PC2048

PC2047

10U_0402_6.3V6M

12

PC2049

PC2050

10U_0402_6.3V6M

12

PC2051

PC2052

PC2053

10U_0402_6.3V6M

+VCCCORE

12

PC2021

1U_0201_6.3V6M

12

C C

PC2031

1U_0201_6.3V6M

12

PC2076

1U_0201_6.3V6M

12

PC2022

PC2023

1U_0201_6.3V6M

12

PC2033

PC2032

1U_0201_6.3V6M

12

PC2078

PC2077

1U_0201_6.3V6M

12

PC2025

PC2024

1U_0201_6.3V6M

12

PC2034

PC2035

1U_0201_6.3V6M

12

PC2080

PC2079

1U_0201_6.3V6M

12

PC2026

PC2027

1U_0201_6.3V6M

12

PC2036

PC2037

1U_0201_6.3V6M

12

PC2081

PC2082

1U_0201_6.3V6M

12

PC2028

PC2038

PC2083

PC2030

PC2029

1U_0201_6.3V6M

12

PC2040

PC2039

1U_0201_6.3V6M

12

PC2085

PC2084

1U_0201_6.3V6M

12

PC11167

PC11168

10U_0402_6.3V6M

1

2

12

PC11166

PC11165

10U_0402_6.3V6M

1

PC1352

1

2

PC1360

PC1359

2

22U_0603_6.3V6M

PC1361

VCC_SA Place on CPU Back Side. 22U_0603 * 6 pcs+10U_0402*10 pcs+ 1U_0201 * 7 pcs

22U_0603_6.3V6M

12

PC1362

10U_0402_6.3V6M

22U_0603_6.3V6M

12

PC1365

PC1364

PC1363

10U_0402_6.3V6M

PC1366

2

10U_0402_6.3V6M

22U_0603_6.3V6M

1

12

PC2004

PC2005

22U_0603_6.3V6M

10U_0402_6.3V6M

12

PC2006

2

22U_0603_6.3V6M

12

PC2009

PC11163

PC11164

10U_0402_6.3V6M

+VCC_GT

12

PC11178

10U_0402_6.3V6M

12

PC2061

1U_0201_6.3V6M

+VCCSA

12

PC11150

10P_0402_25V8J

B B

@RF@

12

PC2086

PC2087

1U_0201_6.3V6M

12

PC2088

1U_0201_6.3V6M

PC2090

PC2089

1U_0201_6.3V6M

12

PC11171

PC11170

PC11169

@

10U_0402_6.3V6M

1

12

PC2103

10U_0402_6.3V6M

12

PC2104

PC1397

PC1398

2

10U_0402_6.3V6M

22U_0603_6.3V6M

12

10U_0402_6.3V6M

12

PC2112

PC2111

1U_0201_6.3V6M

12

PC2114

PC2113

1U_0201_6.3V6M

12

PC2115

PC2117

PC2116

1U_0201_6.3V6M

12

PC11180

PC11179

10U_0402_6.3V6M

12

PC2063

PC2062

1U_0201_6.3V6M

1

PC1321

PC1302

2

22U_0603_6.3V6M

12

PC11182

PC11181

@

10U_0402_6.3V6M

12

PC2065

PC2064

1U_0201_6.3V6M

1

12

PC1303

PC1322

2

22U_0603_6.3V6M

10U_0402_6.3V6M

12

PC11183

10U_0402_6.3V6M

12

PC2066

1U_0201_6.3V6M

1

PC1305

2

22U_0603_6.3V6M

12

PC11185

PC11184

10U_0402_6.3V6M

12

PC2067

PC2068

1U_0201_6.3V6M

1

PC1307

PC1306

2

22U_0603_6.3V6M

12

PC11186

PC11187

10U_0402_6.3V6M

12

PC2070

PC2069

1U_0201_6.3V6M

1

PC1309

PC1308

2

22U_0603_6.3V6M

12

PC11189

PC11188

PC11190

10U_0402_6.3V6M

12

PC2072

PC2071

1

2

PC2073

1U_0201_6.3V6M

PC1310

1U_0201_6.3V6M

12

PC11177

22U_0603_6.3V6M

10U_0402_6.3V6M

1

+VCCSA

1

12

PC11152

2

10P_0402_25V8J

RF@

A A

1

PC1391

PC1392

PC1394

2

22U_0603_6.3V6M

Compal For Lenovo

5

4

1

PC1396

2

12

PC1393

PC2105

2

22U_0603_6.3V6M

3

10U_0402_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC2106

PC11173

PC11172

10U_0402_6.3V6M

Compal Secret Data

Deciphered Date

2016/6/2 2017/6/2

Deciphered Date

2

1

PC1311

2

22U_0603_6.3V6M

1

12

PC11151

PC1301

2

10P_0402_25V8J

@RF@

22U_0603_6.3V6M

1

12

PC1312

1

2

PC1314

PC1313

2

22U_0603_6.3V6M

PC1304

22U_0603_6.3V6M

12

PC2041

22U_0603_6.3V6M

10U_0402_6.3V6M

C

Date: Sheet of

1

PC1315

PC1316

2

10U_0402_6.3V6M

22U_0603_6.3V6M

12

PC1324

PC11174

@

10U_0402_6.3V6M

Compal Electronics, Inc.

Title

PWR-PROCESSOR_DECOUPLING

Size

Document Number R ev

1

PC1317

2

22U_0603_6.3V6M

12

PC11175

@

10U_0402_6.3V6M

1

12

PC1319

PC1318

10U_0402_6.3V6M

PC1320

2

PC11176

22U_0603_6.3V6M

10U_0402_6.3V6M

2.0

48 54Friday, May 18, 2018

1

48 54Friday, May 18, 2018

2.0

5

4

3

2

1

Module model information

R1, R2, R3, R4, R5, C are

D D

C C

B B

A A

based on VGA type to set.

Vboot=Vvref*Rref2/(Rref1+Rref2+Rb oot)

Rt=Rrefadj // (Rboot+Rref2)

Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)]

Vmax=Vvref*Rref2/[(Rref1//Rrefadj) +Rboot +Rref2 ]

Vout=Vmin+N*Vstep

Vstep=(Vmax-Vmin)/Nma x

PSI<24>

12

VGA@

PR7

20.5K_0402_1%

R2

VGA@

R3

PR10

4.32K_0402_1%

12

R4

VGA@

12

R5

VGA@

12

PC10

0.1U_0402_25V6

VGA_B+

RGND_NVVDDS

Remark:

1. Swit ching frequency setting:(Ton pin) Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p) =352Khz

1 2

1

PR20

PC19

16.5K_040 2_1%

2

@VGA@

PR21

RGND_NVVDDS

309_0402_1%

VGA@

Close Vref pin

PR26

VGA@

1 2

2.2_0805_5%

VGA@

1U_0603_25V6K

GND_SENSE_GPU<21>

0.01U_040 2_16V7K

PC28

+VGA_CORE

VDD_SENSE_GPU<21>

4.7U_0402_6.3V 4pcs

10U_0603_6.3V 13pcs

+VGA_CORE

12

PC871

PC872

VGA@

22U_0603 _6.3V6M

Near GPU Core

12

PC837

PC838

VGA@

4.7U_0402_6.3V6M

4.7U_0402 _6.3V6M

12

PC874

PC873

VGA@

22U_0603 _6.3V6M

22U_0603_6.3V6M

22U_0603 _6.3V6M

Compal For Lenovo

R1

1 2

VGA@

6.19K_0402_1%

12

PC9

C

VGA@

4700P_04 02_50V7K

PR13

VGA@

1 2

432K_0402_1%

12

VGA@

1 2

For debug only, HW side need other resister

VGA@

@VGA@

12

PC839

PC840

VGA@

4.7U_0402_6.3V6M

4.7U_0402 _6.3V6M

12

PC876

PC875

VGA@

10U_0402 _6.3V6M

5

GPU_VID0<24>

PR8

Rton

PR15

1 2

0_0402_5%

PR16

10_0402_5%

PR19

10_0402_5%

1 2

PR18

0_0402_1%

12

PC883

VGA@

10U_0402 _6.3V6M

12

PC877

VGA@

1 2

0_0402_5%

REFADJ_NVVDDS

REFIN_NVVDDS

VREF_NVVDDS

TON_NVVDDS

RGND_NVVDDS

12

PC884

VGA@

10U_0402_6.3V6M

12

PC878

VGA@

10U_0402 _6.3V6M

10U_0402_6.3V6M

PR3

VGA@

1 2

0_0402_5%

PC17

1000P_04 02_50V7K

@VGA@

PC885

VGA@

10U_0402_6.3V6M

VGA@

PR4

6

REFADJ

7

REFIN

8

VREF

9

TON

10

RGND

12

PC886

VGA@

12

PC879

10U_0402 _6.3V6M

+1.8VS_DGPU_AON

12

PR41

@VGA@

10K_0402_1%

12

PR42

10K_0402_1%

@VGA@

NVVDDS_PSI_R

NVVDDS_EN

NVVDDS_VID

4

3

5

EN

PSI

VID

OCSET/SS

VSNS

11

12

PR24

36K_0402_1%

VGA@

PC887

VGA@

10U_0402 _6.3V6M

12

PC881

VGA@

10U_0402 _6.3V6M

PGOOD

12

13

OCSET_NVVDDS

1

PC18

2

0.01U_0402_16V7K

@VGA@

Css

+VGA_CORE

12

PC882

VGA@

10U_0402 _6.3V6M

GND

21

12

10U_0402 _6.3V6M

PC880

VGA@

10U_0402_6.3V6M

OpenVReg Configurations:(PSI pin)

Operation phase Number PSI Voltage setting

1 phase with DEM 0V to 0.4V

1 phase with CCM

2 phase with DEM

2 phase with CCM

PWM VID and Output voltage control

1.Boot m ode

2.Standby mode (don't support)

3.Normal mode

DH1_VGA

BST1_NVVDDS

2

1

RT8816AGQW_WQFN20_3X3

BOOT1

UGATE1

PHASE1

LGATE1

PVCC

LGATE2

PHASE2

UGATE2

BOOT2

14

15

BST2_NVVDDS

VGA@

DH2_VGA

PR17

10K_0402_5%

1 2

DGPU_PWROK <21,25>

4.7U_0402_6.3V 12pcs

1U_0402_16V 5pcs

0.7V to 0.88V

1.08V to 1.35V

1.6V to 5.5V

PR2

12

0_0402_5%

PR6 2.2_0603_5%VGA@

BST1_NVVDDS-R

1 2

PU1

LX1_VGA

20

DL1_VGA

19

PVCC_NVVDDS

18

DL2_VGA

17

LX2_VGA

16

12

PR9

BST2_NVVDDS-R

1 2

2.2_0603_5%

Current Limit threshold setting Rocset= (Ivalley * Rds(on) * 12) / Icoset

+3VS

Under GPU Core

12

PC822

VGA@

4.7U_0402 _6.3V6M

12

PC843

PC844

1U_0402_ 16V6K

VGA@

4

12

PC824

PC823

VGA@

4.7U_0402_6.3V6M

4.7U_0402 _6.3V6M

12

PC845

PC846

1U_0402_ 16V6K

VGA@

VGA_CORE_EN <24>

High: >1.2V

Low: <0.55V

12

VGA@

PC8

0.1U_0402_25V6

VGA@

PR14

1_0402_1%

1 2

12

VGA@

PC16

2.2U_0603_16V6K

VGA@

PC22

0.1U_0402_25V6

12

PC826

PC825

VGA@

4.7U_0402_6.3V6M

4.7U_0402 _6.3V6M

PC847

1U_0402_16V6K

VGA@

2

D1

S24S2

S2

3

VGA_B+

12

PC813

10U_0603_25V6M

VGA@

12

@VGA_EMI@

PR816

4.7_1206_5%

SNUB_VGA2

12

PC818 680P_0402_50V7K

12

PC814

10U_0603 _25V6M

VGA@

PL803

1

2

0.22UH_PCMB061HR22MS4R305_14A_20%

@VGA_EMI@

4

3

+5VALW

DH2_VGA

VGA@

PQ802

1

2

AON6962_DFN5X6D-8-7

D1

G1

LX2_VGA

7

D2/S1

S24S2

S2

G2

5

3

6

DL2_VGA

GB4-128 package

12

PC827

VGA@

4.7U_0402_6.3V6M

12

PC828

PC829

VGA@

4.7U_0402 _6.3V6M

Security Classifi cation

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC848

PC830

VGA@

4.7U_0402_6.3V6M

VGA@

4.7U_0402 _6.3V6M

3

12

4.7U_0402 _6.3V6M

2016/6/2

PC851

4.7U_0402 _6.3V6M

VGA@

Compal Secret Data

Deciphered Date

PC849

VGA@

1

AON6962_DFN5X6D-8-7

G1

D2/S1

G2

5

6

DL1_VGA

12

VGA@

Rocset

2

VGA_B+

DH1_VGA

VGA@

PQ801

LX1_VGA

7

PR813

9.1K_0402_1%

2017/6/2

12

PC803

PC802

10U_0603 _25V6M

VGA@

0.22UH_PCMB061HR22MS4R305_14A_20%

1

PC812

@VGA_EMI@

680P_0402_50V7K

2

12

@VGA_EMI@

PR811

4.7_1206_5%

SNUB_VGA1

12

+VGA_CORE

12

PC831

0.1U_0402_25V6

@VGA_RF@

Date : Shee t of

Date: Sheet o f

VGA_EMI@

PL801

S SUPPRE_ 5A Z80 20M 0805

12

PC804

VGA_EMI@

2200P_0402_50V7K

PL802

+VGA_CORE EDP-Continuous 26A EDP-Peak 45A OCP min 54A

original

0.1U_0402_25V 4pcs

12

PC832

0.1U_0402_25V6

@VGA_RF@

Title

Size Document Number Re v

12

B+

PC805

0.1U_0402 _25V6

@VGA_EMI@

4

3

PC833

0.1U_0402_25V6

@VGA_RF@

Compal Electronics, Inc.

NVIDIA VGA_CORE

Friday, May 18, 2018

12

PC834

@VGA_RF@

+VGA_CORE

1

+

PC810

2

VGA@

330U_B2_2.5VM_R9M

0.1U_0402_25V6

1

+

PC809

PC811

2

330U_B2_2.5VM_R9M

VGA@

1

330U_B2_2 .5VM_R9M

49 54

2.0Custom

5

D D

4

3

2

1

Module model information

SY8286_ V1_s ingle .mdd SY8286_ V1_d ual.m dd

+3VS

Confirm HW side

B+_1.35V

EN_1.35V

ILMT_1.35V

12

VGA@

PU901

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8286RAC_QFN20_3X3

PC913

1U_0402_6.3V7K

@VGA@

PJP901

12

112

JUMP_43X79

12

PC912

0.22U_0402_16V7K

2

12

PC901

PC904

2200P_0402_50V7K

VGA_EMI@

@VGA_EMI@

VGA@

LDO_3V_1.35V

12

@VGA@

PR908

0_0402_5%

12

PC903

0.1U_0402_25V6 10U_0603_25V6M

VGA@

+3VALW

B+

C C

1.35V_PWR_EN<25>

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at HW side, please delete PR601.

PD1301

VGA@

1 2

RB751V-40_SOD323-2

PR905 16.5K_0402_1%

1 2

PR906

@VGA@

1M_0402_1%

12

PR901 100K_0402_5%

9

PG

1

BS

LX_1.35V

6

LX

19

LX

20

LX

FB_1.35V

14

FB

LDO_3V_1.35V

17

VCC

10

NC

12

NC

16

NC

21

PAD

keep short pad,

VGA@

snubber is for EMI only.

+1.35VGS_PGOOD <21>

1 2

12

VGA@

PC911

4.7U_0402_6.3V6M

@VGA@

PR903

0_0402_5%

BST_1.35V_RBS T_1.35V

PC905

0.1U_0402_25V7K

@VGA_EMI@

PR902

4.7_1206_5%

SNUB_1.35V

1 2

VGA@

Use 7x7x3 size when the layout space is enough.

PL901

VGA@

1

2

1UH_MMD-05AHN1R0M-X2L_8A_20%

FB=0.6 V

Vout=0.6V* (1+R1/R2) = 0.6*(1+(12.7/10))

Vout=1.362V

@VGA_EMI@

4

3

R1

R2

PC902

680P_0603_50V7K

1 2

12

PR904

12.4K_0402_1%

12

PR907 10K_0402_1%

12

VGA@

12

PC907

PC906

VGA@

22U_0603_6.3V6M

330P_0402_50V7K

VGA@

12

PC908

VGA@

22U_0603_6.3V6M

PC910

PC909

VGA@

22U_0603_6.3V6M

PJP902

@

JUMP_43X118

2

+1.35VGSP

112

+1.35VS_VRAM

+1.35VGSP

EN pin don't floating If have pull down resistor at HW side, pls delete PR702

B B

A A

Compal For Lenovo

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2016/6/2 2017/6/2

Compal Secret Data

2

Deciphered Date

Title

PWR-CPU_CORE/CPU_CORE_NB

Size

Document Number Rev

Custom

Date : Sheet of

Compal Electronics, Inc.

ISL62771 Module

1

50 54Friday, May 18, 2018

2.0