Lenovo S530-13 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

S530 (ELZ02)

DIS M/B Schematics Document

Intel Whiskey Lake U Processor with LPDDR3

N17S-LG (Geforce MX150) (23x23mm)

3 3

2018-5-21

LA-G651P

R E V

：

：

：：

0 . 2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Compal For Lenovo

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/2/5 2019/2/5

2018/2/5 2019/2/5

2018/2/5 2019/2/5

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-G651P

LA-G651P

LA-G651P

0.2

0.2

0.2

o f

1 52Friday, May 18, 2018

1 52Friday, May 18, 2018

1 52Friday, May 18, 2018

E

5

4

3

2

1

D D

N17S-LG (MX150)

VRAM(GDDR5)*2

PCIe x4
2 Lanes

2GB

eDP Panel

FHD LCD

HDMI CONN

eDP x1
2 Lanes

DDI x1

Channel A/B

(1866 MT/s)

USB3.0

USB2.0

USB3.0

USB2.0

USB2.0

On board X 4

LPDDR3

USB3.0 Connector

(USB charger port)

USB3.0 redriver

TI
SN65 LVPE50 2A

Camera

USB3.0 Connector

IO/B

Intel WHL-U_15W

C C

Wireless LAN
WIFI /BT combo

NGFF

Type-C DP/USB3 Switch

Type-C
Conn

B B

Realtek RTS5455

Touch Pad

PCIE x1

GEN1 : 2.5G

USB2.0 x1

DDI x1

USB 3.0

USB 2.0

I2C

4+2

1528 pin BGA

USB2.0

PCIE x4

HDA

Finger print

SSD CONN

NGFF

Audio Codec

Realtek ALC3240

Int. Speaker

Int. Array Mic x2

MIC B

Combo Jack

IO/B

EC

ENE
KB9022

LPC

SPI

SPI ROM

16 MB

Sub-Board

IO/B

USB3.0 *1
Combo Jack *1

A A

Int. KBD

Hall Sensor x1

MIC B

Int. Array Mic x2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Compal For Lenovo

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2018/2/5 2019/2/5

2018/2/5 2019/2/5

2018/2/5 2019/2/5

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Date : Sheet

Date : Sheet of

Date : Sheet of

LA-G651P

LA-G651P

LA-G651P

1

2 52Friday, May 18, 2018

2 52Friday, May 18, 2018

2 52Friday, May 18, 2018

0.2

0.2

0.2

of

1

Voltage Rails

State

S0

S3

S5 S4/AC

power
plane

SIGNAL

B+

O

O

O

O

X

SLP_S1#

LOW

HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW

LOWLOW

+5VALW

+3VALW

+1.8VALW

+1.05VAL W

O

O

+1.2V
+2.5V

O O

O

O

X

SLP_S4#SLP_S3# +V+VALWSLP_S5# Clock+VS

HIGHHIGHHIGH

HIGH

HIGH

HIGH

HIGH

LOWLOW

X

ONONON

ON

ON

ON

ON

ON

OFF

OFF

A A

B B

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

C C

SMBUS Control Table

SOURCE

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SMB_CLK
PCH_SMB_DATA

I2C1_SCL_TS
I2C1_SDA_TS

I2C0_SCL_TP

D D

I2C0_SDA_TP

Address

KB9022QD

+3VL

KB9022QD

+3VS

PCH

+3VS

PCH

+3VS

PCH

+3VS

Write
Read

VGA

X

V

X
X
X

0X9E

BATT

V X

X

X
X
X

CHARGER

V

X
X
X
X

2

+5VS

+3VS

+VCCPLL_ OC

+VCCCORE

+VCCGT

+1.05V_V CCST

+1.05VS_V CCIO

+1.8VS

+1.8V_ME M

X

XX

X

XXX

ONON

ON

LOW

OFF

OFF

OFF

OFF

OFF

OFF

Thermal
Sensor

Reserve

X
X
X

0X4C

Touch Pad

X

X
X

X

V

0X2C

3

BOM Structure Table

Ite m

For DIS DIS@
For UMA UMA@
For GPU GC6
No GPU GC6
For Ke yboard backlight KBL @
No Keyboa rd backlight NOKB L@
For RF RF@
No RF @RF @
For EMI

For ESD
No ESD

For Samsung VRAM
For Micron VRAM
For Hynix VRAM
For samsung 4G DRAM S4G @
For samsung 8G DRAM S8G @
For samsu ng 16G DRAM S16 G@
For Hynix 4G DRAM H4G @
For Hynix 8G DRAM

For Micron 4G DRAM
For Micron 8G DRAM

X4E for UMA X4E_ UMA
X4E for DIS X4E_ DIS
For CNVi interface CNV i@
Non CNVi interface NONC NVi @
For XDP CMC@
For Thermal Sensor EX_T HM@
For 8G_16G DRAM CHA @

UC1

SA0000C1510
S IC FJ8068403999819 QQAT W0 1.8G C38
I7@

UC1

SA0000C1610
S IC FJ8068404000016 QQAU W0 1.6G C38
I5@

BOM Structure

GC6 @
NOGC 6@

EMI @
@EM I@No EMI
ESD @
@ES D@
ME@Conne ct or
S2G @
M2G @
H2G @

H8G @
H16 G@For Hynix 16G DRAM
M4G @
M8G @
M16 G@For Micron 16G DRAM

ZZZ

DA8001FP000

PCB 2D5 LA-G651P REV0 M/B 2

CPU MB

ZZZ

PCH

X

V

X
X
X

TypeC-Mux

X

Reserve

X

V

X

0X5C

HDMI Logo

RO0000003HM

HDMI Logo

4

5

USB 2.0 Port Table

Por t

1

USB2/3 (re-driver) ( I/O BD)

2

USB2/3 (Charger)

3

Type-C

4
5

Camera

6

FP

7
8
9
10

NGFF WLAN+BT(CNVi)

USB 3.0 Port Table

Por t

1

USB2/3 (re-driver) (I/O SB)

2

USB2/3 (for charger)

3

Type-C

4
5
6

PCIE Port Table

Por t

Lan e

1
2
3
4
5
6
7
8

0

9

3

10

2

11

1

12

0

13

0

14

1

15

2

16

3

NGFF WLAN+BT

SSD

GPU

UMA DiscreteEMC/ESD

ZZZ

X4E_UMA@

X4E_UMA

X4EADO38L02

ZZZ

X4E_DIS@

X4E_DIS

X4EADO38L01

LPDDR3 Onboard RAM

ZZZ

ZZZ

X76@ ZZZ

4G

LPDDR3_S4G

8G

X7679138L01

ZZZ

X76@

LPDDR3_S8G

X7679138L04

ZZZ

X76@

LPDDR3_S16G

X7679138L07

45@

16G

X76@

LPDDR3_H4G

X7679138L02

X76@

LPDDR3_H8G

X7679138L05

ZZZ

X76@

LPDDR3_H16G

X7679138L08

X76@

LPDDR3_M4G

X7679138L03

ZZZ

X76@ZZZ

LPDDR3_M8G

X7679138L06

ZZZ

X76@

LPDDR3_M16G

X7679138L09

Security Classification

Security Classification

Compal For Lenovo

1

2

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/2/5 2019/2/5

2018/2/5 2019/2/5

2018/2/5 2019/2/5

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

LA-G651P

LA-G651P

LA-G651P

5

3 52Friday, May 18, 2018

3 52Friday, May 18, 2018

3 52Friday, May 18, 2018

0.2

0.2

0.2

of

of

of

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Security Classification

Compal For Lenovo

5

4

3

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

Compal Secret Data

2018/2/5 2019/2/5

2018/2/5 2019/2/5

2018/2/5 2019/2/5

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Elect ronics, Inc.

Compal Elect ronics, Inc.

Compal Elect ronics, Inc.

Title

Title

Title

Power MAP

Power MAP

Power MAP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1

4 52Friday, May 18, 201 8

4 52Friday, May 18, 201 8

4 52Friday, May 18, 201 8

0.2

0.2

0.2

5

[ELZ02-PWR Sequence]

4

3

2

1

G3->S0 S0->S3 ->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.05V_MPHYPLL

+1.05V_PRIM_CORE

+1.05V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

C C

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

VCCST

+1.2V_VDDQ/+1.2V_VCCSFR_OC

PM_SLP_S3#

SUSP#

VCCSTG

VCCIO

B B

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

DDR_VTT_PG_CT RL

+0.6VS

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

tPCH01_Min : 9 ms

tPCH06_Min : 200 us

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

If EXT_PWR_GATE# Toffmin is too small, Pwr
gate may choose to completely ignore it

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

tPCH43_Min : 95 ms

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

tPCH18_Min : 90 us

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 10msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

tCPU16 Min : 0 ns

/DS3 DS3S0/

S0->S5

+3VL_RTC

SOC_RTCRST#

B+

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.05V_MPHYPLL

+1.05V_PRIM_CORE

+1.05V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

VCCST

+1.2V_VDDQ/+1.2V_VCCSFR_OC

PM_SLP_S3#

SUSP#

VCCSTG

VCCIO

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

DDR_VTT_PG_CT RL

+0.6VS

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Issued Date

Issued Date

Compal For Lenovo

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/2/5 2019/2/5

2018/2/5 2019/2/5

2018/2/5 2019/2/5

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Power Sequence

Power Sequence

Power Sequence

1

5 52Friday, May 1 8, 2018

5 52Friday, May 1 8, 2018

5 52Friday, May 1 8, 2018

0.2

0.2

0.2

A

1 1

2 2

+3VS

B

HDMI

MUX

For HDMI 1.4

C

UC1A

CPU_DP1_N 0<29>
CPU_DP1_P0<29>
CPU_DP1_N 1<29>
CPU_DP1_P1<29>
CPU_DP1_N 2<29>
CPU_DP1_P2<29>
CPU_DP1_N 3<29>
CPU_DP1_P3<29>

CPU_DP2_N 0<30>
CPU_DP2_P0<30>
CPU_DP2_N 1<30>
CPU_DP2_P1<30>
CPU_DP2_N 2<30>
CPU_DP2_P2<30>
CPU_DP2_N 3<30>
CPU_DP2_P3<30>

EDP_COMP

CPU_DP1_C TRL_CLK<29>
CPU_DP1_C TRL_DATA<29>

CPU_DDPC_ CTRL_DATA

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

WHL-U42 _BGA1528

1 of 20

EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
EDP_TXN_2
EDP_TXP_2
EDP_TXN_3
EDP_TXP_3

EDP_AUX_N
EDP_AUX_P

DISP_UTILS

DDI1_AUX_N
DDI1_AUX_P
DDI2_AUX_N
DDI2_AUX_P
DDI3_AUX_N
DDI3_AUX_P

GPP_E13/DDPB_HPD0/DISP_MISC0
GPP_E14/DDPC_HPD1/DISP_MISC1
GPP_E15/DPPD_HPD2/DISP_MISC2
GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

AG4
AG3
AG2
AG1
AJ4
AJ3
AJ2
AJ1

AH4
AH3

AM7

AC7
AC6
AD4
AD3
AG7
AG6

CN6
CM6
CP7
CP6
CM7

CK11
CG11
CH11

D

EDP_TXN0 <28>
EDP_TXP0 <28>

EC_SCI#

EDP_TXN1 <28>
EDP_TXP1 <28>

EDP_AUXN <28>
EDP_AUXP <2 8>

CPU_DP2_AUXN <30>
CPU_DP2_AUXP <30>

CPU_DP1_H PD <29>
CPU_DP2_H PD <30>

EC_SCI# <34>
EDP_HPD <28>

ENBKL <28,34>
PCH_ENVDD <28>
INVPWM <28>

eDP

From eDP

MUX

From HDMI
From MUX

EC_SCI#

E

1 2

RC480 10K_04 02_5%

+3VS

B

+1.05VS_VCCSTG

12

RC4
1K_0402_5%

RC6 499_0402_ 1%

If routed MS, PECI requires 18 mils spacing to other signals

CATERR#
H_PECI

H_PECI<34>

1 2

RC7 49.9_0402 _1%
RC8 49.9_0402 _1%
RC9 49.9_0402_1%@

RC10 49.9_0402_ 1%@

12
12
12

12

H_PROCHOT# _R
H_THERMT RIP#

CPU_POPIRCOMP
PCH_OPIRCOMP
EDRAM_OPIO_RCOMP

EOPIO_RCOMP

UC1D

AA4

CATERR#

AR1

PECI

Y4

PROCHOT#

BJ1

THRMTRIP#

U1

BPM#_0

U2

BPM#_1

U3

BPM#_2

U4

BPM#_3

CE9

GPP_E3/CPU_GP0

CN3

GPP_E7/CPU_GP1

CB34

GPP_B3/CPU_GP2

CC35

GPP_B4/CPU_GP3

BP27

PROC_POPIRCOMP

BW25

PCH_OPIRCOMP

L5

OPCE_RCOMP

N5

OPC_RCOMP

WHL-U42 _BGA1528

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

4 of 20

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI
PCH_TDO
PCH_TMS

PCH_TRST#
PCH_JTAGX

PROC_PREQ#
PROC_PRDY#

CPU_XDP_TCK 0

T6

SOC_XDP_TDI

U6

SOC_XDP_TDO

Y5

SOC_XDP_TMS

T5

SOC_XDP_TRST #

AB6

W6

SOC_XDP_TDI

U5

SOC_XDP_TDO

W5

SOC_XDP_TMS

P5

SOC_XDP_TRST #

Y6

CPU_XDP_TCK 0

P6

W2
W1

2017/5/3 2017/6/2

2017/5/3 2017/6/2

2017/5/3 2017/6/2

DCI

T2402TP@

DCI

T2403TP@
T2404TP@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

< PU/PD for CMC Debug >

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK 0

1 2

RC11 51_0402_5 %CMC@

1 2

RC12 51_0402_5 %CMC@

1 2

RC13 51_0402_5 %

1 2

RC14 51_0402_5 %

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size D ocument Number R ev

Size D ocument Number R ev

Size D ocument Number R ev

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

WHL-U(1/12)DDI,EDP,MISC,CMC

WHL-U(1/12)DDI,EDP,MISC,CMC

WHL-U(1/12)DDI,EDP,MISC,CMC

Custom

Custom

Custom

+1.05VS_VCCSTG

LA-G651P

LA-G651P

LA-G651P

E

0.2

0.2

6 52Friday, May 18, 2018

6 52Friday, May 18, 2018

6 52Friday, May 18, 2018

0.2

RC436 2.2K_02 01_5%

12

CPU_DDPC_ CTRL_DATA

H_PROCHOT#<34>

< Compensation PU For eDP >

+1.05VS_VCCIO

EDP_COMP

1 2

RC3

3 3

4 4

Trace width=20 mils, Spacing=25mil, Max length=600mils

+1.05V_VCCST

RC5 1K_0402_5%

RC19 4 9.9_0402_1%

1 2

@

24.9_0201_1 %

H_THERMT RIP#

12

CATERR#

Compal For Lenovo

A

5

4

3

2

1

Non- Interleaved Memory

D D

DDR_A_D[16..31]<19>

DDR_A_D[48..63]<19>

DDR_B_D[16..31]<20>

DDR_B_D[48..63]<20>

AN35
AN34
AR35
AR34
AN37
AN36
AR36
AR37
AU35

AU34
AW35
AW34

AU37

AU36
AW36
AW37

BA35

BA34

BC35

BC34

BA37

BA36

BC36

BC37

BE35

BE34

BG35

BG34

BE37

BE36

BG36

BG37

NC1VCC

A

GND

SA00005U600

UC1B

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

DDR0_DQ_15/DDR0_DQ_15

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47
DDR0_DQ_32/DDR1_DQ_0
DDR0_DQ_33/DDR1_DQ_1
DDR0_DQ_34/DDR1_DQ_2
DDR0_DQ_35/DDR1_DQ_3
DDR0_DQ_36/DDR1_DQ_4
DDR0_DQ_37/DDR1_DQ_5
DDR0_DQ_38/DDR1_DQ_6
DDR0_DQ_39/DDR1_DQ_7
DDR0_DQ_40/DDR1_DQ_8
DDR0_DQ_41/DDR1_DQ_9
DDR0_DQ_42/DDR1_DQ_10
DDR0_DQ_43/DDR1_DQ_11
DDR0_DQ_44/DDR1_DQ_12
DDR0_DQ_45/DDR1_DQ_13
DDR0_DQ_46/DDR1_DQ_14
DDR0_DQ_47/DDR1_DQ_15
DDR0_DQ_48/DDR1_DQ_32
DDR0_DQ_49/DDR1_DQ_33
DDR0_DQ_50/DDR1_DQ_34
DDR0_DQ_51/DDR1_DQ_35
DDR0_DQ_52/DDR1_DQ_36
DDR0_DQ_53/DDR1_DQ_37
DDR0_DQ_54/DDR1_DQ_38
DDR0_DQ_55/DDR1_DQ_39
DDR0_DQ_56/DDR1_DQ_40
DDR0_DQ_57/DDR1_DQ_41
DDR0_DQ_58/DDR1_DQ_42
DDR0_DQ_59/DDR1_DQ_43
DDR0_DQ_60/DDR1_DQ_44
DDR0_DQ_61/DDR1_DQ_45
DDR0_DQ_62/DDR1_DQ_46
DDR0_DQ_63/DDR1_DQ_47

WHL-U42_BGA1528

UC2

5

4

Y

DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_1/DDR0_CKN_1
DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8

DDR0_CAA_1/DDR0_MA_9
DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15
DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1

DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT#

DDR0_CAA_9/DDR0_BG_1

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSN_7/DDR1_DQSN_5
DDR0_DQSP_7/DDR1_DQSP_5

2 of 20

1

CC1

0.1U_0201_10V6K

@

2

DDR0_CKE_2/NC
DDR0_CKE_3/NC

NC/DDR0_ODT_1

NC/DDR0_MA_3
NC/DDR0_MA_4

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ_0
DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CNTL

+3VS+1.2V

12

RC132

100K_0402_5%

V32
V31
T32
T31

U36
U37
U34
U35

AE32
AF32
AE31
AF31

AC37
AC36
AC34
AC35
AA35
AB35
AA37
AA36
AB34
W36
Y31
W34
AA34
AC32

AC31
AB32
Y32

W32
AB31
V34

V35
W35

C27
D27
D31
C31
J35
J34
P34
P35
AP35
AP34
AV34
AV35
BB35
BB34
BF34
BF35

W37
W31
F36
D35
D37
E36
C35

follow CRB

DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0

DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3

DDR_A_CS#0

DDR_A_CS#1

DDR_A_ODT0

DDR_A_CAB9

DDR_A_CAB8

DDR_A_CAB5

DDR_A_CAA0

DDR_A_CAA2

DDR_A_CAA4

DDR_A_CAA3

DDR_A_CAA1

DDR_A_CAB7

DDR_A_CAA7

DDR_A_CAA6

DDR_A_CAB0

DDR_A_CAB2

DDR_A_CAB1

DDR_A_CAB3

DDR_A_CAB4

DDR_A_CAB6

DDR_A_CAA5

DDR_A_CAA8

DDR_A_CAA9

DDR_A_DQS#0

DDR_A_DQS0

DDR_A_DQS#1

DDR_A_DQS1
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5

+VREF_CA_C
+V_DDR_REFA_C

+V_DDR_REFB_C
DDR_PG_CTRL

DDR_VTT_PG_CTRL <43>

DDR_A_CLK#0 <19>
DDR_A_CLK0 <19>
DDR_A_CLK#1 <19>
DDR_A_CLK1 <19>

DDR_A_CKE0 <19>
DDR_A_CKE1 <19>
DDR_A_CKE2 <19>
DDR_A_CKE3 <19>

DDR_A_CS#0 <19>
DDR_A_CS#1 <19>
DDR_A_ODT0 <19>

DDR_A_CAB9 <19>
DDR_A_CAB8 <19>
DDR_A_CAB5 <19>

DDR_A_CAA0 <19>
DDR_A_CAA2 <19>
DDR_A_CAA4 <19>
DDR_A_CAA3 <19>
DDR_A_CAA1 <19>
DDR_A_CAB7 <19>
DDR_A_CAA7 <19>
DDR_A_CAA6 <19>
DDR_A_CAB0 <19>

DDR_A_CAB2 <19>
DDR_A_CAB1 <19>
DDR_A_CAB3 <19>

DDR_A_CAB4 <19>
DDR_A_CAB6 <19>
DDR_A_CAA5 <19>

DDR_A_CAA8 <19>
DDR_A_CAA9 <19>

DDR_A_DQS#0 <19>
DDR_A_DQS0 <19>
DDR_A_DQS#1 <19>
DDR_A_DQS1 <19>
DDR_A_DQS#4 <19>
DDR_A_DQS4 <19>
DDR_A_DQS#5 <19>
DDR_A_DQS5 <19>
DDR_B_DQS#0 <20>
DDR_B_DQS0 <20>
DDR_B_DQS#1 <20>
DDR_B_DQS1 <20>
DDR_B_DQS#4 <20>
DDR_B_DQS4 <20>
DDR_B_DQS#5 <20>
DDR_B_DQS5 <20>

+VREF_CA_C
+V_DDR_REFA_C

+V_DDR_REFB_C

Trace width/Spacing >= 20mils

DDR_A_D[0..15]<19>

DDR_A_D[32..47]<19>

C C

DDR_B_D[0..15]<20>

DDR_B_D[32..47]<20>

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

< For ODT & VTT Power Control >

DDR_VTT_CNTL to DDR
VTT supplied ramped
<35u S
(tCPU 18)

DDR_PG_CTRL

2

3

74AUP1G07GW_TSSOP5

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1C

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHL-U42_BGA1528

DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_1/DDR1_CKN_1
DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/NC
DDR1_CKE_3/NC

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7
DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15
DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#

DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQSP_7/DDR1_DQSP_7

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_COMP_0
DDR_COMP_1
DDR_COMP_2

3 of 20

AF28
AF29
AE28
AE29

T28
T29
V28
V29

AL37
AL35
AL36
AL34
AG36
AG35
AF34
AG37
AE35
AF35
AE37
AC29
AE36
AB29
AG34
AC28
AB28
AK35

AJ35
AK34
AJ34

AJ37
AJ36
W29

Y28
W28

H24
G24
C23
D23
G30
H30
L30
N30
AL31
AL30
AU31
AU30
BC31
BC30
BH31
BH30

Y29
AE34
BU31

BN28
BN27
BN29

DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK#1
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0

DDR_B_CAB9
DDR_B_CAB8
DDR_B_CAB5

DDR_B_CAA0
DDR_B_CAA2
DDR_B_CAA4
DDR_B_CAA3
DDR_B_CAA1
DDR_B_CAB7
DDR_B_CAA7
DDR_B_CAA6
DDR_B_CAB0

DDR_B_CAB2
DDR_B_CAB1
DDR_B_CAB3

DDR_B_CAB4
DDR_B_CAB6
DDR_B_CAA5

DDR_B_CAA9
DDR_B_CAA8

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 <20>
DDR_B_CLK0 <20>
DDR_B_CLK#1 <20>
DDR_B_CLK1 <20>

DDR_B_CKE0 <20>
DDR_B_CKE1 <20>
DDR_B_CKE2 <20>
DDR_B_CKE3 <20>

DDR_B_CS#0 <20>
DDR_B_CS#1 <20>
DDR_B_ODT0 <20>

DDR_B_CAB9 <20>
DDR_B_CAB8 <20>
DDR_B_CAB5 <20>

DDR_B_CAA0 <20>
DDR_B_CAA2 <20>
DDR_B_CAA4 <20>
DDR_B_CAA3 <20>
DDR_B_CAA1 <20>
DDR_B_CAB7 <20>
DDR_B_CAA7 <20>
DDR_B_CAA6 <20>
DDR_B_CAB0 <20>

DDR_B_CAB2 <20>
DDR_B_CAB1 <20>
DDR_B_CAB3 <20>

DDR_B_CAB4 <20>
DDR_B_CAB6 <20>
DDR_B_CAA5 <20>

DDR_B_CAA9 <20>

DDR_B_CAA8 <20>

DDR_A_DQS#2 <19>
DDR_A_DQS2 <19>
DDR_A_DQS#3 <19>
DDR_A_DQS3 <19>
DDR_A_DQS#6 <19>
DDR_A_DQS6 <19>
DDR_A_DQS#7 <19>
DDR_A_DQS7 <19>
DDR_B_DQS#2 <20>
DDR_B_DQS2 <20>
DDR_B_DQS#3 <20>
DDR_B_DQS3 <20>
DDR_B_DQS#6 <20>
DDR_B_DQS6 <20>
DDR_B_DQS#7 <20>
DDR_B_DQS7 <20>

1 2

RC246 200_0402_1%
RC247 80.6_0201_1%

1 2
1 2

RC40 162_0402_1%

Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/02/06 202 0/5/17

2018/02/06 202 0/5/17

2018/02/06 202 0/5/17

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

WHL-U(2/12)LPDDR3

WHL-U(2/12)LPDDR3

WHL-U(2/12)LPDDR3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, May 18, 2018

Friday, May 18, 2018

Friday, May 18, 2018

LA-G651P

LA-G651P

LA-G651P

1

52

52

52

7

7

7

0.2

0.2

0.2

Compal For Lenovo

5

4

3

2

1

+3VALW

1 2

RC437 100K_02 01_5%

1 2

RC438 100K_02 01_5%

1 2

RC439 100K_02 01_5%

SOC_SPI_0 _SI
SOC_SPI_0 _IO2
SOC_SPI_0 _IO3

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

D D

SOC_SPI_0 _CLK
SOC_SPI_0 _SO
SOC_SPI_0 _SI

SPI ROM

+3VS

1 2

RC25 8.2K_040 2_5%

C C

+3VS

1 2

RC112 10K_040 2_5%

SERIRQ

SERIRQ<34>

KB_RST#

SOC_SPI_0 _IO2
SOC_SPI_0 _IO3
SOC_SPI_0 _CS#0

SERIRQ

RPC1, RPC3 an d RC30 are clo se to UC3

SOC_SPI_0 _SO
SOC_SPI_0 _CLK SOC_SPI_0_CLK_R
SOC_SPI_0 _SI

From SOC

B B

From EC

EC_SPI_CL K<34>
EC_SPI_MO SI<34>
EC_SPI_CS 0#<34>

EC_SPI_MISO<34>

SOC_SPI_0 _IO3

SOC_SPI_0 _IO2

EC_SPI_CL K
EC_SPI_MO SI SOC_SPI_0 _SI_R
EC_SPI_CS 0#
EC_SPI_MISO

1 2

RC469 33_0402 _5%

1 2

RC470 33_0402 _5%EMI@

1 2

RC471 33_0402 _5%

1 2

RC472 33_0402 _5%

1 2

RC30 33_0402 _5%

1 2

RC473 33_0402 _5%EMI@

1 2

RC474 33_0402 _5%

1 2

RC475 33_0402 _5%

1 2

RC476 33_0402 _5%

SOC_SPI_0 _IO2_R

SOC_SPI_0 _SO_R

SOC_SPI_0 _SI_R
SOC_SPI_0 _IO3_R

SOC_SPI_0 _CLK_R

SOC_SPI_0 _CS#0
SOC_SPI_0 _SO_R

UC1E

CH37

SPI0_CLK

CF37

SPI0_MISO

CF36

SPI0_MOSI

CF34

SPI0_IO2

CG34

SPI0_IO3

CG36

SPI0_CS0#

CG35

SPI0_CS1#

CH34

SPI0_CS2#

CF20

GPP_D1/SPI1_CLK/BK1/SBK1

CG22

GPP_D2/SPI1_MISO_IO1/BK2/SBK2

CF22

GPP_D3/SPI1_MOSI_IO0/BK3/SBK3

CG23

GPP_D21/SPI1_IO2

CH23

GPP_D22/SPI1_IO3

CG20

GPP_D0/SPI1_CS0#/BK0/SBK0

CH7

CL_CLK

CH8

CL_DATA

CH9

CL_RST#

BV29

GPP_A0/RCIN#/TIME_SYNC1

BV28

GPP_A6/SERIRQ

WHL -U42_BGA1528

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

5 of 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

CK14
CH15
CJ15

CH14
CF15
CG15

CN15
CM15
CC34

CA29
BY29
BY27
BV27
CA28
CA27

BV32
BV30
BY30

PCH_SMB _CLK
PCH_SMB _DATA

SOC_SML 0CLK
SOC_SML 0DATA

EC_SMB_ CK2
EC_SMB_ DA2

SOC_SML 1ALERT#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRA ME#

LPC_CLK 0

PM_CLKR UN#KB_RST#

1 2

RC26 22_0402 _5%EMI@

1

2

Close to RC26

CC3865

33P_0402_50V8J

@RF@

EC_SMB_ CK2 <24,30,34 ,36>

EC_SMB_ DA2 <24,30,34 ,36>

LPC_AD0 <34>
LPC_AD1 <34>
LPC_AD2 <34>
LPC_AD3 <34>

LPC_FRA ME# <34>

PM_CLKR UN# <3 4>

EC_SMB_ CK2

EC_SMB_ DA2

SOC_SML 1ALERT#

PCH_SMB _CLK
PCH_SMB _DATA
SOC_SML 0CLK
SOC_SML 0DATA

PM_CLKR UN#

SMB

(Link to DDR)

SML1

(Link to EC,DGPU,Thermal IC)

CLK_LPC _EC <3 4>

1 2

RC28 1K_0402 _5%

1 2

RC29 1K_0402 _5%

1 2

@

RC113 150K_04 02_5%

1 2

12
12
12
12

RC465 1K_0402 _5%
RC466 1K_0402 _5%
RC467 1K_0402 _5%
RC468 1K_0402 _5%

RC31 8.2K_0402_5%

+3VS

+3VS

< SPI ROM - 16M >

SOC_SPI_0 _CS#0

SOC_SPI_0 _IO2_R

A A

UC3

1

CS#

2

DO(IO1)

3

IO2

4

GND

XM25QH1 28AHIG SOP 8P

Compal For Lenovo

5

VCC

CLK

DI(IO0)

IO

8
7
6
5

+3VALW

@

1 2

CC2 0.1U_0201 _10V6K

SOC_SPI_0 _IO3_RSOC_SPI_0 _SO_R
SOC_SPI_0 _CLK_R
SOC_SPI_0 _SI_R

1

CC3
10P_040 2_50V8J

2

@EMI@

Security Classification

Security Classification

Security Classification

2017/5/3 2017/6/2

2017/5/3 2017/6/2

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2017/5/3 2017/6/2

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

WHL-U(3/12)SPI,SMB,LPC,ESPI

WHL-U(3/12)SPI,SMB,LPC,ESPI

WHL-U(3/12)SPI,SMB,LPC,ESPI

LA-G651P

LA-G651P

LA-G651P

8 52Friday, May 18, 2018

8 52Friday, May 18, 2018

8 52Friday, May 18, 2018

1

0.2

0.2

0.2

5

Vender ID

Samsung

Hynix

Micron

D D

DRAM Capacity

4GB
8GB
16GB

< HD AUDIO >

HDA_BIT_CLK_R<33>

HDA_SYNC_R<33>
HDA_SDOUT_R<33>

C C

CPU_GPP_G7 CPU_GPP_G6

SDRAM_ID4 SDRAM_ID3

0 0
0
1

CPU_GPP_G5 CPU_GPP_G4

SDRAM_ID2 SDRAM_ID1

1
0

0 0
0
1

HDA_SDOUT reserve 500 ohm PD for Audio
lost issue

1 2

RC477 33_040 2_5%EMI@

1 2

RC478 33_040 2_5%

1 2

RC479 33_040 2_5%

1

Close to RC477

2

1
0

HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT

12

RC3945

@

499_0402_ 1%

CC3866

33P_0402_50V8J

@RF@

CPU Memory down vender control table

CPU_GPP_G7

0 0

1 0 0 1

HDA_SDIN0<33>

< To Enable ME Override >

CNV_RF_RESET #<3 2>

CLKREQ_CNV#<32>

ME_EN< 34>

DGPU

B B

RC116 0_0402 _5%

GC6_FB_EN<24,25>

GPU_EVENT#<24>

1 2

12

GC6_FB_EN GC6_FB_EN1V8

GPU_EVENT# SOC_GPP_C10

CNV_RF_RESET #

RC390775K_0 402_5% CNVi@

HDA_SDOUT

RC463 0_0402 _5%

RC464 0_0402 _5%

12

1 2

HDA_SPKR<33 >

CLK_CNV_CRX_D TX_N<32>
CLK_CNV_CRX_D TX_P<32>
CLK_CNV_CT X_DRX_N<32>
CLK_CNV_CT X_DRX_P<32>

Follow Jefferson Peak schematic check list.

+3VS

1 2

RC487 10K_0402_5%@

1 2

A A

RC33 2.2K_0402 _5%@

WLBT_OFF#

HDA_SPKR

4

CPU_GPP_G4CPU_GPP_G5CPU_GPP_G6

SDRAM_ID2SDRAM_ID3SDRAM_ID4

Vende r

Samsung K4E6E304EC-EG CG

0

Hynix

Micron

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT

CNV_RF_RESET #

CLKREQ_CNV#

HDA_SPKR

1 2

COEX3<32>

1 2

10K_0402_5 %

CNV_CRX_DTX_N0
CNV_CRX_DTX_P0

CNV_CRX_DTX_N1
CNV_CRX_DTX_P1
CNV_CTX_DRX_N0
CNV_CTX_DRX_P0

CNV_CTX_DRX_N1
CNV_CTX_DRX_P1

CLK_CNV_CRX_D TX_N
CLK_CNV_CRX_D TX_P
CLK_CNV_CT X_DRX_N
CLK_CNV_CT X_DRX_P

RC443150_040 2_1% C NVi@

SOC_GPP_C10
WLBT_OFF#

CNV_CRX_DTX_N0<32>
CNV_CRX_DTX_P0<32>

CNV_CRX_DTX_N1<32>
CNV_CRX_DTX_P1<32>

CNV_CTX_DRX_N0<32>
CNV_CTX_DRX_P0<32>

CNV_CTX_DRX_N1<32>
CNV_CTX_DRX_P1<32>

TP_INT#<35>

WLBT_OFF#<32>

COEX1<32>
COEX2<32>

RC444

SDRAM_ID1

0

1
1 1
0 0
010
1
1 1
0 0

MD size

0
1
0

8GB

16GB

4GB

4GB
1
0

8GB

16GB

4GB

4GB

8GB
01

1 1

UC1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

WHL-U42 _BGA1528

CNV_WT_R COMP

COEX3

GC6_FB_EN1V8

COEX1
COEX2

SOC_A4WP_PR ESENT

16GB

4GB

UC1I

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP32

CNV_WT_RCOMP_0

CR32

CNV_WT_RCOMP_1

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

WHL-U42 _BGA1528

3

Vender desciption

K4E8E324EB-EGC G4GB

K4EBE304EC -EGCG
K4E6E304EC -EGCG(CH B-ONLY)
H9CCNNN8GTALAR-NV D
H9CCNNNBJTALAR-NVD
H9CCNNNCLGALAR-NVD
H9CCNNNBJ TALAR-NVD(C HB-ONLY)
MT52L256M32D1PF-093WT:B
MT52L512M32D2PF-093WT:B
MT52L1G32D4PG-093WT:B
MT52L512M32D2PF-093WT:B(CHB-ONLY)

GPP_G0/SD_CMD
GPP_G1/SD3_DATA0
GPP_G2/SD3_DATA1
GPP_G3/SD3_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

7 of 20

GPP_D4/IMGCLKOUT0/BK4/SBK4

9 of 20

GPP_A16/SD_1P8_SEL

SD_1P8_RCOMP
SD_3P3_RCOMP

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_H21
GPP_H22
GPP_H23
GPP_F10

GPD7

GPP_F3

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0
GPP_F13/EMMC_DATA1
GPP_F14/EMMC_DATA2
GPP_F15/EMMC_DATA3
GPP_F16/EMMC_DATA4
GPP_F17/EMMC_DATA5
GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

GPP_H21 XTAL frequency selected.
0: 38.4/19.2Mhz
1: 24MHz XTAL selected

SOC_C10_GATE#

CN27

CM27

SOC_GPP_H21

CF25
CN26
CM26
CK17

SOC_GPD7

BV35
CN20

XTAL INPUT MODE (HVM ONLY)

CG25

LOW: XTAL INPUT IS SINGLE ENDED

CH25

HIGH: XTAL IS ATTACHED

CR20
CM20
CN19
CM19
CN18
CR18
CP18
CM18

CM16
CP16
CR16
CN16

SOC_SD_RCOM P

CK15

BOM Conf i g

Vende r

Samsung

Hynix

Micron

CH36
CL35
CL36
CM35

SDRAM_ID1

CN35

SDRAM_ID2

CH35

SDRAM_ID3

CK36

SDRAM_ID4

CK34

BW36
BY31

CK33

SOC_SD_RCOM P

CM34

RC441 4.7K_0402_5 %

RC442 100K_0 201_5%

SDRAM_ID4 SDRAM_ID3 SDRAM_ID2 SDRAM_ID1

MD size

4GB

8GB

16GB

4GB

8GB

16GB

4GB

8GB

16GB

1 2

RC440 200_040 2_1%

SOC_C10_GATE# <13>

1 2

1 2

2

RC435

RC433

S4G@

RC435

S8G@

RC435

S16G@

RC435

H4G@

RC435

H8G@

RC435

H16G@

RC434

M4G@

RC434

M8G@

RC434

M16G@

S4G@

RC433

S8G@

RC433

S16G@

RC432

H4G@

RC432

H8G@

RC432

H16G@

RC433

M4G@

RC433

M8G@

RC433

M16G@

RC248

RC249

S4G@

S4G@

RC89

S8G@

RC248

S16G@

RC248

H4G@

RC89

H8G@

RC248

H16G@

RC248

M4G@

RC89

M8G@

RC248

M16G@

RC249

S8G@

RC88

S16G@

RC249

H4G@

RC249

H8G@

RC88

H16G@

RC249

M4G@

RC249

M8G@

RC88

M16G@

UD1 S8G@

SA0000AZT20

UD1 S16G@

SA00008VV20

UD1 H8G@

SA0000ALP00

UD1 H16G@

SA00009ZL00

UD1 M8G@

SA0000AM400

UD1 M16G@

SA00009ZN00

LPDDR3

UD2 S8G@

SA0000AZT20

UD2 S16G@

SA00008VV20

UD2 H8G@

SA0000ALP00

UD2 H16G@

SA00009ZL00

UD2 M8G@

SA0000AM400

UD2 M16G@

SA00009ZN00

1

UD3 S4G@

SA0000AZT20

UD3 S8G@

SA0000AZT20

UD3 S16G@

SA00008VV20

UD3 H4G@

SA0000ALP00

UD3 H8G@

SA0000ALP00

UD3 H16G@

SA00009ZL00

UD3 M4G@

SA0000AM400

UD3 M8G@

SA0000AM400

UD3 M16G@

SA00009ZN00

UD4 S4G@

SA0000AZT20

UD4 S8G@

SA0000AZT20

UD4 S16G@

SA00008VV20

UD4 H4G@

SA0000ALP00

UD4 H8G@

SA0000ALP00

UD4 H16G@

SA00009ZL00

UD4 M4G@

SA0000AM400

UD4 M8G@

SA0000AM400

UD4 M16G@

SA00009ZN00

Memory Strap Resistors

+3VS +3VS +3VS + 3VS

+3VALW

SDRAM_ID1
SDRAM_ID2
SDRAM_ID3
SDRAM_ID4

12

12

RC249
10K_0201_5 %

@

RC88
10K_0201_5 %

@

12

12

RC248
10K_0201_5 %

@

RC89
10K_0201_5 %

@

12

RC432
10K_0201_5 %

12

RC433
10K_0201_5 %

12

RC434

@

@

10K_0201_5 %

12

RC435
10K_0201_5 %

@

@

SPKR ( Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode.

Compal For Lenovo

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

2017/5/3 2017/6/2

2017/5/3 2017/6/2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size D ocument Number R ev

Size D ocument Number R ev

Size D ocument Number R ev

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

WHL-U(4/12)HDA,EMMC,SDIO,CSI2

WHL-U(4/12)HDA,EMMC,SDIO,CSI2

WHL-U(4/12)HDA,EMMC,SDIO,CSI2

LA-G651P

LA-G651P

Friday, May 18, 2018

Friday, May 18, 2018

Friday, May 18, 2018

LA-G651P

1

52

52

52

9

9

9

0.2

0.2

0.2

5

< PCH PLTRST Buf f er >

+3VS

1 2

RC481 10K_04 02_5%

1 2

RC482 10K_04 02_5%

1 2

RC483 10K_04 02_5%

CLKREQ_PCIE#0

12

RC140

@

D D

10K_0402_5 %

CLKREQ_PCIE#0
CLKREQ_PCIE#2
CLKREQ_PCIE#4

DGPU

NGFF WL+BT(KEY E)

SSD

+3VL_RTC

WAKE#

SOC_SRTCRS T#

CLR CMOS

SM_INTRUDER#

PCH_PWR OK
EC_RSMRST#
SYS_RESET#

+1.05V_VCCST

12

RC52
1K_0402_5%

RC53 60.4_0402_ 1%

CC126

100P_0402_50V8J

1

ESD@

2

EC_CLEAR_CMO S# <34>

1 2

1 2

RC36 20K_0402_ 5%

12

CC6 1U_0201_6 .3V6M

1 2

RC37 20K_0402_ 5%

12

CC7 1U_0201_6 .3V6M

1 2

CLRP2 SHORT PADS

1 2

C C

B B

RC39 1M_0402_5 %

+3VALW

RC484 10K_04 02_5%
RC485 10K_04 02_5%
RC486 10K_04 02_5%

1 2

ESD@

CC97 100P_0402_ 50V8J

1 2

ESD@

CC94 100P_0402_ 50V8J

1 2

ESD@

CC95 100P_0402_ 50V8J

+3VALW

1 2

1 2
1 2
1 2

RC54

1K_0402_5%

SYS_RESET#

EC_RSMRST#

SYS_PWROK

From EC (Open-Drain)

VCCST_PWR GD<34>

EC_VCCST_PG

4

UC1J

CLK_PCIE_N0< 21>
CLK_PCIE_P0<21>
CLKREQ_PCIE#0<2 1>

CLK_PCIE_N2< 32>
CLK_PCIE_P2<32>
CLKREQ_PCIE#2<3 2>

CLK_PCIE_N4< 32>
CLK_PCIE_P4<32>
CLKREQ_PCIE#4<3 2>

EC_RSMRST#<34>

T31 T P@

SYS_PWROK<34>

PCH_PWR OK<34>

CLKREQ_PCIE#0

CLKREQ_PCIE#2

CLKREQ_PCIE#4

SOC_PLTRST #
SYS_RESET#
EC_RSMRST#

EC_VCCST_PG

SYS_PWROK
PCH_PWR OK
EC_RSMRST#

WAKE#

AW2

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

CLKOUT_PCIE_P_4

CE30

GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N_5

BE2

CLKOUT_PCIE_P_5

CF31

GPP_B10/SRCCLKREQ5#

WHL-U42 _BGA1528

SOC_PLTRST #

UC1K

BJ35

GPP_B13/PLTRST#

CN10

SYS_RESET#

BR36

RSMRST#

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

CR10

SYS_PWROK

BP31

PCH_PWROK

BP30

DSW_PWROK

BV34

GPP_A13/SUSWARN#/SUSPWRDACK

BY32

GPP_A15/SUSACK#

BU30

WAKE#

BU32

GPD2/LAN_WAKE#

BU34

GPD11/LANPHYPC

WHL-U42 _BGA1528

3

10 of 20

TC7SH08FU F_SSOP5

GPP_B11/EXT_PWR_GATE#

11 of 20

XTAL_IN

XTAL_OUT

CLK_BIASREF

CLKIN_XTAL

RTCX1
RTCX2

SRTCRST#

RTCRST#

UC4

P

4

Y

G

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD6/SLP_A#

GPD0/BATLOW#

INTRUDER#

INPUT3VSEL

AU1
AU2

BT32

CK3
CK2

CJ1
CM3

BN31
BN32

BR37
BR34

12

RC44

100K_0402_5%

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

1 2

RC55 0_0402_5%

+3VS

5

1

B

2

A

3

@

GPP_B12/SLP_S0#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPP_B2/VRALERT#

SUSCLK

33E_SOC_XTAL24 _IN_R

33E_SOC_XTAL24 _OUT_R

XCLK_BIASREF
CLKIN_XTAL

SOC_RTCX1
SOC_RTCX2

SOC_SRTCRS T#
EC_CLEAR_CMO S#

12

CC8
100P_0402_ 50V8J

ESD@

BJ37

PM_SLP_S3#

BU36

PM_SLP_S4#

BU27

PM_SLP_S5#

BT29

BU29
BT31
BT30
BU37

PBTN_OUT#

BU28

AC_PRESENT_R

BU35

PM_BATLOW#

BV36

SM_INTRUDER#

BR35

CC37

SOC_VRALERT#

CC36

SOC_INPUT3VSEL

BT27

PCI_RST# <21,32,34>

RC103 0_0402 _5%

SUSCLK <32>

CLKIN_XTAL < 32>

PM_SLP_S3# <34 >
PM_SLP_S4# <34 ,41>

T131TP@

1 2

2

33E_SOC_XTAL24 _IN_R

33E_SOC_XTAL24 _OUT_R

RC58 47_0201_5 %

LC99

1

1

4

4

DLM0NSN90 0HY2D_4P

RC63 47_0201_5 %EMI@

PBTN_OUT# < 34>
AC_PRESENT <24,34 >

1 2

EMI@

@EMI@

1 2

XCLK_BIASREF

RC110 60.4_04 02_1%

CLKIN_XTAL

RC245 10K_04 02_5%

33E_SOC_XTAL24 _IN

2

2

3

3

33E_SOC_XTAL24 _OUT

SOC_RTCX2

SOC_RTCX1

PM_BATLOW#

AC_PRESENT_R

SOC_VRALERT#

SOC_INPUT3VSEL

1

1 2

1 2

1 2

RC38 200K_0402 _1%

YC3

SJ10000UJ00

24MHZ_18PF_XRC GB24M000F2P51R0

3

3

CC19

27P_0402_50V8J

1

2

RC41 10M_0402_ 5%

32.768KHZ_9P F_X1A000141000200

1

CC9

6.8P_0402_5 0V8C

2

RC46 8.2K_0402_ 5%

RC48 10K_0402_ 5%

RC50 10K_0402_ 5%

RC445 4.7K_0402 _5%

RC446 4.7K_0402 _5%

1 2

YC2

1 2

1 2

1 2

@

1 2

@

1 2

@

1 2

NC

NC

2

4

1

1

1

CC10

6.8P_0402_5 0V8C

2

+3VALW

CC20

27P_0402_50V8J

1

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

2017/5/3 2017/6/2

2017/5/3 2017/6/2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

WHL-U(5/12)CLK,PM,GPIO

WHL-U(5/12)CLK,PM,GPIO

WHL-U(5/12)CLK,PM,GPIO

Size D ocument Number R ev

Size D ocument Number R ev

Size D ocument Number R ev

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

2

Date : Sheet of

LA-G651P

LA-G651P

LA-G651P

1

10 52Friday, May 18, 2018

10 52Friday, May 18, 2018

10 52Friday, May 18, 2018

0.2

0.2

0.2

5

4

3

2

1

GSPI0_MOSI (Internal Pu ll Down):

No Reboot

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This funct i on is usef ul
when running ITP/XDP.

D D

GSPI1_MOSI (Internal Pu ll Down):

Boot BIOS Strap Bit

0 = SPI Mode ==> Default

1 = LPC Mode

+3VS

+3VS

C C

1 2

RC59 4.7K_0402 _5%@

1 2

RC60 150K_040 2_5%@

1 2

RC83 49.9K_040 2_1%

1 2

RC84 49.9K_040 2_1%

1 2

RC3941 2.2K_040 2_5%

1 2

RC3942 2.2K_040 2_5%

1 2

RC488 10K_04 02_5%DIS@

1 2

RC489 10K_04 02_5%

1 2

RC42 2.2K_0402 _5%

1 2

RC43 2.2K_0402 _5%

1 2

RC447 10K_04 02_5%@

1 2

RC448 10K_04 02_5%DIS@

GSPI0_MOSI

GSPI1_MOSI

UART0_RX
UART0_TX
I2C_1_SDA
I2C_1_SCL

DGPU_PWR _EN

SOC_GPP_A7
I2C_0_SDA

I2C_0_SCL
DGPU_HOLD_R ST#
DGPU_HOLD_R ST#

Touch Pad

UCM

CNV_BRI_CRX_DTX<32>
CNV_RGI_CTX_DRX<32>
CNV_BRI_CTX_DRX<32>
CNV_RGI_CRX_DTX<32>

I2C_0_SDA<35>
I2C_0_SCL<35>

I2C_1_SDA<30>
I2C_1_SCL<30>

T2406

SOC_GPP_A7
GPP_B16

GSPI0_MOSI

TP@

GSPI1_MOSI

CNV_BRI_CRX_DTX
CNV_RGI_CTX_DRX
CNV_BRI_CTX_DRX
CNV_RGI_CRX_DTX

UART0_RX<32,35 >

UART0_TX<32,35>

UC1F

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHL-U42 _BGA1528

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

6 of 20

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

CN22
CR22
CM22
CP22

CK22
CH20

CH22
CJ22

CJ27
CJ29

CM24
CN23
CM23
CR24

CG12
CH12
CF12
CG14

BW35
BW34
CA37
CA36
CA35
CA34
BW37

GPP_H11

DGPU_PWR _EN
DGPU_HOLD_R ST#
GPU_ALL_PGOOD
DGPU_PRSNT #

T2405TP@

DGPU_PWR _EN <24,26,34>
DGPU_HOLD_R ST# <21>
GPU_ALL_PGOOD < 21>

Funct i on

DIS

UMA Only

DGPU_PRSNT #

DGPU

DGPU_PRSNT#
(GPP_C1 5)

0

1

+3VS

12

R7310K_0402_5 % UMA@

12

R7410K_0402_5 % DIS@

B B

Place close to PCH

+1.8VALW

CNV_RGI_CRX_DTX
CNV_BRI_CRX_DTX

A A

1 2

RC3939 20K_020 1_5%@

1 2

RC3938 20K_020 1_5%@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

2017/5/3 2017/6/2

2017/5/3 2017/6/2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size D ocument Number R ev

Size D ocument Number R ev

Size D ocument Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

WHL-U(6/12)GPIO,I2C,GSPI

WHL-U(6/12)GPIO,I2C,GSPI

WHL-U(6/12)GPIO,I2C,GSPI

LA-G651P

LA-G651P

LA-G651P

1

11 52Friday, May 18, 2018

11 52Friday, May 18, 2018

11 52Friday, May 18, 2018

0.2

0.2

0.2

5

4

3

2

1

D D

PCIE_CRX_ DTX_N8<3 2>

NGFF WLAN+BT

C C

SSD

dGPU

B B

PCIE_CRX_ DTX_P8<32>

PCIE_CTX_ DRX_N8<3 2>
PCIE_CTX_ DRX_P8<32>

PCIE_CRX_ DTX_N9<3 2>
PCIE_CRX_ DTX_P9<32>
PCIE_CTX_ DRX_N9<3 2>
PCIE_CTX_ DRX_P9<32>

PCIE_CRX_ DTX_N10<32>
PCIE_CRX_ DTX_P10<32>
PCIE_CTX_ DRX_N10<32>
PCIE_CTX_ DRX_P10<32>

PCIE_CRX_ DTX_N11<32>
PCIE_CRX_ DTX_P11<32>
PCIE_CTX_ DRX_N11<32>
PCIE_CTX_ DRX_P11<32>

PCIE_CRX_ DTX_N12<32>
PCIE_CRX_ DTX_P12<32>
PCIE_CTX_ DRX_N12<32>
PCIE_CTX_ DRX_P12<32>

PCIE_CRX_DTX_N13<21>
PCIE_CRX_DTX_P13<21>

PCIE_CTX_ C_DRX_N13<21>
PCIE_CTX_ C_DRX_P13<21>

PCIE_CRX_DTX_N14<21>

PCIE_CRX_DTX_P14<21>
PCIE_CTX_ C_DRX_N14<21>
PCIE_CTX_ C_DRX_P14<21>

PCIE_CRX_DTX_N15<21>
PCIE_CRX_DTX_P15<21>

PCIE_CTX_ C_DRX_N15<21>
PCIE_CTX_ C_DRX_P15<21>

PCIE_CRX_DTX_N16<21>
PCIE_CRX_DTX_P16<21>

PCIE_CTX_ C_DRX_N16<21>
PCIE_CTX_ C_DRX_P16<21>

1 2

CC114 0.22U_02 01_6.3V6MDIS@

1 2

CC149 0.22U_02 01_6.3V6MDIS@

1 2

CC188 0.22U_02 01_6.3V6MDIS@

1 2

CC187 0.22U_02 01_6.3V6MDIS@

1 2

CC185 0.22U_02 01_6.3V6MDIS@

1 2

CC186 0.22U_02 01_6.3V6MDIS@

1 2

CC184 0.22U_02 01_6.3V6MDIS@

1 2

CC183 0.22U_02 01_6.3V6MDIS@

1 2

RC71 100_0402_1%

Near UC1

PCIE_CTX_ DRX_N13
PCIE_CTX_ DRX_P13

PCIE_CTX_ DRX_N14
PCIE_CTX_ DRX_P14

PCIE_CTX_ DRX_N15
PCIE_CTX_ DRX_P15

PCIE_CTX_ DRX_N16
PCIE_CTX_ DRX_P16

PCIE_RCOM PN
PCIE_RCOM PP

UC1H

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCIE7_TXN

BU1

PCIE7_TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCIE8_TXN

BT3

PCIE8_TXP

BP5

PCIE9_RXN

BP6

PCIE9_RXP

BR2

PCIE9_TXN

BR1

PCIE9_TXP

BN6

PCIE10_RXN

BN5

PCIE10_RXP

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN10

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE6

PCIE_RCOMP_N

CE5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2/CFG_0

CP28

GPP_H13/M2_SKT2/CFG_1

CN28

GPP_H14/M2_SKT2/CFG_2

CM28

GPP_H15/M2_SKT2/CFG_3

WHL -U42_BGA1528

When PCIE16/SATA2 is used as SATA Port 1 (ODD), then
PCIE15/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

8 of 20

PCIE1_RXN/USB31_1_RXN

PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN
PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

PCIE3_RXN/USB31_3_RXN

PCIE3_RXP/USB31_3_RXP
PCIE3_TXN/USB31_3_TXN
PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN

PCIE4_RXP/USB31_4_RXP
PCIE4_TXN/USB31_4_TXN
PCIE4_TXP/USB31_4_TXP

GPP_E9/USB2_OC0#/GP_BSSB_CLK

GPP_E10/USB2_OC1#/GP_BSSB_DI

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

USB2_1N
USB2_1P

USB2_2N
USB2_2P

USB2_3N
USB2_3P

USB2_4N
USB2_4P

USB2_5N
USB2_5P

USB2_6N
USB2_6P

USB2_7N
USB2_7P

USB2_8N
USB2_8P

USB2_9N
USB2_9P

USB2_10N
USB2_10P

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

UFS_RESET#

CB5
CB6
CA4
CA3

BY8
BY9
CA2
CA1

BY7
BY6
BY4
BY3

BW6
BW5
BW2
BW1

CE3
CE4

CE1
CE2

CG3
CG4

CD3
CD4

CG5
CG6

CC1
CC2

CG8
CG9

CB8
CB9

CH5
CH6

CC3
CC4

CC5
CE8
CC6

CK6
CK5
CK8
CK9

CP8
CR8
CM8

CN8
CM10
CP10

CN7

AR3

USB20_N 1
USB20_P 1

USB20_N 2
USB20_P 2

USB20_N 3
USB20_P 3

USB20_N 5
USB20_P 5

USB20_N 6
USB20_P 6

USB20_N 10
USB20_P 10

USB2_CO MP
USB2_ID
USB2_SE NSE

USB_OC0 #
USB_OC1 #
USB_OC2 #
USB_OC3 #

WL_ OFF#

USB3_CR X_DTX_N1 <37>
USB3_CR X_DTX_P1 <37>
USB3_CT X_DRX_N1 <37>
USB3_CT X_DRX_P1 <37>

USB3_CR X_DTX_N2 <37>
USB3_CR X_DTX_P2 <37>
USB3_CT X_DRX_N2 <37>
USB3_CT X_DRX_P2 <37>

USB3_CR X_MTX_N3 < 30>
USB3_CR X_MTX_P3 <30 >
USB3_CT X_MRX_N3 < 30>
USB3_CT X_MRX_P3 <30 >

USB20_N 1 <37>
USB20_P 1 <3 7>

USB20_N 2 <37>
USB20_P 2 <3 7>

USB20_N 3 <31>
USB20_P 3 <3 1>

USB20_N 5 <28>
USB20_P 5 <2 8>

USB20_N 6 <35>
USB20_P 6 <3 5>

USB20_N 10 <32>
USB20_P 10 < 32>

1 2

RC70 113_040 2_1%

1 2

RC104 0_0402_ 5%@

1 2

RC105 1K_0402 _5%@

WL_ OFF# <32>

USB_OC2 #
USB_OC0 #
USB_OC3 #
USB_OC1 #

USB2/3 (re-driver) (I/O SB)

USB2/3 (for charger)

Type-C

USB2/3 (re-driver) ( I/O BD)

USB2/3 (Charger)

Type-C

Camera

FP

CNVi

Trace length max: 450mils

RC490 10K_040 2_5%
RC491 10K_040 2_5%
RC492 10K_040 2_5%
RC493 10K_040 2_5%

12
12
12
12

+3VALW

+3VS

A A

Security Classification

Security Classification

Security Classification

2017/5/3 2017/6/2

2017/5/3 2017/6/2

Issued Date

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/5/3 2017/6/2

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

WL_ OFF#

Title

Title

Title

WHL-U(7/12)PCIE,USB,SATA

WHL-U(7/12)PCIE,USB,SATA

WHL-U(7/12)PCIE,USB,SATA

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

RC131 10K_040 2_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

@

1 2

LA-G651P

LA-G651P

LA-G651P

0.2

0.2

0.2

12 52Friday, May 18, 2018

12 52Friday, May 18, 2018

12 52Friday, May 18, 2018

1

5

+VL +1.05VS_ VCCIO

+1.05VALW TO +1.05V_VCCST

+1.8VALW TO +1.8VS

D D

C C

SYSON<34,43,44 >

SUSP#<34,38,4 3>

1 2

RC450 0_0402_ 5%

1 2

RC452 0_0402_ 5%

+VL

0.1U_0201_10V6K

CC30

1

@

2

SUSP#

+1.05VAL W

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

CC150

+1.05VALW TO +1.05VS_VCCIO

CC32

+1.05VAL W

+1.8VALW

EN_1.0V_ VCCSTU

EN_1.8VS

I(Max) : 3.675 A(+1.05VS_VCCIO)
RON(Max) : 6.2 mohm
V drop : 0.019 V

UC6

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

EM5201V _DFN8_3X3

4

I(Max) : 0.16 A(+1.05V_VCCST)
RON(Max) : 25 mohm
V drop : 0.004 V

UC7

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 DFN 14P

I(Max) : 0.2 A(+1.8VS)
RON(Max) : 25 mohm
V drop : 0.005 V

+1.05VS_ VCCIO_STG

6

VOUT

5

GND

VOUT1
VOUT1

CT1

GND

CT2

VOUT2
VOUT2

GPAD

14
13

12

11

10

9
8

15

@

1 2

CC33

0.1U_0201_10V6K

1

2

RC451

RC453

1 2

0_0402_ 5%

0_0402_ 5%

+1.05V_V CCST_R

1 2

CC152
8200P_0 402_25V7K

1 2

CC153
1000P_0 402_50V7K

+1.8VS_R

Follow 543977_SKL_PDDG_ Rev0_91
CC24 10PF ->22us(Spec:<= 65us)

+1.05VS_ VCCIO

RC79

1 2

0_0805_ 5%

3

+1.05V_V CCST

+1.8VS

2

+1.2V

UC1N

AD36

3.3 A

CC151

0.1U_0201_10V6K

1

@

2

+1.05V_V CCST

+VCCPLL _OC

+1.05VS_ VCCSTG

0.0 2A

PSC Side

@

CC28

1

2

0.1 2A

10U_0402_6.3V6M

CC34

10U_0402_6.3V6M

1

CC31

2

CC154

0.1U_0201_10V6K

1

@

2

1uF X1

0.1uF X1

+1.05V_V CCST

10U_0402_6.3V6M

1

1

@

CC41

2

2

0.1 9A

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC159

2

AH32
AH36

AM36

AN32

AW32

AY36
BE32
BH36

R32

Y36

BC28

BP11

BP2

BG1
BG2

BL27

BM26

BR11
BT11

WHL -U42_BGA1528

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11

RSVD1

VCCST1
VCCST2

VCCSTG1
VCCSTG2

VCCPLL_OC1
VCCPLL_OC2

VCCPLL1
VCCPLL2

+VCCPLL _OC

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 of 20

1U_0201_6.3V6M

12

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16

VCCSA2
VCCSA1
VCCSA3
VCCSA5
VCCSA6
VCCSA4
VCCSA9
VCCSA7

VCCSA8
VCCSA13
VCCSA14
VCCSA10
VCCSA11
VCCSA12
VCCSA15
VCCSA16

PSC Side

CC29

AK24
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18

BG8
BG10
BH9
BJ8
BJ9
BJ10
BK8
BK25
BK27
BL8
BL9
BL10
BL24
BL26
BM24
BN25

BP28
BP29

BE7
BG7

1

3.67 9A

+VCCSA

6A

Trace Length Match < 25 mils

VSSSA_S ENSE
VCCSA_S ENSE

+1.05VS_ VCCSTG

12

PSC Side

1U_0201_6.3V6M

CC35

VSSSA_S ENSE <46>
VCCSA_S ENSE <46>

Close to BP11 & BP2 Close to BG1 & BG2

+1.05VS_ VCCIO

10P_0402_50V8J

1

12

CC3867

B B

RF@

2

change package of 1U from 0201 to 0402

PSC SideBSC Side BSC SidePSC Side

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

CC39

1U_0201_6.3V6M

1U_0201_6.3V6M

1

12

CC40

12

CC37

CC38

@

1

CC160

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

1

CC36

1

CC161

2

2

+1.2V

10U_0402_6.3V6M

@

CC189

10U_0402_6.3V6M

1

1

CC163

CC164

2

2

Close to CPU Unde rneath CPU

+1.05VALW TO +1.05VS_VCCSTG

+VL

+1.05VAL W

1U_0201_6.3V6M

0.1U_0201_10V6K

CC174

1

12

2

@

A A

S0_C10_ GATE#

+1.05VS_ VCCIO_STG +1.05VS_ VCCSTG_R

I(Max) : 20m A(+1.05VS_VCCSTG)
RON(Max) : 6.2 mohm
V drop : 0.019 V

CC175

UC8

@

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS2296 1DNYR_WSON8

VOUT

GND

+1.05VS_ VCCSTG_R

6

5

RC455

1 2

0_0402_ 5%

+1.05VS_ VCCSTG

Compal For Lenovo

1 2

RC458 0_0402_ 5%

5

4

CPU C10 Save Power

UC9

SOC_C10 _GATE#<9>

1

CC180

0.1U_020 1_10V6K

2

SOC_C10 _GATE#

SUSP#

@

74LVC1G 08FZ4-7_X2-DFN 1410-6

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

1

A

2

B

3

GND

1 2

RC457 0_0402_ 5%@

VCC

NC

+VL

0.1U_0201_10V6K

CC178

+3VALW

CC177

0.1U_020 1_10V6K

1 2

6

5

4

Y

2017/5/3 2017/6/2

2017/5/3 2017/6/2

2017/5/3 2017/6/2

3

@

S0_C10_ GATE#

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

@

2

Deciphered Date

Deciphered Date

Deciphered Date

Close to BR11 & BT11

Close to BM26

change package of 1U from 0201 to 0402

10U_0402_6.3V6M

4.7U_0402_6.3V6M

@

1

CC47

2

+1.2V

1U_0201_6.3V6M

12

@

S0_C10_ GATE#

1

2

CC176

10U_0402_6.3V6M

10U_0402_6.3V6M

@

CC44

1

1

2

CC173

CC172

2

1U_0201_6.3V6M

12

@

+1.2V TO +VCCPLL_OC

I(Max) : 120m A(+VCCPLL_OC)
RON(Max) : 6.2 mohm
V drop : 0.019 V

UC10

1
2

7

3

4

2

@

VIN1
VIN2

VIN thermal

VBIAS

ON

TPS2296 1DNYR_WSON8

6

VOUT

5

GND

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1U_0201_6.3V6M

12

CC167

1U_0201_6.3V6M

12

CC45

CC46

@

Close to CPUUnderneath CPU

RC454 0_0402_ 5%

+VCCPLL _OC_R

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

WHL-U(8/12)Power

WHL-U(8/12)Power

WHL-U(8/12)Power

RC456

1 2

0_0402_ 5%

LA-G651P

LA-G651P

LA-G651P

12

1U_0201_6.3V6M

CC49

1 2

+VCCPLL _OC

1

1U_0201_6.3V6M

12

CC50

1

CC179

@

0.1U_020 1_10V6K

2

13 52Friday, May 18, 201 8

13 52Friday, May 18, 201 8

13 52Friday, May 18, 201 8

+VCCPLL _OC+1.2V

0.2

0.2

0.2

Saf t y s uggest i on r emove EE si de , Keep PWR s i de

+1.05VALW

12

5

1U_0201_6.3V6M

CC66

@

+1.05VALW

12

1U_0201_6.3V6M

CC56

4

3

2

1

Close to BP20Close to BV18

D D

1U_0201_6.3V6M

12

CC68

Close to BV2

+1.05VALW+1.05VALW

1

CC169

4.7U_0402_6.3 V6M

2

Close to BV12

1

CC171
10U_0402_6 .3V6M

2

+1.8VALW

Imax : 0.702A

+3VALW

Imax : 0.21A

+1.8VALW

1U_0201_6.3V6M

12

CC181

Close to CP17

C C

+3VALW

1U_0201_6.3V6M

12

CC57

@

1

@

CC79

0.1U_0201_10 V6K

2

Close to BT24

12

CC55 1U_0 201_6.3V6M

Close to CP29

+3VALW

1U_0201_6.3V6M

CC157

12

@

+3VALW

+3V_1.8V_HDA

Close to BR24

+3VALW

B B

RF@

LC4

1 2

BLM15BB221SN 1D_2P

+3V_1.8V_HDA

RF@

1

CC52

0.1U_0201_10 V6K

2

close to BP20

A A

Imax : 4.982A

Internal LDO

+DCPDSW

+1.05VALW

UC1P

BP20

VCCPRIM_1P05_1

BW16

VCCPRIM_1P05_9

BW18

VCCPRIM_1P05_10

BW19

VCCPRIM_1P05_11

BY16

VCCPRIM_1P05_12

CA14

VCCPRIM_1P05_14

CC15

VCCPRIM_1P8_1

CD15

VCCPRIM_1P8_4

CD16

VCCPRIM_1P8_5

CP17

VCCPRIM_1P8_8

CB22

VCCPRIM_3P3_4

CB23

VCCPRIM_3P3_5

CC22

VCCPRIM_3P3_6

CC23

VCCPRIM_3P3_7

CD22

VCCPRIM_3P3_8

CD23

VCCPRIM_3P3_9

CP29

VCCPRIM_3P3_10

BU15

VCCPRIM_CORE1

BU22

VCCPRIM_CORE2

BV15

VCCPRIM_CORE3

BV16

VCCPRIM_CORE4

BV18

VCCPRIM_CORE5

BV19

VCCPRIM_CORE6

BV20

VCCPRIM_CORE7

BV22

VCCPRIM_CORE8

BW20

VCCPRIM_CORE9

BW22

VCCPRIM_CORE10

CA12

VCCPRIM_CORE11

CA16

VCCPRIM_CORE12

CA18

VCCPRIM_CORE13

CA19

VCCPRIM_CORE14

CA20

VCCPRIM_CORE15

CB12

VCCPRIM_CORE16

CB14

VCCPRIM_CORE17

CB15

VCCPRIM_CORE18

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05_4

BV12

VCCPRIM_MPHY_1P05_1

BW12

VCCPRIM_MPHY_1P05_3

BW14

VCCPRIM_MPHY_1P05_4

BY12

VCCPRIM_MPHY_1P05_5

BY14

VCCPRIM_MPHY_1P05_6

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05_2

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P3_1

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05_4

BT19

VCCPRIM_1P05_5

BU18

VCCPRIM_1P05_7

BU19

VCCPRIM_1P05_8

BT22

VCCPRIM_1P05_6

BP22

VCCPRIM_1P05_2

BV14

VCCPRIM_MPHY_1P05_2

WHL-U42_ BGA1528

K12

VCCOPC1

K14

VCCOPC2

K15

VCCOPC3

K17

VCCOPC4

K18

VCCOPC5

K20

VCCOPC6

L25

VCCOPC7

M24

VCCOPC8

M26

VCCOPC9

P24

VCCOPC10

P26

VCCOPC11

R24

VCCOPC12

R25

VCCOPC13

R26

VCCOPC14

W25

VCC_OPC_1P8_2

V24

VCC_OPC_1P8_1

Y25

VCC_OPC_1P8_4

Y24

VCC_OPC_1P8_3

WHL-U42_ BGA1528

VCCOPC and VCCEOPIO for CFL U43e only

UC1O

16 of 20

VCCEOPIO_SENSE
VSSEOPIO_SENSE

15 of 20

VCCPRIM_3P3_3

VCCPRIM_1P05_13

VCCPRIM_1P05_3

VCCAPLL_1P05_3

VCCA_BCLK_1P05

VCCAPLL_1P05_1

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24_2
VCCDPHY_1P24_4

VCCDPHY_1P24_1
VCCDPHY_1P24_3

VCCDPHY_EC_1P24

VCCDSW_3P3_2

VCCA_19P2_1P05

VCCPRIM_1P8_2
VCCPRIM_1P8_3
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_9

VCCPRIM_3P3_2

VCCPRIM_3P3_1

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

VCCEOPIO1
VCCEOPIO2
VCCEOPIO3
VCCEOPIO4
VCCEOPIO5
VCCEOPIO6
VCCEOPIO7
VCCEOPIO8

VCCRTC

DCPRTC

AA24
AA26
AB25
AC24
AC25
AC26
AD24
AD26

V25
T25

CB16

BR23

BY20
BP24

BR20

BT12

BP14

BR14

BU12

CP5

BY24
CA24

BY23
CA23
CP25

BT23

BR12

CC18
CC19
CD18
CD19
CP23

BW23

BP23

CB36
CB35

+1.05VALW

+3VALW

+DCPRTC

Intenal LDO

VCCDPHY_EC_1P24

Imax : 0.702A

+3VL_RTC

@

1 2

CC62 1U_0201_ 6.3V6M

Close to BP24

+VCCDPHY_1.24V

Close to CP25

1 2

CC182 4.7U _0402_6.3V6M

+1.05VALW

+1.8VALW

PD_INT# < 30,34>

+1.8VALW

1U_0201_6.3V6M

CC59

12

@

Close to CP23

RTC Bat t er y

+3VL_RTC +RTCBATT

W=20mil s

1 2

RC90 0 _0402_5%

1U_0201_6.3V6M

12

CC82

Close to BR23

+1.05VALW

CC3868

10P_0402_50V8J

1U_0201_6.3V6M

CC155

1 2

R3248 0_0201_ 5%CNVi@

1

RF@

2

Close to BP14

+VCCDPHY_1.24V

12

Close to CP5

VCCDPHY_EC_1P24

When CNVi is not used in the design:
VCCDPHY_1P24 pin shall be disconnected from the VCCLDOSRAM_IN_1P24 pin.
The decoupling capacitor shall remain connected to the VCCDPHY_1P24 pin.

Security Classific ation

Security Classific ation

Security Classific ation

Issued Date

Issued Date

Compal For Lenovo

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/5/3 2017/6/2

2017/5/3 2017/6/2

2017/5/3 2017/6/2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

WHL-U(9/12)Power

WHL-U(9/12)Power

WHL-U(9/12)Power

Size D ocument Number R ev

Size D ocument Number R ev

Size D ocument Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

LA-G651P

LA-G651P

LA-G651P

14 5 2Friday, May 18, 2018

14 5 2Friday, May 18, 2018

1

14 5 2Friday, May 18, 2018

0.2

0.2

0.2

5

+VCCCOR E +VCCCOR E

UC1L

AN9

VCCCORE5

AN10

VCCCORE1

D D

C C

AN24
AN26
AN27

AP2

AP9
AP24
AP26

AR5

AR6

AR7

AR8
AR10
AR25
AR27

AT9
AT24
AT26

AU5

AU6

AU7

AU8

AU9
AU24
AU25
AU26
AU27

AV2

AV5

AV7
AV10
AV27

AW5
AW6
AW7
AW8
AW9

AW10

BB9
BC24

AY9
BB24

WHL -U42_BGA1528

VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE6
VCCCORE9
VCCCORE7
VCCCORE8
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE19
VCCCORE17
VCCCORE18
VCCCORE24
VCCCORE25
VCCCORE26
VCCCORE27
VCCCORE28
VCCCORE20
VCCCORE21
VCCCORE22
VCCCORE23
VCCCORE30
VCCCORE32
VCCCORE33
VCCCORE29
VCCCORE31
VCCCORE39
VCCCORE40
VCCCORE41
VCCCORE42
VCCCORE43
VCCCORE34

RSVD3
RSVD4
RSVD1
RSVD2

SVID ALERT

B B

12 of 20

+1.05V_V CCST

12

VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE44
VCCCORE45
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE46
VCCCORE47
VCCCORE51
VCCCORE52
VCCCORE56
VCCCORE57
VCCCORE58
VCCCORE59
VCCCORE53
VCCCORE54
VCCCORE55
VCCCORE63
VCCCORE64
VCCCORE60
VCCCORE61
VCCCORE62
VCCCORE69
VCCCORE65
VCCCORE66
VCCCORE67
VCCCORE68
VCCCORE70
VCCCORE73
VCCCORE71
VCCCORE72
VCCCORE74

VCC_SENSE
VSS_SENSE

VIDALERT#

AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27

AN6
AN5

AA3

AA1

VIDSCK

AA2

VIDSOUT

Y3

RSVD5

BG3

VCCSTG1

Place the PU
resistors close to CPU

RC94
56_0402 _5%

4

SOC_SVID_ ALERT#

VR_SVID_C LK

VR_SVID_D ATA

VCCCORE _SENSE <4 6>

VSSCORE _SENSE <46>

VR_SVID_C LK <46>

+1.05VS_ VCCSTG

3

Trace Length Match < 25 mils

+VCCCOR E

2

+VCC_GT +VCC_GT

UC1M

A5

VCCGT8

A6

VCCGT9

A8

VCCGT10

A11

VCCGT1

A12

VCCGT2

A14

VCCGT3

A15

VCCGT4

A17

VCCGT5

A18

VCCGT6

A20

VCCGT7

AA9

VCCGT11

AB2

VCCGT13

AB8

VCCGT14

AB9

VCCGT15

AB10

VCCGT12

AC8

VCCGT16

AD9

VCCGT17

AE8

VCCGT19

AE9

VCCGT20

AE10

VCCGT18

AF2

VCCGT22

AF8

VCCGT23

AF10

VCCGT21

AG8

VCCGT24

AG9

VCCGT25

AH9

VCCGT26

AJ8

VCCGT28

AJ10

VCCGT27

AK2

VCCGT29

AK9

VCCGT30

AL8

VCCGT32

AL9

VCCGT33

AL10

VCCGT31

AM8

VCCGT34

B3

VCCGT39

B4

VCCGT40

B6

VCCGT41

B8

VCCGT42

B11

VCCGT35

B14

VCCGT36

B17

VCCGT37

B20

VCCGT38

C2

VCCGT49

C3

VCCGT51

C6

VCCGT52

C7

VCCGT53

C8

VCCGT54

C11

VCCGT43

C12

VCCGT44

C14

VCCGT45

C15

VCCGT46

C17

VCCGT47

C18

VCCGT48

C20

VCCGT50

D4

VCCGT62

D7

VCCGT63

D11

VCCGT55

D12

VCCGT56

D14

VCCGT57

Y10

VCCGT119

WHL -U42_BGA1528

VCCGT_SENSE
VSSGT_SENSE

13 of 20

VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT64
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT95
VCCGT96
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT98

VCCGT97
VCCGT100
VCCGT101

VCCGT99
VCCGT102
VCCGT104
VCCGT105
VCCGT106
VCCGT103
VCCGT107
VCCGT108
VCCGT109
VCCGT111
VCCGT112
VCCGT110
VCCGT114
VCCGT113
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT120

D15
D17
D18
D20
E4
F5
F6
F7
F8
F11
F14
F17
F20
G11
G12
G14
G15
G17
G18
G20
H5
H6
H7
H8
H11
H12
H14
H15
H17
H18
H20
J7
J8
J11
J14
J17
J20
K2
K11
L7
L8
L10
M9
N7
N8
N9
N10
P2
P8
R9
T8
T9
T10
U8
U10
V2
V9
W8
W9
Y8

VCCGT_S ENSE

E3

VSSGT_S ENSE

D2

1

VCCGT_S ENSE <4 6>
VSSGT_S ENSE <46>

Trace Length Match < 25 mils

SOC_SVID_ ALERT#

SVID DATA

VR_SVID_D ATA

A A

5

1 2

RC95 220_ 0402_5%

+1.05V_V CCST

Place the PU
resistors close to CPU

12

RC96
100_040 2_1%

VR_ALER T# <46>

VR_SVID_D ATA <46>

Compal For Lenovo

4

(To VR)

(To VR)

Security Classification

Security Classification

Security Classification

2017/5/3 2017/6/2

2017/5/3 2017/6/2

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/5/3 2017/6/2

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

WHL-U(10/12)Power,SVID

WHL-U(10/12)Power,SVID

WHL-U(10/12)Power,SVID

LA-G651P

LA-G651P

LA-G651P

15 52Friday, May 18, 201 8

15 52Friday, May 18, 201 8

15 52Friday, May 18, 201 8

1

0.2

0.2

0.2