Lenovo LE4 Schematics

BOM MARK E@ EXT VGA POPULATE I@ INV VGA POPULATE F@ FIR MODULE POPULATE 4@ 4401 10/100M POPULATE 5@ 5788 1G POPULATE

A A

VGA NVIDA G72M

16M*16(128MB)

PG 18,19,20,21

EXT_CRT

CRT port

LCD Panel

S-VIDEO

B B

PG 23

PG 22

PG 23

SWITCH

CIRCUIT

USB PORT 0,2,6

(64 Bit B/W)

(Bank*4)

EXT_LVDS EXT_TV-OUT

PG 31

HyperThansport I/O BUS

16X PCI-E

INT_CRT INT_LVDS INT_TV-OUT

USB 2.0

32.768KHz

CPU Yonah/Merom

31W/35W

(478 Micro-FCPGA)

Link 16x16

NORTH BRIDGE

Calistoga

945PM945GM 940GML//

INTEGRADED VGA FUNCTION

1466 BGA

DMI LINK

2X PCI-E

PG 6,7,8,9,10,11

PG 4,5

CPU THERMAL SENSOR

SBLINKCLK, SBLINKCLK#

NBSRCCLK, NBSRCCLK#

DDRII 266,333 MHz

33MHZ, 3.3V PCI

PG 5

CPUCLK, CPUCLK#

HTREFCLK

OSC14M

DDRII-SODIMM1

DDRII-SODIMM2

NBSRCCLK, NBSRCCLK#

LE4 BLOCK DIAGRAM

Yonah /Calistoga /ICH-7m

14.318MHz

SYSTEM POWER MAX1993 (1.2V/NB_CORE/1.25V)

CLOCK GEN

IDTXXX/ ICSXXXX 56pins

PG 3

PG 16,17

CPU CORE MAX8771 POWER VCORE 1.2V /44A

SYSTEM MAX8734 POWER(3/5V)

SYSTEM POWER MAX8632 (1.8VSUS/0.9V SMDDR_VREF)

BATT CHARGER MAX8724

DISCHARGE

PG 41

PG 38

PG 39

PG 36

PG 35

PG 40

ICH7-M

SATA-HDD

PG 32

PATA-CDROM

PG 32

652 BGA

ATA 66/100/133

PG 12,13,14,15

Azalia

Conexant Audio

CX20549-12

C C

32.768KHz

3.3V LPC, 33MHz

LPC

PCLK_E

PG 28

MIC IN

PG 28

LAN

BCM4401/5788

PG 33

24.576MHz

CARDREADER / IEEE 1394 CONTROLLER/CF

TI 8412

PG 24,25

25MHz

IO/B

CON.

SIO (87383)

PG 26

IR module

PG 26

FAN

PG 31

PC87551L

Touchpad

Keyboard

PG 26PG 31

PG 30

FLASH

Express Card x1 MINI PICE CARD

USB PORT 1

PG 30

PG 27

MAX9755

PG 29

SPEKER

PG 29

AMP

INT_SPK

PG 29

MDC CONN

PG 27

WIRE

IO/B

RJ11 JACK

PG 24

RJ45 JACK

PG 34

3 IN 1

CARD READER SD, SM, MS,

PG 25

PCB STACK UP

LAYER 1 : TOP LAYER 2 : GND

CARDBUS SOCKET

PG 25

1394 CONN

PG 24

LAYER 3 : IN1

D D

LAYER 4 : VCC LAYER 5 : IN2 LAYER 6 : IN3 LAYER 7 : GND LAYER 8 : BOT

PROJECT : LE4

Size Document Number Rev

BLOCK DIAGRAM

Date: Sheet

BLOCK DIAGRAM

PROJECT : LE4

Quanta Computer Inc.

142Wednesday, November 16, 2005

Board Stack up Description

PCB Layers

A A

Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6 Layer 7 Layer 8

Power On Sequencing Timing Diagram

VID VR_ON Vcc-core

B B

CPU_UP Vccp Vccp_UP

TOP(Component,Other) Ground Plane IN1 Power Plane IN2 IN3 Ground Plane BOTTOM

Tsft_star_vcc

Tboot

Tvccp_up

Vboot Tboot-vid-tr

Tcpu_up

Vid

Voltage Rails

VCC_CORE VCCP SMDDR_VTERM

RVCC1.5 RVCC3

VCC1.5 VCC2.5 VCC3 VCC5

1.8VSUS 3VSUS X 5VSUS

3VPCU 5VPCU 9VPCU

Core voltage for Processor Core voltage for CPU / NB

0.9V for DDR2 Termination voltage

ON S0~S2

ON S3

X X X

X RVCC_ON X

X X X X

X X

ON S4

ON S5

Control signal

VR_ON VR_ON

MAINON

X X

RVCCD

MAIND MAINON MAIND MAIND

X X X

SUSON SUSD SUSD

XVLX X X

5VPCU

0.726V~0.94V

Vccgmch

Tgmch_pwrgd

Tcpu_pwrgd

Vcc,boot

ACIN POWER ON TIMING

ACIN

5VPCU/3VPCU

NBSWON#

PWRBTN#

PLTRST#\PCIRST#

S5_ON

RSMRST#

SUSB#,SUSC#

SUSON

MAINON

VSUS,VCC

VR_ON

VCCP/1.05V

VCORE_CPU

CLK_EN#

PWROK

99ms < t 214

To ICH7

From 87541

To ICH7

From ICH7

From 87541

To clock generator

To GMCH/other PCI device

Voltage Rails ON S0~S1

VCC_CORE GMCH_VTT SMDDR_VTERM

SMDDR_VREF

GMCH_1.5V

1.8VSUS 1.8V for DDR II voltage X +2.5V X

3VPCU X X X X VL 3VSUS +3V

5VPCU 5VSUS +5V

VIN POWER SOURCE

Core voltage for Processor Core voltage for GMCH 1.05V

0.9V for DDR II Termination voltage X MAINON

0.9V for DDR II Reference Voltage MAINON

AD25 PIRQ B/C/DREQ1# / GNT1#PCI7402

ON S3 ON S4

X X MAINON

X X

XX X

X XXX X X X

XXXX

InterruptsREQ# / GNT#PCI DEVICE IDSEL#

ON S5

Control signal

VRON

MAINON SUSON MAINON

SUSON MAINON

VL SUSON MAINON

GMCHPWRGD CLK_ENABLE# IMVP4_PWRGD

Dothan Power-up Timing Specifications

RESET#

BCLK

C C

PWRGOOD

VCC

VID[5:0]

VCCP

Ta=VCC and VCCP asseration to VID[5:0] vaild Tb=VID[5:0] stable to VCC vaild Tc=BCLK stable to PWRGOOD assertion Td=PWRGOOD to RESET# de-assertion time Te=Vcc,boot vaild to PWRGOOD assertion time

D D

H_CPURST#

2ms

From ICH7 to CPU

Form GMCH to CPU

Size Document Number Rev

Date: Sheet

Date: Sheet of

PROJECT : LE4

Quanta Computer Inc.

System Information

242Wednesday, November 16, 2005

FSC FSB FSA CPU SRC PCI 1 0 1 100 100 33 0 0 1 133 100 33

Place these termination to close CK410M. Cause those Pin-out is for Current-Mode.

0 1 1 166 100 33

R199 49.9/F_4R199 49.9/F_4

0 1 0 200 100 33

A A

0 0 0 266 100 33 1 0 0 333 100 33 1 1 0 400 100 33 1 1 1 RSVD 100 33

CLK_EN# PM_STPPCI#

PM_STPCPU# TI_CLK48M CLKUSB_48

CGCLK_SMB

CGDAT_SMB

R195 10_4R195 10_4 R190 10_4R190 10_4

SMbus address D2

LE4 A:

Changed new function Solved sometimes can't power on

+3VRUN

CLK_EN#(14,37)

PM_STPPCI#(14) PM_STPCPU#(14) TI_CLK48M(25)

CLKUSB_48(14)

CPU_MCH_BSEL0(4,7) CPU_MCH_BSEL1(4,7) CPU_MCH_BSEL2(4,7)

LE4 B:

B B

Connect ICH6 SMB

These are for backdrive issue

C C

PCLK_SMB(14,33)

Add R566

R566

pull high

10K_4

with FSA

FSA

R567

R567 *10K_4

*10K_4

PDAT_SMB

PCLK_SMB CGCLK_SMB

+3VRUN

Q32

3 1

RHU002N06

+3VRUN

Q33

3 1

RHU002N06

DOT96(7) DOT96#(7)

RP33

RP33 4P2R-S-10K

4P2R-S-10K

CGDAT_SMB

CT_0229: Change MOS to RHU002N06 due to layout concern.

I@4P2R-S-33

4 2

RP35

Connect DDR Module's SMB

CGDAT_SMB (16,17,27)PDAT_SMB(14,33)

CGCLK_SMB (16,17,27)

C323 33P_4C323 33P_4

14.318MHZ

C324 33P_4C324 33P_4

1 2 1 2

R193 8.2K/F_4R193 8.2K/F_4

1 2

R184 8.2K/F_4R184 8.2K/F_4

1 2

BG614318081

R201 475/F_4R201 475/F_4

Iref=5mA,

R_DOT96

R_DOT96#

Ioh=4*Iref

CT_0505: Change footprint to TSSOP56-8_1-5 from TSSOP56-240

Bypass CAPs need to follow Bypass CAP. Routing Rule, no vias between CAP to CHIPSET VCC Pin or GND.

120 ohms@100Mhz

L31

+3VRUN

1 2

HB-1T2012-121JT_8

XIN

<500mil

XOUT

VDDREF_CR

CLKVDD CLKVDD1

CLKVDD

VDD48_CR

1 2

FSA FSB FSC

IREF

C387

0.047U/10V_4

R204 2.2R204 2.2

1 2

50 49

10 55 54

46 47

12 16 53

48 42

21 28 34

11 39

14 15

0.047U/10V_4

C573

0.047U/10V_4

VDDA_CR

U17

XTAL_IN XTAL_OUT

VTT_PWRGD#/PD# PCI_STOP# CPU_STOP#

SCLK SDATA

FSA/USB_48 FSB/TEST_MODE FSC/TEST_SEL

VDD_REF VDD_CPU

VDD_PCI_1

VDD_PCI_2 VDD_SRC0

VDD_SRC1 VDD_SRC2

VDD_48 IREF

DOT96 DOT96#

C383

0.047U/10V_4

CK-410M

GND_REF

GND_48

0.047U/10V_4

C579

C578

VDDA

CPU2#_ITP/SRC7#

GND_PCI_26GND_SRC29GND_CPU

GND_PCI_1

+3VRUN

CLKVDD

C388

4.7U/10V_8

VDDA_CR

C393

4.7U/10V_8

VSSA

CPU2_ITP/SRC7

REF

CPU0

CPU0#

CPU1

CPU1#

SRC6

SRC6#

SRC5

SRC5#

SRC4

SRC4#

SRC3

SRC3#

SRC2

SRC2#

SRC1

SRC1#

SRC0

SRC0#

PCI5 PCI4 PCI3 PCI2

PCIF1

PCIF0/ITP_EN

ICS954206AGLFT

250mA ( MAX. )

120 ohms@100Mhz

L25

L25 HB-1T2012-121JT_8

HB-1T2012-121JT_8

14M_REF

R_HCLK_CPU

R_HCLK_CPU#

R_HCLK_MCH

R_HCLK_MCH#

R_PCIE_VGA

R_PCIE_VGA#

35 33

32 31

R_MCH_3GPLL# CLK_MCH_3GPLL#

R_PCIE_SATA

R_PCIE_SATA#

R_PCIE_ICH

24 25

R_PCIE_MINI

R_PCIE_MINI#

23 19

R_DREFSSCLK

R_DREFSSCLK#

R_PCLK_LAN PCLK_LAN

R_PCLK_LPC

R_PCLK_LPC_DEBUG

R_PCLK_PCM

R_PCLK_SIO

PCIF0

RP34

RP39

RP43

RP47

RP48

RP44

RP40

RP37

Tie to VCC (Logic 1) is for ITP using. Tie to GND (Logic 0) is for PCIE using.

C351

0.047U/10V_4

R177 2.2R177 2.2

1 2

R191 1R_6R191 1R_6

1 2

LE4 A:

Del this function desgin

1 2

R200 49.9/F_4R200 49.9/F_4

1 2

R196 49.9/F_4R196 49.9/F_4

1 2

R197 49.9/F_4R197 49.9/F_4

1 2

4 2

2 4

R185 33_4R185 33_4

C374

0.047U/10V_4

4P2R-S-33

1 3

4P2R-S-33

1 3

4P2R-S-33

3 1

4P2R-S-33

1 3

4P2R-S-33

1 3

4P2R-S-33

1 3

4P2R-S-33

1 3

I@4P2R-S-33 R186 33_4R186 33_4 R181 33_4R181 33_4 R178 33_4R178 33_4 R182 33_4R182 33_4 R194 33_4R194 33_4

1 2

R189 *10K_4R189 *10K_4

1 2

R183 10K_4R183 10K_4

1 2

I@4P2R-S-33

1 2 1 2 1 2 1 2 1 2

C565

0.047U/10V_4

C340

4.7U/10V_8

C564

0.047U/10V_4

CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_MCH_3GPLLR_MCH_3GPLL

CLK_PCIE_SATA CLK_PCIE_SATA#

CLK_PCIE_ICH CLK_PCIE_ICH#R_PCIE_ICH#

CLK_PCIE_MINI CLK_PCIE_MINI#

DREFSSCLK DREFSSCLK#

PCLK_LPC PCLK_LPC_DEBUG PCLK_PCM PCLK_541

PCLK_ICH

CLKVDD1

C326

4.7U/10V_8

VDD48_CR

VDDREF_CR

+3VRUN

R192 33_4R192 33_4

1 2

R188 33_4R188 33_4

1 2

CLK_CPU_BCLK (4) CLK_CPU_BCLK# (4)

CLK_MCH_BCLK (6) CLK_MCH_BCLK# (6)

CLK_PCIE_VGA (18) CLK_PCIE_VGA# (18)

CLK_PCIE_3GPLL (7) CLK_PCIE_3GPLL# (7)

CLK_PCIE_SATA (12) CLK_PCIE_SATA# (12)

CLK_PCIE_ICH (13) CLK_PCIE_ICH# (13)

CLK_PCIE_MINI (27) CLK_PCIE_MINI# (27)

DREFSSCLK (7) DREFSSCLK# (7)

PCLK_LAN (33) PCLK_LPC (26) PCLK_LPC_DEBUG (27) PCLK_PCM (24) PCLK_541 (30)

PCIF1

1:100 Mhz

0:96 Mhz

PCLK_ICH (13)

CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_PCIE_MINI CLK_PCIE_MINI#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_PCIE_SATA CLK_PCIE_SATA#

CLK_PCIE_ICH CLK_PCIE_ICH#

DREFSSCLK DREFSSCLK#

DOT96 DOT96#

C366

C366 *10P_4

*10P_4

0816a

RP42 49.9_4P2RRP42 49.9_4P2R

RP41 49.9_4P2RRP41 49.9_4P2R

RP46 49.9_4P2RRP46 49.9_4P2R

3 3

RP49 49.9_4P2RRP49 49.9_4P2R

1 3

RP45 49.9_4P2RRP45 49.9_4P2R

1 3

RP38 I@49.9_4P2RRP38 I@49.9_4P2R

1 3

RP36 I@49.9_4P2RRP36 I@49.9_4P2R

2 4

4 2

2 4

4 2

C361

C361 *10P_4

*10P_4

14M_SIO (26)

14M_ICH (14)

PCLK_LAN PCLK_PCM PCLK_541

PCLK_LPC_DEBUG

PCLK_LPC PCLK_ICH

C359 *10P_4C359 *10P_4

1 2

C432 *10P_4C432 *10P_4

1 2

C566 *10P_4C566 *10P_4

1 2

C350 *10P_4C350 *10P_4

1 2

C355 *10P_4C355 *10P_4

1 2

C442 *10P_4C442 *10P_4

1 2

LE4 A:

Add Cap 10p reserve for EMI E-mail 093020051211

Place these termination to close CK410M. Cause those Pin-out is for Current-Mode.

D D

PROJECT : LE4

Size Document Number Rev

Date: Sheet

CLOCK GENERATOR

PROJECT : LE4

Quanta Computer Inc.

342Tuesday, March 14, 2006

H_A#[31:3](6)

A A

H_ADSTB#0(6) H_REQ#[4:0](6)

B B

H_STPCLK#(12)

LE4 A:

Modfiy circuit

C C

H_A#[31:3]

H_ADSTB#1(6)

H_A20M#(12) H_FERR#(12)

H_IGNNE#(12)

H_INTR(12)

H_NMI(12)

H_SMI#(12)

T188T188 T187T187 T189T189 T186T186 T44T44 T48T48 T49T49 T47T47 T59T59 T51T51

T208T208

H_STPCLK#

TP_A32# TP_A33# TP_A34# TP_A35# TP_A36# TP_A37# TP_A38# TP_A39# TP_APM0#

TP_HFPLL

XDP_TMS

XDP_TDI

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

R147 54.9/F_4R147 54.9/F_4

R149 54.9/F_4R149 54.9/F_4

M3 M1

W3 W5

AA1 AA4 AB2 AA3

B25

L4 K5 N2

J1 N3 P5 P2 L1 P4 P1 R1 L2

K3 H2 K2

J3 L5

Y2 U5 R3

U4 Y5 U2 R4 T5 T3

Y4 Y1

V4 A6

A5 C4

D5 C6 B4 A3

N5 T2 V3 B2 C3

XDP PU_R < 0.2"

XDP_BPM#5

Why BMP5 need PH ?

D D

XDP_TCK

XDP_TRST#

R145 54.9/F_4R145 54.9/F_4

R146 54.9/F_4R146 54.9/F_4

R148 54.9/F_4R148 54.9/F_4

U38A

A[3]# A[4]# A[5]# A[6]#

ADDR GROUP 0

A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01]# RSVD[02]# RSVD[03]# RSVD[04]# RSVD[05]# RSVD[06]# RSVD[07]# RSVD[08]# RSVD[09]# RSVD[10]#

RSVD[11]#

PZ47903-2741-01

+1.05V

1 3

Q13

Q13 *MMBT3904

*MMBT3904

ADS#

BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

CONTROL

INIT#

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT

THERMDA

THERMDC

THERMTRIP#

THERMH CLK

BCLK[0] BCLK[1]

RSVD[12]#

RSVD[13]# RSVD[14]# RSVD[15]# RSVD[16]#

RESERVED

RSVD[17]# RSVD[18]# RSVD[19]# RSVD[20]#

+1.05V

+3V_S5

R223

R223 *1K_4

*1K_4

R209

R209 *10K_4

*10K_4

THERM_CPUDIE_L#PM_THRMTRIP#

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 B1

H_RS#0

H_RS#1

H_RS#2

G3 G2

G6 E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1 AC5 AA6 AB3 AB5 AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

A25

PM_THRMTRIP#

A22 A21

TP_EXTBREF

T22

TP_SPARE0

TP_SPARE1

TP_SPARE2

TP_SPARE3

TP_SPARE4

AF1

TP_SPARE5TP_APM1#

D22

TP_SPARE6

C23

TP_SPARE7

C24

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

T58T58

H_ADS# (6) H_BNR# (6) H_BPRI# (6)

H_DEFER# (6) H_DRDY# (6) H_DBSY# (6)

H_BREQ#0 (6)

H_INIT# (12) H_LOCK# (6)

H_CPURST# (6)

H_TRDY# (6) H_HIT# (6)

H_HITM# (6)

T70T70 T67T67 T64T64 T65T65 T55T55

T228T228

CLK_CPU_BCLK (3) CLK_CPU_BCLK# (3)

T224T224

T57T57 T61T61 T53T53 T190T190 T193T193 T76T76 T77T77 T207T207

H_RS#[2:0] (6)

LE4 A:

Modfiy circuit

T191T191

H_THERMDA (5)

H_THERMDC (5)

PM_THRMTRIP# (7,12)

T75T75

Use 1% R

XDP_TCK PD 27.4/1% ? XDP_TRST PD 510ohm /5% ? XDP_TDI PU 150ohm /1.05V XDP_TMS PU 39.2/1%? XDP_TDO PU 54.9ohm? For ITP700

LE4 B:

del R463 in BOM

R463

*0_4

+1.05V

R458

R458 56/F_4

56/F_4

H_D#[63:0](6)

T195T195

T56T56

+1.05V

R198

R198 75_4

75_4

XDP PU_R < 0.2"

+1.05V

R468

R468 1K/F_4

1K/F_4

20/15mils

R467

R467 2K/F_4

2K/F_4

Layout note: 0.5" max for GTLREF

H_PROCHOT#

THERM_CPUDIE# (30)

+1.05V (5,6,7,9,10,12,15,38,40)

Near to MCH <500mils

H_D#[63:0]

H_DSTBN#0(6) H_DSTBP#0(6) H_DINV#0(6)

H_D#[63:0]

H_DSTBN#1(6) H_DSTBP#1(6) H_DINV#1(6)

H_GTLREF

R213

R213 R212

R212

CPU_MCH_BSEL0(3,7) CPU_MCH_BSEL1(3,7) CPU_MCH_BSEL2(3,7)

LE4 A:

Modify circuit

+1.05V

R455

R455 *330_4

*330_4

1 3

Q10

Q10 *MMBT3904

*MMBT3904

H_D#0

E22

H_D#1

F24

H_D#2

E26

H_D#3

H22

H_D#4

F23

H_D#5

G25

H_D#6

E25

H_D#7

E23

H_D#8

K24

H_D#9

G24

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25 H23 G22

J26

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

M24

N25

M26

AD26

*1K_4

C26

51_4

D25

B22 B23 C21

LE4 B:

Change netname

PH_PROCHOT# (37)

FANLESS#(30)

U38B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10 D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF

TEST1 TEST2

BSEL[0] BSEL[1] BSEL[2]

PZ47903-2741-01

DATA GRP 0 DATA GRP 1

MISC

DATA GRP 2

DSTBN[2]# DSTBP[2]#

DINV[2]#

DATA GRP 3

DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

PWRGOOD

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

SLP#

PSI#

XDP_DBRESET#

AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23

AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20

R26 U26 U1 V1

E5 B5 D24 D6 D7 AE6

H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

R454 *54.9/F_4R454 *54.9/F_4

R235 0/F_4R235 0/F_4

H_D#32

AA23

LE4 B:

+5VRUN

R456

R456 100K_4

100K_4

Q12

Q12 DTC144EUA

DTC144EUA

1 3

LE4 A:

Add new circuit with

H_D#[63:0]

H_DSTBN#2 (6) H_DSTBP#2 (6) H_DINV#2 (6)

25/25mils

H_DSTBN#3 (6) H_DSTBP#3 (6) H_DINV#3 (6)

R465

R465 R46454.9/F_4 R46454.9/F_4 R15127.4/F_4 R15127.4/F_4 R15054.9/F_4 R15054.9/F_4

ICH_DPRSTP# (12,37) H_DPSLP# (12)

H_CPUSLP# (6,12) PSI# (37)

27.4/F_4

H_D#[63:0]

TO VRD

Add R235 in BOM

Q11

Q11 E@2N7002K

E@2N7002K

H_PROCHOT#

Trcae width : ? placement <0.5"

H_PWRGD is CMOS driving by ICH

+1.05V

Q34

Q34 2N7002K

2N7002K

SYS_RST# (14)

THERMATRIP_VGA# (19)

H_DPWR# (6) H_PWRGD (12)

Size Document Number Rev

Date: Sheet

LE4 A:

Modify circuit

PROJECT : LE4

Quanta Computer Inc.

Yonah/Merom (Host)

442Tuesday, March 14, 2006

A A

B B

LE4 C:

+3VRUN

Q16

2N7002K

MBDATA(30,35)

MBCLK(30,35)

C C

THERM_ALERT#(14)

D D

THERM_ALERT#

+3VRUN

Q15

Q15 2N7002K

2N7002K

LM86_SMD

LM86__SMC

R232

R232 10K_4

10K_4

+1.05V

C379

0.1U_4

LM86_SMD (19)

LM86_SMC (19)

R231

R231 10K_4

10K_4

LM86__SMC LM86_SMD

U38C

VCC[001]

C316

0.1U_4

VCC_CORE

+3VRUN

R211

R211 10K_4

10K_4

C317

C381

0.1U_4

CH6222M9A01 22UF/10V/X5R

C319

C319 22U_8

22U_8

C335

C335 22U_8

22U_8

C354

C354 22U_8

22U_8

C360

C360 22U_8

22U_8

C382

C382 22U_8

22U_8

C345

C345 22U_8

22U_8

C362

C362 22U_8

22U_8

C329

C329 22U_8

22U_8

C368

C368 22U_8

22U_8

C328

C328 22U_8

22U_8

C371

C371 22U_8

22U_8

C369

C369 22U_8

22U_8

C334

C334 22U_8

22U_8

C346

C346 22U_8

22U_8

C375

C375 22U_8

22U_8

C365

C365 22U_8

22U_8

change to 0805

CRB use 8.2k PH

25mils

U19

SCLK

SDA

ALERT#

OVERT#

MAX6657/GMT-781

ADDRESS: 98H

C286

0.1U_4

VCC DXP DXN

GND

C285

0.1U_4

C372

C372 22U_8

22U_8

C370

C370 22U_8

22U_8

C380

C380 22U_8

22U_8

C357

C357 22U_8

22U_8

C332

C332 22U_8

22U_8

C376

C376 22U_8

22U_8

C373

C373 22U_8

22U_8

C356

C356 22U_8

22U_8

R220

R220 200_4

200_4

LM86VCC

1 2 3 5

LE4 C:

C363

C363 22U_8

22U_8

C378

C378 22U_8

22U_8

C339

C339 22U_8

22U_8

C349

C349 22U_8

22U_8

C377

C377 22U_8

22U_8

C352

C352 22U_8

22U_8

C337

C337 22U_8

22U_8

C331

C331 22U_8

22U_8

LE4 B:

Solve can't power on isuue So change R220 pull high and R211 pull high to thermal circuit.(12/12/2005)

C406

0.1U_4

H_THERMDA

C400

C400 2200P/50V_4

2200P/50V_4

H_THERMDC

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

VCC[010]

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

VCC[033]

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

VCC[042]

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

PZ47903-2741-01

10/20mils

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCSENSE

VSSSENSE

add hardware protect

Unstall R267 , Q28 , Q26 for Intel sighting -> CPU thermal die bug /0506

AB20

VCC[68]

AB7

VCC[69]

AC7

VCC[70]

AC9

VCC[71]

AC12

VCC[72]

AC13

VCC[73]

AC15

VCC[74]

AC17

VCC[75]

AC18

VCC[76]

AD7

VCC[77]

AD9

VCC[78]

AD10

VCC[79]

AD12

VCC[80]

AD14

VCC[81]

AD15

VCC[82]

AD17

VCC[83]

AD18

VCC[84]

AE9

VCC[85]

AE10

VCC[86]

AE12

VCC[87]

AE13

VCC[88]

AE15

VCC[89]

AE17

VCC[90]

AE18

VCC[91]

AE20

VCC[92]

AF9

VCC[93]

AF10

VCC[94]

AF12

VCC[95]

AF14

VCC[96]

AF15

VCC[97]

AF17

VCC[98]

AF18

VCC[99]

VCC[100]

AF20 V6

G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26

VCCA

AD6

VID[0]

AF5

VID[1]

AE5

VID[2]

AF4

VID[3]

AE3

VID[4]

AF2

VID[5]

AE2

VID[6]

AF7 AE7

H_THERMDA (4)

H_THERMDC (4)

VCC_COREVCC_CORE

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

VCCSENSE VSSSENSE

Use 1% R

SYS_SHDN#

+1.05V VCC_CORE +1.5V

H_VID0 (37) H_VID1 (37) H_VID2 (37) H_VID3 (37) H_VID4 (37) H_VID5 (37) H_VID6 (37)

+1.05V (4,6,7,9,10,12,15,38,40) VCC_CORE (37,40) +1.5V (7,9,10,13,15,27,38,40)

+1.05V

C289

ESR :12m ohm

330U/2.5V/ESR-9/POS

+1.5V

VCC_CORE

R167

R167 100_4

100_4

Connect to PWM , special layout

R162

R162 100_4

100_4

LE4 C:

Del R208

R208 *0_6R208 *0_6

+3VRUN

R224

R224 *1M/F_4

*1M/F_4

Q14

Q14 *2N7002K

*2N7002K

+1.5V

C401

0.01U_4

VCCSENSE (37) VSSSENSE (37)

+3VRUN

C408

C408 *0.1U_4

*0.1U_4

C402

C402 10U/10V_8

10U/10V_8

R214

R214 *10K_4

*10K_4

A8 A11 A14 A16 A19 A23 A26

B8 B11 B13 B16 B19 B21 B24

C8 C11 C14 C16 C19

C2 C22 C25

D8 D11 D13 D16 D19 D23 D26

E8 E11 E14 E16 E19 E21 E24

F8 F11 F13 F16 F19

F2 F22 F25

G1 G23 G26

H6 H21 H24

J5 J22 J25

K4 K23 K26

L6 L21 L24

M5 M22 M25

N4 N23 N26

LE4 A:

Add new circuit

with H/W solution

LE4 B:

Del R224, C408, Q14 and Q17 in BOM

Q17

Q17 *2N7002K

*2N7002K

U38D

VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]

PZ47903-2741-01

1999_SHDN# (39)

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24

PROJECT : LE4

Size Document Number Rev

Date: Sheet

Yonah/Merom (Power/NC)

PROJECT : LE4

Quanta Computer Inc.

542Tuesday, March 14, 2006

H_XRCOMP

R448

24.9/F_4

A A

+1.05V

R447

54.9/F_4

H_XSCOMP

+1.05V

R161

R161 221/F_4

221/F_4

R163

R163 100/F_4

100/F_4

B B

+1.05V

R449

54.9/F_4

H_YSCOMP

+1.05V

15 mils/10mils

H_XSWING

C311

0.1U_NPO_4

Use 1% R

R450

R450 221/F_4

221/F_4

H_YSWING

R451

100/F_4

C C

R452

24.9/F_4

H_YRCOMP

C562

0.1U_NPO_4

15 mils/10mils

H_D#[63:0](4)

Use 1% R

H_XRCOMP H_XSCOMP H_XSWING

H_YRCOMP H_YSCOMP H_YSWING

CLK_MCH_BCLK(3) CLK_MCH_BCLK#(3)

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

T204T204

T205T205

Short Stub < 100mils extract from same point

K11 T10

W11

U11 T11

AB7 AA9

Y10 AB8

AA4 AA7 AA2 AA6

AA10

AA1 AB4

AC9 AB11 AC11

AB3 AC2 AD1 AD9 AC1 AD7 AC6

AB5

AD10

AD4 AC8

AG2 AG1

G1 G2

W4 W3

J6 H3 K2

K9 K1 K7

J8 H4

T3 U7 U9

T1 T8 T4

U5 T9

Y3 Y7

E1 E2 E4

Y1 U1

U35A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_XRCOMP H_XSCOMP H_XSWING

H_YRCOMP H_YSCOMP H_YSWING

H_CLKIN H_CLKIN#

Calistoga

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31

H_ADS#

H_VREF_0

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#

H_VREF_1

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

H_SLPCPU#

H_TRDY#

H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14

E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13

J7 W8 U3 AB10

K4 T7 Y5 AC4

K3 T6 AA5 AC5

D3 D4 B3

D8 G8 B8 F8 A8

B4 E6 D6

E3 E7

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

R444 0_4R444 0_4

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[31:3] (4)

H_ADS# (4) H_ADSTB#0 (4) H_ADSTB#1 (4)

H_BNR# (4) H_BPRI# (4) H_BREQ#0 (4) H_CPURST# (4) H_DBSY# (4) H_DEFER# (4) H_DPWR# (4) H_DRDY# (4)

H_DINV#[3:0] (4)

H_DSTBN#[3:0] (4)

H_DSTBP#[3:0] (4)

H_HIT# (4) H_HITM# (4) H_LOCK# (4)

H_REQ#[4:0] (4)

H_RS#[2:0] (4)

H_CPUSLP# (4,12) H_TRDY# (4)

+1.05V

C295

0.1U_NPO_4

C292

0.1U_NPO_4

+1.05V

R155

R155 100/F_4

100/F_4

R157

R157 200/F_4

200/F_4

+1.05V (4,5,7,9,10,12,15,38,40)

< 0.1" Use 1% R H_VREF :10 mils/20 mils space

H_VREF

D D

Size Document Number Rev

Date: Sheet

Calistoga_A (Host)

PROJECT : LE4

Quanta Computer Inc.

642Tuesday, March 14, 2006

Check

A A

CPU_MCH_BSEL0(3,4) CPU_MCH_BSEL1(3,4) CPU_MCH_BSEL2(3,4)

MCH_CFG_13(9)

B B

PLT_RST-R#(13)

+3VRUN

MCH_ICH_SYNC(13)

1.8VSUS

C C

R160

80.6/F_4

M_RCOMP#

15mils/10mils

M_RCOMP

R159

80.6/F_4

+V1.5_PCIE +3VRUN SMDDR_VREF

1.8VSUS

MCH_CFG_[12:5](9) MCH_CFG_[20:16](9)

L_IBG

R74

R74 I@1.5K_4

I@1.5K_4

D D

DELAY_VR_PWRGOOD(14,37)

L_VDDEN

T21T21 T25T25 T24T24 T72T72 T68T68 T63T63 T60T60 T66T66 T42T42 T23T23 T31T31 T173T173 T183T183 T184T184 T36T36 T185T185

T43T43 T62T62 T50T50

T46T46

T192T192 T54T54

T194T194

PM_BMBUSY#(14) PM_EXTTS#0(16,17) PM_EXTTS#1(14,17)

PM_THRMTRIP#(4,12)

R82

100/F_4

R86

R86 I@100K_4

I@100K_4

CLK_MCH_OE# MCH_RSVD_1 MCH_RSVD_2 MCH_RSVD_3 MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8 TV_DCONSEL0 TV_DCONSEL1 MCH_RSVD_11 MCH_RSVD_12 MCH_RSVD_13 MCH_RSVD_14 MCH_RSVD_15

MCH_BSEL0

MCH_BSEL1

MCH_BSEL2

MCH_CFG_3 MCH_CFG_4 MCH_CFG_5

MCH_CFG_6 MCH_CFG_7

MCH_CFG_8

MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13

MCH_CFG_14 MCH_CFG_15

MCH_CFG_16

MCH_CFG_17

MCH_CFG_18 MCH_CFG_19 MCH_CFG_20

RST IN# MCH

T32T32 T33T33

R114 *10K/F_4R114 *10K/F_4

TP_MCH_NC0

T203T203

TP_MCH_NC1

T178T178

TP_MCH_NC2

T202T202

TP_MCH_NC3

T179T179

TP_MCH_NC4

T181T181

TP_MCH_NC5

T182T182

TP_MCH_NC6

T71T71

TP_MCH_NC7

T73T73

TP_MCH_NC8

T201T201

TP_MCH_NC9

T177T177

TP_MCH_NC10

T197T197

TP_MCH_NC11

T176T176

TP_MCH_NC12

T200T200

TP_MCH_NC13

T175T175

TP_MCH_NC14

T199T199

TP_MCH_NC15

T174T174

TP_MCH_NC16

T196T196

TP_MCH_NC17

T180T180

TP_MCH_NC18

T198T198

+3VRUN

R106 10K/F_4R106 10K/F_4

R113 *10K/F_4R113 *10K/F_4

MCH_CFG_9

+V1.5_PCIE (10) +3VRUN (3,5,9,10,12,13,14,15,16,17,18,19,20,22,23,26,27,28,30,31,32,33,36,40,41) SMDDR_VREF (16)

1.8VSUS (9,16,36,40,41)

MCH_CFG_[12:5] MCH_CFG_[20:16]

LCD_ACLK-(19,22)

LCD_ACLK+(19,22)

LCD_A0-(19,22) LCD_A0+(19,22)

LCD_A1-(19,22) LCD_A1+(19,22)

LCD_A2-(19,22) LCD_A2+(19,22)

H32

RSVD_0

T32

RSVD_1

R32

RSVD_2

RSVD_3

RSVD_4

AG11

RSVD_5

AF11

RSVD_6

RSVD_7

J19

RSVD_8

K30

RSVD_9

J29

RSVD_10

A41

RSVD_11

A35

RSVD_12

A34

RSVD_13

D28

RSVD_14

D27

RSVD_15

K16

CFG_0

K18

CFG_1

J18

CFG_2

F18

CFG_3

E15

CFG_4

F15

CFG_5

E18

CFG_6

D19

CFG_7

D16

CFG_8

G16

CFG_9

E16

CFG_10

D15

CFG_11

G15

CFG_12

K15

CFG_13

C15

CFG_14

H16

CFG_15

G18

CFG_16

H15

CFG_17

J25

CFG_18

K27

CFG_19

J26

CFG_20

G28

PM_BMBUSY#

F25

PM_EXTTS#_0

H26

PM_EXTTS#_1

PM_THRMTRIP#

AH33

PWROK

AH34

RSTIN#

H28

SDVO_CTRLCLK

H27

SDVO_CTRLDATA

K28

LT_RESET#

NC0

C41

NC1

NC2

BA41

NC3

BA40

NC4

BA39

NC5

BA3

NC6

BA2

NC7

BA1

NC8

B41

NC9

NC10

AY41

NC11

AY1

NC12

AW41

NC13

AW1

NC14

A40

NC15

NC16

A39

NC17

NC18

PM_EXTTS#0

PM_EXTTS#1

R125 *10K/F_4R125 *10K/F_4

U35B

CFGRSVD

MISC

Calistoga

+3VRUN

RP32 I@4P2R-S-0RP32 I@4P2R-S-0

2 4

RP29 I@4P2R-S-0RP29 I@4P2R-S-0

2 4

RP31 I@4P2R-S-0RP31 I@4P2R-S-0

2 4

RP30 I@4P2R-S-0RP30 I@4P2R-S-0

2 4

1 3

SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3

SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_OCDCOMP_0 SM_OCDCOMP_1

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP#

SM_RCOMP

DDR MUXINGCLKDMI

SM_VREF_0 SM_VREF_1

D_REFCLKIN#

D_REFCLKIN

D_REFSSCLKIN#

D_REFSSCLKIN

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

LA_CLK# LA_CLK

LA_DATAN0 LA_DATAP0

LA_DATAN1 LA_DATAP1

LA_DATAN2 LA_DATAP2

SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3

G_CLKIN#

G_CLKIN

SMDDR_VREF_MCH

R97 I@0_4R97 I@0_4 R101 I@0_4R101 I@0_4 R96 I@0_4R96 I@0_4 R94 I@0_4R94 I@0_4

DMI_TXN[3:0] (13)

DMI_TXP[3:0] (13) DMI_RXN[3:0] (13)

DMI_RXP[3:0] (13)

AY35 AR1 AW7 AW40

AW35 AT1 AY7 AY40

AU20 AT20 BA29 AY29

AW13 AW12 AY21 AW21

AL20 AF10

BA13 BA12 AY20 AU21

AV9 AT9

AK1 AK41

AF33 AG33 A27 A26

RDREFSSCLK#

C40

RDREFSSCLK

D41

DMI_TXN0

AE35

DMI_TXN1

AF39

DMI_TXN2

AG35

DMI_TXN3

AH39

AC35 AE39 AF35 AG39

DMI_RXN0

AE37

DMI_RXN1

AF41

DMI_RXN2

AG37

DMI_RXN3

AH41

DMI_RXP0

AC37

DMI_RXP1

AE41

DMI_RXP2

AF37

DMI_RXP3

AG41

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

SMDDR_VREF_MCH

M_OCDCOMP_0 M_OCDCOMP_1

M_RCOMP# M_RCOMP

SMDDR_VREF_MCH

R_DOT96# R_DOT96

M_CLK_DDR0 (16) M_CLK_DDR1 (16) M_CLK_DDR2 (16) M_CLK_DDR3 (16)

M_CLK_DDR#0 (16) M_CLK_DDR#1 (16) M_CLK_DDR#2 (16) M_CLK_DDR#3 (16)

M_CKE0 (16,17) M_CKE1 (16,17) M_CKE2 (16,17) M_CKE3 (16,17)

M_CS#0 (16,17) M_CS#1 (16,17) M_CS#2 (16,17) M_CS#3 (16,17)

M_ODT0 (16,17) M_ODT1 (16,17) M_ODT2 (16,17) M_ODT3 (16,17)

< 0.1" . 15mils/15mils space

< 0.1" . 15mils/15mils space use 1% R

PCIE_MTX_GRX_C_N0 PCIE_MTX_GRX_C_N1 PCIE_MTX_GRX_C_N2 PCIE_MTX_GRX_C_N3 PCIE_MTX_GRX_C_N4 PCIE_MTX_GRX_C_N5 PCIE_MTX_GRX_C_N6 PCIE_MTX_GRX_C_N7 PCIE_MTX_GRX_C_N8 PCIE_MTX_GRX_C_N9 PCIE_MTX_GRX_C_N10 PCIE_MTX_GRX_C_N11 PCIE_MTX_GRX_C_N12 PCIE_MTX_GRX_C_N13 PCIE_MTX_GRX_C_N14 PCIE_MTX_GRX_C_N15

C187 E@0.1U_P_4C187 E@0.1U_P_4

1 2

C525 E@0.1U_P_4C525 E@0.1U_P_4

1 2

C189 E@0.1U_P_4C189 E@0.1U_P_4

1 2

C527 E@0.1U_P_4C527 E@0.1U_P_4

1 2

C191 E@0.1U_P_4C191 E@0.1U_P_4

1 2

C529 E@0.1U_P_4C529 E@0.1U_P_4

1 2

C193 E@0.1U_P_4C193 E@0.1U_P_4

1 2

C531 E@0.1U_P_4C531 E@0.1U_P_4

1 2

C195 E@0.1U_P_4C195 E@0.1U_P_4

1 2

C533 E@0.1U_P_4C533 E@0.1U_P_4

1 2

C197 E@0.1U_P_4C197 E@0.1U_P_4

1 2

C519 E@0.1U_P_4C519 E@0.1U_P_4

1 2

C199 E@0.1U_P_4C199 E@0.1U_P_4

1 2

C521 E@0.1U_P_4C521 E@0.1U_P_4

1 2

C201 E@0.1U_P_4C201 E@0.1U_P_4

1 2

C523 E@0.1U_P_4C523 E@0.1U_P_4

1 2

R568 *0_4R568 *0_4 R173 0_4R173 0_4

0402

R172 10K/F_6R172 10K/F_6

R171

R171 10K/F_6

10K/F_6

0402

R569 I@0_4R569 I@0_4

Change R172 AND R171 SIZE from 0402 to 0603

LCD_BKLTCTL(22) LCD_BLON_EC(19,22,30)

T22T22

DISP_ON(22)

LE4 B:

Use 1% R

15mils/15mils

R156

*40.2/F_4

Layout as short as passable

NC from WW45

Shall be 10K divider of 1.8V_SUS

DOT96#

DOT96 DREFSSCLK# DREFSSCLK

Reserved for AV

TV_COMP(23) TV_Y/G(23) TV_C/R(23)

CRT_B_COM(23) CRT_G_COM(23) CRT_R_COM(23)

PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15

R421 I@150/F_4R421 I@150/F_4 R425 I@150/F_4R425 I@150/F_4 R430 I@150/F_4R430 I@150/F_4

DDCCLK(23)

DDCDAT(23)

HSYNC_COM(23)

VSYNC_COM(23)

DC Blocked Cap.

Near to North Bridge

add R569

R120

R120 *40.2/F_4

*40.2/F_4

CLK_PCIE_3GPLL# (3) CLK_PCIE_3GPLL (3) DOT96# (3) DOT96 (3) DREFSSCLK# (3) DREFSSCLK (3)

LE4 A:

As below

R428 I@0_4R428 I@0_4 R423 I@0_4R423 I@0_4 R419 I@0_4R419 I@0_4

R406 I@0_4R406 I@0_4 R411 I@0_4R411 I@0_4 R415 I@0_4R415 I@0_4

V_DDR_MCH_REF SMDDR_VREF

1.8VSUS

T38T38

T34T34

EDIDCLK(22) EDIDDATA(22)

R81 I@0_4R81 I@0_4

R591

R590 I@0_6R590 I@0_6

R416 I@150/F_4R416 I@150/F_4 R412 I@150/F_4R412 I@150/F_4

R407 I@150/F_4R407 I@150/F_4 R105 I@0_4R105 I@0_4 R98 I@0_4R98 I@0_4

R116

R116 R126 I@255/F_4R126 I@255/F_4

R112 I@39/F_4R112 I@39/F_4

PCIE_MTX_GRX_C_P0 PCIE_MTX_GRX_C_P1 PCIE_MTX_GRX_C_P2 PCIE_MTX_GRX_C_P3 PCIE_MTX_GRX_C_P4 PCIE_MTX_GRX_C_P5 PCIE_MTX_GRX_C_P6 PCIE_MTX_GRX_C_P7 PCIE_MTX_GRX_C_P8 PCIE_MTX_GRX_C_P9 PCIE_MTX_GRX_C_P10 PCIE_MTX_GRX_C_P11 PCIE_MTX_GRX_C_P12 PCIE_MTX_GRX_C_P13 PCIE_MTX_GRX_C_P14 PCIE_MTX_GRX_C_P15

R391 I@0_4R391 I@0_4 R89 I@0_4R89 I@0_4

L_CLKCTLA

L_CLKCTLB

R119 I@0_4R119 I@0_4 R115 I@0_4R115 I@0_4

LA_CLK#

LA_CLK

T37T37 T39T39

LA_DATAN0

LA_DATAN1

LA_DATAN2

LA_DATAP0

LA_DATAP1

LA_DATAP2

T30T30 T28T28 T26T26

T29T29 T27T27 T35T35

TV_IRTN

I@0_6

TV_COMP1 TV_Y/G1 TV_C/R1

R124

I@4.99K/F_4

CRT_BLUE CRT_GREEN CRT_RED

I@39/F_4

LE4 B:

D32

J30 H30 H29

G26 G25

L_IBG

TVIREF

B38 C35 F32 C33 C32

A33 A32 E27 E26

C37 B35 A37

B37 B34 A36

G30

D30 F29

F30 D29 F28

A16 C18 A19

J20 B16 B18 B19

E23 D23 C22 B22 A21 B21

C26 C25

G23

J22 H23

L_VBG L_VDDEN

CRT_RGB#

CRT_DDC_CLK CRT_DDC_DAT

HSYNC1 CRTIREF

VSYNC1

C186 E@0.1U_P_4C186 E@0.1U_P_4

1 2

C524 E@0.1U_P_4C524 E@0.1U_P_4

1 2

C188 E@0.1U_P_4C188 E@0.1U_P_4

1 2

C526 E@0.1U_P_4C526 E@0.1U_P_4

1 2

C190 E@0.1U_P_4C190 E@0.1U_P_4

1 2

C528 E@0.1U_P_4C528 E@0.1U_P_4

1 2

C192 E@0.1U_P_4C192 E@0.1U_P_4

1 2

C530 E@0.1U_P_4C530 E@0.1U_P_4

1 2

C194 E@0.1U_P_4C194 E@0.1U_P_4

1 2

C532 E@0.1U_P_4C532 E@0.1U_P_4

1 2

C196 E@0.1U_P_4C196 E@0.1U_P_4

1 2

C518 E@0.1U_P_4C518 E@0.1U_P_4

1 2

C198 E@0.1U_P_4C198 E@0.1U_P_4

1 2

C520 E@0.1U_P_4C520 E@0.1U_P_4

1 2

C200 E@0.1U_P_4C200 E@0.1U_P_4

1 2

C522 E@0.1U_P_4C522 E@0.1U_P_4

1 2

add R568

L_CLKCTLA L_CLKCTLB

U35C

L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL

LA_CLK# LA_CLK LB_CLK# LB_CLK

LA_DATA#_0 LA_DATA#_1 LA_DATA#_2

LA_DATA_0 LA_DATA_1 LA_DATA_2

LB_DATA#_0 LB_DATA#_1 LB_DATA#_2

LB_DATA_0 LB_DATA_1 LB_DATA_2

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT

TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC

Calistoga

PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15

R108 I@10K/F_4R108 I@10K/F_4 R102 I@10K/F_4R102 I@10K/F_4

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8

EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11

LVDS

VGA

EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15

EXP_A_RXP_0

EXP_A_RXP_1

EXP_A_RXP_2

EXP_A_RXP_3

EXP_A_RXP_4

EXP_A_RXP_5

EXP_A_RXP_6

EXP_A_RXP_7

EXP_A_RXP_8

EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12

PCI-EXPRESS GRAPHICS

EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15

EXP_A_TXP_0

EXP_A_TXP_1

EXP_A_TXP_2

EXP_A_TXP_3

EXP_A_TXP_4

EXP_A_TXP_5

EXP_A_TXP_6

EXP_A_TXP_7

EXP_A_TXP_8

EXP_A_TXP_9

EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15

PCIE_MTX_GRX_P[0..15] (18)PCIE_MTX_GRX_N[0..15] (18)

+3VRUN

20mils/20mils space

EXP_A_COMPX

D40 D38

PCIE_MRX_GTX_N0

F34

PCIE_MRX_GTX_N1

G38

PCIE_MRX_GTX_N2

H34

PCIE_MRX_GTX_N3

J38

PCIE_MRX_GTX_N4

L34

PCIE_MRX_GTX_N5

M38

PCIE_MRX_GTX_N6

N34

PCIE_MRX_GTX_N7

P38

PCIE_MRX_GTX_N8

R34

PCIE_MRX_GTX_N9

T38

PCIE_MRX_GTX_N10

V34

PCIE_MRX_GTX_N11

W38

PCIE_MRX_GTX_N12

Y34

PCIE_MRX_GTX_N13

AA38

PCIE_MRX_GTX_N14

AB34

PCIE_MRX_GTX_N15

AC38

PCIE_MRX_GTX_P0

D34

PCIE_MRX_GTX_P1

F38

PCIE_MRX_GTX_P2

G34

PCIE_MRX_GTX_P3

H38

PCIE_MRX_GTX_P4

J34

PCIE_MRX_GTX_P5

L38

PCIE_MRX_GTX_P6

M34

PCIE_MRX_GTX_P7

N38

PCIE_MRX_GTX_P8

P34

PCIE_MRX_GTX_P9

R38

PCIE_MRX_GTX_P10

T34

PCIE_MRX_GTX_P11

V38

PCIE_MRX_GTX_P12

W34

PCIE_MRX_GTX_P13

Y38

PCIE_MRX_GTX_P14

AA34

PCIE_MRX_GTX_P15

AB38

PCIE_MTX_GRX_C_N0

F36

PCIE_MTX_GRX_C_N1

G40

PCIE_MTX_GRX_C_N2

H36

PCIE_MTX_GRX_C_N3

J40

PCIE_MTX_GRX_C_N4

L36

PCIE_MTX_GRX_C_N5

M40

PCIE_MTX_GRX_C_N6

N36

PCIE_MTX_GRX_C_N7

P40

PCIE_MTX_GRX_C_N8

R36

PCIE_MTX_GRX_C_N9

T40

PCIE_MTX_GRX_C_N10

V36

PCIE_MTX_GRX_C_N11

W40

PCIE_MTX_GRX_C_N12

Y36

PCIE_MTX_GRX_C_N13

AA40

PCIE_MTX_GRX_C_N14

AB36

PCIE_MTX_GRX_C_N15

AC40

PCIE_MTX_GRX_C_P0

D36

PCIE_MTX_GRX_C_P1

F40

PCIE_MTX_GRX_C_P2

G36

PCIE_MTX_GRX_C_P3

H40

PCIE_MTX_GRX_C_P4

J36

PCIE_MTX_GRX_C_P5

L40

PCIE_MTX_GRX_C_P6

M36

PCIE_MTX_GRX_C_P7

N40

PCIE_MTX_GRX_C_P8

P36

PCIE_MTX_GRX_C_P9

R40

PCIE_MTX_GRX_C_P10

T36

PCIE_MTX_GRX_C_P11

V40

PCIE_MTX_GRX_C_P12

W36

PCIE_MTX_GRX_C_P13

Y40

PCIE_MTX_GRX_C_P14

AA36

PCIE_MTX_GRX_C_P15

AB40

SMDDR_VREF_MCH

C333

0.1U_4

+V1.5_PCIE

R67 24.9/F_4R67 24.9/F_4

PCIE_MRX_GTX_N[0..15] (18)

PCIE_MRX_GTX_P[0..15] (18)

R_DOT96#

R_DOT96 RDREFSSCLK# RDREFSSCLK

940GML/945GM with clock signal

C536

0.1U_4

945PM with power and GND plan

Size Document Number Rev

Date: Sheet

R95 E@0_4R95 E@0_4 R107 E@0_4R107 E@0_4 R100 E@0_4R100 E@0_4 R90 E@0_4R90 E@0_4

LE4 A:

LE4 B:

Change Netname

Calistoga_B (VGA,DMI)

+1.5V

TV_COMP1 TV_Y/G1 TV_C/R1 TVIREF TV_IRTN TV_IRTN

CRT_BLUE CRT_GREEN CRT_RED CRT_RGB# CRT_RGB# CRTIREF

HSYNC1 VSYNC1

LE4 B:

945PM contact power and GND plane 945GM/940GML Contact GND plane

+1.5V

PROJECT : LE4

Quanta Computer Inc.

R576 E@0_4R576 E@0_4 R577 E@0_4R577 E@0_4 R578 E@0_4R578 E@0_4 R579 E@0_4R579 E@0_4 R580 E@0_4R580 E@0_4 R581 E@0_4R581 E@0_4

R582 E@0_4R582 E@0_4 R583 E@0_4R583 E@0_4 R584 E@0_4R584 E@0_4 R585 E@0_4R585 E@0_4 R586 E@0_4R586 E@0_4

R587 E@0_4R587 E@0_4 R588 E@0_4R588 E@0_4 R589 E@0_4R589 E@0_4

742Tuesday, March 14, 2006

+1.05V

A A

M_B_DQ[63:0](16)

M_A_DQ[63:0](16)

B B

C C

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AJ35

AJ34 AM31 AM33

AJ36

AK35

AJ32 AH31 AN35

AP33

AR31

AP31 AN38 AM36 AM34 AN33

AK26

AL27 AM26 AN24

AK28

AL28 AM24

AP26

AP23

AL22

AP21 AN20

AL23

AP24

AP20

AT21 AR12 AR14

AP13

AP12

AT13

AT12

AL14

AL12

AK9 AN7 AK8 AK7 AP9 AN9 AT5

AL5 AY2

AW2

AP1 AN2 AV2 AT3 AN1

AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8

U35D

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

Calistoga

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

DDR SYSTEM MEMORY A

SA_WE#

AU12 AV14 BA20

AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4

AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5

AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12

AW14 AK23 AK24 AY14

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CAS# M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1

M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

TP_MA_RCVENIN# TP_MA_RCVENOUT#

M_A_BS#0 (16,17) M_A_BS#1 (16,17) M_A_BS#2 (16,17) M_A_CAS# (16,17)

M_A_DM[7:0] (16)

M_A_DQS[7:0] (16)

M_A_DQS#[7:0] (16)

M_A_A[13:0] (16,17)

M_A_RAS# (16,17)

T41T41 T40T40

M_A_WE# (16,17)

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AK39

AJ37 AP39 AR41

AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40

AW38

AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31

AW31

AV29

AW29 AM19

AL19 AP14 AN14 AN17

AM16

AP15 AL15

AJ11 AH10

AJ9 AN10 AK13 AH11 AK10

AJ8 BA10

AW10

BA4

AW4

AY10

AY9

AW5

AY5 AV4 AR5 AK4 AK3 AT4 AK5

AJ5

AJ3

U35E

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

Calistoga

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

DDR SYSTEM MEMORY B

SB_WE#

AT24 AV23 AY28

AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4

AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5

AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23

AU23 AK16 AK18 AR27

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6M_A_DQS2 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

TP_MB_RCVENIN# TP_MB_RCVENOUT#

M_B_BS#0 (16,17) M_B_BS#1 (16,17) M_B_BS#2 (16,17) M_B_CAS# (16,17) M_B_DM[7:0] (16)

M_B_DQS[7:0] (16)

M_B_DQS#[7:0] (16)

M_B_A[13:0] (16,17)

M_B_RAS# (16,17)

T52T52 T45T45

M_B_WE# (16,17)

D D

PROJECT : LE4

Size Document Number Rev

Date: Sheet

Calistoga_C ( DDR )

PROJECT : LE4

Quanta Computer Inc.

842Tuesday, March 14, 2006

U35G

C364

+1.05V +1.05V

D D

C C

B B

A A

C364

330U_2.5V_ESR12

AA33

W33

P33 N33

L33 J33

AA32

Y32

W32

V32 P32 N32

M32

L32 J32

AA31

W31

V31

T31 R31 P31 N31

M31

AA30

Y30

W30

V30 U30

T30 R30 P30 N30

M30

L30

AA29

Y29

W29

V29 U29 R29 P29

M29

L29

AB28 AA28

Y28 V28 U28

T28 R28 P28 N28

M28

L28 P27 N27

M27

L27 P26 N26

L26 N25

M25

L25 P24 N24

M24 AB23 AA23

Y23 P23 N23

M23

L23 AC22 AB22

Y22

W22

P22 N22

M22

L22 AC21 AA21

W21

N21

M21

L21 AC20 AB20

Y20

W20

P20 N20

M20

L20 AB19 AA19

Y19 N19

M19

L19

N18

M18

L18

P17 N17

M17

N16

M16

L16

U35G

VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110

VCC

Calistoga

VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8

VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99

VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107

AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1

25mils

VCC_SM1 VCC_SM2

VCC_SM106 VCC_SM107

C214 0.47U_6C214 0.47U_6 C222 0.47U_6C222 0.47U_6

PC6

PC6 330U_2.5V_ESR12

330U_2.5V_ESR12

2.5

C253

0.47U_6

place C49 on AJ23 Ball

place C51 on BA15 Ball

MCH_CFG_6 shall be PH !! depopulate R2504 if use Calistoga

25mils

C325 0.47U_6C325 0.47U_6 C310 0.47U_6C310 0.47U_6

C344

1.8VSUS

C274

C281

C281 10U_8

10U_8

C255

0.47U_6

C254

0.47U_6

place C50 on BA23 Ball

Have to review again ADD Matrix in silkscreen

C269

0.47U_6

intel WW51 recommand

330U_2.5V_ESR12

C242

C242 10U_8

10U_8

120mils

del 1.5V_AUX power planeLE4 B:

MCH_CFG_5(7)

MCH_CFG_6(7)

MCH_CFG_7(7)

MCH_CFG_9(7)

MCH_CFG_10(7)

MCH_CFG_11(7)

MCH_CFG_12(7)

MCH_CFG_13(7)

MCH_CFG_16(7)

MCH_CFG_18(7)

MCH_CFG_19(7)

MCH_CFG_20(7)

C288

C273

C273 10U_8

10U_8

C282

0.1U_4

+1.05V(4,5,6,7,10,12,15,38,40)

1.8VSUS(7,16,36,40,41)

C237

C237 1U_4

1U_4

10U to 1U-Allen

C252

0.1U_4

C288

C272

0.1U_4

C302

0.1U_4

+1.05V

1.8VSUS

Depopulate R2504 for Calistoga-Allen

GMCH Strap pin

R137 *2.2K_4R137 *2.2K_4

R136 *2.2K_4R136 *2.2K_4

R130 *2.2K_4R130 *2.2K_4

R129 *2.2K_4R129 *2.2K_4

R143 *2.2K_4R143 *2.2K_4

R141 2.2K_4R141 2.2K_4

R144 *2.2K_4R144 *2.2K_4

R140 *2.2K_4R140 *2.2K_4

R142 *2.2K_4R142 *2.2K_4

R117 *1K/F_4R117 *1K/F_4

R110 *1K/F_4R110 *1K/F_4

R109 *1K/F_4R109 *1K/F_4

C294

0.1U_4

+3VRUN

AD27 AC27

AB27 AA27

Y27

W27

V27 U27 T27 R27

AD26 AC26

AB26 AA26

Y26

W26

V26 U26 T26 R26

AD25 AC25

AB25 AA25

Y25

W25

V25 U25 T25 R25

AD24 AC24

AB24 AA24

Y24

W24

V24 U24 T24 R24

AD23

V23 U23 T23 R23

AD22

V22 U22 T22 R22

AD21

V21 U21 T21 R21

AD20

V20 U20 T20 R20

AD19

V19 U19 T19

AD18 AC18

AB18 AA18

Y18

W18

V18 U18 T18

U35F

VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72

VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8

VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12

VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8

VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30

NCTF

Calistoga

1.MCH_CFG_5 Low = DMI X2, High=DMIX4

2.MCH_CFG_6 DDR : Low =Moby Dick, High= Calistoga (Default)

3.MCH_CFG_7 CPU Strap Low=RSVD, High=Mobile CPU

4.MCH_CFG_9 PCI Exp Graphics Lane: Low =Reserved,High=Mobility

5.MCH_CFG_10 Host PLL VCC Select: Low=Reserved, High=Mobility

6.MCH_CFG_11: Low=Calistoga, High=Reserved

7.MCH_CFG_16 FSB Dynmic ODT: Low=Dynamic ODT Disabled, High=Dynamic ODT Enabled.

8.MCH_CFG_18 VCC Select: LOW=1.05V, High=1.5V

9.MCH_CFG_19 DMI LANE Reversal:Low=Normal,High=LANES Reversed.

10.MCH_CFG_20 PCIE Backward interpoerability mode: Low= only SDVO or PCIE x1 is operational (defaults) ,High=SDVO and PCIE x1 are operation simultaneously via the PEG port.

VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57

AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17

AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15

+1.5V

LE4 B: change +1.5V_AUX to +1.5V

100mils

Size Document Number Rev

Date: Sheet

Calistoga_D ( POWER )

PROJECT : LE4

Quanta Computer Inc.

942Tuesday, March 14, 2006

L48

+V3.3_TVDAC

L52

L52 I@BLM18PG181SN1D_8

I@BLM18PG181SN1D_8

Oreginal FCM2012C-181 "CX000181008"

+1.5V

E@BLM18PG181SN1D-6_8

60mils

PCIE_L

RC0805

60mils

3GPLL_FB_L

L23

R103

R103 0_8

0_8

+1.5V +V1.5_DPLLA

L53 10uH_8L53 10uH_8

C556

0.1U_4

C516

C516 220U_6.3V

220U_6.3V

0.1U_4

C537

0.1U_4

C318

0.1U_4

C309

0.1U_4

+V1.5_DPLLB

+V1.5_HPLL

+V1.5_MPLL

BLM21PG220SN1D

L18

L18 1uH_6

1uH_6

C296

C296 330U

330U

L49 10uH_8L49 10uH_8

A A

L27 FCM2012C-121_8L27 FCM2012C-121_8

L26 FCM2012C-121_8L26 FCM2012C-121_8

+V1.5_PCIE

B B

C515

C515 10U_8

10U_8

R93

0.5/F_6

C184

C184 330U

330U

C342

10U_8

C341

10U_8

C513

C513 10U_8

10U_8

60mils

3GPLL_FB_R

RC0805

LE4 B:

del R111,C246

change +1.5V_AUX to 1.5V

C C

10U_8

D D

+2_5VRUN

R396 I@0_8R396 I@0_8

R401 E@0_8R401 E@0_8

R2_5VRUNA

LE4 A:

Note:

940GML/945GM contact Power plan 945PM contact GAN plan

+3VRUN +1.5V

C244

C322

C248

+V3.3_TVDAC

0.1U_4

C322

0.1U_4

V1_5SFOLLOW

R440

R440 I@10_4

I@10_4

R154 I@0_8R154 I@0_8

C343

C343 10U_8

10U_8

0.002 1%

RC0805

30mils

BAT54

D6 I@PDZ5.6BD6 I@PDZ5.6B

+V2.5_CRTDAC

+1.05V

LE4 A:

Note:

940GML/945GM contact +2.5_CRTDAC 945PM contact +1.05V

+3.3S_TVDAC_LDO

+1.5V

LE4 B:

Note: 940GML/945GM has circuit 945PM NA

C267

80mils

10U_8

+V3.3_ATVBG

C555

0.1U_4

+V3.3_ATVBG

C553

0.1U_4

+V3.3_ATVBG

C554

0.1U_4

+V3.3_ATVBG

C293

0.022U_4

C279

0.022U_4

C287

0.022U_4

+V3.3_ATVBG

LE4 A:

Note:

940GML/945GM contact +V3.3_ATVBG 945PM contact +1.5V

+1.5V

LE4 C:

Solve black screen issue to change L48 material

Del R389

+1.5V+V1.5_3GPLL

0.002ohm/1%

+1.5V

R397 I@0_8R397 I@0_8

R398 E@0_8R398 E@0_8

LE4 A:

Note:

940GML/945GM contact Power plan 945PM contact GAN plan

R118 I@0_8R118 I@0_8

R127 E@0_8R127 E@0_8

R2.5VCRTDAC

+V1.5_TVDAC +1.5V

C257

0.022U_4

+V1.5_QTVDAC

C259

0.022U_4

+2_5VRUN

C234

C207

4.7U_6

C235

C235 10U_8

10U_8

R2.5VCRTDAC

C258

0.022U_4

R2_5VRUNA

C213

0.1U_4

RV3.3_ATVBG

C271

0.022U_4

RV3.3_ATVBG

VCCD_LVDS

+V3.3_ATVBG

+1.5V

0.1U_4

+V1.5_3GPLL

C231

0.1U_4

C256

0.1U_4

C211

0.01U_4

C270

0.1U_4

R131 I@0_8R131 I@0_8

R438 E@0_8R438 E@0_8

LE4 A:

Note:

940GML/945GM contact +V3.3_ATVBG 945PM contact +1.5V

60mils

L20

C250

0.1U_4

C251

0.1U_4

Oreginal FCM2012C-181 "CX000181008"

L20

FCM2012C-121_8

L22

FCM2012C-121_8

V15_TVDAC_R

Oreginal FCM2012C-181 "CX000181008"

+V1.5_HPLL

+1.5V

40mils

+1.5V

LE4 B:

RC0805

+2_5VRUN

C205

0.1U_4

+2_5VRUN

+3VRUN

R400

0_8

+V1.5_DPLLB

R392 I@0_8R392 I@0_8

C240

C240 10U_8

10U_8

R393 E@0_8R393 E@0_8

R2_5VRUN

+V1.5_PCIE

C233

0.1U_4

+V1.5_DPLLA

+V1.5_MPLL

+V3.3_ATVBG

VCCD_LVDS

+V1.5_TVDAC

+V1.5_QTVDAC

R2_5VRUN

LE4 A:

Note:

940GML/945GM contact Power plan 945PM contact GAN plan

U35H

H22

VCCSYNC

C30

VCC_TXLVDS0

B30

VCC_TXLVDS1

A30

VCC_TXLVDS2

AJ41

VCC3G0

AB41

VCC3G1

Y41

VCC3G2

V41

VCC3G3

R41

VCC3G4

N41

VCC3G5

L41

VCC3G6

AC33

VCCA_3GPLL

G41

VCCA_3GBG

H41

VSSA_3GBG

F21

VCCA_CRTDAC0

E21

VCCA_CRTDAC1

G21

VSSA_CRTDAC

B26

VCCA_DPLLA

C39

VCCA_DPLLB

AF1

VCCA_HPLL

A38

VCCA_LVDS

B39

VSSA_LVDS

AF2

VCCA_MPLL

H20

VCCA_TVBG

G20

VSSA_TVBG

E19

VCCA_TVDACA0

F19

VCCA_TVDACA1

C20

VCCA_TVDACB0

D20

VCCA_TVDACB1

E20

VCCA_TVDACC0

F20

AH1 AH2

A28 B28 C28

D21 A23

B23 B25

H19

AK31 AF31 AE31 AC31

AL30

AK30

AJ30

AH30

AG30

AF30 AE30 AD30 AC30

AG29

AF29 AE29 AD29 AC29

AG28

AF28 AE28 AH22

AJ21

AH21

AJ20 AH20 AH19

P19 P16

AH15

P15

AH14

AG14

AF14 AE14

Y14 AF13 AE13 AF12 AE12 AD12

VCCA_TVDACC1 VCCD_HMPLL0

VCCD_HMPLL1 VCCD_LVDS0

VCCD_LVDS1 VCCD_LVDS2

VCCD_TVDAC VCC_HV0

VCC_HV1 VCC_HV2

VCCD_QTVDAC VCCAUX0

VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40

POWER

Calistoga

VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76

AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1

+1.05V

330U/2.5V/ESR-9/POS

2005/07/14

VTTLF_CAP3

C303

0.47U_6

2005/07/14

VTTLF_CAP2 VTTLF_CAP1

C561

0.47U_6

+1.05V +1.5V +V1.5_PCIE +2_5VRUN +3VRUN

C283

C239

0.22U_4

C300

C300 I@10U_8

I@10U_8

C283

2.2U/6.3V_6

C299

C299 I@0.01U_4

I@0.01U_4

C245

C290

4.7U/6.3v_8

C241

0.22U_4

+2_5VRUN

VTT_56 , VTT_71 and 72 are attached with 0.1u seperated .Checking

R91

R91 10_4

10_4

L19

L19 FCM2012C-121_8

FCM2012C-121_8

+3.3S_TVDAC_LDO

C312

0.22U_4

+1.05V (4,5,6,7,9,12,15,38,40) +1.5V (5,7,9,13,15,27,38,40) +V1.5_PCIE (7) +2_5VRUN (19,22,40) +3VRUN (3,5,7,9,12,13,14,15,16,17,18,19,20,22,23,26,27,28,30,31,32,33,36,40,41)

+1.05V

C261

C249

10U_8

0.1U_4

+1.05V

C264

0.47U_6

25mils

VCCGFOLLOW

C284

0.47U_6

BAT54

D1 PDZ5.6B

PDZ5.6B

For TV-OUT

U16

OUT

BYP

I@AAT3218

GND

Size Document Number Rev

Date: Sheet

+1.05V

+V2.5_CRTDAC

Within 3" of GMCH

+5VRUN

LE4 B:

Note: 940GML/945GM has circuit

C306

C306 I@1U_6

I@1U_6

Quanta Computer Inc.

Calistoga_E ( POWER2 )

945PM NA

PROJECT : LE4

10 42Tuesday, March 14, 2006

U35I

AC41

VSS_0

AA41

VSS_1

W41

VSS_2

T41

VSS_3

P41

VSS_4

M41

VSS_5

J41

VSS_6

F41

VSS_7

AV40

VSS_8

D D

C C

B B

AP40 AN40 AK40

AJ40

AH40

AG40

AF40

AE40

B40

AY39

AW39

AV39 AR39 AN39

AJ39 AC39 AB39 AA39

Y39

W39

V39 T39 R39 P39 N39

M39

L39

J39

H39

G39

F39 D39

AT38

AM38

AH38 AG38

AF38

AE38

C38 AK37 AH37 AB37 AA37

Y37

W37

V37

T37

R37

P37

N37

M37

L37

J37

H37

G37

F37

D37 AY36

AW36

AN36 AH36 AG36

AF36 AE36 AC36

C36

B36 BA35 AV35 AR35 AH35 AB35 AA35

Y35

W35

V35

T35

R35

P35

N35

M35

L35

J35

H35

G35

F35

D35 AN34

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96

Calistoga

VSS

VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23

AT23 AN23 AM23 AH23 AC23

W23

K23

J23 F23 C23

AA22

K22 G22 F22 E22 D22 A22

BA21 AV21 AR21 AN21

AL21

AB21

Y21 P21 K21

J21 H21 C21

AW20

AR20

AM20

AA20

K20 B20 A20

AN19 AC19

W19

K19 G19 C19

AH18

P18 H18 D18 A18

AY17 AR17 AP17

AM17

AK17 AV16 AN16

AL16

J16 F16 C16

AN15

AM15

AK15

N15

M15

L15 B15 A15

BA14

AT14 AK14 AD14 AA14

U14 K14 H14

E14 AV13 AR13 AN13

AM13

AL13

AG13

P13

F13

D13

B13 AY12 AC12

K12

H12

E12 AD11 AA11

Y11

U35J

VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272

VSS

Calistoga

VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1

A A

PROJECT : LE4

Size Document Number Rev

Date: Sheet

Calistoga_F ( VSS NCTF )

PROJECT : LE4

Quanta Computer Inc.

11 42Wednesday, November 16, 2005

RTC

3VPCU

VCCRTC_2

R312

R312 1K/F_4

A A

5VPCU

R310

4.7K_4

R311

R311 15K/F_4

15K/F_4

B B

C C

1K/F_4

BT1

BT1 BAT_CONN

BAT_CONN

20MIL 20MIL

R316

1.2K/F_4

add RTC Bat rechargeable circuit

SATA_LED#(31)

Review current rating

+3VRUN

R334

4.7K_4

R496

4.7K_4

VCCRTC

D15

D15 CH500H-40

CH500H-40

D14

D14 CH500H-40

CH500H-40

R546

R546 1M_4

1M_4

R317

1K/F_4

Difference

+3VRUN

R494

R494 10K_4

10K_4

C667

C667 1U_4

1U_4

C684

1U/6.3V_4

VCCRTC_3VCCRTC_1

Internal PU

SATA_RXN0_C(32) SATA_RXP0_C(32)

SATA_TXN0(32) SATA_TXP0(32)

CKL:1n ~ 20nF

CLK_PCIE_SATA#(3) CLK_PCIE_SATA(3)

25mils/15mils

Q23

SATA_LED#

Place near to Mini-door

LE4 A:

R545

R545 20K/F_4

20K/F_4

G1 SHORT_ PAD1

SHORT_ PAD1

Internal PU

MMBT3904

C449 3900P_P_4C449 3900P_P_4

C448 3900P_P_4C448 3900P_P_4

T245T245 T243T243 T249T249 T248T248

R289 24.9/F_4R289 24.9/F_4

Place within 500 mils of ICH7

PIORDY(32) PDDREQ(32)

C459

C459 15P_4

15P_4

32.768KHZ

BG332768909

C457

C457 18P_4

18P_4

CLK_PCIE_SATA# CLK_PCIE_SATA

PDIOR#(32) PDIOW#(32)

PDDACK#(32)

IRQ14(32)

CKL:C1/C2: 18pF -> CL:12.5pF C1/C: 10pF -> CL Value =

8.5pF

Change C459 value from 18p to 15p

U23A

AB1

RTXC1

AB2

RTCX2

AA3

RTCRST#

INTRUDER#

INTVRMEN

EE_CS

EE_SHCLK

EE_DOUT

EE_DIN

LAN_CLK

LAN_RSTSYNC

LAN_RXD0

LAN_RXD1

LAN_RXD2

LAN_TXD0

LAN_TXD1

LAN_TXD2

ACZ_BIT_CLK

ACZ_SYNC

ACZ_RST#

ACZ_SDIN0

ACZ_SDIN1

ACZ_SDIN2

ACZ_SDOUT

AF18

SATALED#

AF3

SATA0RXN

AE3

SATA0RXP

AG2

SATA0TXN

AH2

SATA0TXP

AF7

SATA2RXN

AE7

SATA2RXP

AG6

SATA2TXN

AH6

SATA2TXP

AF1

SATA_CLKN

AE1

SATA_CLKP

AH10

SATARBIASN

AG10

SATARBIASP

AF15

DIOR#

AH15

DIOW#

AF16

DDACK#

AH16

IDEIRQ

AG16

IORDY

AE15

DDREQ

ICH7-M

CLK_32KX1

4 1

CLK_32KX2

RTCRST#

SM_INTRUDER# ICH_INTVRMEN

T254T254 T124T124

SATA_RXN0_C SATA_RXP0_C

SATA_RXN2_C SATA_RXP2_C SATA_TXN2_C SATA_TXP2_C

SATA_BIAS

PDIOR# PDIOW# PDDACK# IRQ14 PIORDY PDDREQ

LE4 B:

R315

R315 10M_6

10M_6

ACZ_BCLK ACZ_SYNC

ACZ_RST# ACZ_SDIN0

ACZ_SDIN1 ACZ_SDIN2

ACZ_SDOUT

SATA_TXN0_C

SATA_TXP0_C

LPCCPU

RTCLAN

AC-97/AZALIA

SATA

IDE

LAD0 LAD1 LAD2 LAD3

LDRQ0#

LDRQ1#/GPIO23

LFRAME#

A20GATE

A20M#

CPUSLP#

TP1/DPRSTP#

TP2/DPSLP#

FERR#

GPIO49/CPUPWRGD

IGNNE#

INIT3_3V#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THERMTRIP#

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8

DD9 DD10 DD11 DD12 DD13 DD14 DD15

DA0 DA1 DA2

DCS1# DCS3#

AA6 AB5 AC4 Y6

AC3 AA5

AB3 AE22

AH28 AG27 AF24

AH25 AG26 AG24

AG22 AG21 AF22 AF25

AG23 AH24

AF23 AH22 AF26

AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15

AH17 AE17 AF17

AE16 AD16

LAD0 LAD1 LAD2 LAD3

LDRQ#0 LDRQ#1

GATEA20

TP_H_CPUSLP# H_DPRSTP#_R

H_DPSLP#_R

R222 *0_4R222 *0_4 R477 0_4R477 0_4

R473 0_4R473 0_4

R481 0/F_4R481 0/F_4

Difference

T97T97

RCIN#

H_SMI#_R

H_THERMTRIP_R

PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15

PDA0 PDA1 PDA2

LAD0 (26,27,30) LAD1 (26,27,30) LAD2 (26,27,30) LAD3 (26,27,30)

LDRQ#0 (26,27,30)

T251T251

LFRAME# (26,27,30) GATEA20 (30)

H_A20M# (4)

R479 0_4R479 0_4

PDD[15:0] (32)

PDA[2:0] (32)

PDCS1# (32) PDCS3# (32)

R5506 close to MCH

H_CPUSLP# (4,6)

H_PWRGD (4)

H_IGNNE# (4) H_INIT# (4)

H_INTR (4) RCIN# (30) H_NMI (4)

H_SMI# (4) H_STPCLK# (4)

+1.05V

R226

R234

*56_4

ICH_DPRSTP# (4,37) H_DPSLP# (4)

Should be 2" close ICH7

R471 24.9_4R471 24.9_4

Should be 2" close ICH7

O ohm ?

ACZ_SDOUT

ACZ_SYNC

R552 39_4R552 39_4

Near To ICH7-M

R553 39_4R553 39_4

RCIN# GATEA20

ACZ_SDIN0

+3VRUN

R236

R236 10K_4

10K_4

+1.05V

+3VRUN

R244

R244 10K_4

10K_4

+1.05V

R230

R230 56_4

56_4

H_FERR# (4)

R472

R472 56_4

56_4

ACZ_SDIN0 (28)

ACZ_SDOUT_AUDIO (28)

C689

C689 *10P_4

*10P_4

ACZ_SYNC_AUDIO (28)

C690

C690 *10P_4

*10P_4

PM_THRMTRIP# (4,7)

LE4 B:

Change R496 and R334 from 8.2K to 4.7K

IRQ14

PIORDY

ICH7 internal VR enable strap

INTVRMEN

Enable (default)

Disable

VCCRTC

R555

R555 332K/F_6

332K/F_6

ICH_INTVRMEN

R556

R556 *0/F_4

*0/F_4

ACZ_BCLK

ACZ_RST#

R551 39_4R551 39_4

R547 39_4R547 39_4

BIT_CLK_AUDIO (28)

C688

C688 *10P_4

*10P_4

ACZ_RST#_AUDIO (28)

D D

PROJECT : LE4

Size Document Number Rev

Date: Sheet

ICH7-M HOST ( 1 of 4 )

PROJECT : LE4

Quanta Computer Inc.

12 42Tuesday, March 14, 2006

PCIE_RXN0(27)

MINI CARD PCI-E

PCIE_RXP0(27)

PCIE_TXN0(27) PCIE_TXP0(27)

EXPRESS CARD (NEW CARD)

A A

+3VRUN

R309

R528

R528 10K/F_4

10K/F_4

R309 10K/F_4

10K/F_4

SPI_SCLK SPI_CE# SPI_ARB

SPI_SI SPI_SO

T130T130 T241T241 T123T123

T239T239 T125T125

R517

R517 10K/F_4

10K/F_4

Difference

B B

OC2#(31)

C591 0.1U_4C591 0.1U_4

C592 0.1U_4C592 0.1U_4

T212T212 T215T215 T83T83 T78T78

T211T211 T221T221 T210T210 T209T209

T214T214 T222T222 T84T84 T85T85

T217T217 T220T220 T86T86 T80T80

T213T213 T223T223 T87T87 T81T81

T270T270 T271T271

T131T131 T257T257

USBOC#2 USBOC#3 USBOC#4

T258T258 T122T122 T119T119

PCIE_RXN0 PCIE_RXP0 PCIE_TXN0_C PCIE_TXP0_C

PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1

PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2

PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3

PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4

PCIE_RXN5 PCIE_RXP5 PCIE_TXN5 PCIE_TXP5

USBOC#0 USBOC#1

USBOC#5 USBOC#6 USBOC#7

F26 F25 E28 E27

H26 H25 G28 G27

K26 K25

J28 J27

M26 M25

L28 L27

P26 P25 N28 N27

T25 T24 R28 R27

R2 P6 P1

P5 P2

D3 C4 D5 D4 E5 C3 A2 B3

U23D

PERn1 PERp1 PETn1 PETp1

PERn2 PERp2 PETn2 PETp2

PERn3 PERp3 PETn3 PETp3

PERn4 PERp4 PETn4 PETp4

PERn5 PERp5 PETn5 PETp5

PERn6 PERp6 PETn6 PETp6

SPI_CLK SPI_CS# SPI_ARB

SPI_MOSI SPI_MISO

OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31

ICH7-M

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI3RXN DMI3RXP DMI3TXN

PCI-Express

SPI

DMI3TXP

DMI_CLKN DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USB

USBP6N

USBP6P

USBP7N

USBP7P

USBRBIAS#

USBRBIAS

V26 V25 U28 U27

Y26 Y25 W28 W27

AB26 AB25 AA28 AA27

AD25 AD24 AC28 AC27

AE28 AE27

C25 D25

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

USB_RBIAS_PN

Place within 500 mils of ICH7

DMI_RXN0 (7)

DMI_RXP0 (7) DMI_TXN0 (7) DMI_TXP0 (7)

DMI_RXN1 (7)

DMI_RXP1 (7) DMI_TXN1 (7) DMI_TXP1 (7)

DMI_RXN2 (7)

DMI_RXP2 (7) DMI_TXN2 (7) DMI_TXP2 (7)

DMI_RXN3 (7)

DMI_RXP3 (7) DMI_TXN3 (7) DMI_TXP3 (7)

CLK_PCIE_ICH# (3) CLK_PCIE_ICH (3)

DMI_ZCOMP

T132T132

T126T126

USBP1- (27) USBP1+ (27) USBP2- (31) USBP2+ (31) USBP3- (26) USBP3+ (26) USBP4- (26) USBP4+ (26) USBP5- (26) USBP5+ (26) USBP6- (31) USBP6+ (31)

T247T247

T253T253

R540

22.6/F_4

+1.5V

R474

24.9/F_4

15/15mils

24.9/F_4

Place within 500 mils of ICH7

Bluetooth Module Mini PCI e MB USB IO USB IO USB IO USB W/O DSUB FINGER PRINT Can't this USB port

spec. for Lenovo

25mils/15mils

+3VRUN

Carama USB

3VSUS

INTG# PERR# REQ5# INTE#

REQ2# REQ1# STOP# INTB#

INTF# INTC# REQ0# IRDY#

USBOC#2 USBOC#1 USBOC#4 USBOC#0

+3VRUN

LOCK# REQ3# TRDY# FRAME#

+3VRUN

REQ4# DEVSEL# SERR#

+3VRUN

INTD# INTH# INTA#

3VSUS

USBOC#5 USBOC#3 USBOC#7 USBOC#6

6 7 8 9

RP59

8.2KX8_4

RP51

8.2KX8_4

RP54

8.2KX8_4

RP56

8.2KX8_4

5 4 3 2 1

CKL use 10Kohm

U23B

AD[0..31](24,33)

C C

T120T120

INTB#(33) INTC#(24) INTD#(24)

T252T252 T256T256 T117T117 T116T116

D D

T237T237

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

INTA# INTB# INTC# INTD#

TP_ICH_RSVD1 TP_ICH_RSVD2 TP_ICH_RSVD3 TP_ICH_RSVD4 TP_ICH_RSVD5

U23B

E18

AD0

C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12

C13 G15 G13

E12

C11

D11

A11

A10

F11

F10

AE5 AD5 AG4 AH4 AD9

E9 D9 B9 A8 A6 C7 B6 E6 D6

A3 B4 C5 B5

ICH7-M

PCI

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

PIRQA# PIRQB# PIRQC# PIRQD#

MISC

RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3#

GNT3# REQ4#/GPIO22 GNT4#/GPIO48

GPIO1/REQ5#

GPIO17/GNT5#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

GPIO2/PIRQE# GPIO3/PIRQF#

GPIO4/PIRQG#

GPIO5/PIRQH#

RSVD[6] RSVD[7] RSVD[8] RSVD[9]

MCH_SYNC#

D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8

B15 C12 D12 C15

A7 E10 B18 A12 C9 E11 B10 F15 F14 F16

C26 A9 B19

G8 F7 F8 G7

TP_ICH_RSVD6

AE9

TP_ICH_RSVD7

AG8

TP_ICH_RSVD8

AH8

RSVD9

F21

MCH_ICH_SYNC

AH20

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4# GNT4# REQ5# GNT5#_R

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY# PAR PCIRST# DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME#

PLT_RST-R# PCLK_ICH PCI_PME#

INTE# INTF# INTG# INTH#

T250T250 T242T242

REQ2# (24) GNT2# (24)

T233T233

INTE# (24)

T118T118 T235T235 T244T244

T236T236 T115T115 T114T114

R484

R484 *1K/F_4

*1K/F_4

C/BE0# (24,33) C/BE1# (24,33) C/BE2# (24,33) C/BE3# (24,33)

IRDY# (24,33) PAR (24,33) PCIRST# (24,25,33) DEVSEL# (24,33) PERR# (24,33)

SERR# (24,33) STOP# (24,33) TRDY# (24,33) FRAME# (24,33)

PCLK_ICH (3) PCI_PME# (24,33)

R497*10K_4 R497*10K_4

REQ1# (33) GNT1# (33)

3VSUS

Moved from GNT6 on ICH6 to GNT3 per ICH7 C-spec

R501

3.22.1

*1K/F_4

R513

R272

R272 *1K/F_4

*1K/F_4

R513 *1K/F_4

*1K/F_4

PLT_RST-R# (7)

+3VRUN

T113T113 T105T105 T240T240 T234T234

R292

R292 *33_4

*33_4

LE4 A-1108: +3VSUS change

C431

0.1U_4

U39

MCH_ICH_SYNC (7) PLTRST# (14,18,26,27,32)

PLT_RST-R#

2 1

TC7SH08FU

Don't connect to PCI device / Express card

0.1U_4

PLTRST#

3 5

PCLK_ICH

C439

C439 *10P_4

*10P_4

ICH7 Boot BIOS select

STRAP

GNT5# R1

LPC (default)

UNSTUFF11 UNSTUFF

PCI UNSTUFF10 STUFF

01 STUFFSPI UNSTUFF

GNT4# R2

Size Document Number Rev

Date: Sheet

ICH7-M PCI E ( 2 of 4 )

PROJECT : LE4

Quanta Computer Inc.

13 42Tuesday, March 14, 2006

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