Lenovo LE4 Schematics

1

BOM MARK
E@ EXT VGA POPULATE
I@ INV VGA POPULATE
F@ FIR MODULE POPULATE
4@ 4401 10/100M POPULATE
5@ 5788 1G POPULATE

A A

VGA NVIDA
G72M

16M*16(128MB)

PG 18,19,20,21

EXT_CRT

CRT port

LCD Panel

S-VIDEO

B B

PG 23

PG 22

PG 23

SWITCH

CIRCUIT

USB PORT 0,2,6

2

(64 Bit B/W)

(Bank*4)

EXT_LVDS
EXT_TV-OUT

PG 31

HyperThansport I/O BUS

16X PCI-E

INT_CRT
INT_LVDS
INT_TV-OUT

USB 2.0

32.768KHz

3

CPU Yonah/Merom

31W/35W

(478 Micro-FCPGA)

Link 16x16

NORTH BRIDGE

Calistoga

945PM945GM 940GML//

INTEGRADED VGA FUNCTION

1466 BGA

DMI LINK

2X
PCI-E

PG 6,7,8,9,10,11

4

PG 4,5

CPU THERMAL
SENSOR

SBLINKCLK, SBLINKCLK#

NBSRCCLK, NBSRCCLK#

DDRII
266,333 MHz

DDRII
266,333 MHz

33MHZ, 3.3V PCI

5

PG 5

CPUCLK,
CPUCLK#

HTREFCLK

OSC14M

DDRII-SODIMM1

DDRII-SODIMM2

NBSRCCLK, NBSRCCLK#

6

7

LE4 BLOCK DIAGRAM

Yonah /Calistoga /ICH-7m

14.318MHz

SYSTEM POWER MAX1993
(1.2V/NB_CORE/1.25V)

CLOCK GEN

IDTXXX/ ICSXXXX
56pins

PG 3

PG 16,17

PG 16,17

CPU CORE MAX8771
POWER VCORE 1.2V /44A

SYSTEM MAX8734
POWER(3/5V)

SYSTEM POWER MAX8632
(1.8VSUS/0.9V SMDDR_VREF)

BATT CHARGER
MAX8724

DISCHARGE

8

1

PG 41

PG 38

PG 39

PG 36

PG 35

PG 40

ICH7-M

SATA-HDD

PG 32

PATA-CDROM

PG 32

652 BGA

ATA 66/100/133

PG 12,13,14,15

Azalia

Conexant Audio

CX20549-12

C C

32.768KHz

3.3V LPC, 33MHz

LPC

PCLK_E

PG 28

MIC IN

PG 28

LAN

BCM4401/5788

PG 33

24.576MHz

CARDREADER / IEEE 1394
CONTROLLER/CF

TI 8412

PG 24,25

25MHz

IO/B

CON.

SIO (87383)

PG 26

IR module

PG 26

FAN

PG 31

PC87551L

Touchpad

Keyboard

PG 26PG 31

PG 30

FLASH

Express Card x1
MINI PICE CARD

USB PORT 1

PG 30

PG 27

MAX9755

PG 29

SPEKER

PG 29

AMP

INT_SPK

PG 29

MDC CONN

PG 27

WIRE

IO/B

RJ11
JACK

PG 24

RJ45
JACK

PG 34

3 IN 1

CARD
READER SD,
SM, MS,

PG 25

PCB STACK UP

LAYER 1 : TOP
LAYER 2 : GND

CARDBUS
SOCKET

PG 25

1394
CONN

PG 24

LAYER 3 : IN1

D D

LAYER 4 : VCC
LAYER 5 : IN2
LAYER 6 : IN3
LAYER 7 : GND
LAYER 8 : BOT

1

2

3

4

5

6

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

BLOCK DIAGRAM

BLOCK DIAGRAM

Date: Sheet

Date: Sheet

Date: Sheet

BLOCK DIAGRAM

7

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

142Wednesday, November 16, 2005

142Wednesday, November 16, 2005

142Wednesday, November 16, 2005

of

of

of

8

1A

1A

1A

1

2

Board Stack up Description

3

4

5

6

7

8

2

PCB Layers

A A

Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8

Power On Sequencing Timing Diagram

VID
VR_ON
Vcc-core

B B

CPU_UP
Vccp
Vccp_UP

TOP(Component,Other)
Ground Plane
IN1
Power Plane
IN2
IN3
Ground Plane
BOTTOM

Tsft_star_vcc

Tboot

Tvccp_up

Vboot
Tboot-vid-tr

Tcpu_up

Vid

Voltage Rails

Voltage Rails

VCC_CORE
VCCP
SMDDR_VTERM

RVCC1.5
RVCC3

VCC1.5
VCC2.5
VCC3
VCC5

1.8VSUS
3VSUS X
5VSUS

3VPCU
5VPCU
9VPCU

Core voltage for Processor
Core voltage for CPU / NB

0.9V for DDR2 Termination voltage

ON S0~S2

ON S3

X
X
X

X RVCC_ON
X

X
X
X
X

X

X

X
X

ON S4

ON S5

Control signal

VR_ON
VR_ON

MAINON

X
X

X
X

RVCCD

MAIND
MAINON
MAIND
MAIND

X
X
X

X
X
X

X
X
X

SUSON
SUSD
SUSD

XVLX
X
X

VL

5VPCU

0.726V~0.94V

Vccgmch

Tb

Tgmch_pwrgd

Te

Tcpu_pwrgd

Tc

Tf

Vcc,boot

ACIN POWER ON TIMING

ACIN

5VPCU/3VPCU

NBSWON#

PWRBTN#

Td

PLTRST#\PCIRST#

S5_ON

RSMRST#

SUSB#,SUSC#

SUSON

MAINON

VSUS,VCC

VR_ON

VCCP/1.05V

VCORE_CPU

CLK_EN#

PWROK

99ms < t 214

To ICH7

From 87541

To ICH7

From ICH7

From 87541

From 87541

From 87541

From 87541

To clock generator

To GMCH/other PCI device

Voltage Rails ON S0~S1

VCC_CORE
GMCH_VTT
SMDDR_VTERM

SMDDR_VREF

GMCH_1.5V

1.8VSUS 1.8V for DDR II voltage X
+2.5V X

3VPCU X X X X VL
3VSUS
+3V

5VPCU
5VSUS
+5V

VIN POWER SOURCE

Core voltage for Processor
Core voltage for GMCH 1.05V

0.9V for DDR II Termination voltage X MAINON

0.9V for DDR II Reference Voltage MAINON

AD25 PIRQ B/C/DREQ1# / GNT1#PCI7402

ON S3 ON S4

X
X MAINON

X

X
X

XX
X

X XXX
X X
X

XXXX

InterruptsREQ# / GNT#PCI DEVICE IDSEL#

ON S5

Control signal

VRON

MAINON
SUSON
MAINON

SUSON
MAINON

VL
SUSON
MAINON

GMCHPWRGD
CLK_ENABLE#
IMVP4_PWRGD

Dothan Power-up Timing
Specifications

RESET#

BCLK

C C

PWRGOOD

Ta

VCC

VID[5:0]

VCCP

Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild
Tc=BCLK stable to PWRGOOD assertion
Td=PWRGOOD to RESET# de-assertion time
Te=Vcc,boot vaild to PWRGOOD assertion time

D D

1

2

3

H_CPURST#

4

2ms

From ICH7 to CPU

Form GMCH to CPU

5

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

6

7

Date: Sheet of

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

System Information

System Information

System Information

1A

1A

1A

of

242Wednesday, November 16, 2005

242Wednesday, November 16, 2005

242Wednesday, November 16, 2005

8

1

2

3

4

5

6

7

8

FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33

Place these termination to close
CK410M. Cause those Pin-out is
for Current-Mode.

3

0 1 1 166 100 33

R199 49.9/F_4R199 49.9/F_4

0 1 0 200 100 33

A A

0 0 0 266 100 33
1 0 0 333 100 33
1 1 0 400 100 33
1 1 1 RSVD 100 33

CLK_EN#
PM_STPPCI#

PM_STPCPU#
TI_CLK48M
CLKUSB_48

CGCLK_SMB

CGDAT_SMB

R195 10_4R195 10_4
R190 10_4R190 10_4

SMbus address D2

LE4 A:

Changed new function
Solved sometimes can't power on

+3VRUN

CLK_EN#(14,37)

PM_STPPCI#(14)
PM_STPCPU#(14)
TI_CLK48M(25)

CLKUSB_48(14)

CPU_MCH_BSEL0(4,7)
CPU_MCH_BSEL1(4,7)
CPU_MCH_BSEL2(4,7)

LE4 B:

B B

12

12

Connect
ICH6
SMB

These are for
backdrive
issue

C C

PCLK_SMB(14,33)

Add R566

R566

R566

pull high

10K_4

10K_4

with FSA

FSA

R567

R567
*10K_4

*10K_4

PDAT_SMB

PCLK_SMB CGCLK_SMB

+3VRUN

Q32

Q32

3 1

RHU002N06

RHU002N06

+3VRUN

Q33

Q33

3 1

RHU002N06

RHU002N06

2

2

DOT96(7)
DOT96#(7)

2

4

RP33

RP33
4P2R-S-10K

4P2R-S-10K

1

3

CGDAT_SMB

CT_0229: Change
MOS to
RHU002N06 due
to layout
concern.

I@4P2R-S-33

I@4P2R-S-33

4
2

RP35

RP35

Connect DDR
Module's
SMB

CGDAT_SMB (16,17,27)PDAT_SMB(14,33)

CGCLK_SMB (16,17,27)

C323 33P_4C323 33P_4

12

12

14.318MHZ

14.318MHZ

C324 33P_4C324 33P_4

1 2
1 2

R193 8.2K/F_4R193 8.2K/F_4

1 2

R184 8.2K/F_4R184 8.2K/F_4

1 2

BG614318081

12

R201 475/F_4R201 475/F_4

Iref=5mA,

R_DOT96

3

R_DOT96#

1

Ioh=4*Iref

CT_0505: Change footprint to
TSSOP56-8_1-5 from
TSSOP56-240

Bypass CAPs need to
follow Bypass CAP.
Routing Rule, no vias
between CAP to CHIPSET
VCC Pin or GND.

120 ohms@100Mhz

L31

L31

+3VRUN

1 2

HB-1T2012-121JT_8

HB-1T2012-121JT_8

XIN

<500mil

Y2

Y2

XOUT

VDDREF_CR

CLKVDD
CLKVDD1

CLKVDD

VDD48_CR

1 2

FSA
FSB
FSC

IREF

12

C387

C387

0.047U/10V_4

0.047U/10V_4

R204 2.2R204 2.2

1 2

50
49

10
55
54

46
47

12
16
53

48
42

21
28
34

11
39

14
15

0.047U/10V_4

0.047U/10V_4

12

C573

C573

0.047U/10V_4

0.047U/10V_4

VDDA_CR

U17

U17

XTAL_IN
XTAL_OUT

VTT_PWRGD#/PD#
PCI_STOP#
CPU_STOP#

SCLK
SDATA

FSA/USB_48
FSB/TEST_MODE
FSC/TEST_SEL

VDD_REF
VDD_CPU

1

VDD_PCI_1

7

VDD_PCI_2
VDD_SRC0

VDD_SRC1
VDD_SRC2

VDD_48
IREF

DOT96
DOT96#

12

C383

C383

0.047U/10V_4

0.047U/10V_4

CK-410M

CK-410M

GND_REF

GND_48

2

51

13

0.047U/10V_4

0.047U/10V_4

12

C579

C579

12

C578

C578

38

37

VDDA

CPU2#_ITP/SRC7#

GND_PCI_26GND_SRC29GND_CPU

GND_PCI_1

45

+3VRUN

CLKVDD

12

C388

C388

4.7U/10V_8

4.7U/10V_8

VDDA_CR

12

C393

C393

4.7U/10V_8

4.7U/10V_8

VSSA

CPU2_ITP/SRC7

REF

CPU0

CPU0#

CPU1

CPU1#

SRC6

SRC6#

SRC5

SRC5#

SRC4

SRC4#

SRC3

SRC3#

SRC2

SRC2#

SRC1

SRC1#

SRC0

SRC0#

PCI5
PCI4
PCI3
PCI2

PCIF1

PCIF0/ITP_EN

ICS954206AGLFT

ICS954206AGLFT

250mA ( MAX. )

120 ohms@100Mhz

L25

L25
HB-1T2012-121JT_8

HB-1T2012-121JT_8

14M_REF

52

R_HCLK_CPU

44

R_HCLK_CPU#

43

R_HCLK_MCH

41

R_HCLK_MCH#

40

R_PCIE_VGA

36

R_PCIE_VGA#

35
33

32
31

R_MCH_3GPLL# CLK_MCH_3GPLL#

30

R_PCIE_SATA

26

R_PCIE_SATA#

27

R_PCIE_ICH

24
25

R_PCIE_MINI

22

R_PCIE_MINI#

23
19

20

R_DREFSSCLK

17

R_DREFSSCLK#

18

R_PCLK_LAN PCLK_LAN

5

R_PCLK_LPC

4

R_PCLK_LPC_DEBUG

3

R_PCLK_PCM

56

R_PCLK_SIO

9

PCIF0

8

RP34

RP34

RP39

RP39

RP43

RP43

RP47

RP47

RP48

RP48

RP44

RP44

RP40

RP40

RP37

RP37

Tie to VCC (Logic 1) is for ITP using.
Tie to GND (Logic 0) is for PCIE using.

12

12

C351

C351

0.047U/10V_4

0.047U/10V_4

R177 2.2R177 2.2

1 2

R191 1R_6R191 1R_6

1 2

LE4 A:

Del this function desgin

1 2

R200 49.9/F_4R200 49.9/F_4

1 2

R196 49.9/F_4R196 49.9/F_4

1 2

R197 49.9/F_4R197 49.9/F_4

1 2

4
2

4
2

4
2

4
2

2
4

2
4

2
4

2
4

R185 33_4R185 33_4

12

C374

C374

0.047U/10V_4

0.047U/10V_4

3

4P2R-S-33

4P2R-S-33

1
3

4P2R-S-33

4P2R-S-33

1
3

1

4P2R-S-33

4P2R-S-33

3
1

4P2R-S-33

4P2R-S-33

1
3

4P2R-S-33

4P2R-S-33

1
3

4P2R-S-33

4P2R-S-33

1
3

4P2R-S-33

4P2R-S-33

1
3

I@4P2R-S-33
R186 33_4R186 33_4
R181 33_4R181 33_4
R178 33_4R178 33_4
R182 33_4R182 33_4
R194 33_4R194 33_4

1 2

R189 *10K_4R189 *10K_4

1 2

R183 10K_4R183 10K_4

1 2

I@4P2R-S-33

1 2
1 2
1 2
1 2
1 2

12

C565

C565

0.047U/10V_4

0.047U/10V_4

12

C340

C340

4.7U/10V_8

4.7U/10V_8

12

C564

C564

0.047U/10V_4

0.047U/10V_4

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_MCH_3GPLLR_MCH_3GPLL

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_ICH
CLK_PCIE_ICH#R_PCIE_ICH#

CLK_PCIE_MINI
CLK_PCIE_MINI#

DREFSSCLK
DREFSSCLK#

PCLK_LPC
PCLK_LPC_DEBUG
PCLK_PCM
PCLK_541

PCLK_ICH

CLKVDD1

12

C326

C326

4.7U/10V_8

4.7U/10V_8

VDD48_CR

VDDREF_CR

+3VRUN

R192 33_4R192 33_4

1 2

R188 33_4R188 33_4

1 2

CLK_CPU_BCLK (4)
CLK_CPU_BCLK# (4)

CLK_MCH_BCLK (6)
CLK_MCH_BCLK# (6)

CLK_PCIE_VGA (18)
CLK_PCIE_VGA# (18)

CLK_PCIE_3GPLL (7)
CLK_PCIE_3GPLL# (7)

CLK_PCIE_SATA (12)
CLK_PCIE_SATA# (12)

CLK_PCIE_ICH (13)
CLK_PCIE_ICH# (13)

CLK_PCIE_MINI (27)
CLK_PCIE_MINI# (27)

DREFSSCLK (7)
DREFSSCLK# (7)

PCLK_LAN (33)
PCLK_LPC (26)
PCLK_LPC_DEBUG (27)
PCLK_PCM (24)
PCLK_541 (30)

PCIF1

1:100 Mhz

0:96
Mhz

PCLK_ICH (13)

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_MINI
CLK_PCIE_MINI#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DREFSSCLK
DREFSSCLK#

DOT96
DOT96#

12

C366

C366
*10P_4

*10P_4

12

0816a

1

RP42 49.9_4P2RRP42 49.9_4P2R

3

3

RP41 49.9_4P2RRP41 49.9_4P2R

1

1

RP46 49.9_4P2RRP46 49.9_4P2R

3
3

RP49 49.9_4P2RRP49 49.9_4P2R

1
3

RP45 49.9_4P2RRP45 49.9_4P2R

1
3

RP38 I@49.9_4P2RRP38 I@49.9_4P2R

1
3

RP36 I@49.9_4P2RRP36 I@49.9_4P2R

1

2
4

4
2

2
4

4
2

4
2

4
2

4
2

C361

C361
*10P_4

*10P_4

14M_SIO (26)

14M_ICH (14)

PCLK_LAN
PCLK_PCM
PCLK_541

PCLK_LPC_DEBUG

PCLK_LPC
PCLK_ICH

C359 *10P_4C359 *10P_4

1 2

C432 *10P_4C432 *10P_4

1 2

C566 *10P_4C566 *10P_4

1 2

C350 *10P_4C350 *10P_4

1 2

C355 *10P_4C355 *10P_4

1 2

C442 *10P_4C442 *10P_4

1 2

LE4 A:

Add Cap 10p reserve for EMI E-mail
093020051211

Place these termination to
close CK410M. Cause those
Pin-out is for Current-Mode.

D D

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

7

CLOCK GENERATOR

CLOCK GENERATOR

CLOCK GENERATOR

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

342Tuesday, March 14, 2006

342Tuesday, March 14, 2006

342Tuesday, March 14, 2006

of

of

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8

1A

1A

1A

1

H_A#[31:3](6)

A A

H_ADSTB#0(6)
H_REQ#[4:0](6)

B B

H_STPCLK#(12)

LE4 A:

Modfiy circuit

C C

H_A#[31:3]

H_A#[31:3]

H_ADSTB#1(6)

H_A20M#(12)
H_FERR#(12)

H_IGNNE#(12)

H_INTR(12)

H_NMI(12)

H_SMI#(12)

T188T188
T187T187
T189T189
T186T186
T44T44
T48T48
T49T49
T47T47
T59T59
T51T51

T208T208

H_STPCLK#

TP_A32#
TP_A33#
TP_A34#
TP_A35#
TP_A36#
TP_A37#
TP_A38#
TP_A39#
TP_APM0#

TP_HFPLL

XDP_TMS

XDP_TDI

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

R147 54.9/F_4R147 54.9/F_4

R149 54.9/F_4R149 54.9/F_4

M3
M1

W6

W3
W5

W2

AA1
AA4
AB2
AA3

M4

B25

J4

L4
K5
N2

J1
N3
P5
P2
L1
P4
P1
R1
L2

K3
H2
K2

J3
L5

Y2
U5
R3

U4
Y5
U2
R4
T5
T3

Y4
Y1

V4
A6

A5
C4

D5
C6
B4
A3

N5
T2
V3
B2
C3

XDP PU_R < 0.2"

XDP_BPM#5

Why BMP5 need PH ?

D D

1

XDP_TCK

XDP_TRST#

R145 54.9/F_4R145 54.9/F_4

R146 54.9/F_4R146 54.9/F_4

R148 54.9/F_4R148 54.9/F_4

2

U38A

U38A

A[3]#
A[4]#
A[5]#
A[6]#

ADDR GROUP 0

ADDR GROUP 0

A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]#
RSVD[02]#
RSVD[03]#
RSVD[04]#
RSVD[05]#
RSVD[06]#
RSVD[07]#
RSVD[08]#
RSVD[09]#
RSVD[10]#

RSVD[11]#

PZ47903-2741-01

PZ47903-2741-01

+1.05V

2

1 3

Q13

Q13
*MMBT3904

*MMBT3904

2

ADS#

BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

CONTROL

CONTROL

INIT#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

PROCHOT

THERMDA

THERMDC

THERMTRIP#

THERMH CLK

THERMH CLK

BCLK[0]
BCLK[1]

RSVD[12]#

RSVD[13]#
RSVD[14]#
RSVD[15]#
RSVD[16]#

RESERVED

RESERVED

RSVD[17]#
RSVD[18]#
RSVD[19]#
RSVD[20]#

+1.05V

+3V_S5

R223

R223
*1K_4

*1K_4

R209

R209
*10K_4

*10K_4

THERM_CPUDIE_L#PM_THRMTRIP#

3

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
B1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3
G2

G6
E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1
AC5
AA6
AB3
AB5
AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

A25

PM_THRMTRIP#

C7

A22
A21

TP_EXTBREF

T22

TP_SPARE0

D2

TP_SPARE1

F6

TP_SPARE2

D3

TP_SPARE3

C1

TP_SPARE4

AF1

TP_SPARE5TP_APM1#

D22

TP_SPARE6

C23

TP_SPARE7

C24

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

T58T58

H_ADS# (6)
H_BNR# (6)
H_BPRI# (6)

H_DEFER# (6)
H_DRDY# (6)
H_DBSY# (6)

H_BREQ#0 (6)

H_INIT# (12)
H_LOCK# (6)

H_CPURST# (6)

H_TRDY# (6)
H_HIT# (6)

H_HITM# (6)

T70T70
T67T67
T64T64
T65T65
T55T55

T228T228

CLK_CPU_BCLK (3)
CLK_CPU_BCLK# (3)

T224T224

T57T57
T61T61
T53T53
T190T190
T193T193
T76T76
T77T77
T207T207

H_RS#[2:0] (6)

LE4 A:

Modfiy circuit

T191T191

H_THERMDA (5)

H_THERMDC (5)

PM_THRMTRIP# (7,12)

T75T75

Use 1% R

XDP_TCK PD 27.4/1% ?
XDP_TRST PD 510ohm /5% ?
XDP_TDI PU 150ohm /1.05V
XDP_TMS PU 39.2/1%?
XDP_TDO PU 54.9ohm?
For ITP700

LE4 B:

del R463 in BOM

R463

R463

*0_4

*0_4

3

+1.05V

+1.05V

R458

R458
56/F_4

56/F_4

H_D#[63:0](6)

T195T195

T56T56

+1.05V

R198

R198
75_4

75_4

XDP PU_R < 0.2"

+1.05V

R468

R468
1K/F_4

1K/F_4

20/15mils

R467

R467
2K/F_4

2K/F_4

Layout note: 0.5" max for GTLREF

H_PROCHOT#

THERM_CPUDIE# (30)

4

+1.05V (5,6,7,9,10,12,15,38,40)

Near to MCH <500mils

H_D#[63:0]

H_DSTBN#0(6)
H_DSTBP#0(6)
H_DINV#0(6)

H_D#[63:0]

H_DSTBN#1(6)
H_DSTBP#1(6)
H_DINV#1(6)

H_GTLREF

R213

R213
R212

R212

CPU_MCH_BSEL0(3,7)
CPU_MCH_BSEL1(3,7)
CPU_MCH_BSEL2(3,7)

LE4 A:

Modify circuit

+1.05V

R455

R455
*330_4

*330_4

2

1 3

Q10

Q10
*MMBT3904

*MMBT3904

4

H_D#0

E22

H_D#1

F24

H_D#2

E26

H_D#3

H22

H_D#4

F23

H_D#5

G25

H_D#6

E25

H_D#7

E23

H_D#8

K24

H_D#9

G24

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25
H23
G22

J26

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

M24

N25

M26

AD26

*1K_4

*1K_4

C26

51_4

51_4

D25

B22
B23
C21

LE4 B:

Change netname

PH_PROCHOT# (37)

FANLESS#(30)

5

U38B

U38B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

TEST1
TEST2

BSEL[0]
BSEL[1]
BSEL[2]

PZ47903-2741-01

PZ47903-2741-01

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

MISC

MISC

5

DATA GRP 2

DATA GRP 2

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DATA GRP 3

DATA GRP 3

DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

2

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

PSI#

XDP_DBRESET#

AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23

AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20

R26
U26
U1
V1

E5
B5
D24
D6
D7
AE6

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

R454 *54.9/F_4R454 *54.9/F_4

R235 0/F_4R235 0/F_4

H_D#32

AA23

LE4 B:

+5VRUN

R456

R456
100K_4

100K_4

Q12

Q12
DTC144EUA

DTC144EUA

1 3

LE4 A:

Add new circuit with

6

H_D#[63:0]

H_DSTBN#2 (6)
H_DSTBP#2 (6)
H_DINV#2 (6)

25/25mils

H_DSTBN#3 (6)
H_DSTBP#3 (6)
H_DINV#3 (6)

R465

R465
R46454.9/F_4 R46454.9/F_4
R15127.4/F_4 R15127.4/F_4
R15054.9/F_4 R15054.9/F_4

ICH_DPRSTP# (12,37)
H_DPSLP# (12)

H_CPUSLP# (6,12)
PSI# (37)

27.4/F_4

27.4/F_4

H_D#[63:0]

TO VRD

Add R235 in BOM

3

Q11

Q11
E@2N7002K

1

2

E@2N7002K

H_PROCHOT#

3

1

6

2

Trcae width : ?
placement <0.5"

H_PWRGD is CMOS driving by ICH

+1.05V

Q34

Q34
2N7002K

2N7002K

SYS_RST# (14)

THERMATRIP_VGA# (19)

7

H_DPWR# (6)
H_PWRGD (12)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

LE4 A:

Modify circuit

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

Yonah/Merom (Host)

Yonah/Merom (Host)

Yonah/Merom (Host)

8

4

1A

1A

1A

442Tuesday, March 14, 2006

442Tuesday, March 14, 2006

442Tuesday, March 14, 2006

of

of

of

8

1

A A

B B

LE4 C:

+3VRUN

Q16

Q16

2

2N7002K

2N7002K

MBDATA(30,35)

MBCLK(30,35)

C C

THERM_ALERT#(14)

D D

1

3

3

THERM_ALERT#

+3VRUN

Q15

Q15
2N7002K

2N7002K

2

LM86_SMD

1

LM86__SMC

1

2

R232

R232
10K_4

10K_4

2

+1.05V

C379

C379

0.1U_4

0.1U_4

LM86_SMD (19)

LM86_SMC (19)

R231

R231
10K_4

10K_4

LM86__SMC
LM86_SMD

3

U38C

U38C

A7

VCC[001]

A9

C316

C316

0.1U_4

0.1U_4

VCC_CORE

+3VRUN

R211

R211
10K_4

10K_4

C317

C317

C381

C381

0.1U_4

0.1U_4

0.1U_4

0.1U_4

CH6222M9A01
22UF/10V/X5R

C319

C319
22U_8

22U_8

C335

C335
22U_8

22U_8

C354

C354
22U_8

22U_8

C360

C360
22U_8

22U_8

C382

C382
22U_8

22U_8

C345

C345
22U_8

22U_8

C362

C362
22U_8

22U_8

C329

C329
22U_8

22U_8

C368

C368
22U_8

22U_8

C328

C328
22U_8

22U_8

C371

C371
22U_8

22U_8

C369

C369
22U_8

22U_8

C334

C334
22U_8

22U_8

C346

C346
22U_8

22U_8

C375

C375
22U_8

22U_8

C365

C365
22U_8

22U_8

change to 0805

CRB use 8.2k PH

25mils

U19

U19

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

MAX6657/GMT-781

MAX6657/GMT-781

ADDRESS:
98H

C286

C286

0.1U_4

0.1U_4

VCC
DXP
DXN

GND

C285

C285

0.1U_4

0.1U_4

C372

C372
22U_8

22U_8

C370

C370
22U_8

22U_8

C380

C380
22U_8

22U_8

C357

C357
22U_8

22U_8

C332

C332
22U_8

22U_8

C376

C376
22U_8

22U_8

C373

C373
22U_8

22U_8

C356

C356
22U_8

22U_8

R220

R220
200_4

200_4

LM86VCC

1
2
3
5

LE4 C:

C363

C363
22U_8

22U_8

C378

C378
22U_8

22U_8

C339

C339
22U_8

22U_8

C349

C349
22U_8

22U_8

C377

C377
22U_8

22U_8

C352

C352
22U_8

22U_8

C337

C337
22U_8

22U_8

C331

C331
22U_8

22U_8

LE4 B:

Solve can't power on isuue
So change R220 pull high and
R211 pull high to thermal
circuit.(12/12/2005)

C406

C406

0.1U_4

0.1U_4

H_THERMDA

C400

C400
2200P/50V_4

2200P/50V_4

H_THERMDC

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

PZ47903-2741-01

PZ47903-2741-01

10/20mils

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCSENSE

VSSSENSE

add hardware protect

Unstall R267 , Q28 , Q26 for Intel sighting -> CPU thermal die bug /0506

3

4

AB20

VCC[68]

AB7

VCC[69]

AC7

VCC[70]

AC9

VCC[71]

AC12

VCC[72]

AC13

VCC[73]

AC15

VCC[74]

AC17

VCC[75]

AC18

VCC[76]

AD7

VCC[77]

AD9

VCC[78]

AD10

VCC[79]

AD12

VCC[80]

AD14

VCC[81]

AD15

VCC[82]

AD17

VCC[83]

AD18

VCC[84]

AE9

VCC[85]

AE10

VCC[86]

AE12

VCC[87]

AE13

VCC[88]

AE15

VCC[89]

AE17

VCC[90]

AE18

VCC[91]

AE20

VCC[92]

AF9

VCC[93]

AF10

VCC[94]

AF12

VCC[95]

AF14

VCC[96]

AF15

VCC[97]

AF17

VCC[98]

AF18

VCC[99]

VCC[100]

AF20
V6

G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26

VCCA

AD6

VID[0]

AF5

VID[1]

AE5

VID[2]

AF4

VID[3]

AE3

VID[4]

AF2

VID[5]

AE2

VID[6]

AF7
AE7

H_THERMDA (4)

H_THERMDC (4)

4

VCC_COREVCC_CORE

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

VCCSENSE
VSSSENSE

Use 1% R

SYS_SHDN#

+1.05V
VCC_CORE
+1.5V

H_VID0 (37)
H_VID1 (37)
H_VID2 (37)
H_VID3 (37)
H_VID4 (37)
H_VID5 (37)
H_VID6 (37)

5

+1.05V (4,6,7,9,10,12,15,38,40)
VCC_CORE (37,40)
+1.5V (7,9,10,13,15,27,38,40)

+1.05V

C289

C289

ESR :12m ohm

330U/2.5V/ESR-9/POS

330U/2.5V/ESR-9/POS

+

+

+1.5V

VCC_CORE

R167

R167
100_4

100_4

Connect to PWM , special layout

R162

R162
100_4

100_4

LE4 C:

Del R208

R208 *0_6R208 *0_6

+3VRUN

R224

R224
*1M/F_4

*1M/F_4

3

2

Q14

Q14
*2N7002K

*2N7002K

1

5

+1.5V

C401

C401

0.01U_4

0.01U_4

VCCSENSE (37)
VSSSENSE (37)

+3VRUN

C408

C408
*0.1U_4

*0.1U_4

C402

C402
10U/10V_8

10U/10V_8

R214

R214
*10K_4

*10K_4

2

6

A4

A8
A11
A14
A16
A19
A23
A26

B6

B8
B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3

E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

P3

LE4 A:

Add new circuit

3

with H/W solution

LE4 B:

Del R224, C408, Q14
and Q17 in BOM

Q17

Q17
*2N7002K

*2N7002K

1

6

U38D

U38D

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

PZ47903-2741-01

PZ47903-2741-01

1999_SHDN# (39)

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24

7

8

5

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

Yonah/Merom (Power/NC)

Yonah/Merom (Power/NC)

Yonah/Merom (Power/NC)

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

542Tuesday, March 14, 2006

542Tuesday, March 14, 2006

542Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

1

2

3

4

5

6

7

8

H_XRCOMP

R448

R448

24.9/F_4

24.9/F_4

A A

+1.05V

R447

R447

54.9/F_4

54.9/F_4

H_XSCOMP

+1.05V

R161

R161
221/F_4

221/F_4

R163

R163
100/F_4

100/F_4

B B

+1.05V

R449

R449

54.9/F_4

54.9/F_4

H_YSCOMP

+1.05V

15 mils/10mils

H_XSWING

C311

C311

0.1U_NPO_4

0.1U_NPO_4

Use 1% R

R450

R450
221/F_4

221/F_4

H_YSWING

R451

R451

100/F_4

100/F_4

C C

R452

R452

24.9/F_4

24.9/F_4

H_YRCOMP

C562

C562

0.1U_NPO_4

0.1U_NPO_4

15 mils/10mils

H_D#[63:0](4)

Use 1% R

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

CLK_MCH_BCLK(3)
CLK_MCH_BCLK#(3)

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

T204T204

T205T205

Short Stub < 100mils
extract from same point

K11
T10

W11

U11
T11

AB7
AA9

Y10
AB8

AA4
AA7
AA2
AA6

AA10

AA1
AB4

AC9
AB11
AC11

AB3
AC2
AD1
AD9
AC1
AD7
AC6

AB5

AD10

AD4
AC8

AG2
AG1

G1
G2

G4

W9

W7

W6

W4
W3

W5

W2

W1

F1

J1

H1

J6
H3
K2

K9
K1
K7

J8
H4

J3

T3
U7
U9

T1
T8
T4

U5
T9

T5

Y3
Y7

Y8

E1
E2
E4

Y1
U1

U35A

U35A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

H_CLKIN
H_CLKIN#

Calistoga

Calistoga

H_ADSTB#_0
H_ADSTB#_1

HOST

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#

H_VREF_0

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#

H_VREF_1

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13

J7
W8
U3
AB10

K4
T7
Y5
AC4

K3
T6
AA5
AC5

D3
D4
B3

D8
G8
B8
F8
A8

B4
E6
D6

E3
E7

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

R444 0_4R444 0_4

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#[31:3] (4)

H_ADS# (4)
H_ADSTB#0 (4)
H_ADSTB#1 (4)

H_BNR# (4)
H_BPRI# (4)
H_BREQ#0 (4)
H_CPURST# (4)
H_DBSY# (4)
H_DEFER# (4)
H_DPWR# (4)
H_DRDY# (4)

H_DINV#[3:0] (4)

H_DSTBN#[3:0] (4)

H_DSTBP#[3:0] (4)

H_HIT# (4)
H_HITM# (4)
H_LOCK# (4)

H_REQ#[4:0] (4)

H_RS#[2:0] (4)

H_CPUSLP# (4,12)
H_TRDY# (4)

+1.05V

C295

C295

0.1U_NPO_4

0.1U_NPO_4

C292

C292

0.1U_NPO_4

0.1U_NPO_4

+1.05V

R155

R155
100/F_4

100/F_4

R157

R157
200/F_4

200/F_4

+1.05V (4,5,7,9,10,12,15,38,40)

< 0.1"
Use 1% R
H_VREF :10 mils/20 mils space

H_VREF

H_VREF

6

D D

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

7

Calistoga_A (Host)

Calistoga_A (Host)

Calistoga_A (Host)

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

642Tuesday, March 14, 2006

642Tuesday, March 14, 2006

642Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

1

Check

A A

CPU_MCH_BSEL0(3,4)
CPU_MCH_BSEL1(3,4)
CPU_MCH_BSEL2(3,4)

MCH_CFG_13(9)

B B

PLT_RST-R#(13)

+3VRUN

MCH_ICH_SYNC(13)

1.8VSUS

C C

R160

R160

80.6/F_4

80.6/F_4

M_RCOMP#

15mils/10mils

M_RCOMP

R159

R159

80.6/F_4

80.6/F_4

+V1.5_PCIE
+3VRUN
SMDDR_VREF

1.8VSUS

MCH_CFG_[12:5](9)
MCH_CFG_[20:16](9)

L_IBG

R74

R74
I@1.5K_4

I@1.5K_4

D D

DELAY_VR_PWRGOOD(14,37)

L_VDDEN

T21T21
T25T25
T24T24
T72T72
T68T68
T63T63
T60T60
T66T66
T42T42
T23T23
T31T31
T173T173
T183T183
T184T184
T36T36
T185T185

T43T43
T62T62
T50T50

T46T46

T192T192
T54T54

T194T194

PM_BMBUSY#(14)
PM_EXTTS#0(16,17)
PM_EXTTS#1(14,17)

PM_THRMTRIP#(4,12)

R82

R82

100/F_4

100/F_4

R86

R86
I@100K_4

I@100K_4

1

CLK_MCH_OE#
MCH_RSVD_1
MCH_RSVD_2
MCH_RSVD_3
MCH_RSVD_4
MCH_RSVD_5
MCH_RSVD_6
MCH_RSVD_7
MCH_RSVD_8
TV_DCONSEL0
TV_DCONSEL1
MCH_RSVD_11
MCH_RSVD_12
MCH_RSVD_13
MCH_RSVD_14
MCH_RSVD_15

MCH_BSEL0

MCH_BSEL1

MCH_BSEL2

MCH_CFG_3
MCH_CFG_4
MCH_CFG_5

MCH_CFG_6
MCH_CFG_7

MCH_CFG_8

MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13

MCH_CFG_14
MCH_CFG_15

MCH_CFG_16

MCH_CFG_17

MCH_CFG_18
MCH_CFG_19
MCH_CFG_20

RST IN# MCH

T32T32
T33T33

R114 *10K/F_4R114 *10K/F_4

TP_MCH_NC0

T203T203

TP_MCH_NC1

T178T178

TP_MCH_NC2

T202T202

TP_MCH_NC3

T179T179

TP_MCH_NC4

T181T181

TP_MCH_NC5

T182T182

TP_MCH_NC6

T71T71

TP_MCH_NC7

T73T73

TP_MCH_NC8

T201T201

TP_MCH_NC9

T177T177

TP_MCH_NC10

T197T197

TP_MCH_NC11

T176T176

TP_MCH_NC12

T200T200

TP_MCH_NC13

T175T175

TP_MCH_NC14

T199T199

TP_MCH_NC15

T174T174

TP_MCH_NC16

T196T196

TP_MCH_NC17

T180T180

TP_MCH_NC18

T198T198

+3VRUN

R106 10K/F_4R106 10K/F_4

R113 *10K/F_4R113 *10K/F_4

MCH_CFG_9

+V1.5_PCIE (10)
+3VRUN (3,5,9,10,12,13,14,15,16,17,18,19,20,22,23,26,27,28,30,31,32,33,36,40,41)
SMDDR_VREF (16)

1.8VSUS (9,16,36,40,41)

MCH_CFG_[12:5]
MCH_CFG_[20:16]

LCD_ACLK-(19,22)

LCD_ACLK+(19,22)

LCD_A0-(19,22)
LCD_A0+(19,22)

LCD_A1-(19,22)
LCD_A1+(19,22)

LCD_A2-(19,22)
LCD_A2+(19,22)

H32

RSVD_0

T32

RSVD_1

R32

RSVD_2

F3

RSVD_3

F7

RSVD_4

AG11

RSVD_5

AF11

RSVD_6

H7

RSVD_7

J19

RSVD_8

K30

RSVD_9

J29

RSVD_10

A41

RSVD_11

A35

RSVD_12

A34

RSVD_13

D28

RSVD_14

D27

RSVD_15

K16

CFG_0

K18

CFG_1

J18

CFG_2

F18

CFG_3

E15

CFG_4

F15

CFG_5

E18

CFG_6

D19

CFG_7

D16

CFG_8

G16

CFG_9

E16

CFG_10

D15

CFG_11

G15

CFG_12

K15

CFG_13

C15

CFG_14

H16

CFG_15

G18

CFG_16

H15

CFG_17

J25

CFG_18

K27

CFG_19

J26

CFG_20

G28

PM_BMBUSY#

F25

PM_EXTTS#_0

H26

PM_EXTTS#_1

G6

PM_THRMTRIP#

AH33

PWROK

AH34

RSTIN#

H28

SDVO_CTRLCLK

H27

SDVO_CTRLDATA

K28

LT_RESET#

D1

NC0

C41

NC1

C1

NC2

BA41

NC3

BA40

NC4

BA39

NC5

BA3

NC6

BA2

NC7

BA1

NC8

B41

NC9

B2

NC10

AY41

NC11

AY1

NC12

AW41

NC13

AW1

NC14

A40

NC15

A4

NC16

A39

NC17

A3

NC18

PM_EXTTS#0

PM_EXTTS#1

R125 *10K/F_4R125 *10K/F_4

2

U35B

U35B

CFGRSVD

CFGRSVD

PM

PM

MISC

MISC

NC

NC

Calistoga

Calistoga

+3VRUN

RP32 I@4P2R-S-0RP32 I@4P2R-S-0

2
4

RP29 I@4P2R-S-0RP29 I@4P2R-S-0

2
4

RP31 I@4P2R-S-0RP31 I@4P2R-S-0

2
4

RP30 I@4P2R-S-0RP30 I@4P2R-S-0

2
4

1
3

1
3

1
3

1
3

2

SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP#

SM_RCOMP

DDR MUXINGCLKDMI

DDR MUXINGCLKDMI

SM_VREF_0
SM_VREF_1

D_REFCLKIN#

D_REFCLKIN

D_REFSSCLKIN#

D_REFSSCLKIN

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

LA_CLK#
LA_CLK

LA_DATAN0
LA_DATAP0

LA_DATAN1
LA_DATAP1

LA_DATAN2
LA_DATAP2

SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3

G_CLKIN#

G_CLKIN

3

SMDDR_VREF_MCH

R97 I@0_4R97 I@0_4
R101 I@0_4R101 I@0_4
R96 I@0_4R96 I@0_4
R94 I@0_4R94 I@0_4

DMI_TXN[3:0] (13)

DMI_TXP[3:0] (13)
DMI_RXN[3:0] (13)

DMI_RXP[3:0] (13)

AY35
AR1
AW7
AW40

AW35
AT1
AY7
AY40

AU20
AT20
BA29
AY29

AW13
AW12
AY21
AW21

AL20
AF10

BA13
BA12
AY20
AU21

AV9
AT9

AK1
AK41

AF33
AG33
A27
A26

RDREFSSCLK#

C40

RDREFSSCLK

D41

DMI_TXN0

AE35

DMI_TXN1

AF39

DMI_TXN2

AG35

DMI_TXN3

AH39

AC35
AE39
AF35
AG39

DMI_RXN0

AE37

DMI_RXN1

AF41

DMI_RXN2

AG37

DMI_RXN3

AH41

DMI_RXP0

AC37

DMI_RXP1

AE41

DMI_RXP2

AF37

DMI_RXP3

AG41

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

SMDDR_VREF_MCH

M_OCDCOMP_0
M_OCDCOMP_1

M_RCOMP#
M_RCOMP

SMDDR_VREF_MCH

R_DOT96#
R_DOT96

M_CLK_DDR0 (16)
M_CLK_DDR1 (16)
M_CLK_DDR2 (16)
M_CLK_DDR3 (16)

M_CLK_DDR#0 (16)
M_CLK_DDR#1 (16)
M_CLK_DDR#2 (16)
M_CLK_DDR#3 (16)

M_CKE0 (16,17)
M_CKE1 (16,17)
M_CKE2 (16,17)
M_CKE3 (16,17)

M_CS#0 (16,17)
M_CS#1 (16,17)
M_CS#2 (16,17)
M_CS#3 (16,17)

M_ODT0 (16,17)
M_ODT1 (16,17)
M_ODT2 (16,17)
M_ODT3 (16,17)

< 0.1" . 15mils/15mils space

< 0.1" . 15mils/15mils space
use 1% R

PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N15

3

C187 E@0.1U_P_4C187 E@0.1U_P_4

1 2

C525 E@0.1U_P_4C525 E@0.1U_P_4

1 2

C189 E@0.1U_P_4C189 E@0.1U_P_4

1 2

C527 E@0.1U_P_4C527 E@0.1U_P_4

1 2

C191 E@0.1U_P_4C191 E@0.1U_P_4

1 2

C529 E@0.1U_P_4C529 E@0.1U_P_4

1 2

C193 E@0.1U_P_4C193 E@0.1U_P_4

1 2

C531 E@0.1U_P_4C531 E@0.1U_P_4

1 2

C195 E@0.1U_P_4C195 E@0.1U_P_4

1 2

C533 E@0.1U_P_4C533 E@0.1U_P_4

1 2

C197 E@0.1U_P_4C197 E@0.1U_P_4

1 2

C519 E@0.1U_P_4C519 E@0.1U_P_4

1 2

C199 E@0.1U_P_4C199 E@0.1U_P_4

1 2

C521 E@0.1U_P_4C521 E@0.1U_P_4

1 2

C201 E@0.1U_P_4C201 E@0.1U_P_4

1 2

C523 E@0.1U_P_4C523 E@0.1U_P_4

1 2

4

R568 *0_4R568 *0_4
R173 0_4R173 0_4

0402

R172 10K/F_6R172 10K/F_6

R171

R171
10K/F_6

10K/F_6

0402

R569 I@0_4R569 I@0_4

Change R172 AND R171 SIZE from
0402 to 0603

LCD_BKLTCTL(22)
LCD_BLON_EC(19,22,30)

T22T22

DISP_ON(22)

LE4 B:

Use 1% R

15mils/15mils

R156

R156

*40.2/F_4

*40.2/F_4

Layout as short as passable

NC from WW45

Shall be 10K divider of 1.8V_SUS

DOT96#

DOT96
DREFSSCLK#
DREFSSCLK

Reserved
for AV

TV_COMP(23)
TV_Y/G(23)
TV_C/R(23)

CRT_B_COM(23)
CRT_G_COM(23)
CRT_R_COM(23)

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

R421 I@150/F_4R421 I@150/F_4
R425 I@150/F_4R425 I@150/F_4
R430 I@150/F_4R430 I@150/F_4

DDCCLK(23)

DDCDAT(23)

HSYNC_COM(23)

VSYNC_COM(23)

DC Blocked Cap.

Near to North Bridge

add R569

R120

R120
*40.2/F_4

*40.2/F_4

CLK_PCIE_3GPLL# (3)
CLK_PCIE_3GPLL (3)
DOT96# (3)
DOT96 (3)
DREFSSCLK# (3)
DREFSSCLK (3)

LE4 A:

As below

R428 I@0_4R428 I@0_4
R423 I@0_4R423 I@0_4
R419 I@0_4R419 I@0_4

R406 I@0_4R406 I@0_4
R411 I@0_4R411 I@0_4
R415 I@0_4R415 I@0_4

4

V_DDR_MCH_REF
SMDDR_VREF

1.8VSUS

T38T38

T34T34

EDIDCLK(22)
EDIDDATA(22)

R81 I@0_4R81 I@0_4

R591

R591

R590 I@0_6R590 I@0_6

R416 I@150/F_4R416 I@150/F_4
R412 I@150/F_4R412 I@150/F_4

R407 I@150/F_4R407 I@150/F_4
R105 I@0_4R105 I@0_4
R98 I@0_4R98 I@0_4

R116

R116
R126 I@255/F_4R126 I@255/F_4

R112 I@39/F_4R112 I@39/F_4

PCIE_MTX_GRX_C_P0
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P15

R391 I@0_4R391 I@0_4
R89 I@0_4R89 I@0_4

L_CLKCTLA

L_CLKCTLB

R119 I@0_4R119 I@0_4
R115 I@0_4R115 I@0_4

LA_CLK#

LA_CLK

T37T37
T39T39

LA_DATAN0

LA_DATAN1

LA_DATAN2

LA_DATAP0

LA_DATAP1

LA_DATAP2

T30T30
T28T28
T26T26

T29T29
T27T27
T35T35

TV_IRTN

I@0_6

I@0_6

TV_COMP1
TV_Y/G1
TV_C/R1

R124

R124

I@4.99K/F_4

I@4.99K/F_4

CRT_BLUE
CRT_GREEN
CRT_RED

I@39/F_4

I@39/F_4

LE4 B:

D32

J30
H30
H29

G26
G25

L_IBG

TVIREF

B38
C35
F32
C33
C32

A33
A32
E27
E26

C37
B35
A37

B37
B34
A36

G30

D30
F29

F30
D29
F28

A16
C18
A19

J20
B16
B18
B19

E23
D23
C22
B22
A21
B21

C26
C25

G23

J22
H23

L_VBG
L_VDDEN

CRT_RGB#

CRT_DDC_CLK
CRT_DDC_DAT

HSYNC1
CRTIREF

VSYNC1

C186 E@0.1U_P_4C186 E@0.1U_P_4

1 2

C524 E@0.1U_P_4C524 E@0.1U_P_4

1 2

C188 E@0.1U_P_4C188 E@0.1U_P_4

1 2

C526 E@0.1U_P_4C526 E@0.1U_P_4

1 2

C190 E@0.1U_P_4C190 E@0.1U_P_4

1 2

C528 E@0.1U_P_4C528 E@0.1U_P_4

1 2

C192 E@0.1U_P_4C192 E@0.1U_P_4

1 2

C530 E@0.1U_P_4C530 E@0.1U_P_4

1 2

C194 E@0.1U_P_4C194 E@0.1U_P_4

1 2

C532 E@0.1U_P_4C532 E@0.1U_P_4

1 2

C196 E@0.1U_P_4C196 E@0.1U_P_4

1 2

C518 E@0.1U_P_4C518 E@0.1U_P_4

1 2

C198 E@0.1U_P_4C198 E@0.1U_P_4

1 2

C520 E@0.1U_P_4C520 E@0.1U_P_4

1 2

C200 E@0.1U_P_4C200 E@0.1U_P_4

1 2

C522 E@0.1U_P_4C522 E@0.1U_P_4

1 2

5

add R568

L_CLKCTLA
L_CLKCTLB

U35C

U35C

L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL

LA_CLK#
LA_CLK
LB_CLK#
LB_CLK

LA_DATA#_0
LA_DATA#_1
LA_DATA#_2

LA_DATA_0
LA_DATA_1
LA_DATA_2

LB_DATA#_0
LB_DATA#_1
LB_DATA#_2

LB_DATA_0
LB_DATA_1
LB_DATA_2

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC

Calistoga

Calistoga

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

5

R108 I@10K/F_4R108 I@10K/F_4
R102 I@10K/F_4R102 I@10K/F_4

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8

EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11

LVDS

LVDS

TV

TV

VGA

VGA

EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15

EXP_A_RXP_0

EXP_A_RXP_1

EXP_A_RXP_2

EXP_A_RXP_3

EXP_A_RXP_4

EXP_A_RXP_5

EXP_A_RXP_6

EXP_A_RXP_7

EXP_A_RXP_8

EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15

EXP_A_TXP_0

EXP_A_TXP_1

EXP_A_TXP_2

EXP_A_TXP_3

EXP_A_TXP_4

EXP_A_TXP_5

EXP_A_TXP_6

EXP_A_TXP_7

EXP_A_TXP_8

EXP_A_TXP_9

EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15

PCIE_MTX_GRX_P[0..15] (18)PCIE_MTX_GRX_N[0..15] (18)

+3VRUN

6

20mils/20mils space

EXP_A_COMPX

D40
D38

PCIE_MRX_GTX_N0

F34

PCIE_MRX_GTX_N1

G38

PCIE_MRX_GTX_N2

H34

PCIE_MRX_GTX_N3

J38

PCIE_MRX_GTX_N4

L34

PCIE_MRX_GTX_N5

M38

PCIE_MRX_GTX_N6

N34

PCIE_MRX_GTX_N7

P38

PCIE_MRX_GTX_N8

R34

PCIE_MRX_GTX_N9

T38

PCIE_MRX_GTX_N10

V34

PCIE_MRX_GTX_N11

W38

PCIE_MRX_GTX_N12

Y34

PCIE_MRX_GTX_N13

AA38

PCIE_MRX_GTX_N14

AB34

PCIE_MRX_GTX_N15

AC38

PCIE_MRX_GTX_P0

D34

PCIE_MRX_GTX_P1

F38

PCIE_MRX_GTX_P2

G34

PCIE_MRX_GTX_P3

H38

PCIE_MRX_GTX_P4

J34

PCIE_MRX_GTX_P5

L38

PCIE_MRX_GTX_P6

M34

PCIE_MRX_GTX_P7

N38

PCIE_MRX_GTX_P8

P34

PCIE_MRX_GTX_P9

R38

PCIE_MRX_GTX_P10

T34

PCIE_MRX_GTX_P11

V38

PCIE_MRX_GTX_P12

W34

PCIE_MRX_GTX_P13

Y38

PCIE_MRX_GTX_P14

AA34

PCIE_MRX_GTX_P15

AB38

PCIE_MTX_GRX_C_N0

F36

PCIE_MTX_GRX_C_N1

G40

PCIE_MTX_GRX_C_N2

H36

PCIE_MTX_GRX_C_N3

J40

PCIE_MTX_GRX_C_N4

L36

PCIE_MTX_GRX_C_N5

M40

PCIE_MTX_GRX_C_N6

N36

PCIE_MTX_GRX_C_N7

P40

PCIE_MTX_GRX_C_N8

R36

PCIE_MTX_GRX_C_N9

T40

PCIE_MTX_GRX_C_N10

V36

PCIE_MTX_GRX_C_N11

W40

PCIE_MTX_GRX_C_N12

Y36

PCIE_MTX_GRX_C_N13

AA40

PCIE_MTX_GRX_C_N14

AB36

PCIE_MTX_GRX_C_N15

AC40

PCIE_MTX_GRX_C_P0

D36

PCIE_MTX_GRX_C_P1

F40

PCIE_MTX_GRX_C_P2

G36

PCIE_MTX_GRX_C_P3

H40

PCIE_MTX_GRX_C_P4

J36

PCIE_MTX_GRX_C_P5

L40

PCIE_MTX_GRX_C_P6

M36

PCIE_MTX_GRX_C_P7

N40

PCIE_MTX_GRX_C_P8

P36

PCIE_MTX_GRX_C_P9

R40

PCIE_MTX_GRX_C_P10

T36

PCIE_MTX_GRX_C_P11

V40

PCIE_MTX_GRX_C_P12

W36

PCIE_MTX_GRX_C_P13

Y40

PCIE_MTX_GRX_C_P14

AA36

PCIE_MTX_GRX_C_P15

AB40

SMDDR_VREF_MCH

6

C333

C333

0.1U_4

0.1U_4

+V1.5_PCIE

R67 24.9/F_4R67 24.9/F_4

PCIE_MRX_GTX_N[0..15] (18)

PCIE_MRX_GTX_P[0..15] (18)

R_DOT96#

R_DOT96
RDREFSSCLK#
RDREFSSCLK

940GML/945GM with clock signal

C536

C536

0.1U_4

0.1U_4

945PM with power and GND plan

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

R95 E@0_4R95 E@0_4
R107 E@0_4R107 E@0_4
R100 E@0_4R100 E@0_4
R90 E@0_4R90 E@0_4

LE4 A:

LE4 B:

Change Netname

Calistoga_B (VGA,DMI)

Calistoga_B (VGA,DMI)

Calistoga_B (VGA,DMI)

7

8

7

+1.5V

TV_COMP1
TV_Y/G1
TV_C/R1
TVIREF
TV_IRTN
TV_IRTN

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_RGB#
CRT_RGB#
CRTIREF

HSYNC1
VSYNC1

LE4 B:

945PM contact power and GND plane
945GM/940GML Contact GND plane

+1.5V

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

R576 E@0_4R576 E@0_4
R577 E@0_4R577 E@0_4
R578 E@0_4R578 E@0_4
R579 E@0_4R579 E@0_4
R580 E@0_4R580 E@0_4
R581 E@0_4R581 E@0_4

R582 E@0_4R582 E@0_4
R583 E@0_4R583 E@0_4
R584 E@0_4R584 E@0_4
R585 E@0_4R585 E@0_4
R586 E@0_4R586 E@0_4

R587 E@0_4R587 E@0_4
R588 E@0_4R588 E@0_4
R589 E@0_4R589 E@0_4

742Tuesday, March 14, 2006

742Tuesday, March 14, 2006

742Tuesday, March 14, 2006

8

of

of

of

+1.05V

1A

1A

1A

1

2

3

4

5

6

7

8

8

A A

M_B_DQ[63:0](16)

M_A_DQ[63:0](16)

B B

C C

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AJ35

AJ34
AM31
AM33

AJ36

AK35

AJ32
AH31
AN35

AP33

AR31

AP31
AN38
AM36
AM34
AN33

AK26

AL27
AM26
AN24

AK28

AL28
AM24

AP26

AP23

AL22

AP21
AN20

AL23

AP24

AP20

AT21
AR12
AR14

AP13

AP12

AT13

AT12

AL14

AL12

AK9
AN7
AK8
AK7
AP9
AN9
AT5

AL5
AY2

AW2

AP1
AN2
AV2
AT3
AN1

AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

U35D

U35D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

Calistoga

Calistoga

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_WE#

AU12
AV14
BA20

AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

AW14
AK23
AK24
AY14

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CAS#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1

M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

TP_MA_RCVENIN#
TP_MA_RCVENOUT#

M_A_BS#0 (16,17)
M_A_BS#1 (16,17)
M_A_BS#2 (16,17)
M_A_CAS# (16,17)

M_A_DM[7:0] (16)

M_A_DQS[7:0] (16)

M_A_DQS#[7:0] (16)

M_A_A[13:0] (16,17)

M_A_RAS# (16,17)

T41T41
T40T40

M_A_WE# (16,17)

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AK39

AJ37
AP39
AR41

AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40

AW38

AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31

AW31

AV29

AW29
AM19

AL19
AP14
AN14
AN17

AM16

AP15
AL15

AJ11
AH10

AJ9
AN10
AK13
AH11
AK10

AJ8
BA10

AW10

BA4

AW4

AY10

AY9

AW5

AY5
AV4
AR5
AK4
AK3
AT4
AK5

AJ5

AJ3

U35E

U35E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

Calistoga

Calistoga

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_WE#

AT24
AV23
AY28

AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

AU23
AK16
AK18
AR27

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6M_A_DQS2
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

TP_MB_RCVENIN#
TP_MB_RCVENOUT#

M_B_BS#0 (16,17)
M_B_BS#1 (16,17)
M_B_BS#2 (16,17)
M_B_CAS# (16,17)
M_B_DM[7:0] (16)

M_B_DQS[7:0] (16)

M_B_DQS#[7:0] (16)

M_B_A[13:0] (16,17)

M_B_RAS# (16,17)

T52T52
T45T45

M_B_WE# (16,17)

D D

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

7

Calistoga_C ( DDR )

Calistoga_C ( DDR )

Calistoga_C ( DDR )

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

842Tuesday, March 14, 2006

842Tuesday, March 14, 2006

842Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

5

U35G

C364

+1.05V +1.05V

D D

C C

B B

A A

C364

330U_2.5V_ESR12

330U_2.5V_ESR12

+

+

AA33

W33

P33
N33

L33
J33

AA32

Y32

W32

V32
P32
N32

M32

L32
J32

AA31

W31

V31

T31
R31
P31
N31

M31

AA30

Y30

W30

V30
U30

T30
R30
P30
N30

M30

L30

AA29

Y29

W29

V29
U29
R29
P29

M29

L29

AB28
AA28

Y28
V28
U28

T28
R28
P28
N28

M28

L28
P27
N27

M27

L27
P26
N26

L26
N25

M25

L25
P24
N24

M24
AB23
AA23

Y23
P23
N23

M23

L23
AC22
AB22

Y22

W22

P22
N22

M22

L22
AC21
AA21

W21

N21

M21

L21
AC20
AB20

Y20

W20

P20
N20

M20

L20
AB19
AA19

Y19
N19

M19

L19

N18

M18

L18

P17
N17

M17

N16

M16

L16

U35G

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110

5

VCC

VCC

Calistoga

Calistoga

VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8

VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99

VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

25mils

25mils

VCC_SM1
VCC_SM2

VCC_SM106
VCC_SM107

C214 0.47U_6C214 0.47U_6
C222 0.47U_6C222 0.47U_6

+

+

PC6

PC6
330U_2.5V_ESR12

330U_2.5V_ESR12

2.5

2.5

C253

C253

0.47U_6

0.47U_6

place C49 on AJ23 Ball

place C51 on BA15 Ball

MCH_CFG_6 shall be PH !!
depopulate R2504 if use Calistoga

25mils

C325 0.47U_6C325 0.47U_6
C310 0.47U_6C310 0.47U_6

4

C344

C344

+

+

1.8VSUS

C274

C274

C281

C281
10U_8

10U_8

10U_8

10U_8

C255

C255

0.47U_6

0.47U_6

C254

C254

0.47U_6

0.47U_6

place C50 on BA23 Ball

Have to review again
ADD Matrix in silkscreen

C269

C269

0.47U_6

0.47U_6

intel WW51 recommand

4

330U_2.5V_ESR12

330U_2.5V_ESR12

C242

C242
10U_8

10U_8

120mils

del 1.5V_AUX power planeLE4 B:

MCH_CFG_5(7)

MCH_CFG_6(7)

MCH_CFG_7(7)

MCH_CFG_9(7)

MCH_CFG_10(7)

MCH_CFG_11(7)

MCH_CFG_12(7)

MCH_CFG_13(7)

MCH_CFG_16(7)

MCH_CFG_18(7)

MCH_CFG_19(7)

MCH_CFG_20(7)

C288

C273

C273
10U_8

10U_8

C282

C282

0.1U_4

0.1U_4

+1.05V(4,5,6,7,10,12,15,38,40)

1.8VSUS(7,16,36,40,41)

C237

C237
1U_4

1U_4

10U to 1U-Allen

C252

C252

0.1U_4

0.1U_4

C288

C272

C272

0.1U_4

0.1U_4

0.1U_4

0.1U_4

C302

C302

0.1U_4

0.1U_4

+1.05V

1.8VSUS

Depopulate R2504 for Calistoga-Allen

GMCH Strap pin

R137 *2.2K_4R137 *2.2K_4

R136 *2.2K_4R136 *2.2K_4

R130 *2.2K_4R130 *2.2K_4

R129 *2.2K_4R129 *2.2K_4

R143 *2.2K_4R143 *2.2K_4

R141 2.2K_4R141 2.2K_4

R144 *2.2K_4R144 *2.2K_4

R140 *2.2K_4R140 *2.2K_4

R142 *2.2K_4R142 *2.2K_4

R117 *1K/F_4R117 *1K/F_4

R110 *1K/F_4R110 *1K/F_4

R109 *1K/F_4R109 *1K/F_4

C294

C294

0.1U_4

0.1U_4

3

+3VRUN

+3VRUN

3

+3VRUN

AD27
AC27

AB27
AA27

Y27

W27

V27
U27
T27
R27

AD26
AC26

AB26
AA26

Y26

W26

V26
U26
T26
R26

AD25
AC25

AB25
AA25

Y25

W25

V25
U25
T25
R25

AD24
AC24

AB24
AA24

Y24

W24

V24
U24
T24
R24

AD23

V23
U23
T23
R23

AD22

V22
U22
T22
R22

AD21

V21
U21
T21
R21

AD20

V20
U20
T20
R20

AD19

V19
U19
T19

AD18
AC18

AB18
AA18

Y18

W18

V18
U18
T18

U35F

U35F

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

2

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30

NCTF

NCTF

Calistoga

Calistoga

1.MCH_CFG_5 Low = DMI X2, High=DMIX4

2.MCH_CFG_6 DDR : Low =Moby Dick, High= Calistoga (Default)

3.MCH_CFG_7 CPU Strap Low=RSVD, High=Mobile CPU

4.MCH_CFG_9 PCI Exp Graphics Lane: Low =Reserved,High=Mobility

5.MCH_CFG_10 Host PLL VCC Select: Low=Reserved, High=Mobility

6.MCH_CFG_11: Low=Calistoga, High=Reserved

7.MCH_CFG_16 FSB Dynmic ODT: Low=Dynamic ODT Disabled,
High=Dynamic ODT Enabled.

8.MCH_CFG_18 VCC Select: LOW=1.05V, High=1.5V

9.MCH_CFG_19 DMI LANE Reversal:Low=Normal,High=LANES Reversed.

10.MCH_CFG_20 PCIE Backward interpoerability mode: Low= only SDVO
or PCIE x1 is operational (defaults) ,High=SDVO and PCIE x1 are
operation simultaneously via the PEG port.

VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

+1.5V

LE4 B: change +1.5V_AUX to +1.5V

100mils

2

1

9

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Calistoga_D ( POWER )

Calistoga_D ( POWER )

Calistoga_D ( POWER )

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

942Tuesday, March 14, 2006

942Tuesday, March 14, 2006

942Tuesday, March 14, 2006

of

of

1

of

1A

1A

1A

1

2

3

4

5

6

7

8

L48

L48

+V3.3_TVDAC

L52

L52
I@BLM18PG181SN1D_8

I@BLM18PG181SN1D_8

Oreginal FCM2012C-181
"CX000181008"

+1.5V

E@BLM18PG181SN1D-6_8

E@BLM18PG181SN1D-6_8

60mils

PCIE_L

RC0805

60mils

3GPLL_FB_L

L23

L23

R103

R103
0_8

0_8

+1.5V +V1.5_DPLLA

L53 10uH_8L53 10uH_8

C556

C556

0.1U_4

+

+

C516

C516
220U_6.3V

220U_6.3V

0.1U_4

C537

C537

0.1U_4

0.1U_4

C318

C318

0.1U_4

0.1U_4

C309

C309

0.1U_4

0.1U_4

+V1.5_DPLLB

+V1.5_HPLL

+V1.5_MPLL

BLM21PG220SN1D

BLM21PG220SN1D

L18

L18
1uH_6

1uH_6

+

+

C296

C296
330U

330U

L49 10uH_8L49 10uH_8

A A

L27 FCM2012C-121_8L27 FCM2012C-121_8

L26 FCM2012C-121_8L26 FCM2012C-121_8

+V1.5_PCIE

B B

C515

C515
10U_8

10U_8

R93

R93

0.5/F_6

0.5/F_6

+

+

C184

C184
330U

330U

C342

C342

10U_8

10U_8

C341

C341

10U_8

10U_8

C513

C513
10U_8

10U_8

60mils

3GPLL_FB_R

RC0805

LE4 B:

del R111,C246

change +1.5V_AUX to 1.5V

C C

10U_8

10U_8

D D

+2_5VRUN

R396 I@0_8R396 I@0_8

R401 E@0_8R401 E@0_8

R2_5VRUNA

LE4 A:

Note:

940GML/945GM contact Power plan
945PM contact GAN plan

+3VRUN +1.5V

C244

C244

C322

C248

C248

+V3.3_TVDAC

0.1U_4

0.1U_4

1

C322

0.1U_4

0.1U_4

V1_5SFOLLOW

R440

R440
I@10_4

I@10_4

R154 I@0_8R154 I@0_8

C343

C343
10U_8

10U_8

0.002 1%

RC0805

30mils

BAT54

D6 I@PDZ5.6BD6 I@PDZ5.6B

21

+V2.5_CRTDAC

+1.05V

LE4 A:

Note:

940GML/945GM contact +2.5_CRTDAC
945PM contact +1.05V

+3.3S_TVDAC_LDO

+1.5V

LE4 B:

Note:
940GML/945GM has circuit
945PM NA

C267

C267

80mils

10U_8

10U_8

+V3.3_ATVBG

C555

C555

0.1U_4

0.1U_4

+V3.3_ATVBG

C553

C553

0.1U_4

0.1U_4

+V3.3_ATVBG

C554

C554

0.1U_4

0.1U_4

+V3.3_ATVBG

C293

C293

0.022U_4

0.022U_4

C279

C279

0.022U_4

0.022U_4

C287

C287

0.022U_4

0.022U_4

+V3.3_ATVBG

+V3.3_ATVBG

+V3.3_ATVBG

+V3.3_ATVBG

LE4 A:

Note:

940GML/945GM contact +V3.3_ATVBG
945PM contact +1.5V

+1.5V

LE4 C:

Solve black screen issue
to change L48 material

Del R389

+1.5V+V1.5_3GPLL

0.002ohm/1%

+1.5V

R397 I@0_8R397 I@0_8

R398 E@0_8R398 E@0_8

LE4 A:

Note:

940GML/945GM contact Power plan
945PM contact GAN plan

R118 I@0_8R118 I@0_8

R127 E@0_8R127 E@0_8

2

R2.5VCRTDAC

+V1.5_TVDAC +1.5V

C257

C257

0.022U_4

0.022U_4

+V1.5_QTVDAC

C259

C259

0.022U_4

0.022U_4

+2_5VRUN

C234

C234

C207

C207

4.7U_6

4.7U_6

C235

C235
10U_8

10U_8

R2.5VCRTDAC

C258

C258

0.022U_4

0.022U_4

R2_5VRUNA

C213

C213

0.1U_4

0.1U_4

RV3.3_ATVBG

C271

C271

0.022U_4

0.022U_4

RV3.3_ATVBG

VCCD_LVDS

+V3.3_ATVBG

+1.5V

0.1U_4

0.1U_4

+V1.5_3GPLL

C231

C231

0.1U_4

0.1U_4

C256

C256

0.1U_4

0.1U_4

C211

C211

0.01U_4

0.01U_4

C270

C270

0.1U_4

0.1U_4

R131 I@0_8R131 I@0_8

R438 E@0_8R438 E@0_8

LE4 A:

Note:

940GML/945GM contact +V3.3_ATVBG
945PM contact +1.5V

60mils

L20

C250

C250

0.1U_4

0.1U_4

C251

C251

0.1U_4

0.1U_4

Oreginal FCM2012C-181
"CX000181008"

3

L20

FCM2012C-121_8

FCM2012C-121_8

L22

L22

FCM2012C-121_8

FCM2012C-121_8

V15_TVDAC_R

Oreginal FCM2012C-181
"CX000181008"

+V1.5_HPLL

+1.5V

40mils

+1.5V

LE4 B:

RC0805

+2_5VRUN

C205

C205

0.1U_4

0.1U_4

+2_5VRUN

+3VRUN

R400

R400

0_8

0_8

+V1.5_DPLLB

R392 I@0_8R392 I@0_8

C240

C240
10U_8

10U_8

R393 E@0_8R393 E@0_8

R2_5VRUN

+V1.5_PCIE

C233

C233

0.1U_4

0.1U_4

+V1.5_DPLLA

+V1.5_MPLL

+V3.3_ATVBG

+V3.3_ATVBG

+V3.3_ATVBG

VCCD_LVDS

+V1.5_TVDAC

+V1.5_QTVDAC

4

R2_5VRUN

R2_5VRUN

LE4 A:

Note:

940GML/945GM contact Power plan
945PM contact GAN plan

U35H

U35H

H22

VCCSYNC

C30

VCC_TXLVDS0

B30

VCC_TXLVDS1

A30

VCC_TXLVDS2

AJ41

VCC3G0

AB41

VCC3G1

Y41

VCC3G2

V41

VCC3G3

R41

VCC3G4

N41

VCC3G5

L41

VCC3G6

AC33

VCCA_3GPLL

G41

VCCA_3GBG

H41

VSSA_3GBG

F21

VCCA_CRTDAC0

E21

VCCA_CRTDAC1

G21

VSSA_CRTDAC

B26

VCCA_DPLLA

C39

VCCA_DPLLB

AF1

VCCA_HPLL

A38

VCCA_LVDS

B39

VSSA_LVDS

AF2

VCCA_MPLL

H20

VCCA_TVBG

G20

VSSA_TVBG

E19

VCCA_TVDACA0

F19

VCCA_TVDACA1

C20

VCCA_TVDACB0

D20

VCCA_TVDACB1

E20

VCCA_TVDACC0

F20

AH1
AH2

A28
B28
C28

D21
A23

B23
B25

H19

AK31
AF31
AE31
AC31

AL30

AK30

AJ30

AH30

AG30

AF30
AE30
AD30
AC30

AG29

AF29
AE29
AD29
AC29

AG28

AF28
AE28
AH22

AJ21

AH21

AJ20
AH20
AH19

P19
P16

AH15

P15

AH14

AG14

AF14
AE14

Y14
AF13
AE13
AF12
AE12
AD12

VCCA_TVDACC1
VCCD_HMPLL0

VCCD_HMPLL1
VCCD_LVDS0

VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC
VCC_HV0

VCC_HV1
VCC_HV2

VCCD_QTVDAC
VCCAUX0

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

POWER

POWER

Calistoga

Calistoga

5

VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

+1.05V

330U/2.5V/ESR-9/POS

330U/2.5V/ESR-9/POS

2005/07/14

VTTLF_CAP3

C303

C303

0.47U_6

0.47U_6

2005/07/14

VTTLF_CAP2
VTTLF_CAP1

C561

C561

0.47U_6

0.47U_6

6

+1.05V
+1.5V
+V1.5_PCIE
+2_5VRUN
+3VRUN

C283

C239

C239

0.22U_4

0.22U_4

C300

C300
I@10U_8

I@10U_8

C283

2.2U/6.3V_6

2.2U/6.3V_6

C299

C299
I@0.01U_4

I@0.01U_4

C245

C245

+

C290

+

C290

4.7U/6.3v_8

4.7U/6.3v_8

C241

C241

0.22U_4

0.22U_4

+2_5VRUN

VTT_56 , VTT_71 and 72 are
attached with 0.1u seperated .Checking

R91

R91
10_4

10_4

L19

L19
FCM2012C-121_8

FCM2012C-121_8

+3.3S_TVDAC_LDO

C312

C312

0.22U_4

0.22U_4

+1.05V (4,5,6,7,9,12,15,38,40)
+1.5V (5,7,9,13,15,27,38,40)
+V1.5_PCIE (7)
+2_5VRUN (19,22,40)
+3VRUN (3,5,7,9,12,13,14,15,16,17,18,19,20,22,23,26,27,28,30,31,32,33,36,40,41)

+1.05V

C261

C261

C249

C249

10U_8

10U_8

0.1U_4

0.1U_4

+1.05V

C264

C264

0.47U_6

0.47U_6

25mils

VCCGFOLLOW

C284

C284

0.47U_6

0.47U_6

BAT54

D1

D1
PDZ5.6B

PDZ5.6B

For TV-OUT

U16

U16

5

OUT

4

BYP

I@AAT3218

I@AAT3218

1

IN

2

GND

3

EN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

+1.05V

21

+V2.5_CRTDAC

Within 3"
of GMCH

+5VRUN

LE4 B:

Note:
940GML/945GM has circuit

C306

C306
I@1U_6

I@1U_6

Quanta Computer Inc.

Quanta Computer Inc.

Calistoga_E ( POWER2 )

Calistoga_E ( POWER2 )

Calistoga_E ( POWER2 )

945PM NA

PROJECT : LE4

PROJECT : LE4

10

10 42Tuesday, March 14, 2006

10 42Tuesday, March 14, 2006

10 42Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

5

U35I

U35I

AC41

VSS_0

AA41

VSS_1

W41

VSS_2

T41

VSS_3

P41

VSS_4

M41

VSS_5

J41

VSS_6

F41

VSS_7

AV40

VSS_8

D D

C C

B B

AP40
AN40
AK40

AJ40

AH40

AG40

AF40

AE40

B40

AY39

AW39

AV39
AR39
AN39

AJ39
AC39
AB39
AA39

Y39

W39

V39
T39
R39
P39
N39

M39

L39

J39

H39

G39

F39
D39

AT38

AM38

AH38
AG38

AF38

AE38

C38
AK37
AH37
AB37
AA37

Y37

W37

V37

T37

R37

P37

N37

M37

L37

J37

H37

G37

F37

D37
AY36

AW36

AN36
AH36
AG36

AF36
AE36
AC36

C36

B36
BA35
AV35
AR35
AH35
AB35
AA35

Y35

W35

V35

T35

R35

P35

N35

M35

L35

J35

H35

G35

F35

D35
AN34

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96

Calistoga

Calistoga

VSS

VSS

VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179

AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23

4

3

AT23
AN23
AM23
AH23
AC23

W23

K23

J23
F23
C23

AA22

K22
G22
F22
E22
D22
A22

BA21
AV21
AR21
AN21

AL21

AB21

Y21
P21
K21

J21
H21
C21

AW20

AR20

AM20

AA20

K20
B20
A20

AN19
AC19

W19

K19
G19
C19

AH18

P18
H18
D18
A18

AY17
AR17
AP17

AM17

AK17
AV16
AN16

AL16

J16
F16
C16

AN15

AM15

AK15

N15

M15

L15
B15
A15

BA14

AT14
AK14
AD14
AA14

U14
K14
H14

E14
AV13
AR13
AN13

AM13

AL13

AG13

P13

F13

D13

B13
AY12
AC12

K12

H12

E12
AD11
AA11

Y11

U35J

U35J

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272

VSS

VSS

Calistoga

Calistoga

VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

2

1

11

A A

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Calistoga_F ( VSS NCTF )

Calistoga_F ( VSS NCTF )

Calistoga_F ( VSS NCTF )

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

11 42Wednesday, November 16, 2005

11 42Wednesday, November 16, 2005

11 42Wednesday, November 16, 2005

of

of

1

of

1A

1A

1A

1

RTC

3VPCU

VCCRTC_2

R312

R312
1K/F_4

A A

5VPCU

R310

R310

4.7K_4

4.7K_4

R311

R311
15K/F_4

15K/F_4

B B

C C

1K/F_4

12

BT1

BT1
BAT_CONN

BAT_CONN

20MIL 20MIL

R316

R316

1.2K/F_4

1.2K/F_4

add RTC Bat rechargeable circuit

SATA_LED#(31)

Review current rating

+3VRUN

R334

R334

4.7K_4

4.7K_4

R496

R496

4.7K_4

4.7K_4

VCCRTC

VCCRTC

D15

D15
CH500H-40

CH500H-40

D14

D14
CH500H-40

CH500H-40

R546

R546
1M_4

1M_4

R317

R317

1K/F_4

1K/F_4

Difference

+3VRUN

R494

R494
10K_4

10K_4

C667

C667
1U_4

1U_4

C684

C684

1U/6.3V_4

1U/6.3V_4

VCCRTC_3VCCRTC_1

Internal PU

SATA_RXN0_C(32)
SATA_RXP0_C(32)

SATA_TXN0(32)
SATA_TXP0(32)

CKL:1n ~ 20nF

CLK_PCIE_SATA#(3)
CLK_PCIE_SATA(3)

25mils/15mils

Q23

Q23

2

SATA_LED#

2

Place near to Mini-door

LE4 A:

R545

R545
20K/F_4

20K/F_4

12

G1

G1
SHORT_ PAD1

SHORT_ PAD1

Internal PU

13

MMBT3904

MMBT3904

C449 3900P_P_4C449 3900P_P_4

C448 3900P_P_4C448 3900P_P_4

T245T245
T243T243
T249T249
T248T248

R289 24.9/F_4R289 24.9/F_4

Place within 500
mils of ICH7

PIORDY(32)
PDDREQ(32)

C459

C459
15P_4

15P_4

Y5

Y5

32.768KHZ

32.768KHZ

BG332768909

C457

C457
18P_4

18P_4

CLK_PCIE_SATA#
CLK_PCIE_SATA

PDIOR#(32)
PDIOW#(32)

PDDACK#(32)

IRQ14(32)

3

CKL:C1/C2: 18pF -> CL:12.5pF
C1/C: 10pF -> CL Value =

8.5pF

Change C459 value from 18p to 15p

U23A

U23A

AB1

RTXC1

AB2

RTCX2

AA3

RTCRST#

Y5

INTRUDER#

W4

INTVRMEN

W1

EE_CS

Y1

EE_SHCLK

Y2

EE_DOUT

W3

EE_DIN

V3

LAN_CLK

U3

LAN_RSTSYNC

U5

LAN_RXD0

V4

LAN_RXD1

T5

LAN_RXD2

U7

LAN_TXD0

V6

LAN_TXD1

V7

LAN_TXD2

U1

ACZ_BIT_CLK

R6

ACZ_SYNC

R5

ACZ_RST#

T2

ACZ_SDIN0

T3

ACZ_SDIN1

T1

ACZ_SDIN2

T4

ACZ_SDOUT

AF18

SATALED#

AF3

SATA0RXN

AE3

SATA0RXP

AG2

SATA0TXN

AH2

SATA0TXP

AF7

SATA2RXN

AE7

SATA2RXP

AG6

SATA2TXN

AH6

SATA2TXP

AF1

SATA_CLKN

AE1

SATA_CLKP

AH10

SATARBIASN

AG10

SATARBIASP

AF15

DIOR#

AH15

DIOW#

AF16

DDACK#

AH16

IDEIRQ

AG16

IORDY

AE15

DDREQ

ICH7-M

ICH7-M

CLK_32KX1

23

4 1

CLK_32KX2

RTCRST#

SM_INTRUDER#
ICH_INTVRMEN

T254T254
T124T124

SATA_RXN0_C
SATA_RXP0_C

SATA_RXN2_C
SATA_RXP2_C
SATA_TXN2_C
SATA_TXP2_C

SATA_BIAS

PDIOR#
PDIOW#
PDDACK#
IRQ14
PIORDY
PDDREQ

LE4 B:

R315

R315
10M_6

10M_6

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATA_TXN0_C

SATA_TXP0_C

LPCCPU

LPCCPU

RTCLAN

RTCLAN

AC-97/AZALIA

AC-97/AZALIA

SATA

SATA

IDE

IDE

4

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LDRQ1#/GPIO23

LFRAME#

A20GATE

A20M#

CPUSLP#

TP1/DPRSTP#

TP2/DPSLP#

FERR#

GPIO49/CPUPWRGD

IGNNE#

INIT3_3V#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THERMTRIP#

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0
DA1
DA2

DCS1#
DCS3#

AA6
AB5
AC4
Y6

AC3
AA5

AB3
AE22

AH28
AG27
AF24

AH25
AG26
AG24

AG22
AG21
AF22
AF25

AG23
AH24

AF23
AH22
AF26

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AH17
AE17
AF17

AE16
AD16

LAD0
LAD1
LAD2
LAD3

LDRQ#0
LDRQ#1

GATEA20

TP_H_CPUSLP#
H_DPRSTP#_R

H_DPSLP#_R

R222 *0_4R222 *0_4
R477 0_4R477 0_4

R473 0_4R473 0_4

R481 0/F_4R481 0/F_4

Difference

T97T97

RCIN#

H_SMI#_R

H_THERMTRIP_R

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDA0
PDA1
PDA2

5

LAD0 (26,27,30)
LAD1 (26,27,30)
LAD2 (26,27,30)
LAD3 (26,27,30)

LDRQ#0 (26,27,30)

T251T251

LFRAME# (26,27,30)
GATEA20 (30)

H_A20M# (4)

R479 0_4R479 0_4

PDD[15:0] (32)

PDA[2:0] (32)

PDCS1# (32)
PDCS3# (32)

R5506 close to MCH

H_CPUSLP# (4,6)

H_PWRGD (4)

H_IGNNE# (4)
H_INIT# (4)

H_INTR (4)
RCIN# (30)
H_NMI (4)

H_SMI# (4)
H_STPCLK# (4)

6

+1.05V

R226

R226

R234

R234

*56_4

*56_4

*56_4

*56_4

ICH_DPRSTP# (4,37)
H_DPSLP# (4)

Should be 2" close ICH7

R471 24.9_4R471 24.9_4

Should be 2" close ICH7

O ohm ?

ACZ_SDOUT

ACZ_SYNC

R552 39_4R552 39_4

Near To
ICH7-M

R553 39_4R553 39_4

RCIN#
GATEA20

ACZ_SDIN0

+3VRUN

R236

R236
10K_4

10K_4

+1.05V

+3VRUN

R244

R244
10K_4

10K_4

+1.05V

R230

R230
56_4

56_4

H_FERR# (4)

R472

R472
56_4

56_4

ACZ_SDIN0 (28)

ACZ_SDOUT_AUDIO (28)

C689

C689
*10P_4

*10P_4

ACZ_SYNC_AUDIO (28)

C690

C690
*10P_4

*10P_4

7

PM_THRMTRIP# (4,7)

8

12

LE4 B:

Change R496 and R334 from 8.2K to 4.7K

IRQ14

PIORDY

ICH7 internal VR
enable strap

INTVRMEN

Enable
(default)

Disable

VCCRTC

R555

R555
332K/F_6

332K/F_6

1

0

ICH_INTVRMEN

R556

R556
*0/F_4

*0/F_4

ACZ_BCLK

ACZ_RST#

R551 39_4R551 39_4

R547 39_4R547 39_4

BIT_CLK_AUDIO (28)

C688

C688
*10P_4

*10P_4

ACZ_RST#_AUDIO (28)

D D

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

7

ICH7-M HOST ( 1 of 4 )

ICH7-M HOST ( 1 of 4 )

ICH7-M HOST ( 1 of 4 )

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

12 42Tuesday, March 14, 2006

12 42Tuesday, March 14, 2006

12 42Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

1

PCIE_RXN0(27)

MINI CARD PCI-E

PCIE_RXP0(27)

PCIE_TXN0(27)
PCIE_TXP0(27)

EXPRESS CARD (NEW CARD)

A A

+3VRUN

R309

R528

R528
10K/F_4

10K/F_4

R309
10K/F_4

10K/F_4

SPI_SCLK
SPI_CE#
SPI_ARB

SPI_SI
SPI_SO

T130T130
T241T241
T123T123

T239T239
T125T125

R517

R517
10K/F_4

10K/F_4

Difference

B B

2

OC2#(31)

C591 0.1U_4C591 0.1U_4

C592 0.1U_4C592 0.1U_4

T212T212
T215T215
T83T83
T78T78

T211T211
T221T221
T210T210
T209T209

T214T214
T222T222
T84T84
T85T85

T217T217
T220T220
T86T86
T80T80

T213T213
T223T223
T87T87
T81T81

T270T270
T271T271

T131T131
T257T257

USBOC#2
USBOC#3
USBOC#4

T258T258
T122T122
T119T119

PCIE_RXN0
PCIE_RXP0
PCIE_TXN0_C
PCIE_TXP0_C

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5

USBOC#0
USBOC#1

USBOC#5
USBOC#6
USBOC#7

3

F26
F25
E28
E27

H26
H25
G28
G27

K26
K25

J28
J27

M26
M25

L28
L27

P26
P25
N28
N27

T25
T24
R28
R27

R2
P6
P1

P5
P2

D3
C4
D5
D4
E5
C3
A2
B3

U23D

U23D

PERn1
PERp1
PETn1
PETp1

PERn2
PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

ICH7-M

ICH7-M

4

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

PCI-Express

PCI-Express

SPI

SPI

DMI3TXP

DMI_CLKN
DMI_CLKP

Direct Media Interface

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USB

USB

USBP6N

USBP6P

USBP7N

USBP7P

USBRBIAS#

USBRBIAS

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2

USB_RBIAS_PN

D1

Place within 500
mils of ICH7

DMI_RXN0 (7)

DMI_RXP0 (7)
DMI_TXN0 (7)
DMI_TXP0 (7)

DMI_RXN1 (7)

DMI_RXP1 (7)
DMI_TXN1 (7)
DMI_TXP1 (7)

DMI_RXN2 (7)

DMI_RXP2 (7)
DMI_TXN2 (7)
DMI_TXP2 (7)

DMI_RXN3 (7)

DMI_RXP3 (7)
DMI_TXN3 (7)
DMI_TXP3 (7)

CLK_PCIE_ICH# (3)
CLK_PCIE_ICH (3)

DMI_ZCOMP

T132T132

T126T126

USBP1- (27)
USBP1+ (27)
USBP2- (31)
USBP2+ (31)
USBP3- (26)
USBP3+ (26)
USBP4- (26)
USBP4+ (26)
USBP5- (26)
USBP5+ (26)
USBP6- (31)
USBP6+ (31)

T247T247

T253T253

R540

R540

22.6/F_4

22.6/F_4

5

+1.5V

R474

R474

24.9/F_4

15/15mils

24.9/F_4

Place within 500
mils of ICH7

Bluetooth Module
Mini PCI e
MB USB
IO USB
IO USB
IO USB W/O DSUB
FINGER PRINT
Can't this USB port

spec. for Lenovo

25mils/15mils

+3VRUN

+3VRUN

+3VRUN

Carama USB

3VSUS

INTG#
PERR#
REQ5#
INTE#

REQ2#
REQ1#
STOP#
INTB#

INTF#
INTC#
REQ0#
IRDY#

USBOC#2
USBOC#1
USBOC#4
USBOC#0

6

7

8

13

+3VRUN

LOCK#
REQ3#
TRDY#
FRAME#

+3VRUN

REQ4#
DEVSEL#
SERR#

+3VRUN

INTD#
INTH#
INTA#

3VSUS

USBOC#5
USBOC#3
USBOC#7
USBOC#6

6
7
8
9

10

6
7
8
9

10

6
7
8
9

10

6
7
8
9

10

RP59

RP59

8.2KX8_4

8.2KX8_4

RP51

RP51

8.2KX8_4

8.2KX8_4

RP54

RP54

8.2KX8_4

8.2KX8_4

RP56

RP56

8.2KX8_4

8.2KX8_4

5
4
3
2
1

5
4
3
2
1

5
4
3
2
1

5
4
3
2
1

CKL use 10Kohm

U23B

AD[0..31](24,33)

C C

T120T120

INTB#(33)
INTC#(24)
INTD#(24)

T252T252
T256T256
T117T117
T116T116

D D

T237T237

1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

INTA#
INTB#
INTC#
INTD#

TP_ICH_RSVD1
TP_ICH_RSVD2
TP_ICH_RSVD3
TP_ICH_RSVD4
TP_ICH_RSVD5

U23B

E18

AD0

C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12

C13
G15
G13

E12

C11

D11

A11

A10

F11

F10

AE5
AD5
AG4
AH4
AD9

E9
D9
B9
A8
A6
C7
B6
E6
D6

A3
B4
C5
B5

ICH7-M

ICH7-M

PCI

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

MISC

MISC

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

2

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#

GNT3#
REQ4#/GPIO22
GNT4#/GPIO48

GPIO1/REQ5#

GPIO17/GNT5#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

GPIO2/PIRQE#
GPIO3/PIRQF#

GPIO4/PIRQG#

GPIO5/PIRQH#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

MCH_SYNC#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

TP_ICH_RSVD6

AE9

TP_ICH_RSVD7

AG8

TP_ICH_RSVD8

AH8

RSVD9

F21

MCH_ICH_SYNC

AH20

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#
GNT4#
REQ5#
GNT5#_R

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
LOCK#
SERR#
STOP#
TRDY#
FRAME#

PLT_RST-R#
PCLK_ICH
PCI_PME#

INTE#
INTF#
INTG#
INTH#

T250T250
T242T242

REQ2# (24)
GNT2# (24)

T233T233

INTE# (24)

T118T118
T235T235
T244T244

T236T236
T115T115
T114T114

R484

R484
*1K/F_4

*1K/F_4

3

C/BE0# (24,33)
C/BE1# (24,33)
C/BE2# (24,33)
C/BE3# (24,33)

IRDY# (24,33)
PAR (24,33)
PCIRST# (24,25,33)
DEVSEL# (24,33)
PERR# (24,33)

SERR# (24,33)
STOP# (24,33)
TRDY# (24,33)
FRAME# (24,33)

PCLK_ICH (3)
PCI_PME# (24,33)

R497*10K_4 R497*10K_4

12

REQ1# (33)
GNT1# (33)

3VSUS

Moved from GNT6 on ICH6
to GNT3 per ICH7 C-spec

R501

R501

3.22.1

*1K/F_4

*1K/F_4

R513

R272

R272
*1K/F_4

*1K/F_4

R513
*1K/F_4

*1K/F_4

PLT_RST-R# (7)

+3VRUN

T113T113
T105T105
T240T240
T234T234

R292

R292
*33_4

*33_4

LE4 A-1108:
+3VSUS change

C431

C431

0.1U_4

U39

U39

MCH_ICH_SYNC (7) PLTRST# (14,18,26,27,32)

PLT_RST-R#

2
1

TC7SH08FU

TC7SH08FU

Don't connect to PCI device / Express card

4

0.1U_4

PLTRST#

4

3 5

5

PCLK_ICH

C439

C439
*10P_4

*10P_4

ICH7 Boot BIOS select

STRAP

GNT5#
R1

LPC
(default)

UNSTUFF11 UNSTUFF

PCI UNSTUFF10 STUFF

01 STUFFSPI UNSTUFF

6

GNT4#
R2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

ICH7-M PCI E ( 2 of 4 )

ICH7-M PCI E ( 2 of 4 )

ICH7-M PCI E ( 2 of 4 )

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

13 42Tuesday, March 14, 2006

13 42Tuesday, March 14, 2006

13 42Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

1

2

3

4

5

6

7

8

14

+3V_S5+3V_S5

PCLK_SMB
PDAT_SMB

R376

A A

No stuff-->boot

PCIE_WAKE#

Stuff-->No boot

+3VRUN

R267

R267
*1K_4

*1K_4

ACZ_SPKR(28)

+3VRUN

R246

+3VRUN

R252

R252

8.2K/F_4

8.2K/F_4

R246
*10K/F_4

*10K/F_4

R250

R250
*10K_4

*10K_4

PM_STPPCI#(3)
PM_STPCPU#(3)

B B

Note: Connect to EC; Reserve PH/3V

THERM_ALERT#(5)

+3VRUN

PM_BMBUSY#(7)

No ASF support

R483 0_4R483 0_4
R486 0/F_4R486 0/F_4

CLKRUN#(24,26,27,30,33)

T229T229

PCIE_WAKE#(27)

SERIRQ(24,26,27,30)

T225T225

SCI#(30)

KBSMI#(30)

to Clock Gen & DIMM

PCLK_SMB(3,33)
PDAT_SMB(3,33)

T88T88
T92T92
T94T94

RI#(24,26)

SUS_STAT#(24,26,27)
SYS_RST#(4)

T96T96

T99T99
T216T216

CLKRUN#

ICH_GPO33

BOARD_ID2
PCIE_WAKE#

SERIRQ

VR_PWRGD_CK410

R491 0_4R491 0_4

R492 0/F_4R492 0/F_4

R482 2.2K_4R482 2.2K_4
R485 2.2K_4R485 2.2K_4
R498 680_4R498 680_4

LE4 B:

Change Value from 1K to 680

SYS_RST is suspend rail

U23C

PCLK_SMB
PDAT_SMB

SMB_LINK_ALERT#

SMLINK0
SMLINK1

RI#

SUS_STAT#
SYS_RST#

R499 0/F_4R499 0/F_4

SMBALERT# ICH_PWROK

PM_STPPCI_ICH#
PM_STPCPU_ICH#

BIOS_REC_R

FWH_MFG_MODE_R

RUNTIME_SCI#_R

EXTSMI#_R

U23C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0/BM_BUSY#

B23

GPIO11/SMBALERT#

AC20

GPIO18/STPPCI#

AF21

GPIO20/STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32/CLKRUN#

AC19

GPIO33/AZ_DOCK_EN#

U2

GPIO34/AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7-M

ICH7-M

RI#
SMB_LINK_ALERT#
SMLINK0
SMLINK1
EXTSMI#_R
WAKE_SCI#_R
SMBALERT#

SMB

SMB

SYS

GPIO

SYS

GPIO

GPIO

GPIO

R207 10K_4R207 10K_4
R215 10K_4R215 10K_4
R218 10K_4R218 10K_4
R221 10K_4R221 10K_4
R495 *10K_4R495 *10K_4
R459 10K_4R459 10K_4
R225 10K_4R225 10K_4

GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP

SATA

GPIO

SATA

GPIO

GPIO37/SATA3GP

Clocks

Clocks

GPIO16/DPRSLPVR

TP0/BATLOW#

PWRBTN#

Power MGT

Power MGT

LAN_RST#

RSMRST#

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39

DNBSWON#
SYS_RST# SERIRQ

PM_BATLOW#

SWI#

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23

C19
Y4
E20

A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

BOARD_ID0
BOARD_ID1
BOARD_ID3
BOARD_ID4

14M_ICH

CLKUSB_48
ICH_SUSCLK

R476 100/F_4R476 100/F_4
R480 100/F_4R480 100/F_4

PM_DPRSLPVR_R
PM_BATLOW#
DNBSWON#

R500 100K/F_4R500 100K/F_4

R460 0/F_4R460 0/F_4

SWI#
GPIO10
MXM_THERM#
WAKE_SCI#_R

LCDID0
LCDID1
GPIO24
GPIO25

R_PLTRST_DELAY# PLTRST_DELAY#

PLTRST#

R255

R255

R478 10K_4R478 10K_4
R229 10K_6R229 10K_6

R247 8.2K/F_4R247 8.2K/F_4
R270 10K_4R270 10K_4

14M_ICH (3)
CLKUSB_48 (3)

T231T231

SUSB# (30)
SUSC# (30)

T219T219

R475 100/F_4R475 100/F_4
R243 100/F_4R243 100/F_4

DNBSWON# (30)

R295 100/F_4R295 100/F_4

PLTRST# (13,18,26,27,32)

SWI# (30)

T98T98
T226T226
T79T79

LCDID0 (22)

LCDID1 (22)

T261T261

T230T230

T218T218

*E@0_4

*E@0_4

R227 0_4R227 0_4
R233 *100K/F_4R233 *100K/F_4

RSMRST#PM_RSMRST#_R

AMP_BEEP (28)

MXM_ON#: 1 -> No MXM Module
0 -> MXM Module

+3V_S5

CLKRUN#

LCDID0
LCDID1

RUNTIME_SCI#_R

SYS_RST#

RSMRST#

PM_EXTTS#1 (7,17)
PM_DPRSLPVR (37)

PM_BATLOW# (30)

RSMRST# (30)

GPIO25 /Suspend rail is a HW strap , don't pull down .

PLTRST_DELAY# (18)

R259 8.2K/F_4R259 8.2K/F_4
R248 8.2K/F_4R248 8.2K/F_4

R554 10K_4R554 10K_4
R253 10K_4R253 10K_4

R488 10K/F_4R488 10K/F_4
R238 *10K/F_4R238 *10K/F_4

R294 10K/F_4R294 10K/F_4

CKL :100Kohm PD

CLKUSB_48

+3VRUN

14M_ICH

+3VRUN

R239

R239
*10K_4

*10K_4

U21

U21

1

5

CLK_EN#(3,37)

2

43

NL17SZ14DFT2G

NL17SZ14DFT2G

VR_PWRGD_CK410

Note: External pull-up 3V

R487

R487
*10K/F_6

*10K/F_6

BIOS_REC

R489

3VPCU

R489
*0_4

*0_4

R462

R462
*10K_4

*10K_4

R470

R470
*0_4

*0_4

FWH_MFG_MODE

C C

D D

R256

R256
*0/F_4

*0/F_4

BIOS_REC_R

R597 0_4R597 0_4

USBEN_MB# (31)

LE4 B:

del R487,R256,R469 and R462in BOM

LE4 C:

Add to select power on/off for USB
function with R598 and R597

R469

R469
*0/F_4

*0/F_4

BOARD_ID0 BOARD_ID2BOARD_ID1 BOARD_ID3 BOARD_ID4

GPIO21 GPIO19 GPIO36GPIO34 GPIO37

L

1

FWH_MFG_MODE_R

L
L

R598 0_4R598 0_4

USBEN_LE3#(26)

L
LH

2

L
L

DELAY_VR_PWRGOOD(7,37)

LL

GPIO24
GPIO25

LE4 C:

Add to select power
on/off for USB
function

+3VRUN

PWROK(22,30)

LE3--L
LE4--H

3

USBEN_LS# (26)
USBEN_RJ# (26)

PWM require 6.9K
Change to 6.8K

R543 6.8K_4R543 6.8K_4

R542

R542

100K_4

100K_4

Level is incorrect !!

2
1

3VSUS

4

C675

C675

0.047U_4

0.047U_4

U41

U41

TC7SH08FU

TC7SH08FU

3 5

MXM_THERM#

ICH_PWROK

4

R251 10K_4R251 10K_4

+3VRUN +3VRUN

R541

R541
10K_4

10K_4

5

+3V_S5

R493

R265

R265
*10K/F_4

*10K/F_4

BOARD_ID0 BOARD_ID1

R512

R512
10K_4

10K_4

R493
*10K/F_4

*10K/F_4

R490

R490
10K/F_4

10K/F_4

+3VRUN

R466

R466
*10K_4

*10K_4

6

R314

R314
*10_4

*10_4

C458

C458
*10P_4

*10P_4

R461

R461
10K/F_4

10K/F_4

BOARD_ID2

R550

R550
*33_4

*33_4

C681

C681
*10P_4

*10P_4

CHECK

PATA,SATA Select

PATA Mode:
SATA Mode: 0

LE4 A:

Place close to ICH7

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

+3VRUN +3VRUN

R257

R257
*10K_4

*10K_4

BOARD_ID3 BOARD_ID4

R258

R258
10K_4

10K_4

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

ICH7-M GPIO ( 3 of 4 )

ICH7-M GPIO ( 3 of 4 )

ICH7-M GPIO ( 3 of 4 )

R268

R268
*10K_4

*10K_4

R269

R269
10K_4

10K_4

1A

1A

1A

14 42Tuesday, March 14, 2006

14 42Tuesday, March 14, 2006

14 42Tuesday, March 14, 2006

of

of

of

8

1

U23E

U23E

A4

VSS[1]

A23

VSS[2]

B1

VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

ICH7-M

ICH7-M

VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

B8
B11
B14
B17
B20
B26
B28

C2

C6

A A

B B

C C

C27
D10
D13
D18
D21
D24

E15

F12
F27
F28

G1
G2
G5
G6

G9
G14
G18
G21
G24
G25
G26

H24
H27
H28

J24
J25

J26
K24
K27
K28
L13
L15
L24
L25
L26

M3
M4

M5
M12
M13
M14
M15
M16
M17
M24
M27
M28

N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26

P12
P13
P14
P15
P16
P17
P24
P27

E1
E2
E4
E8

F3
F4
F5

H3
H4
H5

J1
J2
J5

N1
N2
N5
N6

P3
P4

VSS[98]
VSS[99]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Check with Intel for power plan.

2

15/15mils

+5VRUN +3VRUN

21

D8

R509

R509
100_4

100_4

C624

C624
1U_6

1U_6

+1.5V +1.5V_GPLL_ICH

R210

R210
0/F_4

0/F_4

+1.5V

C638

C638

0.1U_4

0.1U_4

D8
PDZ5.6B

PDZ5.6B

C608

C608

0.1U_4

0.1U_4

+1.5V +1.5V_PCIE_ICH

L63

L63

MPZ1608S101AT_6

MPZ1608S101AT_6

100 ohm ,3A

R217

R217
1_4

1_4

+3VRUN

3

+3V_S5

V5REF(1)

5VPCU 3VPCU

R557

R557
10/F_4

10/F_4

C687

C687
1U_6

1U_6

+

+

C405

C405
220U

220U

L62

L62
1uH_6

1uH_6

C589

C589

0.01U_4

0.01U_4

C628

C628

0.1U_4

0.1U_4

3VPCU

R539

R539
0/F_4

0/F_4

C674

C674

0.1U_4

0.1U_4

R544

R544
*0/F_4

*0/F_4

+1.5V

21

D16

D16
PDZ5.6B

PDZ5.6B

C599

C599

0.1U_4

0.1U_4

30mils

C650

C650

0.1U_4

0.1U_4

15/15mils

C663

C663

0.1U_4

0.1U_4

C601

C601

0.1U_4

0.1U_4

30mils

GPLL_R_LGPLL_R

C590

C590
10U_8

10U_8

T128T128
T238T238

V5REF_SUS

C595

C595

0.1U_4

0.1U_4

+3VRUN

C647

C647

0.1U_4

0.1U_4

+1.5V

C609

C609
1U/6.3V_4

1U/6.3V_4

+1.5V

C649

C649
1U_4

1U_4

3VS5_ICH_SUS3

TPVCCSUSLAN1
TPVCCSUSLAN2

4

U23F

U23F

G10

V5REF[1]

AD17

V5REF[2]

F6

V5REF_Sus

AA22

Vcc1_5_B[1]

AA23

Vcc1_5_B[2]

AB22

Vcc1_5_B[3]

AB23

Vcc1_5_B[4]

AC23

Vcc1_5_B[5]

AC24

Vcc1_5_B[6]

AC25

Vcc1_5_B[7]

AC26

Vcc1_5_B[8]

AD26

Vcc1_5_B[9]

AD27

Vcc1_5_B[10]

AD28

Vcc1_5_B[11]

D26

Vcc1_5_B[12]

D27

Vcc1_5_B[13]

D28

Vcc1_5_B[14]

E24

Vcc1_5_B[15]

E25

Vcc1_5_B[16]

E26

Vcc1_5_B[17]

F23

Vcc1_5_B[18]

F24

Vcc1_5_B[19]

G22

Vcc1_5_B[20]

G23

Vcc1_5_B[21]

H22

Vcc1_5_B[22]

H23

Vcc1_5_B[23]

J22

Vcc1_5_B[24]

J23

Vcc1_5_B[25]

K22

Vcc1_5_B[26]

K23

Vcc1_5_B[27]

L22

Vcc1_5_B[28]

L23

Vcc1_5_B[29]

M22

Vcc1_5_B[30]

M23

Vcc1_5_B[31]

N22

Vcc1_5_B[32]

N23

Vcc1_5_B[33]

P22

Vcc1_5_B[34]

P23

Vcc1_5_B[35]

R22

Vcc1_5_B[36]

R23

Vcc1_5_B[37]

R24

Vcc1_5_B[38]

R25

Vcc1_5_B[39]

R26

Vcc1_5_B[40]

T22

Vcc1_5_B[41]

T23

Vcc1_5_B[42]

T26

Vcc1_5_B[43]

T27

Vcc1_5_B[44]

T28

Vcc1_5_B[45]

U22

Vcc1_5_B[46]

U23

Vcc1_5_B[47]

V22

Vcc1_5_B[48]

V23

Vcc1_5_B[49]

W22

Vcc1_5_B[50]

W23

Vcc1_5_B[51]

Y22

Vcc1_5_B[52]

Y23

Vcc1_5_B[53]

B27

Vcc3_3[1]

AG28

VccDMIPLL

AB7

Vcc1_5_A[1]

AC6

Vcc1_5_A[2]

AC7

Vcc1_5_A[3]

AD6

Vcc1_5_A[4]

AE6

Vcc1_5_A[5]

AF5

Vcc1_5_A[6]

AF6

Vcc1_5_A[7]

AG5

Vcc1_5_A[8]

AH5

Vcc1_5_A[9]

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10

Vcc1_5_A[10]

AB9

Vcc1_5_A[11]

AC10

Vcc1_5_A[12]

AD10

Vcc1_5_A[13]

AE10

Vcc1_5_A[14]

AF10

Vcc1_5_A[15]

AF9

Vcc1_5_A[16]

AG9

Vcc1_5_A[17]

AH9

Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

AA2

VccSus1_05/VccLAN1_05[1]

Y7

VccSus1_05/VccLAN1_05[2]

ICH7-M

ICH7-M

VCC PAUX

VCC PAUX

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

VccSus3_3/VccSusHDA

VCCA3GP

VCCA3GP

ATXARX

ATXARX

5

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]

CORE

CORE

Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3/VccHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

IDE

IDE

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]

PCI

PCI

Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]

USB

USB

VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

USB CORE

USB CORE

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

V5
V1
W2
W7

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

C613

C613

0.1U_4

0.1U_4

+3VRUN

C631

C631

0.1U_4

0.1U_4

C617

C617

0.1U_4

0.1U_4

C669

C669

0.1U_4

0.1U_4

C607

C607

0.1U_4

0.1U_4

TP_ICHVCCSUS1
TP_ICHVCCSUS2

TP_ICHVCCSUS3

+1.5V

C614

C614

0.1U_4

0.1U_4

C630

C630

0.1U_4

0.1U_4

C594

C594

0.1U_4

0.1U_4

C596

C596

0.1U_4

0.1U_4

C657

C657

0.1U_4

0.1U_4

+3V_S5

+3V_S5

C623

C623

0.1U_4

0.1U_4

C639

C639

0.1U_4

0.1U_4

C640

C640

0.1U_4

0.1U_4

+3V_S5

C646

C646

0.1U_4

0.1U_4

C602

C602

0.1U_4

0.1U_4

T246T246
T82T82

T227T227

6

C604

C604

0.1U_4

0.1U_4

C605

C605

0.1U_4

0.1U_4

C600

C600

0.1U_4

0.1U_4

C610

C610

0.1U_4

0.1U_4

+3VRUN

+1.5V

+1.05V

C717

C717

10U_25V_1206

10U_25V_1206

C597

C597

0.1U_4

0.1U_4

C632

C632

0.1U_4

0.1U_4

+3VRUN

C615

C615

0.1U_4

0.1U_4

C603

C603

0.1U_4

0.1U_4

C461

C461

0.1U_4

0.1U_4

C636

C636

0.1U_4

0.1U_4

+3V_S5

C612

C612

0.1U_4

0.1U_4

VCCRTC

C692

C692

0.1U_4

0.1U_4

C664

C664

0.1U_4

0.1U_4

Oreginal 270U P/N
"CH7270LM885"

LE4 C:

Del C386
Add C718 and C719

C656

C656

0.1U_4

0.1U_4

+1.05V

C611

C611

C404

C404

0.1U_4

0.1U_4

4.7U_8

4.7U_8

+1.5V

+1.5V

C648

C648

0.1U_4

0.1U_4

C658

C658

0.1U_4

0.1U_4

7

8

15

D D

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

7

ICH-M POWER ( 4 of 4 )

ICH-M POWER ( 4 of 4 )

ICH-M POWER ( 4 of 4 )

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

15 42Tuesday, February 07, 2006

15 42Tuesday, February 07, 2006

15 42Tuesday, February 07, 2006

of

of

of

8

1A

1A

1A

1

2

3

4

5

6

7

8

+3VRUN

A A

B B

C C

D D

+3VRUN (3,5,7,9,10,12,13,14,15,17,18,19,20,22,23,26,27,28,30,31,32,33,36,40,41)

1.8VSUS (7,9,36,40,41)

M_A_DQ1
M_A_DQ5

M_A_DQS#0
M_A_DQS0

M_A_DQ2
M_A_DQ3

M_A_DQ12
M_A_DQ8

M_A_DQS#1
M_A_DQS1

M_A_DQ9
M_A_DQ15

M_A_DQ21

M_A_DQ17
M_A_DQS#2

M_A_DQS2
M_A_DQ23

M_A_DQ19
M_A_DQ24

M_A_DQ25
M_A_DM3

M_A_DQ26
M_A_DQ27

M_CKE0(7,17) M_CKE2(7,17) M_CKE3 (7,17)

M_A_BS#2(8,17)

M_A_BS#0(8,17)

M_A_WE#(8,17)

M_A_CAS#(8,17)

M_CS#1(7,17)
M_ODT1(7,17)

+3VRUN

1

M_CKE0

M_A_BS#2
M_A_A12

M_A_A9
M_A_A8

M_A_A5
M_A_A3
M_A_A1

M_A_A10
M_A_BS#0
M_A_WE#

M_A_CAS#
M_CS#1

M_ODT1
M_A_DQ35

M_A_DQS#4
M_A_DQS4

M_A_DQ38
M_A_DQ39

M_A_DQ40
M_A_DQ41

M_A_DM5
M_A_DQ42

M_A_DQ46
M_A_DQ48

M_A_DQ49

M_A_DQS#6
M_A_DQS6

M_A_DQ50

M_A_DQ56
M_A_DQ60

M_A_DM7
M_A_DQ62

CGCLK_SMB

SMDDR_VREF_DIMM

1.8VSUS

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

CN15

CN15

VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)

DDR2_SODIMM

DDR2_SODIMM

VSS46

DQ4
DQ5

VSS15

DM0

VSS5

DQ6
DQ7

VSS16

DQ12
DQ13

VSS17

DM1

VSS53

CK0

CK0#

VSS41

DQ14
DQ15

VSS54
VSS20

DQ20
DQ21
VSS6

NC3
DM2

VSS21

DQ22
DQ23

VSS24

DQ28
DQ29

VSS25

DQS#3

DQS3

VSS10

DQ30
DQ31
VSS8
CKE1

VDD8

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A15
A14

VDD11

A11

VDD4

VDD12

BA1

RAS#

S0#
VDD1
ODT0

A13
VDD6

NC2

VSS12

DQ36
DQ37

VSS28

DM4

VSS42

DQ38
DQ39

VSS55

DQ44
DQ45

VSS43

DQS#5

DQS5

VSS56

DQ46
DQ47

VSS44

DQ52
DQ53

VSS57

CK1

CK1#

VSS45

DM6

VSS32

DQ54
DQ55

VSS35

DQ60
DQ61
VSS7

DQS#7

DQS7

VSS36

DQ62
DQ63

VSS13

SA0
SA1

CLOCK 0,1 CLOCK 3,4

H 5.2 H 9.2

2

1.8VSUS 1.8VSUS 1.8VSUS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

M_A_DQ4
M_A_DQ0

M_A_DM0
M_A_DQ7

M_A_DQ6
M_A_DQ14

M_A_DQ13
M_A_DM1

M_CLK_DDR0
M_CLK_DDR#0

M_A_DQ10 M_B_DQ14
M_A_DQ11

M_A_DQ20
M_A_DQ16

PM_EXTTS#0
M_A_DM2

M_A_DQ18
M_A_DQ22

M_A_DQ28
M_A_DQ29

M_A_DQS#3
M_A_DQS3

M_A_DQ30
M_A_DQ31

M_CKE1

M_A_A11
M_A_A7
M_A_A6

M_A_A4
M_A_A2
M_A_A0

M_A_BS#1
M_A_RAS#
M_CS#0

M_ODT0
M_A_A13

M_A_DQ32

M_A_DQ36M_A_DQ37

M_A_DM4
M_A_DQ34

M_A_DQ33
M_A_DQ44

M_A_DQ45
M_A_DQS#5

M_A_DQS5
M_A_DQ43

M_A_DQ47
M_A_DQ52

M_A_DQ53

M_CLK_DDR1
M_CLK_DDR#1

M_A_DM6
M_A_DQ54

M_A_DQ55M_A_DQ51
M_A_DQ57

M_A_DQ61
M_A_DQS#7

M_A_DQS7
M_A_DQ63M_A_DQ58

M_A_DQ59

R132 10K_4R132 10K_4
R138 10K_4R138 10K_4

M_CKE1 (7,17)

M_A_BS#1 (8,17)
M_A_RAS# (8,17)
M_CS#0 (7,17)

M_ODT0 (7,17)

M_CLK_DDR1 (7)
M_CLK_DDR#1 (7)

SMbus address A0

M_A_DM[0..7] (8)
M_A_DQ[0..63] (8)
M_A_DQS[0..7] (8)
M_A_DQS#[0..7] (8)
M_A_A[0..13] (8,17)

M_CLK_DDR0 (7)
M_CLK_DDR#0 (7)

PM_EXTTS#0 (7,17)

3

CGDAT_SMB(3,17,27)
CGCLK_SMB(3,17,27)

M_B_BS#2(8,17)

M_B_BS#0(8,17)

M_B_WE#(8,17)

M_B_CAS#(8,17)

M_CS#3(7,17)
M_ODT3(7,17)

+3VRUN

M_B_DQ1
M_B_DQ5

M_B_DQS#0
M_B_DQS0

M_B_DQ2
M_B_DQ3

M_B_DQ9
M_B_DQ8 M_B_DM1

M_B_DQS#1
M_B_DQS1

M_B_DQ11
M_B_DQ10

M_B_DQ20
M_B_DQ17

M_B_DQS#2
M_B_DQS2

M_B_DQ23
M_B_DQ19

M_B_DQ29

M_B_DQ28

M_B_DM3

M_B_DQ26
M_B_DQ27

M_B_BS#2
M_B_A12

M_B_A9
M_B_A8

M_B_A5
M_B_A3
M_B_A1

M_B_A10
M_B_BS#0
M_B_WE#

M_B_CAS#
M_CS#3

M_ODT3
M_B_DQ33

M_B_DQ32
M_B_DQS#4

M_B_DQS4
M_B_DQ38

M_B_DQ34
M_B_DQ44

M_B_DQ45
M_B_DM5

M_B_DQ46

M_B_DQ43

M_B_DQS#6
M_B_DQS6

M_B_DQ54
M_B_DQ60

M_B_DQ57
M_B_DM7
M_B_DQ58

M_B_DQ59
CGDAT_SMBCGDAT_SMB

CGCLK_SMB

M_CKE2

4

SMDDR_VREF_DIMM

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

SMDDR_VREF_DIMM1.8VSUS

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

CN16

CN16

VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)

2-1734073-2

2-1734073-2

CKE 2,3CKE 0,1

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

VDD8

84

A15

86

A14

88

VDD11

PC4800 DDR2 SDRAM

PC4800 DDR2 SDRAM

90

SO-DIMM (200P)

SO-DIMM (200P)

A11

92

A7

94

A6

96

VDD4

98

A4

100

A2

102

A0

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

M_B_DQ0
M_B_DQ4

M_B_DM0
M_B_DQ7

M_B_DQ6
M_B_DQ12

M_B_DQ13

M_CLK_DDR3
M_CLK_DDR#3

M_B_DQ15

M_B_DQ16
M_B_DQ21

PM_EXTTS#0
M_B_DM2

M_B_DQ18
M_B_DQ22

M_B_DQ24
M_B_DQ25

M_B_DQS#3
M_B_DQS3

M_B_DQ31
M_B_DQ30

M_CKE3

M_B_A11
M_B_A7
M_B_A6

M_B_A4
M_B_A2
M_B_A0

M_B_BS#1
M_B_RAS#
M_CS#2

M_ODT2
M_B_A13

M_B_DQ37
M_B_DQ36

M_B_DM4
M_B_DQ39

M_B_DQ35
M_B_DQ40

M_B_DQ41
M_B_DQS#5

M_B_DQS5
M_B_DQ47

M_B_DQ42
M_B_DQ48M_B_DQ53

M_B_DQ52M_B_DQ49

M_CLK_DDR2
M_CLK_DDR#2

M_B_DM6
M_B_DQ55M_B_DQ51

M_B_DQ50
M_B_DQ56

M_B_DQ61
M_B_DQS#7

M_B_DQS7
M_B_DQ62

M_B_DQ63

R133 10K_4R133 10K_4
R139 10K_4R139 10K_4

+3VRUN

SMbus address A4

5

M_B_DM[0..7] (8)
M_B_DQ[0..63] (8)
M_B_DQS[0..7] (8)
M_B_DQS#[0..7] (8)
M_B_A[0..13] (8,17)

M_CLK_DDR3 (7)

M_CLK_DDR#3 (7)

LE4 A:

Intel errta note 0818

M_B_BS#1 (8,17)
M_B_RAS# (8,17)

M_CS#2 (7,17)

M_ODT2 (7,17)

M_CLK_DDR2 (7)
M_CLK_DDR#2 (7)

R15

R15

*10K/F_6

*10K/F_6

6

1.8VSUS

Place these Caps near So-Dimm1.

C158

C158

2.2U/6.3V_6

2.2U/6.3V_6

1.8VSUS

Place these Caps near So-Dimm1.

C183

C183

0.1U_4

0.1U_4

SMDDR_VTERM

C125

C125

0.1U_4

0.1U_4

C178

C178

2.2U/6.3V_6

2.2U/6.3V_6

C511

C511

0.1U_4

0.1U_4

C115

C115

2.2U/6.3V_6

2.2U/6.3V_6

C514

C514

X5R

2.2U/6.3V_6

2.2U/6.3V_6

C538

C538

0.1U_4

0.1U_4

+3VRUN

C12

C12

0.1U_4

0.1U_4

C278

C278

2.2U/6.3V_6

2.2U/6.3V_6

X7R

C276

C276

0.1U_4

0.1U_4

Place these Caps near So-Dimm1.
No Vias Between the Trace of PIN to
CAP.

1.8VSUS

Place these Caps near So-Dimm2.

C208

C208

2.2U/6.3V_6

2.2U/6.3V_6

1.8VSUS

SMDDR_VTERM

C534

C534

2.2U/6.3V_6

2.2U/6.3V_6

C507

C507

2.2U/6.3V_6

2.2U/6.3V_6

Place these Caps near So-Dimm1.

C517

C203

C203

0.1U_4

0.1U_4

C228

C228

0.1U_4

0.1U_4

C517

0.1U_4

0.1U_4

C124

C124

2.2U/6.3V_6

2.2U/6.3V_6

C502

C502

0.1U_4

0.1U_4

+3VRUN

C275

C275

2.2U/6.3V_6

2.2U/6.3V_6

C138

C138

0.1U_4

0.1U_4

C277

C277

0.1U_4

0.1U_4

Place these Caps near So-Dimm2.
No Vias Between the Trace of PIN to
CAP.

SMDDR_VREF_DIMM

R16

R16

Add for memory margin --Allen /0228

R18 0_4R18 0_4

*10K/F_6

*10K/F_6

SMDDR_VREF (7)

1.8VSUS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

DDR II SO-DIMM ( 200P )

DDR II SO-DIMM ( 200P )

DDR II SO-DIMM ( 200P )

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

16

16 42Tuesday, March 14, 2006

16 42Tuesday, March 14, 2006

16 42Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

1

2

3

4

5

6

7

8

17

A A

DDRII DUAL CHANNEL A,B.

DDRII A CHANNEL

M_A_A[13..0]
SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

C220

C218

C218

C128

C127

C127

0.1U_4

0.1U_4

0.1U_4

0.1U_4

B B

C128

0.1U_4

0.1U_4

0.1U_4

0.1U_4

C135

C135

C220

0.1U_4

0.1U_4

0.1U_4

0.1U_4

M_A_A[13..0] (8,16)
SMDDR_VTERM (16,36,40)

C180

C180

C209

C209

0.1U_4

0.1U_4

C204

C204

0.1U_4

0.1U_4

C182

C182

0.1U_4

0.1U_4

C139

C139

0.1U_4

0.1U_4

C157

C157

0.1U_4

0.1U_4

C219

C219

0.1U_4

0.1U_4

C212

C212

0.1U_4

0.1U_4

SMDDR_VTERM

C181

C181

0.1U_4

0.1U_4

C156

C156

0.1U_4

0.1U_4

DDRII B CHANNEL

C137

C137

0.1U_4

0.1U_4

M_B_A[13..0]

1.8VSUS
+3VRUN

C217

C217

0.1U_4

0.1U_4

M_B_A[13..0] (8,16)

1.8VSUS (7,9,16,36,40,41)
+3VRUN (3,5,7,9,10,12,13,14,15,16,18,19,20,22,23,26,27,28,30,31,32,33,36,40,41)

C179

C179

C206

C206

0.1U_4

0.1U_4

0.1U_4

0.1U_4

C134

C134

0.1U_4

0.1U_4

C133

C133

0.1U_4

0.1U_4

C129

C129

0.1U_4

0.1U_4

C225

C225

0.1U_4

0.1U_4

C223

C223

0.1U_4

0.1U_4

C224

C224

0.1U_4

0.1U_4

C221

C221

0.1U_4

0.1U_4

Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM

M_ODT0(7,16)

M_CKE1(7,16)

M_A_WE#(8,16)

M_A_BS#1(8,16)

M_A_CAS#(8,16)

M_A_BS#0(8,16)

M_ODT0
M_A_A13
M_A_A9
M_A_A8
M_A_A5
M_A_A3

M_A_A11
M_CKE1
M_A_A10
M_A_WE#
M_A_A6
M_A_A7
M_A_A2
M_A_A4

M_A_BS#1
M_A_A0
M_A_A12
M_A_A1
M_A_CAS#
M_A_BS#0

RP25 56X2RP25 56X2

1
3

RP9 56X2RP9 56X2

1
3

RP15 56X2RP15 56X2

1
3

RP5 56X2RP5 56X2

1
3

RP17 56X2RP17 56X2

1
3

RP10 56X2RP10 56X2

1
3

RP13 56X2RP13 56X2

1
3

RP18 56X2RP18 56X2

1
3

RP7 56X2RP7 56X2

1
3

RP21 56X2RP21 56X2

1
3

2
4
2
4
2
4

2
4
2
4
2
4
2
4

2
4
2
4
2
4

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

M_B_BS#1(8,16)

M_CKE2(7,16)

M_B_BS#2(8,16)

M_CS#2(7,16)

M_B_RAS#(8,16)

M_B_WE#(8,16)

M_B_CAS#(8,16)

M_B_BS#0(8,16)

M_B_BS#1
M_B_A0
M_B_A3
M_B_A1
M_B_A12
M_B_A5

M_B_A2
M_B_A4
M_B_A8
M_B_A9
M_B_A6
M_B_A7
M_CKE2
M_B_BS#2

M_CS#2
M_B_RAS#
M_B_WE#
M_B_CAS#
M_B_A10
M_B_BS#0

RP20 56X2RP20 56X2

1
3

RP16 56X2RP16 56X2

1
3

RP11 56X2RP11 56X2

1
3

RP14 56X2RP14 56X2

1
3

RP8 56X2RP8 56X2

1
3

RP12 56X2RP12 56X2

1
3

RP3 56X2RP3 56X2

1
3

RP23 56X2RP23 56X2

1
3

RP24 56X2RP24 56X2

1
3

RP19 56X2RP19 56X2

1
3

2
4
2
4
2
4

2
4
2
4
2
4
2
4

2
4
2
4
2
4

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

C C

M_CS#0(7,16)

M_A_RAS#(8,16)

M_ODT2(7,16)
M_CS#3(7,16)

M_ODT3(7,16)
M_ODT1(7,16)
M_CS#1(7,16)

M_CKE3(7,16)

M_A_BS#2(8,16)

M_CKE0(7,16)

+3VRUN

C185

R62

R62
*200_4

LM86_3V

*200_4

DDR_THERMDA

DDR_THERMDC

U9

U9

D D

PM_EXTTS#1(7,14)

Allen

CGCLK_SMB(3,16,27)
CGDAT_SMB(3,16,27)

PM_EXTTS#0(7,16)

PM_EXTTS#1

1

CGCLK_SMB
CGDAT_SMB
PM_EXTTS#0

R58 *0_4R58 *0_4

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

*LM86CIMM

*LM86CIMM

2

VCC
DXP
DXN

GND

1
2
3
5

C185
*0.1U_4

*0.1U_4

3

Uninstall

13

Q2

Q2

2

*PMST3904

*PMST3904

M_CS#0
M_A_RAS#
M_ODT2
M_B_A13
M_CS#3
M_ODT3
M_ODT1
M_CS#1
M_B_A11
M_CKE3
M_A_BS#2
M_CKE0

RP22 56X2RP22 56X2

1
3

RP28 56X2RP28 56X2

1
3

RP27 56X2RP27 56X2

1
3

RP26 56X2RP26 56X2

1
3

RP6 56X2RP6 56X2

1
3

RP4 56X2RP4 56X2

1
3

2
4
2
4
2
4
2
4
2
4
2
4

4

SMDDR_VTERM

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

6

Date: Sheet

7

DDR II TERMINATION

DDR II TERMINATION

DDR II TERMINATION

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

17 42Tuesday, March 14, 2006

17 42Tuesday, March 14, 2006

17 42Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

5

PCIE_MTX_GRX_P[0..15](7)
PCIE_MTX_GRX_N[0..15](7)

PCIE_MRX_GTX_P[0..15](7)

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P1

D D

C C

B B

A A

PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15

+1.22V_GFX_PCIE

+VCC_GFX_CORE

+1.22V_GFX_PCIE

1 2

E@BLM11A121S_6

E@BLM11A121S_6

L44

L44

12

12

12

12

L15

L15

1 2

E@BLM11A121S_6

E@BLM11A121S_6

C40

C40
E@100P_4

E@100P_4

C56

C56
E@220P_4

E@220P_4

C101

C101
E@220P_4

E@220P_4

C60

C60
E@10U_6.3V_6

E@10U_6.3V_6

12

C504

C504

E@4.7U_6.3V_6

E@4.7U_6.3V_6

C148E@0.1U_4 C148E@0.1U_4

12

C172E@0.1U_4 C172E@0.1U_4

12

C150E@0.1U_4 C150E@0.1U_4

12

C174E@0.1U_4 C174E@0.1U_4

12

C152E@0.1U_4 C152E@0.1U_4

12

C176E@0.1U_4 C176E@0.1U_4

12

C154E@0.1U_4 C154E@0.1U_4

12

C162E@0.1U_4 C162E@0.1U_4

12

C140E@0.1U_4 C140E@0.1U_4

12

C164E@0.1U_4 C164E@0.1U_4

12

C142E@0.1U_4 C142E@0.1U_4

12

C166E@0.1U_4 C166E@0.1U_4

12

C144E@0.1U_4 C144E@0.1U_4

12

C168E@0.1U_4 C168E@0.1U_4

12

C146E@0.1U_4 C146E@0.1U_4

12

C170E@0.1U_4 C170E@0.1U_4

12

12

E@4.7U_6.3V_6

E@4.7U_6.3V_6

12

C45

C45
E@0.01U_4

E@0.01U_4

12

C71

C71
E@100P_4

E@100P_4

12

C66

C66

E@0.01U_4

E@0.01U_4

12

C83

C83
E@10U_6.3V_6

E@10U_6.3V_6

PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_P15

G72_PLLVDD

12

C61

C58

C58
E@0.01U_4

E@0.01U_4

C84

C84
E@220P_4

E@220P_4

C87

C87
E@220P_4

E@220P_4

C61
E@0.1U_4

E@0.1U_4

12

C42

C42
E@100P_4

E@100P_4

12

C95

C95
E@100P_4

E@100P_4

12

C86

C86
E@220P_4

E@220P_4

C120

C120

12

12

12

PLACE NEAR BALLS

12

C501

C501

E@1U_6.3V_4

E@1U_6.3V_4

12

C503

C503

E@1U_6.3V_4

E@1U_6.3V_4

12

C107

C107

E@0.1U_4

E@0.1U_4

12

C96

C96
E@0.01U_4

E@0.01U_4

12

C68

C68
E@1U_6.3V_4

E@1U_6.3V_4

12

C99

C99
E@10U_6.3V_6

E@10U_6.3V_6

CLK_PCIE_VGA(3)
CLK_PCIE_VGA#(3)

12

C97

C97
E@0.01U_4

E@0.01U_4

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1

PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3

PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4

PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5

PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6

PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7

PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8

PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9

PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10

PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11

PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12

PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13

PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14

PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

G72_PLLVDD

PEX_PLL_AVDD

PEX_PLL_DVDD

4

AG2
AG3

AG4

AG6
AG7

AG9

AG10

AF10
AF11

AG12
AG13

AG15
AG16

AF16
AF17

AG18
AG19

AF19
AF20

AG21
AG22

AF22
AF23

AG24
AG25

AG26

AF27

W13

W15

W16

AF1

AF4
AF5

AF7
AF8

AE3
AE4

M9

J10

J11
M11
N11
R11

T11

L12
M12

T12
U12

L13
M13

T13
U13

M14

T14

L15
M15

T15
U15

L16
M16

T16
U16

M17
N17
R17

T17

AA5

AA6

J9

N9
R9
T9

Y6

U33A

U33A

PEX_RX0P
PEX_RX0N

PEX_RX1P
PEX_RX1N

PEX_RX2P
PEX_RX2N

PEX_RX3P
PEX_RX3N

PEX_RX4P
PEX_RX4N

PEX_RX5P
PEX_RX5N

PEX_RX6P
PEX_RX6N

PEX_RX7P
PEX_RX7N

PEX_RX8P
PEX_RX8N

PEX_RX9P
PEX_RX9N

PEX_RX10P
PEX_RX10N

PEX_RX11P
PEX_RX11N

PEX_RX12P
PEX_RX12N

PEX_RX13P
PEX_RX13N

PEX_RX14P
PEX_RX14N

PEX_RX15P
PEX_RX15N

Clock

Clock

PEX_REFCLK
PEX_REFCLK#

VDD_01
VDD_02
VDD_03
VDD_04
VDD_05
VDD_06
VDD_07
VDD_08
VDD_09
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36

PEX_PLLAVDD

PEX_PLLDVDD

PEX_PLLGND

G72M

G72M

PART 1 OF 4

PART 1 OF 4

P

P
C

C
I

I

-

­E

E
X

X
P

P
R

R
E

E
S

S
S

S

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

PCIE Power

PCIE Power

PEX_TX0P
PEX_TX0N

PEX_TX1P
PEX_TX1N

PEX_TX2P
PEX_TX2N

PEX_TX3P
PEX_TX3N

PEX_TX4P
PEX_TX4N

PEX_TX5P
PEX_TX5N

PEX_TX6P
PEX_TX6N

PEX_TX7P
PEX_TX7N

PEX_TX8P
PEX_TX8N

PEX_TX9P
PEX_TX9N

PEX_TX10P
PEX_TX10N

PEX_TX11P
PEX_TX11N

PEX_TX12P
PEX_TX12N

PEX_TX13P
PEX_TX13N

PEX_TX14P
PEX_TX14N

PEX_TX15P
PEX_TX15N

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT#

PEX_RST#

PEX_IOVDD_01
PEX_IOVDD_02
PEX_IOVDD_03
PEX_IOVDD_04
PEX_IOVDD_05
PEX_IOVDD_06
PEX_IOVDD_07
PEX_IOVDD_08

PEX_IOVDDQ_01
PEX_IOVDDQ_02
PEX_IOVDDQ_03
PEX_IOVDDQ_04
PEX_IOVDDQ_05
PEX_IOVDDQ_06
PEX_IOVDDQ_07
PEX_IOVDDQ_08
PEX_IOVDDQ_09
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19

VDD_LP_01
VDD_LP_02
VDD_LP_03
VDD_LP_04

VDD33_01
VDD33_02
VDD33_03
VDD33_04
VDD33_05
VDD33_06

NC_01
NC_02
NC_03
NC_04

AD5
AD6

AE6
AE7

AD7
AC7

AE9
AE10

AD10
AC10

AE12
AE13

AD13
AC13

AC15
AD15

AE15
AE16

AC18
AD18

AE18
AE19

AC21
AD21

AE21
AE22

AD22
AD23

AF25
AE25

AE24
AD24

AF13
AF14

AC6

AB10
AB11
AB14
AB15
W17
W18
AB20
AB21

AA4
AB5
AB6
AB7
AB8
AB9
AC9
AC11
AB12
AC12
AB13
AB16
AC16
AB17
AC17
AB18
AB19
AC19
AC20

W9
W10
W11
W12

J12
F13
J13
F14
J15
J16

D12
E12
F12
C13

3

PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_C_N0

PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_N1

PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_N2

PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_N3

PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_N4

PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_N5

PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_N6

PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_N7

PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_N8

PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_N9

PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_N10

PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_N11

PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_N12

PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_N13

PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_N14

PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N15

PEX_TSTCLK
PEX_TSTCLK#

R387 *E@200_4R387 *E@200_4

1 2

R59 *E@0R59 *E@0

12

12

C39

C39
E@0.1U_4

E@0.1U_4

PLACE NEAR BALLS

PCIE_MRX_GTX_N[0..15](7)

PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

C149E@0.1U_4 C149E@0.1U_4

12

C173E@0.1U_4 C173E@0.1U_4

12

C151E@0.1U_4 C151E@0.1U_4

12

C175E@0.1U_4 C175E@0.1U_4

12

C153E@0.1U_4 C153E@0.1U_4

12

C177E@0.1U_4 C177E@0.1U_4

12

C155E@0.1U_4 C155E@0.1U_4

12

C163E@0.1U_4 C163E@0.1U_4

12

C141E@0.1U_4 C141E@0.1U_4

12

C165E@0.1U_4 C165E@0.1U_4

12

C143E@0.1U_4 C143E@0.1U_4

12

C167E@0.1U_4 C167E@0.1U_4

12

C145E@0.1U_4 C145E@0.1U_4

12

C169E@0.1U_4 C169E@0.1U_4

12

C147E@0.1U_4 C147E@0.1U_4

12

C171E@0.1U_4 C171E@0.1U_4

12

PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_N15

LE4 B:

del R387,R59 in BOM

PLTRST_DELAY#R_PLTRST_DELAY#

12

C106

C106
E@0.1U_4

E@0.1U_4

12

C121

C121
E@0.022U_4

E@0.022U_4

PLACE NEAR BALLS PLACE NEAR GPU

12

C111

C111

E@10U_6.3V_6

E@10U_6.3V_6

PLACE NEAR BALLS

12

C74

C74
E@220P_4

E@220P_4

12

C54

C54
E@4700P_4

E@4700P_4

12

C85

C85
E@0.01U_4

E@0.01U_4

12

C31

C31
E@0.022U_4

E@0.022U_4

PLTRST_DELAY# (14)

12

C118

C118
E@0.022U_4

E@0.022U_4

12

C117

C117
E@0.022U_4

E@0.022U_4

+3VRUN

12

C114

C114
E@0.022U_4

E@0.022U_4

+VCC_GFX_CORE

12

C65

C65
E@0.1U_4

E@0.1U_4

12

C43

C43
E@1U_6.3V_4

E@1U_6.3V_4

12

E@10U_6.3V_6

E@10U_6.3V_6

12

C116

C116
E@0.1U_4

E@0.1U_4

12

LE4 B:

Update correct
power plane

C112

C112

C108

C108
E@0.1U_4

E@0.1U_4

2

12

C122

C122

E@1U_6.3V_4

E@1U_6.3V_4

12

C123

C123
E@1U_6.3V_4

E@1U_6.3V_4

R_PLTRST_DELAY#

+1.22V_GFX_PCIE

12

C510

C510
E@4.7U_6.3V_6

E@4.7U_6.3V_6

+1.22V_GFX_PCIE

12

C508

C508
E@4.7U_6.3V_6

E@4.7U_6.3V_6

+3VRUN

U31

U31

E@TC7SH08FU

E@TC7SH08FU

4

+1.22V_GFX_PCIE +VCC_GFX_CORE

+

+

C100

C100
330U/2.5V-12m

330U/2.5V-12m

Place near VGA chipset

2
1

3 5

R349

R349

+

+

C17

C17
330U/2.5V-12m

330U/2.5V-12m

LE4 A:

12

*E@0_4

*E@0_4

1

12

C482

C482
E@0.1U

E@0.1U

PLTRST#

PLTRST# (13,14,26,27,32)

LE4 B:

del U31, C482 in BOM

18

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

VGA G72M ( PCIe POWER )

VGA G72M ( PCIe POWER )

VGA G72M ( PCIe POWER )

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

18 42Tuesday, March 14, 2006

18 42Tuesday, March 14, 2006

18 42Tuesday, March 14, 2006

of

of

1

of

1A

1A

1A

A

Cancel R355,R367 in BOM

+3VRUN

4 4

+3VRUN

+2_5VRUN

3 3

LE4 B:

Cancel parts in BOM

12

12

12

12

R373

R373
*E@10K_4

*E@10K_4

R370

R370
E@10K_4

E@10K_4

R381

R381
E@2K/F_4

E@2K/F_4

R368

R368
E@10K_4

E@10K_4

12

R369

R369
*E@10K_4

*E@10K_4

12

R374

R374

*E@2K/F_4

*E@2K/F_4

L11 E@BLM11A121S_6L11 E@BLM11A121S_6

12

R377

R377
*E@10K_4

*E@10K_4

12

R378

R378
E@10K_4

E@10K_4

12

R375

R375

*E@2K/F_4

*E@2K/F_4

12

C33

C33
E@2.2U_6.3V_6

E@2.2U_6.3V_6

R380

R380
*E@10K_4

*E@10K_4

R379

R379
E@10K_4

E@10K_4

12

R360

R360
*E@10K_4

*E@10K_4

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3

PEX_PLL_EN_TERM100

12

R351

R351
E@10K_4

E@10K_4

12

12

LE4 B:

Cancel parts in BOM

12

R376

R376
*E@2K/F_4

*E@2K/F_4

PCI_DEVID0
PCI_DEVID1
PCI_DEVID2
PCI_DEVID3

PLLVDD

12

C30

C30
E@4700P_4

E@4700P_4

12

+3VRUN

C38

C38
E@470P_4

E@470P_4

R354 E@2K/F_4R354 E@2K/F_4
R355 *E@2K/F_4R355 *E@2K/F_4

R367 *E@2K/F_4R367 *E@2K/F_4

CFG0CFG1CFG2CFG3

128MB(16M*16)

DEV3 DEV2 DEV1 DEV0

G72M

2 2

+3VRUN

10

LCD_BLON_EC(7,22,30)

R17 E@10K_4R17 E@10K_4

1

00 0

00

1 2

R85 *E@0_4R85 *E@0_4

GFX_CORE_CNTRL

12

BIA_PWM(22)
ENVDD(22)

PANEL_BKEN(22)

GFX_CORE_CNTRL(41)

R_THERMATRIP_VGA#

PANEL_BKEN

LE4 B:

LE4 B:

Update correct power plane

SSFOUT(22)

C18 E@18P_4C18 E@18P_4

LE4 B:

Cancel
R21 in
BOM

C19 E@18P_4C19 E@18P_4

1 2

1 2

R21

R21
*E@1M_4

*E@1M_4

CLK_VGA_27M_NSS_R

1 2

BG627000131

R359 E@0_4R359 E@0_4

Y1

Y1
E@27MHz

E@27MHz
R30 E@0_4R30 E@0_4

1 2

Place R??
close to G72.

CLK_VGA_27M_OUT

1 2

R29 E@0_4R29 E@0_4

1 2

LE4 B:

Update correct power plane

12

R366

R366
E@10K_4

E@10K_4

12

R353

R353
E@10K_4

E@10K_4

I2CH_SCL
I2CH_SDA

E@10K_4

E@10K_4

12

E@10K_4

E@10K_4

12

BXTALOUT
XTALSSIN

A

BXTALOUT(22)

1 1

+3VRUN

ENVDD
PANEL_BKEN

1
3

RP2

RP2
E@4P2R-10K

E@4P2R-10K

2
4

R19

R19
R20

R20

R352

R352
E@2K/F_4

E@2K/F_4

1 2

T152T152
T153T153
T154T154
T148T148

1 2

T162T162

1 2
1 2

T166T166
T149T149

T157T157

T159T159
T160T160

T161T161

T155T155

+3VRUN

+3VRUN

T2T2
T158T158

T150T150
T145T145

T146T146
T1T1
T147T147
T151T151

Maximum down
spread of -3%

+3VRUN

+3VRUN

PEX_PLL_EN_TERM100
SUB_VENDOR

R382 E@10K_4R382 E@10K_4

C32 E@0.1U_4C32 E@0.1U_4

C46 E@0.1U_4C46 E@0.1U_4

MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND

T3T3

GFX_CORE_CNTRL

R386 E@10K_4R386 E@10K_4

T169T169
T171T171
T172T172

R388 E@10K_4R388 E@10K_4
R28 E@10K_4R28 E@10K_4

R361 *E@0_4R361 *E@0_4

1 2

12

C481

C481
E@0.1U_4

E@0.1U_4

LE4 B:

Del R361, C481 in BOM

3GIO_ADR_0
3GIO_ADR_1

3GIO_ADR_2

RAM_CFG0
RAM_CFG1

PCI_DEVID2
PCI_DEVID0
PCI_DEVID1

MOBILE_GPIO
RAM_CFG2
RAM_CFG3

PCI_DEVID3

12

12

12

R363E@10K_4R363E@10K_4

R356 E@10K_4R356 E@10K_4

PANEL_BKEN

1 2

R357 E@0_4R357 E@0_4

VGA_THERMDN
VGA_THERMDP

1 2
1 2

ENVDD

PLLVDD

XTALSSIN
XTALIN
BXTALOUT

1 2

I2CH_SCL
I2CH_SDA

12

B

U33B

U33B

A2

MIO_A_D0

B3

MIO_A_D1

A3

MIO_A_D2

D4

MIO_A_D3

A4

MIO_A_D4

B4

MIO_A_D5

B6

MIO_A_D6

P4

MIO_A_D7

C6

MIO_A_D8

G5

MIO_A_D9

V4

MIO_A_D10

C4

MIO_A_HSYNC

G2

MIO_B_D0

G3

MIO_B_D1

J2

MIO_B_D2

J1

MIO_B_D3

K4

MIO_B_D4

K1

MIO_B_D5

M2

MIO_B_D6

M1

MIO_B_D7

N1

MIO_B_D8

N2

MIO_B_D9

N3

MIO_B_D10

R3

MIO_B_D11

F2

MIO_B_CTL3

G1

MIO_B_DE

G4

MIO_B_HSYNC

F1

MIO_B_VSYNC

R2

MIO_B_CLKIN

K2

MIO_B_CLKOUT

K3

MIO_B_CLKOUT#

F6

MIO_A_VDDQ1

G6

MIO_A_VDDQ2

J6

MIO_A_VDDQ3

K5

MIO_B_VDDQ1

K6

MIO_B_VDDQ2

L6

MIO_B_VDDQ3

J5

MIO_B_CAL_PD_VDDQ

M3

MIO_B_CAL_PU_GND

J4

MIO_B_VREF

12

A9

GPIO[0]

D9

GPIO[1]

A10

GPIO[2]

B10

GPIO[3]

C10

GPIO[4]

C12

GPIO[5]

B12

GPIO[6]

A12

GPIO[7]

A13

GPIO[8]

B13

GPIO[9]

B15

GPIO[10]

A15

GPIO[11]

B16

GPIO[12]

C9

THERMDN

B9

THERMDP

H4

PLLVDD

H5

PLLGND

C1

XTALSSIN

B1

XTALIN

C3

XTALOUTBUFF

C2

XTALOUT

AE27

JTAG_TCK

AD26

JTAG_TMS

AD27

JTAG_TDI

AE26

JTAG_TDO

AD25

JTAG_TRST#

D1

ROM_CS#

F3

ROM_SI

D3

ROM_SO

D2

ROM_SCLK

D11

CLAMP

C7

I2CH_SCL

B7

I2CH_SDA

AC8

RFU_GND

G72M

G72M

B

General

General
Purpose

Purpose
I/O

I/O

Thermal

Thermal
Diode

Diode

PLL &

PLL &
XTAL

XTAL

Test

Test

ROM

ROM

PART 2 OF 4

PART 2 OF 4

V

V
I

I
D

D
E

E
O

O

&

&

M

M
U

U
L

L
T

T
I

I
M

M
E

E

Multi-Use Input/Output Interface

Multi-Use Input/Output Interface

D

D
I

I
A

A

MISC

MISC

Integrated

Integrated
TMDS

TMDS

IFPC_TXD0N
IFPC_TXD0P
IFPC_TXD1N
IFPC_TXD1P
IFPC_TXD2N
IFPC_TXD2P

IFPC_TXCN
IFPC_TXCP

IFPCD_RSET

IFPCD_VPROBE

I2CB_SCL

I2CB_SDA

IFPC_IOVDD

IFPCD_PLLVDD

IFPCD_PLLGND

DACA / CRT

DACA / CRT

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

I2CA_SCL

I2CA_SDA

DACA_RSET

DACA_IDUMP

DACA_VDD

DACA_VREF

DACB (TV/CRT2)

DACB (TV/CRT2)

DACB_R_C
DACB_G_Y

DACB_B_COMP

DACB_HSYNC

DACB_VSYNC

DACB_RSET

DACB_IDUMP

DACB_VDD

DACB_VREF

LVDS

LVDS

IFPA_TXD0N
IFPA_TXD0P
IFPA_TXD1N
IFPA_TXD1P
IFPA_TXD2N
IFPA_TXD2P
IFPA_TXD3N
IFPA_TXD3P

IFPA_TXCN

IFPA_TXCP
IFPB_TXD4N
IFPB_TXD4P
IFPB_TXD5N
IFPB_TXD5P
IFPB_TXD6N
IFPB_TXD6P
IFPB_TXD7N
IFPB_TXD7P

IFPB_TXCN

IFPB_TXCP
IFPAB_RSET

IFPAB_VPROBE

IFPA_IOVDD
IFPB_IOVDD

IFPAB_PLLVDD

IFPAB_PLLGND

I2CC_SCL
I2CC_SDA

BUFRST#

STEREO

SWAPRDY

TESTMODE

R1
T1
T2
T3
V3
V2
W1
V1

J3
M5

F9
F10

L4

M4

M6

AE1
AD1
AD2

AD4
AC4

D10
E10

AD3
U9
AE2

AB4

F4
E4
D5

E6
F5

D6
L9
F8

E7

N5
N4
R4
R5
T6
T5
P6
R6
U4
T4
W2
W3
AA3
AA2
AA1
AB1
AB2
AB3
W6
W5

U6
N6

W4
Y4

V5

V6

E9
D8

A6
F7
A7
D7

VGA_RED
VGA_GRN
VGA_BLU

VGAHSYNC
VGAVSYNC

VGADDCCLK
VGADDCDAT

DACA_RSET

DACA_VDD
DACA_VREF

DACB_RSET

DACB_VDD
DACB_VREF

R_LCD_A0-
R_LCD_A0+
R_LCD_A1-
R_LCD_A1+
R_LCD_A2-
R_LCD_A2+

R_LCD_ACLK-
R_LCD_ACLK+
LCD_B0-
LCD_B0+
LCD_B1-
LCD_B1+
LCD_B2-
LCD_B2+

LCD_BCLK-
LCD_BCLK+

R57 *E@1K_4R57 *E@1K_4

IFPAB_IOVDD

IFPAB_PLLVDD

LCD_DDCCLK
LCD_DDCDAT

R362 *E@10K_4R362 *E@10K_4

1 2

R27 E@10K_4R27 E@10K_4

R44 E@10K_4R44 E@10K_4

R46 E@10K_4R46 E@10K_4

E@100P_4

E@100P_4

C

T163T163
T164T164
T11T11
T9T9
T10T10
T12T12
T167T167
T165T165

T156T156
T7T7

12

12

VGA_RED (23)
VGA_GRN (23)
VGA_BLU (23)

VGAHSYNC (23)
VGAVSYNC (23)

VGADDCCLK (23)
VGADDCDAT (23)

1 2

R53 E@124/FR53 E@124/F

TV_C (23)
TV_Y (23)
TV_CVBS (23)

R31

R31
E@124/F_4

E@124/F_4

1 2

12

C488

C488

12

LE4 B:

T8T8

Cancel R57 in BOM

+3VRUN

1

3

RP58

RP58
E@4P2R-2.2K

E@4P2R-2.2K

2

4

12

12

C487

C487
E@100P_4

E@100P_4

+3VRUN

Cancel R362 in BOM

C

+3VRUN

1

3

RP1

RP1
E@4P2R-2.2K

E@4P2R-2.2K

2

4

T14T14
T16T16
T18T18
T17T17
T168T168
T170T170

T13T13
T15T15

LCD_DDCCLK (22)
LCD_DDCDAT (22)

LE4 B:

R_THERMATRIP_VGA#

TV_C

TV_Y

TV_CVBS

VGA_THERMDN

C25

C25

E@2200P_4

E@2200P_4

VGA_THERMDP

B:Change U9 from G781-1 to MAX6649 for thermal issue

D:Change U9 footprint from SOIC8 to MSOP8

IFPCD_PLLVDD

R33 E@150/F_4R33 E@150/F_4

1 2

R22 E@150/F_4R22 E@150/F_4

1 2

R35 E@150/F_4R35 E@150/F_4

1 2

DACA_VDD
DACA_VREF

DACB_VDD
DACB_VREF

4

12

C159

C159
E@0.01U_4

E@0.01U_4

12

C27

C27
E@0.01U_4

E@0.01U_4

IFPAB_IOVDD

IFPAB_PLLVDD

+3VRUN

U46

U46

E@TC7SH08FU

E@TC7SH08FU

2
1

3 5

R599

R599

D

Thermal Sensor for Graphic

SLAVE ADDRESS: 9A

C13

C13
E@0.1U_4

E@0.1U_4

12

C53

C53
E@470P_4

E@470P_4

12

C130

C130
E@4700P_4

E@4700P_4

12

C22

C22
E@4700P_4

E@4700P_4

12

C73

C73
E@470P_4

E@470P_4

12

C113

C113
E@470P_4

E@470P_4

THERMATRIP_VGA#

6642VCC_VGA

12

C52

C52
E@4700P_4

E@4700P_4

12

C711

C711
E@0.1U

E@0.1U

R12 E@200_4R12 E@200_4

R11

R11

E@10K_4

E@10K_4

U2

U2

3
2

E@MAX6649

E@MAX6649

VGA_RED

VGA_GRN

VGA_BLU

VCC1/ALERT
DXN
DXP
GND5PWM

12

C51

C51
E@4.7U_6.3V_6

E@4.7U_6.3V_6

6
7

SDA

8

SCLK

4

L12

L12
E@BLM11A121S_6

E@BLM11A121S_6

R56 E@150/F_4R56 E@150/F_4

1 2

R55 E@150/F_4R55 E@150/F_4

1 2

R54 E@150/F_4R54 E@150/F_4

1 2

Place close to VGA Chip

L17

L17
E@BLM11A121S_6

E@BLM11A121S_6

12

C132

C132
E@470P_4

E@470P_4

12

C29

C29
E@470P_4

E@470P_4

12

C72

C72
E@4700P_25V_4

E@4700P_25V_4

12

C105

C105
E@4700P_4

E@4700P_4

12

C136

C136
E@2.2U_6.3V_6

E@2.2U_6.3V_6

L8

L8
E@BLM11A121S_6

E@BLM11A121S_6

12

C20

C20
E@2.2U_6.3V_6

E@2.2U_6.3V_6

L13

L13
E@BLM11A121S_6

E@BLM11A121S_6

12

C70

C70
E@4.7U_6.3V_6

E@4.7U_6.3V_6

L14

L14
E@BLM11A121S_6

E@BLM11A121S_6

12

C98

C98
E@4.7U_6.3V_6

E@4.7U_6.3V_6

THERMATRIP_VGA# (4)

LE4 C:

Add U46,R599,C711

12

*E@0_4

*E@0_4

D

+3VRUN

LE4 C:

+2_5VRUN

+3VRUN

+3VRUN

+1.8VRUN

+2_5VRUN

R_LCD_A0­R_LCD_A0+
R_LCD_A1­R_LCD_A1+
R_LCD_A2­R_LCD_A2+
R_LCD_ACLK­R_LCD_ACLK+

E

19

LE4 B:

Del R13, R14 in BOM

R14 *E@0_4R14 *E@0_4
R13 *E@0_4R13 *E@0_4

THERMATRIP_VGA#

R7 E@0_4R7 E@0_4
R10 E@0_4R10 E@0_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

LCD_DDCCLK
LCD_DDCDAT

LM86_SMD
LM86_SMC

R72 E@0_4R72 E@0_4
R73 E@0_4R73 E@0_4
R83 E@0_4R83 E@0_4
R87 E@0_4R87 E@0_4
R78 E@0_4R78 E@0_4
R79 E@0_4R79 E@0_4
R88 E@0_4R88 E@0_4
R92 E@0_4R92 E@0_4

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

VGA-G72M ( VIDEO )

VGA-G72M ( VIDEO )

VGA-G72M ( VIDEO )

LM86_SMD (5)
LM86_SMC (5)

LCD_A0- (7,22)
LCD_A0+ (7,22)
LCD_A1- (7,22)
LCD_A1+ (7,22)
LCD_A2- (7,22)
LCD_A2+ (7,22)
LCD_ACLK- (7,22)
LCD_ACLK+ (7,22)

E

19 42Tuesday, March 14, 2006

19 42Tuesday, March 14, 2006

19 42Tuesday, March 14, 2006

of

of

of

1A

1A

1A

A

U33C

A26
C24
B24
A24
C22
A25
B25
D23
G22

J23

E24

F23
J24

F24
G23
H24
D16
E16
D17

F18
E19
E18
D20
D19
A18
B18
A19
B19
D18
C19
C16
C18
N26
N25
R25
R26
R27

T25

T27

T26

AB23

Y24

AB24
AB22
AC24
AC22
AA23
AA22

T24

T23
R24
R23
R22

T22
N23
P24

AA24
AA27
AA26
AB25
AB26
AB27
AA25

W25

L24
K23

M22

N22

M23
M24

K22
A16

D14
D13
C15

U33C

FB_DQ0
FB_DQ1
FB_DQ2
FB_DQ3
FB_DQ4
FB_DQ5
FB_DQ6
FB_DQ7
FB_DQ8
FB_DQ9
FB_DQ10
FB_DQ11
FB_DQ12
FB_DQ13
FB_DQ14
FB_DQ15
FB_DQ16
FB_DQ17
FB_DQ18
FB_DQ19
FB_DQ20
FB_DQ21
FB_DQ22
FB_DQ23
FB_DQ24
FB_DQ25
FB_DQ26
FB_DQ27
FB_DQ28
FB_DQ29
FB_DQ30
FB_DQ31
FB_DQ32
FB_DQ33
FB_DQ34
FB_DQ35
FB_DQ36
FB_DQ37
FB_DQ38
FB_DQ39
FB_DQ40
FB_DQ41
FB_DQ42
FB_DQ43
FB_DQ44
FB_DQ45
FB_DQ46
FB_DQ47
FB_DQ48
FB_DQ49
FB_DQ50
FB_DQ51
FB_DQ52
FB_DQ53
FB_DQ54
FB_DQ55
FB_DQ56
FB_DQ57
FB_DQ58
FB_DQ59
FB_DQ60
FB_DQ61
FB_DQ62
FB_DQ63

FB_CLK0
FB_CLK0#

FB_CLK1
FB_CLK1#

FB_REFCLK
FB_REFCLK#

FB_DEBUG
FB_VREF

FB_PLLVDD
FB_PLLAVDD
FB_PLLAGND

G72M

G72M

FB_CMD[0..26] (21)
FBD[0..63] (21)
FBDQM[0..7] (21)
FBDQS[0..7] (21)
FBDQS#[0..7] (21)

4 4

3 3

+1.8VRUN

12

R365

R365

Rt

E@1K/F_4

E@1K/F_4

FBVREF

12

C489

C489
E@0.1U_4

E@0.1U_4

Rb

12

R364

R364
E@1K/F_4

E@1K/F_4

FBD0 FB_CMD0
FBD1
FBD2
FBD3
FBD4
FBD5
FBD6
FBD7
FBD8
FBD9
FBD10
FBD11
FBD12
FBD13
FBD14
FBD15
FBD16
FBD17
FBD18
FBD19
FBD20
FBD21
FBD22
FBD23
FBD24
FBD25
FBD26
FBD27
FBD28
FBD29
FBD30
FBD31
FBD32
FBD33
FBD34
FBD35
FBD36
FBD37
FBD38
FBD39
FBD40
FBD41
FBD42
FBD43
FBD44
FBD45
FBD46
FBD47
FBD48
FBD49
FBD50
FBD51
FBD52
FBD53
FBD54
FBD55
FBD56
FBD57
FBD58
FBD59
FBD60
FBD61
FBD62
FBD63

FBVREF = FBVDDQ * Rb/(Rt + Rb).
VREF = 0.5 * FBVDDQ.
DDR: 0.9V = 1.8V * 1K/(1K + 1K).

2 2

LE4 B:

+3VRUN

+1.22V_GFX_PCIE

del L5 in BOM

L5

L5
*E@BLM11A121S_6

*E@BLM11A121S_6

L7

L7
E@BLM11A121S_6

E@BLM11A121S_6

12

C21

C21

E@4.7U_6.3V_6

E@4.7U_6.3V_6

FB_CLK0(21)
FB_CLK0#(21)

FB_CLK1(21)
FB_CLK1#(21)

T4T4

12

C23

C23

E@1U_6.3V_4

E@1U_6.3V_4

FBA_PLLVDD
FB_PLLAVDD

12

C26

C26
E@0.01U_4

E@0.01U_4

FB_DEBUG
FBVREF

B

Part 3 of 4

Part 3 of 4

FB_CMD0
FB_CMD1
FB_CMD2
FB_CMD3
FB_CMD4
FB_CMD5
FB_CMD6
FB_CMD7
FB_CMD8

FB_CMD9
FB_CMD10
FB_CMD11
FB_CMD12
FB_CMD13
FB_CMD14
FB_CMD15
FB_CMD16
FB_CMD17
FB_CMD18
FB_CMD19
FB_CMD20
FB_CMD21

MEMORY INTERFACE

MEMORY INTERFACE

FB_CMD22
FB_CMD23
FB_CMD24
FB_CMD25
FB_CMD26

FB_DQM0

FB_DQM1

FB_DQM2

FB_DQM3

FB_DQM4

FB_DQM5

FB_DQM6

FB_DQM7

FB_DQS_RN0
FB_DQS_RN1
FB_DQS_RN2
FB_DQS_RN3
FB_DQS_RN4
FB_DQS_RN5
FB_DQS_RN6
FB_DQS_RN7

FB_DQS_WP0
FB_DQS_WP1
FB_DQS_WP2
FB_DQS_WP3
FB_DQS_WP4
FB_DQS_WP5
FB_DQS_WP6
FB_DQS_WP7

write strobe read strobe

write strobe read strobe

FBVTT_01
FBVTT_02
FBVTT_03
FBVTT_04
FBVTT_05
FBVTT_06
FBVTT_07
FBVTT_08
FBVTT_09
FBVTT_10

FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBCAL_TERM_GND

G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27
G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24

D21
F22
F20
A21
V27
W22
V22
V24

A22
E22
F21
B21
V26
W23
V23
W27

B22
D22
E21
C21
V25
W24
U24
W26

E15
F15
F16
J17
J18
L19
N19
R19
U19
W19

F17
F19
J19
M19
T19
J22
L22
P22
U22
Y22

FBCAL_PD_VDDQ

D15

FBCAL_PU_GND

E13

FBCAL_TERM_GND

H22

FB_CMD1
FB_CMD2
FB_CMD3
FB_CMD4
FB_CMD5
FB_CMD6
FB_CMD7
FB_CMD8
FB_CMD9
FB_CMD10
FB_CMD11
FB_CMD12
FB_CMD13
FB_CMD14
FB_CMD15
FB_CMD16
FB_CMD17
FB_CMD18
FB_CMD19
FB_CMD20
FB_CMD21
FB_CMD22
FB_CMD23
FB_CMD24
FB_CMD25
FB_CMD26

FBDQM0
FBDQM1
FBDQM2
FBDQM3
FBDQM4
FBDQM5
FBDQM6
FBDQM7

FBDQS#0
FBDQS#1
FBDQS#2
FBDQS#3
FBDQS#4
FBDQS#5
FBDQS#6
FBDQS#7

FBDQS0
FBDQS1
FBDQS2
FBDQS3
FBDQS4
FBDQS5
FBDQS6
FBDQS7

LE4 B:

del R40 in BOM

R40

R40

1 2

E@0_4

E@0_4

T6T6

T5T5

+1.8VRUN

12

12

C

R34

R34
E@40.2/F_4

E@40.2/F_4

R32

R32
E@30/F_4

E@30/F_4

PLACE BELOW GPU

12

C104

C104
E@4700P_4

E@4700P_4

12

C47

C47
E@4700P_4

E@4700P_4

12

C44

C44
E@4700P_4

E@4700P_4

12

C103

C103
E@0.022U_4

E@0.022U_4

12

C48

C48
E@0.022U_4

E@0.022U_4

12

C35

C35
E@0.022U_4

E@0.022U_4

AC2

AF2
AF3

AC5

AF6

AD8

AD9

AF9
B11
E11
F11
L11
P11
U11

AD11

N12
P12
R12

AD12

AF12

N13
P13
R13
B14
E14

J14
L14
N14

B2
E2
H2
L2
P2
U2
Y2

B5
E5
L5
P5
U5
Y5

H6
B8

E8
K9

P9
V9

U33D

U33D

GND_01
GND_02
GND_03
GND_04
GND_05
GND_06
GND_07
GND_08
GND_09
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47

G72M

G72M

12

C15

C15
E@0.1U_4

E@0.1U_4

12

C63

C63
E@0.1U_4

E@0.1U_4

12

C36

C36
E@0.1U_4

E@0.1U_4

Part 4 of 4

Part 4 of 4

12

C14

C14
E@4700P_4

E@4700P_4

12

C62

C62
E@4700P_4

E@4700P_4

12

C50

C50
E@0.022U_4

E@0.022U_4

+1.8VRUN

+

+

C16

C16
330U/2.5V-12m

330U/2.5V-12m

GND

GND

D

12

12

12

GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94

C160

C160
E@0.1U_4

E@0.1U_4

C76

C76
E@0.022U_4

E@0.022U_4

C37

C37
E@0.1U_4

E@0.1U_4

P14
R14
U14
W14
AC14
AD14
N15
P15
R15
AF15
N16
P16
R16
AD16
B17
E17
L17
P17
U17
AD17
AF18
K19
P19
V19
AD19
B20
E20
AD20
AF21
B23
E23
H23
L23
P23
U23
Y23
AC23
AF24
B26
E26
H26
L26
P26
U26
Y26
AC26
AF26

12

C93

C93

E@4.7U_6.3V_6

E@4.7U_6.3V_6

12

C77

C77
E@0.1U_4

E@0.1U_4

+1.8VRUN

12

C161

C161
E@1U_6.3V_4

E@1U_6.3V_4

12

C88

C88
E@4.7U_6.3V_6

E@4.7U_6.3V_6

12

C82

C82
E@1U_6.3V_4

E@1U_6.3V_4

E

20

1 1

A

B

C

LE4 A:

Place near VGA chipset

D

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

VGA-G72M ( MENORY, GND )

VGA-G72M ( MENORY, GND )

VGA-G72M ( MENORY, GND )

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

20 42Tuesday, March 14, 2006

20 42Tuesday, March 14, 2006

20 42Tuesday, March 14, 2006

of

of

E

of

1A

1A

1A

1

FB_CMD[0..26] (20)
FBD[0..63] (20)
FBDQM[0..7] (20)
FBDQS[0..7] (20)
FBDQS#[0..7] (20)

R48

R48
E@10K_4

A A

E@10K_4

1 2

R384

R384
E@10K_4

E@10K_4

1 2

FB_CMD12

FB_CMD11

FB_CLK0(20)

FB_CLK0#(20)

FB_CLK0

12

B B

R358

R358
E@120_4

E@120_4

FB_CLK0#

2

U32

U32

FB_CMD1
FB_CMD3
FB_CMD2
FB_CMD0
FB_CMD24
FB_CMD22
FB_CMD21
FB_CMD23
FB_CMD19
FB_CMD20
FB_CMD17
FB_CMD16
FB_CMD14

FB_CMD10
FB_CMD18

FBDQM1
FBDQM0

FB_CMD15
FB_CMD25
FB_CMD9
FB_CMD8
FB_CMD11
FB_CMD12 FB_CMD12

FB_CLK0
FB_CLK0#

+1.8VRUN +1.8VRUN

FB_A0
FB_A1
FB_A2
FB_A3
FB_A4
FB_A5
FB_A6
FB_A7
FB_A8
FB_A9
FB_A10
FB_A11

FB_BA0
FB_BA1

FB_RAS*
FB_CAS*
FB_WE*
FB_CS0*
FB_CKE

M8

A0

M3

A1

M7

A2

N2

A3

N8

A4

N3

A5

N7

A6

P2

A7

P8

A8

P3

A9

M2

A10

P7

A11

R2

A12

L2

BA0

L3

BA1

B3

UDM

F3

LDM

K7

RAS

L7

CAS

K3

WE

L8

CS

K2

CKE

K9

ODT

J8

CLK

K8

CLK#

J1

VDDL

J7

VSSDL

A3

VSS_0

E3

VSS_1

J3

VSS_2

N1

VSS_3

P9

VSS_4

A7

VSSQ_0

B2

VSSQ_1

B8

VSSQ_2

D2

VSSQ_3

D8

VSSQ_4

E7

VSSQ_5

F2

VSSQ_6

F8

VSSQ_7

H2

VSSQ_8

H8

VSSQ_9

VRAM

VRAM

VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

UDQS

UDQS#

LDQS

LDQS#

NC1

NC2

NC3

NC4

NC5

NC6

VREF

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4

G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9

B7
A8

F7
E8

A2
E2
L1
R3
R7
R8

J2

A1
E1
J9
M9
R1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VREF1

3

FBD6
FBD0
FBD7
FBD4
FBD3
FBD5
FBD2
FBD1
FBD11
FBD15
FBD14
FBD8
FBD12
FBD13
FBD9
FBD10

FBDQS1
FBDQS#1

FBDQS0
FBDQS#0

+1.8VRUN

+1.8VRUN

12

C485

C485

E@4.7U_6.3V_6

E@4.7U_6.3V_6

12

C483

C483
E@0.1U_4

E@0.1U_4

E@0.1U_10V_4

E@0.1U_10V_4

12

R47

R47
E@1K/F_4

E@1K/F_4

12

R383

R383
E@1K/F_4

E@1K/F_4

12

C494

C494
E@0.1U_4

E@0.1U_4

12

C492

C492

C81

C81
E@0.1U_P_4

E@0.1U_P_4

1 2

12

C493

C493
E@0.01U_4

E@0.01U_4

12

C484

C484
E@0.01U_4

E@0.01U_4

4

FB_CMD1
FB_CMD3
FB_CMD2
FB_CMD0
FB_CMD24
FB_CMD22
FB_CMD21
FB_CMD23
FB_CMD19
FB_CMD20
FB_CMD17
FB_CMD16
FB_CMD14

FB_CMD10
FB_CMD18

FBDQM2
FBDQM3

FB_CMD15
FB_CMD25
FB_CMD9
FB_CMD8
FB_CMD11

FB_CLK0
FB_CLK0#

FB_A0
FB_A1
FB_A2
FB_A3
FB_A4
FB_A5
FB_A6
FB_A7
FB_A8
FB_A9
FB_A10
FB_A11

FB_BA0
FB_BA1

FB_RAS*
FB_CAS*
FB_WE*
FB_CS0*
FB_CKE

5

6

7

8

U4

M8

A0

M3

A1

M7

A2

N2

A3

N8

A4

N3

A5

N7

A6

P2

A7

P8

A8

P3

A9

M2

A10

P7

A11

R2

A12

L2

BA0

L3

BA1

B3

UDM

F3

LDM

K7

RAS

L7

CAS

K3

WE

L8

CS

K2

CKE

K9

ODT

J8

CLK

K8

CLK#

J1

VDDL

J7

VSSDL

A3

VSS_0

E3

VSS_1

J3

VSS_2

N1

VSS_3

P9

VSS_4

A7

VSSQ_0

B2

VSSQ_1

B8

VSSQ_2

D2

VSSQ_3

D8

VSSQ_4

E7

VSSQ_5

F2

VSSQ_6

F8

VSSQ_7

H2

VSSQ_8

H8

VSSQ_9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

UDQS

UDQS#

LDQS

LDQS#

NC1

NC2

NC3

NC4

NC5

NC6

VREF

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4

VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

FBD24

G8

FBD26

G2

FBD25

H7

FBD30

H3

FBD28

H1

FBD27

H9

FBD29

F1

FBD31

F9

FBD19

C8

FBD20

C2

FBD16

D7

FBD18

D3

FBD23

D1

FBD17

D9

FBD22

B1

FBD21

B9

FBDQS2

B7

FBDQS#2

A8

FBDQS3

F7

FBDQS#3

E8
A2

E2
L1
R3
R7
R8

J2

A1
E1
J9
M9
R1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VREF1

+1.8VRUN

12

C8

C8

E@4.7U_6.3V_6

E@4.7U_6.3V_6

12

C10

C10
E@0.1U_4

E@0.1U_4

12

C79

C79
E@0.1U_4

E@0.1U_4

12

C80

C80
E@0.1U_4

E@0.1U_4

12

C9

C9
E@0.01U_4

E@0.01U_4

12

C78

C78
E@0.01U_4

E@0.01U_4

21

VRAMU4VRAM

U7

FB_CMD1

FB_CLK1

12

R52

R52
E@120_4

E@120_4

FB_CLK1#

C C

FB_CMD3
FB_CMD13
FB_CMD4
FB_CMD5
FB_CMD6
FB_CMD21
FB_CMD23
FB_CMD19
FB_CMD20
FB_CMD17
FB_CMD16
FB_CMD14

FB_CMD10
FB_CMD18

FBDQM5
FBDQM4

FB_CMD15
FB_CMD25
FB_CMD9
FB_CMD8
FB_CMD11
FB_CMD12 FB_CMD12

FB_CLK1(20)

FB_CLK1#(20)

+1.8VRUN +1.8VRUN

D D

FB_A0
FB_A1
FB_A2
FB_A3
FB_A4
FB_A5
FB_A6
FB_A7
FB_A8
FB_A9
FB_A10
FB_A11

FB_BA0
FB_BA1

FB_RAS*
FB_CAS*
FB_WE*
FB_CS0*
FB_CKE

M8

A0

M3

A1

M7

A2

N2

A3

N8

A4

N3

A5

N7

A6

P2

A7

P8

A8

P3

A9

M2

A10

P7

A11

R2

A12

L2

BA0

L3

BA1

B3

UDM

F3

LDM

K7

RAS

L7

CAS

K3

WE

L8

CS

K2

CKE

K9

ODT

J8

CLK

K8

CLK#

J1

VDDL

J7

VSSDL

A3

VSS_0

E3

VSS_1

J3

VSS_2

N1

VSS_3

P9

VSS_4

A7

VSSQ_0

B2

VSSQ_1

B8

VSSQ_2

D2

VSSQ_3

D8

VSSQ_4

E7

VSSQ_5

F2

VSSQ_6

F8

VSSQ_7

H2

VSSQ_8

H8

VSSQ_9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

UDQS

UDQS#

LDQS

LDQS#

NC1
NC2
NC3
NC4
NC5
NC6

VREF

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4

VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

FBD37

G8

FBD36

G2

FBD34

H7

FBD33

H3

FBD32

H1

FBD35

H9

FBD38

F1

FBD39

F9

FBD47

C8

FBD46

C2

FBD43

D7

FBD44

D3

FBD42

D1

FBD45

D9

FBD41

B1

FBD40

B9

FBDQS5

B7
A8

FBDQS4

F7
E8

A2
E2
L1
R3
R7
R8

VREF2

J2

A1
E1
J9
M9
R1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

+1.8VRUN

12

R50

R50
E@1K/F_4

E@1K/F_4

12

C91

R385

R385
E@1K/F_4

E@1K/F_4

C91
E@0.1U_P_4

E@0.1U_P_4

1 2

+1.8VRUN +1.8VRUN

12

C496

C496

E@4.7U_6.3V_6

E@4.7U_6.3V_6

12

C90

C90
E@0.1U_4

E@0.1U_4

12

C41

C41
E@0.1U_4

E@0.1U_4

12

C92

C92
E@0.1U_4

E@0.1U_4

12

C486

C486
E@0.01U_4

E@0.01U_4

12

C89

C89
E@0.01U_4

E@0.01U_4

FB_CMD1
FB_CMD3
FB_CMD13
FB_CMD4
FB_CMD5
FB_CMD6
FB_CMD21
FB_CMD23
FB_CMD19
FB_CMD20
FB_CMD17
FB_CMD16
FB_CMD14

FB_CMD10
FB_CMD18

FBDQM7
FBDQM6

FB_CMD15
FB_CMD25
FB_CMD9
FB_CMD8
FB_CMD11

FB_CLK1
FB_CLK1#

FB_A0
FB_A1
FB_A2
FB_A3
FB_A4
FB_A5
FB_A6
FB_A7
FB_A8
FB_A9
FB_A10
FB_A11

FB_BA0
FB_BA1

FB_RAS*
FB_CAS*
FB_WE*
FB_CS0*
FB_CKE

VRAMU7VRAM

1

2

3

U34

U34

M8

A0

M3

A1

M7

A2

N2

A3

N8

A4

N3

A5

N7

A6

P2

A7

P8

A8

P3

A9

M2

A10

P7

A11

R2

A12

L2

BA0

L3

BA1

B3

UDM

F3

LDM

K7

RAS

L7

CAS

K3

WE

L8

CS

K2

CKE

K9

ODT

J8

CLK

K8

CLK#

J1

VDDL

J7

VSSDL

A3

VSS_0

E3

VSS_1

J3

VSS_2

N1

VSS_3

P9

VSS_4

A7

VSSQ_0

B2

VSSQ_1

B8

VSSQ_2

D2

VSSQ_3

D8

VSSQ_4

E7

VSSQ_5

F2

VSSQ_6

F8

VSSQ_7

H2

VSSQ_8

H8

VSSQ_9

VRAM

VRAM

4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

UDQS

UDQS#

LDQS

LDQS#

NC1

NC2

NC3

NC4

NC5

NC6

VREF

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4

VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

FBD51

G8

FBD49

G2

FBD55

H7

FBD54

H3

FBD52

H1

FBD53

H9

FBD48

F1

FBD50

F9

FBD56

C8

FBD60

C2

FBD58

D7

FBD61

D3

FBD59

D1

FBD57

D9

FBD62

B1

FBD63

B9

FBDQS7

B7

FBDQS#7FBDQS#5

A8

FBDQS6

F7

FBDQS#6FBDQS#4

E8
A2

E2
L1
R3
R7
R8

VREF2

J2

A1
E1
J9
M9
R1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

12

C495

C495

E@4.7U_6.3V_6

E@4.7U_6.3V_6

12

C499

C499
E@0.1U_4

E@0.1U_4

12

C498

C498
E@0.1U_4

E@0.1U_4

12

C49

C49
E@0.1U_4

E@0.1U_4

5

12

C11

C11
E@0.01U_4

E@0.01U_4

12

C497

C497
E@0.01U_4

E@0.01U_4

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

6

Date: Sheet

7

VGA-G72M ( VRAM )

VGA-G72M ( VRAM )

VGA-G72M ( VRAM )

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

21 42Tuesday, March 14, 2006

21 42Tuesday, March 14, 2006

21 42Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

1

+2_5VRUN +2_5VRUN

EDIDCLK(7)

A A

B B

Q29

Q29

DTC144EU

DTC144EU

C C

+3VRUN

R437

R437
10K_4

10K_4

1 3

LCD_DDCCLK(19)

EDIDDATA(7)

LCD_DDCDAT(19)

DISPON

2

D5

D5

2 1

BAS316

BAS316

EC_FPBACK# (30)

2

+3VRUN

R432

R432

2.2K_F_4

2.2K_F_4

R431

R431

2.2K_F_4

2.2K_F_4

2

1

Q5 I@2N7002KQ5 I@2N7002K

1

Q26 I@2N7002KQ26 I@2N7002K

3

+2_5VRUN

2

3

+3VRUN+2_5VRUN

PULL HIGH TO +3V_S5 AT PAGE19

For N-vidia

PANEL_BKEN(19)

For UMA

LCD_BLON_EC(7,19,30)

LE4 B:

Add R570

R166 E@0_4R166 E@0_4

R570 I@0_4R570 I@0_4

3

R433

R433

2.2K_F_4

2.2K_F_4

I_EDIDCLK

R434

R434

2.2K_F_4

2.2K_F_4

I_EDIDDATA

ADD LEVEL SHIFT FOR EDID

LID551#

LID#

+3VRUN

R435

R435
10K_4

10K_4

2

2

Q7

Q7
DTC144EUA

DTC144EUA

1 3

+3VRUN

R436

R436
10K_4

10K_4

DISPON

Q28

Q28
DTC144EUA

DTC144EUA

1 3

LID551# (30,31)

LID# (30,31)

R152 0_6R152 0_6

R_DISPON

4

VADJ(30)

L51 BK1608LL121_6L51 BK1608LL121_6
C549 0.1U_4C549 0.1U_4

5

RVADJ
R_DISPON
VIN

+3VRUN

LCDVCC

LCDID0(14) LCD_A1+ (7,19)
LCDID1(14)

LCDVIN

LCDVCC

RVADJ
LCDVIN
R_DISPON
LCDID0
LCDID1

LCDVIN

1 2

12

C560

C560

10U/25V/1210/X6S

10U/25V/1210/X6S

LCDVCC

LCDVCC

C297

C297
*10P_4

*10P_4

6

C336

C336

0.1U_6_25V

0.1U_6_25V

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930

C548

C548

0.1U_4

0.1U_4

31

CN3

CN3

2

2

31

4

4

6

6

8

8

10

10

12
14
16
18
20
22
24
26
28
30

32

FOX GS12301-1011

FOX GS12301-1011

32

0.1U_4

0.1U_4

+3VRUN

C550

C550

TXLCLKOUT­TXLCLKOUT+

TXLOUT0­TXLOUT0+

TXLOUT1­TXLOUT1+

TXLOUT2­TXLOUT2+

I_EDIDCLK
I_EDIDDATA

C552

C552

0.1U_4

0.1U_4

7

LCD_ACLK- (7,19)
LCD_ACLK+ (7,19)

LCD_A0- (7,19)
LCD_A0+ (7,19)

LCD_A1- (7,19)

LCD_A2- (7,19)
LCD_A2+ (7,19)

LCDVIN

12

C558

C558

*10U/25V_12

*10U/25V_12

C327

C327
1000P_4

1000P_4

8

22

LCD CONNECTOR

+15V

3

1

R158

R158
330K_6

330K_6

2

Q4

Q4

2N7002K

2N7002K

+3VRUN

LCDENVCC

6
5
2
1

C304 3300P_6C304 3300P_6

Q27

Q27
FDC653N_NL

FDC653N_NL

4

3

LCDVCC

C551

C551
10U/10V_8

10U/10V_8

35 mils
500mA

LCDENVCC

C298

C298

0.1uF_6

0.1uF_6

Q25

Q25

2N7002K

2N7002K

R439

R439
47_8

47_8

1 2

3

2

1

For N-vidia

ENVDD(19)

DISP_ON(7)

For UMA

R442 E@0_6R442 E@0_6

R445 I@0_6R445 I@0_6

LE4 B:

Add opantion

3VPCU

R441

R441
10K_6

10K_6

LCDENVCC

2

Q6

Q6

1 3

DTC144EUA

DTC144EUA

LCD VCC

+3VRUN

+3VRUN

R346

R346
10K_4

10K_4

U30

U30

BXTALOUT(19)

R347 0_4R347 0_4

1 2

SSFOUT(19)

D D

1

XIN/CLKIN

2

VSS

3

SO

4

SSCLK

PG1819G-08SR

PG1819G-08SR

XOUT

VDD

PD#

REFCLK

5
6
7
8

-1.75% (DOWN)

0.85% (CENTER)

1

2

S0

0

1

R345

R345
10K_4

10K_4

1 2

1 2

L41

12

C479

C479

0.1U_4

0.1U_4

L41

12

BLM11A121S_6

BLM11A121S_6

+3VRUN

LE4 B:

Update correct power plane

+3VL

12

C480

C480
10U_10V_8

10U_10V_8

BIA_PWM(19)

LCD_BKLTCTL(7)

For N-vidia

For UMA

R128 *E@0_4R128 *E@0_4

R571 *I@0_6R571 *I@0_6

U13

U13

*TC7SH08FU

*TC7SH08FU

LE4 B:

Del U13,R571,R128 in BOM

C268

C268

0.1U_4

0.1U_4

2
1

3 5

PWROK(14,30)

4

DISPON

PWROK

R168 0_6R168 0_6

LE4 B:

Add R168 in BOM

+3VRUN

R165

R165
10K_4

10K_4

R170

R170
20K_6

20K_6

2

Q8

Q8

1 3

DTC144EUA

DTC144EUA

INVERTER POWER CIRCUIT

3

4

5

6

R175 100K_6R175 100K_6

Q9

Q9
SI3457DV

SI3457DV

4

G3S

2

D

1

D

D

D

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LCD CON. & LCD POWER

LCD CON. & LCD POWER

LCD CON. & LCD POWER

Date: Sheet

Date: Sheet

Date: Sheet

7

VIN

5
6

50mils

LCDVIN

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

22 42Tuesday, March 14, 2006

22 42Tuesday, March 14, 2006

22 42Tuesday, March 14, 2006

8

of

of

of

1A

1A

1A

A

B

C

D

E

LE4 C:

Change D7 packing

+5VRUN

ESD PORTECTION

+5VRUN

U36

U36

+5VRUN

+5VRUN

2
1
3

2
1
3

2
1
3

CRT_B_1
DDCCLK_1

4 4

3 3

C338

C338

0.1U/10V_4

0.1U/10V_4

DDCDAT_1 CRT_HS_1

C616

C616

0.1U/10V_4

0.1U/10V_4

TV_LUMA_1

C347

C347

0.1U/10V_4

0.1U/10V_4

IO4

VCC
IO1

IO3

IO2

GND

DALC208SC6

DALC208SC6

U37

U37

IO4

VCC
IO1

IO3

IO2

GND

DALC208SC6

DALC208SC6

U40

U40

IO4

VCC
IO1

IO3

IO2

GND

DALC208SC6

DALC208SC6

6
4
5

6
4
5

6
4
5

CRT_R_1
CRT_G_1

CRT_VS_1

TV_CHROMA_1
TV_COMP_1

VGA_RED_SYS
VGA_GEN_SYS
VGA_BLU_SYS

R164

R164
150/F_4

150/F_4

R446

R446
150/F_4

150/F_4

R169

R169
150/F_4

150/F_4

+3VRUN

+3VRUN

C557

C557

C315

C315

10P_4

10P_4

10P_4

10P_4

R176 2.2K_4R176 2.2K_4

CRTDCLK

R179 2.2K_4R179 2.2K_4

CRTDDAT

L55 BLM18BB470SN1D_6L55 BLM18BB470SN1D_6
L57 BLM18BB470SN1D_6L57 BLM18BB470SN1D_6
L59 BLM18BB470SN1D_6L59 BLM18BB470SN1D_6

C559

C559
10P_4

10P_4

+3VRUN

2

1

RHU002N06

RHU002N06

Q30

Q30

VSYNC_T
HSYNC_T

R187 39_4R187 39_4
R453 39_4R453 39_4

+3VRUN

2

1

RHU002N06

RHU002N06

Q31

Q31

F1

F1

FUSE1A6V_POLY

FUSE1A6V_POLY

LE4 B:

SWAP parts

RED_PI
GEN_PI
BLU_PI

C308

C308
22P_4

22P_4

3

3

C367

C367

0.1U_4

0.1U_4

CRTVDD_5V

T206T206

C358

C358
33P_4

33P_4

6
7

2
8
3
9
4

10

5

C563

C563
33P_4

33P_4

1617

CRT_VS_1
CRT_HS_1

C353

C353
33P_4

33P_4

CN18

CN18

CRT_CONN

CRT_CONN

111
12
13
14
15

C330

C330
33P_4

33P_4

L61

D7

12

C314

C314
22P_4

22P_4

DDCCLK2 DDCCLK_1
CRT_VS2
CRT_HS2
DDCDAT2 DDCDAT_1

D7

2 1

EC10QS04

EC10QS04

L54 BLM18BB470SN1D_6L54 BLM18BB470SN1D_6
L56 BLM18BB470SN1D_6L56 BLM18BB470SN1D_6
L58 BLM18BB470SN1D_6L58 BLM18BB470SN1D_6

C321

C321
22P_4

22P_4

R174

R174

2.2K_4

2.2K_4

R180

R180

2.2K_4

2.2K_4

CRTVDD2

CRTVDD_5V

L24 BK1608HM121_6L24 BK1608HM121_6
L29 BK1608HM121_6L29 BK1608HM121_6
L28 BK1608HM121_6L28 BK1608HM121_6
L60 BK1608HM121_6L60 BK1608HM121_6

CRTVDD_5V

L61

FBM2125HM330_8

FBM2125HM330_8

CRT_R_1
CRT_G_1
CRT_B_1

C320

C320

C313

C313

10P_4

10P_4

10P_4

10P_4

C307

C307
10P_4

10P_4

CRT PORT

CRT_SENSE#

C305

C305
180P_4

180P_4

23

T69T69

TV-OUT

LE4 C:

Change C425,C434 and C427 from 6p to 270p
Change C424,C433 and C429 from 6p to 330p
ChangeL35 size from 0603 to 0805
Add C712 ,C713 and C714

Intel CRB

TV_Y/G_SYS

R260

R260
150/F_4

150/F_4

TV_C/R_SYS

R279

R279
150/F_4

150/F_4

TV_COMP_SYS

R275

R275
150/F_4

150/F_4

C712 22p/50VC712 22p/50V
L34 1.8uH_8L34 1.8uH_8

1 2

C425

C425
270p/25V

270p/25V

C713 22p/50VC713 22p/50V
L36 1.8uH_8L36 1.8uH_8

1 2

C434

C434
270p/25V

270p/25V

C714 22p/50VC714 22p/50V
L35 1.8uH_8L35 1.8uH_8

1 2

C427

C427
270p/25V

270p/25V

C424

C424
330p/50V

330p/50V

TV_CHROMA_1

C433

C433
330p/50V

330p/50V

C429

C429
330p/50V

330p/50V

TV_COMP_1

TV_LUMA_1

CN20

CN20
S-VIDEO

S-VIDEO

5

6

6

9

9

3

5

7

7

4

4

8

8

13

2

2

2
4

4
2

4
2

2
4

VGA_RED_SYS
VGA_GEN_SYS
VGA_BLU_SYS

VSYNC
HSYNC

CRTDCLK
CRTDDAT

VGA_RED_SYS
VGA_GEN_SYS
VGA_BLU_SYS

VSYNC
HSYNC

CRTDCLK
CRTDDAT

TV_Y/G_SYS
TV_C/R_SYS
TV_COMP_SYS

TV_Y/G_SYS
TV_C/R_SYS
TV_COMP_SYS

+5VRUN

AHCT1G125DCH

C708 0.1U_4C708 0.1U_4

VSYNC VSYNC_T

+5VRUN

C709 0.1U_4C709 0.1U_4

HSYNC HSYNC_T

AHCT1G125DCH

1

53

2 4

1

53

2 4

AHCT1G125DCH

AHCT1G125DCH

U44

U44

U45

U45

R596

R596

1 2

1K_4

1K_4

CRT_R_COM(7)
CRT_G_COM(7)
CRT_B_COM(7)

VSYNC_COM(7)
HSYNC_COM(7)

DDCCLK(7)

DDCDAT(7)

VGA_RED(19)
VGA_GRN(19)
VGA_BLU(19)

VGAVSYNC(19)

2 2

VGAHSYNC(19)
VGADDCCLK(19)

VGADDCDAT(19)

TV_Y/G(7)
TV_C/R(7)
TV_COMP(7)

TV_Y(19)
TV_C(19)
TV_CVBS(19)

R414 I@0_4R414 I@0_4
R410 I@0_4R410 I@0_4
R405 I@0_4R405 I@0_4

RN4 I@4P2R-S-0RN4 I@4P2R-S-0

1
3

RN2 I@4P2R-S-0RN2 I@4P2R-S-0

3
1

R413 E@0_4R413 E@0_4
R408 E@0_4R408 E@0_4
R402 E@0_4R402 E@0_4

RN3 E@4P2R-S-0RN3 E@4P2R-S-0

3
1

RN1 E@4P2R-S-0RN1 E@4P2R-S-0

1
3

R422 I@0_4R422 I@0_4
R418 I@0_4R418 I@0_4
R427 I@0_4R427 I@0_4

R424 E@0_4R424 E@0_4
R420 E@0_4R420 E@0_4
R429 E@0_4R429 E@0_4

150 ohm@ 100MHZ

1 1

LE4 B:

Add U44,U45,R596,C708,C709

6pf 6pf
16V 16V

CH00606TB04 CH00606TB04

A

B

(100mA)

CX8PG181001

C

(180 ohm ,1.5A)

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CRT & TV-OUT CONN

CRT & TV-OUT CONN

CRT & TV-OUT CONN

Date: Sheet

Date: Sheet

D

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

23 42Tuesday, March 14, 2006

23 42Tuesday, March 14, 2006

23 42Tuesday, March 14, 2006

of

of

E

of

1A

1A

1A

8

7

6

5

4

3

2

1

LE4 B:

TPBIAS0

24

C391

C391
12P-50V_4

LE4 B:

D D

C C

B B

GNT2#(13)
REQ2#(13)

FRAME#(13,33)

IRDY#(13,33)

DEVSEL#(13,33)

TRDY#(13,33)
SERR#(13,33)
STOP#(13,33)

PERR#(13,33)

PAR(13,33)

C/BE3#(13,33)
C/BE2#(13,33)
C/BE1#(13,33)
C/BE0#(13,33)

PCLK_PCM(3)

PCIRST#(13,25,33)
AD[0..31](13,33)

GNT2#
REQ2#
AD25

R280 150_4R280 150_4

FRAME#
IRDY#
DEVSEL#
TRDY#
SERR#
STOP#
PERR#
PAR

C/BE0#
PCLK_PCM
PCIRST#

GRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

SAWP GNT2# AND REQ2#

W10

R11

P11

U11

V11
W11
R10
U10

V10

GRST#

W5
W6

W9

W7
W4

M5
M6
M3
M2
M1

L2
L3
N5
R6
V5
U6

V6
R7
U7

P2
U5
V7

L1
K3

K5

R9
U9
V9

V8
U8
R8

T2
T1
R3
P5
R2
R1
P3
N3
N2
N1

U22A

U22A

GNT#
REQ#
IDSEL
FRAME#
IRDY#
DEVSEL#
TRDY#
SERR#
STOP#
PERR#
PAR

CBE3
CBE2
CBE1
CBE0

PCLK
PRST#

GRST#
AD00

AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI7412

PCI7412

PCI Interface

PCI Interface

RSVD_03/VD0/VCCD1#/PS_MODE

3VSUS

R286

R286
100K_4

100K_4

C436

C436

0.22U/10V_4

0.22U/10V_4

PN

XI

XO

R0
R1

CPS

TEST0

VSSPLL

TPA0P
TPA0N

TPBIAS0

TPB0P
TPB0N

TPA1P
TPA1N

TPBIAS1

TPB1P
TPB1N

1394 Interface

1394 Interface

Miscellaneous

Miscellaneous

2 1

2 1

VDDPLL15

PHY_TEST_MA

PC0_RSVD
PC1_RSVD
PC2_RSVD

AGND_00
AGND_01
AGND_02

SUSPEND#

RI_OUT#

SPKROUT

VR_EN#

USB_EN

SCL
SDA

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

LATCH/VD3/VPPD0

CLOCK/VD1/VCCD0#

DATA/VD2/VPPD1

LE4 C:

Modify PCIRST# circuit method

D3 *1SS355_NCD3 *1SS355_NC

D18 *1SS355_NCD18 *1SS355_NC

R285

R285

R19
R18

T18
T19
R12
P12
R17

V14
W14
R13
V13
W13

V16
W16
W17
V15
W15

P15
P17

U12
V12
W12

U13
U14
R14

J5
L5
H3

K2
E10

G2
G3

G1
H5
H2
H1
J1
J2
J3

C9
A9
B9
C4

1 2

1394_XIN

1394_XOUT

R0

R205 FW@6.34K/F_4R205 FW@6.34K/F_4

R1

CPS

R237 FW@0_4R237 FW@0_4

R241 FW@0_4R241 FW@0_4

TPA0P
TPA0N
TPBIAS0
TPB0P
TPB0N

1394_TPA1+
1394_TPA1­TPBIAS1
1394_TPB1+
1394_TPB1-

R219 FW@4.7K_4R219 FW@4.7K_4

R281 0_4R281 0_4

PCMSPK

R282 *0_4R282 *0_4

SCL_CARD
SDA_CARD

INTC#
INTD#
INTE#

R284 10K_4R284 10K_4

R249 0_4R249 0_4

1 2

R245 0_4R245 0_4

1 2

R240 0_4R240 0_4

1 2

R278 10K_4R278 10K_4

LE4 A-1108:

GRST#_7402 (30)

*0_4

*0_4

12P-50V_4

Y3

Y3
FW@24.576MHZ

FW@24.576MHZ

BG624576473

1 2

C389

C389
12P-50V_4

12P-50V_4

LE4 C:

Change R237 and R241 from
390K and 330 to 0 ohm

T91T91
T90T90
T89T89
T93T93
T95T95

1394_AVDD

3VSUS

R283

R283
10K_4

10K_4

PCI_PME# (13,33)
PCMSPK (28)
RI# (14,26)

INTC# (13)
INTD# (13)
INTE# (13)
SERIRQ (14,26,27,30)

3VSUS

CLKRUN# (14,26,27,30,33)

3VSUS

PCIRST#

Add C?, solve
1394 hang up
and busy on
system.

C394

C394
1U-16V_6

1U-16V_6

D2 *1SS355_NCD2 *1SS355_NC

2 1

T111T111

TPS_LATCH (25)
TPS_CLOCK (25)
TPS_DATA (25)

LE4 C:

C715

C715
270P-25V_4

270P-25V_4

TPA0P
TPA0N

TPB0P
TPB0N

R37

R37

FW@56.2/F_4

FW@56.2/F_4

R42

R42

FW@5.1K/F_6

FW@5.1K/F_6

SUS_STAT# (14,26,27)

PCMSPK

R38

R38
FW@56.2/F_4

FW@56.2/F_4

1394_TPA1+
1394_TPA1-
TPBIAS1
1394_TPB1+
1394_TPB1-

R600

R600
0_4

0_4

R604

R604
47K_4

47K_4

R39

R39
FW@56.2/F_4

FW@56.2/F_4

R36

R36
FW@56.2/F_4

FW@56.2/F_4

C28

C28
270P-25V_4

270P-25V_4

R601

R601
0_4

0_4

C34

C34
1U-16V_6

1U-16V_6

R602

R602
0_4

0_4

C716

C716
1U-16V_6

1U-16V_6

LE4 B:

R603

R603
0_4

0_4

LE4 C:

Solve to hang
up and busy on
system

R24 FW@0_4R24 FW@0_4
R23 FW@0_4R23 FW@0_4

R26 0_4R26 0_4
R25 0_4R25 0_4

TPA0P
TPA0N

TPB0P
TPB0N

L1394_TPA0+
L1394_TPA0-

L1394_TPB0+
L1394_TPB0-

No Struff

L9

L9
*PLW3216S900SQ2T1

*PLW3216S900SQ2T1

<PN>

<PN>

3 4

L10

L10

3 4

34

34

*PLW3216S900SQ2T1

*PLW3216S900SQ2T1

<PN>

<PN>

34

34

12

12

12

12

12

12

L1394_TPA0+
L1394_TPA0-

L1394_TPB0+
L1394_TPB0-

L1394_TPB0-
L1394_TPA0-
L1394_TPA0+
L1394_TPB0+

J1

J1

1
3
4
2

FOX_UV31413-K1

FOX_UV31413-K1

5
6

LE4 B:

Add L71

3VSUS

3VSUS

R264

R261

R261

2.2K_4

2.2K_4

SCL_CARD
SDA_CARD

R262

R262
*220_4

*220_4

A A

8

R264

2.2K_4

2.2K_4

R263

R263
*220_4

*220_4

U24

U24

8
7
6
5

24LC02BT

24LC02BT

VCC
NC
SCL
SDA

GND

1

A0

2

A1

3

A3

4

7

3VSUS

C422

C422

0.1U-10V_4

0.1U-10V_4

1394_AVDD

L71 FW@BK1608HS800_6L71 FW@BK1608HS800_6
L32 FW@BK1608HS800_6L32 FW@BK1608HS800_6

1394_AVDD

C398

C398

0.1U-10V_4

0.1U-10V_4

6

C392

C392

1U-16V_6

1U-16V_6

R290

R290
*33_4

*33_4

5

PCLK_PCM

C440

C440
*10P_4

*10P_4

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

4

3

Date: Sheet

2

PC7412 - IEEE1394

PC7412 - IEEE1394

PC7412 - IEEE1394

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

24 42Tuesday, March 14, 2006

24 42Tuesday, March 14, 2006

24 42Tuesday, March 14, 2006

of

of

of

1

1A

1A

1A

1

U22C

U22C

CLK_48

C10
A10
F11
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19
J17
J15
J18
K15
K17
K18
L15
L18
L19
M17
M18
N19
M15
N17
N18
P19

E13
E18
H18
L17

B10
N15
B11

A13
C15
H15
C14
C12
F19
E19
G17
E12
B16
G19
G18
F17
G15

H17
M19

A11
H14
A15
J19
A12
B12
F18

F2
G5
G6
C5
A4
B4
D1
E3
E2
F5
E1

F1
F3

E9
A8
B8

A3
C8

F8
E8
A7

B7
C7
A6
B6

E7
C6

A5
B5
E6

A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0

A_CC/BE3#
A_CC/BE2#
A_CC/BE1#
A_CC/BE0#

A_CRSVD/D2
A_CCD1#
A_CCD2#

A_CVS1#
A_CRST#
A_CBLOCK#
A_CREQ#
A_CSERR#
A_CDEVSEL#
A_CFRAME#
A_CGNT#
A_CINT#
A_CVS2#
A_CPERR#
A_CSTOP#
A_CIRDY#
A_CTRDY#

A_CRSVD/A18

A_RSVD/D14

A_CCLKRUN#

A_CPAR

A_CSTSCHG
A_CAUDIO
A_CCLK

SC_OC#

SC_PWR_CTRL

SD_CMD/SM_ALE/SC_GPIO2

SD_CLK/SM_RE#/SC_GPIO1

SM_PHYS_WP#/SC_FCB

A A

XD_CD#/SM_PHYS_WP#

MC_PWR_CTRL_1/SM_R/B#

MS_BS/SD_CMD/SM_WE#

MS_CLK/SD_CLK/SM_EL_WP#

MS_SDIO(DATA0)/SD_DATA0/SM_D0

MS_DATA1/SD_DATA1_SM_D1

FlashMedia Interface

FlashMedia Interface

MS_DATA2/SD_DATA2_SM_D2
MS_DATA3/SD_DATA3_SM_D3

SD_DAT0/SM_D4/SC_GPIO6
SD_DAT1/SM_D5/SC_GPIO5
SD_DAT2/SM_D6/SC_GPIO4
SD_DAT3/SM_D7/SC_GPIO3

PCI7412

PCI7412

U22B

U22B

B B

CardBus Interface

CardBus Interface

C C

RSVD_04/D2
CCD1#/CD1#
CCD2#/CD2#

CREQ#/INPACK#

CSERR#/WAIT#

RSVD_02/A18
RSVD_01/D14

D D

PCI7412

PCI7412

SC_VCC5

SM_CLE/SC_GPIO0

SM_R/B#/SC_RFU

SC_CLK
SC_RST

SC_DATA

SC_CD#
SD_CD#
MS_CD#
SM_CD#

MC_PWR_CTRL_0

SD_WP/SM_CE#

CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD09
CAD08
CAD07
CAD06
CAD05
CAD04
CAD03
CAD02
CAD01
CAD00

CCBE3
CCBE2
CCBE1
CCBE0

CVS1/VS1#

CRST#

CBLOCK#

CDEVSEL#

CFRAME#
CGRANT#

CINT#

CVS2/VS2#

CPERR#
CSTOP#

CIRDY

CTRDY#

CCLKRUN#

CPAR
VCCCA_01
VCCCA_00

CSTSCHG

CAUDIO

CCLK

CARD BUS

1

2

3

4

DO NOT INSERT SD/MMC, MEMORYSTICK AND XD SIMULTANEOUSLY.

3 IN1 CARD READER(push-push)

VCC_FM

TI_CLK48M

SD_CDZ
MS_CDZ

MC_PWR_CTRL_0#
SM_R/B#
MS_BS_SD_CMD_SM_WEZ
MS_CLK_SD_CLK_SM_ELWPZ_R

MS_DATA0_SD_DAT0_SM_D0
MS_DATA1_SD_DAT1_SM_D1
MS_DATA2_SD_DAT2_SM_D2
MS_DATA3_SD_DAT3_SM_D3

SD_WP_SM_CEZ

A_VCC

R443 47_6R443 47_6

2

A_CCLK1

TI_CLK48M (3)

R266 CR@10K_4R266 CR@10K_4
R271 CR@10K_4R271 CR@10K_4
R254 47_6R254 47_6

R277 CR@10K_4R277 CR@10K_4

A_CAD0
A_CAD1
A_CAD3
A_CAD5
A_CAD7
A_CC/BE0#
A_CAD9
A_CAD11
A_CAD12
A_CAD14
A_CC/BE1#
A_CPAR
A_CPERR#
A_CGNT#
A_CINT#

A_CCLK1
A_CIRDY#
A_CC/BE2#
A_CAD18
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A_CAD29
A_CRSVD/D2
A_CCLKRUN#

A_CCD1#
A_CAD2
A_CAD4
A_CAD6
A_RSVD/D14
A_CAD8
A_CAD10
A_CVS1#
A_CAD13
A_CAD15
A_CAD16
A_CRSVD/A18
A_CBLOCK#
A_CSTOP#
A_CDEVSEL#

A_CTRDY#
A_CFRAME#
A_CAD17
A_CAD19
A_CVS2#
A_CRST#
A_CSERR#
A_CREQ#
A_CC/BE3#
A_CAUDIO
A_CSTSCHG
A_CAD28
A_CAD30
A_CAD31
A_CCD2#

MS_CLK_SD_CLK_SM_ELWPZ

VCC_FM

CN4

CN4

1

GND1

2

SKTAAD0/D3

3

SKTAAD1/D4

4

SKTAD3/D5

5

SKTAD5/D6

6

SKTAAD7/D7

7

-SKTACBE0/CE1#

8

SKTAAD9/A10

9

SKTABAD11/OE#

10

SKTAAD12/A11

11

SKTAAD14/A9

12

-SKTACBE1/A8

13

SKTAPAR/A13

14

-SKTAPERR/A14

15

-SKTAGNT/WE#

16

-SKTAINT/RDY

19

SKTAPCLK/A16

20

-SKTAIRDY/A15

21

-SKTACBE2/A12

22

SKTAAD18/A7

23

SKTAAD20/A6

24

SKTAAD21/A5

25

SKTAAD22/A4

26

SKTAAD23/A3

27

SKTAAD24/A2

28

SKTAAD25/A1

29

SKTAAD26/A0

30

SKTAAD27/D0

31

SKTAAD29/D1

32

SKTARSVD/D2

33

-SKTACLKRUN/WP

34

GND2

35

GND3

36

-SKTACD1/CD1#

37

SKTAAD2/D11

38

SKTAD4/D12

39

SKTAAD6/D13

40

SKTARSVD/D14

41

SKTAAD8/D15

42

SKTAAD10/CE2#

43

-SKTAVS1/VS1#

44

SKTAAD13/IORD#

45

SKTAAD15/IOWR#

46

SKTAAD16/A17

47

-SKTRSVD/A18

48

-SKTALOCK/A19

49

-SKTASTOP/A20

50

-SKTADEVSEL/A21

53

-SKTATRDY/A22

54

-SKTAFRAME/A23

55

SKTAAD17/A24

56

SKTAAD19/A25

57

-SKTAVS2VS2#

58

-SKTARST/RESET

59

0SKTASERR/WAIT#

60

-SKTAREQ/INPACK#

61

-SKTACBE3/REG#

62

SKTAAUDIO/BVD2

63

-SKTASTSCHG/BVD1

64

SKTAAD28/D8

65

SKTAAD30/D9

66

SKTAAD31/D10

67

-SKTACD2/CD2#

68

GND4

CARDBUS SLOT

FOX_1CA4C5G2-TC_CARD BUS

FOX_1CA4C5G2-TC_CARD BUS

3

UPPER PIN

UPPER PIN

LOWER PIN

LOWER PIN

MS_DATA3_SD_DAT3_SM_D3
MS_BS_SD_CMD_SM_WEZ

MS_CLK_SD_CLK_SM_ELWPZ
MS_DATA0_SD_DAT0_SM_D0

MS_DATA1_SD_DAT1_SM_D1
MS_DATA2_SD_DAT2_SM_D2
SD_CDZ

SD_WP_SM_CEZ

GND5
GND6
GND7
GND8

17
51

18
52

69
70
71
72

A_VPP

A_VCC

4

SKTA/VCC1
SKTA/VCC2

SKTA/VPP1
SKTA/VPP2

C571

C571

0.1U-10V_4

0.1U-10V_4

C568

C568

0.01U-16V_4

0.01U-16V_4

A_VCC

A_VPP

TPS_DATA(24)

TPS_CLOCK(24)

TPS_LATCH(24)

PCIRST#(13,24,33)

C570

C570

0.01U-16V_4

0.01U-16V_4

C567

C567

0.01U-16V_4

0.01U-16V_4

CN8

CN8

18

SD-1(DAT3)

15

SD-2(CMD)

12

SD-3(VSS)

10

SD-4(VCC)

7

SD-5(CLK)

4

SD-6(VSS)

3

SD-7(DAT0)

2

SD-8(DAT1)

20

SD-9(DAT2)

21

SD-CD1

23

SD-CD2(G)

1

SD-WP1

22

SD-WP-COM

24

NAIL1

25

NAIL2

26

NAIL3

3@3IN1_DFHD23MS069

3@3IN1_DFHD23MS069

3VSUS

C415

C415

0.1U-10V_4

0.1U-10V_4

3VSUS

C421

C421

0.1U-10V_4

0.1U-10V_4

T74T74

A_VPP

A_VCC

5VSUS

C581

C581

0.1U-10V_4

0.1U-10V_4

C572

C572

0.1U-10V_4

0.1U-10V_4

5

(VSS)MS-1

(BS)MS-2
(DAT1)MS-3
(DAT0)MS-4
(DAT2)MS-5

(INS)MS-6
(DAT3)MS-7
(SCLK)MS-8

(VCC)MS-9

(VSS)MS-10

5
6
8
9
11
13
14
16
17
19

MS_BS_SD_CMD_SM_WEZ
MS_DATA1_SD_DAT1_SM_D1
MS_DATA0_SD_DAT0_SM_D0
MS_DATA2_SD_DAT2_SM_D2
MS_CDZ
MS_DATA3_SD_DAT3_SM_D3
MS_CLK_SD_CLK_SM_ELWPZ

LE4 D:

change footprint form
3IN1-R009-020-XX-21P to
3IN1-R009-020-XX-21P-LE4

3VSUS

C418

1U-16V_6

1U-16V_6

1
2
3
4
5
6
7
8

9
10
11
12

3VSUS

C583

C583

0.1U-10V_4

0.1U-10V_4

C576

C576
10U-10V_8

10U-10V_8

C418

0.1U-10V_4

0.1U-10V_4

1394_AVDD

C437

C437

U18

U18

5V_0
5V_1
DATA
CLOCK
LATCH
NC_0

BVPP/BVCORE
12V_0
AVPP/AVCORE
AVCC0
AVCC1
GND
RESET#

C412

C412
10U-10V_8

10U-10V_8

C423

C423

1U-16V_6

1U-16V_6

5VSUS 5VSUS

TPS_DATA
TPS_CLOCK
TPS_LATCH

C575

C575
10U-10V_8

10U-10V_8

C574

C574

0.1U-10V_4

0.1U-10V_4

5

C403

C403

0.1U-10V_4

0.1U-10V_4

SHDN#

12V_1

BVCC1
BVCC0

3.3VIN0

3.3VIN1

NC

25

C584

C584

0.1U-10V_4

0.1U-10V_4

C569

C569

0.01U-16V_4

0.01U-16V_4

C396

C396

0.1U-10V_4

0.1U-10V_4

5V_2
NC_3
NC_2

NC_1

OC#

TPS2220APWP

TPS2220APWP

C399

C399

1U-16V_6

1U-16V_6

24
23
22
21
20
19
18
17
16
15
14
13

C580

C580
10U-10V_8

10U-10V_8

C577

C577
10U-10V_8

10U-10V_8

6

C435

C435
10U-10V_8

10U-10V_8

C441

C441

2.2U-6.3V_6

2.2U-6.3V_6

3VSUS

6

C416

C416

0.01U-16V_4

0.01U-16V_4

VCC_FM

CLOSE CONN

C588

C588

0.01U-16V_4

0.01U-16V_4

3VSUSA_VCC

C587

C587

0.1U-10V_4

0.1U-10V_4

VCC_FM

C397

C397

0.01U-16V_4

0.01U-16V_4

R302

R302

CR@150K_6

CR@150K_6

1394_AVDD

C582

C582

0.01U-16V_4

0.01U-16V_4

C586

C586

1U-16V_6

1U-16V_6

VCC_FM

MC_PWR_CTRL_0#

C395

C395

0.1U-10V_4

0.1U-10V_4

C585

C585

1U-16V_6

1U-16V_6

7

8

25

C409

C451

C451

0.1U-10V_4

0.1U-10V_4

3VSUS

R242

R242
CR@10K_4

CR@10K_4

3VSUS

C411

C411

0.1U-10V_4

0.1U-10V_4

C410

C410

0.1U-10V_4

0.1U-10V_4

Supporting MMC/SD/MS Cards

U22D

U22D

K1

1.5V_00

K19

1.5V_01

U19

VDDPLL33

H6

GND_00

K6

GND_01

N6

GND_02

P7

GND_03

P9

GND_04

M14

GND_05

K14

GND_06

G14

GND_07

F13

GND_08

F10

GND_09

F7

GND_10

PCI7412

PCI7412

TPS_CLOCK

R457

R457
*47K_4

*47K_4

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

PCI7412 - 3 IN 1 / CARD BUS

PCI7412 - 3 IN 1 / CARD BUS

PCI7412 - 3 IN 1 / CARD BUS

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

C409
CR@.1U-10V_4

CR@.1U-10V_4

Q35

Q35
TPS2061DGNR

TPS2061DGNR

2

IN1

OUT3

IN23OUT2
EN#

GND
GND-C

OUT1

OC#

4
1
9

P/N:DFHS19FR012Foxconn

VCC33_00
VCC33_01
VCC33_02
VCC33_03
VCC33_04
VCC33_05
VCC33_06
VCC33_07
VCC33_08
VCC33_09
VCC33_10

AVDD33_00
AVDD33_01

Power/GND

Power/GND

AVDD33_02

VCCP_00
VCCP_01

8
7
6

5

J6
L6
P6
P8
P10
L14
J14
F14
F12
F9
F6

P13
P14
U15

P1
W8

25 42Tuesday, March 14, 2006

25 42Tuesday, March 14, 2006

25 42Tuesday, March 14, 2006

8

C443

C443
CR@.1U-10V_4

CR@.1U-10V_4

VCC_FM

C598

C598
10U-10V_8

10U-10V_8

3VSUS

1394_AVDD

3VSUS

of

of

of

1A

1A

1A

5

4

3

2

1

M/B TO MODEM/B

CN25

CN25

LAD0(12,27,30)
LAD1(12,27,30)
LAD2(12,27,30)
LAD3(12,27,30)

PCLK_LPC(3)

LDRQ#0(12,27,30)

LFRAME#(12,27,30)

PLTRST#(13,14,18,27,32)

SERIRQ(14,24,27,30)
CLKRUN#(14,24,27,30,33)
14M_SIO(3)

SUS_STAT#(14,24,27)

+3VRUN
+5VRUN

3VSUS

MODEM B TO B(88019-40N0)

MODEM B TO B(88019-40N0)

IRRX
IRMODE
IRTXOUT

PCLK_LPC

IRTXOUT
IRRX
IRMODE

3VPCU

MY4
MY5
MY6
MY7

MY12
MY13
MY14
MY15

MX4
MX5
MX6
MX7

3VPCU

10

10

10

RP53

RP53

9
8
7 4

10KX8

10KX8
RP55

RP55

9
8
7 4

10KX8

10KX8
RP57

RP57

9
8
7 4

10KX8

10KX8

MY3

1

MY2

2

MY1

3

MY0

56

MY11

1

MY10

2

MY9

3

MY8

56

MX3

1

MX2

2

MX1

3

MX0

56

LPC SIO

IR

INT K/B

MY15(30)
MY14(30)

D D

MY13(30)
MY12(30)
MY11(30)
MY10(30)
MY9(30)
MY8(30)
MY7(30)
MY6(30)
MY5(30,31)
MY4(30)
MY3(30)
MX7(30)
MX6(30)
MY2(30)
MX5(30)
MX4(30)
MX3(30)
MX2(30)
MY1(30)
MY0(30)
MX1(30,31)
MX0(30)

MY15
MY14
MY13
MY12
MY11
MY10
MY9
MY8
MY7
MY6
MY5
MY4
MY3
MX7
MX6
MY2
MX5
MX4
MX3
MX2
MY1
MY0
MX1
MX0

MY0
MY1
MY2
MX0
MX1
MX2
MX3
MY3
MY4
MX4
MX5
MX6
MX7
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

KB-CON(85201-24051)

KB-CON(85201-24051)

CN6

CN6

1/27 update keymatrix as

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

USBP3­USBP3+

USBP4­USBP4+

USBP5­USBP5+

RING#

U20

U20

3

TXD

4

RXD

5

SD

8

GND

VISHAY_TFDU6102_8P

VISHAY_TFDU6102_8P

VCC

MODE

LED_C
LED_A

same as le1

C C

R565

R565
*22_4

*22_4

C707

C707
*10P_4

*10P_4

USBP3- (13)
USBP3+ (13)

USBEN_RJ# (14)
USBP4- (13)
USBP4+ (13)

USBEN_LS# (14)
USBP5- (13)
USBP5+ (13)

USBEN_LE3# (14)

RI# (14,24)

5VSUS

+3VRUN

6
7

2
1

FIR_LED_A

R206 5.6_1206R206 5.6_1206
R216 5.6_1206R216 5.6_1206

C407

C407
*10U/10V_8

*10U/10V_8

T = 20mil

C413

C413

0.1U_4

0.1U_4

T = 20mil

R228 *0_12R228 *0_12

Change USBEN meaning from OC#

LE4 C:

to GPIO#

C420

C420
10U/10V_8

10U/10V_8

+3VRUN

C419

C419
10U/10V_8

10U/10V_8

+5VRUN

C390

C390
10U/10V_8

10U/10V_8

Reverse +3V to FIR LED_A

26

HOLE13

HOLE6

*H-C354D106P2

*H-C354D106P2

HOLE6

1

*H-C354D106P2

*H-C354D106P2

CRT and
SV
between

HOLE15

H-C354D106P2

H-C354D106P2

B B

HOLE15

1

VGA-RU

HOLE1

*H-C354D106P2

*H-C354D106P2

HOLE1

1

Audio Jack

HOLE2

*H-TC236BC354D106P2

*H-TC236BC354D106P2

A A

HOLE2

1

PCMCIA-L-M

HOLE5

*H-C354D106P2

*H-C354D106P2

HOLE5

1

*H-C354D106P2

*H-C354D106P2

N.B and BIOS
between

PCMCIA-R-M

HOLE13

1

LID
between

HOLE7

HOLE7

1

5

HOLE11

*H-C354D106P2

*H-C354D106P2

HOLE11

1

ODD-RLAN and

HOLE12

*H-C236BC354D106P2

*H-C236BC354D106P2

HOLE12

1

ODD-L+screw

HOLE14

*H-C354D106P2

*H-C354D106P2

HOLE14

1

Power/B

HOLE4

*H-C354D106P2

*H-C354D106P2

HOLE4

1

CRAD BUS R-DOWN

HOLE3

*H-C354D106P2

*H-C354D106P2

HOLE3

1

1394

HOLE24

H-C236D150P2

H-C236D150P2

HOLE24

H-C238D150P2

H-C238D150P2

IO Module NUT

HOLE23

HOLE23

1

1

H-C236D106P2

H-C236D106P2

HDD NUT

HOLE9

HOLE9

1

4

VGA+N.B. NUT

HOLE16

*H-C2380150P2

*H-C2380150P2

HOLE16

1

CPU NUT

HOLE22

H-C238D150P2

H-C238D150P2

H-C238D150P2

H-C238D150P2

HOLE22

1

HOLE17

HOLE17

1

Modem NUT

HOLE10

HOLE10

H-C236D142P2

H-C236D142P2

1

HOLE20

H-C238D150P2

H-C238D150P2

H-C238D150P2

H-C238D150P2

HOLE20

HOLE19

HOLE19

H-C238D150P2

H-C238D150P2

H-C238D150P2

H-C238D150P2

H-C236D142P2

H-C236D142P2

1

1

HOLE18

HOLE18

1

HOLE21

HOLE21

1

HOLE8

HOLE8

1

EMIPAD158X87

EMIPAD158X87

EMIPAD158X87

EMIPAD158X87

3

P24

HOLE25

HOLE25

H-C236D142P2

H-C236D142P2

1

P29

P29

EMIPAD158X87

EMIPAD158X87

1

P7

P7

EMIPAD158X87

EMIPAD158X87

1

H-C236D142P2

H-C236D142P2

P24

EMIPAD158X87

EMIPAD158X87

1

P9

P9

EMIPAD158X87

EMIPAD158X87

1

HOLE26

HOLE26

1

P23

P23

EMIPAD158X87

EMIPAD158X87

1

P10

P10

EMIPAD158X87

EMIPAD158X87

PCIe-NUT

BOTTON TOP

E@EMI

E@EMI

E@EMI

P21

P21

1

P18

P18

1

E@EMI

E@EMI

E@EMI

E@EMI

P22

P22

EMIPAD158X87

EMIPAD158X87

1

P17

P17

EMIPAD158X87

EMIPAD158X87

1

E@EMI

E@EMI

E@EMI

E@EMI

P20

P20

EMIPAD158X87

EMIPAD158X87

1

P19

P19

EMIPAD158X87

EMIPAD158X87

1

E@EMI

E@EMI

E@EMI

P4

P4

EMIPAD158X87

EMIPAD158X87

P2

P2

EMIPAD158X87

EMIPAD158X87

E@EMI

E@EMI

EMIPAD158X87

EMIPAD158X87

EMIPAD158X87

EMIPAD158X87

1

EMIPAD158X87

EMIPAD158X87

1

EMIPAD158X87

EMIPAD158X87

1

P27

P27

1

P14

P14

1

E@EMI

E@EMI

P5

P5

1

P3

P3

1

E@EMI

E@EMI

2

P11

P11

EMIPAD158X87

EMIPAD158X87

1

P25

P25

EMIPAD158X87

EMIPAD158X87

1

E@EMI

E@EMI

P6

P6

EMIPAD158X87

EMIPAD158X87

1

P12

P12

EMIPAD158X87

EMIPAD158X87

1

P16

P16

EMIPAD158X87

EMIPAD158X87

1

P26

P28

P28

EMIPAD158X87

EMIPAD158X87

1

P1

P1

EMIPAD158X87

EMIPAD158X87

1

AGND

EMIPAD158X87

EMIPAD158X87

P8

P8

EMIPAD158X87

EMIPAD158X87

1

P15

P15

EMIPAD158X87

EMIPAD158X87

1

P13

P13

1

P26

EMIPAD158X87

EMIPAD158X87

1

P30

P30

EMIPAD158X87

EMIPAD158X87

1

MIC

S8-90

S8-90

P31

P31

1

LE4 C:

Arrange modem cable

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

SCREW hole EMI pad

SCREW hole EMI pad

SCREW hole EMI pad

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

26 42Tuesday, March 14, 2006

26 42Tuesday, March 14, 2006

26 42Tuesday, March 14, 2006

of

of

1

of

1A

1A

1A

1

2

3

4

5

6

7

8

27

A A

B B

For Debug Only

Need one more wireless LED /mini card on MB ?
currently , No LED here

R306 0_6R306 0_6

1 2

*DLW21HN900SQ2L

*DLW21HN900SQ2L

USBP1-(13)
USBP1+(13)

1
4 3

CML1

CML1

R303 0_6R303 0_6

1 2

2

CARD_USBP6-

CARD_USBP6­CARD_USBP6+

CARD_USBP6+

LE4 B:

Add debug function

CLKRUN#(14,24,26,30,33)

SERIRQ(14,24,26,30)

LDRQ#0(12,26,30)

SUS_STAT#(14,24,26)

PCI-Express TX and RX direct to connector

0816a

PCLK_LPC_DEBUG(3)

PCIE_TXP0(13)
PCIE_TXN0(13)

PCIE_RXP0(13)
PCIE_RXN0(13)

PCLK_LPC_DEBUG

CLK_PCIE_MINI(3)
CLK_PCIE_MINI#(3)

PLTRST#

PLTRST#(13,14,18,26,32)

PCIE_WAKE#(14)

T103T103
T100T100
T101T101

PCIE_TXP0
PCIE_TXN0

PCIE_RXP0
PCIE_RXN0

R291 0_6R291 0_6

R293 0_6R293 0_6

CLK_PCIE_MINI

CLK_MINI_OE#

CCI_CLK
CCI_DATA

13

Q21

Q21

DTC144EUA

DTC144EUA

2

3VSUS

PCI-E Mini Card

CN22

CN22

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

Reserved

41

Reserved

39

Reserved

37

Reserved

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

Reserved

17

Reserved

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

67910-0002

67910-0002

67910-0002

LED_WPAN#
LED_WLAN#

LED_WWAN#

USB_D+

SMB_DATA

SMB_CLK

+3.3Vaux

PERST#

Reserved

Reserved
Reserved
Reserved
Reserved
Reserved

boss53boss

54

+3.3V

GND

+1.5V

GND

USB_D-

GND

+1.5V

GND

GND

+1.5V

GND

+3.3V

3VSUS

+1.5V+3VRUN

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

LAD0_1

16

LAD1_1

14

LAD2_1

12

LAD3_1

10
8
6
4
2

R296 0_6R296 0_6

LAD1_1
LAD0_1
LAD3_1
LAD2_1

R288 0_6R288 0_6

+3VRUN

R308 *0_6R308 *0_6
R305 *0_6R305 *0_6
R304 0_6R304 0_6

CARD_USBP6+
CARD_USBP6-

PLTRST#

RP52 0X2RP52 0X2

1
3
1
3

RP50 0X2RP50 0X2

+3VRUN

T259T259

T255T255

2 1

R298 *10K_6R298 *10K_6

2
4
2
4

LFRAME#

BLUELED
RF_LINK

CGDAT_SMB (3,16,17)
CGCLK_SMB (3,16,17)

LAD1
LAD0
LAD3CLK_PCIE_MINI#
LAD2

0816a

+3VRUN

D4
RB500D4RB500

T129T129

T121T121

+3VRUN

R313

R313

*10K_4

*10K_4

RF_OFF#

LAD1 (12,26,30)
LAD0 (12,26,30)
LAD3 (12,26,30)
LAD2 (12,26,30)

LFRAME# (12,26,30)

+3VRUN

1 3

Q24 *PDTC144EUQ24 *PDTC144EU

RF_OFF# (30)

2

WIRELESS_LED

WIRELESS_LED (31)

RF_OFF#

LE4 C:

1. Del R298,Q24,R313,R305

2. Add Q36,Q37,R605 for enable
wireless led circiut

+3VRUN

R605

R605

10K-4

10K-4

3

2

Q37

Q37

2N7002K

2N7002K

1

2

1

Q36

Q36
SI2301BDS

SI2301BDS

3

WIRELESS_LED

LE4 A-1108:
+3VSUS change

+3VRUN +1.5V3VSUS

C430

C430

C456

C447

C447

0.1U_4

C C

D D

1

2

3

0.1U_4

C444

C444
1U/_P_6

1U/_P_6

C428

C428

0.1U_4

0.1U_4

4

C348

C348
10U/10V_8

10U/10V_8

0.01U_4

0.01U_4

C456

0.1U_4

0.1U_4

C450

C450
10U/10V_8

10U/10V_8

5

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

6

Date: Sheet

7

MIMI PCI e

MIMI PCI e

MIMI PCI e

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

of

of

of

27 42Tuesday, March 14, 2006

27 42Tuesday, March 14, 2006

27 42Tuesday, March 14, 2006

8

1A

1A

1A

A

B

C

D

E

LE4 A-1108:

4

3V_DVDD

C238

C238

0.1U_4

0.1U_4

3

42

0.1U/10V_4

0.1U/10V_4

C291

C291

45

8

DVDD

VDDIO

DVDDM

DVSS

VSSIO_46

VSSIO_42

6

46

04/9

12

R80 10K_4R80 10K_4

10K_4

10K_4

AVDD

C543

C543

0.1U_4

0.1U_4

37

20

31

AVDDHP

AVDD_20

AVDD_31

MIC_BIAS_L

MIC_BIAS_R

LINEOUT_L

LINEOUT_R

PORT-A_BIAS_L
PORT-A_BIAS_R

PORT-A_L

PORT-A_R

PORT-B_BIAS_L
PORT-B_BIAS_R

PORT-B_L

PORT-B_R

VREF_LO

VC_REFA

AVSS_25

AVSSHP

AVSS_12

AVSS_32

25

40

12

32

AGND

ANALOG

E200505-0166

5/6 update

R84

R84

MIC_L

MIC_R

CD_L

CD_GND

CD_R

SENSE

VREF_HI

0.47U/10V_6

0.47U/10V_6

C232

C232

C230

C230

0.1U_4

0.1U_4

29
30
21
22

35
36

33
34
38
39

14
15
23
24

17
18
19

13

26
27
28

C260

C260

0.1U_4

0.1U_4

AGND

MICBIAS_INT
INT_MIC

LINEIN_L_1
LINEIN_R_1

EXT_MICBIAS_L
EXT_MICBIAS_R
EXT_MIC_L
EXT_MIC_R

CDAUDL

C229 1U/16V_6C229 1U/16V_6

CDGND
CDAUDR

C216 1U_6C216 1U_6

SENSE

R75 5.11K/F_6R75 5.11K/F_6

R71 5.11K/F_6R71 5.11K/F_6

R68 10K/F_4R68 10K/F_4

R69 39.2K_4R69 39.2K_4

R70 20K_4R70 20K_4

VREF_HI
VREF_LO
VC_REFA

BEEPPCBEEP

C202

C202
10U/10V_8

10U/10V_8

C263 1U_6C263 1U_6
C262 1U_6C262 1U_6

C540 1U_4C540 1U_4

3VSUS

For associated Line Side
Device portion of this
design
see Conexant RD02-D450
reference schematic

VDDIO is used in determining which HD Audio bus voltage
is present on the system. When VDDIO is +1.5V, the
device will use 1.5v signaling on the HDA interface pins;
when VDDIO is +3.3v, the device will use 3.3v signaling
on the HDA interface pins.

ACZ_RST#_AUDIO(12)

BIT_CLK_AUDIO(12)

ACZ_SYNC_AUDIO(12)

ACZ_SDIN0(12)

ACZ_SDOUT_AUDIO(12)

DIBP_HS(29)

DIBN_HS(29)

EAPD(29)

R399

1 1

R399
*22_4

*22_4

AMP_BEEP(14)

C544

C544
*10P_4

*10P_4

PCMSPK(24)

ACZ_SPKR(14)

MUTE#(29,30)

ACZ_RST#_AUDIO
BIT_CLK_AUDIO

ACZ_SYNC_AUDIO
ACZ_SDOUT_AUDIO

DIBP_HS

DIBN_HS

Near To
Codec

EAPD

3V_DVDD

BIT_CLK_AUDIO
ACZ_SYNC_AUDIOACZ_SYNC_AUDIO

ACZ_SDIN0

C542

C542

C236

C236

*10P_4

*10P_4

*10P_4

*10P_4

L50

L50

1 2

BK2125HS330-T

BK2125HS330-T

R104 33_4R104 33_4

R99 0_4R99 0_4

R122 0_4R122 0_4

R123 0_4R123 0_4

R403 237K/F_8

R403 237K/F_8

RC0805

RC0805

U15

U15

74AHCT1G86GW

74AHCT1G86GW

1
2

R153 *0_4R153 *0_4

DIBP

DIBN

BEEP

RCOSC

+5VRUN

3 5

74AHCT1G08GW

74AHCT1G08GW

C247

C247
10U/10V_8

10U/10V_8

BITCLK

SDI

C301

C301

0.1U/10V_4

0.1U/10V_4

4

U14

U14

10

5
9
7
4

44

43

11

48

47

1
2

16
41

12

1
2

C243

C243

0.1U_4

0.1U_4

U11

U11

RESET#
BIT_CLK

SYNC
SDI
SDO

DIBP

DIBN

PCBEEP

SPDIF

EAPD

NC_1
NC_2
NC_16

RCOSC

CX20549-12

CX20549-12

DIGITAL

+5VRUN

53

BEEP

MIC

R572 *0_4R572 *0_4

LE4 B:

add R572

LE4 C:

Cancel R572

ADD R80,R84,U15,U14,C301,C291

1 2

L21 *BK2125HS330-TL21 *BK2125HS330-T
U10

U10
GMT_G910T21U

GMT_G910T21U

1

Vout

AGND

C215 1U/16V_6C215 1U/16V_6

SENSE_MIC

AGND

3

Vin

GND

2

LINEOUT_L (29)
LINEOUT_R (29)

HPOUT_L
HPOUT_R

AGND

AVDD

SENSE_PORT_A
SENSE_PORT_B

C541 1U_4C541 1U_4

+3VRUN

HPOUT_L (29)
HPOUT_R (29)

T19T19

C69

C69
1U_4

1U_4

Speaker

MIC IN

T20T20

SENSE_LINEOUT (29)

C75

C75

0.1U_4

0.1U_4

EXT_MIC_R

+5VRUN

C59

C59
10U/10V_8

10U/10V_8

C227 10U_8C227 10U_8
C226 10U_8C226 10U_8

EXT_MICBIAS_R
EXT_MICBIAS_L

AGND

R64

R64

2.2K_4

2.2K_4

R63

R63
*1K_4

*1K_4

AGND

R77 *10K_4R77 *10K_4
R76 *10K_4R76 *10K_4

R65

R65

2.2K_4

2.2K_4

R66

R66
*1K_4

*1K_4

AVDD
AVDD

R_SYS_MIC_1 SYS_MIC_1
R_SYS_MIC_2EXT_MIC_L

SENSE_PORT_B

L1 BK1608LL121_6L1 BK1608LL121_6
L3 BK1608LL121_6L3 BK1608LL121_6

R6 0_6R6 0_6

C2
100P_4C2100P_4

AGND AGND

C5
100P_4C5100P_4

SYS_MIC_2

MIC JACK

CN13

CN13

1
2
6
3
4
5

JACK_MIC(010178FR006G101JL)

JACK_MIC(010178FR006G101JL)

AGND

Fox : JA6333L-1S0-TR => AC97
JA6333L-3S0-TR => Azalia

LE4 B:

SWAP CN13,CN14
position and Change
Footprint

7

8

28

AGND

MICBIAS_INT

CN12

C: Change to 0_4

CN12

R343

R343

INT_MIC

0_4

0_4

MICGND

A

INT_MIC

INT_MIC1 R_INT_MIC

1
2

MICGND

R344

R344

0_4

0_4

R342

R342
*1K_4

*1K_4

MICGND

B

L40 BK1608LL121_6L40 BK1608LL121_6

C478

C478
100P_4

100P_4

L_INT_MIC INT_MIC

C

R394 *10K_4R394 *10K_4

R395

R395

2.2K_4

2.2K_4

C539 10U_8C539 10U_8

R390

R390
*1K_4

*1K_4

AGND

AVDD

LE4 C:

Modidy bias voltage type from C539 before

D

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Azalia Codec / Audio Jack

Azalia Codec / Audio Jack

Azalia Codec / Audio Jack

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

28 42Tuesday, March 14, 2006

28 42Tuesday, March 14, 2006

28 42Tuesday, March 14, 2006

of

of

E

of

1A

1A

1A

1

2

3

4

5

6

7

8

0816a

29

AMPVDD

C102

C102

1U/10V_6

1U/10V_6

AMPVDD

C109

20
14
13
4

5
17
18

6
3
16
19

C109

0.1U/10V_4

0.1U/10V_4

HPS
R_SPKL
R_SPKR
INTSPKL+

INTSPKL­INTSPKR­INTSPKR+

AMPVDD

LE4 C:

Support Vista function

AGND

SPKL
SPKR

C110

C110

0.1U_4

0.1U_4

AGND

R608 0_4R608 0_4
R607 0_4R607 0_4

C119

C119

0.1U_4

0.1U_4

C55

C55
10U/10V_8

10U/10V_8

LE4 A:

Place near Audio port with CN26

AGND

HPOUT_L(28)
HPOUT_R(28)

2N7002K

2N7002K

AMPVDD

C67

C67

0.1U/10V_4

AGND

C57

C57
1U/10V_6

1U/10V_6

0.1U/10V_4

1

27

2

28

24
23
22
21

NC
NC
INL
INR

GAIN
GND
/SHDN
VBIAS

15

8

C1P

HPVDD

U6

U6

10

12

R8 0_4R8 0_4

25

VDD

MAX9755ETI+

MAX9755ETI+

GND26CPGND9CPVSS11VSS

7

C1N

CPVDD

OUTL+

OUTL­OUTR-

OUTR+
PVDDL

PGNDL
PVDDR

PGNDR

C94

C94
1U/10V_6

1U/10V_6

HPS
HPL

HPR

A A

EAPD
low:mute

MUTE#(28,30)

EAPD(28)

LE4 B:

B B

LINEOUT_L(28)
LINEOUT_R(28)

C64

C64

*0.1U_4

*0.1U_4

add D17 and R573

LE4 C:

slove power on systrm
when the sound had
bob

C545 1.0U/16V_8x5C545 1.0U/16V_8x5

LINEOUT_L

C547 1.0U/16V_8x5C547 1.0U/16V_8x5

LINEOUT_R

12

53

1
2

D17 CH500H-40D17 CH500H-40

+5VRUN

4

U5

U5
*74AHCT1G08GW

*74AHCT1G08GW

+5VRUN

GAIN

MUTE GAIN

R573

R573
100K_4

100K_4

AGND AGNDAGND

AUDIO POWER

C6 *100P_4C6 *100P_4

AUDIO POWER

R60 0_8R60 0_8
R61 0_8R61 0_8

*AME8815BEGT475

*AME8815BEGT475

U8

+5VRUN

80 MIL

+5VAUDIO_IN

C C

C535 47U/6.3V_1210C535 47U/6.3V_1210

2 1

C210 1U_10V_6C210 1U_10V_6

U8

80 MIL

L16 PBY201209T-300Y-N_8L16 PBY201209T-300Y-N_8

AGND

1

GND

Vout

2

4

Vout

C131 10U_10V_8C131 10U_10V_8
C126 10U_10V_8C126 10U_10V_8

3

Vin

AGND

R348 0_4R348 0_4 L46 BK1608LL121_6L46 BK1608LL121_6

08/04:Change CN5 Left/right pin define and P/N

LE4 C:

Del R350

R9 0_4R9 0_4

C7 1000P_4C7 1000P_4

D D

AGND

Place near Audio port with CN14

1

LE4 A:

2

Place near audio codec

3

4

+5VRUN

R45

R45
10K_4

10K_4

3

Q1

Q1

C500

C500
10U/10V_8

10U/10V_8

2

1

SENSE_LINEOUT_A

LE4 C:

Support Vista function

R609 *0_4R609 *0_4
R610 *0_4R610 *0_4

C266 *100P_4C266 *100P_4
C265 *0.01U_4C265 *0.01U_4

R135 0_8R135 0_8
R417 *0_8R417 *0_8
R426 *0_8R426 *0_8

LE4 A:

GAIN SPKR

MODE

0

10.5

1

5

9

SPKL
SPKR SPKR_0

AGND

HP

MODE

3

0

100P_4

100P_4

INTSPKL+
INTSPKL-
INTSPKR+
INTSPKR-

100P_4

100P_4

R2 330_4R2 330_4
R3 330_4R3 330_4

AMPVDD

R51

R51
*1K_6

*1K_6

R49

R49
1K_6

1K_6

AGND

AGND AGND

C506

C506

C509

C509

AGND AGND

C505

C505
100P_4

100P_4
L43 BK1608LL121_6L43 BK1608LL121_6

L45 BK1608LL121_6L45 BK1608LL121_6
L47 BK1608LL121_6L47 BK1608LL121_6

C512

C512
100P_4

100P_4

SPKL_0

R4
*1K_4R4*1K_4

AGND AGND

L2 BK1608LL121_6L2 BK1608LL121_6
L4 BK1608LL121_6L4 BK1608LL121_6

R1
*1K_4R1*1K_4

LE4 B:

Change GND plane from
AUDGND to AGND

SENSE_LINEOUT(28)

6

INSPKL+_R
INSPKL-_R
INSPKR+_R
INSPKR-_R

C4
470P_4C4470P_4

AGND

AMPVDD

1

AHCT1G125DCH

AHCT1G125DCH

CN21

CN21

910
78
56
34
12

MODEM_B2B

MODEM_B2B

Modem connector

INT_SPK

CN2

CN2

1
2

5

3

6

4

SPEAKER-CON(CWY040-B0G1Z)

SPEAKER-CON(CWY040-B0G1Z)

2/16 swap audio conn
pin define

SPKL-R
SPKR-R

C3

SENSE_LINEOUT_A

C1

5

0.1U_6C10.1U_6

24

U1

U1

AGND

470P_4C3470P_4

AGND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

audio-010164fr006gx35xl-6p

audio-010164fr006gx35xl-6p

When Docking insert , disable BTL

Audio Amp.

Audio Amp.

Audio Amp.

DIBP_HS (28)
DIBN_HS (28)

CN14

CN14

1
2
6
3
4
5

HEADPHONE

HEADPHONE

R5

7

8

AGND

+5VRUN

10K_6R510K_6

LE4 B:

SWAP CN13,CN14
position and Change
Footprint

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

1A

1A

1A

29 42Tuesday, March 14, 2006

29 42Tuesday, March 14, 2006

29 42Tuesday, March 14, 2006

of

of

of

8

5

D D

+3VRUN

LDRQ#(pin 8) internal is no use

LDRQ#0(12,26,27)

3VPCU

R505

R505
470K_4

470K_4

12

0816a

C643

C643
10P_4

10P_4

PCLK_541

12

R504

R504
*10_4

*10_4

C C

B B

A A

+5VRUN

12

C642

C642
*10P_4

*10P_4

RN6 10KX4RN6 10KX4

6
4
2

R338 10K_4R338 10K_4
R333 10K_4R333 10K_4

LFRAME#(12,26,27)

LAD0(12,26,27)
LAD1(12,26,27)
LAD2(12,26,27)
LAD3(12,26,27)

PCLK_541(3)

MSCLK

78

MSDATA

5

KPCLK

3

KPDATA

1

TPCLK
TPDATA

TPCLK(31)
TPDATA(31)
CAPSLED#(31)
NUMLED#(31)

GRST#_7402(24)

DNBSWON#(14)

LDRQ#0 DRQ0#

SERIRQ(14,24,26,27)

KBSMI#(14)

SCI#(14)

MX0(26)
MX1(26,31)
MX2(26)
MX3(26)
MX4(26)
MX5(26)
MX6(26)
MX7(26)

MY0(26)
MY1(26)
MY2(26)
MY3(26)
MY4(26)
MY5(26,31)
MY6(26)
MY7(26)
MY8(26)

MY9(26)
MY10(26)
MY11(26)
MY12(26)
MY13(26)
MY14(26)
MY15(26)

FANLESS#(4)

HWPG(36,37,38,39,41)
SUSC#(14)

SWI#(14)
MUTE#(28,29)
S5_ON(40)

SUSON(36,40)
MAINON(36,38,40,41)

T260T260

VRON(37)

RSMRST#(14)
PWROK(14,22)

Battery LED BLUE
and AMBER

5

R502 *0_6R502 *0_6

SERIRQ

LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_541
591RESET#
KBSMI#

SCI#

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15

PS/2 to Port Replicator

MSCLK
MSDATA
KPCLK
KPDATA
TPCLK
TPDATA
CAPSLED#
NUMLED#

FANLESS#
HWPG
SUSC#
SWI# 551_SWI#
GRST#_7402
MUTE#

S5_ON
SUSON
MAINON
LAN_POWER
VRON
DNBSWON#
RSMRST#
PWROK

MBCLK
MBDATA

2 1

D9 BAS316D9 BAS316

2 1

D10 BAS316D10 BAS316

R300 20M_4R300 20M_4

Y4

Y4

2 3

C452

C452

32.768KHZ

32.768KHZ

20P_4

20P_4

BG332768747

2 1

D13 BAS316D13 BAS316

D11 BAS316D11 BAS316

2 1

R507 0_4R507 0_4

CS#

U27

U27

6

SCL

5

SDA

7

WP

*NM24C08

*NM24C08

GATEA20(12)

VCC
GND

T104T104

RCIN#(12)

41

1

A0

2

A1

3

A2

8
4

DRQ0#

551_KBSMI#

551_SCI#

GATEA20
RCIN#

T140T140
T143T143
T142T142
T137T137

R299 120K_4R299 120K_4

C445

C445

5.6P_4

5.6P_4

T112T112
T232T232

3VPCU

TINT-

541_32KX1

541_32KX2

541SEL1#
541CLK

4

3VPCU +3VALW_541

R564 0_8

R564 0_8

RC0805

RC0805

C661

C661

0.1U/10V_4

0.1U/10V_4

C641

C641

0.1U/10V_4

0.1U/10V_4

4

U25

U25

7

SERIRQ

8

LDRQ

9

LFRAME

15

LAD0

14

LAD1

13

LAD2

10

LAD3

18

LCLK

19

LREST

22

SMI

23

PWUREQ

31

IOPD3/ECSCI

5

GA20/IOPB5

6

KBRST/IOPB6

71

KBSIN0

72

KBSIN1

73

KBSIN2

74

KBSIN3

77

KBSIN4

78

KBSIN5

79

KBSIN6

80

KBSIN7

49

KBSOUT0

50

KBSOUT1

51

KBSOUT2

52

KBSOUT3

53

KBSOUT4

56

KBSOUT5

57

KBSOUT6

58

KBSOUT7

59

KBSOUT8

60

KBSOUT9

61

KBSOUT10

64

KBSOUT11

65

KBSOUT12

66

KBSOUT13

67

KBSOUT14

68

KBSOUT15

105

TINT

106

TCK

107

TDO

108

TDI

109

TMS

110

PSCLK1/IOPF0

111

PSDAT1/IOPF1

114

PSCLK2/IOPF2

115

PSDAT2/IOPF3

116

PSCLK3/IOPF4

117

PSDAT3/IOPF5

118

PSCLK4/IOPF6

119

PSDAT4/IOPF7

158

32KX1/32KCLKOUT

160

32KX2

62

IOPJ2/BST0

63

IOPJ3/BST1

69

IOPJ4/BST2

70

IOPJ5/PFS

75

IOPJ6/PLI

76

IOPJ7/BRKL_RSTO

148

IOPM0/D8

149

IOPM1/D9

155

IOPM2/D10

156

IOPM3/D11

3

IOPM4/D12

4

IOPM5/D13

27

IOPM6/D14

28

IOPM7/D15

173

SEL0

174

SEL1

47

CLK

AJ875410F34

AJ875410F34

16

VDD

Host interface

Host interface

Key matrix scan

Key matrix scan

JTAG debug port

JTAG debug port

PS2 interface

PS2 interface

PORTM

PORTM

L39

L39
FBM2125HM330_8

FBM2125HM330_8

123

VCC134VCC245VCC3

PORTJ-2

PORTJ-2

GND117GND235GND346GND4

122

159

GND5

136

157

VCC4

VCC5

PORTD-1

PORTD-1

GND6

GND7

167

137

551_AVCC

166

95

VCC6

AVCC

AD Input

AD Input

DA output

DA output

PWM

PWM
or PORTA

or PORTA

PORTB

PORTB

PORTC

PORTC

PORTE

PORTE

IOPE6/LPCPD/EXWIN45

IOPE7/CLKRUN/EXWINT46

PORTH

PORTH

PORTI

PORTI

PORTJ-1

PORTJ-1

PORTD-2

PORTD-2

PORTK

PORTK

PORTL

PORTL

AGND

NC1

96

11

VCCRTC

0816a

0.1U/10V_4

0.1U/10V_4

IOPC4/TB1/EXWINT22
IOPC6/TB2/EXWINT23

IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21

NC212NC320NC421NC585NC686NC791NC892NC997NC10

R532

R532

C475

C475

161

VBAT

IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7

DP/AD8
DN/AD9

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

IOPB0/URXD
IOPB1/UTXD

IOPB2/USCLK

IOPB3/SCL1

IOPB4/SDA1

IOPB7/RING/PFAIL

IOPC0
IOPC1/SCL2
IOPC2/SDA2

IOPC3/TA1
IOPC5/TA2

IOPC7/CLKOUT

IOPD2/EXWINT24

IOPE4/SWIN

IOPE5/EXWINT40

IOPH0/A0/ENV0

IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1

IOPH4/A4/TRIS

IOPH5/A5/SHBM

IOPH6/A6
IOPH7/A7

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

IOPJ0/RD

IOPJ1/WR0

SELIO
IOPD4

IOPD5
IOPD6
IOPD7

IOPK0/A8

IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12

IOPK5/A13/BE0
IOPK6/A14/BE1

IOPK7/A15/CBRD

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19

IOPL4/WR1

C629

C629
1U/10V_6

1U/10V_6

*0_4

*0_4

AD0
AD1
AD2
AD3

DA0
DA1
DA2
DA3

3

R297

81
82
83
84
87
88
89
90
93
94

99
100
101
102

32
33
36
37
38
39
40
43

153
154
162
163
164
165

168
169
170
171
172
175
176
1

26
29
30

2
44
24
25

124
125
126
127
128
131
132
133

138
139
140
141
144
145
146
147

150
151

152
41

42
54
55

143
142
135
134
130
129
121
120

113
112
104
103
48

R297

TEMP_MBAT
MBATV

L_SENSOR

MBID0
MBID1
MBID2

PR_INSERT#

CC-SET
CV-SET

BT1#
BT2#
VFAN
BT_OFF#
RF_OFF#

R511 0_4R511 0_4

BATLED_BLUE#
BATLED_AMBER#
PWR_BLUE#
MBCLK
MBDATA
PLTRST_R#

PM_BATLOW#_X
ABCLK
ABDATA

FANSIG
BT4#

THERM_CPUDIE#
SUSB#

ACIN
LID551#

NBSWON#
LCD_BLON_EC
591_PME#
CLKRUN#

ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7

D0
D1
D2
D3
D4
D5
D6
D7

RD#
WR#

IOSEL#

A8
A9
A10
A11
A12
A13
A14
A15

A16
A17
A18

C446

C446
*0.1U/10V_4

*0.1U/10V_4

98

LE4 A:

Change Power plan

LAN_PME#(33)

3

+3VALW_541

C455

C473

C473

10U/10V_8

10U/10V_8

Should have a 0.1uF capacitor close to

0_4

0_4

every GND-VCC pair + one larger cap on

C455

0.1U/10V_4

0.1U/10V_4

C438

C438

0.1U/10V_4

0.1U/10V_4

C462

C462

0.1U/10V_4

0.1U/10V_4

the supply.

TEMP_MBAT (35)
MBATV (35)

T134T134
T135T135
T136T136

T138T138
T265T265
T139T139
T141T141

BT3#

T127T127
T108T108

CELL_SET (35)
D/C# (35)
BL/C# (35)

R516 *0_4R516 *0_4

AKE358AKZ61
AKE358AKZ87 IC EEPROM(40P)MX29LV008CTTC-70G(1M*8)LF

R287

R287
*4.7K_4

*4.7K_4

T133T133

CC-SET (35)

T268T268

VADJ (22)

T144T144

BT1# (31)
BT2# (31)
VFAN (31)

T110T110

RF_OFF# (27)

NOVO_LED# (31)

R515 0_4R515 0_4

T109T109

BT3# (31)

T269T269

BATLED0# (31)
BATLED1# (31)
PWRLED# (31)
MBCLK (5,35)
MBDATA (5,35)

T106T106
T102T102
T107T107

FANSIG (31)

T267T267

BT4# (31)

THERM_CPUDIE# (4)

SUSB# (14)
ACIN (35)
LID551# (22,31)

NBSWON# (31)

CLKRUN# (14,24,26,27,33)

LE4 B:

LE4 B:

D12BAS316 D12BAS316

LE4 B:

Change BT4# from pin 43
to pin176

21

LE4 B:

Chnage pin 176 form
551_LPCPD# to BT4#

pin 24 add 591_PME#

IOSEL# is NC now

EC_FPBACK# (22)

LE4 B:

VCC1_PWROK

IC EEPROM(40P)MX29LV008BTTC-70G(1M*8)LF

+3V_S5+3V_S5 3VPCU

R273

2

1 3

Q20

Q20
PDTC143TT

PDTC143TT

R273

4.7K_4

4.7K_4

591_PME#

LE4 B:

Add R273 in BOM

2

C637

C637

0.1U/10V_4

0.1U/10V_4

LE4 B:

BT1#
BT4#
ENV1
BADDR0
BADDR1
SHBM

BADDR1-0 Index

0 0
0 1 4F
1 0
1 1

C622

C622

0.1U/10V_4

0.1U/10V_4

LE4 B:

Pull high, add
R594, R595

LCD_BLON_EC

R274

R274

100K_4

100K_4

1 2

Pull high, Add
R593, R592

LCD_BLON_EC (7,19,22)

Power LED controll

PM_BATLOW# (14)

3VPCU

pin 175 EC_FPBACK#

change to pin 41

R549

R549
10K_4

10K_4

BATLED0#

R548 *0_4R548 *0_4

BATLED1#

R535 *0_4R535 *0_4

FLASH

8Mbit (1M Byte),NO PLCC TYPE

AMD :Pin 10 is RESET# ; Pin12 is RY/BY#
SST :Pin10,12 are NC

U42

U42

CS#
RD#
WR#

21
20
19
18
17
16
15
14

8
7

36

6
5
4
3
2

1
40
13
37

22
24

9

SST39VF080

SST39VF080

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

CE#
OE#
WE#

RESET#/NC

RY/BY#/NC

NC1
NC2
NC3

VCC
VCC

GND
GND

25

D0

26

D1

27

D2

28

D3

32

D4

33

D5

34

D6

35

D7

10
12
29
38
11

31
30

23
39

1.AMD-29LV081B require MAX 500nS Tready for it's hardware
reset.And MAX6326_UR29 has >100mS reset timing.So we can tie
it's reset# pin to +3VALW directly.

2.SIO has internal 20 mS delay of VCC1_PWROK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

R593 4.7K_4R593 4.7K_4
R592 4.7K_4R592 4.7K_4
R332 10K_4R332 10K_4
R331 *10K_4R331 *10K_4
R330 *10K_4R330 *10K_4
R329 10K_4R329 10K_4

(HCFGBAH, HCFGBAL)

TINT­PR_INSERT#
NBSWON#

KBSMI#

PWROK

BT2#

BT3#

ABDATA
ABCLK
MBDATA
MBCLK

R536

R536
10K_4

10K_4

D0
D1
D2
D3
D4
D5
D6
D7

VCC1_PWROK

3VPCU

T266T266

12

C644

C644

0.1U/10V_4

0.1U/10V_4

PC87541 & FLASH

PC87541 & FLASH

PC87541 & FLASH

1

30

3VPCU

I/O Address

2E
4E

Reserved

R340 4.7K_4R340 4.7K_4
R559 4.7K_4R559 4.7K_4
R508 4.7K_4R508 4.7K_4

R503 4.7K_4R503 4.7K_4

R514 4.7K_4R514 4.7K_4

R594 4.7K_4R594 4.7K_4
R595 4.7K_4R595 4.7K_4

RN5 10KX4RN5 10KX4

6
4
2

T263T263
T262T262

12

C645

C645

0.047U/10V_4

0.047U/10V_4

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

Data

2F

(HCFGBAH, HCFGBAL)+1

3VPCU

+3VRUN

3VPCU

78
5
3
1

LE4 A:

for EC Debug

3VPCU

R558

R558
100K_4

100K_4

12

C693

C693

0.1U/10V_4

0.1U/10V_4

1

of

of

of

30 42Tuesday, March 14, 2006

30 42Tuesday, March 14, 2006

30 42Tuesday, March 14, 2006

1A

1A

1A

1

VFAN(30)

LE4 B:

Modify FAN control circuit

A A

+5VRUN

R409 0_4R409 0_4

VFAN1

D/A Output

FAN CONTROL

VFAN1

VFAN1

C710

C710

0.1U_4

0.1U_4

U12

U12

VIN2VO

1

VEN

4

VSET

G993

G993

2

10 mil10 mil

FANPWR = 1.6*VSET

3
5

GND
GND
GND
GND

6
7
8

C546

C546

4.7U/6.3V_8

4.7U/6.3V_8

3

FAN_PWR

+3VRUN

R134

R134
10K_4

10K_4

C280

C280
*0.01U_4

*0.01U_4

CN17

CN17

1
2
345

FAN

FAN

FANSIG (30)

4

5VSUS

USBEN_MB#(14)

C:Change C388 from 47uF-1210 to 100uF-3528,it can solve USB inrush issue

5

U3

U3
TPS2061DGNR

TPS2061DGNR

2

IN1

R43 0_4R43 0_4R404 100K_4R404 100K_4

12

IN23OUT2

4

EN#

1

GND

9

GND-C

OUT3
OUT1

OC#

8
7
6

5

MB USB PORT

R606

R606

6

USBPWR2

1 2

7

8

31

L6

OC2# (13)

R371 0_6R371 0_6
R372 0_6R372 0_6

USBPWR2

1

1
443

L42

L42
*DLW21HN900SQ2L

*DLW21HN900SQ2L

*0_4

*0_4

USBP2-(13)

USBP2+(13)

BK2125HS330_8

BK2125HS330_8

2

2

3

L6

BUSBP2­BUSBP2+

C491

C491
*22P_4

*22P_4

USB2POWER

+

+

C24

C24

470U/6.3V-7343

470U/6.3V-7343

C490

C490
*22P_4

*22P_4

LE2 RAMP: modify C388

CN1

CN1

1

5

2

6
3
4

USB CONN(020133MR004S500ZL)

USB CONN(020133MR004S500ZL)

2/2 chagne p/n to
DFHS04FR873

LE2 D:

BUTTON/B+LED/B

CN7

CN7

+3VRUN

CDLED#(32)

CAPSLED#(30)

NUMLED#(30)

SATA_LED#(12)

B B

NBSWON#(30)

BT1#(30)
BT2#(30)
BT3#(30)
BT4#(30)

PWRLED#(30)

NOVO_LED#(30)

3VPCU

CDLED#
CAPSLED#
NUMLED#
SATA_LED#

PWRLED#

C:change from 3VPCU to 3V_ALWAYS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

POWER/B(85201-24051)

POWER/B(85201-24051)

+3VRUN

C468

C468

0.1U_4

0.1U_4

3VPCU

C426

C426

0.1U_4

0.1U_4

CN11

CN11
LID SWITCH PROTECT

LID SWITCH PROTECT

12
34

+5VRUN

R561

R561
10K_4

10K_4

TPDATA(30)

TPCLK(30)

TOUCH PAD

20 MIL

L70

L70

+5V_TP

BK2125HS330_8

BK2125HS330_8

R560

R560
10K_4

10K_4

LZA10-2ACB104MT_6

LZA10-2ACB104MT_6
L69

L69
L68

L68
LZA10-2ACB104MT_6

LZA10-2ACB104MT_6

C703 0.1U_4C703 0.1U_4

C702

C702
*0.1U_4

*0.1U_4

C698

C698
*0.1U_4

*0.1U_4

REVB P/N&FT CHANGE

CN9

CN9

TP_DATA
TP_CLK

TP/B TO MB(85201-0405L)

TP/B TO MB(85201-0405L)

1
2
3
4 5

6

LE2 D:

SW1

C C

LID551#(22,30)

LID591#

1
2

SW1

MISAKI_LID

MISAKI_LID

3
4

SW3

NBSWON#

3VPCU

R337 330_4R337 330_4

D D

BATLED0#(30)
BATLED1#(30)

WIRELESS_LED(27)

1/27 add LID SW in MB

-PWRLED PWRLED#

PWRLED#

POWER/B

1

2

SW3

1
3

NTC031-AA1G-A160T

NTC031-AA1G-A160T

2 1

3VPCU

CN10

CN10

1
2
3
4
5
6
7
8

LED B TO B(85204-0800L)

LED B TO B(85204-0800L)

2
4
65

LED1

LED1

LED_B_LTST-C190TBKT

LED_B_LTST-C190TBKT

3VPCU

C477

C477

0.1U_4

0.1U_4

LE4 B:

3

3VSUS

LE4 B:

CN5

CN5

1
2
3
4
5

FINGER PRINTER(EIC 3703-05)

FINGER PRINTER(EIC 3703-05)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

USB BT FP TP PB BD FAN

USB BT FP TP PB BD FAN

USB BT FP TP PB BD FAN

8

1A

1A

of

of

of

31 42Tuesday, March 14, 2006

31 42Tuesday, March 14, 2006

31 42Tuesday, March 14, 2006

1A

1
4

LE4 B:

1
4

MY5(26,30)
MX1(26,30)

USBP6-(13)

USBP6+(13)

R574 FS@0_6R574 FS@0_6
R575 FS@0_6R575 FS@0_6

R202 H@0_6R202 H@0_6
R203 H@0_6R203 H@0_6

2

2

3

3

L30

*DLW21HN900SQ2L

*DLW21HN900SQ2L

L30

for FP switch

BUSBP1­BUSBP1+

C385

C385
*22P_4

*22P_4

C384

C384
*22P_4

*22P_4

Finger Printer

4

5

6

1

2

3

4

5

6

7

8

Add L74

C417

C417

LE4 B:

Add L73

BLM18PG181SN1_6

BLM18PG181SN1_6

12
12

BLM18PG121SN_6

BLM18PG121SN_6
BLM18PG181SN1_6

BLM18PG181SN1_6

12
12

BLM18PG121SN_6

BLM18PG121SN_6

+3VHDD

C414

C414

4.7U_10V_8

4.7U_10V_8

SATA_RXP0_C (12)
SATA_RXN0_C (12)

SATA_TXN0 (12)
SATA_TXP0 (12)

Near To SATA connector

+5VRUN

+3VRUN

+3VHDD

C606

C606
150U/6.3V_7

150U/6.3V_7

C593

C593
150U/6.3V_7

150U/6.3V_7

+5VRUN+5VHDD

C460

C460
150U/6.3V_7

150U/6.3V_7

PDD[0..15]

PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ
PDDACK#

R276

R276

1 2

*5.6K_4

*5.6K_4

PDD[0..15] (12)
PDCS1# (12)

PDCS3# (12)
PDA0 (12)
PDA1 (12)
PDA2 (12)
PDIOR# (12)
PDIOW# (12)
PIORDY (12)
IRQ14 (12)
PDDREQ (12)
PDDACK# (12)

PDDREQ

32

1.5A

SATA HDD

CN19

CN19

22

26

21

A A

B B

25

20

24

19

23

18
17
16
15
14
13
12
11
10

9
8

7
6
5
4

SATA

SATA

3
2
1

ALLTOP-C16647-122A4-L

ALLTOP-C16647-122A4-L

SATA_RXP0
SATA_RXN0

SATA_TXN0
SATA_TXP0

+5VHDD

+3VHDD

+5VHDD

+3VHDD

C454 3900P_4C454 3900P_4
C453 3900P_4C453 3900P_4

L37

L37
L73

L73

L33

L33
L74

L74

LE4 B:

0.1U/10V_4

0.1U/10V_4

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

51
52

LE4 A:

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14

PDD15
PDDREQ
PDIOR#

PDDACK#
PDIAG#

PDA2

PDCS3#

C472

C472

0.1U/10V_4

0.1U/10V_4

PLTRST#(13,14,18,26,27)

footprint

R328 *10K_4R328 *10K_4

C470

C470
1000P_4

1000P_4

C471

C471
1000P_4

1000P_4

R307 0_4R307 0_4

LE4 C:

Del R328 in BOM

+5VODD

C463

C463
150U/6.3V_7

150U/6.3V_7

+5VODD

+3VRUN +5VRUN

2

1 3

Q22

Q22

DTC144EU

DTC144EU

R301

R301
10K_4

10K_4

-IDERST

LE4 A:

Place near POWER source

Place near SATA connector

ODD

C C

CDLED#(31)

+5VODD

D D

-IDERST

CDLED#

+5VODD

R327

R327
*10K_4

*10K_4

LE4 B:

Add parts in BOM

set to MasterR335

PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

PDIOW#
PIORDY
IRQ14
PDA1
PDA0
PDCS1#

RCSEL

1 2

R335

R335
470_4

470_4

LE4 B:

CN24 change back to LE2

CN24

CN24

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

ALLTOP-C1242B-150B1

ALLTOP-C1242B-150B1

DFHD50MRA75

+5VODD +5VRUN

L38 BLM18PG121SN_6L38 BLM18PG121SN_6
L72 BLM18PG121SN_6L72 BLM18PG121SN_6

2.0A

1

2

3

4

12
12

LE4 B:

Add L72

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

6

Date: Sheet

7

SATA HDD & PATA ODD

SATA HDD & PATA ODD

SATA HDD & PATA ODD

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

32 42Tuesday, March 14, 2006

32 42Tuesday, March 14, 2006

32 42Tuesday, March 14, 2006

of

of

of

8

1A

1A

1A

5

Digitally signed by
fdsf
DN: cn=fdsf,
o=fsdfsd, ou=ffsdf,
email=fdfsd@fsdff,
c=US
Date: 2010.02.13
13:19:59 +07'00'

FOR 10/100
FOR GIGA

C668

C686

C706

C706
10U/10V_8

10U/10V_8

D D

C686

0.1U_4

0.1U_4

C672

C672

0.1U_4

0.1U_4

Voltage Rail
VDDIO_PCI 3V_S5 +3V

C668

0.1U_4

0.1U_4

57024401

5705M
+3V

+3V_S5

+3VRUN

C696

C696

0.01U/16V_4

0.01U/16V_4

AD[31..0](13,24)

2.5V3.3V 2.5V+3V_2.5V_LAN

1.2V1.8V 1.2V+1.8V_1.2V_LAN

C C

C/BE0#(13,24)
C/BE1#(13,24)
C/BE2#(13,24)

C/BE3#(13,24)

+3V_S5
REQ1#(13)
GNT1#(13)

FRAME#(13,24)

IRDY#(13,24)

DEVSEL#(13,24)

STOP#(13,24)

TRDY#(13,24)

PAR(13,24)
PERR#(13,24)
SERR#(13,24)

INTB#(13)

LE4 C:

Select enable
or disable
LAN function

PCIRST#(13,24,25)

PCLK_LAN(3)

LAN_PME#(30)

PCI_PME#(13,24)

4401,5788 support CLKRUN

CLKRUN#(14,24,26,27,30)
PCLK_SMB(3,14)

B B

A A

4401 and 5788M don't
support SMBus

+3V_2.5V_LAN

+1.8V_1.2V_LAN

PDAT_SMB(3,14)

C685

C685

0.1U_4

0.1U_4

L67

L67

BK1608HS330_6

BK1608HS330_6

C670

C670

0.1U_4

0.1U_4

C694

C694

0.01U/16V_4

0.01U/16V_4

10mils

R321 4.7K_4R321 4.7K_4

AD23

R523 0_4R523 0_4
R522 0_4R522 0_4

R525 0_4R525 0_4
R520 *0_4R520 *0_4
R521 *0_4R521 *0_4
R322 5@4.7K_4R322 5@4.7K_4

C466 27P_4C466 27P_4

C465 27P_4C465 27P_4

LAN_PLLVDD2

C682

C682

0.1U_4

0.1U_4

R562 4@0_8R562 4@0_8
R563 5@0_8R563 5@0_8

C660

C660

0.01U/16V_4

0.01U/16V_4

AD[31..0]

C683

C683

4.7U/6.3V_8

4.7U/6.3V_8

C680

C680

0.01U/16V_4

0.01U/16V_4

CLK_LAN_X1

BG625000737

1 2

CLK_LAN_X2

T264T264

LAN_PME#

Y6
25MHZY625MHZ

VDDIO_LAN

C654

C654

0.01U/16V_4

0.01U/16V_4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

J12

A10
M11

J14
N11
N10

R319

R319
200_6

200_6

H14

M7

M5

M1
M2
M3

M4

M9

N7
P6

P5
N5

P4
N4
P3
N3
N2

L1

L2
K1
E3
D1
D2
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
A8
B8

L3
F3
C4

C3

J3
F2
F1
H3
H1
G3

J1

J2
A2
H2
C2
A3
A4
A6

C8
H4

C9

F4

P7

L8
N8

4

+1.8V_1.2V_LAN

E12

H6

P2

VDDCH7VDDCH8VDDCJ5VDDCJ6VDDCJ7VDDCJ8VDDCJ9VDDC

VDDC

VDDCH5VDDC

VDDIO_PCIA7VDDIO_PCIB3VDDIO_PCIC5VDDIO_PCIE1VDDIO_PCIE4VDDIO_PCIG1VDDIO_PCIK3VDDIO_PCIL4VDDIO_PCIN6VDDIO_PCI

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE_0#
CBE_1#
CBE_2#
CBE_3#

VAUXPRSNT
REQ#
GNT#
FRAME#
IRDY#
DEVSEL#
STOP#
TRDY#
PAR
PERR#
SERR#
INTA#
PCI_RST#
PCI_CLK
IDSEL
PME#

CSTSCHG
CLKRUN#
SMB_CLK
SMB_DATA
LOW_PWR

M66EN

XTALVDD
XTALI
XTALO

NC/PLLVDD3
PLLVDD2

NC
NC
NC

VSSB7VSSD4VSSD5VSSD6VSSD7VSSD8NC/VSSD9VSSE2VSSE5VSSE6VSSE7VSSE8VSSE9VSSF5VSSF6VSSF7VSSF8VSSF9VSS

@BCM4401/5788

@BCM4401/5788

15mm x 15mm

15mm x 15mm

BGA196

BGA196

J10

VSSG4VSSG5VSSG6VSSG7VSSG8VSSG9VSS

F10

K10

L10

M14

N14

VDDCK5VDDCK6VDDCK7VDDCK8VDDCK9VDDC

LINK_LED100#/SPD100LEDB

VDDCL5VDDC

VDDC

VDDC

VDDCP8VDDC

BIASVDD

VDDIO
VDDIO
VDDIO
VDDIO

VESD1
VESD2
VESD3

NC/VDDP
NC/VDDP

NC/AVDD
NC/AVDD

EPHY_AVDD/AVDDL
EPHY_AVDD/AVDDL

NC/TRD[3]-

NC/TRD[3]+

NC/TRD[2]-

NC/TRD[2]+

RDN/TRD[1]-

RDP/TRD[1]+

TDN/TRD[0]-

TDP/TRD[0]+

LINK_LED10#/LINKLEDB

COL_LED#/SPD1000LEDB

ACT_LED#/TRAFFICLEDB

GPIO0
GPIO1
GPIO2

SPROM_CLK/EECLK

SPROM_CS/EEDATA

SPROMDOUT/NC

SPROMDIN/NC

TRST#

REGIN33/REGSUP25

NC/REGCTL25

OUT33/REGSEN25

NC/REGSUP12

NC/REGCTL12

REGOUT18/REGSEN12

VSS/NC
VSS/NC

EECLK_PXE/SCLK

VSSH9VSSK2VSSL6VSSL9VSS

G10

NC/CS#

EEDATA_PXE/SI

NC/SO

ND/VSS

VSSN1VSS

VSS

M6

M12

M13

3

P12

P13

P14

U26

U26

VDDC

VDDC

A14
A11
F11
K12
L12

P1
G2
A1

K14
L13
P11

VDDP

A13
F14

F12
F13

E14
E13

D14
D13

C14
C13

B14
B13

G13
H13
G12
G14

D10

RDAC

H12
K13
J13

M10
P10

N9
P9

D11
D12

TDI

C12

TCK

A12

TMS

B12

TDO

B11
C11
C10

B9
B10
A9
L7

NC

K11

NC

K4

NC

J11

NC

J4

NC

H10

NC

M8

NC

L14
L11

H11
E11
E10
G11

VSS

BCM4401 is for 10/100(1.8)

N12

N13

BCM5702 is for giga
BCM5705M is for giga cost-down(12)

10mils

BIASVDD

C651

+3V_S5

+3V_S5

+3V_2.5V_LAN

LAN_AVDDL

10MBPS#

-100MBPS
1GBPS#

ACT#
LAN_RDAC

EEWP#

EECLK
EEDATA

BCM_DI
BCM_DO

BCM_TRST#

1

1

1.5" AWAY FROM CHIP

Use Philips BCP69-16, hfe=75~275

C651
1000P_4

1000P_4

LAN_AVDD

C652

C652

0.1U_4

0.1U_4

R538 0_4R538 0_4

R320 1K_4R320 1K_4

R323 5@1K_4R323 5@1K_4
R324 5@1K_4R324 5@1K_4

R518 1K_4R518 1K_4

Q18

Q18

3

5@BCP69T1

5@BCP69T1

E

4

C

C

2

Q19

Q19

3

5@BCP69T1

5@BCP69T1

E

4

C

C

2

1G

1G

B

B

L64

L64

PBY201209T-300Y-S_8

PBY201209T-300Y-S_8

+3V_2.5V_LAN

L65

L65

BK1608HS330_6

BK1608HS330_6

ALWAYS USE -100MBPS

+3V_S5

C633

C633
10U/10V_8

10U/10V_8

40mils

C634

C634
10U/10V_8

10U/10V_8

40mils

C635

C635
10U/10V_8

10U/10V_8

+3V_2.5V_LAN

C671 5@0.1U_4C671 5@0.1U_4

5@49.9/F_4

5@49.9/F_4

100MBPS# (34)
ACT# (34)

C625

C625

0.01U/16V_4

0.01U/16V_4

+3V_S5

C697

C697
5@0.1U_4

5@0.1U_4

+3V_S5

40mils

R519

R519

2.5V@88mA 0.564W

C626

C626

0.01U/16V_4

0.01U/16V_4

C620

C620

0.01U/16V_4

0.01U/16V_4

1.2V@618mA 0.803W

C621

C621

0.01U_4

0.01U_4

C619

C619

0.01U_4

0.01U_4

2

C665 5@0.1U_4C665 5@0.1U_4

R533

R537

R537

R534

R534

5@49.9/F_4

5@49.9/F_4

R533

5@49.9/F_4

5@49.9/F_4

1.27Kohm+-1% for 4401

1.24Kohm+-1% for 5788M

5@1.24K/F_4/4@1.27K/F_4

5@1.24K/F_4/4@1.27K/F_4

U29

U29

EEWP#
EECLK
EEDATA

+3V_2.5V_LAN

C618

C618

0.01U/16V_4

0.01U/16V_4

+1.8V_1.2V_LAN

C627

C627

0.01U_4

0.01U_4

8
7
6
5

VCC
WP#
SCL
SDA

5@24C128

5@24C128

GND

A0
A1
A3

R531

R531
5@49.9/F_4

5@49.9/F_4

1
2
3
4

C662 0.1U_4C662 0.1U_4

R530

R530

49.9/F_4

49.9/F_4

LAN_AVDDL

EEDATA
EECLK
BCM_DI
BCM_DO

R529

R529

49.9/F_4

49.9/F_4

1

C659 0.1U_4C659 0.1U_4

R527

R527

49.9/F_4

49.9/F_4

L66

L66

C673

C673

BK1608HS330_6

BK1608HS330_6

0.1U_4

0.1U_4

1
2
3
4

R526

R526

49.9/F_4

49.9/F_4

TX3N
TX3P

TX2N
TX2P

TX1N
TX1P

TX0N
TX0P

U28

U28

CS
SK
DI
DO

4@93LC46

4@93LC46

33

+1.8V_1.2V_LAN

8

VCC

7

NC

6

ORG

5

GND

TX3N (34)
TX3P (34)

TX2N (34)
TX2P (34)

TX1N (34)
TX1P (34)

TX0N (34)
TX0P (34)

+3V_S5

4@0.1U_4

4@0.1U_4

C679

C679

R524

PCLK_LAN

R524

*22_4

*22_4

+3V_2.5V_LAN

C666

C691

C704

C655

C655

*10P_4

*10P_4

5

4

C704
10U/10V_8

10U/10V_8

C691

0.1U_4

0.1U_4

C666

0.1U_4

0.1U_4

+1.8V_1.2V_LAN

C701

C701

0.1U_4

0.1U_4

C705

C705
10U/10V_8

10U/10V_8

3

C695

C695

0.1U_4

0.1U_4

C700

C700

0.1U_4

0.1U_4

C699

C699

0.1U_4

0.1U_4

C677

C677

0.01U/16V_4

0.01U/16V_4

C676

C676

0.01U/16V_4

0.01U/16V_4

C678

C678

0.01U/16V_4

0.01U/16V_4

2

C653

C653

0.01U/16V_4

0.01U/16V_4

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

BCM4401/5705M LAN

BCM4401/5705M LAN

BCM4401/5705M LAN

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

33 42Tuesday, March 14, 2006

33 42Tuesday, March 14, 2006

33 42Tuesday, March 14, 2006

of

of

1

of

A

A

A

5

4

3

2

1

34

D D

B:Change LED define

ACT#(33)

+3V_S5

B:Change 10/100 LAN transform U23 to ST1284A(DB0MW1LAN09)

+3V_2.5V_LAN

U43

+3V_2.5V_LAN

TX0P(33)
TX0N(33)

TX1P(33)
TX1N(33)

TX2P(33)

C C

TX2N(33)

TX3P(33)
TX3N(33)

TX0P
TX0N

+3V_2.5V_LAN
TX1P
TX1N

+3V_2.5V_LAN
TX2P
TX2N

+3V_2.5V_LAN
TX3P
TX3N

GST5009 for giga lan/TST1284 for 1/100

GST5009 for giga lan/TST1284 for 1/100

10/100 DB0MW1LAN09

U43

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

MCT1
MX1+

MX1-

MCT2
MX2+

MX2-

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

24
23
22

21
20
19

18
17
16

15
14
13

R341

R341

R339

R339

R326

R326

X-TX0P
X-TX0N

X-TX1P
X-TX1N

X-TX2P
X-TX2N

X-TX3P
X-TX3N

R325

R325

100MBPS#(33)

+3V_S5

R318 220_F_4R318 220_F_4

X-TX0P
X-TX0N
X-TX1P
X-TX2P
X-TX2N
X-TX1N
X-TX3P
X-TX3N

R336 220_F_4R336 220_F_4

10

12
11

CN23

CN23

10

9

9

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8
12

11

RJ45

RJ45

G3
G4

G1
G2

15
16

13
14

1G DBKN1NLAN03

75/F_4

75/F_4

75/F_4

75/F_4

5@75/F_4

5@75/F_4

5@75/F_4

5@75/F_4

C467

C467
1500P/2KV_18

1500P/2KV_18

C464

C464

5@0.1U_4

5@0.1U_4

+3V_2.5V_LAN

C469

C469

C474

C474

5@.1U_4

5@.1U_4

0.1U_4

0.1U_4

C476

C476

0.1U_4

0.1U_4

B B

A A

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DVO CH7011A & RJ45-11 CON

DVO CH7011A & RJ45-11 CON

DVO CH7011A & RJ45-11 CON

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

34 42Tuesday, March 14, 2006

34 42Tuesday, March 14, 2006

1

34 42Tuesday, March 14, 2006

A

A

A

5

LE4 B:

HI0805R800R-10

PJ1

PJ1

2DC-S726B201

D D

2DC-S726B201

1
2
3
4

PJ1.1

PC168

PC168

0.1U_50V_6

0.1U_50V_6

HI0805R800R-10

12

PC169

PC169
1000P_X7_6

1000P_X7_6

add PL27 change PL18 same as PL27

PL27

PL27

HI0805R800R-10

HI0805R800R-10

PL18

PL18

PC171

PC171

0.1U_50V_6

0.1U_50V_6

LE4 B:

del PL4

LE4 B:

change size 0805
to 0603

LE4 C:

VA-1

LE4 B:

del PR80

PR81

PR81
75K_6

75K_6

LE4 A:

VA2

12

CC-SET_R

PR180

PR180
100K_F_6

100K_F_6

PR181

PR181
20K_6

20K_6

MBATV

PC176

PC176

0.01U_25V_4

0.01U_25V_4

PR82

PR82
10K_F_6

10K_F_6

PR84

PR84
0_6

PQ40

PQ40

DTA124EU

C C

ACOK

PR96

PR96
10K_F_6

10K_F_6

DTA124EU

2

8724LDO

13

8724_3D3_LDO

0_6

CC-SET(30)

ACIN(30)

PR95

PR95
15K_6

15K_6

3

PQ39

PQ39

2N7002K

2N7002K

B B

2

PD9

PD9

SW1010C

SW1010C

1

PR93

PR93
1M_F_6

1M_F_6

2 1

4A

V_CHG

PF1

PF1

TR2/6125FA10A

TR2/6125FA10A

1 2

PC91

PC91

1 2

1U_X7_8

1U_X7_8

3VPCU

PL8

PL8

HI0805R800R-10

HI0805R800R-10

PL7

PL7

HI0805R800R-10

HI0805R800R-10

ACOK#

8724_3D3_LDO

PR179

PR179

*0_6

*0_6

LE4 C:

PR195 100K_4PR195 100K_4

PR202

PR202
*0_6

*0_6

PR193

PR193
14K_F_4

14K_F_4

3VPCU

PR196

PR196
330_4

330_4

MBCLK(5,30)

MBDATA(5,30)

PD22

A A

PD22
ZD5.6V

ZD5.6V

2 1

2 1

PR197

PR197
330_4

330_4

10K_F_4

10K_F_4

PD21

PD21
ZD5.6V

ZD5.6V

PR194

PR194

TEMP_MBAT(30)

PC177

PC177

0.1U_10V_410V

0.1U_10V_410V

LE4 C:

5

LE4 C:

PC78

PC78

0.01U_50V_6

0.01U_50V_6

PC82

PC82

1000P_X7_6

1000P_X7_6

PR83

PR83
1K_6

1K_6

PC77

PC77

0.1U_50V_6

0.1U_50V_6

456
3

7
2
1

4

VA-1

PD17

PD17
SSM24PT

SSM24PT

2 1

2 1

PD18

PD18
SSM24PT

SSM24PT

LE4 C:

VA-1

21

PD16

PD16
RB500

RB500

PC172

PC172
1U_X7_8

1U_X7_8

1 2

PC80

PC80

1000P_X7_6

1000P_X7_6

12

PC81

PC81

0.01U_50V_6

0.01U_50V_6

PJ2

PJ2

SUYIN_200275MR005G118ZL

SUYIN_200275MR005G118ZL

4

PC79

PC79

0.1U_50V_6

0.1U_50V_6

12

MBATV (30)

12

12

PC83

PC83

0.01U_50V_6

0.01U_50V_6

VA

PC173

PC173

+

+

10U_25V_1206

10U_25V_1206

ACOK#

PR183

PR183

0.01

0.01

1 2

1P

1

DCIN

10

ACIN

15

VCTL

13

ICTL

12

REFIN

11

ACOK

9

ICHG

28

IINP

8

SHDN

7

CCV

6

CCI

5

CCS

GND

29

2P

27

26

CELLS

CSSP

CSSN

DLOV

PGND

CSIP
CSIN

BATT

GND

14

PU5

PU5
MAX8724

MAX8724

LDO

BST

DHI

DLO

REF

CLS

R3

17
2
22
24

25
23

LX

21
20
19

18

V_CHG

16
4

3

Iinput =(V CLS / V REF)*(0.075/ RS1)
ICHG =(V ICTL / V REFIN)*(0.075/ RS2)

8724_3D3_LDO

8724LDO

12

8724DLOV

8724BST

8724DH
8724LX
8724DL

PR85

PR85
20K_6

20K_6

R1

PR89

PR89

13.3K_F_6

13.3K_F_6

R2

3

VA2

PC88

PC88
10U_25V_1206

10U_25V_1206

PR86

PR86
100K_F_6

100K_F_6

8724_3D3_LDO

PR88 825_F_6PR88 825_F_6

PR90

PR90

33_6

33_6

PC85

PC85
1U_10V_X5_6

1U_10V_X5_6

PR91

PR91

0_6

0_6

12

PC84

PC84
1U_10V_X5_6

1U_10V_X5_6

3

+

+

PC89

PC89

0.1U_50V_6

0.1U_50V_6

PR87 100K_F_6PR87 100K_F_6

PR182

PR182

1.33K_F_6

1.33K_F_6

21

PD8

PD8
SW1010C

SW1010C

12

0.1U_50V_6

0.1U_50V_6

CSIP
CSIN

PC87

PC87

12

12

PC86

PC86
1U_10V_X5_6

1U_10V_X5_6

PL5

PL5

FBJ3216HS800-T

FBJ3216HS800-T

3

2

1

D1

D1

1

D1 S1/D2

D1 S1/D2

2

G2

G2

3

S2

S2

4

PQ37 SI4914DY-T1-E3

PQ37 SI4914DY-T1-E3

PD20

PD20

SW1010

SW1010

VA2

VIN

PC170

PC170
1U_X7_8

1U_X7_8

1 2

CELL-SET
0 = 4 CELL
1 = 3 CELL

CELL_SET

PQ35

PQ35
2N7002K

2N7002K

G1

G1

8
7
6
5

3VPCU(12,14,15,22,26,30,31,39,40)

VIN(22,36,37,38,39,41)

3VPCU

2 1

P331

2

300mil

PQ55

PQ55
DTA124EU

DTA124EU

1 3

LE4 C:

2

1 2

PC167

PC167

0.1U_50V_6

0.1U_50V_6

CELL_SET (30)

LE4 B:

change c from

0.015ohm to 0.01ohm

PR97

PR97

0.01

2

PQ62

PQ62
2N7002K

2N7002K

2

0.01

1 2

5VPCU

1
3

PL6

PL6

8724LXR

10uH 30% 4.4A(SIL104R-100PF)L-F

10uH 30% 4.4A(SIL104R-100PF)L-F

5VPCU(12,15,36,38,39,40)

3VPCU

VIN

PR187

PR187
475K_F_6

475K_F_6

PR188

PR188
332K_F_4

332K_F_4

3

1

1

35

PR192

PR192

10K_F_6

10K_F_6

321

PQ56

PQ56

SI4425BDY-T1-E3

SI4425BDY-T1-E3

876

5 4

VIN

12

PC90

PC90

0.1U_50V_6

0.1U_50V_6

321

PQ38

PQ38

SI4425BDY-T1-E3

SI4425BDY-T1-E3

876

5 4

V_CHG

V_CHG

1P

2P

12

PC92

PC92

0.1U_50V_6

0.1U_50V_6

+

+

PC94

PC94
10U_25V_1206

10U_25V_1206

VAD-5

2

PD19

PD19
RB500

RB500

2

PQ58

PQ58
2N7002K

2N7002K

3

1

D/C#

PR191

PR191
100K_F_6

100K_F_6

ACOK

3VPCU

21

ACOK-2

P332

PR189

PR189
100K_F_6

100K_F_6

3

1

PR190

PR190
100K_F_6

100K_F_6

5

+

+

4

-

-

PU9

PU9
LMV331

LMV331

2

BL/C# (30)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Charger --MAX8724

Charger --MAX8724

Charger --MAX8724

Date: Sheet

Date: Sheet

Date: Sheet

PQ61

PQ61
2N7002K

2N7002K

PR94

PR94
200K_F_6

200K_F_6

PR186

PR186
100K_F_6

100K_F_6

+

+

PC93

PC93
10U_25V_1206

10U_25V_1206

D/C# (30)

PROJECT : LE4

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

35 42Tuesday, March 14, 2006

35 42Tuesday, March 14, 2006

35 42Tuesday, March 14, 2006

of

of

1

of

1A

1A

1A

A

B

C

D

E

36

1 1

5VPCU

LE4 B:

Cancel power plane
with 5VSUS

LE4 B:

Change
open-short to
bead

VIN

2 2

LE4 B:

Change
open-short to
Res.

Current limit at 11.6A

1.8VSUS

3 3

LE4 C:

Cancel PR198

PC137

PC137

0.1U_50V_6

0.1U_50V_6

PL19

PL19

HI0805R800R-10

HI0805R800R-10

LE4 B:

Add PC138 in BOM

+

+

PC139

PC139

470U/2.5V/12m

470U/2.5V/12m

PC127

PC127

10U_25V_1206

10U_25V_1206

1.8V_P

+

PC138

+

PC138
220U/4V25m

220U/4V25m

8632VDD

+DDR_PWR_SRC

PC124

PC124

PC132

PC132

2200P_5X7_4

10U_25V_1206

10U_25V_1206

2200P_5X7_4

RDS(ON)=13m ohm

1.5uH_SIQH125_1R5_13A/6mohm

1.5uH_SIQH125_1R5_13A/6mohm

12

PR143

PR143

*100K/F_4

*100K/F_4

PR144

PR144

1 2

0_4

0_4

12

PR145

PR145
*63.4KF_6

*63.4KF_6

PL13

PL13

LE4 B:

Change
footprint

PC134

PC134

0.1U_50V_6

0.1U_50V_6

12

9

52

3
876

2

351

1

RDS(ON)=5m ohm

PQ49

PQ49

RQW130N03

RQW130N03

4

PQ50

PQ50

FDS7088SN3

FDS7088SN3

4

Freq=300K

+1.8V

PR7

PR7

1 2

*E@0_4

*E@0_4

1.8VSUS

PQ6

PQ6
E@RSS090N03

E@RSS090N03

8
7

5

4

PC5

PC5
E@0.047u_50V_6

E@0.047u_50V_6

2

+5VRUN

PR206

PR206
E@100K_4

E@100K_4

3

1

PR207 E@0_4PR207 E@0_4

MAIND(40)

PQ63

PQ63
E@2N7002K

E@2N7002K

1.8VSUS(7,9,16,40,41)

1 2

LE4 A:

+15V

PR205

PR205
E@1M_F_6

E@1M_F_6

MAINON

4 4

2

PQ64

PQ64

E@DTC144EUA

E@DTC144EUA

1 3

PC182

PC182
*E@1U_6.3V_6

*E@1U_6.3V_6

+1.8VRUN

1
2
36

12

PC4

PC4

E@10U_25V_1206

E@10U_25V_1206

+

+

PC2

PC2

E@470U/2.5V/12m

E@470U/2.5V/12m

+

PC3

+

PC3
E@470U/2.5V/12m

E@470U/2.5V/12m

LE4 B:

Solve Power timing issue so del PC5

+1.8VRUN (19,20,21,40)

del PR132

PR131

PR131
0_6

0_6

PC122

PC122

0.1U_50V_6

0.1U_50V_6

21

4.7U_1X7_8

4.7U_1X7_8

PD13

PD13
CH501

CH501

1.8V_BST

PR139 *0_4PR139 *0_4

1 2

MAX8632ETI+

MAX8632ETI+

1.8V_DH

8632REF

PR141

PR141

100K_F_4

100K_F_4

PC123

PC123

0.22U_25V_6

0.22U_25V_6

LE4 B:

Modify value from 110K/F to

43.2K/F

PU8

PU8

PR138

PR138

0_6

0_6

1.8V_LX

1.8_DL

8632VDD

PC121

PC121

20

18

19

21

23
16
15

12

1.8V_LIM

12

PR140

PR140

43.2K/F_4

43.2K/F_4

PR135

PR135

*0_4

*0_4

22

VDD

BST

DH

LX

DL

PGND1
OUT
FB

1

TON

3

REF

ILIM

4

PR129 *0_4PR129 *0_4

1 2

PR133 10_6PR133 10_6

12

12

PR136

PR136
0_4

0_4

1 2
2

OVP/UVP

TP0

SKIP

25

28

12

PR130

PR130
0_4

0_4

8632VDD

26

VIN

AVDD

POK1
POK2

SHDN

STBY

VTTI

REFIN

PGND2

VTT

VTTS
VTTR

GND

8

24

GND_DDR

SS

SUSON

PC120

PC120
1U_10V_X5_6

1U_10V_X5_6

+DDR_PWR_SRC

17
5
6
27

PR142

PR142

1 2

7

0_4

0_4

13
14

11

12
9

10

PC125

PC125
1000P_X7_4

1000P_X7_4

PR134 0_6PR134 0_6

PR146

PR146

1 2

PC129

PC129

0.1U_50V_6

0.1U_50V_6

0.9V_P

PC126

PC126
1U_10V_X5_6

1U_10V_X5_6

+3VRUN

12

PR8

PR8
100K_F_4

100K_F_4

HWPG (30,37,38,39,41)

PR137

PR137

1 2

0_4

0_4

MAINON

1.8V_P

20_/F_4

20_/F_4

V_DDR_MCH_REF

LE4 B:

Add circuit to MCH

LE4 A-power:

SUSON

MAINON (30,38,40,41)

PC130

PC130

0.1U_50V_6

0.1U_50V_6

PC131

PC131

0.1U_50V_6

0.1U_50V_6

SUSON (30,40)

PC133

PC133

10U_6.3V_8

10U_6.3V_8

PC136

PC136
10U_6.3V_8

10U_6.3V_8

LE4 B:

Change
open-short to
bead

LE4 C:

Cancel PL20

Design current 1.05A
Peak current 1.5A

PC135

PC135
10U_6.3V_8

10U_6.3V_8

0.9 Volt +/-5%

SMDDR_VTERM

PC128

PC128

*10U_6.3V_8

*10U_6.3V_8

1.8VSUS

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR2 (MAX8632)

DDR2 (MAX8632)

DDR2 (MAX8632)

Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

36 42Tuesday, March 14, 2006

36 42Tuesday, March 14, 2006

36 42Tuesday, March 14, 2006

of

of

E

of

1A

1A

1A

1

2

3

4

5

PR79

PR79

1 2

1K_F_4

1K_F_4

T272T272

VRON(30)

HWPG(30,36,38,39,41)

LE4 B:

CLK_EN#

PQ34

PQ34
2N7002K

2N7002K

PC76

PC76

0.1U_4

0.1U_4

CLKEN

PR62 *0_6PR62 *0_6

DELAY_VR_PWRGOOD(7,14)

PR173 100K_F_4PR173 100K_F_4

PR172 0_4PR172 0_4

1 2

LE4 A:

Add layout note on pins 22 and 28 of MAX8771
controller. These nets have large voltage swings.
Need to route them away from the sensitive areas that
are trying to detect small changes in voltage, such as
the voltage sense VccSense VssSense lines.

3

2

1

1 2

CLK_EN#(3,14)

1 2

LE4 B:

Change nename

PR78

PR78

1 2

H_VID0(5)
H_VID1(5)
H_VID2(5)
H_VID3(5)
H_VID4(5)
H_VID5(5)
H_VID6(5)

PC161

PC161
100P_50V_4

100P_50V_4

8771VCC

PH_PROCHOT#(4)

*0_4

*0_4

0_6

0_6

12

PR38

PR38
10K_F_4

10K_F_4

ICH_DPRSTP#(4,12)

PM_DPRSLPVR(14)

*NTC 10K_6-B4.25K_6

*NTC 10K_6-B4.25K_6

5VSUS

PR36

PR36

12

PR39

PR39

1.91K_F_6

1.91K_F_6

PR64 0_4PR64 0_4
PR63 0_4PR63 0_4
PR58 0_4PR58 0_4
PR54 0_4PR54 0_4
PR49 0_4PR49 0_4
PR47 0_4PR47 0_4
PR45 0_4PR45 0_4

PSI#(4)

PR168 10K_F_4PR168 10K_F_4

1 2

5VSUS

12

PR171

PR171
10K_F_4

10K_F_4

CLKEN

1 2
1 2
1 2
1 2
1 2
1 2
1 2

PR40 0_4PR40 0_4

1 2

PR37 0_4PR37 0_4

1 2

PR44 0_4PR44 0_4

PC49 470P_X7_4PC49 470P_X7_4

PR42 71.5K_F_4PR42 71.5K_F_4

PC59 0.22U_10V_6PC59 0.22U_10V_6

PR169

PR169

PR41

PR41
56_4

56_4

12

8771REF

PR167

PR167
10K_F_4

10K_F_4

1 2

PC159

PC159

0.1U_10V_4

0.1U_10V_4

8771VCC

PC63

PC63

2.2U_10V_X5_6

2.2U_10V_X5_6

17

PHASEGD

2

PWRGD

1

CLKEN

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

3

PSI

38

SHDN

40

DPRSTP

39

DPRSLPVR

9

CCV

7

TIME

11

REF

18

GND

41

EP

6

THRM

5

VRHOT

4

POUT

12

19

PR66

PR66
10_4

10_4

VCC

PR175

PR175
0_6

0_6

5VSUS

PR33

PR33
0_6

0_6

PC68

PC68

4.7U_1X7_8

4.7U_1X7_8

+CPU_PWR_SRC

25

TON

VDD

BST1

LX1

DH1

DL1

PGND1

FB

CCI

GNDS

CSP1

CSN12

CSP2

DH2

DL2
LX2

BST2

PGND2

PU3

PU3
MAX8771

MAX8771

12

PR43

PR43
200K_F_4

200K_F_4

8
30
28
29
26
27

12

10

13
16
15
14

21
24
22
20
23

LE4 B:

change PC68

10u 25V_1206 to 4.7u_0805

8771VDD

21

PD6

PD6
SDM10K45-7-F

SDM10K45-7-F

8771BST1

12

PR70

PR70

12

0_6

0_6

8771BST1_R

8771LX1
8771DH1
8771DL1

PR165

PR165

*3.48K/F_4

*3.48K/F_4

1 2

PR164

PR164

3.48K_F_4

3.48K_F_4

PC56

PC56
470P_X7_4

470P_X7_4

8771CSP1
8771CSN12
8771CSP2

8771DH2
8771DL2
8771LX2
BST2_R

8771VDD

PR65

PR65
0_6

0_6

1 2

8771BST2

2 1

PC67

PC67

0.22U_25V_6

0.22U_25V_6

FDS7088SN3

FDS7088SN3

PC58

PC58
*1nF_50V_4

PC158

PC158
*4700P_4

*4700P_4

PR166

PR166
100_4

100_4

PC50

PC50
4700P_X7_4

4700P_X7_4

PR46

PR46

20K_4

20K_4

PD4

PD4
SDM10K45-7-F

SDM10K45-7-F

*1nF_50V_4

PR170

PR170
100_4

100_4

PC160

PC160
1000P_X7_6

1000P_X7_6

PC65

PC65

0.22U_25V_6

0.22U_25V_6

Sense lines are 18 mil wide, Z0=27.4 Ohm.
Use differential routing with 7 mil spacing.
Route external layer with solid GND reference
(no split planes).
Use 25 mil separation from any other signal.

PQ32

PQ32

4

PR48

PR48
*100_4

*100_4

VCC_CORE

8/11 change

PR53

PR53
*100_4

*100_4

LE4 B:

Enable Value

PQ20

PQ20

FDS7088SN3

FDS7088SN3

PC31

PC31
*1nF_50V_4

*1nF_50V_4

RQW130N03

RQW130N03

876

9

FDS7088SN3

FDS7088SN3

2

351

VCCSENSE (5)

8/11 change

VSSSENSE (5)

876

4

2

351

LE4 B:

Change
footprint

4

PQ33

PQ33

PQ28

PQ28

1

4

*1.5n_50V_6

*1.5n_50V_6

LE4 B:

Change
footprint

PQ29

PQ29

RQW130N03

RQW130N03

9

PQ21

PQ21

FDS7088SN3

FDS7088SN3

+CPU_PWR_SRC

52

del PC165,PC166,PC55

3

876

9

12

PR30

PR30
*0_6

*0_6

2

351

PC41

PC41

8771CSP1
8771CSN12

Use differential routing away from switch nodes
8771LX1 and 8771LX2

52

4

1

3

876

9

4

2

351

PC40

*1.5n_50V_6

*1.5n_50V_6

PC40

LE4 B:

PC53

PC53
2200P_5X7_4

2200P_5X7_4

PL17

0.45_25A_20%_ETQP4LR45XFC

0.45_25A_20%_ETQP4LR45XFC

12

8771CSP2
8771CSN12

PL17

1 2

3

4

PR176

PR176

2.1K_F_4

2.1K_F_4
PR177

PR177

1 2

4.02K_F_4

4.02K_F_4

PC163

PC163

0.22U_10V_6

0.22U_10V_6

PC57

PC57

0.1U_50V_6

0.1U_50V_6

PR28

PR28
*0_6

*0_6

Use differential routing away from switch nodes
8771LX1 and 8771LX2

PR174

PR174

NTC 10K_6-B4.25K

NTC 10K_6-B4.25K

PR56 0_4PR56 0_4

LE4 B:

del PC48

PL15

PL15

0.45_25A_20%_ETQP4LR45XFC

0.45_25A_20%_ETQP4LR45XFC

4

PR32

PR32

2.1K_F_4

2.1K_F_4
PR34

PR34

4.02K_F_4

4.02K_F_4

PC47

PC47

0.22U_10V_6

0.22U_10V_6

LE4 B:

Add PC20 in BOM

PC74

PC74

0.1U_50V_6

0.1U_50V_6

12

3

PR29

PR29

NTC 10K_6-B4.25K

NTC 10K_6-B4.25K

0_4

0_4

PR52

PR52

12

PC20

PC20
330UF_2V_7mohm_7343

330UF_2V_7mohm_7343

distribute evenly between N side and S
side, preferably on secondary side.

330UF_2V_7mohm

330UF_2V_7mohm

LE4 B:

Change
open-short to
bead

PL21

PL21

HI0805R800R-10

HI0805R800R-10

PL22

100U/25V

12

PC143

PC143
330UF_2V_7mohm

330UF_2V_7mohm

PC60

PC60
10U_25V_1206

10U_25V_1206

X6S_1206

12

PC142

PC142
330UF_2V_7mohm

330UF_2V_7mohm

12

PC157

PC157

+

+

100U/25V

+CPU_PWR_SRC

12

PC162

PC162

+

+

100U/25V

100U/25V

PC73

12

PC19

PC19

PC73
10U_25V_1206

10U_25V_1206

X6S_1206

LE4 B:

Del PC26
parts in
BOM

12

PC26

PC26
330UF_2V_7mohm

330UF_2V_7mohm

PC75

PC75
2200P_5X7_4

2200P_5X7_4

LE4 B:

Add PC20
in BOM

12

PC141

PC141

330UF_2V_7mohm_7343

330UF_2V_7mohm_7343

distribute evenly between N side and S
side, preferably on secondary side.

PL22
HI0805R800R-10

HI0805R800R-10

PC72

PC72
10U_25V_1206

10U_25V_1206

X6S_1206

VCC_CORE

PC12

PC12

0.01U_25V_4

0.01U_25V_4

PC62

PC62
10U_25V_1206

10U_25V_1206

X6S_1206

VCC_CORE

PC140

PC140

0.01U_25V_4

0.01U_25V_4

VIN

Change netname from
VR_PWRGD_CK410# to CLK_EN#

A A

VRON

B B

C C

D D

37

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU power MAX8771

CPU power MAX8771

CPU power MAX8771

Date: Sheet

Date: Sheet

1

2

3

4

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

37 42Tuesday, March 14, 2006

37 42Tuesday, March 14, 2006

37 42Tuesday, March 14, 2006

of

of

5

of

1A

1A

1A

1

2

3

4

5

38

A A

LE4 C:

5VPCU

4

V+

19

BST2

18

DH2

17

LX2

16

CS2

20

DL2

15

OUT2

14

FB2

7

PGOOD

11

ON1

12

ON2

6

SKIP

8

OVP

9

UVP

MAX8743

MAX8743

del PR162

PR178 20_4PR178 20_4

1 2

22

VCC

PU4

PU4

PR198

PR198
0_4

0_4

12

12

PR199

PR199
*0_4

*0_4

GND

23

8743_VCC

21

VDD

BST1

DH1

LX1

CS1

DL1

OUT1

FB1

REF

TON
ILIM1
ILIM2

PR203

PR203

1.05V_BST

25
26
27
28
24
1
2

10

LE4 C:

5
3
13

0_6

0_6

GND_8743

PR55

PR55
0_6

0_6

PC64

PC64

4.7U_1X7_1206

4.7U_1X7_1206

PR61 0_6PR61 0_6

1.05V_DH

1.05V_LX1.5V_RUN_P

1.05V_DL

1.05V_OUT

1.05V_FB

Setting frequency

8743_REF

PC66

PC66
1U_10V_X5_6

1U_10V_X5_6

21

1.05V_BST_1

12

12

12

PR60 *0_4PR60 *0_4

PR59 100K_F_4PR59 100K_F_4

12

PR57 61.9K_F_4PR57 61.9K_F_4

LE4 C:

PD3

PD3
SDM10K45-7-F

SDM10K45-7-F

PC61

PC61

0.1U_50V_6

0.1U_50V_6

12

PR73 100K_F_4PR73 100K_F_4

12

PR72 619K_F_4PR72 619K_F_4

PQ24

PQ24
AO4422

AO4422

876

4

2

351
876

4

PQ31

PQ31

FDS6676S

FDS6676S

2

351

LE4 B:

Change part number

LE4 C:

PC52

PC52

0.1U_50V_6

0.1U_50V_6

1.5UH_SIL104R-1R5_10A/8.1 mohm

1.5UH_SIL104R-1R5_10A/8.1 mohm

1 2

PD23

PD23

EC10QS04

EC10QS04

2 1

PL16

PL16

PC51

PC51
2200P_5X7_4

2200P_5X7_4

LE4 C:

LE4 C:

12

PR50

PR50
1K_F_4

1K_F_4

12

PR51

PR51
20K_F_4

20K_F_4

PC154

PC154
10U_25V_1206

10U_25V_1206

PC156

PC156

+

+

470U/2.5V/12m

470U/2.5V/12m

LE4 B:

Change
open-short to
bead

PL24

PL24

HI0805R800R-10

HI0805R800R-10

PC155

PC155
10U_25V_1206

10U_25V_1206

1.05V_VCCP_P

VIN

LE4 B:

Change
open-short to
Res.

LE4 C:

Cancel PR199

PC153

PC153

8.3A Current Limit

0.1U_10V_4

0.1U_10V_4

+1.05V

LE4 B:

Change
open-short to
bead

LE4 B:

Cancel power plane
with 5VSUS

VIN

B B

7.8A Current Limit

LE4 B:

Change
open-short to
Res.

+1.5V

C C

LE4 C:

Cancel PR200

LE4 B:

Add parts

+

PC178

+

PC178
220U/4V25m

220U/4V25m

PL23

PL23

HI0805R800R-10

HI0805R800R-10

PC25

PC25

0.1U_10V_4

0.1U_10V_4

12

PC30

PC30

+

+

330U_2.5V_ESR12

330U_2.5V_ESR12

PC148

PC148

0.1U_50V_6

PC146

PC146
10U_25V_1206

10U_25V_1206

3.8UH_SIL104R_6A/13mohm

3.8UH_SIL104R_6A/13mohm

12

PR75

PR75
10K_F_4

10K_F_4

12

PR74

PR74

18.7K_F_4

18.7K_F_4

0.1U_50V_6

PQ53

PQ53
AO4422

AO4422

PL14

PL14

PQ51

PQ51
AO4422

AO4422

1.5V_OUT

MAINON(30,36,40,41)

PC147

PC147
2200P_5X7_4

2200P_5X7_4

12

PD5

PD5

SDM10K45-7-F

SDM10K45-7-F

876

2

351
876

2

351

1 2

PD7 SDM10K45-7-FPD7 SDM10K45-7-F

21

1.5V_BST_R1

4

4

For RC Filter

PR76

PR76

PC70

PC70

0_4

0_4

*1nF_50V_4

*1nF_50V_4

PR68 33.2K_F_4PR68 33.2K_F_4

1 2

PR71

PR71
0_6

0_6

PC69

PC69

0.1U_50V_6

0.1U_50V_6

LE4 C:

HWPG(30,36,37,39,41)

1 2

PR77 100K_F_4PR77 100K_F_4

21

8743_VCC

12

8743_VCC

PC164

PC164
1U_10V_X5_6

1U_10V_X5_6

LE4 C:

1.5V_BST_R

1.5V_DH

1.5V_LX

1.5V_DL

1.5V_OUT_R

1.5V_FB

PC71

PC71
*1nF_50V_4

*1nF_50V_4

LE4 C:

12

PR67

PR67

12.7K_F_4

12.7K_F_4

31

PQ54

2

PQ54

RHU002N06

RHU002N06

8743_VCC

12

PR69

PR69
*0_4

*0_4

Setting OVP level

LE4 C: LE4 C:

LE4 C:

D D

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

VCCP (MAX8743)

VCCP (MAX8743)

VCCP (MAX8743)

Date: Sheet

Date: Sheet

1

2

3

4

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

38 42Tuesday, March 14, 2006

38 42Tuesday, March 14, 2006

38 42Tuesday, March 14, 2006

of

of

5

of

1A

1A

1A

A

B

C

D

E

39

LE4 B:

Change
open-short to
bead

PR31

1 1

VIN

PL25

PL25

HI0805R800R-10

HI0805R800R-10

PC34

PC34

10U_25V_1206

10U_25V_1206

PC36

PC36

0.1U_50V_6

0.1U_50V_6

7

8

Place PC81, PC82 as close as possible to

Current Limit at 6.7A

3VPCU

2 2

220U/4V/25m

220U/4V/25m

PQ27 drain and PQ26 source

LE4 B:

Change Vaule from 2.5UH
to 3.3UH

+3.3V_SUSP

+

+

PC14

PC14

PC13

PC13

0.1U_50V_6

0.1U_50V_6

IND SMD 3.3UH 30% 6.6A

IND SMD 3.3UH 30% 6.6A

12

PR153

PR153
*0_4

*0_4

12

PR152

PR152
0_4

0_4

PL2

PL2

3 6

241

7

8

3 6

241

LE4 A-power:

+DC1_PWR_SRC2

PC43

PC43

0.1U_50V_6

0.1U_50V_6

5

PQ19

PQ19
RSS090N03

RSS090N03

5

PQ16

PQ16
RSS090N03

RSS090N03

PC33

PC33

*10U_25V_1206

*10U_25V_1206

PC32

PC32
2200P_5X7_4

2200P_5X7_4

PC37

PC37

0.1U_50V_6

0.1U_50V_6

BST_3_1

PR27

PR27
0_6

0_6

BST3
DH3
LX3
DL3

FB3

ON5

3V_AL

RDS(ON)=20m ohm

5V_AL

PR23

PR23
2K_F_4

2K_F_4

1 2

PR31
47_6

47_6

PC46

PC46

1U_10V_X5_6

1U_10V_X5_6

PD2

PD2
CH501

CH501

20

V+

17

VCC

1

N.C.

28

BST3

26

DH3

27

LX3

24

DL3

22

OUT3

7

FB3

3

ON3

4

ON5

25

LDO3

PC44

PC44

4.7U_1X7_8

4.7U_1X7_8

21

SKIP

12

21

PD1

PD1
CH501

CH501

LDO5
BST5

DH5

LX5

DL5

OUT5

FB5

PRO

ILIM5
ILIM3

REF
TON

GND

PGOOD

SHDN

6

PU2

PU2
MAX8734AEEI+

MAX8734AEEI+

Place PC78, PC79 as close as possible to
PQ25 drain and PQ24 source

5V_AL8734VCC

LE4 A-power:

PC45

18
14
16
15
19
21
9

10
11

5
8
13
23
2

BST_5_1

PR22

PR22
0_6

0_6

BST5
DH5
LX5
DL5

FB5
PRO#

ILIM5
ILIM3
8734REF
TON

PC45

4.7U_1X7_8

4.7U_1X7_8

PC38

PC38

0.1U_50V_6

0.1U_50V_6

8734REF

PC144

PC144
1U_10V_X5_6

1U_10V_X5_6

PR163 0_6PR163 0_6

GND_DC/DC

0.1U_50V_6

0.1U_50V_6
PC9

PC9

3V_AL

578

578

3 6

241

3 6

241

12

PR18

PR18
*100K_F_4

*100K_F_4

+DC1_PWR_SRC1

PC8

PC8
2200P_5X7_4

2200P_5X7_4

PQ10

PQ10
RSS090N03

RSS090N03

PQ11

PQ11
RSS090N03

RSS090N03

RDS(ON)=20m ohm

HWPG (30,36,37,38,41)

LE4 B:

Change
open-short to
bead

VIN

PL26

PL26

HI0805R800R-10

HI0805R800R-10

PC7

PC7

10U_25V_1206

10U_25V_1206

LE4 B:

Change Vaule from 2.5UH
to 3.3UH

PL3

PL3

IND SMD 3.3UH 30% 6.6A(PLC-1045-3R3)L-F

IND SMD 3.3UH 30% 6.6A(PLC-1045-3R3)L-F

+5V_SUSP

12

PR160

PR160
*0_4

*0_4

12

PR156

PR156
0_4

0_4

PC16

PC16

0.1U_50V_6

0.1U_50V_6

Current Limit at 5.7A

5VPCU

+

PC10

+

PC10
220U/6.3V/ESR25

220U/6.3V/ESR25

PR21

1 2

PR21
240K_4

240K_4

PC35

PC35
*1000P_50V_4

*1000P_50V_4

PR148

PR148
0_4

0_4

12

LE4 A-power:

PR157 200K_4PR157 200K_4

3 3

+DC1_PWR_SRC2

LE4 B:

Add parts in BOM

1999_SHDN# (5)

+15V

PR162 0_4PR162 0_4

PC180

PC180

0.1U_50V_6

0.1U_50V_6

8734VCC

12

PR159

PR159
*0_4

*0_4

8734VCC

12

PR158

PR158
*0_4

*0_4

8734REF

REF=2V

12

PR147

PR147

63.4K_F_4

63.4K_F_4

12

PR151

PR151

63.4K_F_4

63.4K_F_4

ILIM5

PC145

PC145

0.1U_50V_6

0.1U_50V_6

12

PR161

PR161
100K_F_4

100K_F_4

DL3

ILIM3
PRO#
TON

12

PR155

PR155
0_4

0_4

4 4

12

PR154

PR154
0_4

0_4

12

PR150

PR150
91K_F_4

91K_F_4

12

PR149

PR149

63.4K_F_4

63.4K_F_4

add PC150.PC149

PC150

PC150

0.01U_50V_6

0.01U_50V_6

3

PD14

PD14
BAT54S

BAT54S

1

2

PC149

PC149

4.7U_1X7_8

4.7U_1X7_8

10V

Change PC149,PC152 size and Value
from 0603 to 0805 and from 0.1 and

4.7u

PC151

PC151

0.01U_50V_6

0.01U_50V_6

3

PD15

PD15
BAT54S

BAT54S

1

PC181

PC181

0.1U_50V_6

0.1U_50V_6

2

PC152

PC152

4.7U_1X7_8

4.7U_1X7_8

5VPCU

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D/D ( MAX8734)

D/D ( MAX8734)

D/D ( MAX8734)

Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

39 42Tuesday, March 14, 2006

39 42Tuesday, March 14, 2006

39 42Tuesday, March 14, 2006

of

of

E

of

1A

1A

1A

A

B

C

MAIND(36)

LE4 B:

Change Power plane

D

E

40

5VPCU

578

3 6

241

3 6

5VPCU

241

3VPCU

AO4422

AO4422
PQ13

PQ13

PQ18

PQ18
AO4422

AO4422

PC15

PC15

0.1U_10V_4

0.1U_10V_4

10V

10V

PC17

PC17

0.1U_10V_4

0.1U_10V_4

10V

10V

PC23

PC23

0.1U_10V_4

0.1U_10V_4

10V

10V

+5VRUN (4,10,15,23,26,28,29,30,31,32,36)

3A

+5VRUN

PC24

PC24

0.1U_10V_4

0.1U_10V_4

10V

10V

+3VRUN (3,5,7,9,10,12,13,14,15,16,17,18,19,20,22,23,26,27,28,30,31,32,33,36,41)

4.5A

+3VRUN

+15V

+5VRUN

+1.8VRUN

+VCC_GFX_CORE+3VRUN

+1.22V_GFX_PCIE+2_5VRUN

+15V

LE4 A:

4 4

DISCHARGE

MAINON

MAINON(30,36,38,41)

3 3

LE4 A:

S5_ON a:

LE4 B:

Cancel Circuit

2

PR26

PR26
1M_F_6

1M_F_6

PQ23

PQ23
PDTC144EU

PDTC144EU

1 3

2

MAINON

PR16

PR16
22_8

22_8

3

2N7002K

2N7002K

1

2

PQ17

PQ17

2

+15V

1 3

PR100

PR100
22_8

22_8

3

PQ44

PQ44

2N7002K

2N7002K

1

PR20

PR20
1M_F_6

1M_F_6

PQ52

PQ52

PDTC144EU

PDTC144EU

PR6

PR14

PR14
22_8

22_8

3

2

PQ15

PQ15

2N7002K

2N7002K

1

PR6
22_8

22_8

3

2

PQ5

PQ5

2N7002K

2N7002K

1

PR98

PR98
22_8

22_8

3

2

PQ42

PQ42

2N7002K

2N7002K

1

PR1

PR1
22_8

22_8

3

2

PQ2

2N7002K

2N7002K

1

PQ1

PQ1

PQ2
2N7002K

2N7002K

PR4

PR4
1M_F_6

1M_F_6

3

2

1

MAIND

PC1

PC1
*2200P_5X7_6

*2200P_5X7_6

3VPCU

+1.5V

PR92

PR92
22_8

22_8

3

2

PQ36

PQ36

2N7002K

2N7002K

1

VCC_CORE

PR13

PR13
22_8

22_8

3

2

2N7002K

2N7002K

1

PQ12

PQ12

SMDDR_VTERM

PR9

PR9
22_8

22_8

3

2

PQ7

PQ7
2N7002K

2N7002K

1

+1.05V

PR11

PR11
22_8

22_8

3

2

PQ9

PQ9
2N7002K

2N7002K

1

PR3

PR3
*1M_6

*1M_6

578

200mils

LE4 A:

S0-S5

PQ60

2

PQ60
SI3456DV

SI3456DV

6
5
2
1

3VSUS

3

PR15

PR15
22_8

22_8

3

PQ25

PQ25
2N7002K

2N7002K

1

4

PC174

PC174

0.1U_25V_6

0.1U_25V_6

3VPCU

+3V_S5

PR184

PR184
22_8

22_8

3

2

PQ59

PQ59

2N7002K

2N7002K

1

+15V +15V

PR25

PR25
1M_F_6

1M_F_6

5VSUS

PR35

PR35
22_8

22_8

PR99

PR99
10K_F_4

10K_F_4

2

+15V

31

PR5

PR5
100K_4

100K_4

PQ3

PQ3
FDS6676S

FDS6676S

LE4 A:

2

PQ41

PQ41

5VPCU

31

S5_ON b:

2 2

S5_ON(30)

S5_ON

RHU002N06

RHU002N06

LE4 B:

Modify discharge circuit
with +3V_S5

SUSON_G

3

SUSON(30,36)

1 1

LE4 C:

Change power plane from
10V to +15V

A

2

PQ22

PQ22

1 3

PDTC144EU

PDTC144EU

2

PQ30

PQ30
2N7002K

2N7002K

1

B

1.8VSUS

2

modify PQ40

+3V_S5

PC175

PC175
10U_6.3V_8

10U_6.3V_8

PR10

PR10
22_8

22_8

3

PQ8

PQ8

2N7002K

2N7002K

1

0.5A

+3V_S5 (4,14,15,30,33,34)

LE4 B:

Change Power plane

PR24

PR24
1M_F_6

1M_F_6

SUSD

3

2

PQ27

PQ27

2N7002K

2N7002K

1

PC39

PC39
*2200P_50V_6

*2200P_50V_6

C

+3VRUN
+5VRUN

PQ14

PQ14
SI3456DV

SI3456DV

3VPCU

3

HI0805R800R-00

HI0805R800R-00

HI0805R800R-00

HI0805R800R-00

65241

578

PL28

PL28

PL1

PL1

10U_6.3V_8

10U_6.3V_8

3VPCU

5VPCU

3 6

241

LE4 B:

PC29

PC29

PC21

PC21

0.1U_10V_4

0.1U_10V_4

10V

10V

5VPCU

AO4422

AO4422
PQ26

PQ26

add PL28

PR12

PR12

0_4

0_4

PC11

PC11
1U_X5_6

1U_X5_6

3VPCU (12,14,15,22,26,30,31,35,39)

3VSUS

PC22

PC22

0.1U_10V_4

0.1U_10V_4

10V

10V

PC42

PC42

0.1U_10V_4

0.1U_10V_4

10V

10V

VCNTL 2.5VA

PR19

PR19

6.34K_F_4

6.34K_F_4

12

PR17

PR17
20K_F_4

20K_F_4

1A

3VSUS (13,14,24,25,26,27,28,31)

5VPCU (12,15,35,36,38,39)

5VSUS (25,26,31,37,41)

2A

5VSUS

PC54

PC54

0.1U_10V_4

0.1U_10V_4

10V

10V

1
6

3
9

VIN
VCNTL

VREF
GND1

D

2

VOUT

AGND

17

GND

NC

NC
NC

4
5

8
7

PU1

PU1
APL5331

APL5331

+2.5VA

12

PC27

PC27
1000P_X7_6

1000P_X7_6

2.5V/ 1A

+2_5VRUN

PC18

PC18

10U_6.3V_8

10U_6.3V_8

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

PC28

PC28
10U_6.3V_8

10U_6.3V_8

Quanta Computer Inc.

Quanta Computer Inc.

Discharge Circuit

Discharge Circuit

Discharge Circuit

PROJECT : LE4

PROJECT : LE4

40 42Tuesday, March 14, 2006

40 42Tuesday, March 14, 2006

E

40 42Tuesday, March 14, 2006

of

of

of

1A

1A

1A

1

2

3

4

5

41

LE4 B:

VIN

PL12

PL12

E@HI0805R800R-00

E@HI0805R800R-00

A A

PL11

PL11

12

E@HI0805R800R-00

E@HI0805R800R-00

+

PC115

PC115
E@10U_25V_1206

E@10U_25V_1206

+

1.2V/1.0V 12A

+VCC_GFX_CORE

250 mils

LE4 C:

Cancel PR201

VGA_CORE

LE4 C:

Portest diode with ??
reserve.

B B

PD24

PD24

E@EC10QS04

E@EC10QS04

2 1

PC95

PC95

E@0.1U_50V_6

E@0.1U_50V_6

PD10

PD10

E@2.4V

E@2.4V

2 1

+

+

PC97

PC97

E@330U_2.5V_ESR12

E@330U_2.5V_ESR12

LE4 C:

Slove +VCC_GFX_CORE of rippe

+

+

PC96

PC96

E@330U_2.5V_ESR12

E@330U_2.5V_ESR12

1993_VIN

1993_VIN

12

+

+

PC110

PC104

PC104

E@0.1U_50V_6

E@0.1U_50V_6

*E@2.2UH-HILP-2525CZRZ-2R2-14A/20m ohm

*E@2.2UH-HILP-2525CZRZ-2R2-14A/20m ohm

+

+

PC110

E@10U_25V_1206

E@10U_25V_1206

PC98

PC98

E@330U_2.5V_ESR12

E@330U_2.5V_ESR12

12

+

+

PC108

PC108
E@10U_25V_1206

E@10U_25V_1206

PC111

PC111

E@0.1U_50V_6

E@0.1U_50V_6

PL10

PL10

0.56uH/ 1.6m ohm

0.56uH/ 1.6m ohm

PL9

PL9

1 2

PR105

PR105

1.62K/F

1.62K/F

PC99

PC99

12

E@0.22U_10V_6

E@0.22U_10V_6

PR104

PR104

1.62K/F

1.62K/F

E@2200P_5X7_4

E@2200P_5X7_4

E@EC10QS04

E@EC10QS04

VIN

PC113

PC113

PD11

PD11

PR125

PR125

12

2 1

Cancel dot

LE4 B:

Change
footprint

PD12

PD12

E@SDM10K45-7-F

E@SDM10K45-7-F

52

4

PQ47

PQ47

E@SI7392DP

E@SI7392DP

1

3

52

4

PQ46

PQ46
E@SI7336ADP

E@SI7336ADP

1

3

VGA_CSP

21

PR109

PR109

*E@0_4

*E@0_4

PC105

PC105

E@4.7U_1X7_8

E@4.7U_1X7_8

PR114 E@0_6PR114 E@0_6

PC103

PC103
E@0.1U_50V_6

E@0.1U_50V_6

1993_LX

PR103

PR103

PR120

PR120

E@0_6

E@0_6

5VSUS

PR117

PR117

12

+

+

VGA_BST
1993_DH

1993_DL

*E@0_4

*E@0_4

E@0_6

E@0_6

19

PU6

PU6

VDD

17

BST

15

DH

16

LX

18

DL

20

GND

11

CSP

12

CSN

10

OUT

9

FB

E@MAX1993ETG

E@MAX1993ETG

LE4 B:

Change to LF part
number

PR121

PR121

E@20_4

E@20_4

SKIP

13

VGA_P_VCC

22

24

OVP/UVP

SHDN

GATE

REFIN

FBLANK

2

5

VCC

POK

LSAT

GND
GND
GND
GND
GND

TON
REF

ILIM

V+

OD

14

1993PG

4
3
23
21

7

8
25

26
27
28
29
1

VGA_P_REF

6

PR110

PR110
E@100K_F_4

E@100K_F_4

PC106

PC106

E@1U_X5_6

E@1U_X5_6

1993_VIN

PR113 E@0_4PR113 E@0_4

PR115 *E@0_4PR115 *E@0_4

PR116*0_4 PR116*0_4

PC101

PC101

E@1U_10V_X5_6

E@1U_10V_X5_6

1 2

+3VRUN

PR112

PR112

*E@10K_4

*E@10K_4

PR119 E@0_4PR119 E@0_4

PR108

PR108

E@75K_F_4

E@75K_F_4

PR106

PR106

E@16.9K_F_4

E@16.9K_F_4

LE4 A:

Add GND pin

HWPG (30,36,37,38,39)

VGA_P_REFVGA_REFIN

PR107 E@75K_F_4PR107 E@75K_F_4

12

PC100

PC100
E@470P_X7_4

E@470P_X7_4

LE4 C:

Change enable type from mainon to
+3VRUN

Because it had been fist up with
+3VRUN to +VCC_GFX_CORE and 1.8VRUN

+3VRUN

*E@0_4

*E@0_4
PR204

PR204

PC107

PC107
E@0.022u_50V_6

E@0.022u_50V_6

PD26

PD26

2 1

E@SDM10K45-7-F

E@SDM10K45-7-F

PR118 E@100K_4PR118 E@100K_4

GFX_CORE_CNTRL(19)

LE4 A:

V_PWRCNTL:
High(3.3V) = 1.0V
Low(0V) = 1.1V

MAINON

PR101

PR101
*E@1M_F_4

*E@1M_F_4

C C

MAINON(30,36,38,40)

MAINON

*E@PDTC144EU

*E@PDTC144EU

PQ45

PQ45

2

MAINON

1 3

PR200

PR200

E@0_4

E@0_4

PR201

PR201

PR102

PR102
*E@1M_F_4

*E@1M_F_4

+3VRUN

*E@0_4

LE4 C:

Add +3VRUN and MAINON
selector function and fixed
circiut for C-test

D D

1

*E@0_4

2

3

2

1

PR124

PR124

*E@0_4

*E@0_4

PR123

PR123

*E@100K_4

*E@100K_4

PR122

PR122

*E@43K_F_4

*E@43K_F_4

*E@2N7002K

*E@2N7002K

*E@0_4

*E@0_4

LE4 B:

Del PR125 in BOM

PQ43

PQ43

PD25 E@SDM10K45-7-FPD25 E@SDM10K45-7-F

21

PR127

PR127

E@120K_4

E@120K_4

2

PC112

PC112
*E@0.1U_50V_6

*E@0.1U_50V_6

*E@MMBT3904

*E@MMBT3904

1 3

EN_4215

PC114

PC114
E@0.22U_50V_6

E@0.22U_50V_6

PQ48

PQ48

1.8VSUS

PC116

PC116

1 2

E@10U/X6S_8

E@10U/X6S_8

PC117

PC117
E@0.1U_50V_6

E@0.1U_50V_6

3

1

NC0

2

EN

3

VIN

4

NC1

PR126

PR126

E@10K_F_4

E@10K_F_4

PC102

PC102

E@0.1U_50V_6

E@0.1U_50V_6

PU7

PU7
E@SC4215

E@SC4215

NC2

VO
GND0
GND1

ADJ

7

4215FB

R2

PR111

PR111

E@43.2K_F_4

E@43.2K_F_4

Modify value from 127K/F to

43.2K/F

5
6
8
9

R1

PR128 E@5.1K_F_4PR128 E@5.1K_F_4

Vo=0.8(R1+R2)/R2

PC119

PC119

1 2

E@10U/X6S_8

E@10U/X6S_8

LE4 B:

PC118

PC118

1 2

E@10U/X6S_8

E@10U/X6S_8

PC109

PC109
E@0.1U_50V_6

E@0.1U_50V_6

4

LE4 B:

1.22V/ 2A

+1.22V_GFX_PCIE

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

VGA --- MAX1993

VGA --- MAX1993

VGA --- MAX1993

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

41 42Tuesday, March 14, 2006

41 42Tuesday, March 14, 2006

41 42Tuesday, March 14, 2006

of

of

5

of

1A

1A

1A

5

4

3

2

1

CW3 M/B

MODEL

CW3 M/B

D D

REV

1A

0316~0317

CHANGE LIST

1. ADD EMI Solution (Per EMI Team suggestion)

FROM

A1A

TO

C C

B B

A A

PROJECT : LE4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Change History

Change History

Change History

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : LE4

Quanta Computer Inc.

Quanta Computer Inc.

of

of

of

42 42Wednesday, November 16, 2005

42 42Wednesday, November 16, 2005

42 42Wednesday, November 16, 2005

1

1A

1A

1A