Lenovo LA46-Dis Schematics
5
A
4
LA46 Switchable Graphics System Schematics
Clock GEN
CK505
11
12
3
Channel A
DDR3 800/1066
Intel CPU
Auburndale
(Dual Core)
Channel B
DDR3 800/1066
13
HDA Link
27
SATA Port 0
28
SATA Port 1
28
USB 2.0 port?
CH3
32
CH5
24
CH7
38
CH7
35
CH8
35
CH0
35
DDR3 800/1066MHz
4,5,6,7,8,9,10
PCH HM55
AC97 2.3/Azalia Interface
14,15,16,17,18,19,20,21,22
EHCI#1
SPI
USB 2.0
SPI FLASH
4MB
38
Intel
USB 2.0 (12 ports)
Serial ATA (4 ports)
PCI Express (8 ports)
ACPI 2.0
LPC I/F
PCI Rev 2.3
INT. RTC
Nuvoton NPCE781E
Multi-touch
Touchpad
DMI x4FDI
LPC Bus / 33MHz
KBC
38
D D
C C
Headphone out
SATA HDD
SATA ODD
B B
Mic in
5-in-1
Slot
USB BD
Thermal
Sensor
EMC2103
UNBUFFERED
DDR3 SODIMM
Socket1
204-PIN DDR3 SODIMM
UNBUFFERED
DDR3 SODIMM
Socket2
HD AUDIO CODEC
ALC269Q-VB-GR
SATA CONN
SATA CONN
I/O BD
MediaCard Reader
Realtek/5138
Bluetooth
Camera
Finger Printer
USB 2.0
USB 2.0
USB 2.0
PCIe 16X Gen2
LVDS
RGB
PCI Express 8
USB 2.0 CH2
PCI Express 1
USB 2.0 CH4
PCI Express 3
USB 2.0 CH6
PCI Express 4
Int. KB
36
VRAM
PortA
NVIDIA
N11M-GE
54,55,56,57,58,59
RGB
MUX
GLAN
AR8131
Mini PCI-E
WLAN Card
Mini PCI-E
WWAN Card
Express Card
G-Sensor
38
3
DDR3
X4
512MB / 1GB
57,58
23,24,25
36
SPI Flash
128Kb
38
Project Code: 91.4GV01.001
PCB(Raw Card): 09911-1
HDMI
LVDS
LVDS
RGB
29
Transformer RJ45
30
SIM Slot
LPC Debug
Board Conn
36
HDMI CONN
HDMI BD
14'' WUXGA
(WSXGA) LCD
CRT CONN
CRT BD
I/O BD
31
2
USB BD
I/O BD
CRT BD
Power BD
Finger Printer BD
26
24
25
30
HDMI BD
BT BD
AV BD
1
PCB LAYER
L1: Top
L2: GND
L3: Signal
L4: Signal
L5: VCC
L6: Signal
L7: GND
L8: Signal
CPU DC/DC
ISL62882
INPUTS
DCBATOUT
SYSTEM DC/DC
INPUTS
SYSTEM DC/DC
DCBATOUT
SYSTEM DC/DC
INPUTS OUTPUTS
DCBATOUT
SYSTEM DC/DC
DCBATOUT
INPUTS
INPUTS
1D5V_S3 DDR_VREF_S3
SYSTEM DC/DC
DCBATOUT
SYSTEM DC/DC
DCBATOUT
INPUTS
DCBATOUT
OUTPUTS
VCC_CORE
TPS51123
OUTPUTS
5V_AUX_S5
3D3V_AUX_S5
5V_S5DCBATOUT
3D3V_S5
RT8209E
OUTPUTSINPUTS
1D5V_S3
RT8209E
1D05V_S0
RT8209E
OUTPUTSINPUTS
1D05V_VTT
LDO
RT9025
OUTPUTS
1D8V_S03D3V_S5
LDO
RT9026
OUTPUTS
0D75_S0
ISL62881
OUTPUTSINPUTS
VCC_GFXCORE
ISL62872
OUTPUTSINPUTS
VGA_CORE_S0
CHARGER
BQ24745
OUTPUTS
BT+
38,39
40
41
41
42
43
43
44
45
46
A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
01_Block Diagram
01_Block Diagram
01_Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C
1 58Wednesday, January 27, 2010
1 58Wednesday, January 27, 2010
1 58Wednesday, January 27, 2010
-1
-1
-1
5
DCCBBAA
Date:
Sheet
of
258Wednesday, January 27, 2010
Date:
Sheet
of
258Wednesday, January 27, 2010
Date:
Sheet
of
258Wednesday, January 27, 2010
Processor Strapping
Pin Name Strap Description Configuration (Default value for each bit is
CFG[4] Disabled - No Physical Display Port attached to
DisplayPort
Presence
CFG[3]
PCI-Express Static
Lane Reversal1:0:
CFG[0]
CFG[7]
PCI-Express
Configuration
Select
Reserved Temporarily used
for early
Clarksfield
samples.
D
PCH Strapping
Name Schematics Notes
SPKR
INIT3_3V# Weak internal pull-down. Do not pull high.
GNT3#/
GPIO55
INTVRMEN
GNT0#,
GNT1#
GNT2#/
GPIO53
GPIO33
SPI_MOSI
NV_ALE
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN#
/GPIO[33]
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC
GPIO15
GPIO8
GPIO27
N11M-GE Power Sequence
VDD33
PEX_VDD
NVVDD
IFPAB_IOVDD
FBVDDQ
Reboot option at power-up
Internal weak Pull-down.
Default Mode:
Connect to Vcc3_3 with 8.2-kΩ
No Reboot Mode with TCO Disabled:
- 10-kΩ weak pull-up resistor.
Internal pull-up.
Default Mode:
(Connect to ground with 4.7-kΩ weak
Low (0) = Top Block Swap Mode
pull-down resistor).
High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
Left both GNT0# and GNT1# floating. No pull up
Default (SPI):
required.
Connect GNT1# to ground with 1-kΩ pull-down
Boot from PCI:
resistor. Leave GNT0# Floating.
Connect both GNT0# and GNT1# to ground with 1-kΩ
Boot from LPC:
pull-down resistor.
Default - Internal pull-up.
= Configures DMI for ESI compatible operation (for servers
Low (0)
only. Not for mobile/desktops).
Do not pull low.
Default:
Connect to ground with 1-kΩ
Disable ME in Manufacturing Mode:
pull-down resistor.
Connect to Vcc3_3 with 8.2-kΩ weak pull-up resistor.
Enable iTPM:
Left floating, no pull-down required.
Disable iTPM:
Connect to Vcc3_3 with 8.2-kΩ weak pull-up
Enable Danbury:
resistor.
Connect to ground with 4.7-kΩ weak pull-down
Disable Danbury:
resistor.
Flash Descriptor Security will be overridden.
Low (0):
Flash Descriptor Security will be in effect.
High (1) :
Weak internal pull-down. Do not pull high.
Weak internal pull-down. Do not pull high.
Weak internal pull-up. Do not pull low.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
1 unless specified otherwise)
1:Embedded
Embedded DisplayPort.
Enabled - An external Display Port device is
0:
connected to the Embedded Display Port.
Normal Operation.
Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
Single PCI-Express Graphics
1:
Bifurcation enabled
0:
-
Clarksfield (only for early samples pre-ES1)
Connect to GND with 3.01K Ohm/5% resistor
Only temporary for early CFD samples
Note:
(rPGA/BGA) [For details please refer to the WW33
MoW and sighting report].
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not
impact AUB functionality.
PEX_VDD can ramp up any time
tNVVDD
tNV-IFPAB_IOVDD
tNV-FBVDDQ
Default
Value
1
1
1
0
4
Sequence AC
AD+
3D3V_AUX_S5
5V_AUX_S5
S5_ENABLE (KBC)
5V_S5
3D3V_S5
RSMRST#_KBC
LAN_PWR_ON
3D3V_LAN_S5
KBC_PWRBTN#
PM_PWRBTN#
PM_SLP_S4#
1D5V_S3
DDR3_VREF_S3
PM_SLP_S3#
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_S0
0D75V_S0
ALL_PWRGD
1D05V_VTT
VTT_PWRGD
(H_VTTPWRGD -->CPU, KBC)
GFX_VR_EN
VCC_GFXCORE
DIS: Before 1D05V_VTT
Platform
controlled
Sillicon
controlled
DGPU_PWR_EN#
3D3V_S0_NV
VGA_CORE_PWR
DGPU_PWROK
1D8V_S0_NV
FBVDD
1D05V_S0_NV
S0_PWR_GOOD
(IMVP_VR_EN)
VCC_CORE
VR_CLKEN#
CORE_PWRGD
(SYS_PWROK, PCH_PWROK)
PM_DRAM_PWRGD
H_PWRGD
PLT_RST#
>10ms
can power after power switch press
3
>99ms
2
1
PLANAR_ID[1..0]
KBC GPIn
PLANAR_IDn
31
1
0
0
1 0
1 1
23
0
0
1
DDR_VREF_S312,13,43
VCC_GFXCORE8,36,44
3D3V_S0_NV45,50,51,53,54,55
VGA_CORE_S045,50,51
1D8V_S0_NV50,54
FBVDD50,52,57,58
1D05V_S0_NV50,51,52,54,55
Planar ID Version
LA46 - SA
LA46 - SB
VCC_CORE7,36,39
5V_S011,20,21,23,24,25,26,27,28,35,36,44,45,48,49
3D3V_S03,5,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,31,32,33,34,35,36,38,41,43,44,50
1D5V_S35,8,12,13,36,41,43,50
1D05V_S03,14,15,16,20,21,41,50
1D05V_VTT5,7,8,19,20,21,36,38,42
1D8V_S08,20,23,36,43
Planar PCB Version
SA
SBLA46 - SB
SC
-1
VCC_CORE
5V_S0
3D3V_S0
1D5V_S3
1D05V_S0
1D05V_VTT
1D8V_S0
DDR_VREF_S3
VCC_GFXCORE
3D3V_S0_NV
VGA_CORE_S0
1D8V_S0_NV
FBVDD
1D05V_S0_NV
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
02_Reference
02_Reference
02_Reference
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA46 MB -1
A2
LA46 MB -1
A2
LA46 MB -1
A2
Taipei Hsien 221, Taiwan, R.O.C
5
A
4
3
2
1
3D3V_S0 3D3V_CK505
1 2
R247
R247
0R0603-PAD
0R0603-PAD
12
12
C358
C358
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C347
C347
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C348
C348
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
D D
DREFCLK#15
DREFCLK15
CLKIN_DMI#15
CLKIN_DMI15
CLK_PCIE_SATA#15
-1 0107
C C
CLK_PCIE_SATA15
CLK_CPU_BCLK#15
CLK_CPU_BCLK15
C369
C369
FOR CO-LAY SLG8LV595
1D5V_S0
12
C346
C346
SC47P50V2JN-3GP
SC47P50V2JN-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C383
C383
C349
C349
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_CK505
-1 0111
1 2
DY
DY
R264
R264
0R3J-0-U-GP
0R3J-0-U-GP
14
13
11
10
22
23
19
20
SLG8SP585VTR-GP
SLG8SP585VTR-GP
2ND = 71.93197.003
2ND = 71.93197.003
1D5V_S0_CK5051D5V_S0_CK505
U27
U27
4
DOT_96#
3
DOT_96
SRC_2#
SRC_2
SRC_1/SATA#
SRC_1/SATA
CPU_0#
CPU_0
CPU_1#
CPU_1
12
R258
R258
0R3J-0-U-GP
0R3J-0-U-GP
24
33
VDD_CPU
GND
1D05V_S0
-1 0107
1 2
R268
R268
0R0603-PAD
0R0603-PAD
1D05V_CK505
Low voltage I/O power
supply for outputs.
1
5
17
29
15
18
VGA 27M X1
Crystal
6
7
16
25
30
28
27
31
32
CLK GENMount
VGA_XIN1_L
OSC_SPREAD_L
CPU_STOP#
CK_PWRGD
REF_0/CPU_SEL
GEN_XTAL_IN
GEN_XTAL_OUT
VDD_SRC
VSS_CPU
VSS_REF
21
26
VDD_SRC_IO
VDD_CPU_IO
27MHZ
27MHZ_SS
CPU_STOP#
CKPWRGD/PD#
REF_0/CPU_SEL
XTAL_IN
XTAL_OUT
SDA
SCL
VSS_DOT
VSS_278VSS_SATA
VSS_SRC
2
12
9
VDD_27
VDD_REF
VDD_DOT
12
DY
DY
4
FOR DIS
12
C402
C402
C401
C401
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
R75RNT1
DYDY
Mount
Mount
DY
RNT1
RNT1
1
SRN33J-5-GP-U
SRN33J-5-GP-U
23
R249 33R2J-2-GPR249 33R2J-2-GP
PCH_SMBDATA12,13,15
PCH_SMBCLK 12,13,15
12
R79
Mount
DY
1 2
C376
C376
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D05V_CK505
12
R80
C107
MountDYMount
DY
VGA_XIN155
OSC_SPREAD 55
DY
DY
C384
C384
SC47P50V2JN-3GP
SC47P50V2JN-3GP
C131
Mount
DY
12
C351
C351
SC10P50V2JN-4GP
SC10P50V2JN-4GP
CLK_ICH14 15
1D05V_CK505 3D3V_CK505
10KR2J-3-GP
R251
R251
2K2R2J-2-GP
2K2R2J-2-GP
DY
B B
DY
1 2
1 2
REF_0/CPU_SEL
R250
R250
10KR2J-3-GP
10KR2J-3-GP
FSC 0 1
SPEED
133MHz
(Default)
100MHz
CK_PWRGD
VR_CLKEN#38
G
SB-1015 change to 84.2N702.E31
10KR2J-3-GP
R266
R266
1 2
Q21
Q21
2N7002A-7-GP
2N7002A-7-GP
S D
3D3V_CK505
1 2
R255 10KR2J-3-GPR255 10KR2J-3-GP
3.3V LVTTL input for CPU_STOP#. Contains
internal pull-up resistor.
CPU_STOP#
CL=20pF±0.2pF
C370
C370
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1 2
1 2
C377
C377
SC12P50V2JN-3GP
SC12P50V2JN-3GP
GEN_XTAL_IN
12
X4
X4
82.30005.A51
82.30005.A51
X-14D31818M-50GP
X-14D31818M-50GP
2ND = 82.30005.C51
2ND = 82.30005.C51
GEN_XTAL_OUT
Layout Notes:
Make sure that the stubs to the
test points(CK_PWRGD, CLK_EN#,
GEN_XTAL_OUT) in the layout are as
short as possible on the high speed
signals.
SB BOM change to 82.30005.A51
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
03_Clock Generator SLG8SP585
03_Clock Generator SLG8SP585
03_Clock Generator SLG8SP585
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
3 58Tuesday, January 26, 2010
3 58Tuesday, January 26, 2010
3 58Tuesday, January 26, 2010
A
-1
-1
-1
5
A
CPU1A
CPU1A
DMI_TXN016
DMI_TXN116
DMI_TXN216
DMI_TXN316
DMI_TXP016
DMI_TXP116
DMI_TXP216
D D
C C
DMI_TXP316
DMI_RXN016
DMI_RXN116
DMI_RXN216
DMI_RXN316
DMI_RXP016
DMI_RXP116
DMI_RXP216
DMI_RXP316
FDI_TXN016
FDI_TXN116
FDI_TXN216
FDI_TXN316
FDI_TXN416
FDI_TXN516
FDI_TXN616
FDI_TXN716
FDI_TXP016
FDI_TXP116
FDI_TXP216
FDI_TXP316
FDI_TXP416
FDI_TXP516
FDI_TXP616
FDI_TXP716
FDI_FSYNC016
FDI_FSYNC116
FDI_INT16
FDI_LSYNC016
FDI_LSYNC116
A24
C23
B22
A21
B24
D23
B23
A22
D24
G24
F23
H23
D25
F24
E23
G23
E22
D21
D19
D18
G21
E19
F21
G18
D22
C21
D20
C18
G22
E20
F20
G19
F17
E17
C17
F18
D17
DMI_RX0#
DMI_RX1#
DMI_RX2#
DMI_RX3#
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_TX0#
DMI_TX1#
DMI_TX2#
DMI_TX3#
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI_TX0#
FDI_TX1#
FDI_TX2#
FDI_TX3#
FDI_TX4#
FDI_TX5#
FDI_TX6#
FDI_TX7#
FDI_TX0
FDI_TX1
FDI_TX2
FDI_TX3
FDI_TX4
FDI_TX5
FDI_TX6
FDI_TX7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
B B
4
1 OF 9
1 OF 9
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
PEG_RX0#
PEG_RX1#
PEG_RX2#
DMI
DMI
PEG_RX3#
PEG_RX4#
PEG_RX5#
AUBURNDALE
AUBURNDALE
PEG_RX6#
PEG_RX7#
PEG_RX8#
PEG_RX9#
PEG_RX10#
PEG_RX11#
PEG_RX12#
PEG_RX13#
PEG_RX14#
PEG_RX15#
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
Intel(R) FDI
Intel(R) FDI
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX0#
PEG_TX1#
PEG_TX2#
PEG_TX3#
PEG_TX4#
PEG_TX5#
PEG_TX6#
PEG_TX7#
PEG_TX8#
PEG_TX9#
PEG_TX10#
PEG_TX11#
PEG_TX12#
PEG_TX13#
PEG_TX14#
PEG_TX15#
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PEG_IRCOMP_R
EXP_RBIAS
3
R500
R500
49D9R2F-GP
1 2
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_TXN15_L PEG_TXN15
PEG_TXN14_L PEG_TXN14
PEG_TXN13_L PEG_TXN13
PEG_TXN12_L PEG_TXN12
PEG_TXN11_L PEG_TXN11
PEG_TXN10_L PEG_TXN10
PEG_TXN9_L PEG_TXN9
PEG_TXN8_L PEG_TXN8
PEG_TXN7_L PEG_TXN7
PEG_TXN6_L PEG_TXN6
PEG_TXN5_L PEG_TXN5
PEG_TXN4_L PEG_TXN4
PEG_TXN3_L PEG_TXN3
PEG_TXN2_L PEG_TXN2
PEG_TXN1_L
PEG_TXN0_L PEG_TXN0
PEG_TXP15_L PEG_TXP15
PEG_TXP14_L PEG_TXP14
PEG_TXP13_L PEG_TXP13
PEG_TXP12_L PEG_TXP12
PEG_TXP11_L PEG_TXP11
PEG_TXP10_L PEG_TXP10
PEG_TXP9_L PEG_TXP9
PEG_TXP8_L PEG_TXP8
PEG_TXP7_L PEG_TXP7
PEG_TXP6_L PEG_TXP6
PEG_TXP5_L PEG_TXP5
PEG_TXP4_L PEG_TXP4
PEG_TXP3_L PEG_TXP3
PEG_TXP2_L PEG_TXP2
PEG_TXP1_L PEG_TXP1
PEG_TXP0_L PEG_TXP0
1 2
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
49D9R2F-GP
R498
R498
750R2F-GP
750R2F-GP
C632 SCD1U10V2KX-5GP
C632 SCD1U10V2KX-5GP
1 2
C628 SCD1U10V2KX-5GP
C628 SCD1U10V2KX-5GP
1 2
C630 SCD1U10V2KX-5GP
C630 SCD1U10V2KX-5GP
1 2
C342 SCD1U10V2KX-5GP
C342 SCD1U10V2KX-5GP
1 2
C343 SCD1U10V2KX-5GP
C343 SCD1U10V2KX-5GP
1 2
C340 SCD1U10V2KX-5GP
C340 SCD1U10V2KX-5GP
1 2
C338 SCD1U10V2KX-5GP
C338 SCD1U10V2KX-5GP
1 2
C345 SCD1U10V2KX-5GP
C345 SCD1U10V2KX-5GP
1 2
C335 SCD1U10V2KX-5GP
C335 SCD1U10V2KX-5GP
1 2
C316 SCD1U10V2KX-5GP
C316 SCD1U10V2KX-5GP
1 2
C312 SCD1U10V2KX-5GP
C312 SCD1U10V2KX-5GP
1 2
C294 SCD1U10V2KX-5GP
C294 SCD1U10V2KX-5GP
1 2
C270 SCD1U10V2KX-5GP
C270 SCD1U10V2KX-5GP
1 2
C272 SCD1U10V2KX-5GP
C272 SCD1U10V2KX-5GP
1 2
C260 SCD1U10V2KX-5GP
C260 SCD1U10V2KX-5GP
1 2
C258 SCD1U10V2KX-5GP
C258 SCD1U10V2KX-5GP
1 2
C633 SCD1U10V2KX-5GP
C633 SCD1U10V2KX-5GP
1 2
C629 SCD1U10V2KX-5GP
C629 SCD1U10V2KX-5GP
1 2
C631 SCD1U10V2KX-5GP
C631 SCD1U10V2KX-5GP
1 2
C341 SCD1U10V2KX-5GP
C341 SCD1U10V2KX-5GP
1 2
C344 SCD1U10V2KX-5GP
C344 SCD1U10V2KX-5GP
1 2
C339 SCD1U10V2KX-5GP
C339 SCD1U10V2KX-5GP
1 2
C337 SCD1U10V2KX-5GP
C337 SCD1U10V2KX-5GP
1 2
C336 SCD1U10V2KX-5GP
C336 SCD1U10V2KX-5GP
1 2
C332 SCD1U10V2KX-5GP
C332 SCD1U10V2KX-5GP
1 2
C320 SCD1U10V2KX-5GP
C320 SCD1U10V2KX-5GP
1 2
C302 SCD1U10V2KX-5GP
C302 SCD1U10V2KX-5GP
1 2
C277 SCD1U10V2KX-5GP
C277 SCD1U10V2KX-5GP
1 2
C268 SCD1U10V2KX-5GP
C268 SCD1U10V2KX-5GP
1 2
C276 SCD1U10V2KX-5GP
C276 SCD1U10V2KX-5GP
1 2
C263 SCD1U10V2KX-5GP
C263 SCD1U10V2KX-5GP
1 2
C252 SCD1U10V2KX-5GP
C252 SCD1U10V2KX-5GP
1 2
PEG_RXN[15..0] 51
PEG_RXP[15..0] 51
PEG_TXN1
PEG_TXN[15..0] 51
PEG_TXP[15..0] 51
2
1
AUBURUNF
AUBURUNF
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
04_CPU (1/7)-PEG / DMI / FDI
04_CPU (1/7)-PEG / DMI / FDI
04_CPU (1/7)-PEG / DMI / FDI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
4 58Tuesday, January 26, 2010
4 58Tuesday, January 26, 2010
4 58Tuesday, January 26, 2010
A
-1
-1
-1
A
1D05V_VTT
D D
H_PROCHOT#
If using an optional glue
logic receiver, a series
resistor of 2.2 k ±5% is
needed.
C C
B B
1 2
R162 49D9R2F-GPR162 49D9R2F-GP
1 2
R207 68R2-GPR207 68R2-GP
1D5V_S3
12
S3
S3
DRAMPWROK
12
S3
S3
R125
R125
1K1R2F-GP
1K1R2F-GP
R120
R120
3KR2F-GP
3KR2F-GP
5
1 2
H_CATERR#
PROCHOT#
H_PECI19
H_PROCHOT#38
PM_THRMTRIP-A#19,36
130°C
H_PM_SYNC16
H_PWRGD19,36
PM_DRAM_PWRGD16
PLT_RST#18,29,31,33,35,51
R496 20R2F-GPR496 20R2F-GP
R497 20R2F-GPR497 20R2F-GP
R179 49D9R2F-GPR179 49D9R2F-GP
R499 49D9R2F-GPR499 49D9R2F-GP
R209 0R2J-2-GP
R209 0R2J-2-GP
1 2
R493
R493
0R0402-PAD
0R0402-PAD
-1 0107
R128
R128
PM_SLP_S3#16,31,33,36,41,42,43,44
VTT_PWRGD33,42
1 2
1 2
1 2
TP41TPAD14-GP TP41TPAD14-GP
SKTOCC# (Socket Occupied)
1 2
DY
DY
-1 0112
TP50TPAD14-GP TP50TPAD14-GP
1 2
1 2
R119 0R0402-PADR119 0R0402-PAD
TP53TPAD14-GP TP53TPAD14-GP
1 2
1K5R2F-2-GP
1K5R2F-2-GP
U58
U58
1
B
2
A
3
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
S3_DY
S3_DY
1
1
R213
R213
0R0402-PAD
0R0402-PAD
1
12
R132
R132
750R2F-GP
750R2F-GP
VCC
Y
VCCPWRGOOD_1
VCCPWRGOOD_0
DRAMPWROK
H_VTTPWRGD
H_PWRGD_XDP
PLT_RST#_R
5
4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
SKTOCC#_R
H_CATERR#
PROCHOT#
H_CPURST#
3D3V_S5
CPU_VDDQ_PWRGDCPU_VDDQ_PWRGDCPU_VDDQ_PWRGDCPU_VDDQ_PWRGD
4
AT23
AT24
G16
AT26
AH24
AK14
AT15
AN26
AK15
AP26
AL15
AN14
AN27
AK13
AM15
AM26
AL14
12
C593
C593
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
S3_DY
S3_DY
CPU1B
CPU1B
COMP3
COMP2
COMP1
COMP0
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
RESET_OBS#
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
RSTIN#
AUBURUNF
AUBURUNF
SC 1130 change to 1.5Kohm
R486
R486
1 2
1K5R2F-2-GP
1K5R2F-2-GP
S3_DY
S3_DY
CPU_VDDQ_PWRGD 43
2 OF 9
2 OF 9
BCLK
MISC
MISC
CLOCKS
CLOCKS
AUBURNDALE
AUBURNDALE
THERMAL PWR MANAGEMENT
THERMAL PWR MANAGEMENT
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
R487
R487
750R2F-GP
750R2F-GP
S3_DY
S3_DY
1 2
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
PM_EXT_TS0#
PM_EXT_TS1#
SA 0903
BCLK#
PRDY#
PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPM6#
BPM7#
TCK
TMS
TDI
TDO
A16
B16
AR30
AT30
E16
D16
A18
A17
F6
AL1
AM1
AN1
AN15
AP15
AT28
AP27
AN28
AP28
AT27
AT29
AR27
AR29
AP29
AN25
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
3
BCLK_CPU_P
BCLK_CPU_N
PEG_CLK_R
PEG_CLK#_R
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DDR3_DRAMRST#_R
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_TDI_M
XDP_TDO_M
XDP_DBRESET#
1
VTT_PWRGD33,42
BCLK_CPU_P 19
BCLK_CPU_N 19
PEG_CLK_R 15
PEG_CLK#_R 15
DPLL_REF_SSCLK 15
DPLL_REF_SSCLK# 15
RN30
RN30
SRN10KJ-5-GP
SRN10KJ-5-GP
1
2 3
TP106TPAD14-GPTP106TPAD14-GP
-1 0114
1D05V_VTT
4
R494
R494
10KR2J-3-GP
10KR2J-3-GP
VTT_PWRGD H_VTTPWRGD_RDRAMPWROK
C617
C617
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
PM_EXTTS#0_R12
PM_EXTTS#1_R13
3D3V_S0
12
1 2
2
DPLL_REF_SSCLK#
DPLL_REF_SSCLK
-1 0112
SA 0901 : LC require to reserve
DDR3_DRAMRST#_R
R489
R489
100KR2J-1-GP
100KR2J-1-GP
S3_DY
S3_DY
XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
Q51
Q51
1
6
2
5
3 4
DMN66D0LDW-7-GP
DMN66D0LDW-7-GP
SB 1015 change to 84.DMN66.03F
1 2
R503 51R2J-2-GP
R503 51R2J-2-GP
1 2
R504 51R2J-2-GP
R504 51R2J-2-GP
1 2
R205 51R2J-2-GP
R205 51R2J-2-GP
1 2
R502 51R2J-2-GPR502 51R2J-2-GP
1 2
R215 51R2J-2-GP
R215 51R2J-2-GP
1 2
R501 51R2J-2-GPR501 51R2J-2-GP
R492
R492
100KR2J-1-GP
100KR2J-1-GP
RN77
RN77
1
4
2 3
SRN0J-6-GP
SRN0J-6-GP
DY
DY
1 2
R484 0R2J-2-GP
R484 0R2J-2-GP
S3
S3
2 3
S
S
12
3D3V_S5
1
G
G
1 2
DY
DY
DY
DY
DY
DY
DY
DY
12
1D05V_VTT
12
R495
R495
1KR2J-1-GP
1KR2J-1-GP
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
Q49
Q49
S3_DY
S3_DY
BSS138LT1
BSS138LT1
D
D
2ND = 84.00138.G31
2ND = 84.00138.G31
Vgs(th)<=1.5V
C601
C601
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
S3_DY
S3_DY
1D05V_VTT
H_VTTPWRGD
1 2
R90 100R2F-L1-GP-UR90 100R2F-L1-GP-U
1 2
R91 24D9R2F-L-GPR91 24D9R2F-L-GP
1 2
R92 130R2F-1-GPR92 130R2F-1-GP
impedance compensation
1D5V_S3
R479
R479
1KR2J-1-GP
1KR2J-1-GP
S3_DY
S3_DY
1 2
DDR3_DRAMRST# 12,13
SC CHECK
RST_GATE19
CPU JTAG
XDP_TDO_M
-1 0107
XDP_TDI_M
XDP_DBRESET#
1 2
R203
R203
1KR2J-1-GP
1KR2J-1-GP
check list: 5k pu
1
12
R505
R505
0R0402-PAD
0R0402-PAD
3D3V_S0
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
05_CPU (2/7)-HOST
05_CPU (2/7)-HOST
05_CPU (2/7)-HOST
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Taipei Hsien 221, Taiwan, R.O.C
1
5 58Tuesday, January 26, 2010
5 58Tuesday, January 26, 2010
5 58Tuesday, January 26, 2010
A
-1
-1
-1
5
DCCBBAA
CPU1C
CPU1C
3 OF 9
3 OF 9
4
3
CPU1D
CPU1D
2
4 OF 9
4 OF 9
1
AA6
SA_CK0
M_A_DQ[63..0]12
D
M_A_BS012
M_A_BS112
M_A_BS212
M_A_CAS#12
M_A_RAS#12
M_A_WE#12
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
C10
D10
H10
G10
AH5
AF5
AK6
AK7
AF6
AG5
AJ10
AL10
AK12
AK8
AK11
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
AC3
AB2
AE1
AB3
AE9
A10
SA_DQ0
SA_DQ1
C7
SA_DQ2
A7
SA_DQ3
B10
SA_DQ4
SA_DQ5
E10
SA_DQ6
A8
SA_DQ7
D8
SA_DQ8
F10
SA_DQ9
E6
SA_DQ10
F7
SA_DQ11
E9
SA_DQ12
B7
SA_DQ13
E7
SA_DQ14
C6
SA_DQ15
SA_DQ16
G8
SA_DQ17
K7
SA_DQ18
J8
SA_DQ19
G7
SA_DQ20
SA_DQ21
J7
SA_DQ22
J10
SA_DQ23
L7
SA_DQ24
M6
SA_DQ25
M8
SA_DQ26
L9
SA_DQ27
L6
SA_DQ28
K8
SA_DQ29
N8
SA_DQ30
P9
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
AJ7
SA_DQ38
AJ6
SA_DQ39
SA_DQ40
AJ9
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
AL7
SA_DQ45
SA_DQ46
AL8
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS0
SA_BS1
U7
SA_BS2
SA_CAS#
SA_RAS#
SA_WE#
AUBURNDALE
AUBURNDALE
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CK0#
SA_CKE0
SA_CK1
SA_CK1#
SA_CKE1
SA_CS0#
SA_CS1#
SA_ODT0
SA_ODT1
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_CLK_DDR0 12
M_CLK_DDR#0 12
M_CKE012
M_CLK_DDR1 12
M_CLK_DDR#1 12
M_CKE112
M_CS#012
M_CS#112
M_ODT012
M_ODT112
M_A_DM[7..0] 12
M_A_DQS#[7..0] 12
M_A_DQS[7..0] 12
M_A_A[15..0] 12
M_B_DQ[63..0]13
M_B_BS013
M_B_BS113
M_B_BS213
M_B_CAS#13
M_B_RAS#13
M_B_WE#13
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AG1
AG4
AG3
AM6
AM4
AM3
AR10
AT10
AF3
AJ3
AK1
AJ4
AH4
AK3
AK4
AN2
AK5
AK2
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AB1
AC5
AC6
B5
SB_DQ0
A5
SB_DQ1
C3
SB_DQ2
B3
SB_DQ3
E4
SB_DQ4
A6
SB_DQ5
A4
SB_DQ6
C4
SB_DQ7
D1
SB_DQ8
D2
SB_DQ9
F2
SB_DQ10
F1
SB_DQ11
C2
SB_DQ12
F5
SB_DQ13
F3
SB_DQ14
G4
SB_DQ15
H6
SB_DQ16
G2
SB_DQ17
J6
SB_DQ18
J3
SB_DQ19
G1
SB_DQ20
G5
SB_DQ21
J2
SB_DQ22
J1
SB_DQ23
J5
SB_DQ24
K2
SB_DQ25
L3
SB_DQ26
M1
SB_DQ27
K5
SB_DQ28
K4
SB_DQ29
M4
SB_DQ30
N5
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS0
W5
SB_BS1
R7
SB_BS2
SB_CAS#
Y7
SB_RAS#
SB_WE#
AUBURNDALE
AUBURNDALE
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
SB_CK0
SB_CK0#
SB_CKE0
SB_CK1
SB_CK1#
SB_CKE1
SB_CS0#
SB_CS1#
SB_ODT0
SB_ODT1
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
W8
W9
M3
V7
V6
M2
AB8
AD6
AC7
AD1
D4
E1
H3
K1
AH1
AL2
AR4
AT8
D5
F4
J4
L4
AH2
AL4
AR5
AR8
C5
E3
H4
M5
AG2
AL5
AP5
AR7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_CLK_DDR2 13
M_CLK_DDR#2 13
M_CKE213
M_CLK_DDR3 13
M_CLK_DDR#3 13
M_CKE313
M_CS#213
M_CS#313
M_ODT213
M_ODT313
M_B_DM[7..0] 13
M_B_DQS#[7..0] 13
M_B_DQS[7..0] 13
M_B_A[15..0] 13
AUBURUNF
AUBURUNF
5
4
3
AUBURUNF
AUBURUNF
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
06_CPU (3/7)-MEM INTERFACE
06_CPU (3/7)-MEM INTERFACE
06_CPU (3/7)-MEM INTERFACE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
Taipei Hsien 221, Taiwan, R.O.C
6 58Tuesday, January 26, 2010
6 58Tuesday, January 26, 2010
6 58Tuesday, January 26, 2010
1
-1
-1
-1
5
A
4
6 OF 9
CPU1F
CPU1F
6 OF 9
3
2
1
PROCESSOR CORE POWER
48A -->Arrandale
D D
VCC_CORE
C238
C235
C235
C244
C244
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C240
C240
C618
C618
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C C
C242
C242
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C238
C236
C236
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C619
C619
C620
C620
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C267
C267
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C243
C243
C627
C627
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C239
C239
C237
C237
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C241
C241
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C251
C251
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C634
C634
C635
C635
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
B B
VCC_CORE
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AUBURUNF
AUBURUNF
AUBURNDALE
AUBURNDALE
1.1V RAIL POWER
1.1V RAIL POWER
CPU CORE SUPPLY
CPU CORE SUPPLY
PROC_DPRSLPVR
CPU VIDS
CPU VIDS
POWER
POWER
VTT_SELECT
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
SENSE LINES
SENSE LINES
AH14
VTT0
AH12
VTT0
AH11
VTT0
AH10
VTT0
J14
VTT0
J13
VTT0
H14
VTT0
H12
VTT0
G14
VTT0
G13
VTT0
G12
VTT0
G11
VTT0
F14
VTT0
F13
VTT0
F12
VTT0
F11
VTT0
E14
VTT0
E12
VTT0
D14
VTT0
D13
VTT0
D12
VTT0
D11
VTT0
C14
VTT0
C13
VTT0
C12
VTT0
C11
VTT0
B14
VTT0
B12
VTT0
A14
VTT0
A13
VTT0
A12
VTT0
A11
VTT0
AF10
VTT0
AE10
VTT0
AC10
VTT0
AB10
VTT0
Y10
VTT0
W10
VTT0
U10
VTT0
T10
VTT0
J12
VTT0
J11
VTT0
J16
VTT0
J15
VTT0
AN33
PSI#
H_VID0
AK35
VID0
VID1
VID2
VID3
VID4
VID5
VID6
ISENSE
AK33
AK34
AL35
AL33
AM33
AM35
AM34
G15
AN35
AJ34
AJ35
B15
A15
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_VTTVID1
SB 1019 remove test point
C621
C621
C616
C616
C613
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
Clarksfield H_VTTVID1 = Low, VTT = 1.1V
Arrandale H_VTTVID1 = High, VTT = 1.05V
1
C613
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide.
C602
C602
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PSI#38
H_VID[6..0] 38
PM_DPRSLPVR38
TP35 TPAD14-GPTP35 TPAD14-GP
IMVP_IMON38
VTT_SENSE42
1D05V_VTT
C604
C604
C603
C603
C605
C605
12
C218
C218
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
Please note that the VTT Rail
Values are Auburndale
VTT=1.05V; Clarksfield
VTT=1.1V
VCC_CORE
12
R238
R238
100R2F-L1-GP-U
100R2F-L1-GP-U
12
R232
R232
100R2F-L1-GP-U
100R2F-L1-GP-U
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1D05V_VTT
C611
C611
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
VCC_SENSE38
VSS_SENSE38
SA 0917
1D05V_VTT
C636
C636
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
1 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
07_CPU (4/7)-POWER
07_CPU (4/7)-POWER
07_CPU (4/7)-POWER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C
7 58Wednesday, January 27, 2010
7 58Wednesday, January 27, 2010
7 58Wednesday, January 27, 2010
A
-1
-1
-1
D D
A
C C
B B
VCC_GFXCORE
C216
C216
C614
C614
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
DY
DY
Please note that the VTT Rail
Values are Auburndale
VTT=1.05V; Clarksfield
VTT=1.1V
1D05V_VTT
TC7
TC7
ST220U2D5VBM-2GP
ST220U2D5VBM-2GP
C223
C223
5
C609
C609
C610
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
DY
DY
1D05V_VTT
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C607
C607
C610
C612
C612
18A
12
12
DY
DY
C210
C210
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
C208
C208
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C233
C233
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C234
C234
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
C205
C205
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C608
C608
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C255
C255
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4
CPU1G
CPU1G
AT21
VAXG1
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
H25
K26
H27
G28
G27
G26
F26
E26
E25
J24
J23
J27
J26
J25
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
AUBURUNF
AUBURUNF
AUBURNDALE
AUBURNDALE
GRAPHICS
GRAPHICS
FDI PEG & DMI
FDI PEG & DMI
POWER
POWER
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
GRAPHICS VIDs
GRAPHICS VIDs
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
1.1V1.8V
1.1V1.8V
7 OF 9
7 OF 9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
AN24
AR25
AT25
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
3
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6
12
C201
C201
C230
C230
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C211
C211
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C256
C256
VCC_AXG_SENSE44
VSS_AXG_SENSE44
GFX_VR_EN:
4.7-k pull-down to GND at PWM
GFX_VR_EN44
GFX_DPRSLPVR 44
GFX_IMON44
12
12
C202
C202
C203
C203
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
12
12
+V1.8S_VCCSFR
12
12
C259
C259
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C606
C606
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C209
C209
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C246
C246
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C204
C204
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D05V_VTT
1D05V_VTT
12
C247
C247
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
GFX_VID[6..0] 44
6A
12
12
C182
C182
C184
C184
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C381
C381
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
0.6A
1 2
0R0603-PAD
0R0603-PAD
2
C185
C185
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
R257
R257
-1 0110
12
C186
C186
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1D8V_S0
1
SA 0901: LC require to reserve s3 reduce
power circuit
1D5V_CPU_VDDQ
1 2
S3
S3
R454 0R2J-2-GP
R454 0R2J-2-GP
1 2
S3
S3
R453 0R2J-2-GP
R453 0R2J-2-GP
1 2
S3
S3
R455 0R2J-2-GP
R455 0R2J-2-GP
1 2
S3
S3
R456 0R2J-2-GP
R456 0R2J-2-GP
1 2
S3
S3
R457 0R2J-2-GP
R457 0R2J-2-GP
U56
U56
S3_DY
S3_DY
S
S
1
S
S
2
S
S
3
G D
G D
4 5
AO4468-GP
AO4468-GP
84.04468.037
84.04468.037
2nd = 84.04800.D37
2nd = 84.04800.D37
U37_G
1 2
S3_DY
S3_DY
R459 0R2J-2-GP
R459 0R2J-2-GP
C570
C570
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
S3_DY
S3_DY
1D5V_CPU_VDDQ
R466
R466
200R2J-L1-GP
200R2J-L1-GP
S3_DY
S3_DY
1 2
Q64_D
Q45
Q45
2N7002A-7-GP
2N7002A-7-GP
S3_DY
S3_DY
G
-1 0114
S D
SA 0903: Place across the plane
D
D
8
D
D
7
D
D
6
ESD Protect
PM_SLP_S336
1D5V_S3
RUN_POWER_ON
SB 1022 Remove
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
08_CPU (5/7)-Graphic PWR
08_CPU (5/7)-Graphic PWR
08_CPU (5/7)-Graphic PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
8 58Wednesday, January 27, 2010
8 58Wednesday, January 27, 2010
8 58Wednesday, January 27, 2010
A
-1
-1
-1
5
A
8 OF 9
CPU1H
CPU1H
AT20
VSS
AT17
VSS
AR31
VSS
AR28
VSS
AR26
VSS
AR24
VSS
AR23
D D
C C
B B
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AUBURNDALE
AUBURNDALE
VSS
VSS
8 OF 9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
4
CPU1I
CPU1I
K27
VSS
K9
VSS
K6
VSS
K3
VSS
J32
VSS
J30
VSS
J21
VSS
J19
VSS
H35
VSS
H32
VSS
H28
VSS
H26
VSS
H24
VSS
H22
VSS
H18
VSS
H15
VSS
H13
VSS
H11
VSS
H8
VSS
H5
VSS
H2
VSS
G34
VSS
G31
VSS
G20
VSS
G9
VSS
G6
VSS
G3
VSS
F30
VSS
F27
VSS
F25
VSS
F22
VSS
F19
VSS
F16
VSS
E35
VSS
E32
VSS
E29
VSS
E24
VSS
E21
VSS
E18
VSS
E13
VSS
E11
VSS
E8
VSS
E5
VSS
E2
VSS
D33
VSS
D30
VSS
D26
VSS
D9
VSS
D6
VSS
D3
VSS
C34
VSS
C32
VSS
C29
VSS
C28
VSS
C24
VSS
C22
VSS
C20
VSS
C19
VSS
C16
VSS
B31
VSS
B25
VSS
B21
VSS
B18
VSS
B17
VSS
B13
VSS
B11
VSS
B8
VSS
B6
VSS
B4
VSS
A29
VSS
A27
VSS
A23
VSS
A9
VSS
3
9 OF 9
9 OF 9
AUBURNDALE
AUBURNDALE
VSS
VSS
VSS_NCTF#AR34
VSS_NCTF#B34
VSS_NCTF#B2
VSS_NCTF#B1
VSS_NCTF#A35
VSS_NCTF#AT1
VSS_NCTF#AT35
RSVD_NCTF#AT33
RSVD_NCTF#AT34
RSVD_NCTF#AP35
RSVD_NCTF#AR35
RSVD_NCTF#AT3
RSVD_NCTF#AR1
RSVD_NCTF#AP1
RSVD_NCTF#AT2
RSVD_NCTF#C1
RSVD_NCTF#A3
RSVD_NCTF#C35
RSVD_NCTF#B35
RSVD_NCTF#A34
RSVD_NCTF#A33
NCTF TEST PIN:
A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,
AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35
NCTF TEST PIN:
A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,
AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35
AR34
B34
B2
B1
A35
AT1
AT35
AT33
AT34
AP35
AR35
AT3
AR1
AP1
AT2
C1
A3
C35
B35
A34
A33
TP_MCP_VSS_NCTF6
TP_MCP_VSS_NCTF1
TP_MCP_VSS_NCTF2
TP_MCP_VSS_NCTF7
TP27 AFTE14P-GPTP27 AFTE14P-GP
1
TP63 AFTE14P-GPTP63 AFTE14P-GP
1
TP26 AFTE14P-GPTP26 AFTE14P-GP
1
TP64 AFTE14P-GPTP64 AFTE14P-GP
1
2
1
AUBURUNF
AUBURUNF
AUBURUNF
AUBURUNF
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
09_CPU (6/7)-VSS
09_CPU (6/7)-VSS
09_CPU (6/7)-VSS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
9 58Tuesday, January 26, 2010
9 58Tuesday, January 26, 2010
9 58Tuesday, January 26, 2010
A
-1
-1
-1
5
A
CPU1E
CPU1E
AP25
RSVD#AP25
AL25
RSVD#AL25
AL24
RSVD#AL24
AL22
RSVD#AL22
AJ33
RSVD#AJ33
AG9
D D
H_RSVD9_R
1
TP37TPAD14-GP TP37TPAD14-GP
TP38TPAD14-GP TP38TPAD14-GP
H_RSVD10_R CFG3
1
M27
G25
G17
H17
E31
E30
L28
J17
RSVD#AG9
RSVD#M27
RSVD#L28
SA_DIMM_VREF#
SB_DIMM_VREF#
RSVD#G25
RSVD#G17
RSVD#E31
RSVD#E30
4
5 OF 9
5 OF 9
RSVD#AJ13
RSVD#AJ12
RSVD#AH25
RSVD#AK26
RSVD#AL26
RSVD_NCTF#AR2
AUBURNDALE
AUBURNDALE
RSVD#AJ26
RSVD#AJ27
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
3
CFG0
12
R236
R236
3KR2F-GP
3KR2F-GP
DY
DY
12
R233
R233
3KR2F-GP
3KR2F-GP
2
1
PCI-Express Configuration Select
CFG0
1:Single PEG
0:Bifurcation enabled
CFG3 - PCI-Express Static Lane Reversal
CFG3
1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
KEY
RSVD#D15
RSVD#C15
VSS
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AR32
E15
F15
A2
D15
C15
RSVD64_R
AJ15
RSVD65_R
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
RSVD_VSS
AP34
1 2
0R0402-PAD
0R0402-PAD
VSS (AP34) can be left NC is
CRB implementation; EDS/DG
recommendation to GND.
R231
R231
1
1
TP36 TPAD14-GPTP36 TPAD14-GP
TP33 TPAD14-GPTP33 TPAD14-GP
-1 0114
CFG4
CFG7
12
R235
R235
3KR2F-GP
3KR2F-GP
DY
DY
12
R234
R234
3KR2F-GP
3KR2F-GP
DY
DY
CFG4 - Display Port Presence
CFG4
CFG7 Clarksfield (only for early samples pre-ES1) -
1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
CFG7(Reserved) - Temporarily used for early
Clarksfield samples.
Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample
(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.
CFG0
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
B19
A19
A20
B20
AC9
AB9
U9
J29
J28
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD_TP#H16
RSVD#B19
RSVD#A19
RSVD#A20
RSVD#B20
RSVD#U9
T9
RSVD#T9
RSVD#AC9
RSVD#AB9
RSVD#J29
RSVD#J28
AUBURUNF
AUBURUNF
CFG1
1
TP51TPAD14-GP TP51TPAD14-GP
TP59TPAD14-GP TP59TPAD14-GP
TP58TPAD14-GP TP58TPAD14-GP
TP55TPAD14-GP TP55TPAD14-GP
TP61TPAD14-GP TP61TPAD14-GP
TP56TPAD14-GP TP56TPAD14-GP
TP49TPAD14-GP TP49TPAD14-GP
TP48TPAD14-GP TP48TPAD14-GP
C C
TP105TPAD14-GP TP105TPAD14-GP
TP104TPAD14-GP TP104TPAD14-GP
TP57TPAD14-GP TP57TPAD14-GP
TP60TPAD14-GP TP60TPAD14-GP
TP62TPAD14-GP TP62TPAD14-GP
TP52TPAD14-GP TP52TPAD14-GP
TP47TPAD14-GP TP47TPAD14-GP
TP54TPAD14-GP TP54TPAD14-GP
1
1
CFG2
1
CFG3
CFG4
CFG5
1
CFG6
1
CFG7
CFG8
1
CFG9
1
CFG10
1
CFG11
1
CFG12
1
CFG13
1
CFG14
1
CFG15
1
CFG16
1
CFG17
1
H_RSVD17_R
H_RSVD18_R
B B
RSVD#AL28
RSVD#AL29
RSVD#AP30
RSVD#AP32
RSVD#AL27
RSVD#AT31
RSVD#AT32
RSVD#AP33
RSVD#AR33
RSVD#AR32
RSVD_TP#E15
RSVD_TP#F15
RESERVED
RESERVED
RSVD#AJ15
RSVD#AH15
RSVD_TP#AA5
RSVD_TP#AA4
RSVD_TP#R8
RSVD_TP#AD3
RSVD_TP#AD2
RSVD_TP#AA2
RSVD_TP#AA1
RSVD_TP#R9
RSVD_TP#AG7
RSVD_TP#AE3
RSVD_TP#V4
RSVD_TP#V5
RSVD_TP#N2
RSVD_TP#AD5
RSVD_TP#AD7
RSVD_TP#W3
RSVD_TP#W2
RSVD_TP#N3
RSVD_TP#AE5
RSVD_TP#AD9
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
10_CPU (7/7)-RESERVED
10_CPU (7/7)-RESERVED
10_CPU (7/7)-RESERVED
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
10 58Tuesday, January 26, 2010
10 58Tuesday, January 26, 2010
10 58Tuesday, January 26, 2010
A
-1
-1
-1
5
A
4
3
2
1
Close to PCH on top side.
SA 0905 change to 390p
3
E
D D
C
Q6
Q6
MMBT3904WT1G-GP
MMBT3904WT1G-GP
2
E
C
Q42
Q42
MMBT3904WT1G-GP
MMBT3904WT1G-GP
between CPU, VGA and DIMM on bottom side
C C
HW_THRMTRIP#33,36
B
B
3D3V_AUX_S5
12
C183
C183
SC390P50V2KX-GP
SC390P50V2KX-GP
12
C404
C404
SC390P50V2KX-GP
SC390P50V2KX-GP
DY
DY
R633
R633
10KR2J-3-GP
10KR2J-3-GP
1 2
3D3V_S0
G
Q25
Q25
2N7002A-7-GP
2N7002A-7-GP
2200p close to smsc2103 chip
3D3V_S0
12
R275
R275
10KR2J-3-GP
10KR2J-3-GP
SD
SYS_SHDN# FAN_PWM_CFAN_PWM
REMOTE2-
12
C569
C569
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
REMOTE2+
SHDN_SEL
3D3V_S0
12
R280
R280
6K8R2J-GP
6K8R2J-GP
SHDN --> 2N3904 ON External diode
SB 1015 change to 84.2N702.E31
T8
1
C
B
Q9
Q9
E
MMBT3904WT1G-GP
MMBT3904WT1G-GP
CPU backside or inside the socket
CPU TEMP:
H_THERMDA and H_THERMDC routing 10mil trace width
and spacing. Locate Capacity near Thermal diode.
Close to connector
KA
D2
1SS355PT-GP
1SS355PT-GP
FAN_TACH
FAN_PWM_C49
FAN_TACH49
D2
DY
DY
R427
R427
1 2
0R0402-PAD
0R0402-PAD
C39
C39
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
SA 0905
-1 0107
2200p close to smsc2103 chip
5V_S0
12
R426
R426
10KR2J-3-GP
10KR2J-3-GP
H_THERMDA
12
C389
C389
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
H_THERMDC
SA 0823
FAN1
FAN1
5
1
2
3
4
6
ACES-CON4-GP-U1
ACES-CON4-GP-U1
20.F0714.004
20.F0714.004
4 WIRE PWM Fan Control circuit
3D3V_S0
12
R260
R260
68R2-GP
C388
C388
2103_VDD
1 2
SCD1U10V2KX-4GP
1 2
SCD1U10V2KX-4GP
SYS_SHDN# SHDN_SEL
THERM_SCI#_R
SMBC_THERM33,34,55
SMBD_THERM33,34,55
H_THERMDA
H_THERMDC
REMOTE2+
REMOTE2-
SC 1203
R272 0R0402-PADR272 0R0402-PAD
B B
1
TP66
TP66
TPAD14-GP
TPAD14-GP
THERM_SCI#
pin6, ALERT# OD
pin7, SYS_SHDN# OD
68R2-GP
U31
U31
3
VDD
2
DP1
1
DN1
16
DP2/DN3
15
ND2/DP3
7
SYS_SHDN#
6
ALERT#
9
SMCLK
8
SMDATA
EMC2103-2-AP-GP
EMC2103-2-AP-GP
GPIO1
GPIO2
TACH
PWM
TRIP_SET
SHDN_SEL
GND
GND
4
5
10
11
14
13
12
17
2103_4
1
2103_5
1
TRIP_SET
R276 2K05R2F-GPR276 2K05R2F-GP
1 2
TP65 TPAD14-GPTP65 TPAD14-GP
TP67 TPAD14-GPTP67 TPAD14-GP
T8 = 105
RN49
RN49
2 3
1
SRN10KJ-5-GP
SRN10KJ-5-GP
D7
D7
1SS355PT-GP
1SS355PT-GP
3D3V_S0
4
FAN_TACH
KA
FAN_PWM
SA 0905
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
11_THERMAL SMSC2103
11_THERMAL SMSC2103
11_THERMAL SMSC2103
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
11 58Tuesday, January 26, 2010
11 58Tuesday, January 26, 2010
11 58Tuesday, January 26, 2010
A
-1
-1
-1
5
A
D D
SA 0902
1D5V_S3 DDR_VREF_S3
12
12
R63
R63
1KR2F-3-GP
1KR2F-3-GP
DY
DY
R64
R64
1KR2F-3-GP
1KR2F-3-GP
DY
DY
R66
R66
0R0603-PAD
0R0603-PAD
1 2
DIMM0_VREF_CADQ
-1 0114
C C
DIMM0_VREF_CADQ
R59
R59
1 2
0R0603-PAD
0R0603-PAD
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
-1 0107
DIMM0_VREF_CADQ
B B
Place these caps
close to VTT1 and
VTT2.
R42
R42
0R0603-PAD
0R0603-PAD
0D75_S0
1 2
12
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R46
R46
0R0603-PAD
0R0603-PAD
12
C58
C58
C48
C48
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
MA_VTT
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
M_VREF_CA_DIMM0
12
C89
M_VREF_DQ_DIMM0
12
C89
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
C55
C55
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
C82
C82
C53
C53
SB 1026 change to 78.22520.5BL
-1 0107
12
C70
C70
C60
C60
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DDR3_DRAMRST#5,13
4
SA 0820
DM1
M_A_A[15..0]6
M_A_BS26
M_A_BS06
M_A_BS16
M_A_DQ[63..0]6
M_A_DQS#[7..0]6
M_A_DQS[7..0]6
M_ODT06
M_ODT16
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_VREF_CA_DIMM0
M_VREF_DQ_DIMM0
MA_VTT
H = 4mm
DM1
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P-31-GP-U
DDR3-204P-31-GP-U
62.10017.M11
62.10017.M11
62.10017.M41
62.10017.M41
SB 1024 Change to 62.10017.M41
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
WE#
3
NP1
NP1
NP2
NP2
110
113
115
114
121
73
74
101
CK0
103
102
CK1
104
M_A_DM0
11
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
SA0
SA1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_A_DM1
28
M_A_DM2
46
M_A_DM3
63
M_A_DM4
136
M_A_DM5
153
M_A_DM6
170
M_A_DM7
187
SODIMM0_1_SMB_DATA_R
200
SODIMM0_1_SMB_CLK_R
202
TS#_DIMM0
198
199
SA0_DIM0
197
SA1_DIM0
201
77
122
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
R52
R52
0R0402-PAD
0R0402-PAD
1D5V_S3
1 2
M_A_RAS# 6
M_A_WE# 6
M_A_CAS# 6
M_CS#0 6
M_CS#1 6
M_CKE0 6
M_CKE1 6
M_CLK_DDR0 6
M_CLK_DDR#0 6
M_CLK_DDR1 6
M_CLK_DDR#1 6
M_A_DM[7..0] 6
-1 0107
12
C54
C54
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC 1203
PM_EXTTS#0_R 5
C57
C57
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
2
3D3V_S0
12
DY
DY
SA0_DIM0
SA1_DIM0
12
R53 0R0402-PADR53 0R0402-PAD
1 2
R54 0R0402-PADR54 0R0402-PAD
1 2
3D3V_S0
SB 1026 change to 78.22520.5BL
12
R45
R45
10KR2J-3-GP
10KR2J-3-GP
SODIMM A DECOUPLING
1D5V_S3
C81
C81
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
Place these Caps near SO-DIMMA.
R43
R43
10KR2J-3-GP
10KR2J-3-GP
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0
R44
R44
SO-DIMMA SPD Address is 0xA2
10KR2J-3-GP
10KR2J-3-GP
SO-DIMMA TS Address is 0x32
PCH_SMBDATA 3,13,15
PCH_SMBCLK 3,13,15
12
12
C46
C46
C47
C47
C83
C83
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C84
C84
C85
C85
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
12
C86
C86
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C51
C51
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12_DDR3-SODIMM1
12_DDR3-SODIMM1
12_DDR3-SODIMM1
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
12
C87
C87
C88
C88
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C52
C52
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
12 58Wednesday, January 27, 2010
12 58Wednesday, January 27, 2010
12 58Wednesday, January 27, 2010
A
-1
-1
-1
5
A
M_B_A[15..0]6
D D
M_B_BS26
M_B_BS06
M_B_BS16
M_B_DQ[63..0]6
SA 0902
1D5V_S3 DDR_VREF_S3
12
R420
R420
1KR2F-3-GP
1KR2F-3-GP
DY
DY
12
R421
R421
1KR2F-3-GP
1KR2F-3-GP
DY
DY
C C
DIMM1_VREF_CADQ
DIMM1_VREF_CADQ
R425
R425
1 2
0R0603-PAD
0R0603-PAD
R423
R423
1 2
0R0603-PAD
0R0603-PAD
R419
R419
0R0603-PAD
0R0603-PAD
1 2
DIMM1_VREF_CADQ
-1 0107
C547
C547
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C544
C544
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_VREF_CA_DIMM1
12
M_VREF_DQ_DIMM1
12
-1 0114
C543
C543
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
C538
C538
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
SB 1026 change to 78.22520.5BL
B B
M_B_DQS#[7..0]6
M_B_DQS[7..0]6
0D75_S0
-1 0107
Place these caps
close to VTT1 and
VTT2.
12
C40
C40
R41
R41
0R0603-PAD
0R0603-PAD
12
12
C41
C41
C42
C42
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DDR3_DRAMRST#5,12
1 2
12
C43
C43
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4
SA 0820
DM2
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_ODT26
M_ODT36
MB_VTT
MB_VTT
M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1
DM2
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P-51-GP
DDR3-204P-51-GP
62.10017.P51
62.10017.P51
62.10017.P91
62.10017.P91
SB 1024 Change to 62.10017.P91
RAS#
WE#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
NP1
NP1
NP2
NP2
110
113
115
114
121
73
74
101
CK0
103
102
CK1
104
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198
199
197
SA0
201
SA1
77
122
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
3
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SODIMM1_1_SMB_DATA_R
SODIMM1_1_SMB_CLK_R
TS#_DIMM1
SA0_DIM1
SA1_DIM1
1D5V_S3
R38
R38
0R0402-PAD
0R0402-PAD
M_B_RAS# 6
M_B_WE# 6
M_B_CAS# 6
M_CS#2 6
M_CS#3 6
M_CKE2 6
M_CKE3 6
M_CLK_DDR2 6
M_CLK_DDR#2 6
M_CLK_DDR3 6
M_CLK_DDR#3 6
M_B_DM[7..0] 6
SC 1203
1 2
-1 0107
12
C548
C548
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PM_EXTTS#1_R 5
H =8mm
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
2
SA1_DIM1
SA0_DIM1
R39 0R0402-PADR39 0R0402-PAD
1 2
R40 0R0402-PADR40 0R0402-PAD
1 2
C546
C546
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
SB 1026 change to 78.22520.5BL
SODIMM B DECOUPLING
1D5V_S3
C539
C539
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C540
C540
3D3V_S0
12
12
C44
C44
C45
C45
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C541
C541
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
12
C542
C542
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R424
R424
10KR2J-3-GP
10KR2J-3-GP
12
C535
C535
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C49
C49
12
3D3V_S0
12
R36
R36
10KR2J-3-GP
10KR2J-3-GP
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
12
R37
R37
10KR2J-3-GP
10KR2J-3-GP
DY
DY
PCH_SMBDATA 3,12,15
PCH_SMBCLK 3,12,15
12
12
C536
C536
C537
C537
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C50
C50
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
13_DDR3-SODIMM2
13_DDR3-SODIMM2
13_DDR3-SODIMM2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C
13 58Wednesday, January 27, 2010
13 58Wednesday, January 27, 2010
13 58Wednesday, January 27, 2010
A
-1
-1
-1
D D
A
C C
B B
C191
C191
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC-BOM Change to 6p
-1 0109 10ppm
-1 0126 BOM Change
ACZ_RST#
ACZ_SYNC
ACZ_BIT_CLK
ACZ_SDATAOUT
3D3V_S0
CHECK
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_RST#
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_RST#
PCH_JTAG_TCK
When unused all JTAG pins may be NC
5
1 2
R104 10MR2J-L-GPR104 10MR2J-L-GP
X2
X2
4
X-32D768KHZ-34GPU
X-32D768KHZ-34GPU
12
82.30001.661
82.30001.661
1 2
ECT4 SC33P50V2JN-3GP
ECT4 SC33P50V2JN-3GP
DY
DY
1 2
ECT1 SC33P50V2JN-3GP
ECT1 SC33P50V2JN-3GP
DY
DY
1 2
ECT3 SC33P50V2JN-3GP
ECT3 SC33P50V2JN-3GP
DY
DY
1 2
ECT2 SC33P50V2JN-3GP
ECT2 SC33P50V2JN-3GP
DY
DY
NO REBOOT STRAP
1 2
DY
DY
R158 1KR2J-1-GP
R158 1KR2J-1-GP
No Reboot Strap R23
Low = Default
HDA_SPKR
High = No Reboot
-1 0114
1 2
DY
DY
R145 200R2J-L1-GP
R145 200R2J-L1-GP
1 2
DY
DY
R131 200R2J-L1-GP
R131 200R2J-L1-GP
1 2
DY
DY
R149 200R2J-L1-GP
R149 200R2J-L1-GP
1 2
DY
DY
R126 10KR2J-3-GP
R126 10KR2J-3-GP
1 2
DY
DY
R136 100R2J-2-GP
R136 100R2J-2-GP
1 2
DY
DY
R135 100R2J-2-GP
R135 100R2J-2-GP
1 2
DY
DY
R140 100R2J-2-GP
R140 100R2J-2-GP
1 2
DY
DY
R121 51R2F-2-GP
R121 51R2F-2-GP
1 2
R154 51R2F-2-GPR154 51R2F-2-GP
5
1
23
ACZ_SPKR
ICH_RTCX1
ICH_RTCX2
12
C190
C190
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
check 20ppm + 5.6p
1D05V_S0
4
SA 0906
R472
R472
20KR2J-L2-GP
20KR2J-L2-GP
1 2
12
C591
C591
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
RTC_AUX_S5
R471
R471
1 2
20KR2J-L2-GP
20KR2J-L2-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
ACZ_BITCLK_AUDIO27
ACZ_SYNC_AUDIO27
ACZ_SPKR27
ACZ_RST#_AUDIO27
ACZ_SDATAIN027
ACZ_SDATAOUT_AUDIO27
-1 0107
ME_UNLOCK#33
Low: Flash Descriptor Security will be overridden
SPI_CS0#, SPI_MISO, SPI_MOSI, SPI_CLK:
No series resistor required if routing length is 1.5"-6.5"
PCH_SPI_CLK35
PCH_SPI_CS#035
PCH_SPI_MOSI35
SPI_MOSO_R35
Enable iTPM: Connect to Vcc3_3 with
SPI_MOSI
8.2-kΩ weak pull-up resistor.
Disable iTPM: Left floating, no
pull-down required
3D3V_S0
1 2
DY
DY
R204 8K2R2J-3-GP
R204 8K2R2J-3-GP
SPI_MOSI_R
4
RTC_AUX_S5RTC_AUX_S5
21
G77
G77
GAP-OPEN
GAP-OPEN
SRTCRST# new signal Pin
12
C587
C587
R482
R482
1 2
0R0402-PAD
0R0402-PAD
1 2
R481 8K2R2J-3-GP
R481 8K2R2J-3-GP
R206
R206
15R2J-GP
15R2J-GP
R202
R202
15R2J-GP
15R2J-GP
R201
R201
15R2J-GP
15R2J-GP
3
R99 1MR2J-1-GPR99 1MR2J-1-GP
R475 330KR2F-L-GPR475 330KR2F-L-GP
1 2
R96 33R2J-2-GPR96 33R2J-2-GP
1 2
R94 33R2J-2-GPR94 33R2J-2-GP
1 2
R97 33R2J-2-GPR97 33R2J-2-GP
TP98TPAD14-GP TP98TPAD14-GP
R95 33R2J-2-GPR95 33R2J-2-GP
DY
DY
1 2
1 2
1 2
RTC_AUX_S5 RTC_BAT
12
1 2
1
1 2
1 2
R515
R515
0R0603-PAD
0R0603-PAD
C643
C643
SC1U10V2ZY-GP
SC1U10V2ZY-GP
ICH_INTVRMEN
ICH_RTCX1
ICH_RTCX2
ICH_RTCRST#
SRTCRST#
SM_INTRUDER#
ICH_INTVRMEN
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
HDA_SDIN2
ACZ_SDATAOUT
HDA_DOCK_EN#
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#
SPI_CLK_R
SPI_CS#0_R
SPI_MOSI_R
SPI_MOSO_R
RTC_PWR_L
-1 0107
PCH1A
PCH1A
B13
D13
C14
D17
A16
A14
A30
D29
P1
C30
G30
F30
E32
F32
B29
H32
J30
M3
K3
K1
J2
J4
BA2
AV3
AY3
AY1
AV1
IBEXPEAK-M-GP-NF
IBEXPEAK-M-GP-NF
D20
D20
3
BAS40WCGP-GP-U
BAS40WCGP-GP-U
83.00040.R81
83.00040.R81
2ND = 83.BAT54.Z81
2ND = 83.BAT54.Z81
SB 1015 change to 83.00040.Q81
SB 1030 change to 83.00040.R81
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
TRST#
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
3D3V_AUX_S5
2
RTC_PWR
1
RTCIHDA
RTCIHDA
SPI JTAG
SPI JTAG
1 2
R516
R516
1KR2J-1-GP
1KR2J-1-GP
FWH4/LFRAME#
LDRQ1#/GPIO23
LPC
LPC
SATA
SATA
SATAICOMPO
SATAICOMPI
SATA0GP/GPIO21
SATA1GP/GPIO19
SM_INTRUDER#
1 2
3
1 OF 10
1 OF 10
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATALED#
2
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
integrated VccLan1_05VccCL1_05
LAN100_SLP
D33
B33
C32
A32
C34
A34
PCH_GPIO23
F34
INT_SERIRQ
AB9
AK7
AK6
AK11
AK9
AH6
AH5
AH9
AH8
AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
AF15
T3
Y9
V1
SATAICOMP
SATA_LED#
SATA_DET#0_R
SATA_DET#1_R
High=Enable Low=Disable
High=Enable Low=Disable
LPC_LAD0 33,35
LPC_LAD1 33,35
LPC_LAD2 33,35
LPC_LAD3 33,35
LPC_LFRAME# 33,35
SATA_RXN0 28
SATA_RXP0 28
SATA_TXN0 28
SATA_TXP028
SATA_RXN4 28
SATA_RXP4 28
SATA_TXN4 28
SATA_TXP428
1 2
R186
R186
37D4R2F-GP
37D4R2F-GP
INT_SERIRQ
SATA_LED#
SATA_DET#1_R
SATA_DET#0_R
SA-0914
RTC1
RTC1
4
1
2
3
5
ACES-CON3-4-GP-U
ACES-CON3-4-GP-U
20.F1267.003
20.F1267.003
2
1
TP101TPAD14-GPTP101TPAD14-GP
INT_SERIRQ 33
HDD
PCH: 71.0IBEX.G0U
ODD
1D05V_S0
SATA_LED# 34
RN25
RN25
6
7
8
SRN10KJ-6-GP
SRN10KJ-6-GP
3D3V_S0
45
3
2
1
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
14_PCH (1/9)-SATA/SPI/LPC/HDA
14_PCH (1/9)-SATA/SPI/LPC/HDA
14_PCH (1/9)-SATA/SPI/LPC/HDA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
14 58Wednesday, January 27, 2010
14 58Wednesday, January 27, 2010
14 58Wednesday, January 27, 2010
1
A
-1
-1
-1
5
DCCBBAA
4
3
2
1
2 OF 10
PCH1B
LAN
D
MINICARD1
WLAN
MINICARD2
WWAN
NEW CARD
PCIECLKRQ{0,3,4,5,6,7}# should
have a 10K pull-up to +3VALW.
PCIECLKRQ{1,2} should have a
10K pull-up to +1.05VS (But CRB is
pull-up to +3VS).
PCIE_RXN129
PCIE_RXP129
PCIE_TXN129
PCIE_TXP129
PCIE_RXN231
PCIE_RXP231
PCIE_TXN231
PCIE_TXP231
PCIE_RXN331
PCIE_RXP331
PCIE_TXN331
PCIE_TXP331
PCIE_RXN431
PCIE_RXP431
PCIE_TXN431
PCIE_TXP431
CHECK
CLK_PCIE_MINI1#31
CLK_PCIE_MINI131
MINI1_CLKREQ#31
CLK_PCIE_MINI2#31
CLK_PCIE_MINI231
MIN2_CLKREQ#31
CLK_PCIE_LAN#29
CLK_PCIE_LAN29
LAN_CLKREQ#29
CLK_PCIE_NEW#31
CLK_PCIE_NEW31
NEW_CLKREQ#31
PCIE_RXN1
PCIE_RXP1
PCIE_RXN2
PCIE_RXP2
C328 SCD1U10V2KX-5GPC328 SCD1U10V2KX-5GP
C327 SCD1U10V2KX-5GPC327 SCD1U10V2KX-5GP
C326 SCD1U10V2KX-5GPC326 SCD1U10V2KX-5GP
C325 SCD1U10V2KX-5GPC325 SCD1U10V2KX-5GP
1 2
R172 0R0402-PADR172 0R0402-PAD
1 2
R148 0R0402-PADR148 0R0402-PAD
1 2
R113 0R0402-PADR113 0R0402-PAD
1 2
R122 0R0402-PADR122 0R0402-PAD
TXN1
C321SCD1U10V2KX-5GP C321SCD1U10V2KX-5GP
12
TXP1
C322SCD1U10V2KX-5GP C322SCD1U10V2KX-5GP
12
TXN2
C324SCD1U10V2KX-5GP C324SCD1U10V2KX-5GP
12
TXP2
C323SCD1U10V2KX-5GP C323SCD1U10V2KX-5GP
12
TXN3
12
TXP3
12
TXN4
12
TXP4
12
PCIE_CLK_RQ0#
PCIE_CLK_RQ1#
PCIE_CLK_RQ2#
PCIE_CLK_RQ3#
PCIE_CLK_RQ4#
-1 0111
PCIE_CLK_RQ5#
PEG_B_CLKRQ#
CHECK
3D3V_S03D3V_S5 3D3V_S0
PCH1B
BG30
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0#/GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1#/GPIO18
AM47
CLKOUT_PCIE2N
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2#/GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3#/GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4#/GPIO26
AJ50
CLKOUT_PCIE5N
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5#/GPIO44
AK53
CLKOUT_PEG_B_N
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ#/GPIO56
IBEXPEAK-M-GP-NF
IBEXPEAK-M-GP-NF
SMBus
SMBus
PCI-E*
PCI-E*
Link
Link
Controller
Controller
PEG
PEG
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P
From CLK BUFFER
From CLK BUFFER
CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P
Clock Flex
Clock Flex
2 OF 10
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1ALERT#/GPIO74
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
B9
H14
C8
J14
C6
G8
M14
E10
G12
T13
T11
T9
H1
AD43
AD45
AN4
AN2
AT1
AT3
AW24
BA24
AP3
AP1
F18
E18
AH13
AH12
P41
J42
AH51
AH53
AF38
T45
P43
T42
N50
SMB_CLK
SMB_DATA
SML0_CLK
SML0_DATA
PCH_GPIO74
KBC_SCL1
KBC_SDA1
CL_CLK
1
CL_DATA
1
CL_RST#
1
PEG_CLKREQ#PEG_CLKREQ#
R124 0R2J-2-GP
R124 0R2J-2-GP
CLK_PCH_PEGA_N
CLK_PCH_PEGA_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI#
CLKIN_DMI
CLK_CPU_BCLK#
CLK_CPU_BCLK
DREFCLK#
DREFCLK
CLK_PCIE_SATA#
CLK_PCIE_SATA
CLK_ICH14
CLK_PCI_FB
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
PCH_FLEX0
1
PCH_FLEX1
1
PCH_FLEX2
1
CLK48
PCH_GPIO11 19
SMB_CLK31
SMB_DATA31
PCH_GPIO60 19
TP45 TPAD14-GPTP45 TPAD14-GP
TP43 TPAD14-GPTP43 TPAD14-GP
TP40 TPAD14-GPTP40 TPAD14-GP
1 2
DY
DY
DIS
DIS
2 3
1
4
DY
DY
CLKIN_DMI# 3
CLKIN_DMI 3
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
DREFCLK# 3
DREFCLK 3
CLK_PCIE_SATA# 3
CLK_PCIE_SATA 3
CLK_ICH14 3
CLK_PCI_FB 18
1 2
R229 90D9R2F-1-GPR229 90D9R2F-1-GP
TP107TPAD14-GPTP107TPAD14-GP
TP108TPAD14-GPTP108TPAD14-GP
TP109TPAD14-GPTP109TPAD14-GP
1 2
R15533R2J-2-GP R15533R2J-2-GP
PU, page 19
PU, page 19
RN27
RN27
SRN0J-10-GP-U
SRN0J-10-GP-U
4
-1 0111
1
RN36
RN36
23
SRN0J-10-GP-U
SRN0J-10-GP-U
12
C207
C207
DY
DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
IO
PEX_CLKREQ 51
1D05V_S0
CLK48_Cardreader 31
KBC_SCL1 33
KBC_SDA1 33
CLK_PCIE_PEG# 51
CLK_PCIE_PEG 51
PEG_CLK#_R 5
PEG_CLK_R 5
DPLL_REF_SSCLK# 5
DPLL_REF_SSCLK 5
SML0_DATA
3D3V_S5
PCH_SMBDATA3,12,13
PCH_GPIO1219
SML0_CLK
SMB_CLK
SMB_DATA
SMB_CLK
CHECK
SA 0908
XTAL-25MHZ-102-GP
XTAL-25MHZ-102-GP
82.30020.851
82.30020.851
2nd = 82.30020.791
2nd = 82.30020.791
3D3V_S5
678
RN70
RN70
SRN2K2J-4-GP
SRN2K2J-4-GP
123
4 5
KBC_SDA1
KBC_SCL1
3D3V_S0
678
RN62
RN62
SRN2K2J-4-GP
SRN2K2J-4-GP
123
4 5
Q7
Q7
1
6
2
5
3 4
DMN66D0LDW-7-GP
DMN66D0LDW-7-GP
84.DMN66.03F
84.DMN66.03F
2ND = 84.27002.F3F
2ND = 84.27002.F3F
SB 1015 change to 84.DMN66.03F
PEG_CLKREQ#
PCIE_CLK_RQ0#
PCH_GPIO74
XTAL25_IN
XTAL25_IN
XTAL25_OUT
1 2
R127 10KR2J-3-GPR127 10KR2J-3-GP
RN23
RN23
1
2
3
4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
ASM if external crystal is not used.
1 2
R187 0R2J-2-GPR187 0R2J-2-GP
X3
X3
12
DY
DY
C227
C227
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
C219
C219
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
3D3V_S0
SMB_DATA
PCH_SMBCLK 3,12,13
3D3V_S5
8
7
6
DY
DY
12
DY
DY
12
R112
R112
10KR2J-3-GP
10KR2J-3-GP
1 2
PCIE_CLK_RQ3#
R114
R114
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
5
R168
R168
10KR2J-3-GP
10KR2J-3-GP
1 2
PCIE_CLK_RQ1#
12
R165
R165
10KR2J-3-GP
10KR2J-3-GP
DY
DY
R153
R153
10KR2J-3-GP
10KR2J-3-GP
1 2
PCIE_CLK_RQ2#
12
R157
R157
10KR2J-3-GP
10KR2J-3-GP
DY
DY
3D3V_S5
4
RN72
RN72
1
2
3
4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
8
7
6
PEG_B_CLKRQ#
PCIE_CLK_RQ4#
PCIE_CLK_RQ5#
PCH_GPIO57
PCH_GPIO57 19
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
15_PCH (2/9)-PCIE / SMBUS / CLK
15_PCH (2/9)-PCIE / SMBUS / CLK
15_PCH (2/9)-PCIE / SMBUS / CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
3
2
Taipei Hsien 221, Taiwan, R.O.C
1
-1
-1
15 58Tuesday, January 26, 2010
15 58Tuesday, January 26, 2010
15 58Tuesday, January 26, 2010
-1
D D
A
C C
B B
SA 0906
5
DMI_RXN04
DMI_RXN14
DMI_RXN24
DMI_RXN34
DMI_RXP04
DMI_RXP14
DMI_RXP24
DMI_RXP34
DMI_TXN04
DMI_TXN14
DMI_TXN24
DMI_TXN34
DMI_TXP04
DMI_TXP14
DMI_TXP24
DMI_TXP34
1D05V_S0
1 2
R219 49D9R2F-GPR219 49D9R2F-GP
R102 0R2J-2-GP
R102 0R2J-2-GP
1 2
DY
PM_PWROK36
CORE_PWRGD36,38
PM_DRAM_PWRGD5
DY
1 2
R103 0R0402-PADR103 0R0402-PAD
1 2
R116 10KR2J-3-GPR116 10KR2J-3-GP
SC 1203
SUS_PWR_DN_ACK33
PM_PWRBTN#33
AC_PRESENT33
1 2
R159 0R0402-PADR159 0R0402-PAD
1 2
R169 0R0402-PADR169 0R0402-PAD
1 2
R166 0R0402-PADR166 0R0402-PAD
DMI_IRCOMP_R
PM_PWROK_1
1 2
R139 0R0402-PADR139 0R0402-PAD
1 2
R485 10KR2J-3-GPR485 10KR2J-3-GP
4
3D3V_S0
12
R173
R173
10KR2J-3-GP
10KR2J-3-GP
PM_SYSRST#_R
-1 0107-1 0107
ME_PWROK
LAN_RST#1
PM_RSMRST#
SUS_PWR_DN_ACK_R
PM_PWRBTN#_R
AC_PRESENT_R
PCH_GPIO72
PM_RI#
PCH1C
PCH1C
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_DN_ACK/GPIO30
P5
PWRBTN#
P7
ACPRESENT/GPIO31
A6
BATLOW#/GPIO72
F14
RI#
IBEXPEAK-M-GP-NF
IBEXPEAK-M-GP-NF
3
3 OF 10
3 OF 10
BA18
FDI_RXN0
BH17
FDI_RXN1
BD16
FDI_RXN2
BJ16
FDI_RXN3
BA16
FDI_RXN4
BE14
FDI_RXN5
BA14
FDI_RXN6
BC12
FDI_RXN7
BB18
FDI_RXP0
BF17
FDI_RXP1
BC16
FDI_RXP2
BG16
FDI_RXP3
AW16
FDI_RXP4
BD14
FDI_RXP5
BB14
FDI_RXP6
BD12
FDI_RXP7
BJ14
FDI_INT
WAKE#
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH
BF13
BH13
BJ12
BG14
J12
Y1
P8
F3
E4
H7
P12
K8
N2
BJ10
F6
PCIE_WAKE#
PM_CLKRUN#
PM_SUS_STAT#
PM_SUS_CLK
PM_SLP_S5#
PM_SLP_S4#_R
PM_SLP_S3#_R
PM_SLP_M#_R
PM_SLP_DSW#
H_PM_SYNC
PM_SLP_LAN#
FDI_FSYNC0
DMI
FDI
DMI
FDI
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
System Power Management
System Power Management
SLP_LAN#/GPIO29
FDI_TXN04
FDI_TXN14
FDI_TXN24
FDI_TXN34
FDI_TXN44
FDI_TXN54
FDI_TXN64
FDI_TXN74
FDI_TXP04
FDI_TXP14
FDI_TXP24
FDI_TXP34
FDI_TXP44
FDI_TXP54
FDI_TXP64
FDI_TXP74
FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4
1
TP42 TPAD14-GPTP42 TPAD14-GP
1
TP28 TPAD14-GPTP28 TPAD14-GP
1
TP97 TPAD14-GPTP97 TPAD14-GP
1 2
R129 0R0402-PADR129 0R0402-PAD
1 2
R137 0R0402-PADR137 0R0402-PAD
1
TP102TPAD14-GPTP102TPAD14-GP
1
TP30 TPAD14-GPTP30 TPAD14-GP
1
TP96 TPAD14-GPTP96 TPAD14-GP
PCIE_WAKE# 29,31
PM_CLKRUN# 33
2
PM_SLP_S4#31,33,36,41,43
PM_SLP_S3#5,31,33,36,41,42,43,44
-1 0107
H_PM_SYNC 5
1
RN24
PM_RI#
SUS_PWR_DN_ACK_R
AC_PRESENT_R
3D3V_AUX_S5
3D3V_S5
83.00054.T81
83.00054.T81
2ND = 83.00054.Z81
2ND = 83.00054.Z81
D16
RSMRST#_KBC33
1 2
R601
R601
0R0402-PAD
0R0402-PAD
RSMRST#_KBC_R
D16
3
BAT54PT-GP
BAT54PT-GP
1
2
12
R100
R100
10KR2J-3-GP
10KR2J-3-GP
PM_RSMRST#
12
R101
R101
100KR2J-1-GP
100KR2J-1-GP
10KR2J-3-GP
10KR2J-3-GP
-1 0107
R646
R646
12
DY
DY
DMN66D0LDW-7-GP
DMN66D0LDW-7-GP
84.DMN66.03F
84.DMN66.03F
2ND = 84.27002.F3F
2ND = 84.27002.F3F
12
R647
R647
100KR2J-1-GP
DY
DY
34
2
1
100KR2J-1-GP
PM_RSMRST#
Q64
Q64
5
6
DY
DY
SC 1209
PWM_RSMRST#40
High Active
PM_PWRBTN#_R
PCH_GPIO72
PCIE_WAKE#
PM_CLKRUN#
RN24
1
2
3
4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
1 2
R111 8K2R2J-3-GPR111 8K2R2J-3-GP
1 2
R133 1KR2J-1-GPR133 1KR2J-1-GP
1 2
R174
R174
8K2R2J-3-GP
8K2R2J-3-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
16_PCH (3/9)-DMI / FDI / PM
16_PCH (3/9)-DMI / FDI / PM
16_PCH (3/9)-DMI / FDI / PM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
3D3V_S5
8
7
6
3D3V_S5
3D3V_S0
A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
-1
-1
-1
16 58Tuesday, January 26, 2010
16 58Tuesday, January 26, 2010
16 58Tuesday, January 26, 2010
5
A
4
3
2
1
SA 0908 Add
3D3V_S0
RN26
RN26
PCH_HDMI_CLK
PCH_HDMI_DATA
4
CLK_DDC_EDID
DAT_DDC_EDID
4
LCTL_CLK
4
LCTL_DATA
LIBG
12
PCH_HDMI_DETECT
PCH_DDCCLK
PCH_DDCDATA
4
PCH_BLUE
1
PCH_GREEN
2
PCH_RED
3
45
Reserve PD at SW
PCH_BL_ON23
PCH_LCDVDD_ON24
L_BKLTCTL24
CLK_DDC_EDID23
DAT_DDC_EDID23
TP44TPAD14-GP TP44TPAD14-GP
R196
R196
0R0402-PAD
0R0402-PAD
PCH_TXACLK-23
PCH_TXACLK+23
PCH_TXAOUT0-23
PCH_TXAOUT1-23
PCH_TXAOUT2-23
PCH_TXAOUT0+23
PCH_TXAOUT1+23
PCH_TXAOUT2+23
PCH_BLUE23
PCH_GREEN23
PCH_RED23
PCH_DDCCLK25
PCH_DDCDATA25
PCH_HSYNC25
PCH_VSYNC25
1 2
R177
R177
1KR2D-1-GP
1KR2D-1-GP
Intel check list recommend use 1K 0.5%
1K 0.5% ohm
1
12
CLK_DDC_EDID
DAT_DDC_EDID
LCTL_CLK
LCTL_DATA
LIBG
L_LVBG
LVDS_VREF
PCH_BLUE
PCH_GREEN
PCH_RED
PCH_DDCCLK
PCH_DDCDATA
CRT_IREF
PCH1D
PCH1D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IBEXPEAK-M-GP-NF
IBEXPEAK-M-GP-NF
4 OF 10
4 OF 10
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ46
BG46
BJ48
BG48
BF45
BH45
T51
T53
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
U50
U52
BC46
BD46
AT38
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
CRT
CRT
PCH_HDMI_CLK
PCH_HDMI_DATA
PCH_HDMI_DETECT
PCH_HDMI_DATA2-_L
PCH_HDMI_DATA2+_L
PCH_HDMI_DATA1-_L
PCH_HDMI_DATA1+_L
PCH_HDMI_DATA0-_L
PCH_HDMI_DATA0+_L
PCH_HDMI_CLK-_L
PCH_HDMI_CLK+_L
PCH_HDMI_CLK 26
PCH_HDMI_DATA 26
1 2
UMA
UMA
C288 SCD1U10V2KX-5GP
C288 SCD1U10V2KX-5GP
1 2
UMA
UMA
C289 SCD1U10V2KX-5GP
C289 SCD1U10V2KX-5GP
1 2
UMA
UMA
C286 SCD1U10V2KX-5GP
C286 SCD1U10V2KX-5GP
1 2
UMA
UMA
C287 SCD1U10V2KX-5GP
C287 SCD1U10V2KX-5GP
1 2
UMA
UMA
C284 SCD1U10V2KX-5GP
C284 SCD1U10V2KX-5GP
1 2
UMA
UMA
C285 SCD1U10V2KX-5GP
C285 SCD1U10V2KX-5GP
1 2
UMA
UMA
C283 SCD1U10V2KX-5GP
C283 SCD1U10V2KX-5GP
1 2
UMA
UMA
C282 SCD1U10V2KX-5GP
C282 SCD1U10V2KX-5GP
PCH_HDMI_DETECT 26
PCH_HDMI_DATA2- 26
PCH_HDMI_DATA2+ 26
PCH_HDMI_DATA1- 26
PCH_HDMI_DATA1+ 26
PCH_HDMI_DATA0- 26
PCH_HDMI_DATA0+ 26
PCH_HDMI_CLK- 26
PCH_HDMI_CLK+ 26
2 3
1
RN22
RN22
UMA
UMA
SRN2K2J-1-GP
SRN2K2J-1-GP
D D
SA 0904 Add
3D3V_S0
2 3
1
RN67
RN67
SRN2K2J-1-GP
SRN2K2J-1-GP
3D3V_S0
1
2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
R195
R195
2K37R2F-GP
2K37R2F-GP
LVDS reference current.
SA 0908 Add
C C
1 2
R191
R191
100KR2J-1-GP
100KR2J-1-GP
SA 0904 Add
3D3V_S0
RN66
RN66
2 3
1
SRN2K2J-1-GP
SRN2K2J-1-GP
RN29
RN29
8
7
6
SRN150F-1-GP
SRN150F-1-GP
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
17_PCH (4/9)-LVDS / CRT
17_PCH (4/9)-LVDS / CRT
17_PCH (4/9)-LVDS / CRT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
17 58Tuesday, January 26, 2010
17 58Tuesday, January 26, 2010
17 58Tuesday, January 26, 2010
A
-1
-1
-1
5
DCCBBAA
RN63
1 2
1 2
1 2
RN65
RN65
1
2
3
4 5
1 2
DY
DY
1 2
DY
DY
RN63
1
2
3
4
5 6
SRN8K2J-2-GP-U
SRN8K2J-2-GP-U
INT_PIRQA#
8
INT_PIRQC#
7
INT_PIRQE#
6
PCI_SERR#
R118
R118
1KR2J-1-GP
1KR2J-1-GP
R150
R150
1KR2J-1-GP
1KR2J-1-GP
PCI_TRDY#
PCI_PLOCK#
PCI_DEVSEL#
D
INT_PIRQG#
3D3V_S0
3D3V_S0
R134 8K2R2J-3-GPR134 8K2R2J-3-GP
R141 8K2R2J-3-GPR141 8K2R2J-3-GP
3D3V_S0
R138 8K2R2J-3-GPR138 8K2R2J-3-GP
3D3V_S0
SRN8K2J-4-GP
SRN8K2J-4-GP
PCI_GNT0#
PCI_GNT1#
10
9
8
PCI_IRDY#
7
INT_PIRQB#
PCI_REQ3#
INT_PIRQF#
3D3V_S0
PCI_STOP#
INT_PIRQD#
PCI_FRAME#
3D3V_S0
dGPU_PWM_SELECT#24
These pins are left as NC,
because the function is disable.
RN73
RN73
1
8
2
7
3
6
4 5
SRN8K2J-4-GP
SRN8K2J-4-GP
SB 1015 R105 change to ASM
dGPU_SELECT#23,24,25
3D3V_S0
BOOT BIOS Strap
PCI_GNT#1 BOOT BIOS LocationPCI_GNT#0
0 0 LPC(Default)
01 Reserved
0 1
PCI
11
SPI
R151 22R2J-2-GPR151 22R2J-2-GP
1 2
R160 22R2J-2-GPR160 22R2J-2-GP
1 2
R161 22R2J-2-GPR161 22R2J-2-GP
1 2
3D3V_S5
5
VCC
4
Y
1 2
PCI_PLTRST#
PCLK_FWH35
CLK_PCI_FB15
CLK_PCI_KBC33
U59
U59
1
B
2
A
3
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
DY
DY
R483 0R2J-2-GPR483 0R2J-2-GP
5
PCI_REQ0#
PCI_PERR#
INT_PIRQH#
PCI_REQ1#
-1 0114
R105
R105
8K2R2J-3-GP
8K2R2J-3-GP
1 2
dGPU_SELECT#
dGPU_PWM_SELECT#
TP39TPAD14-GP TP39TPAD14-GP
TP32TPAD14-GP TP32TPAD14-GP
TP29TPAD14-GP TP29TPAD14-GP
12
C197
C197
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
12
R490
R490
100KR2J-1-GP
100KR2J-1-GP
4
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_GNT0#
PCI_GNT1#
PCI_GNT3#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
PCI_SERR#
PCI_PERR#
PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#
PCI_PLOCK#
PCI_STOP#
PCI_TRDY#
ICH_PME#
1
PCI_PLTRST#
CLK_PCI_SIO_R
CLK_PCI_FB_R
CLK_PCI_KBC_R
CLK_PCI_3
1
CLK_PCI_4
1
PLT_RST#5,29,31,33,35,51
4
PCH1E
PCH1E
H40
AD0
N34
AD1
C44
AD2
A38
AD3
C36
AD4
J34
AD5
A40
AD6
D45
AD7
E36
AD8
H48
AD9
E40
AD10
C40
AD11
M48
AD12
M45
AD13
F53
AD14
M40
AD15
M43
AD16
J36
AD17
K48
AD18
F40
AD19
C42
AD20
K46
AD21
M51
AD22
J52
AD23
K51
AD24
L34
AD25
F42
AD26
J40
AD27
G46
AD28
F44
AD29
M47
AD30
H36
AD31
J50
C/BE0#
G42
C/BE1#
H47
C/BE2#
G34
C/BE3#
G38
PIRQA#
H51
PIRQB#
B37
PIRQC#
A44
PIRQD#
F51
REQ0#
A46
REQ1#/GPIO50
B45
REQ2#/GPIO52
M53
REQ3#/GPIO54
F48
GNT0#
K45
GNT1#/GPIO51
F36
GNT2#/GPIO53
H53
GNT3#/GPIO55
B41
PIRQE#/GPIO2
K53
PIRQF#/GPIO3
A36
PIRQG#/GPIO4
A48
PIRQH#/GPIO5
K6
PCIRST#
E44
SERR#
E50
PERR#
A42
IRDY#
H44
PAR
F46
DEVSEL#
C46
FRAME#
D49
PLOCK#
D41
STOP#
C48
TRDY#
M7
PME#
D5
PLTRST#
N52
CLKOUT_PCI0
P53
CLKOUT_PCI1
P46
CLKOUT_PCI2
P51
CLKOUT_PCI3
P48
CLKOUT_PCI4
IBEXPEAK-M-GP-NF
IBEXPEAK-M-GP-NF
5 OF 10
5 OF 10
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1
NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NVRAM
NVRAM
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15
NV_ALE
NV_CLE
NV_RCOMP
PCI
PCI
NV_RB#
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USB
USB
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
PCI_GNT3#
1 2
R123 4K7R2J-2-GP
R123 4K7R2J-2-GP
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3 Low = A16 swap
3
AY9
BD1
AP15
BD8
AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
These pins are left as NC,
BE4
because the function is disable.
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
NV_ALE
BD3
NV_CLE
AY6
NV_RCOMP
AU2
AV7
AY8
AY5
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
B25
D25
N16
J16
F16
L16
E14
G16
F12
T15
DY
DY
override/Top-Block
Swap Override enabled
High = Default
R197
R197
32D4R2F-GP
32D4R2F-GP
USB_RBIAS_PN
USB_OC#3
USB_OC#3
1 2
R115
R115
20R2F-GP
20R2F-GP
3
DY
DY
1 2
USB_OC#0 32
USB_OC#1 32
USB_OC#4 32
2
DMI Termination Voltage
NV_CLE Set to Vss when low.
USBPN1 32
USBPP132
USBPN2 32
USBPP232
USBPN3 31
USBPP331
USBPN4 31
USBPP431
USBPN5 31
USBPP531
USBPN8 32
USBPP832
USBPN9 32
USBPP932
USBPN10 35
USBPP1035
USBPN12 31
USBPP1231
USBPN13 24
USBPP1324
Set to Vcc when high.
Danbury Technology:
Disabled when Low.
Enable when High.
1KR2J-1-GP
1KR2J-1-GP
NV_CLE
NV_ALE
Pair
Device
0
NC
USB3
1
USB1
2
3
WLAN
4 Card Reader
WWAN
5
Disable (HM55)
6
7
Disable (HM55)
89USB2
Blue Tooth
10
Finger Print
11
NC
1213Express Card
Camera
SC 1208, BOM Change to 20ohm for fine tune USB signal
3D3V_S5
RN68
USB_OC#4
USB_OC#1
USB_OC#3
USB_OC#0
RN68
8
7
6
SRN10KJ-6-GP
SRN10KJ-6-GP
1
2
3
45
OC#0 Port 0 & 1
OC#1 Port 2 & 3
OC#2 Port 4 & 5
EHCI 1
OC#3 Port 6 & 7
OC#4 Port 8 & 9
OC#5 Port 10 & 11
OC#6 Port 12 & 13
EHCI 2
OC#7 Floater OC# (not used)
2
+V_NVRAM_VCCQ
12
R210
R210
DY
DY
+V_NVRAM_VCCQ
12
R214
R214
1KR2J-1-GP
1KR2J-1-GP
DY
DY
1
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
18_PCH (5/9)-PCI / USB
18_PCH (5/9)-PCI / USB
18_PCH (5/9)-PCI / USB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA46 MB DIS
LA46 MB DIS
LA46 MB DIS
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C
18 58Tuesday, January 26, 2010
18 58Tuesday, January 26, 2010
18 58Tuesday, January 26, 2010
1
-1
-1
-1
Loading...