Lenovo LA-8952P VIUS3, IdeaPad S300, IdeaPad S400, LA-8952P VIUS4 Schematic

A

B

C

D

E

Compal Confidential

Model Name : VIUS3/S4

le Name : LA-8952PR01

1 1

Fi
BOM P/N:43

Compal Confidential

2 2

VIUS3/S4 M/B Schematics Document

Intel Ivy Bridge ULV Processor + Panther Point PCH

AMD Seymour XT

3 3

2013-01-07

REV:0.1

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-8952P

LA-8952P

LA-8952P

0.1

0.1

1 55Thursday, January 10, 2013

1 55Thursday, January 10, 2013

E

1 55Thursday, January 10, 2013

0.1

A

Compal confidential

File Name :VIUS3/VIUS4

B

C

D

E

Chief River

AMD Seymour XT

1 1

23mm *23mm

VRAM 128MB*16

gDDR3*4

PCI-E X16

Gen 2

UP TO 1G

IVY Bridge SV/ULV

Intel

(Sandy Bridge)

Processor

BGA1023

R3-SO-DIMM X1

DD

BANK 0, 1

Dua

l Channel

DDR3-1066/1333(1.5V) for Sandy Bridge
DDR3-1600(1.5V) for Ivy Bridge

SATA3.0 HDD CONN

FDI *8

Std HDMI

HDMI 1.4a

100MHz

2.7GT/s

Connector

2 2

LVDS
Connector

PCI Express (Half)
Mini card Slot 1

WLAN/WiMAX

PCI Express (Full)
Mi

ni card Slot 2

SSD

PX 5.0

USB(WiMAX)

PCI-E(WLAN)

mSATA(SSD)

Gen 2

6*PCI-E x1

SPI ROM

Intel
Pan

ther Point

HM77/HM70

FCBGA 989 Balls

25mm*25mm

LPC BUS

BIOS

3 3

LA

WLAN/WiMAX

N(10/100/Giga)

Realtek
81

05E-VD (10/100)

8111F-VL (Giga)

4MB*1
2MB*1

EC

ENE KB9012

Touch Pad

RJ45 CONN

Su

b-borad

4 4

POWER BOARD

ermal Sensor

Th

EMC1403

DMI2 *4

100MHz
5GT/s

6*SATA

(port0,1 Support SATA3)

4*USB3.0

14*USB2.0

HD Audio

Int.KBD

SATA3.0 HDD (SSD)

USB PORT 3.0 x1 (Left)

US

B PORT 2.0 x2 (Right)

Card Reader RTS 5178 (2in1)

CMO

S Camera

BlueTooth CONN

WLAN/WiMAX

WWAN
Touch Screen

Audio Codec

RealTek

C259-VC2

AL

Board

IO

IO Board

2Channel Speaker

Single Digital MIC

Audio Combo Jack
(APPLE type)

HeadPhone Output
Microphone Input

Board

IO

LED BOARD

oard

IO B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/07/21 2012/12/31

2011/07/21 2012/12/31

2011/07/21 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

MB Block Diagram

MB Block Diagram

2 55Thursday, January 10, 2013

2 55Thursday, January 10, 2013

2 55Thursday, January 10, 2013

E

0.1

0.1

0.1

A

Voltage Rails

power

State

S0

S3

S5 S4/AC

Device

Smart Battery

plane

Address

0001 011X b

+B

O

O

O

O

X

+5VALW

+3VALW

O

O

O

X

X X X

+1.5V

+1.5V_IO

EC SM Bus2 address

Device

Thermal Sen sor F75303M

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

EC SM Bus1 address

PCH SM Bus address

Device Address

DDR DIMM0

3 3

DDR DIMM2

1001 000Xb

1001 010Xb

AMD-GPU SM Bus address

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

SMBUS Control Table

X

X
X

V

+3VS

SODIMM

X
X

V

+3VS

X

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

4 4

SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012

X V

+3VALW

X
X
X

V

+3VS

A

X
X
X

B

+5VS

+3VS

+1.5VS

+1.05VS_VTT

+CPU_CORE

+VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

O

X X

X

Address

1001_101xb

X
XX

V

+3VS

Thermal
Sensor

X
X
X

WLAN
WWAN

XX

X

V

+3VS

B

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

D

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

ON

ON

E

ONONON ON

ON

OFF

OFF

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0

PCB Revision

0.1

1
2
3
4

OO

5
6
7

X

USB Port Table

X

USB 3.0

xHCI1
xHCI2
xHCI3
xHCI4

HM70 Disable xHCI3,xHCI4

USB 2.0 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

SATA Port Table

SATA P0
SATA P1

PCH

X

V

+3VS

SATA P2
SATA P3
SATA P4
SATA P5

HM70 Disable P1,P3

X

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

3 External
USB Port

0
1
2
3
4
5
6
7
8

9
10
11
12
13

USB 3.0 Port (Left Side)
Mini Card(WLAN)
Touch Panel

X (USB PORT disabled on HM70 )

X (USB PORT disabled on HM70 )

X (USB PORT disabled on HM70 )

X (USB PORT disabled on HM70 )

USB/B (Right Side USB-BD)

USB/B (Right Side USB-BD)

USB Port (Right Side CR-BD)

Camera (LVDS)

X (USB PORT disabled on HM70 )

X (USB PORT disabled on HM70 )

HM77

GEN3/2/1

GEN2/1

GEN2/1

GEN2/1

GEN2/1

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V

1.935 V

2.500 V

12/12/24

HM70

GEN3/2/1

DisableGEN3/2/1

GEN2/1

Disable

GEN2/1

GEN2/1

SSD

HDD (HM77)

HDD (HM70)

V typ

AD_BID

V

AD_BID

max

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.759 V

2.200 V

3.300 V

2.341 V

3.300 V

BOM Structure Table

BTO Item BOM Structure

INTEL UMA only UMA@

PX@ GPU:Seymour XT

HDMI HDMI@
HDD1 (HM77 SATA 3.0) HDD1@
HDD2 (HM70 SATA 2.0) HDD2@
Intel-USB3.0 USB3@

PCH HM77@
PCH HM70@

HM77@

HM70@

10/100 LAN 8105@
GIGA LAN 8111@
AOAC
CMOS
Deep S3
mSATA SSD

AOAC@

CMOS@

DS3@

mSATA@

Connector ME@
45 LEVEL 45@
Unpop

@

PCIe Port Table

HM77

PCIe P1
PCIe P2
PCIe P3
PCIe P4
PCIe P5
PCIe P6
PCIe P7
PCIe P8

Enable

Enable

Enable

Enable

Enable

Enable

Enable

Enable

HM70 Disable P5,P6,P7,P8

HM70

Enable

Enable

Enable

Enable

Disable

Disable

able

Dis

Disable

Porject Phase

G-series

G-series

G-series

G-series

Y-series

Y-series

Y-series

Y-series

LAN

WLAN

MP
PVT
DVT
EVT
EVT
DVT
PVT
MP

X

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

XX X

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

2011/06/15 2012/07/11

2011/06/15 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

LA-8952P

LA-8952P

LA-8952P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

3 55Thursday, January 10, 2013

3 55Thursday, January 10, 2013

3 55Thursday, January 10, 2013

E

0.1

0.1

0.1

5

4

3

2

1

Power-Up/Down Sequence

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up

D D

sequence, though a shorter ramp-up duration is preferred.

2. VDDR3 should ramp-up before or simultaneously with

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.

5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)

VDDR3(3.3VGS)

VDDC.

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC(1.0V)

VDDR1(1.5VGS)

C C

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

Without BACO option :

PXS_RST# : Low -> Reset dGPU ; High ->Normal operation
PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON

BACO option :

PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode)
PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

dGPU Power Pins Max current

DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and
SPV10

PCIE_VDDC

VDDR3 , and A2VDD

BIF_VDDC (current consumption = 55mA@1.0V, in
BACO mode)
BIF_VDDC=VGA_CORE When GPU enable
BIF_VDDC=1.0V When BACO

VDDR1

VDDC/VDDCI

iGPU

PXS_RST#

dGPU

Voltage

1.8V

1.0V

1.0V

3.3V

Same as
VDDC

1.5V

1.12V

PX 3.0

OFF

OFF

OFF

OFF

OFF

OFF

OFF

BACO Mode

ON

ON

ON

ON

ON
Same as
PCIE_VDDC

OFF

OFF

1679mAPCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,

575mA

2A

190mA

70mA

2.8A

12.9A

PERSTb

PXS_PWREN

REFCLK

Straps Reset

+3.3VALW

Straps Valid

B B

Global ASIC Reset

T4+16clock

+1.0V

+1.8V

MOS

Regulator

SI4800

+3.3VGS

1

+1.0VGS

2

+1.8VGS

5

part

CPU

UCPU1

CPU1@

UCPU1

CPU1@

UCPU1

UCPU1

I3_3217 1.8G

I3_3217 1.8G

SA00005L5D0

SA00005L5D0

UCPU1

CPU7@

UCPU1

CPU7@

I5_2467M 1.6G

I5_2467M 1.6G

SA00004X000

SA00004X000

A A

I5_3427 1.8G

I5_3427 1.8G

SA00005L950

SA00005L950

UCPU1

UCPU1

I3_2367M 1.4G

I3_2367M 1.4G

SA000051H70

SA000051H70

5

CPU2@

CPU2@

CPU8@

CPU8@

UCPU1

UCPU1

I5_2557 1.4G

I5_2557 1.4G

SA00004VZ50

SA00004VZ50

UCPU1

UCPU1

I3_2357M 1.3G

I3_2357M 1.3G

SA00004QZ20

SA00004QZ20

CPU3@

CPU3@

CPU9@

CPU9@

UCPU1

UCPU1

977_1.4G

977_1.4G

SA00005BJ40

SA00005BJ40

UCPU1

UCPU1

967_1.3G

967_1.3G

SA000051J20

SA000051J20

UCPU1

CPU4@

CPU4@

CPU10@

CPU10@

UCPU1

SA00005K6E0

SA00005K6E0

UCPU1

UCPU1

SA00004AY20

SA00004AY20

PCH part

U13

HM70@

U13

HM70@

PCH_HM70

PCH_HM70

SA00005MQ80

SA00005MQ80

CPU5@

CPU5@

I5_3317U 1.7G

I5_3317U 1.7G

CPU11@

CPU11@

957_1.2G

957_1.2G

4

UCPU1

UCPU1

I5_2537 1.4G

I5_2537 1.4G

SA00004H910

SA00004H910

UCPU1

UCPU1

I7-3667U 2G

I7-3667U 2G

SA00005LAD0

SA00005LAD0

CPU6@

CPU6@

CPU12@

CPU12@

UCPU1

CPU13@

UCPU1

CPU13@

987 1.4G

987 1.4G

SA00005QH30

SA00005QH30

UCPU1

CPU14@

UCPU1

CPU14@

I3-2377M 1.5G

I3-2377M 1.5G

SA00005MX80

SA00005MX80

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

UCPU1

CPU15@

UCPU1

CPU15@

I7-3517U

I7-3517U

SA00005K5C0

SA00005K5C0

UCPU1

CPU16@

UCPU1

CPU16@

I3-2365M

I3-2365M

SA00005UH10

SA00005UH10

2011/06/15 2012/07/11

2011/06/15 2012/07/11

2011/06/15 2012/07/11

3

PCB part

ZZZ5

ZZZ5

PCB 0R LA-8951P REV0 M/B

PCB 0R LA-8951P REV0 M/B

DAZ0S900100

DAZ0S900100

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

ZZZ2

ZZZ2

Hynix

Hynix

S512@

S512@

X7641338L01

X7641338L01

ZZZ1

ZZZ1

Hynix

Hynix

H512@

H512@

X7641338L02

X7641338L02

ZZZ3

ZZZ3

Hynix

Hynix

S1G@

S1G@

X7641338L03

X7641338L03

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

ZZZ4

ZZZ4

Hynix

Hynix

H1G@

H1G@

X7641338L04

X7641338L04

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

VGA Notes List

VGA Notes List

VGA Notes List

LA-8952P

LA-8952P

LA-8952P

4 55Thursday, January 10, 2013

4 55Thursday, January 10, 2013

4 55Thursday, January 10, 2013

1

0.1

0.1

0.1

A

1 1

2 2

eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function...

3 3

+1.05VS_ VTT

12

R247

R247

24.9_040 2_1%

24.9_040 2_1%

B

DMI_CRX_P TX_N0<15>
DMI_CRX_P TX_N1<15>
DMI_CRX_P TX_N2<15>
DMI_CRX_P TX_N3<15>

DMI_CRX_P TX_P0<15>
DMI_CRX_P TX_P1<15>
DMI_CRX_P TX_P2<15>
DMI_CRX_P TX_P3<15>

DMI_CTX_P RX_N0<15>
DMI_CTX_P RX_N1<15>
DMI_CTX_P RX_N2<15>
DMI_CTX_P RX_N3<15>

DMI_CTX_P RX_P0<15>
DMI_CTX_P RX_P1<15>
DMI_CTX_P RX_P2<15>
DMI_CTX_P RX_P3<15>

FDI_CTX_P RX_N0<15>
FDI_CTX_P RX_N1<15>
FDI_CTX_P RX_N2<15>
FDI_CTX_P RX_N3<15>
FDI_CTX_P RX_N4<15>
FDI_CTX_P RX_N5<15>
FDI_CTX_P RX_N6<15>
FDI_CTX_P RX_N7<15>

FDI_CTX_P RX_P0<15>
FDI_CTX_P RX_P1<15>
FDI_CTX_P RX_P2<15>
FDI_CTX_P RX_P3<15>
FDI_CTX_P RX_P4<15>
FDI_CTX_P RX_P5<15>
FDI_CTX_P RX_P6<15>
FDI_CTX_P RX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

W=12mil L=500mil S=15mil

EDP_COM P

UCPU1A

UCPU1A

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1 023

IVY-BRIDGE_BGA1 023

@

@

C

W=12mil L=500mil S=15mil

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

G3
G1
G4

H22

PEG_GTX _C_HRX_N0

J21

PEG_GTX _C_HRX_N1

B22

PEG_GTX _C_HRX_N2

D21

PEG_GTX _C_HRX_N3

A19

PEG_GTX _C_HRX_N4

D17

PEG_GTX _C_HRX_N5

B14

PEG_GTX _C_HRX_N6

D13

PEG_GTX _C_HRX_N7

A11

PEG_GTX _C_HRX_N8

B10

PEG_GTX _C_HRX_N9

G8

PEG_GTX _C_HRX_N10

A8

PEG_GTX _C_HRX_N11

B6

PEG_GTX _C_HRX_N12

H8

PEG_GTX _C_HRX_N13

E5

PEG_GTX _C_HRX_N14

K7

PEG_GTX _C_HRX_N15

K22

PEG_GTX _C_HRX_P0

K19

PEG_GTX _C_HRX_P1

C21

PEG_GTX _C_HRX_P2

D19

PEG_GTX _C_HRX_P3

C19

PEG_GTX _C_HRX_P4

D16

PEG_GTX _C_HRX_P5

C13

PEG_GTX _C_HRX_P6

D12

PEG_GTX _C_HRX_P7

C11

PEG_GTX _C_HRX_P8

C9

PEG_GTX _C_HRX_P9

F8

PEG_GTX _C_HRX_P10

C8

PEG_GTX _C_HRX_P11

C5

PEG_GTX _C_HRX_P12

H6

PEG_GTX _C_HRX_P13

F6

PEG_GTX _C_HRX_P14

K6

PEG_GTX _C_HRX_P15

G22

PEG_HTX _GRX_N0

C23

PEG_HTX _GRX_N1

D23

PEG_HTX _GRX_N2

F21

PEG_HTX _GRX_N3

H19

PEG_HTX _GRX_N4

C17

PEG_HTX _GRX_N5

K15

PEG_HTX _GRX_N6

F17

PEG_HTX _GRX_N7

F14

PEG_HTX _GRX_N8

A15

PEG_HTX _GRX_N9

J14

PEG_HTX _GRX_N10

H13

PEG_HTX _GRX_N11

M10

PEG_HTX _GRX_N12

F10

PEG_HTX _GRX_N13

D9

PEG_HTX _GRX_N14

J4

PEG_HTX _GRX_N15

F22

PEG_HTX _GRX_P0

A23

PEG_HTX _GRX_P1

D24

PEG_HTX _GRX_P2

E21

PEG_HTX _GRX_P3

G19

PEG_HTX _GRX_P4

B18

PEG_HTX _GRX_P5

K17

PEG_HTX _GRX_P6

G17

PEG_HTX _GRX_P7

E14

PEG_HTX _GRX_P8

C15

PEG_HTX _GRX_P9

K13

PEG_HTX _GRX_P10

G13

PEG_HTX _GRX_P11

K10

PEG_HTX _GRX_P12

G10

PEG_HTX _GRX_P13

D8

PEG_HTX _GRX_P14

K4

PEG_HTX _GRX_P15

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]

DMI Intel(R) FDI

DMI Intel(R) FDI

eDP

eDP

PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_COM P

+1.05VS_ VTT

12

R249

R249

24.9_040 2_1%

24.9_040 2_1%

Layout placement: Place close to U8 (GPU)

1 2

C259 0.1U_040 2_6.3V6KPX@C259 0.1U_040 2_6.3V6KPX@

1 2

C276 0.1U_040 2_6.3V6KPX@C276 0.1U_040 2_6.3V6KPX@

1 2

C257 0.1U_040 2_6.3V6KPX@C257 0.1U_040 2_6.3V6KPX@

1 2

C274 0.1U_040 2_6.3V6KPX@C274 0.1U_040 2_6.3V6KPX@

1 2

C254 0.1U_040 2_6.3V6KPX@C254 0.1U_040 2_6.3V6KPX@

1 2

C272 0.1U_040 2_6.3V6KPX@C272 0.1U_040 2_6.3V6KPX@

1 2

C252 0.1U_040 2_6.3V6KPX@C252 0.1U_040 2_6.3V6KPX@

1 2

C270 0.1U_040 2_6.3V6KPX@C270 0.1U_040 2_6.3V6KPX@

1 2

C250 0.1U_040 2_6.3V6KPX@C250 0.1U_040 2_6.3V6KPX@

1 2

C268 0.1U_040 2_6.3V6KPX@C268 0.1U_040 2_6.3V6KPX@

1 2

C248 0.1U_040 2_6.3V6KPX@C248 0.1U_040 2_6.3V6KPX@

1 2

C267 0.1U_040 2_6.3V6KPX@C267 0.1U_040 2_6.3V6KPX@

1 2

C246 0.1U_040 2_6.3V6KPX@C246 0.1U_040 2_6.3V6KPX@

1 2

C264 0.1U_040 2_6.3V6KPX@C264 0.1U_040 2_6.3V6KPX@

1 2

C244 0.1U_040 2_6.3V6KPX@C244 0.1U_040 2_6.3V6KPX@

1 2

C262 0.1U_040 2_6.3V6KPX@C262 0.1U_040 2_6.3V6KPX@

1 2

C258 0.1U_040 2_6.3V6KPX@C258 0.1U_040 2_6.3V6KPX@

1 2

C277 0.1U_040 2_6.3V6KPX@C277 0.1U_040 2_6.3V6KPX@

1 2

C256 0.1U_040 2_6.3V6KPX@C256 0.1U_040 2_6.3V6KPX@

1 2

C275 0.1U_040 2_6.3V6KPX@C275 0.1U_040 2_6.3V6KPX@

1 2

C255 0.1U_040 2_6.3V6KPX@C255 0.1U_040 2_6.3V6KPX@

1 2

C273 0.1U_040 2_6.3V6KPX@C273 0.1U_040 2_6.3V6KPX@

1 2

C253 0.1U_040 2_6.3V6KPX@C253 0.1U_040 2_6.3V6KPX@

1 2

C271 0.1U_040 2_6.3V6KPX@C271 0.1U_040 2_6.3V6KPX@

1 2

C251 0.1U_040 2_6.3V6KPX@C251 0.1U_040 2_6.3V6KPX@

1 2

C269 0.1U_040 2_6.3V6KPX@C269 0.1U_040 2_6.3V6KPX@

1 2

C249 0.1U_040 2_6.3V6KPX@C249 0.1U_040 2_6.3V6KPX@

1 2

C266 0.1U_040 2_6.3V6KPX@C266 0.1U_040 2_6.3V6KPX@

1 2

C247 0.1U_040 2_6.3V6KPX@C247 0.1U_040 2_6.3V6KPX@

1 2

C265 0.1U_040 2_6.3V6KPX@C265 0.1U_040 2_6.3V6KPX@

1 2

C245 0.1U_040 2_6.3V6KPX@C245 0.1U_040 2_6.3V6KPX@

1 2

C263 0.1U_040 2_6.3V6KPX@C263 0.1U_040 2_6.3V6KPX@

1 2

C562 0.1U_040 2_6.3V6KPX@C562 0.1U_040 2_6.3V6KPX@

1 2

C582 0.1U_040 2_6.3V6KPX@C582 0.1U_040 2_6.3V6KPX@

1 2

C564 0.1U_040 2_6.3V6KPX@C564 0.1U_040 2_6.3V6KPX@

1 2

C584 0.1U_040 2_6.3V6KPX@C584 0.1U_040 2_6.3V6KPX@

1 2

C566 0.1U_040 2_6.3V6KPX@C566 0.1U_040 2_6.3V6KPX@

1 2

C587 0.1U_040 2_6.3V6KPX@C587 0.1U_040 2_6.3V6KPX@

1 2

C568 0.1U_040 2_6.3V6KPX@C568 0.1U_040 2_6.3V6KPX@

1 2

C589 0.1U_040 2_6.3V6KPX@C589 0.1U_040 2_6.3V6KPX@

1 2

C570 0.1U_040 2_6.3V6KPX@C570 0.1U_040 2_6.3V6KPX@

1 2

C591 0.1U_040 2_6.3V6KPX@C591 0.1U_040 2_6.3V6KPX@

1 2

C572 0.1U_040 2_6.3V6KPX@C572 0.1U_040 2_6.3V6KPX@

1 2

C593 0.1U_040 2_6.3V6KPX@C593 0.1U_040 2_6.3V6KPX@

1 2

C574 0.1U_040 2_6.3V6KPX@C574 0.1U_040 2_6.3V6KPX@

1 2

C594 0.1U_040 2_6.3V6KPX@C594 0.1U_040 2_6.3V6KPX@

1 2

C576 0.1U_040 2_6.3V6KPX@C576 0.1U_040 2_6.3V6KPX@

1 2

C597 0.1U_040 2_6.3V6KPX@C597 0.1U_040 2_6.3V6KPX@

1 2

C561 0.1U_040 2_6.3V6KPX@C561 0.1U_040 2_6.3V6KPX@

1 2

C583 0.1U_040 2_6.3V6KPX@C583 0.1U_040 2_6.3V6KPX@

1 2

C563 0.1U_040 2_6.3V6KPX@C563 0.1U_040 2_6.3V6KPX@

1 2

C585 0.1U_040 2_6.3V6KPX@C585 0.1U_040 2_6.3V6KPX@

1 2

C565 0.1U_040 2_6.3V6KPX@C565 0.1U_040 2_6.3V6KPX@

1 2

C586 0.1U_040 2_6.3V6KPX@C586 0.1U_040 2_6.3V6KPX@

1 2

C567 0.1U_040 2_6.3V6KPX@C567 0.1U_040 2_6.3V6KPX@

1 2

C588 0.1U_040 2_6.3V6KPX@C588 0.1U_040 2_6.3V6KPX@

1 2

C569 0.1U_040 2_6.3V6KPX@C569 0.1U_040 2_6.3V6KPX@

1 2

C590 0.1U_040 2_6.3V6KPX@C590 0.1U_040 2_6.3V6KPX@

1 2

C571 0.1U_040 2_6.3V6KPX@C571 0.1U_040 2_6.3V6KPX@

1 2

C592 0.1U_040 2_6.3V6KPX@C592 0.1U_040 2_6.3V6KPX@

1 2

C573 0.1U_040 2_6.3V6KPX@C573 0.1U_040 2_6.3V6KPX@

1 2

C595 0.1U_040 2_6.3V6KPX@C595 0.1U_040 2_6.3V6KPX@

1 2

C575 0.1U_040 2_6.3V6KPX@C575 0.1U_040 2_6.3V6KPX@

1 2

C596 0.1U_040 2_6.3V6KPX@C596 0.1U_040 2_6.3V6KPX@

D

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX _HRX_N0
PEG_GTX _HRX_N1
PEG_GTX _HRX_N2
PEG_GTX _HRX_N3
PEG_GTX _HRX_N4
PEG_GTX _HRX_N5
PEG_GTX _HRX_N6
PEG_GTX _HRX_N7
PEG_GTX _HRX_N8
PEG_GTX _HRX_N9
PEG_GTX _HRX_N10
PEG_GTX _HRX_N11
PEG_GTX _HRX_N12
PEG_GTX _HRX_N13
PEG_GTX _HRX_N14
PEG_GTX _HRX_N15

PEG_GTX _HRX_P0
PEG_GTX _HRX_P1
PEG_GTX _HRX_P2
PEG_GTX _HRX_P3
PEG_GTX _HRX_P4
PEG_GTX _HRX_P5
PEG_GTX _HRX_P6
PEG_GTX _HRX_P7
PEG_GTX _HRX_P8
PEG_GTX _HRX_P9
PEG_GTX _HRX_P10
PEG_GTX _HRX_P11
PEG_GTX _HRX_P12
PEG_GTX _HRX_P13
PEG_GTX _HRX_P14
PEG_GTX _HRX_P15

PEG_HTX _C_GRX_N0
PEG_HTX _C_GRX_N1
PEG_HTX _C_GRX_N2
PEG_HTX _C_GRX_N3
PEG_HTX _C_GRX_N4
PEG_HTX _C_GRX_N5
PEG_HTX _C_GRX_N6
PEG_HTX _C_GRX_N7
PEG_HTX _C_GRX_N8

PEG_HTX _C_GRX_N9
PEG_HTX _C_GRX_N10
PEG_HTX _C_GRX_N11
PEG_HTX _C_GRX_N12
PEG_HTX _C_GRX_N13
PEG_HTX _C_GRX_N14
PEG_HTX _C_GRX_N15

PEG_HTX _C_GRX_P0

PEG_HTX _C_GRX_P1

PEG_HTX _C_GRX_P2

PEG_HTX _C_GRX_P3

PEG_HTX _C_GRX_P4

PEG_HTX _C_GRX_P5

PEG_HTX _C_GRX_P6

PEG_HTX _C_GRX_P7

PEG_HTX _C_GRX_P8

PEG_HTX _C_GRX_P9
PEG_HTX _C_GRX_P10
PEG_HTX _C_GRX_P11
PEG_HTX _C_GRX_P12
PEG_HTX _C_GRX_P13
PEG_HTX _C_GRX_P14
PEG_HTX _C_GRX_P15

E

PEG_GTX _HRX_N[0..15] <22>
PEG_GTX _HRX_P[0..15] < 22>

PEG_HTX _C_GRX_N[0..15] <22>
PEG_HTX _C_GRX_P[0..15] <22>

4 4

Security Class ification

Security Class ification

Security Class ification

2011/06/ 24 2012/07/ 12

2011/06/ 24 2012/07/ 12

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/ 24 2012/07/ 12

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

LA-8952P

LA-8952P

LA-8952P

5 55Thursday, January 10, 20 13

5 55Thursday, January 10, 20 13

5 55Thursday, January 10, 20 13

E

0.1

0.1

0.1

A

1 1

PCH->CPU
UNCOREPWRGOOD:
SM_DRAMPWROK:DRAM power ok
RESET#:

都都都都ok後後後後後後後後

CPU

非非非非

CORE

做做做做

reset

外外外外外外外外外外外外

OK

Follow DG 1.5& Tacoma_Fall2 1.0

reserve XBOX

@

@

12

C614 0.1U_ 0402_16V4Z

C614 0.1U_ 0402_16V4Z

R292 10K_0402 _5%

R292 10K_0402 _5%

2 2

12

H_CPUPW RGD_R

OREPWRGOOD:

UNC

+1.05VS_VTT

H_PROCHOT#<37,42>

非非非非

CORE

SM_DRAMPWROK:DRAM power ok

B

PROC_SELECT#
PH VCPLL and connect to PCH DF_TVS

H_SNB_IVB#<17>

偵偵偵偵偵偵偵偵

CPU

有有有有有有有有有有有有有有有有

三三三三三三三三三三三三三三三三

follow Checklist 1.5

R534 62_ 0402_5%

R534 62_ 0402_5%

外外外外外外外外外外外外

OK

H_CPUPW RGD<18>

12

H_PECI<18,37>

R305 0_ 0402_5%@R305 0_0402_5%@

T33 PAD@T33 PAD@

R533

R533

56_0402_5 %

56_0402_5 %

1 2

H_THERMT RIP#<18>

H_PM_SYNC<15>

1 2

R237

R237

1 2

130_0402_ 1%

130_0402_ 1%

H_CATERR#

H_PECI

H_PROCHOT# _RH_PROCHOT#

H_CPUPW RGD_R

VDDPWRGOOD_R

BUF_CPU_RST#

UCPU1B

UCPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

@

@

C

J3

BCLK

MISC THERMAL PWR MANAGEMENT

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

CLOCKS

SM_DRAMRST#

DDR3

MISC

DDR3

MISC

JTAG & BPM

JTAG & BPM

BCLK#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#

PREQ#

TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H2

AG3
AG1

AT30

BF44
BE43
BG43

N53
N55

L56

TCK

L55
J58

M60

TDI

L59

K58

G58
E55
E59
G55
G59
H60
J59
J61

D

+1.05VS_VTT

CLK_CPU_D PLL#

CLK_CPU_D PLL

Checklist1.5 P.67 Graphis Disable Guide
DIS only SKU eDP disable
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT

CLK_CPU_D PLL
CLK_CPU_D PLL#

SM_RCOMP0,SM_RCOMP1
W=20mil L=500mil S=13mil

SM_RCOMP2
W=15mil L=500mil S=13mil

SM_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

R517 1K_0402 _5%R517 1K_0402 _5%

R516 1K_0402 _5%R516 1K_0402 _5%

CLK_CPU_D MI <14>
CLK_CPU_D MI# <14>

R272 140_0402_ 1%R272 140_0402_ 1%
R273 25.5_0402_1 %R273 25.5_0402_1 %
R267 200_0402_ 1%R267 200_0402_ 1%

12

12

12
12
12

100P_0402_ 50V8J

100P_0402_ 50V8J

DDR3 Compensation Signals

XDP_PRDY#
XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI
XDP_TDO

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

XDP_DBRESET#

T97T97
T98T98

0301 Add test point

0419 ESD request to reserve

1

@

T49T49 C1278
T90T90
T91T91
T92T92
T93T93
T94T94
T95T95
T96T96

0301 Add test point

@

C1278

1000P_0402 _50V7K

1000P_0402 _50V7K

2

1

C82

@ C82

@

2

ESD
C

Reserve

PU/PD for JTAG signals

XDP_TMS
XDP_TDI
XDP_TDO

XDP_TCK
XDP_TRST#

XDP_DBRESET#

Tacoma_Fall2 1.0 PH 1K +3VS
Check list 1.5 PH 1K +3VS
Debug port DG1.1-1.3 50~5K ohm

E

SM_DRAMRST# <7>

R20 51_0402_5 %R20 51_0402_5%
R39 51_0402_5 %R39 51_0402_5%
R37 51_0402_5 %R37 51_0402_5%

R40 51_0402_5 %R 40 51_0402_5%
R28 51_0402_5 %R28 51_0402_5%

R312 1K_0402 _5%

R312 1K_0402 _5%

12
12
12

12
12

12

+1.05VS_VTT

+3VS

+3VALW

3 3

SYS_PWROK<15>

4 4

+3VS

R31

R31

10K_0402_5 %

10K_0402_5 %

1 2

R35

R35

10K_0402_5 %

10K_0402_5 %

1 2

PM_DRAM_PWRGD<15>

A

0.1U_0402_ 16V4Z

0.1U_0402_ 16V4Z

@

@

RUN_ON_CPU1.5VS3#<10>

C228

C228

12

U22

U22

5

1

P

B

O

2

A

G

74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

3

RUN_ON_CPU 1.5VS3#

4

PM_SYS_PWRGD_BUF

Q4

Q4

2N7002K_SOT 23-3

2N7002K_SOT 23-3

+1.5V_CPU_VDDQ

12

R238

R238
200_0402_ 5%

200_0402_ 5%

12

R38@

R38@
39_0402_5 %

39_0402_5 %

13

D

D

2

G

G

S

S

@

@

B

C43

C43

0.1U_0402_ 16V4Z

0.1U_0402_ 16V4Z

@

@

+1.05VS_VTT

R546

R546

75_0402_5 %

75_0402_5 %

R544

R544

43_0402_5 %

43_0402_5 %

1 2

12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Buffered reset to CPU

C617

C617

0.1U_0402_ 16V4Z

0.1U_0402_ 16V4Z

12

BUFO_CPU_RST#BUF_CPU_RST#

SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

+3VS

12

5

U45

U45

1

P

NC

4

Y

2

PCH_PLTRST#

A

G

3

Compal Secret Data

Compal Secret Data

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

Compal Secret Data

PCH_PLTRST# <17>

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Docu ment Number Rev

Size Docu ment Number Rev

Size Docu ment Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

LA-8952P

LA-8952P

LA-8952P

E

6 5 5Thursday, January 10, 20 13

6 5 5Thursday, January 10, 20 13

6 5 5Thursday, January 10, 20 13

0.1

0.1

0.1

A

UCPU1C

DDR_A_D[0..63]<12>

1 1

2 2

3 3

DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AG6

AP11

AJ10

AR11

AP6
AU6
AV9
AR6

AP8
AT13
AU13

BC7

BB7
BA13
BB11

BA7

BA9

BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

AL6

AJ8
AL8
AL7

AJ6

UCPU1C

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

B

AU36

SA_CK[0]

AV36

SA_CK#[0]

AY26

SA_CKE[0]

AT40

SA_CK[1]

AU40

SA_CK#[1]

BB26

SA_CKE[1]

BB40

SA_CS#[0]

BC41

SA_CS#[1]

AY40

SA_ODT[0]

BA41

SA_ODT[1]

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_CLK_DDR0 <12 >
SA_CLK_DDR#0 <1 2>
DDRA_CKE0_DIMMA <12>

SA_CLK_DDR1 <12 >
SA_CLK_DDR#1 <1 2>
DDRA_CKE1_DIMMA <12>

DDRA_CS0_DIMMA# <12>
DDRA_CS1_DIMMA# <12>

SA_ODT0 <12>
SA_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12>

C

UCPU1D

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

D

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

E

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

@

@

Follow CRB1.0

R216

R216

0_0402_5%

0_0402_5%

1 2

@

1 2

@

D

S

D

S

13

G

G

SB00000QO00

SB00000QO00

2

1

C190

C190

0.047U_0402_16V7K

0.047U_0402_16V7K

2

DIMM_DRAMRST#_RSM_DRAMRST#

Q16

Q16
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

CPU通通DIMM做reset

SM_DRAMRST#<6>

R217

R217

4.99K_0402_1%

4.99K_0402_1%

4 4

@

@

1 2

DRAMRST_CNTRL_PC H<14>

DRAMRST_CNTRL<10>

DRAMRST_CNTRL_EC<37>

For DS3

A

R62 0_0402_5%

R62 0_0402_5%

R64 0_0402_5%@R64 0_0402_5%@

DRAMRST_CNTRL

1 2

+1.5V

12

R212

R212

1K_0402_5%

1K_0402_5%

1 2

R219 1K_0402_5%R219 1K_0402_5%

S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset

B

DIMM_DRAMRST# <12>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

IVY-BRIDGE_BGA1023

@

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

LA-8952P

LA-8952P

LA-8952P

E

0.1

0.1

7 55Thursday, January 10, 2013

7 55Thursday, January 10, 2013

7 55Thursday, January 10, 2013

0.1

A

B

C

D

E

CFG Straps for Processor

UCPU1E

UCPU1E

T32 PAD @T32 PAD @

1 1

2 2

3 3

+CPU_CO RE

R302

R302

49.9_040 2_1%

49.9_040 2_1%

1 2

R91

R91
100_040 2_1%

100_040 2_1%

1 2

R306

R306

49.9_040 2_1%

49.9_040 2_1%

1 2

+VGFX_C ORE

R310

R310

49.9_040 2_1%

49.9_040 2_1%

1 2

R95

R95
100_040 2_1%

100_040 2_1%

1 2

R311

R311

49.9_040 2_1%

49.9_040 2_1%

1 2

@

@

@

@

VCC_VAL _SENSE

VSS_VAL _SENSE

VAXG_VA L_SENSE

VSSAXG_ VAL_SENSE

CFG0

CFG2

CFG4
CFG5
CFG6
CFG7

VCC_VAL _SENSE
VSS_VAL _SENSE

VAXG_VA L_SENSE
VSSAXG_ VAL_SENSE

T18 PAD @T18 PAD @

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1 023

IVY-BRIDGE_BGA1 023

@

@

BCLK_ITP#

RESERVED

RESERVED

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

BCLK_ITP

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

N59
N58

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61

These pins are for solder joint

BD61

reliability and non-critical to

BE61
BE59

function. For BGA only.

BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

eDP enable

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

*

*

CFG6
CFG5

R543

R543

1K_0402 _1%

1K_0402 _1%

11: (Default) 1x16 PCI Express

*

10: 2x8 PCI Express

12

R296

R296
1K_0402 _1%

1K_0402 _1%

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

CFG4

12

R293

@ R293

@

1K_0402 _1%

1K_0402 _1%

UMA,Optimus eDP
DISO eDP

1:Disable

0:Enable

12

12

R541

R541

1K_0402 _1%

@

@

1K_0402 _1%

@

@

01: Reserved

00

: 1x8,2x4 PCI Express

CFG7

12

R297

R297
1K_0402 _1%@

1K_0402 _1%@

關關關關關關關關

啟啟啟啟啟啟啟啟

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following
xxRESETB de assertion

Tacoma_Fall2 1.0 P.12

0: PEG Wait for BIOS for training

4 4

Security Class ification

Security Class ification

Security Class ification

2011/06/ 24 2012/07/ 12

2011/06/ 24 2012/07/ 12

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/ 24 2012/07/ 12

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

LA-8952P

LA-8952P

LA-8952P

E

0.1

0.1

0.1

8 55Thursday, January 10, 20 13

8 55Thursday, January 10, 20 13

8 55Thursday, January 10, 20 13

A

1 1

INTEL Recommend VCC
4*470UF,12*22uF(0805) and 35*2.2uF(0402)
PD0.8
CAP at Power side

2 2

3 3

4 4

B

UCPU1F

ULV type

UCPU1F

DC 33A

+CPU_CORE

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

@

@

C

POWER

POWER

CORE SUPPLY

CORE SUPPLY

8.5A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

VCCIO50
VCCIO51

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE
VSS_SENSE

AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16
W17

BC22

AM25
AN22

A44
B43
C44

F43
G43

AN16
AN17

VCCSENSE_R
VSSSENSE_R

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

PEG IO AND DDR IO

PEG IO AND DDR IO

RAILS

RAILS

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

SENSE LINES SVID QUIET

D

+1.05VS_VTT

For DDR

INTEL Recommend VCCIO
2*330UF,10*10uF(0603) and 26*1uF(0402)
PD0.8
CAP at Power side

For PEG

+3VS

12

R521

R521

10K_0402_5%

10K_0402_5%

+1.05VS_VTT

VCCIO_SEL

10K_0402_5%

10K_0402_5%

VCCIO_SEL

+1.05VS_VTT

1 2

C553

C553
1U_0402_6.3V6K

1U_0402_6.3V6K

Place the PU
resistors close to VR

1 2

R282 0_0402_5%@R282 0_0402 _5%@
R289 0_0402_5%@R289 0_0402 _5%@

1 2

R513 10_0402_5%R513 10_040 2_5%

1 2

VCCIO_SENSE
VSSIO_SENSE_L

12

R512

R512
10_0402_5%

10_0402_5%

Check list 1.5

R522

R522

VCCIO_SENSE <47>
VSSIO_SENSE_L <47>

VCCIO_SEL after Ivy bridge ES2 Voltage support

12

@

@

12

+1.05VS_VTT

BC22

R531

R531
130_0402_5%

130_0402_5%

1 2

R528 43_0402_1%

R528 43_0402_1%
R527 0_0402_5%@R527 0_0402_5%@

1 2
1 2

R530 0_0402_5%@R530 0_0402_5%@

R79

R79

1 2

100_0402_1%

100_0402_1%

@

@

*

1/NC : (Default) +1.05VS_VTT

0: +1.0VS_VTT

+1.05VS_VTT+ 1.05VS_VTT

+CPU_CORE

12

12

12

R281

R281
100_0402_1%

100_0402_1%

R288

R288
100_0402_1%

100_0402_1%

Place the PU

R529

R529

re

75_0402_5%

75_0402_5%

VCCSENSE <50>
VSSSENSE <50 >

Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.

E

sistors close to CPU

VR_SVID_ALRT# <50 >
VR_SVID_CLK < 50>
VR_SVID_DAT <50>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

LA-8952P

LA-8952P

LA-8952P

E

9 55Thursday, January 10, 2013

9 55Thursday, January 10, 2013

9 55Thursday, January 10, 2013

0.1

0.1

0.1

A

1 2

R65

+3VALW

12

RUN_ON_CPU1.5VS3#

13

D

D

S

S

@

@

R65

SUSP<40,45,46>

R78

R78

100K_0402_5% @

12

100K_0402_5% @

Q6

Q6

2N7002K_SOT23-3

2N7002K_SOT23-3

2

G

G

1 1

@

@

R81 0_0402_5%

SUSP#<37,40, 45,46,47,49>

R81 0_0402_5%

1 2

@

@

R82

0_0402_5% R82

0_0402_5%

CPU1.5V_S3_GATE<37,40>

INTEL Recommend VAXG
2*

470uF,6*22uF(0805) and 6*10uF(0603)
11*1U(0402)
PD0.8

2 2

CR CheckList Rev1.5

INTEL Recommend VCCPLL

3 3

4 4

1*330uF,2*1uF(0402)
PD0.8

SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9

B phase Cost down proposal

+1.8VS

+VCCSA

VCC_AXG_SENSE<50>

VSS_AXG_SENSE<50>

Place BOT OUT Conn

1

@

@

+

+

C242

C242
330U_D2_2V_Y

330U_D2_2V_Y

2

INTEL Recommend VCCSA
1*330uF,5*10uF(0603) ,5*1uF(0402)

+VGFX_CORE

@

Place TOP IN BGA

C309

C309

1U_0402_6.3V6K

1U_0402_6.3V6K

12

@

@

Place BOT OUT BGA

C577

C577

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

12

PD0.8

A

22U_0805_6.3V6M@C633

22U_0805_6.3V6M

@

@

0_0402_5%@

0_0402_5%@

+VCCSA

12

12

+VGFX_CORE

12

R308

R308

100_0402_5%

100_0402_5%

12

R309

R309

100_0402_5%

100_0402_5%

C633

10U_0603_6.3V6M

10U_0603_6.3V6M

12

C302

C302

1U_0402_6.3V6K

1U_0402_6.3V6K

12

@

@

C560

C560

10U_0603_6.3V6M

10U_0603_6.3V6M

12

B

2

C153

C153

1

12

2

C301

C301

C300

C300

1U_0402_6.3V6K

1U_0402_6.3V6K

12

@

@

C579

C579

C555

C555

10U_0603_6.3V6M

10U_0603_6.3V6M

12

B

+1.5V

+VSB

12

R85

R85
82K_0402_5%

82K_0402_5%

RUN_ON_CPU1.5VS3

13

D

D

G

Q8

G

Q8
2N7002K_SOT23-3

2N7002K_SOT23-3

S

S

RUN_ON_CPU1.5VS3# <6>

DC 29A

1 2

R87

R87

100_0402_1%

100_0402_1%

@

@

1.2A

C280

1U_0402_6.3V6K

C280

1U_0402_6.3V6K

C281

1U_0402_6.3V6K

C281

1U_0402_6.3V6K

1

2

6A

C308

C308

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

@

@

C559

C559

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

12

J1@

J1@

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

U11 AO4430L_SO8

U11 AO4430L_SO8

8
7
6
5

UCPU1G

UCPU1G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

@

@

SB00000RV00

SB00000RV00

4

12

R77

R77
330K_0402_5%

330K_0402_5%

@

@

+1.5V_CPU_VDDQ

1
2
3

R175

R175
15K_0402_1%

15K_0402_1%

1 2

POWER

POWER

220_0402_5%

220_0402_5%

2N7002K_SOT23-3

2N7002K_SOT23-3

12

C115

C115

0.047U_0603_25V7K

0.047U_0603_25V7K

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREF

VREF

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

GRAPHICS

GRAPHICS

SENSE

LINES

SENSE

LINES

QUIET RAILS

QUIET RAILS

1.8V RAIL

1.8V RAIL

VSS_SENSE_VDDQ

SENSE LINES

SENSE LINES

SA RAIL

SA RAIL

VCCSA VID

lines

VCCSA VID

lines

R80

R80

Q7

Q7

SM_VREF

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]

VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

VCCDQ[1]
VCCDQ[2]

VDDQ_SENSE

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

C

12

13

D

D

S

S

AY43

BE7
BG7

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

AM28
AN26

BC43
BA43

U10

D48
D49

C

12

C116@

C116@

0.1U_0402_10V6K

0.1U_0402_10V6K

2

G

G

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

5A

+1.5V_CPU_VDDQ

C

PU EDS1.3 P.93

CSA_VID0 Must PD

VC

D

M3 Support

SA_DIMM_VREFDQ

RUN_ON_CPU1.5VS3#

+1.5V_CPU_VDDQ

+V_SM_VREF_CNT should

ve 20 mil trace width

ha

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

12

R518

@R518

R519

1K_0402_1%

1K_0402_1%

@R519

@

1K_0402_1%

1K_0402_1%

@

Place TOP IN BGA

C351

C351

C348

C348

C328

C329

C329

C321

C321

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

12

@

@

@

@

@

@

C328

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

@

@

@

@

@

@

Place BOT OUT BGA

C340

C340

C338

C338

C337

C337

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

12

12

12

12

C317

C317
1U_0402_6.3V6K

1U_0402_6.3V6K

R248
0_0402_5%

0_0402_5%

+VCCSA_SENSE <48>

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

12

@ R248

@

H_VCCSA_VID0
H_VCCSA_VID1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

12

R113

R113
1K_0402_1%

1K_0402_1%

12

C117

C117

12

R124

R124
1K_0402_1%

1K_0402_1%

C349

C312

C312

1U_0402_6.3V6K

1U_0402_6.3V6K

12

C296

C296

10U_0603_6.3V6M

10U_0603_6.3V6M

12

12

@

@

12

H_VCCSA_VID0 < 48>
H_VCCSA_VID1 < 48>

C349

C318

C318

1U_0402_6.3V6K

1U_0402_6.3V6K

12

@

@

@

@

C295

C295

10U_0603_6.3V6M

10U_0603_6.3V6M

12

+1.5V_CPU_VDDQ +1.5V

C316

C316

C320

C320

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

@

@

@

@

C298

C298

C339

C339

C299

C299

Compal Secret Data

Compal Secret Data

Compal Secret Data

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

12

12

12

C150 0.1U_0402_10V7KC150 0.1U_0402_10V7K

12

C151 0.1U_0402_10V7KC151 0.1U_0402_10V7K

12

C152 0.1U_0402_10V7KC152 0.1U_0402_10V7K

12

C157 0.1U_0402_10V7KC157 0.1U_0402_10V7K

Deciphered Date

Deciphered Date

Deciphered Date

D

R117 0_0402_5%@R117 0_0402_5%@

S

S

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

1

+

+

C286

C286
330U_D2_2V_Y

330U_D2_2V_Y

2

SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9

VID0

0

0

1 1

12

G

G

VID1

E

1 2

R86 0_0402_5%@R86 0_0402_5%@

D

S

D

S

13

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

SB00000QO00

SB00000QO00

G

G

Q2204

Q2204

2

DRAMRST_CNTRL_PCH

+1.5V

12

R76@

R76@
1K_0402_1%

D

D

123

Q11

Q11
AO3414_SOT23-3

AO3414_SOT23-3

@

@

+V_SM_VREF+V_SM_VREF_CNT

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Check list1.5 P18 M1 default M3 no stuff

12

1K_0402_1%

R116@

R116@
1K_0402_1%

1K_0402_1%

INTEL Recommend VDDQ
1*330uF,8*10uF(0603) ,10*1uF(0402)
PD0.8

V

VCCSA

UL

Vout

HR CR

0.9V

0

1

0 X1

V V

0.85V

V

0.775V

0.75V

V

V

VX

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-8952P

LA-8952P

LA-8952P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

+VREF_DQ_DIMMA

DRAMRST_CNTRL <7>

0.1

0.1

10 55Thursday, January 10, 2013

10 55Thursday, January 10, 2013

10 55Thursday, January 10, 2013

0.1

A

UCPU1H

UCPU1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

1 1

2 2

3 3

4 4

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

@

@

VSS

VSS

A

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

B

UCPU1I

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

@

@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS

VSS

Issued Date

Issued Date

Issued Date

NCTF

NCTF

C

M4

VSS[250]

M58

VSS[251]

M6

VSS[252]

N1

VSS[253]

N17

VSS[254]

N21

VSS[255]

N25

VSS[256]

N28

VSS[257]

N33

VSS[258]

N36

VSS[259]

N40

VSS[260]

N43

VSS[261]

N47

VSS[262]

N48

VSS[263]

N51

VSS[264]

N52

VSS[265]

N56

VSS[266]

N61

VSS[267]

P14

VSS[268]

P16

VSS[269]

P18

VSS[270]

P21

VSS[271]

P58

VSS[272]

P59

VSS[273]

P9

VSS[274]

R17

VSS[275]

R20

VSS[276]

R4

VSS[277]

R46

VSS[278]

T1

VSS[279]

T47

VSS[280]

T50

VSS[281]

T51

VSS[282]

T52

VSS[283]

T53

VSS[284]

T55

VSS[285]

T56

VSS[286]

U13

VSS[287]

U8

VSS[288]

V20

VSS[289]

V61

VSS[290]

W13

VSS[291]

W15

VSS[292]

W18

VSS[293]

W21

VSS[294]

W46

VSS[295]

W8

VSS[296]

Y4

VSS[297]

Y47

VSS[298]

Y58

VSS[299]

Y59

VSS[300]

G48

VSS[301]

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

Compal Secret Data

Compal Secret Data

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

LA-8952P

LA-8952P

LA-8952P

E

0.1

0.1

0.1

11 55Thursday, January 10, 2013

11 55Thursday, January 10, 2013

11 55Thursday, January 10, 2013

E

A

+1.5V

12

R223

R223
1K_0402_1%

1K_0402_1%

12

All VREF traces should
have 10 mil trace width

1 1

DDR_A_DQS#[0..7] <7>

DDR_A_DQS[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

Layout Note:
Place near JDIMM1

+1.5V

C294

1U_0402_6.3V6K

C294

1U_0402_6.3V6K

C326

1U_0402_6.3V6K

C326

1U_0402_6.3V6K

1

1

1

2

2

2

2 2

+1.5V

C287

10U_0603_6.3V6M

C287

10U_0603_6.3V6M

1

2

+1.5V

C303

10U_0603_6.3V6M

C303

10U_0603_6.3V6M

1

2

3 3

+0.75VS

C411

1U_0402_6.3V6K C411

1U_0402_6.3V6K

1

2

Layout Note:
Pla

ce near JDIMM1.203,204

4 4

C314

10U_0603_6.3V6M

C314

10U_0603_6.3V6M

C284

10U_0603_6.3V6M

C284

10U_0603_6.3V6M

1

1

2

2

C293

10U_0603_6.3V6M

C293

10U_0603_6.3V6M

C343

10U_0603_6.3V6M@C343

10U_0603_6.3V6M

1

1

@

2

2

C412

1U_0402_6.3V6K C412

1U_0402_6.3V6K

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K C413

1U_0402_6.3V6K

C291

C291

1

2

1

2

C413

1

2

C289

10U_0603_6.3V6M

C289

10U_0603_6.3V6M

C311

220U_B2_2.5VM_R35

C311

220U_B2_2.5VM_R35

+

+

@

@

1

2

DDR_A0_DM0
DDR_A0_DM1
DDR_A0_DM2
DDR_A0_DM3
DDR_A0_DM4
DDR_A0_DM5
DDR_A0_DM6
DDR_A0_DM7

A

C310

1U_0402_6.3V6K

C310

1U_0402_6.3V6K

C414

1U_0402_6.3V6K C414

1U_0402_6.3V6K

+0.75VS

R226

R226
1K_0402_1%

1K_0402_1%

DDRA_CKE0_DIMMA< 7>

DDRA_CS1_DIMMA#<7>

+3VS

C222

2.2U_0402_6.3V6M

C222

2.2U_0402_6.3V6M

1

12

2

DDR_A_BS2<7>

SA_CLK_DDR0<7>
SA_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

C409

2.2U_0402_6.3V6M

C409

2.2U_0402_6.3V6M

1

12

2

+VREF_DQ_DIMMA

C221

0.1U_0402_16V4Z

C221

0.1U_0402_16V4Z

DDRA_CKE0_DIMMA

DDR_A_BS2

DDRA_CS1_DIMMA#

C408

0.1U_0402_16V4Z C408

0.1U_0402_16V4Z

1 2

B

DDR_A_D0
DDR_A_D1

DDR_A0_DM0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A0_DM3

DDR_A_D26
DDR_A_D27

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

SA_CLK_DDR0
SA_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A0_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A0_DM7

DDR_A_D58
DDR_A_D59

10K_0402_5%

10K_0402_5%

R336

R336

R331

R331

10K_0402_5%

10K_0402_5%

1 2

B

+1.5V +1.5V+VREF_DQ_DIMMA

JDIMM1

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

TYCO_2-2013022-1

TYCO_2-2013022-1

ME@

ME@

RESET#

VREF_CA

EVENT#

<Address: SA1:SA0=00>

DQS0#

DQS0

DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

VDD

VDD

VDD

VDD

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

GND2

BOSS2

DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

CK1

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

C

2

VSS

4

DDR_A_D4

6

DDR_A_D5

8
10

DDR_A_DQS#0

12

DDR_A_DQS0

14
16

DDR_A_D6

18

DDR_A_D7

20
22

DDR_A_D12

24

DDR_A_D13

26
28

DDR_A0_DM1

30

DIMM_DRAMRST#

32
34

DDR_A_D14

36

DDR_A_D15

38
40

DDR_A_D20

42

DDR_A_D21

44
46

DDR_A0_DM2

48
50

DDR_A_D22

52

DDR_A_D23

54
56

DDR_A_D28

58

DDR_A_D29

60
62

DDR_A_DQS#3

64

DDR_A_DQS3

66
68

DDR_A_D30

70

DDR_A_D31

72

74

DDRA_CKE1_DIMMA

76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

SA_CLK_DDR1
SA_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDRA_CS0_DIMMA#
SA_ODT0

SA_ODT1

+VREF_CA

DDR_A_D36
DDR_A_D37

DDR_A0_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A0_DM6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

SMB_DATA_S3
SMB_CLK_S3

+0.75VS

A15
A14

A11

A7

A6
A4

A2
A0

BA1

S0#

NC

DIMM_DRAMRST# <7>

DDRA_CKE1_DIMMA <7>

SA_CLK_DDR1 <7>
SA_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDRA_CS0_DIMMA# <7>
SA_ODT0 <7>

SA_ODT1 <7>

C353

0.1U_0402_16V4Z C353

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

12

2

SMB_DATA_S3 <14,31,3 8>
SMB_CLK_S3 <14,3 1,38>

+1.5V

12

R265

R265
1K_0402_1%

1K_0402_1%

12

R269

R269

C354

C354

1K_0402_1%

1K_0402_1%

D

E

Channel A

DIMM_1 Standard H:4.0mm

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB

DDRIII DIMMB

LA-8952P

LA-8952P

LA-8952P

0.1

0.1

12 5 5Thursday, January 10, 2013

12 5 5Thursday, January 10, 2013

E

12 5 5Thursday, January 10, 2013

0.1

A

B

C

D

E

RTCRST close to RAM door

12

12

R501

+RTCBATT

R356 20K_0402_5%

R356 20K_0402_5%

R357 20K_0402_5%

R357 20K_0402_5%

1 1

+RTCBATT

R358 1M_0402_5%

R358 1M_0402_5%

R355 330K_0402_5%

R355 330K_0402_5%

*

C439

C439

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

1 2

C440

C440

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

1 2

INTVRMEN

H

：：：：

Integrated VRM enable

：：：：

Integrated VRM disable

L

(INTVRMEN should always be pull high.)

+3VS

1 2

R109 1K_0402_5%@

R109 1K_0402_5%@

HIGH= Enable ( No Reboot)Disable TCO timer system rebo

LOW= Disable (Default internal PD)

*

2 2

HDA_SDO

ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when sampled high

*

1.8V when sampled low
eds to be pulled High for Huron River platfrom

Ne

HDA_BITCLK_AUDIO<36>

3 3

HDA_SDOUT_AUDIO<36>

4 4

+3V_PCH

ME_FLASH<37>

R47 1K_0402_5%

R47 1K_0402_5%

HDA_SYNC_AUDIO<36>

HDA_RST_AUDIO#<36>

12

@

@

R134

R134

200_0402_5%

200_0402_5%

12

@

@

R141

R141

100_0402_1%

100_0402_1%

1 2

R406 10M_0402_5%R406 10M_0402_5%

Y2

Y2

1 2

32.768KHZ_12.5PF_9H03200 019

32.768KHZ_12.5PF_9H03200 019

18P_0402_50V8J

18P_0402_50V8J

SJ10000BM00

SJ10000BM00

1

C452

C452

2

R501
0_0603_5%@

0_0603_5%@

PCH_RTCRST#

PCH_SRTCRST#

12

12

R372

R372
0_0603_5%@

0_0603_5%@

SM_INTRUDER# HDA_SPKR

PCH_INTVRMEN

HDA_SPKR

R46

R46

1K_0402_5%

1K_0402_5%

12

12

HDA_SYNC_PCH

@

@

PCH_RTCX1

PCH_RTCX2

1

C451

C451
18P_0402_50V8J

18P_0402_50V8J

2

A

HDA_SDOUT_PCH

HDA_BITCLK_PCH

HDA_SYNC_PCH_R

HDA_RST_PCH#

HDA_SDOUT_PCH

12

PCH_JTAG_TDIPCH_JTAG_TDO PCH_JTAG_TMS

12

@

@

R73

R73

0_0402_5%

0_0402_5%

@

@

12

R75

R75
33_0402_5%

33_0402_5%

1 2

R30

R30
33_0402_5%

33_0402_5%

1 2

R74

R74
33_0402_5%

33_0402_5%

1 2

R72

R72
33_0402_5%

33_0402_5%

1 2

+3V_PCH+3V_PCH +3V_PCH

12

@

@

R143

R143

200_0402_5%

200_0402_5%

12

R140

R140
100_0402_1%

100_0402_1%

@

@

R137

R137

200_0402_5%

200_0402_5%

@

@

R142

R142

100_0402_1%

100_0402_1%

ot feature

Prevent back drive issue.

+5VS

G

G

2

SB00000QO00

SB00000QO00

S

S

R48

R48

1 2

12

R29

R29
1M_0402_5%

1M_0402_5%

+3V_PCH

1 2

R266

R266

1 2

R221

R221

1 2

R127

R127

1 2

R171

R171

Q3

Q3
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

D

D

HDA_SPKR<36>

0_0402_5%@

0_0402_5%@

HDA_SDIN0<36>

1 2

R162 1K_0402_1%@R162 1K_0402_1%@

R341 10K_0402_5%

R341 10K_0402_5%

SPI_WP#1

3.3K_0402_5%

3.3K_0402_5%

SPI_HOLD#1

3.3K_0402_5%

3.3K_0402_5%

SPI_WP#

3.3K_0402_5%

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

3.3K_0402_5%

12

R100

R100

@

@

51_0402_5%

51_0402_5%

B

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK_PCH

HDA_SYNC_PCHHDA_SYNC_PCH_R

HDA_RST_PCH#

HDA_SDOUT_PCH

12

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH_R

SPI_SB_CS0#

SPI_SB_CS1#

SPI_SI

SPI_SO_R

SPI_SB_CS1#
SPI_SO_R

SPI_SB_CS0#

HDA_SDIN0

PCH_GPIO33

PCH_GPIO13

0_0402_5%

0_0402_5%

1 2

33_0402_5%

33_0402_5%

0_0402_5%

0_0402_5%

1 2

33_0402_5%

33_0402_5%

U13A

U13A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER_FCBGA989

PANTHER_FCBGA989

HM77@

HM77@

JTAG

JTAG

2MB SPI ROM FOR ME
& Non-share ROM.

@

@

R172

R172

12

CS1#
SPI_SO1 SPI_HOLD#1

SPI_WP#1

R188

R188

U6 Rersver 4M+2M Solution

@

@

R173

R173

12

CS#
SPI_SO_LSPI_SO_R

R169

R169

U46

U46

1

CS#

2

SO

3

WP#

4

GND

16M W25Q16BVSSIG SOIC 8P

16M W25Q16BVSSIG SOIC 8P

U44

U44

1

CS#

2

SO

3

SPI_WP# SPI_CLK_PCH

WP#

4

GND

32M W25Q32BVSSIG SOIC 8P

32M W25Q32BVSSIG SOIC 8P

C38

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

RTCIHDA

RTCIHDA

SPI

SPI

VCC

HOLD#

SCLK

HOLD#

SCLK

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA 6G

SATA 6G

SATA

SATA

SATAICOMPO

SATA3RCOMPO

SATA3COMPI

SATA0GP / GPIO21

SATA1GP / GPIO19

+3VS+3VS

8
7
6
5

SI

8

VCC

7
6
5

SI

Issued Date

Issued Date

Issued Date

C

SERIRQ

SATA0RXN
SATA0RXP

SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP

SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATAICOMPI

SATA3RBIAS

SATALED#

SPI_CLK1
SPI_SI1

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SPI_HOLD#

SPI_SI_R

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36
K36

V5

SERIRQ

AM3
AM1
AP7

SATA_PTX_DRX_C_N0

AP5

SATA_PTX_DRX_C_P0

AM10

SATA_DTX_C_R_PRX_N1

AM8

SATA_DTX_C_R_PRX_P1

AP11

SATA_PTX_DRX_N1

AP10

SATA_PTX_DRX_P1

AD7

SATA_DTX_C_R_PRX_N2

AD5

SATA_DTX_C_R_PRX_P2

AH5

SATA_PTX_DRX_N2

AH4

AB8
AB10
AF3

Disable w/ HM70

AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

L=500mil S=15mil

Y10

SATA_COMP

AB12

L=500mil S=15mil

AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

BBS_BIT0_R

@

@

R199

R199

0_0402_5%

0_0402_5%

1 2

SPI_CLK_PCH_R

1 2

SPI_SI

R196

R196
33_0402_5%

33_0402_5%

C191

C191

1 2

0_0402_5%

0_0402_5%
R168

R168

1 2

@

@

1 2

R170

R170
33_0402_5%

33_0402_5%

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

LPC_AD0 <31,3 7>
LPC_AD1 <31,3 7>
LPC_AD2 <31,3 7>
LPC_AD3 <31,3 7>

LPC_FRAME# <31,37>

SERIRQ <37 >

R148 0_0402_5%HDD1@R148 0_0402_5 %HDD1@
R149 0_0402_5%HDD1@R149 0_0402_5 %HDD1@
R150 0_0402_5%HDD1@R150 0_0402_5 %HDD1@
R151 0_0402_5%HDD1@R151 0_0402_5 %HDD1@

R154 0_0402_5%HDD2@R154 0_0402_5 %HDD2@
R157 0_0402_5%HDD2@R157 0_0402_5 %HDD2@
R160 0_0402_5%HDD2@R160 0_0402_5 %HDD2@
R161 0_0402_5%HDD2@R161 0_0402_5 %HDD2@

1 2

R121 37.4 _0402_1%

R121 37.4 _0402_1%

1 2

R126 49.9 _0402_1%

R126 49.9 _0402_1%

1 2

R440 750 _0402_1%

R440 750 _0402_1%

SPI_CLK_PCH_R
SPI_SI

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

C1185 0 .01U_0402_16V7KC1185 0 .01U_0402_16V7K

12

C1208 0 .01U_0402_16V7KC1208 0 .01U_0402_16V7K

+1.05VS_VTT

+1.05VS_VTT

No use PH 10K +3VS

Deciphered Date

Deciphered Date

Deciphered Date

12
12
12
12

12
12
12
12

C459

C459
10P_0402_50V8J

10P_0402_50V8J

1 2

@

@

D

SATA_PTX_R_DRX_N1_CO
SATA_PTX_R_DRX_P1_CO

R434 33_ 0402_5%@

R434 33_ 0402_5%@

SATA_PRX_DTX_C_N0 <31>
SATA_PRX_DTX_C_P0 <31>
SATA_PTX_DRX_N0 <31>
SATA_PTX_DRX_P0 <31>

SATA_DTX_C_PRX_N1

SATA_DTX_C_PRX_P1
SATA_PTX_R_DRX_N1_CO
SATA_PTX_R_DRX_P1_COSATA_PTX_DRX_P2

Reserve for EMI

12

SPI_CLK_PCH_R

SERIRQ

R118 10K_0402_5%

R118 10K_0402_5%

12

SSD

12

C1209 0.01U_0402_16V7KC1209 0.01U_0402_16V7K

12

C1223 0.01 U_0402_16V7KC1223 0.01U_0402_16V7K

SATA_DTX_C_PRX_N1 <35>
SATA_DTX_C_PRX_P1 <35>
SATA_PTX_R_DRX_N1 <35>
SATA_PTX_R_DRX_P1 <35>

HDD0 w/ HM77
Disable w/ HM70

HDD1 w/ HM70

GPIO19 has internal Pull up
GPIO21 Debug Port DG 1.2 PH 4.7K +3VS

BBS_BIT0_R

PCH_SATALED#

PCH_GPIO21

R466 10K_0402_5%

R466 10K_0402_5%

R429 10K_0402_5%

R429 10K_0402_5%

R136 10K_0402_5%

R136 10K_0402_5%

Boot BIOS Strap

Boot BIOS

LPC

Reserved

-

SPI

*

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Documen t Number Rev

Size Documen t Number Rev

Size Documen t Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

LA-8952P

LA-8952P

LA-8952P

12

12

12

GPIO51

0 0
0
1
1 1

GPIO19

E

+3VS

1
0

13 55Thursday, January 10 , 2013

13 55Thursday, January 10 , 2013

13 55Thursday, January 10 , 2013

+3VS

0.1

0.1

0.1

A

PCIE_DTX_C_PRX_N1<32>

PCIE LAN

WLAN

1 1

+3VS

R424 10K_0402_5%

R424 10K_0402_5%

R110 10K_0402_5%

R110 10K_0402_5%

+3V_PCH

R414 10K_0402_5%

R414 10K_0402_5%

R389 10K_0402_5%

R389 10K_0402_5%

R53 10K_0402_5%

R53 10K_0402_5%

R50 10K_0402_5%

R50 10K_0402_5%

R32 10K_0402_5%

R32 10K_0402_5%

R51 10K_0402_5%

R51 10K_0402_5%

R54 10K_0402_5%

R54 10K_0402_5%

PCIE LAN

2 2

No use PH 10K +3VALW

WLAN

No use PH 10K +3VS

PCIE_DTX_C_PRX_P1<32>
PCIE_PTX_C_DRX_N1<32>
PCIE_PTX_C_DRX_P1<32>

PCIE_PRX_DTX_N2<31>

PCIE_PRX_DTX_P2<31>
PCIE_PTX_C_DRX_N2<31>
PCIE_PTX_C_DRX_P2<31>

12

12

12

12

12

12

12

12

12

CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>

LAN_CLKREQ#<32>

CLK_PCIE_WLAN1#<31>
CLK_PCIE_WLAN1<31>

WLAN_CLKREQ#<31>

WLAN_CLKREQ#_R

PCH_GPIO20

PCH_GPIO25

LAN_CLKREQ#_R

PCH_GPIO26

PCH_GPIO44

PCH_GPIO45

PCH_GPIO46

PCH_GPIO56

1 2

C480 0.1U_0402_16V7KC480 0.1U _0402_16V7K

1 2

C478 0.1U_0402_16V7KC478 0.1U _0402_16V7K

1 2

C482 0.1U_0402_16V7KC482 0.1U _0402_16V7K

1 2

C481 0.1U_0402_16V7KC481 0.1U _0402_16V7K

HM70 not support
PCI

1 2

R153 0_0402_5%@R 153 0_0402_5%@

1 2

R163 0_0402_5%@R 163 0_0402_5%@

1 2

R164 0_0402_5%@R164 0_0402_5%@

1 2

R165 0_0402_5%@R 165 0_0402_5%@

1 2

R166 0_0402_5%@R 166 0_0402_5%@

1 2

R167 0_0402_5%@R 167 0_0402_5%@

use PH 10K +3VS

No

E port 4-7

No use PH 10K +3VALW

No use PH 10K +3VALW

3 3

No use PH 10K +3VALW

No use PH 10K +3VALW

No

use PH 10K +3VALW

No use PH 10K +3VALW

4 4

B

PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

LAN_CLKREQ#_R

CLK_PCIE_WLAN1#_R
CLK_PCIE_WLAN1_R

WLAN_CLKREQ#_R

PCH_GPIO20

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

PCIE_CLK_8N
PCIE_CLK_8P

U13B

U13B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GP IO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GP IO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GP IO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GP IO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GP IO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GP IO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GP IO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GP IO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

PANTHER_FCBGA989

PANTHER_FCBGA989

HM77@

HM77@

SMBUSController

SMBUSController

SML1ALERT# / PC HHOT# / GPIO74

PCI-E*

PCI-E*

CLOCKS

CLOCKS

CLKOUT_DP_N / C LKOUT_BCLK1_N

CLKOUT_DP_P / C LKOUT_BCLK1_P

C

SMBALERT# / GP IO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO 60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO7 5

CL_CLK1

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKIN_SATA_N / CKS SCD_N

CLKIN_SATA_P / CKS SCD_P

FLEX CLOCKS

FLEX CLOCKS

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_DMI2_N
CLKIN_DMI2_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / G PIO64

CLKOUTFLEX1 / G PIO65

CLKOUTFLEX2 / G PIO66

CLKOUTFLEX3 / G PIO67

E12

PCH_GPIO11

H14

C9

PCH_SMBDATA

A12

DRAMRST_CNTRL_PC H

C8

PCH_SML0CLK

G12

PCH_SML0DATA

C13

PCH_HOT#

E14

PCH_SML1CLK

M16

PCH_SML1DATA

M7

T11

P10

M10

PEG_CLKREQ#_R

AB37

CLK_PCIE_VGA#_R

AB38

CLK_PCIE_VGA_R

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12
AM13

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_GND1#

BG30

CLKIN_GND1

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

W=12mil S=15mil

Y47

XCLK_RCOMP

K43

F47

H47

LAN_48M

K49

DGPU_PRSNT#

R56 10K_0402_5%

R56 10K_0402_5%

1 2

R207 22_0402_5%@R207 22_0402_5%@

D

No use PH 10K +3VALW

EC LID SW OUT

R,WLAN,XDPSMBUS

DD

PH 2.2K +3VALW

DRAMRST_CNTRL_PC H <7>

S3 reduse

PCH_HOT# <37>

No use PH 10K +3VALW

No use PH 10K +3VALW

EC-PCH SMBUS

H

2.2K +3VALW

P

@

@

12

R9

R9
0_0402_5%

0_0402_5%

PX@

PX@

1 2

R58 0_04 02_5%@R58 0_0402_5%@

12

CLK_PCIE_VGA#

12

CLK_PCIE_VGA

R59 0_04 02_5%@R59 0_0402_5%@

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

1 2

R152 10K_0402_5%

R152 10K_0402_5%

1 2

R147 10K_0402_5%

R147 10K_0402_5%

1 2

R453 10K_0402_5%

R453 10K_0402_5%

1 2

R452 10K_0402_5%

R452 10K_0402_5%

1 2

R99 10K_0402_5%

R99 10K_0402_5%

1 2

R93 10K_0402_5%

R93 10K_0402_5%

1 2

R139 10K_0402_5%

R139 10K_0402_5%

1 2

R138 10K_0402_5%

R138 10K_0402_5%

1 2

R101 10K_0402_5%

R101 10K_0402_5%

R96

@R96

@

33_0402_5%

33_0402_5%

Reserve for EMI please close to PCH

R120

R120

90.9_0402_1%

90.9_0402_1%

1 2

PCH_LAN_48M

PEG_CLKREQ# <23>

No use PH 10K +3VALW

12

C29 22P_0402_50V8J@C29 22P_0402_50V8J@

+1.05VS_VTT

DGPU_PRSNT#

DI

CLK_PCIE_VGA# <22>
CLK_PCIE_VGA <22>

1 2

UMA@

UMA@

S,Optimus

UMA

PCH_GPIO11

PCH_SMBCLKPCH_SMBCLK

PCH_SMBDATA

DRAMRST_CNTRL_PC H

PCH_HOT#

PCH_SML1CLK

PCH_SML1DATA

PEG_CLKREQ#_R

6 1

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

PCH_SML1DATA

PCH_SML1CLK

Pull down 10K ohm
for using internal Clock

+3VS

12

R421

R421
10K_0402_5%

10K_0402_5%

R420

R420
10K_0402_5%PX@

10K_0402_5%PX@

1 2

GPIO67

DGPU_PRSNT#

6 1

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

CLK_PCI_LPBACK <17>

0
1

1 2

R33 10K_0402_5%

R33 10K_0402_5%

1 2

R405 2.2K_0402_5%

R405 2.2K_0402_5%

1 2

R370 2.2K_0402_5%

R370 2.2K_0402_5%

1 2

R391 1K_0402_5%

R391 1K_0402_5%

1 2

R392 10K_0402_5%

R392 10K_0402_5%

1 2

R403 2.2K_0402_5%R403 2.2K_0402_5%

1 2

R369 2.2K_0402_5%R369 2.2K_0402_5%

UMA@

UMA@

1 2

R25 10K_0402_5%

R25 10K_0402_5%

+3VS

2

Q34A

Q34A

3 4

Q34B

Q34B

+3VS

2

Q33A

Q33A

3 4

XTAL25_IN

XTAL25_OUT

10P_0402_50V8J

10P_0402_50V8J

For DDR

R404

R404

2.2K_0402_5%

2.2K_0402_5%

1 2

SMB_DATA_S3PCH_SMBDATA

R371

R371

2.2K_0402_5%

2.2K_0402_5%

5

1 2

SMB_CLK_S3

Pull up at EC side.
For VGA,EC,Thermal sensor

EC_SMB_DA2

5

EC_SMB_CK2

Q33B

Q33B

1

25MHZ_10PF_7V25000014

25MHZ_10PF_7V25000014

C457

C457

2

E

+3V_PCH

+3VS

SMB_DATA_S3 <12,31,38>

+3VS

SMB_CLK_S3 <12,31,38>

EC_SMB_DA2 <23,34,37>

EC_SMB_CK2 <23,34,37>

+3V_PCH

R551

R551

2.2K_0402_5%

2.2K_0402_5%

OSC

NC

1 2

4

NC

1

OSC

PCH_SML0CLK

PCH_SML0DATA

1 2

R431 1M_0402_5%

R431 1M_0402_5%

3

2

Y3

Y3

SJ10000E500

SJ10000E500

R545

R545

2.2K_0402_5%

2.2K_0402_5%

1 2

1

2

C468

C468

10P_0402_50V8J

10P_0402_50V8J

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

LA-8952P

LA-8952P

LA-8952P

E

14 5 5Thursday, January 10, 2013

14 5 5Thursday, January 10, 2013

14 5 5Thursday, January 10, 2013

0.1

0.1

0.1

A

+3V_PCH

R26 200K_0402_ 5%

R26 200K_0402_ 5%

+3V_PCH

1 1

R34 10K_0402_5 %R34 10K_0402_5 %

R49 10K_0402_5 %R49 10K_0402_5 %

R390 10K_0402_5 %

R390 10K_0402_5 %

R393 300_0402_5 %R39 3 300_0402_5 %

R394 10K_0402_5 %

R394 10K_0402_5 %

+3VS

not support Deep S4,S5
can be left unconnected.
Check list1.5 P.81

2 2

R397

@R397

@

@

@

12

12

12

12

12

12

12

200_0402_5 %

200_0402_5 %

Follow G

AC_PRESENT_R

SUSWARN#_R

PCH_GPIO72

RI#

PM_DRAM_PW RGD

PCH_RSMRST#

PM_DRAM_PW RGD

For DS3

SUSACK#<37>

not support AMT APWROK can mux
wi

th PWROK (check list1.5 P.47)

R191 0_ 0402_5%@R1 91 0_0402_5%@

AEPWROK can be connect to
PWROK if iAMT disable

+3VALW

R195 200K_0402_ 5%R195 200K_0402_ 5%

12

12

APWROKPCH_PW ROK_R

PCH_APWROK<37>

For DS3

AC_PRESENT_R

PCH_PWROK

PM_DRAM_PW RGD<6>

EC_RSMRST#<37>

SUSWARN#<37>

PBTN_OUT#<37 >

ACIN<23,3 7,43>

No use PH 10K +3VALW

3 3

Ring Indicator CRB1.0 PH 10K +3VALW

B

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5 >
DMI_CTX_PRX_P1<5 >
DMI_CTX_PRX_P2<5 >
DMI_CTX_PRX_P3<5 >

DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5 >
DMI_CRX_PTX_P1<5 >
DMI_CRX_PTX_P2<5 >
DMI_CRX_PTX_P3<5 >

+1.05VS_VTT

R156 49.9_0 402_1%

R156 49.9_0 402_1%

R155 750_0402 _1%

R155 750_0402 _1%

4mil width and place
within 500mil of the PCH

R1468

R1468

+3VS

R107 0_0402_5%@R10 7 0_0402_5%@

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

L=500mil S=15mil

1 2

1 2

1 2

R415 10K_0402_ 5%

R415 10K_0402_ 5%

1 2

1 2

R303 0 _0402_5%@R303 0_0402_5 %@

0_0402_5%

0_0402_5%

1 2

R125

@ R125

@

R1489 0_0402_5 %@R1489 0_0402_5%@

1 2

@ R129

@

D3

D3

1 2

RB751V-40_SOD3 23-2

RB751V-40_SOD3 23-2

0_0402_5%

0_0402_5%
R129

DMI_IRCOMP

DMI2RBIAS

0_0402_5%@

0_0402_5%@

12

XDP_DBRESET#_R

SYS_PWROK

PCH_PWROK_R

PM_DRAM_PW RGD

PCH_RSMRST#

12

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

SUSACK#_R

APWROK

C

U13C

U13C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER_FCBGA989

PANTHER_FCBGA989

HM77@

HM77@

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK

PCH_PCIE_WAKE #

CLKRUN#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

SLP_A#

SLP_SUS#

H_PM_SYNC

PCH_GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

DMI

System Power Management

System Power Management

FDI_RXP6

FDI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

D

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 < 5>
FDI_CTX_PRX_P1 < 5>
FDI_CTX_PRX_P2 < 5>
FDI_CTX_PRX_P3 < 5>
FDI_CTX_PRX_P4 < 5>
FDI_CTX_PRX_P5 < 5>
FDI_CTX_PRX_P6 < 5>
FDI_CTX_PRX_P7 < 5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

@

@

1 2

R133 0_0402 _5%

R133 0_0402 _5%

PCH_RSMRST#

T1 PAD@T1 PAD@

T4 PAD@T4 PAD@

H_PM_SYNC <6>

DSWODVREN

DSWODVREN - On Die DSW VR Enable

H

：：：：

Enable internal DSW +1.05VS

*

：：：：

Disable

L
Must always PH at +RTCVCC

PCH_PCIE_WAKE #

PCH_GPIO29

CLKRUN#

For DS3

PCH_DPWROK

R135 0_0402_ 5%@R135 0_0402_5%@

not support Deep S4,S5 DPWROK mux with RSMRST#
check list1.5 P.50

PCH_PCIE_WAKE # <31,32>

12

R375

R375
10K_0402_5 %

10K_0402_5 %

SUSCLK <37>

PM_SLP_S5# <37>

PM_SLP_S4# <37>

PM_SLP_S3# <37>

0111 Add R375 to GND

Can be left NC
when IAMT is not
support on the
platfrom

SLP_SUS# <37, 40>

For DS3

If Intel LAN no use, can let be NC.

E

R350 330K_040 2_5%

R350 330K_040 2_5%

R368 330K_040 2_5%@R368 330K_0402_5%@

R374 10K_0402 _5%

R374 10K_0402 _5%

R36 10K_0 402_5%@R36 10K_0402_ 5%@

R423 8.2K_040 2_5%

R423 8.2K_040 2_5%

12

12

12

1 2

1 2

@

@

1 2

DPWROK_EC <37>

not support
Deep S4,S5 can NC
PCH EDS1.5 P.75

+RTCBATT

+3V_PCH

+3VS

tell PCH all power ok
bu

t cpu core

A

PCH_PWROK

12

R104

R104
10K_0402_5 %

10K_0402_5 %

VGATE<50>

PCH_PWROK<37>

4 4

+3VS

5

U36

U36

2

P

B

1

A

G

MC74VHC1G08DFT2G_ SC70-5

MC74VHC1G08DFT2G_ SC70-5

3

Y

4

ALL power OK

SYS_PWROK

B

12

R119

R119
100K_0402_ 5%

100K_0402_ 5%

SYS_PWROK <6>

1

C52

C52

0.047U_0402 _16V7K

0.047U_0402 _16V7K

2

@

@

Security Classification

Security Classification

Security Classification

2011/06/24 2012/0 7/12

2011/06/24 2012/0 7/12

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/0 7/12

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Do cument Number Rev

Size Do cument Number Rev

Size Do cument Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM

PCH (3/9) DMI,FDI,PM

PCH (3/9) DMI,FDI,PM

LA-8952P

LA-8952P

LA-8952P

E

of

15 55Thursday, January 1 0, 2013

15 55Thursday, January 1 0, 2013

15 55Thursday, January 1 0, 2013

0.1

0.1

0.1

A

+3VS

1 1

R108 2.2K_0402_5%R108 2.2K_0402_5%

R105 2.2K_0402_5%R105 2.2K_0402_5%

Change to eDP only

1 2

1 2

CTRL_CLK

CTRL_DATA

DIS only can NC

UMA LVDS DDC

1 2

R428 2.2K_0402_5%R428 2.2K_0402_5%

R425 2.2K_0402_5%R425 2.2K_0402_5%

1 2

EDID_CLK

EDID_DATA

Check list1.5 P.60 disable Graphics
ALL Can NC
but DAC_IREF still need PD

LVDS disable:
DATA/Clock/Control an NC
VCC_TX_LVDS,VCCA_LVDS PD to GND

2 2

CRT disable:
DATA/Clock/Control an NC

UM77 not support

VD

S/CRT

L

VCCADAC connect to +3VS
DAC_IREF connect 1K_0402_5%

3 3

B

PCH_ENBKL<29>
PCH_ENVDD<29>

PCH_PWM<29>

EDID_CLK<29>
EDID_DATA<29>

L=500mil S=20mil

R132

R132

10mil S=30mil

W=

LVDS_ACLK#<29>
LVDS_ACLK<29>

LVDS_A0#<29>
LVDS_A1#<29>
LVDS_A2#<29>

LVDS_A0<29>
LVDS_A1<29>
LVDS_A2<29>

CRT disable
us

2.37K_0402_1%

2.37K_0402_1%

12

1K_0402_5%

1K_0402_5%

e 1K_0402_5%

PCH_ENBKL

CTRL_CLK
CTRL_DATA

LVDS_IBG

LVD_VREF

LVDS_ACLK#
LVDS_ACLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

12

R114

R114

CRT_IREF

U13D

U13D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER_FCBGA989

PANTHER_FCBGA989

HM77@

HM77@

C

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39

2.2K_0402_5%

2.2K_0402_5%

AP40

P38

HDMICLK_NB

M39

HDMIDAT_NB

AT49
AT47
AT40

TMDS_B_HPD#

AV42

TMDS_B_DATA2#_PCH

AV40

TMDS_B_DATA2_PCH

AV45

TMDS_B_DATA1#_PCH

AV46

TMDS_B_DATA1_PCH

AU48

TMDS_B_DATA0#_PCH

AU47

TMDS_B_DATA0_PCH

AV47

TMDS_B_CLK#_PCH

AV49

TMDS_B_CLK_PCH

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

CRT

CRT

DDPD_HPD

R144

R144

HDMI@

HDMI@

D

+3VS

12

12

R131

R131

2.2K_0402_5%

2.2K_0402_5%

HDMI@

HDMI@

HDMICLK_NB <30>
HDMIDAT_NB <30>

TMDS_B_HPD# <30>

C406 0.1U_0402_10V6KHDMI@ C406 0.1U_0402_10V6KHDMI@

1 2
1 2

C352 0.1U_0402_10V6KHDMI@ C352 0.1U_0402_10V6KHDMI@

1 2

C539 0.1U_0402_10V6KHDMI@ C539 0.1U_0402_10V6KHDMI@

1 2

C538 0.1U_0402_10V6KHDMI@ C538 0.1U_0402_10V6KHDMI@

1 2

C535 0.1U_0402_10V6KHDMI@ C535 0.1U_0402_10V6KHDMI@
C534 0.1U_0402_10V6KHDMI@ C534 0.1U_0402_10V6KHDMI@

1 2
1 2

C537 0.1U_0402_10V6KHDMI@ C537 0.1U_0402_10V6KHDMI@

1 2

C536 0.1U_0402_10V6KHDMI@ C536 0.1U_0402_10V6KHDMI@

Place close to connector side

E

HDMI_TX2-_CK <30>
HDMI_TX2+_CK <30>
HDMI_TX1-_CK <30>
HDMI_TX1+_CK <30>
HDMI_TX0-_CK <30>
HDMI_TX0+_CK <30>
HDMI_CLK-_CK <30>
HDMI_CLK+_CK <30>

HDMI

HDMI D2

HDM

I D1

HDMI D0

HDMI CLK

4 4

Security Classification

Security Classification

Security Classification

2011/06/24 2012/07/12

2011/06/24 2012/07/12

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

LA-8952P

LA-8952P

LA-8952P

16 55Thursday, January 10, 2013

16 55Thursday, January 10, 2013

16 55Thursday, January 10, 2013

E

0.1

0.1

0.1

of

A

+3VS

R90

R90

18

PCI_PIRQC#

27

PCI_PIRQB#

36

PCI_PIRQA#

45

R409

R409

18
27
36
45

PCI_PIRQD#

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PXS_PWREN_R

PCH_GPIO51

PCH_WL_OFF#

PCH_GPIO53

PCH_GPIO52

PCH_GPIO5

DGPU_HOLD_RST#_R

USB3.0

8.2K_1206_8P4R_5%

1 1

2 2

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%

1 2

R408 8.2K_0402_5%R408 8.2K_0402_5%

1 2

R418 8.2K_0402_5%R418 8.2K_0402_5%

1 2

R432 8.2K_0402_5%R432 8.2K_0402_5%

1 2

R433 8.2K_0402_5%R433 8.2K_0402_5%

1 2

R401 8.2K_0402_5%R401 8.2K_0402_5%

+3VS

1 2

R66 8.2K_0402_5%R66 8.2K_0402_5%

1 2

R41 8.2K_0402_5%@R41 8.2K_0402_5%@

Boot BIOS Strap

Boot BIOS

GPI

O51GPIO19

GNT1#/
GPIO51

Internal
PH

CR Check list 1.5 only use for GPIO

No use PH +3VS

Only GPIO
fun

ction

3 3

4 4

PCH_WL_OFF#

R215 1K_0402_5%@R215 1K_0402_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

PCH_PLTRST#

DGPU_HOLD_RST#

Bit11

0 1

1

1 1

CR Check list 1.5 only use for GPIO

無無無無無無無無

PH(Internal PH),

1 2

A

Destination

Bit10

Reserved

0

00

如如如如如如如如

GPIO55

*

R10 0_0402_5%@R10 0_0402_5%@

U25

@U25

@
2

1

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

U29

PX@U29

PX@
2

1

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

PCI

SPI

*

LPC

GPIO PH +3VS

CLK_PCI_LPBACK<14>

12

+3VS

5

P

B

4

Y

A

G

3

+3VS

5

P

B

4

Y

A

G

3

PXS_PWREN<24,49>

CLK_PCI_EC<37>

CLK_PCI_DB<31>

12

R11

R11

100K_0402_5%

100K_0402_5%

DGPU_HOLD_RST#

R6

12

0_0402_5%@R60_0402_5%@

B

USB3_RX2_N<39>

USB3_RX2_P<39>

USB3_TX2_N<39>

USB3_TX2_P<39>

PCI Interrupt Requests

R55 0_0402_5% @R55 0_0402_5% @

R57 0_0402_5% @R57 0_0402_5% @

PCH_WL_OFF#<31>

CLK_PCI_LPBACK

CLK_PCI_EC

R417 22_0402_5%

R417 22_0402_5%
R84 22_0402_5%

R84 22_0402_5%
R340 22_0402_5%

R340 22_0402_5%

PLT_RST# <31,32,37>

GPU_RST# <22>

B

12

12

PCI_PME#<37>

PCH_PLTRST#<6>

1 2
1 2

@

@

USB3_RX2_N

USB3_RX2_P

USB3_TX2_N

USB3_TX2_P

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#_R

PCH_GPIO52

PXS_PWREN_R

PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5

PCI_PME#

PCH_PLTRST#

12

CLK_PCI0
CLK_PCI1
CLK_PCI2CLK_PCI_DB

U13E

U13E

BG26

BJ26

BH25

BJ16
BG16
AH38
AH37
AK43
AK45

C18
N30

H3

AH12

AM4
AM5

Y13
K24

L24
AB46
AB45

B21

M20
AY16
BG46

BE28
BC30
BE32

BJ32
BC28
BE30

BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28

AW30

K40
K38
H38
G38

C46
C44
E40

D47
E42
F46

G42
G40
C42
D44

K10

C6

H49
H43
J48
K42
H40

PANTHER_FCBGA989

PANTHER_FCBGA989

HM77@

HM77@

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

TP21
TP22
TP23
TP24

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PME#

PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

C

AY7

NV_CE#0

AV7

NV_CE#1

AU3

NV_CE#2

BG4

NV_CE#3

AT10

NV_DQS0

BC8

NV_DQS1

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC5# / GPIO9

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AY1

DF_TVS

AV10

AT8

AY5
BA2

AT12
BF3

C24
A24
C25

USB20_N1

B25

USB20_P1

C26

USB20_N2

A26

USB20_P2

K28

USB20_N3

H28

USB20_P3

E28
D28
C28
A28
C29

HM70 not support USB port 4,5,6,7,12,13

B29
N28
M28
L30

USB20_N8

K30

USB20_P8

G30

USB20_N9

E30

USB20_P9

C30

USB20_N10

A30

USB20_P10

L32

USB20_N11

K32

USB20_P11

G32
E32
C32
A32

C33

USBRBIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

USB20_N1 <39>
USB20_P1 <39>
USB20_N2 <31>
USB20_P2 <31>
USB20_N3 <29>
USB20_P3 <29>

12/12/24 add touch function

USB20_N8 <38>
USB20_P8 <38>
USB20_N9 <38>
USB20_P9 <38>
USB20_N10 <38>
USB20_P10 <38>
USB20_N11 <29>
USB20_P11 <29>

0110 modify WLAN USB port to USB8
Port9 is for debug.

1 2

R399 22.6_0402_1%

R399 22.6_0402_1%

L=500mil S=15mil

Compal Secret Data

Compal Secret Data

2011/06/24 2012/07/12

2011/06/24 2012/07/12

2011/06/24 2012/07/12

Compal Secret Data

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10

NVRAM

NVRAM

NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

RSVD

RSVD

NV_RE#_WRB0
NV_RE#_WRB1

NV_WE#_CK0
NV_WE#_CK1

PCI

PCI

USB

USB

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC6# / GPIO10
OC7# / GPIO14

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

USB3 (Left side)

Mini Card (WLAN)

Touch Panel

USB2 (Right side)

USB2 (Right side)

Card Reader

CMOS Camera (LVDS)

USB_OC0# <39>

USB_OC4# <38>

Deciphered Date

Deciphered Date

Deciphered Date

D

Card reader

EHCI 1

EHCI 2

E

DMI,FDI Termination Voltage

DF_TVS

Set to Vcc when HIGH

Set to Vss when LOW

HR CPU NC

CR CPU PD

CR Check list P.89 PH 2.2K series 1K

+1.8VS

12

R145

R145

2.2K_0402_5%

2.2K_0402_5%

DF_TVS

R146 1K_0402_5%

R146 1K_0402_5%

CLOSE TO THE BRANCHING POINT

USB_OC0#
USB_OC7#
USB_OC5#
USB_OC6#

USB_OC1#
USB_OC4#
USB_OC3#
USB_OC2#

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

10K_1206_8P4R_5%

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

10K_1206_8P4R_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH (5/9) PCI, USB, NVRAM

PCH (5/9) PCI, USB, NVRAM

PCH (5/9) PCI, USB, NVRAM

LA-8952P

LA-8952P

LA-8952P

R351

R351

R349

R349

H_SNB_IVB# <6>

+3V_PCH

+3V_PCH

E

17 55Thursday, January 10, 2013

17 55Thursday, January 10, 2013

17 55Thursday, January 10, 2013

0.1

0.1

0.1