Lenovo IDEAPAD S340 schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

EL432/EL532

M/B Schematic Documents

AMD Picasso FP5 APU with DDR4

3 3

4 4

curity Classification

curity Classification

curity Classification

Se

Se

Se

ed Date

ed Date

ed Date

Issu

Issu

Issu

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

LA-H131P

2018-11-05

v : 0.4

Re

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

20

20

20

C

Co

Deciphered Date

Deciphered Date

Deciphered Date

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

tle

tle

tle

Ti

Ti

Ti

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Date : Sheet

Date : Sheet

D

Date : Sheet

Co

ver Page

ver Page

ver Page

Co

Co

Co

-H131P

-H131P

-H131P

LA

LA

LA

E

o f

1 4

o f

1 4

o f

1 4

4

4

4

0.

0.

0.

6Monday, November 05, 2018

6Monday, November 05, 2018

6Monday, November 05, 2018

A

www.schematic-x.blogspot.com

B

C

D

E

DDR4 2400MHz

NGFF (Key M)

IE/SATA SSD

1 1

PC
2242/2280 conn.

Ie/SATA Mux

PC

ricom PI3DBS12212A

Pe

PCIe x3 , Gen3 8Gb/s

PCIe x1 , Gen3 8Gb/s

SATA x1 , Gen3 6Gb/s

USB2.0 x 1, 480Mb/s

CH-A DDR4-SO-DIMM X1
CH-B on board RAM x4

B Charger

US

TI SN1702001RTER

USB2.0 x1, 480Mb/s

B3.0 Conn.

US
with AOU

B3.1 x1, 5Gb/s

F (Key E)

NGF

AN/BT5.0

WL
2230 conn.

P Panel

eD

FHD LCD

PCIe x1 , Gen1 2.5Gb/s

USB2.0 x 1, 480Mb/s

P x2 HBR 2.7Gb/s

eD

AMD Picasso Ridge

1140pin BGA

2 2

I x4 , 2.97GT/s

MI Conn.

HD

MI1.4b

HD

D Conn.

HD

DD

TA x1 , Gen3 6Gb/s

SA

US

B3.1 x1, 5Gb/s

US

B2.0 x1, 480Mb/s

US

USB2.0 x 1, 480Mb/s

USB2.0 x 1, 480Mb/s

PCIe x1 , Gen1 2.5Gb/s

VBus

pe-C Conn.

3 3

Ty

B3.1 Gen1

US

CC/Vconn

USB3.1x1, Gen 1

Switch

5V

MUX/CC

Realtek RTS5448

B2.0 x1, 480Mb/s

US

USB3.1x1, Gen 1

A

HD

I2C

SPI

LPC

B3 redriver

US

Parade PS8713B

B3 redriver

US

rade PS8713B

Pa

. Camera

Int

Touch Panel

Card Reader

altek RTS5232S

Re

dio Codec

Au

Realtek
ALC3287-CG

uchPad

To

I ROM

SP

8MB

USB3.1 x1, Gen1 5Gb/s

USB3.1 x1, Gen1 5Gb/s

B2.0 Hub

US

ngerPr int

Fi

SDIO

HP

SPK

DMIC

B3.0 Conn.

US

On Sub Board

serve

Re

SD Card Conn.

On Sub Board

Combo Jack

Int. Speaker

t. Array Mic *2

In

t. KBD

In

4 4

ll Sensor x1

Ha

KBC

EN

E KB9022

LED

curity Classification

curity Classification

curity Classification

Se

Se

Se

Issued Date

Issued Date

Issued Date

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

TH

TH

TH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPALELECTRONICS,I NC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPALELECTRONICS,I NC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPALELECTRONICS,I NC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

20

20

20

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

Deciphered Date

Deciphered Date

Deciphered Date

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

Co

tle

tle

tle

Ti

Ti

Ti

Size

Size

Size

D

D

D

Date: Sheet

Date: Sheet

Date: Sheet

ver Page

ver Page

ver Page

Co

Co

Co

Document Number Rev

Document Number Rev

Document Number Rev

-H131P

-H131P

-H131P

LA

LA

LA

E

2 4

2 4

2 4

6Monday, Novembe r 05, 201 8

6Monday, Novembe r 05, 201 8

6Monday, Novembe r 05, 201 8

of

of

of

4

4

4

0.

0.

0.

A

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

+APU_CO RE_SOC ON

TC_APU

+R

+3VALW 3.3V always on power rail

1 1

+3VS

+1.8VALW

.8VS

+1

.8VALW

+0

.8VS

+0

.2V_DDR

+1

+2.5V_MEM 2.5V power rail for DDR

+0.6VS_VTT

+5VALW

VS

+5

BUS Control Table

SM

2 2

_SMB_CK1

EC
EC_SMB_DA1

U_SCLK0

AP
APU_SDATA0

EC_SMB_CK2
EC_SMB_DA2

Adapter power supply

AC or battery power rail for power circuit.

Core voltage for APU

Core voltage for APU

C power

RT

3.3V switched power rail

8V always on power rail

1.

1.8V switched power rail

0.95V always on power rail

0.95V switched power rail

1.2V power rail for APU and DDR

6V switched power rail f or DDR terminator

0.

5V always on power rail

5V switched power rail

SOURCE

902 2

+3VALW

APU

+3VS

902 2

+3VS

APU

X V

X

V

+1.8VS

TT

BA

VALW

+3

X X

EC

V

+3VALW

V

+3VALW

S0 S3 S5

ON ON ON

ON

N ON

N

ON

ON O

N

O

ON

ON

ON

N ON

O

ON

ON

SODIMM

X

VX X

+3VS

OFF

OFF OFF

ONO

OF

OFF OFF

ON ON

OF

ON

OF

ON ON

OFF OFF

AN

WL

X

X

X

ONONON

OFF

ONO

ON

F OFF

F OFF

OFF

OFF

FONOFF

B

STATE

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF) LOW

NON

SIGNAL

SLP_S3# SLP _S5# +VALW +V +VS Clock

HIGH

HIGH

ON

ON

ON

HIGH HIGH

HIGH

LOW

ON

M STRUCTURE DESCR IPT IO N

BO

@

14

@

15

R@

OB

_OB R@

NO
SDP @
DDP @
SINGL E_M IC @
MULTI _M IC@
KBL @

" Only Components

14

" Only Components

15

Board RAM SKU Only

On

On Board RAM SKU Only

No

Memory Down - SDP Package

Memory Down - DDP Package

MIC Select Strap (1 MIC)

MIC Select Strap (2 MIC)

Keyboard Backlight

C

ON ON ON

ON

OFF

OFF

OFF

OFF

OFFLOW

BOM STRUCTURE

BOM STRUCTURE DESCR IPT IO N

Ryzen 5_ PR@

OFF

OFF

OFF

Ryzen 7_ PR@
45@
14_DA Z_ R0@
15_DA Z_ R0@
X4E @
X76R AM@
S4G_ MD@
H4G_ MD@
M4G_ MD@
HDT @
EMI @
ESD @
RF@

@

TS

D

Ryzen5 CPU (PR Sample)

Ryzen7 CPU (PR Sample)

HDMI Logo

14" DAZ (Rev0 PCB)

15" DAZ (Rev0 PCB)

43J X4E Level

On Board RAM X76 Resistors

On Board RAM (Samsung 4GB)

On Board RAM (Hynix 4GB)

On Board RAM (Micron 4GB)

HDT Debugging ME Components

EMI Components

ESD Components

RF Components

uch Screen

To

BOM STRUCTURE DESC RIP TIO N

Ryzen 3_ PC@
Ryzen 3_ PR@
Ryzen 5_ PC@
Ryzen 7_ ES@
Ryzen 7_ PC@
@
@EM I@
@ES D@
20V_P RT CT@
FP@
ME@

_TH M@

EX

B@

HU
DA_R 0@

_R1 @

DA

_DAZ _R 1@

14
15_DA Z_ R1@

@

RD

@

TI

RAD E@

PA

RIC OM@

PE

6_T I@

X7

6_PA RAD E@

X7

6_PER IC OM@

X7

E

Ryzen3 CPU (PC Sample)

Ryzen3 CPU (PR Sample)

Ryzen5 CPU (PC Sample)

Ryzen7 CPU (ES Sample)

zen7 CPU (PC Sample)

Ry

-Mount Components

Un

I Un-Mount Components

EM

ESD Un-Mount Components

5448 EXT Voltage Protection

Finger Printer (Reserved)

ermal Sensor

Th

B2.0 HUB

US

PCB Part Number (Rev0 PCB)

B Part Number (Rev1 PCB)

PC

14" DAZ (Rev1 PCB)

" DAZ (Rev1 PCB)

15

B3.0 Re-Driver BOM

US

Re-Driver Only

TI

rade Re-Driver Only

Pa

ricom Re-Driver Only

Pe

Re-Driver X76 Level

TI

rade Re-Driver X76 Level

Pa

ricom Re-Driver X76 Level

Pe

EC SM Bus1 address EC SM Bus2 address

dress HEX

vice

De

art Battery 0001 011x b

Sm

Charger 0001 0010 b

AP

3 3

SM Bus 0

Ad

U SM Bus address

vice

De

DDR DIMM1

Ad

10 001Xb

10

De

APU

H

16

H

12

dress HEX

A2

vice

H

APU I2C Bus address

Touch Pad (Synaptics)

I2C 3

uch Pad (Elan)

To

USB3.0 Port (USB_0)

POR T F UNCT IO N

0

Type-C

1

Sub/B USB3.0 Type-A

2

Sub/B USB3.0 Type-A

3
4

4 4

AddressDevice

$2C

15

0X

USB2.0 Port

PO

USB2.0 Hub

POR T FUNCT ION

A

dress HEX

Ad

01 100X b

10

RT FUNC TIO N

0
1
2
3
4
5

1
2

pe-C

Ty

Sub/B USB3.0 Type-A
Camera
USB2.0 Hub
Bluetooth

Touch Screen
Finger Printer

H

98

GPP Port

FUNC TIO NPOR T

GPP0
GPP1
GPP2
GPP3
GPP4
GPP5
GPP6
GPP7

SSD (PCIe x4)

Card Reader (PCIe x1)
WLAN (PCIe x1)
SSD (SATA x1)
HDD (SATA x1)

PCB

Z

ZZ

v0 PCB

Re

DA60023G000

Z

ZZ

v1 PCB

Re

DA60023G010

Z

ZZ

v0 DAZ_14

Re

DAZ2GH00100

Z

ZZ

v1 DAZ_14

Re

DAZ2GH00101

_DAZ_R0@

14

_DAZ_R1@

14

Z

ZZ

v0 DAZ_15

Re

DAZ2GD00100

Z

ZZ

v1 DAZ_15

Re

DAZ2GD00101

_DAZ_R0@

15

_DAZ_R1@

15

_R0@

DA

_R1@

DA

Display Port

POR T

B

FUNC TIO N

0

eDP

1

HDMISub/B USB3.0 Type-A

CPU

1

Ryzen5_PC@

UC

IC RYZEN5 ZM350SC4T4MFG 2G QS BGA APU

S

1

Ryzen7_ES@

UC

IC RYZEN7 2M370SC4T4MFB 2.2G ES APU

S

SA0000C7610

curity Classification

curity Classification

curity Classification

Se

Se

Se

s

s

s

sued Date

sued Date

sued Date

I

I

I

H

H

H

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SA0000CCR00

1

Ryzen7_PC@

UC

IC RYZEN7 ZM370SC4T4MFG 2.2G QS APU

S

SA0000C7620

Compal Secret Data

Compal Secret Data

0

0

0

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

2

2

2

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

BOARD RAM * 4 HDMI Logo

ON

Z

Z

H4G_MD@

ZZ

6 HYNIX 4GB MD

X7

680438L51

X7

Z

M4G_MD@

ZZ

6 MICRON 4GB MD

X7

680438L52

X7

S4G_MD@

ZZ

6 SAMSUNG 4GB MD

X7

680438L53

X7

CARD READER (SUB BOARD)

*Main Source - Realte
*Substitute - Genesys

1

Ryzen5_PR@

UC

IC RYZEN5 YM3500C4T4MFG 2G BGA1140 APU

S

SA0000CCR20

1

Ryzen7_PR@

UC

IC RYZEN7 YM3700C4T4MFG 2.2G BGA APU

S

SA0000C7640

T

T

T

Size

Size

Size

Date: Sheet

Date: Sheet

D

Date: Sheet

k

1

Ryzen3_PC@

UC

IC RYZEN3 ZM320SC4T2OFG 2.5G QS APU

S

SA0000CCS00

1

Ryzen3_PR@

UC

IC RYZEN3 YM3200C4T2OFG 2.5G BGA 1140 APU

S

SA0000CCS20

TYPE2TYPE1

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

itle

i

i

C

C

C

Co

tle

tle

ocument Number Re v

D

ocument Number Re v

ocument Number Re v

D

D

O

O

O

TES LIST

TES LIST

TES LIST

N

N

N

A

A

A

-H131P

-H131P

-H131P

L

L

L

E

X4E

Z

ZZ

HD

RO

Z

ZZ

X4

EAF938L01

X4

MI Logo

0000003HM

E EMC

3

3

3

X4E@

45@

.

.

.

0

0

0

f

4

f

4

f

4

6Monday, November 05, 2018

6Monday, November 05, 2018

6Monday, November 05, 2018

o

o

o

4

4

4

5

4

3

2

1

Shut
Down

N1_ AC_ IN

VCI

+3V LP

EC_ ON

+5V ALW

+3V ALW

3V/5 VAL W_PG

+1.8 VAL W

+0.8 VAL W

ON/O FF#

EC_R SMR ST#

PBTN _OU T#

PM_S LP_ S5#

PM_S LP_ S3#

SYS ON

+2.5 V_M EM

+1.2 V_D DR

SUS P#

0.8V S_P WR_E N

+5V S

+3V S

+1. 8VS

+0. 8VS

+0. 6VS

VR_ ON

+APU _CO RE

+APU_ COR E_S OC

VGA TE

PCH_ PWR OK

APU_ PWR GD

PLT_ RST #

PCIR ST#

APU_ RST #

CLK_ PCI E

: 15ms~26ms

T2

T3 : 30us~64us

Boot

T5_Min : 1ms

T8 : 15ms~17ms

T9 : 12ms~14.6ms

Power Sequence

N1_ AC_ IN

D D

EC Pin 110 Intput

EC Pin 112 Output

AC Plug

EC Pin 114 Intput

EC Pin 100 Output

EC Pin 122 Output

C C

EC Pin 123 Intput

EC Pin 6 Intput

EC Pin 95 Output

EC Pin 116 Output

EC Pin 99 Output

B B

EC Pin 121 Output

EC Pin 36 Intput

EC Pin 32 Output

Pin 13 Intput

EC

VCI

+3V LP

EC_ ON

+5V ALW

+3V ALW

5VA LW_ PG

3V/

+1.8 VAL W

+0.8 VAL W

ON/O FF#

EC_R SMR ST#

_CL K RTC_ CLK

RTC

PBTN _OU T#

PM_S LP_ S5#

PM_S LP_ S3#

SYS ON

+2.5 V_M EM

+1.2 V_D DR

SUS P#

0.8V S_P WR_E N

+5V S

+3V S

+1. 8VS

+0. 8VS

+0. 6VS

VR_ ON

+APU _CO RE

+APU_ COR E_S OC

VGA TE

PCH_ PWR OK

APU_ PWR GD

_RS T#

PLT

PCIR ST#

APU_ RST #

CLK_ PCI E

T1_

Min : 10ms

A A

urity Classification

urity Classification

urity Classification

Sec

Sec

Sec

ued Date

ued Date

ued Date

Iss

Iss

Iss

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

8/11/05 2019/11/05

8/11/05 2019/11/05

8/11/05 2019/11/05

201

201

201

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Tit

Size

Size

Size

ocument Number Re v

ocument Number Re v

ocument Number Re v

D

D

D

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

onday, November 05, 2018

onday, November 05, 2018

onday, November 05, 2018

er Sequence

er Sequence

er Sequence

Pow

Pow

Pow

H131P

H131P

H131P

LA-

LA-

LA-

1

pal Electronics, Inc.

pal Electronics, Inc.

pal Electronics, Inc.

Com

Com

Com

le

le

le

Tit

Tit

0.4

0.4

0.4

f

4

f

4

f

4

o

4

6M

o

4

6M

o

4

6M

5

4

3

2

1

Main Func = CPU

D D

_A_MA[13 ..0]<12>

DDR

_A_WE #<12>

DDR

_A_CAS#<12>

DDR

_A_RAS#<12>

DDR

_A_BA0<12>

DDR

_A_BA1<12>

DDR

_A_BG0<12>

DDR

_A_BG1<12>

DDR

_A_ACT#<1 2>

DDR

_A_DM[7.. 0]<12>

DDR

C C

_A_DQS0<12>

DDR

_A_DQS0 #<12>

DDR

_A_DQS1<12>

DDR

_A_DQS1 #<12>

DDR

_A_DQS2<12>

DDR

_A_DQS2 #<12>

DDR

_A_DQS3<12>

DDR

_A_DQS3 #<12>

DDR

_A_DQS4<12>

DDR

_A_DQS4 #<12>

DDR

_A_DQS5<12>

DDR

_A_DQS5 #<12>

DDR

_A_DQS6<12>

DDR

_A_DQS6 #<12>

DDR

_A_DQS7<12>

DDR

_A_DQS7 #<12>

DDR

_A_CLK0<12>

DDR

_A_CLK0 #<12>

DDR

_A_CS0#<12>

DDR

B B

_A_CKE0<12>

DDR

_A_ODT0<12>

DDR

_A_ALER T#<12>

DDR

_A_RST#<1 2>

DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR

DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR

_A_MA0
_A_MA1
_A_MA2
_A_MA3
_A_MA4
_A_MA5
_A_MA6
_A_MA7
_A_MA8
_A_MA9
_A_MA10
_A_MA11
_A_MA12
_A_MA13

_A_BG0
_A_BG1

_A_ACT#

_A_DM0
_A_DM1
_A_DM2
_A_DM3
_A_DM4
_A_DM5
_A_DM6
_A_DM7

_A_EVEN T#

UC1A

AF25

MA_

3

AE2

MA_

7

AD2

MA_

1

AE2

MA_

4

AC2

MA_

6

AC2

MA_

1

AD2

MA_

7

AC2

MA_

2

AD2

MA_

1

AC2

MA_

AF22

MA_

4

AA2

MA_

3

AC2

MA_

5

AJ2

MA_

7

AG2

MA_

3

AG2

MA_

6

AG2

MA_

AF21

MA_

AF27

MA_

1

AA2

MA_

7

AA2

MA_

2

AA2

MA_

F21

MA_

G27

MA_

N24

MA_

N23

MA_

4

AL2

MA_

7

AN2

MA_

5

AW2

MA_

1

AT2

MA_

T27

RSV

F22

MA_

G22

MA_

H27

MA_

H26

MA_

N27

MA_

N26

MA_

R21

MA_

P21

MA_

6

AM2

MA_

7

AM2

MA_

4

AN2

MA_

5

AN2

MA_

3

AU2

MA_

3

AT2

MA_

0

AV2

MA_

0

AW2

MA_

V24

RSV

V23

RSV

5

AD2

MA_

4

AD2

MA_

6

AE2

MA_

7

AE2

MA_

1

AG2

MA_

7

AJ2

MA_

Y23

MA_

Y26

MA_

4

AG2

MA_

2

AJ2

MA_

5

AA2

MA_

4

AE2

MA_

Y24

MA_

FP5

@

ADD0

ADD1

ADD2

ADD3

ADD4

ADD5

ADD6

ADD7

ADD8

ADD9

ADD10

ADD11

ADD12

ADD13_BANK2

WE_L_ADD14

CAS_L_ADD15

RAS_L_ADD16

BANK0

BANK1

BG0

BG1

ACT_L

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

D_36

DQS_H0

DQS_L0

DQS_H1

DQS_L1

DQS_H2

DQS_L2

DQS_H3

DQS_L3

DQS_H4

DQS_L4

DQS_H5

DQS_L5

DQS_H6

DQS_L6

DQS_H7

DQS_L7

D_41

D_40

CLK_H0

CLK_L0

CLK_H1

CLK_L1

CS_L0

CS_L1

CKE0

CKE1

ODT0

ODT1

ALERT_L

EVENT_L

RESET_L

_BGA114 0~D

MEMORY A

FP5 REV 0.90

T 1 OF 13

PAR

_A_DQ[63 ..0] <12>

MA_

DATA1

MA_

DATA2

MA_

DATA3

MA_

DATA4

MA_

DATA5

MA_

DATA6

MA_

DATA7

MA_

DATA8

MA_

DATA9

MA_

DATA10

MA_

DATA11

MA_

DATA12

MA_

DATA13

MA_

DATA14

MA_

DATA15

MA_

DATA16

MA_

DATA17

MA_

DATA18

MA_

DATA19

MA_

DATA20

MA_

DATA21

MA_

DATA22

MA_

DATA23

MA_

DATA24

MA_

DATA25

MA_

DATA26

MA_

DATA27

MA_

DATA28

MA_

DATA29

MA_

DATA30

MA_

DATA31

MA_

DATA32

MA_

DATA33

MA_

DATA34

MA_

DATA35

MA_

DATA36

MA_

DATA37

MA_

DATA38

MA_

DATA39

MA_

DATA40

MA_

DATA41

MA_

DATA42

MA_

DATA43

MA_

DATA44

MA_

DATA45

MA_

DATA46

MA_

DATA47

MA_

DATA48

MA_

DATA49

MA_

DATA50

MA_

DATA51

MA_

DATA52

MA_

DATA53

MA_

DATA54

MA_

DATA55

MA_

DATA56

MA_

DATA57

MA_

DATA58

MA_

DATA59

MA_

DATA60

MA_

DATA61

MA_

DATA62

MA_

DATA63

MA_

D_34

RSV

D_35

RSV

D_51

RSV

D_52

RSV

D_27

RSV

D_28

RSV

D_43

RSV

D_42

RSV

PAROUT

MA_

H21
F23
H23
G20
F20
J22
J23

G25
F26
L24
L26
L23
F25
K25
K27

M25
M27
P27
R24
L27
M24
P24
P25

M22
N21
T22
V21
L21
M20
R23
T21

AL2
AL2
AP2
AR2
AK2
AK2
AM2
AP2

AM2
AM2
AR2
AU2
AL2
AL2
AP2
AP2

AW2
AV2
AV2
AW2
AU2
AV2
AW2
AT2

AW2
AU2
AP2
AN2
AR2
AN2
AT2
AR2

T24
T25
W25
W27
R26
R27
V27
V26

AF24

_A_DQ1

DDR

_A_DQ2

DDR

_A_DQ3

DDR

_A_DQ4

DDR

_A_DQ5

DDR

_A_DQ6

DDR

_A_DQ7

DDR

_A_DQ8

DDR

_A_DQ9

DDR

_A_DQ10

DDR

_A_DQ11

DDR

_A_DQ12

DDR

_A_DQ13

DDR

_A_DQ14

DDR

_A_DQ15

DDR

_A_DQ16

DDR

_A_DQ17

DDR

_A_DQ18

DDR

_A_DQ19

DDR

_A_DQ20

DDR

_A_DQ21

DDR

_A_DQ22

DDR

_A_DQ23

DDR

_A_DQ24

DDR

_A_DQ25

DDR

_A_DQ26

DDR

_A_DQ27

DDR

_A_DQ28

DDR

_A_DQ29

DDR

_A_DQ30

DDR

_A_DQ31

DDR

_A_DQ32

DDR

7

_A_DQ33

DDR

5

_A_DQ34

DDR

6

_A_DQ35

DDR

7

_A_DQ36

DDR

6

_A_DQ37

DDR

4

_A_DQ38

DDR

4

_A_DQ39

DDR

7

_A_DQ40

DDR

3

_A_DQ41

DDR

1

_A_DQ42

DDR

5

_A_DQ43

DDR

7

_A_DQ44

DDR

2

_A_DQ45

DDR

1

_A_DQ46

DDR

4

_A_DQ47

DDR

3

_A_DQ48

DDR

6

_A_DQ49

DDR

5

_A_DQ50

DDR

2

_A_DQ51

DDR

2

_A_DQ52

DDR

6

_A_DQ53

DDR

7

_A_DQ54

DDR

3

_A_DQ55

DDR

2

_A_DQ56

DDR

1

_A_DQ57

DDR

1

_A_DQ58

DDR

1

_A_DQ59

DDR

0

_A_DQ60

DDR

2

_A_DQ61

DDR

2

_A_DQ62

DDR

0

_A_DQ63

DDR

0

_A_PAR

DDR

_A_DQ0

DDR

J21

DATA0

DDR

_A_PAR <12>

DDR

_B_MA[13 ..0]<13>

DDR

_B_WE #<13>

DDR

_B_CAS#<13>

DDR

_B_RAS#<13>

DDR

_B_BA0<13>

DDR

_B_BA1<13>

DDR

_B_BG0<13>

DDR

_B_BG1<13>

DDR

_B_ACT#<1 3>

DDR

_B_DM[7.. 0]<13>

DDR

_B_DQS0<13>

DDR

_B_DQS0 #<13>

DDR

_B_DQS1<13>

DDR

_B_DQS1 #<13>

DDR

_B_DQS2<13>

DDR

_B_DQS2 #<13>

DDR

_B_DQS3<13>

DDR

_B_DQS3 #<13>

DDR

_B_DQS4<13>

DDR

_B_DQS4 #<13>

DDR

_B_DQS5<13>

DDR

_B_DQS5 #<13>

DDR

_B_DQS6<13>

DDR

_B_DQS6 #<13>

DDR

_B_DQS7<13>

DDR

_B_DQS7 #<13>

DDR

_B_CLK0<13>

DDR

_B_CLK0 #<13>

DDR

_B_CLK1<13>

DDR

_B_CLK1 #<13>

DDR

_B_CS0#<13>

DDR

_B_CS1#<13>

DDR

_B_CKE0<13>

DDR

_B_CKE1<13>

DDR

_B_ODT0<13>

DDR

_B_ODT1<13>

DDR

_B_ALER T#<13>

DDR

_B_EVEN T#<13>

DDR

_B_RST#<1 3>

DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR

DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR

_B_MA0
_B_MA1
_B_MA2
_B_MA3
_B_MA4
_B_MA5
_B_MA6
_B_MA7
_B_MA8
_B_MA9
_B_MA10
_B_MA11
_B_MA12
_B_MA13

_B_BG0
_B_BG1

_B_ACT#

_B_DM0
_B_DM1
_B_DM2
_B_DM3
_B_DM4
_B_DM5
_B_DM6
_B_DM7

_B_EVEN T#

UC1I

0

AG3

MB_

2

AC3

MB_

0

AC3

MB_

9

AB2

MB_

1

AB3

MB_

0

AA3

MB_

9

AA2

MB_

Y30

MB_

1

AA3

MB_

W29

MB_

9

AH2

MB_

Y32

MB_

W31

MB_

0

AL3

MB_

0

AK3

MB_

2

AK3

MB_

0

AJ3

MB_

1

AH3

MB_

2

AG3

MB_

V31

MB_

V29

MB_

V30

MB_

C21

MB_

C25

MB_

E32

MB_

K30

MB_

0

AP3

MB_

1

AW3

MB_

6

BB2

MB_

2

BD2

MB_

N32

RSV

D22

MB_

B22

MB_

D25

MB_

B25

MB_

F29

MB_

F30

MB_

K31

MB_

K29

MB_

9

AR2

MB_

1

AR3

MB_

0

AW3

MB_

9

AW2

MB_

5

BC2

MB_

5

BA2

MB_

2

BC2

MB_

2

BA2

MB_

N31

RSV

N29

RSV

1

AC3

MB_

0

AD3

MB_

9

AD2

MB_

1

AD3

MB_

0

AE3

MB_

2

AE3

MB_

AF29

MB_

AF31

MB_

1

AJ3

MB0

1

AM3

MB0

9

AJ2

MB1

9

AM2

MB1

U29

MB0

T30

MB0

V32

MB1

U31

MB1

1

AL3

MB0

2

AM3

MB0

9

AL2

MB1

0

AM3

MB1

W30

MB_

9

AG2

MB_

T31

MB_

FP5

@

ADD0

ADD1

ADD2

ADD3

ADD4

ADD5

ADD6

ADD7

ADD8

ADD9

ADD10

ADD11

ADD12

ADD13_BANK2

WE_L_ADD14

CAS_L_ADD15

RAS_L_ADD16

BANK0

BANK1

BG0

BG1

ACT_L

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

D_21

DQS_H0

DQS_L0

DQS_H1

DQS_L1

DQS_H2

DQS_L2

DQS_H3

DQS_L3

DQS_H4

DQS_L4

DQS_H5

DQS_L5

DQS_H6

DQS_L6

DQS_H7

DQS_L7

D_20

D_18

CLK_H0

CLK_L0

CLK_H1

CLK_L1

CLK_H2

CLK_L2

CLK_H3

CLK_L3

_CS_L0

_CS_L1

_CS_L0

_CS_L1

_CKE0

_CKE1

_CKE0

_CKE1

_ODT0

_ODT1

_ODT0

_ODT1

ALERT_L

EVENT_L

RESET_L

_BGA114 0~D

MEMORY B

FP5 REV 0.90

T 9 OF 13

PAR

_B_DQ[63 ..0] <13>

MB_

DATA1

MB_

DATA2

MB_

DATA3

MB_

DATA4

MB_

DATA5

MB_

DATA6

MB_

DATA7

MB_

DATA8

MB_

DATA9

MB_

DATA10

MB_

DATA11

MB_

DATA12

MB_

DATA13

MB_

DATA14

MB_

DATA15

MB_

DATA16

MB_

DATA17

MB_

DATA18

MB_

DATA19

MB_

DATA20

MB_

DATA21

MB_

DATA22

MB_

DATA23

MB_

DATA24

MB_

DATA25

MB_

DATA26

MB_

DATA27

MB_

DATA28

MB_

DATA29

MB_

DATA30

MB_

DATA31

MB_

DATA32

MB_

DATA33

MB_

DATA34

MB_

DATA35

MB_

DATA36

MB_

DATA37

MB_

DATA38

MB_

DATA39

MB_

DATA40

MB_

DATA41

MB_

DATA42

MB_

DATA43

MB_

DATA44

MB_

DATA45

MB_

DATA46

MB_

DATA47

MB_

DATA48

MB_

DATA49

MB_

DATA50

MB_

DATA51

MB_

DATA52

MB_

DATA53

MB_

DATA54

MB_

DATA55

MB_

DATA56

MB_

DATA57

MB_

DATA58

MB_

DATA59

MB_

DATA60

MB_

DATA61

MB_

DATA62

MB_

DATA63

MB_

D_17

RSV

D_19

RSV

D_26

RSV

D_29

RSV

D_16

RSV

D_15

RSV

D_25

RSV

D_24

RSV

PAROUT

MB_

_B_DQ1

DDR

D21

_B_DQ2

DDR

B23

_B_DQ3

DDR

D23

_B_DQ4

DDR

A20

_B_DQ5

DDR

C20

_B_DQ6

DDR

A22

_B_DQ7

DDR

C22

_B_DQ8

DDR

D24

_B_DQ9

DDR

A25

_B_DQ10

DDR

D27

_B_DQ11

DDR

C27

_B_DQ12

DDR

C23

_B_DQ13

DDR

B24

_B_DQ14

DDR

C26

_B_DQ15

DDR

B27

_B_DQ16

DDR

C30

_B_DQ17

DDR

E29

_B_DQ18

DDR

H29

_B_DQ19

DDR

H31

_B_DQ20

DDR

A28

_B_DQ21

DDR

D28

_B_DQ22

DDR

F31

_B_DQ23

DDR

G30

_B_DQ24

DDR

J29

_B_DQ25

DDR

J31

_B_DQ26

DDR

L29

_B_DQ27

DDR

L31

_B_DQ28

DDR

H30

_B_DQ29

DDR

H32

_B_DQ30

DDR

L30

_B_DQ31

DDR

L32

_B_DQ32

DDR

9

AP2

_B_DQ33

DDR

2

AP3

_B_DQ34

DDR

9

AT2

_B_DQ35

DDR

2

AU3

_B_DQ36

DDR

0

AN3

_B_DQ37

DDR

1

AP3

_B_DQ38

DDR

0

AR3

_B_DQ39

DDR

1

AT3

_B_DQ40

DDR

9

AU2

_B_DQ41

DDR

0

AV3

_B_DQ42

DDR

0

BB3

_B_DQ43

DDR

8

BA2

_B_DQ44

DDR

0

AU3

_B_DQ45

DDR

1

AU3

_B_DQ46

DDR

2

AY3

_B_DQ47

DDR

9

AY2

_B_DQ48

DDR

7

BA2

_B_DQ49

DDR

7

BC2

_B_DQ50

DDR

4

BA2

_B_DQ51

DDR

4

BC2

_B_DQ52

DDR

8

BD2

_B_DQ53

DDR

7

BB2

_B_DQ54

DDR

5

BB2

_B_DQ55

DDR

5

BD2

_B_DQ56

DDR

3

BC2

_B_DQ57

DDR

2

BB2

_B_DQ58

DDR

1

BC2

_B_DQ59

DDR

0

BD2

_B_DQ60

DDR

3

BB2

_B_DQ61

DDR

3

BA2

_B_DQ62

DDR

1

BB2

_B_DQ63

DDR

1

BA2

M31
N30
P31
R32
M30
M29
P30
P29

_B_PAR

DDR

1

AG3

_B_DQ0

DDR

B21

DATA0

DDR

_B_PAR <13>

DDR

NT# pull high

EVE

2V

+1.

A A

1 2

RC1 1

1 2

RC2 1

K_0402_ 5%

K_0402_ 5%OBR@

DDR

DDR

_B_EVEN T#

_A_EVEN T#

_B_RST#

DDR

7

CC9

P_0402_ 50V8J

100

1 2

@ESD@

ESD

rity Classification

rity Classification

rity Classification

Secu

Secu

Secu

Issued Date

Issued Date

Issued Date

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINSCONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINSCONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINSCONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8/11/05 2019/11/05

8/11/05 2019/11/05

8/11/05 2019/11/05

201

201

201

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Tit

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

tom

tom

tom

Cus

Cus

Cus

Date : Sheet

Date : Sheet

Date : Sheet

DDR4 MEMORY I/F

DDR4 MEMORY I/F

DDR4 MEMORY I/F

FP5

FP5

FP5

H131P

H131P

H131P

LA-

LA-

LA-

1

f

f

f

5 46Monday, November 05 , 2018

5 46Monday, November 05 , 2018

5 46Monday, November 05 , 2018

o

o

o

pal Electronics, Inc.

pal Electronics, Inc.

pal Electronics, Inc.

Com

Com

Com

le

le

le

Tit

Tit

0.4

0.4

0.4

5

Main Func = CPU

4

3

2

1

D D

C C

IE_ARX_DTX_P0

PC

IE_ARX_DTX_N0

PC

IE_ARX_DTX_P1

PC

IE_ARX_DTX_N1

PC

IE_ARX_DTX_P2

PC

IE_ARX_DTX_N2

PC

IE_ARX_DTX_P3

PC

IE_ARX_DTX_N3

PC

IE_ARX_DTX_P4

IE_ARX_DTX_P4<20>

Card Rea der

WLAN

B B

NGFF_S ATA

SATA HDD

Main _SS D

PC

IE_ARX_DTX_N4<20>

PC

IE_ARX_DTX_P5<16>

PC

IE_ARX_DTX_N5<16>

PC

TA_ARX_DTX_P0<17>

SA

TA_ARX_DTX_N0<17>

SA

TA_ARX_DTX_P1<19>

SA

TA_ARX_DTX_N1<19>

SA

IE_ARX_DTX_P[0..3]<17>

PC

IE_ARX_DTX_N[0..3]<17>

PC

PC

IE_ARX_DTX_N4

PC

IE_ARX_DTX_P5

PC

IE_ARX_DTX_N5

PC

TA_ARX_DTX_P0

SA

TA_ARX_DTX_N0

SA

TA_ARX_DTX_P1

SA

TA_ARX_DTX_N1

SA

IE_ARX_DTX_P[0..3]

PC

IE_ARX_DTX_N[0..3]

PC

UC1B @

P8
P9

N6
N7

M8
M9

L6
L7

1

K1

1

J1

H6
H7

G6
F7

G8
F8

0

N1

N9

0

L1

L9

2

L1

1

M1

2

P1

1

P1

V6
V7

T8
T9

R6
R7

R9

0

R1

FP

GFX_RXP0

P_

GFX_RXN0

P_

GFX_RXP1

P_

GFX_RXN1

P_

GFX_RXP2

P_

GFX_RXN2

P_

GFX_RXP3

P_

GFX_RXN3

P_

GFX_RXP4

P_

GFX_RXN4

P_

GFX_RXP5

P_

GFX_RXN5

P_

GFX_RXP6

P_

GFX_RXN6

P_

GFX_RXP7

P_

GFX_RXN7

P_

GPP_RXP0

P_

GPP_RXN0

P_

GPP_RXP1

P_

GPP_RXN1

P_

GPP_RXP2

P_

GPP_RXN2

P_

GPP_RXP3

P_

GPP_RXN3

P_

GPP_RXP4

P_

GPP_RXN4

P_

GPP_RXP5

P_

GPP_RXN5

P_

GPP_RXP6/SATA_RXP0

P_

GPP_RXN6/SATA_RXN0

P_

GPP_RXP7/SATA_RXP1

P_

GPP_RXN7/SATA_RXN1

P_

5_BGA1140~D

5 REV 0.90

FP

RT 2 OF 13

PA

IE

PC

N1

GFX_TXP0

P_

N3

GFX_TXN0

P_

M2

GFX_TXP1

P_

M4

GFX_TXN1

P_

L2

GFX_TXP2

P_

L4

GFX_TXN2

P_

L1

GFX_TXP3

P_

L3

GFX_TXN3

P_

K2

GFX_TXP4

P_

K4

GFX_TXN4

P_

J2

GFX_TXP5

P_

J4

GFX_TXN5

P_

H1

GFX_TXP6

P_

H3

GFX_TXN6

P_

H2

GFX_TXP7

P_

H4

GFX_TXN7

P_

GPP_TXP0

P_

GPP_TXN0

P_

GPP_TXP1

P_

GPP_TXN1

P_

GPP_TXP2

P_

GPP_TXN2

P_

GPP_TXP3

P_

GPP_TXN3

P_

GPP_TXP4

P_

GPP_TXN4

P_

GPP_TXP5

P_

GPP_TXN5

P_

GPP_TXP6/SATA_TXP0

P_

GPP_TXN6/SATA_TXN0

P_

GPP_TXP7/SATA_TXP1

P_

GPP_TXN7/SATA_TXN1

P_

N2
P3

P4
P2

R3
R1

T4
T2

W2
W4

W3
V2

V1
V3

U2
U4

IE_ATX_DRX_P0

PC

IE_ATX_DRX_N0

PC

IE_ATX_DRX_P1

PC

IE_ATX_DRX_N1

PC

IE_ATX_DRX_P2

PC

IE_ATX_DRX_N2

PC

IE_ATX_DRX_P3

PC

IE_ATX_DRX_N3

PC

IE_ATX_DRX_P4

PC

IE_ATX_DRX_N4

PC

IE_ATX_DRX_P5

PC

IE_ATX_DRX_N5

PC

TA_ATX_DRX_P0

SA

TA_ATX_DRX_N0

SA

TA_ATX_DRX_P1

SA

TA_ATX_DRX_N1

SA

1 0.22U_0402_6.3V6K

CC

1 2
1 2

2 0.22U_0402_6.3V6K

CC

1 2

3 0.22U_0402_6.3V6K

CC

1 2

4 0.22U_0402_6.3V6K

CC

1 2

5 0.22U_0402_6.3V6K

CC

6 0.22U_0402_6.3V6K

CC

1 2

1 2

7 0.22U_0402_6.3V6K

CC

8 0.22U_0402_6.3V6K

CC

1 2

1 2

9 0.1U_0201_10V6K

CC

10 0.1U_0201_10 V6K

CC

1 2

11 0.1U_0201_10 V6K

CC

1 2
1 2

12 0.1U_0201_10 V6K

CC

IE_ATX_C_DRX_P[0..3]

PC

IE_ATX_C_DRX_N[0..3]

PC

IE_ATX_C_DRX_P0

PC

IE_ATX_C_DRX_N0

PC

IE_ATX_C_DRX_P1

PC

IE_ATX_C_DRX_N1

PC

IE_ATX_C_DRX_P2

PC

IE_ATX_C_DRX_N2

PC

IE_ATX_C_DRX_P3

PC

IE_ATX_C_DRX_N3

PC

IE_ATX_C_DRX_P4 <20>

PC

IE_ATX_C_DRX_N4 <20>

PC

IE_ATX_C_DRX_P5 <16>

PC

IE_ATX_C_DRX_N5 <16>

PC

TA_ATX_DRX_P0 <17>

SA

TA_ATX_DRX_N0 <17>

SA

TA_ATX_DRX_P1 <19>

SA

TA_ATX_DRX_N1 <19>

SA

IE_ATX_C_DRX_P[0..3] <17>

PC

IE_ATX_C_DRX_N[0..3] <17>

PC

Main _SS D

rdR ead er

Ca

WLAN

NGFF_S ATA

SATA HDD

A A

curity Classification

curity Classification

curity Classification

Se

Se

Se

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

20

20

Issued Date

Issued Date

Issued Date

IS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

TH

TH

TH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

20

Compal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

3

Deciphered Date

Deciphered Date

Deciphered Date

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

tle

tle

tle

Ti

Ti

Ti

ze

ze

ze

Si

Do

Si

Do

Si

Do

stom

stom

stom

Cu

Cu

Cu

Dat e: Sheet

Dat e: Sheet

2

Dat e: Sheet

Co

5 PCIE/UMI

5 PCIE/UMI

5 PCIE/UMI

FP

FP

cument Number Re v

cument Number Re v

cument Number Re v

FP

LA

LA

LA

-H131P

-H131P

-H131P

6 46Monday, November 05, 2018

6 46Monday, November 05, 2018

6 46Monday, November 05, 2018

o f

o f

1

o f

4

4

4

0.

0.

0.

A

B

C

D

E

Main Func = CPU

INV

INV

ENBKL_R

TPWM_R

TPWM_R

+1.8VS

+1.

2

3

1

2

8VS

2

3

APU

QC1

Gate

1

Drain

rce

Sou

LBSS139 WT1G_SC70 -3

SB00001 GC00

8VS

+1.

5

P

NC

4

Y

A

G

UC6

3

4AUP1G0 7GW_SC70 -5

7

SA00005 U600

QC4

e

Gat

1

INV

in

Dra

rce

Sou

BSS139W T1G_SC70-3

L

SB00001 GC00

@

8VALW

+1.

1

3

5

7

_TRST#_R

9

11

13

15

17

19

ENBKL <14, 28>

TPWM <14 >

INV

TPWM

T1

JHD

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

SAMTE_ASP -136446-07-B

DC021004 270

ME@

APU

APU

APU

APU

APU

APU

APU

_TCK

_TMS

_TDI

_TDO

_PWRGD

_RST#

_DBREQ#

TPWM

INV

KL

ENB

KL_R

ENB

DD

ENV

TPWM_R

INV

_HPD

EDP

_TEST14

APU

_TEST15

APU

_TEST16

APU

_TEST17

APU

_TEST31

APU

STEREOSYNC

DP_

_ZVDDP

SMU

ETYPE

COR

APU
APU
APU
APU
APU

_TRST#
_TCK
_TMS
_TDI
_DBREQ#

_TDI

APU

_DBREQ#

APU

_TRST#

APU

RC4 4
RC5 2

RC6 1
RC8 1
RC9 1
RC1

RC1
RC1
RC1
RC1

RC1
RC1

RC1
RC1

RHD
RHD
RHD
RHD
RHD

1 2

.7K_040 2_5%

1 2

.2K_040 2_5%

1 2

00K_040 2_5%

1 2

00K_040 2_5%

1 2

00K_040 2_5%

1 2

0 100K_ 0402_5%

1 2

1 10K_0402_5%@

1 2

2 10K_0402_5%@

1 2

3 10K_0402_5%@

1 2

4 10K_0402_5%@

1 2

5 1K_04 02_5%@

1 2

6 1K_04 02_5%@

1 2

7 1K_04 02_5%

1 2

8 1K_04 02_5%@

1 2

2 196_0402_1%

RC2

1 2

3 1K_0402_5%@

RC2

1 2

T1 1K_0402 _5%HDT@

1 2

T2 1K_0402 _5%HDT@

1 2

T3 1K_0402 _5%HDT@

1 2

T4 1K_0402 _5%HDT@

1 2

T5 1K_0402 _5%HDT@

@

1 2

T1 0.01U_ 0402_16V 7K

CHD

HDT@

1 2

T2 0.01U_ 0402_16V 7K

CHD

HDT@

1 2

T3 0.01U_ 0402_16V 7K

CHD

+3VS

+1.

+1.

+3V

8VS

8VS

+1.

8VS

8VS

+0.

ALW

8VALW

+1.

DP0: eDP
DP1: HDMI
DP2: N/A
DP3: N/A

UC1C @

DISPLAY/SVI2/JTAG/TES T

A8

B8

B6

E6

E1

F3
E4

F4
F2

6

_TXP0

DP0

_TXN0

DP0

_TXP1

DP0

_TXN1

DP0

_TXP2

DP0

_TXN2

DP0

_TXP3

DP0

_TXN3

DP0

_TXP0

DP1

_TXN0

DP1

_TXP1

DP1

_TXN1

DP1

_TXP2

DP1

_TXN2

DP1

_TXP3

DP1

_TXN3

DP1

TDI

TDO

TCK

TMS

T_L

TRS

EQ_L

DBR

ET_L

RES

OK

PWR

SIC

SID

RT_L

ALE

RMTRIP_L

THE

CHOT_L

PRO

0

SVC

0

SVD

0

SVT

_BGA114 0~D

FP5

FP5 REV 0.90

T 3 OF 13

PAR

RC1

1

NC

2

A

11 0_0402_ 5%@

+3V

BLON

DP_

DIGON

DP_

VARY_BL

DP_

_AUXP

DP0

_AUXN

DP0

_HPD

DP0

_AUXP

DP1

_AUXN

DP1

_HPD

DP1

_AUXP

DP2

_AUXN

DP2

_HPD

DP2

_AUXP

DP3

_AUXN

DP3

_HPD

DP3

STEREOSYNC

DP_

D_4

RSV

D_3

RSV

D_2

RSV

T4

TES

T5

TES

T6

TES

T14

TES

T15

TES

T16

TES

T17

TES

T31

TES

T41

TES

T470

TES

T471

TES

_ZVDD

SMU

ETYPE

COR

P_SENSE

VDD

CR_SOC_SENSE

VDD

CR_SENSE

VDD

_SENSE_A

VSS

_SENSE_B

VSS

S

5

P

4

Y

G

2

UC2

3

74AUP1G 07GW_SC7 0-5

SA00007 WE00

@

12

erve for sequence tuning

_TDI
_TDO
_TCK
_TMS
_TRST#
_DBREQ#

_RST#
_PWRGD

_ALERT#
RMTRIP#

C8

D8

C7

C6
D6

D5

C1

AU2
AU4
AU1
AU3
AV3

AW3

AW4
AW2

H14

J14
J15

AP1

L19

F16
H16

J16

_RST#_EC<28 >

APU

Res

_TXP0<14>

EDP

_TXN0<14>

1 1

eDP

HDM

2 2

3 3

8VS

+1.

4 300_0 402_5%

RC2

5 300_0 402_5%

RC2

S

+3V

RC3
RC2
RC2

RC3

1 2
1 2

1 2

1 1K_0402_5%

1 2

8 1K_0402_5%

1 2

9 1K_0402_5%

1 2

0 220_0402_5%@

EDP

_TXP1<14>

EDP

_TXN1<14>

EDP

_DP1_P0<15>

APU

_DP1_N0<15>

APU

_DP1_P1<15>

APU

_DP1_N1<15>

APU

I

_DP1_P2<15>

APU

_DP1_N2<15>

APU

_DP1_P3<15>

APU

_DP1_N3<15>

APU

APU
APU
APU
APU
APU
APU

APU

_PWRGD<3 8>

APU

SMB_CK2<26,28>

EC_

SMB_DA2<26,28>

EC_

THERMTRIP#<28 >

EC_

ROCHOT#<28, 38>

H_P

_SVC<38>

APU

_SVD<38>

APU

_SVT<3 8>

APU

_RST#

APU

_PWRGD

APU

_ALERT#

APU

ROCHOT#

H_P

RMTRIP#

THE

_PWRGD

APU

RC2

1 2

1 0_0402_5%@

APU

APU
THE

KL_R

ENB

G15
F15

DD

ENV

TPWM_R

INV

L14

D9
B9
C10

G11
F11
G13

J12
H12
K13

J10
H10
K8

STEREOSYNC

DP_

K15

F14
F12

F10

_TEST4

APU

4

AP1

_TEST5

APU

4

AN1

_TEST6

APU

F13

_TEST14

APU

G18

_TEST15

APU

H19

_TEST16

APU

F18

_TEST17

APU

F19

_TEST31

APU

W24

_TEST41

APU

1

AR1

_TEST470

APU

1

AJ2

_TEST471

APU

1

AK2

_ZVDDP

SMU

V4

1

AW1

ETYPE

COR

_VDDP_RUN_ FB_H

APU

1

AN1
J19
K18

_VDD_RUN_F B_L

APU

J18

_VDDP_RUN_ FB_L

APU

1

AM1

_RST#

APU

ENV

EDP
EDP
EDP

APU
APU
APU

T1
T2

T3

T4
T5
T6
T7

T8

T9

T10
T11

+LCDVDD_CONN PWR switch enable pin VIH=1.2V

DD <14 >

_AUXP <14>
_AUXN <1 4>
_HPD <14>

_DP1_CTRL_ CLK <15>
_DP1_CTRL_ DAT <15>
_DP1_HPD <1 5>

T12
T13
T14

T15

T16

eDP

HDMI

_VDDP_RUN_ FB_H <37>

APU

_VDDSOC_ SEN <38>

APU

_VDDCR_SE N <38>

APU

_VDD_RUN_F B_L <38>

APU

_VDDP_RUN_ FB_L <37>

APU

HDT+ (debug + HDT@)

_TRST#

APU

RHD

RHD

RHD

RHD

1 2

T6 3 3_0402_5%HDT@

1 2

T7 1 0K_0402_5 %HDT@

1 2

T8 1 0K_0402_5 %HDT@

1 2

T9 1 0K_0402_5 %HDT@

ESD

4 4

1 2

7 100P_04 02_50V8JESD@

CC1

1 2

8 100P_04 02_50V8JESD@

CC1

1 2

9 100P_04 02_50V8JESD@

CC1

H_P

APU

APU

ROCHOT#

_PWRGD

_RST#

rity Classification

rity Classification

rity Classification

Secu

Secu

Secu

Issued Date

Issued Date

Issued Date

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINSCONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINSCONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINSCONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8/11/05 2019/11/05

8/11/05 2019/11/05

8/11/05 2019/11/05

201

201

201

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Tit

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

tom

tom

tom

Cus

Cus

Cus

Date : Sheet

Date : Sheet

Date : Sheet

DISP/MISC/HDT

DISP/MISC/HDT

DISP/MISC/HDT

FP5

FP5

FP5

H131P

H131P

H131P

LA-

LA-

LA-

E

f

f

f

7 46Monday, November 05 , 2018

7 46Monday, November 05 , 2018

7 46Monday, November 05 , 2018

o

o

o

pal Electronics, Inc.

pal Electronics, Inc.

pal Electronics, Inc.

Com

Com

Com

le

le

le

Tit

Tit

0.4

0.4

0.4

A

B

C

D

E

Main Func = CPU

Capacit

y

Description

WITHOUT ON-BOARD RA
SAMSUNG 2666MHz
MICRON 2666MHz
HYNIX 2666MHz

1 1

+1.

8VALW

1

2

CC2

0.1U_0201_10V6K

6 22K_0402_5%

RC3

1 2

2

ESD@

3 100P_0402_50V8J

CC2

1 2

@ESD@

1 2

4 100P_0402_50V8J

CC2

EC_

SYS

RSMRST# <28>

EC_

RSMRST#

_RESET#

4GB

N/A
N/A
N/A
N/A

Capacit

y

Description

WITHOUT ON-BOARD RA
N/A
N/A
N/A

4GB

N/A
SAMSUNG 2666MHz
MICRON 2666MHz (MT40A512M16LY-075:E
HYNIX 2666MHz

ESD

ALW

+3V

1 2

5 10K_0402_5%

RC4

7 10K_0402_5%

RC4

2 2

3 3

4 4

8 10K_0402_5%@

RC4

1 2.2K_0402_5%

RC6

2 2.2K_0402_5%

RC6

0 1K_0402_5%

RC5

3 10K_0402_5%@

RC5

4 10K_0402_5%@

RC5

S

+3V

6 2.2K_0402_5%

RC5

7 2.2K_0402_5%

RC5

_BITCLK_AUDIO<21>

HDA

_SDOUT_AUDIO<21>

HDA

_SYNC_AUDIO<21>

HDA

I2C

_3_SCL_R<27>

I2C

_3_SDA_R<27>

1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

E_DET

PCI

N_OUT#

PBT

_PCIE_WAKE#

APU

I2C
I2C

_RST#

HDA

_SDIN0

HDA

_BIT_CLK

HDA

I2C
I2C

7 33_0402_5%EMI@

RC6

1 2
1 2

8 33_0402_5%

RC6

9 33_0402_5%

RC6

1 2

0 1K_0402_5%

RC7

1 2
1 2

1 1K_0402_5%

RC7

S

+3V

2

A

QC3
2N7002KDW 2N SC88-6

SB00000EO00

_3_SCL
_3_SDA

_2_SCL
_2_SDA

4

61

QC3

5

2N7002KDW 2N SC88-6

SB00000EO00

_PCIE_RST#_R

APU

1

CC2

_BIT_CLK

HDA

_SDOUT

HDA

_SYNC

HDA

0

CC2

1

2

150

150

@

P_0402_50V8J

P_0402_50V8J

2

1

EMI

B

_3_SCL

I2C

3

_3_SDA

I2C

_PWRGD_EC<28>

SYS

M

(K4A8G165WC-BCTD

MT40A512M16LY-075:E

(

(H5AN8G6NCJR-VKC

M

(K4A8G165WC-BCTD

(H5AN8G6NCJR-VKC

1 2

4 33_0402_5%

RC3

5 33_0402_5%@

RC3

1 2

N_OUT#<28>

PBT

SLP_S3#<28>

PM_

SLP_S5#<28,33,36>

PM_

_SDIN0<21>

HDA

check list discuss unconnected if no used

SYS

)

)

_PWRGD_EC

)

)

)

)

_PCIE0_RST#

APU

_PCIE1_RST#

APU

RSMRST#

EC_

N_OUT#

PBT

_FCH_PWRGD_R

APU

_RESET#

SYS

_PCIE_WAKE#

APU

SLP_S3#

PM_

SLP_S5#

PM_

_BIT_CLK

HDA

_SDIN0

HDA

_RST#

HDA

_SYNC

HDA

_SDOUT

HDA

1

2

RC6

X7680438L53
X7680438L52
X7680438L51

AGPIO11
MEM_ID2

0
0
0
0
1
1
1
1

ALW

+3V

5

P

NC

A

G

3

4

X76

N/A

N/A
N/A
N/A
N/A

AGPIO
MEM_ID1

BD5
BB6

6

AT1

AR15

AV6

0

AP1

1

AV1

3

AV1

4

AT1

AR8

0

AT1

AN6

AW8

AR2
AP7
AP1
AP4
AP3
AR4
AR3

AT2
AT4
AR6
AP6

UC7

4

Y

4AUP1G07GW_SC70-5

7

SA00007WE00

@

12

402_5%@

0_0

PART NUMBER(R

N/A

SA0000B6F00
SA0000ARD20
SA0000BMN00

N/A

N/A

N/A

N/A

9

AGPIO

MEM_ID0

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

UC1D @

E_RST0_L/EGPIO26

PCI

E_RST1_L/EGPIO27

PCI

RST_L

RSM

_BTN_L/AGPIO0

PWR

_GOOD

PWR

_RESET_L/AGPIO1

SYS

E_L/AGPIO2

WAK

_S3_L

SLP

_S5_L

SLP

3_GPIO/AGPIO10

S0A

PRES/AGPIO23

AC_

_L/AGPIO12

LLB

IO42

EGP

BITCLK/TDM_BCLK_MIC

AZ_

SDIN0/CODEC_GPI

AZ_

SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

AZ_

SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

AZ_

RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

AZ_

SYNC/TDM_FRM_MIC

AZ_

SDOUT/TDM_FRM_PLAYBACK

AZ_

MCLK/TDM_BCLK_BT

SW_

DATA0/TDM_DOUT_BT

SW_

IO7/FCH_ACP_I2S_SDIN_BT

AGP

IO8/FCH_ACP_I2S_LRCLK_BT

AGP

FP5_BGA1140~D

ALW

+3V

12

5

RC5

8.2K_0402_5%

_FCH_PWRGD_R

APU

1

PART NUMBER

)

N/A

SA0000B6F10
SA0000ARD30
SA0000BMN10

N/A

N/A

N/A

N/A

6

RC41NO_
10K_0402_5%

RC42NO_
10K_0402_5%

RC43NO_
10K_0402_5%

No On Board RAM Straps (NO_OBR@)

ACPI/AUDIO/I2 C/GPIO/ MISC

3.3VALW input

3.3

3.3VS input

3.3VS input

FP5 REV 0.90

T 4 OF 13

PAR

_PCIE_RST#_R

APU

R

3

(

)

OBR@

OBR@

OBR@

IO41/SFI_S5_EGPIO41

EGP

IO39/SFI_S5_AGPIO39

AGP

0_SCL/SFI0_I2C_SCL/EGPIO151

I2C

0_SDA/SFI0_I2C_SDA/EGPIO152

I2C

1_SCL/SFI1_I2C_SCL/EGPIO149

I2C

1_SDA/SFI1_I2C_SDA/EGPIO150

I2C

2_SCL/EGPIO113/SCL0

I2C

2_SDA/EGPIO114/SDA0

I2C

3_SCL/AGPIO19/SCL1

I2C

3_SDA/AGPIO20/SDA1

I2C

PSA

PSA

IO4/SATAE_IFDET

AGP

IO5/DEVSLP0

AGP

IO6/DEVSLP1

AGP

A_ACT_L/AGPIO130

SAT

3.3VALW input

3.3VALW input

3.3VALW input

3.3VS input

RUDER_ALERT

INT

VS Output

R/AGPIO91

SPK

NK/AGPIO11

BLI

INT1_L/AGPIO89

GEN

INT2_L/AGPIO90

GEN

IN0/AGPIO84

FAN

OUT0/AGPIO85

FAN

12

2

RC7
10K_0402_5%

_I2C_SCL

_I2C_SDA

AGP

AGP

AGP

AGP

AGP

_ID0

MEM

_ID1

MEM

_ID2

MEM

2

AW1
AU12

AR13

3

AT1

AN8
AN9

BC20

0

BA2

AM9

0

AM1

L16
M16

5

AT1

IO3

0

AW1

AP9
AU10

5

AV1

AU7

IO9

AU6

IO40

3

AW1

IO69

5

AW1

IO86

AU14
AU16
AV8

6

AW1
BD15

AR18

8

AT1

RC7

+3VALW

7

RC3
10K_0402_5%

X76RAM@

2

RC4
10K_0402_5%

X76RAM@

8

RC3
10K_0402_5%

X76RAM@

1 2

1

RC4
10K_0402_5%

X76RAM@

1 2

ON B

Not Implemented Need Pull down by SW

Not Implemented Need Pull down by SW

_2_SCL_R

I2C

_2_SDA_R

I2C

_3_SCL

I2C

_3_SDA

I2C

2

1

3 0_0402_5%@

1 2

E_DET

PCI
MEM

MEM

MOD

HDA
MEM

_SELECT

MIC

+3V

5

B

A

3

_ID0

_ID1

EL_ID

_SPKR
_ID2

ALW

P

4

Y

G

UC8
M

SA00000OH00

@

1 2

17 0_0402_5%@

RC1

18 0_0402_5%@

RC1

1 2

1

@

CC2

0.1U_0201_10V6K

2

C74VHC1G08DFT2G SC70 5P

9

RC3
10K_0402_5%

X76RAM@

1 2

3

RC4
10K_0402_5%

X76RAM@

1 2

OARD RAM ID

T22
T21

T23
T24

6

E_DET <17>

PCI

_SPKR <21>

HDA

TP_

INT# <27>

_PCIE_RST# <16,17,20>

APU

_2_SCL

I2C

_2_SDA

I2C

Functio

n

MODEL_I

D

AGPIO69

(

EL_ID

(

13

RC1
10K_0402_5%

MULTI_MIC@

16

RC1
10K_0402_5%

SINGLE_MIC@

0
1

+3V

MIC_SELEC

AGPIO84

0
1

+3V

_RESET#

SYS

DEF

)

S

RC1
10K_0402_5%

15@

1 2

RC1
10K_0402_5%

14@

1 2

)

S

1 2

1 2

INITION

12

15

T

+1.

9

RC5
10K_0402_5%

5

RC6
2K_0402_5%

@

8VALW

ALW

+3V

0

RC6
10K_0402_5%

1 2

1 2

12

12

6

RC6
2K_0402_5%

@

S340-14

S340-15

1 2

Functio

1 MIC

2 MIC

APU

_SPI_CLK_R<9>

APS

MOD

n

_SELECT

MIC

1 2

_2_SCL <13>

I2C

_2_SDA <13>

I2C

STR

STRAPS

1 : Use 48MHZ Crystal C lock and Gene rate both internal
and external clo cks (Default)

SPI_CLK

0 : Use 100MHZ PCIE clock as reference clock
and generate internal clocks only

1 : Normal reset mode (Default)

SYS_RST#

0 : short reset mode

rity Classification

rity Classification

rity Classification

Secu

Secu

Secu

d Date

d Date

d Date

Issue

Issue

Issue

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS, INC.

A

B

C

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS, INC.

8/11/05 2019/11/05

8/11/05 2019/11/05

8/11/05 2019/11/05

201

201

201

pal Secret Data

pal Secret Data

pal Secret Data

Com

Com

Com

iphered Date

iphered Date

iphered Date

Dec

Dec

Dec

D

Title

le

le

Tit

Tit

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cust

Cust

Cust

Date: Sheet

Date: Sheet

Date: Sheet

om

om

om

pal Electronics, Inc.

pal Electronics, Inc.

pal Electronics, Inc.

Com

Com

Com

GPIO/AZ/MISC/STRAPS

GPIO/AZ/MISC/STRAPS

GPIO/AZ/MISC/STRAPS

FP4

FP4

FP4

H131P

H131P

H131P

LA-

LA-

LA-

E

0.4

0.4

0.4

8 46Monday, November 05, 2018

8 46Monday, November 05, 2018

8 46Monday, November 05, 2018

of

of

of

Main Func = CPU

A

B

C

D

E

48MHz CRYSTAL

1 1

75 1M_0402_5%

RC

2

2

3

3

1

27

CC

4.7P_0402_50V8C

2

SE07147AB80

.768KHz CRYSTAL

32

2 2

VS

+3

3 3

M_X2_R

48

M_X1_R

48

12

1

1

1

YC
48MHZ_8PF_7V48000010

SJ10000JP00

4

4

1

28

CC

4.7P_0402_50V8C

2

SE07147AB80

86 20M_0402_5%

RC

1 2

1

30

CC

P_0402_50V8J

10

2

12

89 10K_0402_5%

RC

90 10K_0402_5%

RC

12
12

91 10K_0402_5%

RC

1 2

74 33_0402_5%EMI@

RC

76 33_0402_5%EMI@

RC

1 2

Vendor Tuning Value was 3.9pF, Lack Source

12

2

YC

32.768KHZ_9PF_X1A000141000200

SJ10000PW00

1

31

CC

P_0402_50V8J

10

2

KREQ_SSD1#

CL

KREQ_SD#

CL

KREQ_WLAN#

CL

USB3.1 Type-C

USB3.1 Type-A Port 1

USB3.1 Type-A Port 2

mera

Ca

USB2.0 Hub

NGFF_B T

VALW

+3

B_OC0#

1 2

98 100K_0402_5%

RC

99 100K_0402_5%

RC

1 2

4 4

US

B_OC1#

US

M_X2

48

M_X1

48

I

EM

n_S SD

Mai

CardRe ader

WLAN

K_X1

32

K_X2

32

C_CLK_R<16>

RT

CL
CL
CL

AP

CL
CL

CL
CL

CL
CL

87 22 +-5% 0402@

RC

KREQ_SSD1#<17>
KREQ_SD#<20>
KREQ_WLAN#<16>

U_BT_OFF#<16>

K_PCIE_SSD1<17>
K_PCIE_SSD1#<17>

K_PCIE_SD<20>
K_PCIE_SD#<20>

K_PCIE_WLAN<16>
K_PCIE_WLAN#<16>

KREQ_SSD1#

CL

KREQ_SD#

CL

KREQ_WLAN#

CL

U_BT_OFF#

AP

K_PCIE_SSD1

CL

K_PCIE_SSD1#

CL

K_PCIE_SD

CL

K_PCIE_SD#

CL

K_PCIE_WLAN

CL

K_PCIE_WLAN#

CL

48

48

RT

12

32

32

B20_P0<25>

US

B20_N0<25>

US

B20_P1<20>

US

B20_N1<20>

US

B20_P2<20>

US

B20_N2<20>

US

B20_P3<14>

US

B20_N3<14>

US

B20_P4<22>

US

B20_N4<22>

US

B20_P5<16>

US

B20_N5<16>

US

B_OC0#<20>

US

B_OC1#<20>

US

Not Implemented Pull down by SW

B20_P0

US

B20_N0

US

B20_P1

US

B20_N1

US

B20_P2

US

B20_N2

US

B20_P3

US

B20_N3

US

B20_P4

US

B20_N4

US

B20_P5

US

B20_N5

US

B_OC0#

US

B_OC1#

US

7

AE

B_0_DP0

US

6

AE

B_0_DM0

US

10

AG

B_0_DP1

US

9

AG

B_0_DM1

US

12

AF

B_0_DP2

US

11

AF

B_0_DM2

US

10

AE

B_0_DP3

US

9

AE

B_0_DM3

US

12

AJ

B_1_DP0

US

11

AJ

B_1_DM0

US

AD9

B_1_DP1

US

AD8

B_1_DM1

US

6

AM

BC_I2C_SCL

US

7

AM

BC_I2C_SDA

US

10

AK

B_OC0_L/AGPIO16

US

9

AK

B_OC1_L/AGPIO17

US

9

AL

B_OC2_L/AGPIO18

US

8

AL

B_OC3_L/AGPIO24

US

7

AW

PIO14/USB_OC4_L

AG

12

AT

PIO13/USB_OC5_L

AG

FP5_BGA1140~D

UC1J @

FP5 REV 0.90

RT 10 OF 13

PA

USB

BC0_A2/USB_0_TXP0/DP3_TXP2

US

BC0_A3/USB_0_TXN0/DP3_TXN2

US

BC0_B11/USB_0_RXP0/DP3_TXP3

US

BC0_B10/USB_0_RXN0/DP3_TXN3

US

BC0_B2/DP3_TXP1

US

BC0_B3/DP3_TXN1

US

BC0_A11/DP3_TXP0

US

BC0_A10/DP3_TXN0

US

US

US

US

US

US

US

US

US

BC1_A2/USB_0_TXP3/DP2_TXP2

US

BC1_A3/USB_0_TXN3/DP2_TXN2

US

BC1_B11/USB_0_RXP3/DP2_TXP3

US

BC1_B10/USB_0_RXN3/DP2_TXN3

US

BC1_B2/DP2_TXP1

US

BC1_B3/DP2_TXN1

US

BC1_A11/DP2_TXP0

US

BC1_A10/DP2_TXN0

US

US

US

US

US

B_0_TXP1

B_0_TXN1

B_0_RXP1

B_0_RXN1

B_0_TXP2

B_0_TXN2

B_0_RXP2

B_0_RXN2

B_1_TXP0

B_1_TXN0

B_1_RXP0

B_1_RXN0

M_X1

M_X2

C_CLK

K_X1

K_X2

UC1E @

18

AV

K_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

CL

9

AN1

K_REQ1_L/AGPIO115

CL

19

AP

K_REQ2_L/AGPIO116

CL

19

AT

K_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

CL

9

AU1

K_REQ4_L/OSCIN/EGPIO132

CL

18

AW

K_REQ5_L/EGPIO120

CL

19

AW

K_REQ6_L/EGPIO121

CL

1

AK

P_CLK0P

GP

3

AK

P_CLK0N

GP

2

AM

P_CLK1P

GP

4

AM

P_CLK1N

GP

1

AM

P_CLK2P

GP

3

AM

P_CLK2N

GP

2

AL

P_CLK3P

GP

4

AL

P_CLK3N

GP

AN2

P_CLK4P

GP

AN4

P_CLK4N

GP

AN3

P_CLK5P

GP

2

AP

P_CLK5N

GP

2

AJ

P_CLK6P

GP

4

AJ

P_CLK6N

GP

3

AJ

M_OSC

48

3

BB

8M_X1

X4

5

BA

8M_X2

X4

8

AF

VD_76

RS

9

AF

VD_77

RS

14

AW

CCLK

RT

1

AY

2K_X1

X3

4

AY

2K_X2

X3

FP5_BGA1140~D

B3_ATX_DRX_P0

US

AD2

B3_ATX_DRX_N0

US

AD4

B3_ARX_DTX_P0

US

AC2

B3_ARX_DTX_N0

US

AC4

4

AF

2

AF

3

AE

1

AE

B3_ATX_DRX_P1

US

3

AG

B3_ATX_DRX_N1

US

1

AG

B3_ARX_DTX_P1

US

9

AJ

B3_ARX_DTX_N1

US

8

AJ

B3_ATX_DRX_P2

US

4

AG

B3_ATX_DRX_N2

US

2

AG

B3_ARX_DTX_P2

US

7

AG

B3_ARX_DTX_N2

US

6

AG

2

AA

4

AA

Y1
Y3

AC1
AC3

2

AB

4

AB

AH4
AH2

7

AK

6

AK

CLK/LPC/EMMC/SD/SPI/eS PI/UART

FP5 REV 0.90

RT 5 OF 13

PA

B3_ATX_DRX_P0 <24>

US

B3_ATX_DRX_N0 <24>

US

B3_ARX_DTX_P0 <24>

US

B3_ARX_DTX_N0 <24>

US

B3_ATX_DRX_P1 <20>

US

B3_ATX_DRX_N1 <20>

US

B3_ARX_DTX_P1 <20>

US

B3_ARX_DTX_N1 <20>

US

B3_ATX_DRX_P2 <20>

US

B3_ATX_DRX_N2 <20>

US

B3_ARX_DTX_P2 <20>

US

B3_ARX_DTX_N2 <20>

US

PIO70/SD_CLK

EG

C_PD_L/SD_CMD/AGPIO21

LP

D0/SD_DATA0/EGPIO104

LA

D1/SD_DATA1/EGPIO105

LA

D2/SD_DATA2/EGPIO106

LA

D3/SD_DATA3/EGPIO107

LA

CCLK0/EGPIO74

LP

C_CLKRUN_L/AGPIO88

LP

CCLK1/EGPIO75

LP

RIRQ/AGPIO87

SE

RAME_L/EGPIO109

LF

C_RST_L/SD_WP_L/AGPIO32

LP

PIO68/SD_CD

AG

C_PME_L/SD_PWR_CTRL/AGPIO22

LP

I_ROM_REQ/EGPIO67

SP

I_ROM_GNT/AGPIO76

SP

PI_RESET_L/KBRST_L/AGPIO129

ES

PI_ALERT_L/LDRQ0_L/EGPIO108

ES

I_CLK/ESPI_CLK

SP

I_DI/ESPI_DATA

SP

I_WP_L/ESPI_DAT2

SP

I_HOLD_L/ESPI_DAT3

SP

I_CS1_L/EGPIO118

SP

I_CS2_L/ESPI_CS_L/AGPIO30

SP

I_CS3_L/AGPIO31

SP

I_TPM_CS_L/AGPIO29

SP

RT0_RXD/EGPIO136

UA

RT0_TXD/EGPIO138

UA

RT0_RTS_L/UART2_RXD/EGPIO137

UA

RT0_CTS_L/UART2_TXD/EGPIO135

UA

RT0_INTR/AGPIO139

UA

PIO141/UART1_RXD

EG

PIO143/UART1_TXD

EG

PIO142/UART1_RTS_L/UART3_RXD

EG

PIO140/UART1_CTS_L/UART3_TXD

EG

PIO144/UART1_INTR

AG

TYPEC

Type-A

Type-A left port2

3

BD1

14

BB

CPD#

LP

C_AD0_R

LP

12

BB

C_AD1_R

LP

1

BC1

C_AD2_R

LP

15

BB

C_AD3_R

LP

5

BC1

C_CLK0

LP

15

BA

3

BC1

KRUN#

CL

13

BB

Not Implemented Need Pull down by SW

2

BC1

12

BA

C_RST#

LP

1

BD1

11

BA

13

BA

BC8

8

BB

11

BB
BC6

U_SPI_CLK

AP

7

BB

U_SPI_MISO

AP

9

BA

U_SPI_MOSI

AP

10

BB

I_DO

SP

U_SPI_WP#

AP

10

BA

U_SPI_HOLD#

AP

0

BC1

U_SPI_CS1#

AP

BC9

8

BA

Not Implemented Need Pull down by SW

6

BA
BD8

RT_0_ARXD_DTXD

UA

16

BA

RT_0_ATXD_DRXD

UA

18

BB

7

BC1

18

BA

8

BD1

8

BC1

17

BA

D_RST#

SS

6

BC1

19

BB

U_WL_OFF#

AP

16

BB

Right

left port1

Not Implemented Need Pull down by SW

7

T1

77 10_0402_5%

RC

12
12

78 10_0402_5%

RC

79 10_0402_5%

RC

12

80 10_0402_5%

RC

12
12

81 22_0402_5%

RC

82 33_0402_5%

RC

12

84 10_0402_1%EMI@

RC

12

8

T1

9

T1

0

T2

.8VALW

+1

92 10K_0402_5%@

RC

93 10K_0402_5%

RC

94 10K_0402_5%

RC

96 10K_0402_5%

RC

95 10K_0402_5%

RC

97 10_0402_5%@EMI@

RC

1

33

CC
10P_0402_50V8J

@EMI@

2

EM

C_AD0 <28>

LP

C_AD1 <28>

LP

C_AD2 <28>

LP

C_AD3 <28>

LP

C_CLK0_EC <28>

LP

KRUN# <28>

CL

RIRQ <28>

SE

C_FRAME# <28>

LP

C_RST#_R <28>

LP

_SCI# <28>

EC

_RST# <28>

KB

U_SPI_CLK_R <8>

AP

C_RST#

LP

_RST#

KB

12

83 100K_0402_5%@

RC

29 150P_0402_50V8J

CC

12

85 10K_0402_5%@

RC

12

VS

+3

I

RT_0_ARXD_DTXD <16>

UA

RT_0_ATXD_DRXD <16>

UA

D_RST# <17>

SS

U_WL_OFF# <16>

AP

I ROM (XMC)

SP

2

U_SPI_MOSI

12
12
12
12
12

12

AP

U_SPI_MISO

AP

U_SPI_WP#

AP

U_SPI_HOLD#

AP

U_SPI_CS1#

AP

U_SPI_CLK

AP

EM

I

U_SPI_CS1#

AP

U_SPI_MISO

AP

U_SPI_WP#

AP

1
2
3
4

UC

CS
DO
WP
GND

S IC FL 64M XM25QU64AHIGT SOP 8P SPI ROM

SA0000BJU00

8

#

VCC

7

(IO1)

LD#(IO3)

HO

6

#(IO2)

K

CL

5

(IO0)

DI

U_SPI_HOLD#

AP

U_SPI_CLK_R

AP

U_SPI_MOSI

AP

+1

.8VALW

1

32

CC

0.1U_0201_10V6K

@

2

curity Classification

curity Classification

curity Classification

Se

Se

Se

ed Date

ed Date

ed Date

Issu

Issu

Issu

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

TH

TH

TH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS, INC.

A

B

C

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS, INC.

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

20

20

20

D

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

ciphered Date

ciphered Date

ciphered Date

De

De

De

Ti

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cu

Cu

Cu

Date: Sheet

Date: Sheet

Date: Sheet

stom

stom

stom

5 SATA/CLK/USB/SPI

5 SATA/CLK/USB/SPI

5 SATA/CLK/USB/SPI

FP

FP

FP

-H131P

-H131P

-H131P

LA

LA

LA

E

9 46Monday, November 05, 2018

9 46Monday, November 05, 2018

9 46Monday, November 05, 2018

of

of

of

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

Co

Title

tle

tle

Ti

4

4

4

0.

0.

0.

A

B

C

D

E

Main Func = CPU

+1.2V

U_CORE

U_CORE_SOC

1 1

CC3

CC3

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

1

2 2

2

6

5

2

CC5

CC5

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

3

4

2

2

BU(on bottom side under SOC)

All

CC3

22U_0603_6.3V6M

1

2

1U_0201_6.3V6M

22U_0603_6.3V6M

1

7

2

CC5

CC5

1U_0201_6.3V6M

1

6

5

2

@

CC5

CC3

1

8

2

CC5

1U_0201_6.3V6M

1

7

2

CC3

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

9

2

CC5

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

8

2

2

CC4

CC4

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

1

0

1

1

2

2

CC4

CC4

1U_0201_6.3V6M

22U_0603_6.3V6M

1

1

3

2

2

2

8VS

+0.

+VD

CC5

CC6

1U_0201_6.3V6M

1

9

0

2

@

CC6

CC6

1U_0201_6.3V6M

1

1

1

2

2

@

CC6

1U_0201_6.3V6M

180P_0402_50V8J

1

2

3

2

@

CC4

1U_0201_6.3V6M

4

DP_ALW

22U_0603_6.3V6M

1

2

CC4

180P_0402_50V8J

1

5

2

CC6

CC6

1U_0201_6.3V6M

1

1

5

4

2

2

@

Across VDDIO & VSS split.

CC4

180P_0402_50V8J

1

2

8VALW

+0.

CC6

1U_0201_6.3V6M

1

6

2

CC4

.22U 6.3V K X5R 0402

180P_0402_50V8J

1

1

6

7

2

2

8VS

+1.

CC6

1U_0201_6.3V6M

7

CC4

8

01 0_0402_5%@

RC1

CC4

.22U 6.3V K X5R 0402

1

9

2

1 2

CC5

CC5

.22U 6.3V K X5R 0402

1

2

.22U 6.3V K X5R 0402

1

0

1

2

IO_AUDIO

VDD

1

1

2

9

8

CC6

CC6

1U_

22U

2

0201_6.3V6M

_0603_6.3V6M

+AP

TDC :10A
EDC: 13A

2V

+1.

TDC :6A

BO BU

8VALW

+1.

CC7

22U_0603_6.3V6M

1U_0201_6.3V6M

1

1

0

2

2

3 3

BO BU BO BU

CC7

CC7

1U_0201_6.3V6M

1

2

1

2

CLEAR_CMOS#<28>

EC_

CC7

22U_0603_6.3V6M

1

3

2

06 0_0402_5%@

RC1

C1

1U

1

_0201_6.3V6M

@

2

1 2

8VS

+1.

CC7

1U_0201_6.3V6M

1

4

2

ALW

+3V

CC7

CC7

22U_0603_6.3V6M

1

1

5

2

2

@

CC7

1U_0201_6.3V6M

1U_0201_6.3V6M

1

6

7

2

S

+3V

CC7

CC7

10U_0402_6.3V6M

1U_0201_6.3V6M

1

1

8

2

9

2

@

Note : Cap placemet need to close APU

C_APU

+RT

RC1

@

12

CLR
SHORT PADS

P1

1 2

07 10K_0402_5%

1

1

CC8

0.22U_0402_6.3V6K

2

+RT

CBATT_R

V

1.5

1

UC1

3

t

Vou

1

Vin

2

GND

AP2138N-1.5TRG1_SOT23-3

SA000066U00

CC8

1U_0201_6.3V6M

1

0

2

S

+3V

+1.

ALW

+3V

8VALW

+0.

8VALW

IO_AUDIO

VDD

8VS

+1.

TDC :0.2A

TDC :0.25A

TDC :2A

TDC :0.5A

TDC :0.25A

8VS

+0.

TDC :1A

TDC :4A

C_APU

CBATT

+RT

12

2

CC8
1U_0201_6.3V6M

+RT

TDC :4.5uA

UC1F @

M15

CR_SOC_1

VDD

M18

CR_SOC_2

VDD

M19

CR_SOC_3

VDD

N16

CR_SOC_4

VDD

N18

CR_SOC_5

VDD

N20

CR_SOC_6

VDD

P17

CR_SOC_7

VDD

P19

CR_SOC_8

VDD

R18

CR_SOC_9

VDD

R20

CR_SOC_10

VDD

T19

CR_SOC_11

VDD

U18

CR_SOC_12

VDD

U20

CR_SOC_13

VDD

V19

CR_SOC_14

VDD

W18

CR_SOC_15

VDD

W20

CR_SOC_16

VDD

Y19

CR_SOC_17

VDD

T32

IO_MEM_S3_1

VDD

V28

IO_MEM_S3_2

VDD

W28

IO_MEM_S3_3

VDD

W32

IO_MEM_S3_4

VDD

Y22

IO_MEM_S3_5

VDD

Y25

IO_MEM_S3_6

VDD

Y28

IO_MEM_S3_7

VDD

0

AA2

IO_MEM_S3_8

VDD

3

AA2

IO_MEM_S3_9

VDD

6

AA2

IO_MEM_S3_10

VDD

8

AA2

IO_MEM_S3_11

VDD

2

AA3

IO_MEM_S3_12

VDD

0

AC2

IO_MEM_S3_13

VDD

2

AC2

IO_MEM_S3_14

VDD

5

AC2

IO_MEM_S3_15

VDD

8

AC2

IO_MEM_S3_16

VDD

3

AD2

IO_MEM_S3_17

VDD

6

AD2

IO_MEM_S3_18

VDD

8

AD2

IO_MEM_S3_19

VDD

2

AD3

IO_MEM_S3_20

VDD

0

AE2

IO_MEM_S3_21

VDD

2

AE2

IO_MEM_S3_22

VDD

5

AE2

IO_MEM_S3_23

VDD

8

AE2

IO_MEM_S3_24

VDD

3

AF2

IO_MEM_S3_25

VDD

6

AF2

IO_MEM_S3_26

VDD

8

AF2

IO_MEM_S3_27

VDD

2

AF3

IO_MEM_S3_28

VDD

0

AG2

IO_MEM_S3_29

VDD

2

AG2

IO_MEM_S3_30

VDD

5

AG2

IO_MEM_S3_31

VDD

8

AG2

IO_MEM_S3_32

VDD

0

AJ2

IO_MEM_S3_33

VDD

3

AJ2

IO_MEM_S3_34

VDD

6

AJ2

IO_MEM_S3_35

VDD

8

AJ2

IO_MEM_S3_36

VDD

2

AJ3

IO_MEM_S3_37

VDD

8

AK2

IO_MEM_S3_38

VDD

8

AL2

IO_MEM_S3_39

VDD

2

AL3

IO_MEM_S3_40

VDD

2

AP1

IO_AUDIO

VDD

8

AL1

_33_1

VDD

7

AM1

_33_2

VDD

0

AL2

_18_1

VDD

9

AM1

_18_2

VDD

9

AL1

_18_S5_1

VDD

8

AM1

_18_S5_2

VDD

7

AL1

_33_S5_1

VDD

6

AM1

_33_S5_2

VDD

4

AL1

P_S5_1

VDD

5

AL1

P_S5_2

VDD

4

AM1

P_S5_3

VDD

3

AL1

P_1

VDD

2

AM1

P_2

VDD

3

AM1

P_3

VDD

2

AN1

P_4

VDD

3

AN1

P_5

VDD

1

AT1

BT_RTC_G

VDD

_BGA1140~D

FP5

ER

POW

REV 0.90

FP5

T 6 OF 13

PAR

G7

CR_1

VDD

G10

CR_2

VDD

G12

CR_3

VDD

G14

CR_4

VDD

H8

CR_5

VDD

H11

CR_6

VDD

H15

CR_7

VDD

K7

CR_8

VDD

K12

CR_9

VDD

K14

CR_10

VDD

L8

CR_11

VDD

M7

CR_12

VDD

M10

CR_13

VDD

N14

CR_14

VDD

P7

CR_15

VDD

P10

CR_16

VDD

P13

CR_17

VDD

P15

CR_18

VDD

R8

CR_19

VDD

R14

CR_20

VDD

R16

CR_21

VDD

T7

CR_22

VDD

T10

CR_23

VDD

T13

CR_24

VDD

T15

CR_25

VDD

T17

CR_26

VDD

U14

CR_27

VDD

U16

CR_28

VDD

V13

CR_29

VDD

V15

CR_30

VDD

V17

CR_31

VDD

W7

CR_32

VDD

W10

CR_33

VDD

W14

CR_34

VDD

W16

CR_35

VDD

Y8

CR_36

VDD

Y13

CR_37

VDD

Y15

CR_38

VDD

Y17

CR_39

VDD

AA7

CR_40

VDD

0

AA1

CR_41

VDD

4

AA1

CR_42

VDD

6

AA1

CR_43

VDD

8

AA1

CR_44

VDD

3

AB1

CR_45

VDD

5

AB1

CR_46

VDD

7

AB1

CR_47

VDD

9

AB1

CR_48

VDD

4

AC1

CR_49

VDD

6

AC1

CR_50

VDD

8

AC1

CR_51

VDD

AD7

CR_52

VDD

0

AD1

CR_53

VDD

3

AD1

CR_54

VDD

5

AD1

CR_55

VDD

7

AD1

CR_56

VDD

9

AD1

CR_57

VDD

AE8

CR_58

VDD

4

AE1

CR_59

VDD

6

AE1

CR_60

VDD

8

AE1

CR_61

VDD

AF7

CR_62

VDD

0

AF1

CR_63

VDD

3

AF1

CR_64

VDD

5

AF1

CR_65

VDD

7

AF1

CR_66

VDD

9

AF1

CR_67

VDD

4

AG1

CR_68

VDD

6

AG1

CR_69

VDD

8

AG1

CR_70

VDD

3

AH1

CR_71

VDD

5

AH1

CR_72

VDD

7

AH1

CR_73

VDD

9

AH1

CR_74

VDD

AJ7

CR_75

VDD

0

AJ1

CR_76

VDD

4

AJ1

CR_77

VDD

6

AJ1

CR_78

VDD

8

AJ1

CR_79

VDD

3

AK1

CR_80

VDD

5

AK1

CR_81

VDD

7

AK1

CR_82

VDD

9

AK1

CR_83

VDD

TDC: 35A
EDC: 45A

+AP

4 4

rity Classification

urity Classification

urity Classification

Secu

Sec

Sec

ssu

d Date

ued Date

ued Date

I

e

Iss

Iss

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

8/11/05 2019/11/05

8/11/05 2019/11/05

8/11/05 2019/11/05

201

201

201

Compal Secret Data

pal Secret Data

pal Secret Data

Com

Com

Deciphered Date

Deciphered Date

Deciphered Date

pal Electronics, Inc.

pal Electronics, Inc.

pal Electronics, Inc.

Com

Com

le

le

le

Tit

Tit

Tit

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cus

Cus

Cus

Date : Sheet

Date : Sheet

D

Date : Sheet

Com

PWR

PWR

PWR

FP4

FP4

tom

tom

tom

FP4

LA-

LA-

LA-

H131P

H131P

H131P

E

0.4

0.4

0.4

f

f

f

10 46Monday, November 05, 2018

10 46Monday, November 05, 2018

10 46Monday, November 05, 2018

o

o

o

5

Main Func = CPU

4

3

2

1

8

A1

8

C1

5

A1

5

C1

6

B1

6

C1

9

C1

8

B1

7

B1

7

D1

2

D1

2

B1

3

C1

3

A1

1

B1

2

C1

3

J1

UC1L @

1

T1

RS

7

AC

RS

Y9

RS

0

Y1

RS

1

W1

RS

2

W1

RS

V9

RS

0

V1

RS

12

AA

RS

10

AC

RS

FP

UC1M @

M0_CSI2_CLOCKP

CA

M0_CSI2_CLOCKN

CA

M0_CSI2_DATAP0

CA

M0_CSI2_DATAN0

CA

M0_CSI2_DATAP1

CA

M0_CSI2_DATAN1

CA

M0_CSI2_DATAP2

CA

M0_CSI2_DATAN2

CA

M0_CSI2_DATAP3

CA

M0_CSI2_DATAN3

CA

M1_CSI2_CLOCKP

CA

M1_CSI2_CLOCKN

CA

M1_CSI2_DATAP0

CA

M1_CSI2_DATAN0

CA

M1_CSI2_DATAP1

CA

M1_CSI2_DATAN1

CA

VD_6

RS

5_BGA1140~D

FP

VD_32

VD_66

VD_55

VD_56

VD_47

VD_48

VD_38

VD_39

VD_64

VD_68

5_BGA1140~D

RS

FP5 REV 0.90

RT 12 OF 13

PA

MERAS

CA

FP5 REV 0.90

RT 13 OF 13

PA

VD

VD_62

RS

VD_61

RS

VD_65

RS

VD_72

RS

VD_67

RS

VD_63

RS

VD_33

RS

VD_73

RS

VD_53

RS

VD_54

RS

VD_45

RS

VD_46

RS

CA

M0_I2C_SCL

CA

M0_I2C_SDA

CA

M0_SHUTDOWN

CA

CA

M1_I2C_SCL

CA

M1_I2C_SDA

CA

M1_SHUTDOWN

CA

M_PRIV_LED

CA

CA

9

AA

8

AA

6

AC

11

AD

9

AC

11

AA

2

T1

12

AD

Y6
Y7

W8
W9

M0_CLK

M1_CLK

M_IR_ILLU

5

B1

5

D1

4

C1

3

B1

0

B1

1

A1

1

C1

1

D1

3

D1

0

D1

AW

AR
AR
AR
AR
AR
AR
AR
AR

AU
AU
AU
AU
AU
AU
AU
AU

AV
AV
AV
AV
AV
AV
AV
AV
AV
AV

AY
AY
AY
AY
AY
AY
AY
AY
AY
AY
AY
AY
AY
AY
AY
AY

BB
BB

BD
BD
BD

AW

AR
AR

AU
AU

AV
AV
AV

AY
AY
AY

BB

BD
BD

5

7
12
14
16
19
21
26
28
32

5

8
11
13
15
18
20
22
25
28

1

5

7
10
12
14
16
19
21
23
26
28
32

5
28

6

7

8
10
11
12
13
14
15
16
18
19
20
21
22
23
25
26
27

1
20
32

3

7
10
12
14

UC1K @

FP

S_248

VS

S_249

VS

S_250

VS

S_251

VS

S_252

VS

S_253

VS

S_254

VS

S_255

VS

S_256

VS

S_257

VS

S_258

VS

S_259

VS

S_260

VS

S_261

VS

S_262

VS

S_263

VS

S_264

VS

S_265

VS

S_266

VS

S_267

VS

S_268

VS

S_269

VS

S_270

VS

S_271

VS

S_272

VS

S_273

VS

S_274

VS

S_275

VS

S_276

VS

S_277

VS

S_278

VS

S_279

VS

S_280

VS

S_281

VS

S_282

VS

S_283

VS

S_284

VS

S_285

VS

S_286

VS

S_287

VS

S_288

VS

S_289

VS

S_290

VS

S_291

VS

S_292

VS

S_293

VS

S_294

VS

S_295

VS

S_296

VS

S_297

VS

S_298

VS

S_299

VS

S_300

VS

S_301

VS

S_302

VS

S_303

VS

S_304

VS

S_305

VS

S_306

VS

S_307

VS

S_308

VS

S_309

VS

FP5 REV 0.90

PA

5_BGA1140~D

D/RSVD

GN

RT 11 OF 13

16

BD

S_310

VS

19

BD

S_311

VS

21

BD

S_312

VS

23

BD

S_313

VS

26

BD

S_314

VS

30

BD

S_315

VS

0

B2

VD_1

RS

G3

VD_5

RS

0

J2

VD_7

RS

K3

VD_8

RS

K6

VD_9

RS

0

K2

VD_10

RS

M3

VD_11

RS

M6

VD_12

RS

3

M1

VD_13

RS

P6

VD_22

RS

2

P2

VD_23

RS

T3

VD_30

RS

T6

VD_31

RS

9

T2

VD_37

RS

W6

VD_44

RS

1

W2

VD_49

RS

2

W2

VD_50

RS

1

Y2

VD_57

RS

7

Y2

VD_58

RS

3

AA

VD_59

RS

6

AA

VD_60

RS

29

AC

VD_69

RS

3

AD

VD_70

RS

6

AD

VD_71

RS

3

AF

VD_74

RS

6

AF

VD_75

RS

30

AF

VD_78

RS

6

AJ

VD_79

RS

24

AJ

VD_80

RS

23

AK

VD_81

RS

27

AK

VD_82

RS

3

AL

VD_83

RS

29

AN

VD_87

RS

31

AN

VD_88

RS

4

M1

VD_14

RS

6

AL

VD_84

RS

11

AL

VD_85

RS

16

AN

VD_86

RS

N1

A3
A5

A7
A1
A1
A1
A1
A1
A2
A2
A2
A3

C3
C3
D1
D1
D2

E7

E8
E1
E1
E1
E1
E1
E1
E1
E1
E1
E2
E2
E2
E2
E2
E2
E2

F5

F2

G1

G5
G1
G1
G2
G2
G2
G2
G3

H5
H1
H1
H2
H2
H2
H2

K1

K5
K1
K1
K2
K2
K2
K2

UC1G @

2

0
2
4
6
9
1
3
6
0

2
6
8
0

0
1
2
3
4
5
6
8
9
0
1
2
3
5
6
7

8

6
9
1
3
6
8
2

3
8
0
2
5
8

6
9
1
2
6
8

FP

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

S_316

S_1

S_2

S_3

S_4

S_5

S_6

S_7

S_8

S_9

S_10

S_11

S_12

S_13

S_14

S_15

S_16

S_17

S_18

S_19

S_20

S_21

S_22

S_23

S_24

S_25

S_26

S_27

S_28

S_29

S_30

S_31

S_32

S_33

S_34

S_35

S_36

S_37

S_38

S_39

S_40

S_41

S_42

S_43

S_44

S_45

S_46

S_47

S_48

S_49

S_50

S_51

S_52

S_53

S_54

S_55

S_56

S_57

S_58

S_59

S_60

S_61

5 REV 0.90

FP

RT 7 OF 13

PA

5_BGA1140~D

GND

2

K3

S_62

VS

L5

S_63

VS

3

L1

S_64

VS

5

L1

S_65

VS

8

L1

S_66

VS

0

L2

S_67

VS

5

L2

S_68

VS

8

L2

S_69

VS

M1

S_70

VS

M5

S_71

VS

2

M1

S_72

VS

1

M2

S_73

VS

3

M2

S_74

VS

6

M2

S_75

VS

8

M2

S_76

VS

2

M3

S_77

VS

N4

S_78

VS

N5

S_79

VS

N8

S_80

VS

1

N1

S_81

VS

3

N1

S_82

VS

5

N1

S_83

VS

7

N1

S_84

VS

9

N1

S_85

VS

2

N2

S_86

VS

5

N2

S_87

VS

8

N2

S_88

VS

P1

S_89

VS

P5

S_90

VS

4

P1

S_91

VS

6

P1

S_92

VS

8

P1

S_93

VS

0

P2

S_94

VS

3

P2

S_95

VS

6

P2

S_96

VS

8

P2

S_97

VS

2

P3

S_98

VS

R5

S_99

VS

1

R1

S_100

VS

2

R1

S_101

VS

3

R1

S_102

VS

5

R1

S_103

VS

7

R1

S_104

VS

9

R1

S_105

VS

2

R2

S_106

VS

5

R2

S_107

VS

8

R2

S_108

VS

0

R3

S_109

VS

T1

S_110

VS

T5

S_111

VS

4

T1

S_112

VS

6

T1

S_113

VS

8

T1

S_114

VS

0

T2

S_115

VS

3

T2

S_116

VS

6

T2

S_117

VS

8

T2

S_118

VS

3

U1

S_119

VS

5

U1

S_120

VS

7

U1

S_121

VS

9

U1

S_122

VS

V5

S_123

VS

D D

C C

B B

AA
AA
AA
AA
AB
AB
AB
AB

AC
AC
AC
AC
AC
AC

AD
AD
AD
AD

AE
AE
AE
AE
AE
AE

AF
AF
AF
AF

V8
V1
V1
V1
V1
V1
V2
V2
V2

W1

W5
W1
W1
W1
W1
W2
W2

Y5
Y1
Y1
Y1
Y1
Y1
Y2
AA
AA

13

15

17

19

14

16

18

20

AC
AC

11

12

13

15

17

19

AD
AD

14

16

18

20
AE

11

12

13

15

17

19
AF
AF

14

16

18

20

AG

UC1H @

S_124

VS

1

S_125

VS

2

S_126

VS

4

S_127

VS

6

S_128

VS

8

S_129

VS

0

S_130

VS

2

S_131

VS

5

S_132

VS

S_133

VS

S_134

VS

3

S_135

VS

5

S_136

VS

7

S_137

VS

9

S_138

VS

3

S_139

VS

6

S_140

VS

S_141

VS

1

S_142

VS

2

S_143

VS

4

S_144

VS

6

S_145

VS

8

S_146

VS

0

S_147

VS

1

S_148

VS

5

S_149

VS

S_150

VS

S_151

VS

S_152

VS

S_153

VS

S_154

VS

S_155

VS

S_156

VS

S_157

VS

5

S_158

VS

8

S_159

VS

S_160

VS

S_161

VS

S_162

VS

S_163

VS

S_164

VS

S_165

VS

1

S_166

VS

5

S_167

VS

S_168

VS

S_169

VS

S_170

VS

S_171

VS

5

S_172

VS

S_173

VS

S_174

VS

S_175

VS

S_176

VS

S_177

VS

S_178

VS

1

S_179

VS

5

S_180

VS

S_181

VS

S_182

VS

S_183

VS

S_184

VS

5

S_185

VS

5_BGA1140~D

FP

5 REV 0.90

FP

RT 8 OF 13

PA

GND

8

AG

S_186

VS

11

AG

S_187

VS

12

AG

S_188

VS

13

AG

S_189

VS

15

AG

S_190

VS

17

AG

S_191

VS

19

AG

S_192

VS

14

AH

S_193

VS

16

AH

S_194

VS

18

AH

S_195

VS

20

AH

S_196

VS

1

AJ

S_197

VS

5

AJ

S_198

VS

13

AJ

S_199

VS

15

AJ

S_200

VS

17

AJ

S_201

VS

19

AJ

S_202

VS

5

AK

S_203

VS

8

AK

S_204

VS

11

AK

S_205

VS

12

AK

S_206

VS

14

AK

S_207

VS

16

AK

S_208

VS

18

AK

S_209

VS

20

AK

S_210

VS

22

AK

S_211

VS

25

AK

S_212

VS

1

AL

S_213

VS

5

AL

S_214

VS

7

AL

S_215

VS

10

AL

S_216

VS

12

AL

S_217

VS

16

AL

S_218

VS

23

AL

S_219

VS

26

AL

S_220

VS

5

AM

S_221

VS

8

AM

S_222

VS

15

AM

S_223

VS

20

AM

S_224

VS

22

AM

S_225

VS

25

AM

S_226

VS

28

AM

S_227

VS

1

AN

S_228

VS

5

AN

S_229

VS

7

AN

S_230

VS

10

AN

S_231

VS

15

AN

S_232

VS

18

AN

S_233

VS

21

AN

S_234

VS

23

AN

S_235

VS

26

AN

S_236

VS

28

AN

S_237

VS

32

AN

S_238

VS

5

AP

S_239

VS

8

AP

S_240

VS

13

AP

S_241

VS

15

AP

S_242

VS

18

AP

S_243

VS

20

AP

S_244

VS

25

AP

S_245

VS

28

AP

S_246

VS

1

AR

S_247

VS

A A

curity Classification

curity Classification

curity Classification

Se

Se

Se

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

20

20

Issued Date

Issued Date

Issued Date

IS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

TH

TH

TH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

20

Co

Co

Co

3

mpal Secret Data

mpal Secret Data

mpal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

tle

tle

tle

Ti

Ti

Ti

ze

ze

ze

Si

Do

Si

Do

Si

Do

stom

stom

stom

Cu

Cu

Cu

Dat e: Sheet

Dat e: Sheet

2

Dat e: Sheet

Co

5 GND

5 GND

5 GND

FP

FP

FP

cument Number Re v

cument Number Re v

cument Number Re v

-H131P

-H131P

-H131P

LA

LA

LA

11 46Monday, November 05, 2018

11 46Monday, November 05, 2018

11 46Monday, November 05, 2018

o f

o f

1

o f

4

4

4

0.

0.

0.

5

4

DDR4 - MEMORY DOWN (MEMORY CHANNEL A, x16 x4 PCS)

3

2

1

DDR_A_DQ[63..0]

DDR_A_DM[7..0]

.2V

.2V

+1

OBR@

1 2

3 0 .1U_0201_10 V6K

CD

@

1 2

4 0 .1U_0201_10 V6K

CD

2

5

CD

@

1

2

6

CD

0.1U_0201_1 0V6K

OBR@

1

+1

RD

.6VS

+0

RD

.2V

+1

RD
1K_0402_1 %

OBR@

1 2

RD
1K_0402_1 %

OBR@

1 2

DD
DD
DD
DD

D D

0.1U_0201_1 0V6K

C C

VREF traces should be at least 20mils wide
20mils spacing to other sig nals

B B

A A

1 2

1 1K_ 0402_5%OBR@

1 2

2 39_ 0402_5%OBR@

32

37

+0

R_A_DQS5#<5>
R_A_DQS5<5>
R_A_DQS4#<5>
R_A_DQS4<5>

1 2

28 39_0 402_5%OBR@

RD

1 2

29 39_0 402_5%OBR@

RD

Memory

.6V_DDRA_VREFCA

+0

.6V_DDRA_VREFCA

OBR@

CD

1

8

.047U_0402_16V7K

2

RD

.5V

+2

DDR_A_DQ[63..0] <5>

DDR_A_DM[7..0] <5>

DD

DD

Side

2

7

CD

0.1U_0201_1 0V6K

OBR@

1

R_A_MA0

DD

R_A_MA1

DD

R_A_MA2

DD

R_A_MA3

DD

R_A_MA4

DD

R_A_MA5

DD

R_A_MA6

DD

R_A_MA7

DD

R_A_MA8

DD

R_A_MA9

DD

R_A_MA10

DD

R_A_MA11

DD

R_A_MA12

DD

R_A_MA13

DD

R_A_WE#

DD

R_A_BA0

DD

R_A_BA1

DD

R_A_DM5

DD

R_A_DM4

DD

R_A_CLK0

DD

R_A_CLK0#

DD

R_A_CKE0

DD

R_A_ODT0

DD

R_A_CS0#

DD

R_A_RAS#

DD

R_A_CAS#

DD

R_A_RST#

DD

1 2

40

OBR@

240_0201_ 1%

R_A_ACT#

DD

R_A_BG0

DD

R_A_ALERT#

DD

R_A_PAR

DD

R_A_ALERT#

R_A_PAR

DD

DD

R_A_CLK0

R_A_CLK0#

M1

3

P

7

P

3

R

7

N

3

N

8

P

2

P

8

R

2

R

7

R
M3

T2

M7

T8
L2

N2
N8

E2
E7

K7
K8
K2

K3
L7
L8

M8

A7
B7
F3

G3

P1

9

F

L3
M2
N9

P9

T3

7

T

B1
R9

+0.6V_DDRA_VREFCA +0.6V_DDRA_VREFCA

OBR@

CD

1

2

R_A_MA0<5>

DD

.047U_0402_16V7K

R_A_MA1<5>

DD

R_A_MA2<5>

DD

2

R_A_MA3<5>

DD

R_A_MA4<5>

DD

R_A_MA5<5>

DD

R_A_MA6<5>

DD

R_A_MA7<5>

DD

R_A_MA8<5>

DD

R_A_MA9<5>

DD

R_A_MA10<5>

DD

R_A_MA11<5>

DD

R_A_MA12<5>

DD

R_A_MA13<5>

DD

R_A_WE#<5>

DD

R_A_BA0<5>

DD

R_A_BA1<5>

DD

R_A_DM1

DD

R_A_DM0

DD

R_A_CLK0<5>

DD

R_A_CLK0#<5>

DD

R_A_CKE0<5>

DD

R_A_ODT0<5>

DD

R_A_CS0#<5>

DD

R_A_RAS#<5>

DD

R_A_CAS#<5>

DD

R_A_DQS1#<5>

DD

R_A_DQS1<5>

DD

R_A_DQS0#<5>

DD

R_A_DQS0<5>

DD

R_A_RST#<5>

DD

1 2

35

OBR@

RD

240_0201_ 1%

R_A_ACT#<5>

DD

R_A_BG0<5>

DD

R_A_ALERT#<5>

DD

R_A_PAR<5>

DD

.5V

+2

3

UD

EFCA

VR

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

0/AP

A1

1

A1

2/BC

A1

3

A1

4/WE

A1

0

BA

1

BA

U/DBIU

DM

L/DBIL

DM

_t

CK

_c

CK

E

CK

T

OD
CS

S

RA

S

CA

SU_c

DQ

SU_t

DQ

SL_c

DQ

SL_t

DQ

SET

RE

ZQ

T

AC

0

BG

N

TE

ERT

AL

R

PA

NC

P

VP

P

VP

-BALL

96

SDRAM DDR4

K4A8G165WB -BCPB_FBGA96

SA00008Z000

@

R_A_DQ32

DD

G2

R_A_DQ39

DD

L0

DQ

F7

R_A_DQ33

DD

L1

DQ

H3

R_A_DQ37

DD

L2

DQ

H7

R_A_DQ38

DD

L3

DQ

H2

R_A_DQ35

DD

L4

DQ

H8

R_A_DQ36

DD

L5

DQ

J3

R_A_DQ34

DD

L6

DQ

J7

L7

DQ

R_A_DQ44

DD

A3

R_A_DQ42

DD

U0

DQ

B8

R_A_DQ45

DD

U1

DQ

C3

R_A_DQ47

DD

U2

DQ

C7

R_A_DQ40

DD

U3

DQ

C2

R_A_DQ43

DD

U4

DQ

C8

R_A_DQ41

DD

U5

DQ

D3

R_A_DQ46

DD

U6

DQ

D7

U7

DQ

B3

D

VD

B9

D

VD

D1

D

VD

G7

D

VD

J1

D

VD

J9

D

VD

L1

D

VD

L9

D

VD

R1

D

VD

T9

D

VD

A1

DQ

VD

A9

DQ

VD

C1

DQ

VD

D9

DQ

VD

F2

DQ

VD

F8

DQ

VD

G1

DQ

VD

G9

DQ

VD

J2

DQ

VD

J8

DQ

VD

B2

S

VS

E1

S

VS

E9

S

VS

G8

S

VS

K1

S

VS

K9

S

VS

M9

S

VS

N1

S

VS

T1

S

VS

A2

SQ

VS

A8

SQ

VS

C9

SQ

VS

D2

SQ

VS

D8

SQ

VS

E3

SQ

VS

E8

SQ

VS

F1

SQ

VS

H1

SQ

VS

H9

SQ

VS

38 0_02 01_5%DDP@

RD

DD

1 2

R_A_BG1_R

.2V

+1

UD1

M1

VREFCA

3

P

A0

7

P

A1

3

R

A2

7

N

A3

3

N

A4

8

P

A5

2

P

A6

8

R

A7

2

R

A8

7

R

A9

M3

0/AP

A1

T2

1

A1

M7

2/BC

A1

T8

3

A1

L2

4/WE

A1

N2

0

BA

N8

1

BA

E2

U/DBIU

DM

E7

L/DBIL

DM

K7

_t

CK

K8

_c

CK

K2

E

CK

K3

T

OD

L7

CS

L8

S

RA

M8

S

CA

A7

SU_c

DQ

B7

SU_t

DQ

F3

SL_c

DQ

G3

SL_t

DQ

P1

SET

RE

9

F

ZQ

L3

T

AC

M2

0

BG

N9

N

TE

P9

ERT

AL

T3

R

PA

7

T

NC

B1

P

VP

R9

P

VP

-BALL

96

SDRAM DDR4

K4A8G165WB -BCPB_FBGA96

SA00008Z000

@

R_A_DQS7#<5>

DD

R_A_DQS7<5>

DD

R_A_DQS6#<5>

DD

R_A_DQS6<5>

DD

DQL0
DQL1

L2

DQ

L3

DQ

L4

DQ

L5

DQ

L6

DQ

L7

DQ

U0

DQ

U1

DQ

U2

DQ

U3

DQ

U4

DQ

U5

DQ

U6

DQ

U7

DQ

D

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

VD

DQ

VD

DQ

VD

DQ

VD

DQ

VD

DQ

VD

DQ

VD

DQ

VD

DQ

VD

DQ

VD

DQ

VD

S

VS

S

VS

S

VS

S

VS

S

VS

S

VS

S

VS

S

VS

S

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

.6V_DDRA_VREFCA

+0

OBR@

DDR_A_DQ1

G2

DDR_A_DQ7

F7

DDR_A_DQ4

H3

R_A_DQ6

DD

H7

R_A_DQ5

DD

H2

R_A_DQ3

DD

H8

R_A_DQ0

DD

J3

R_A_DQ2

DD

J7

R_A_DQ12

DD

A3

R_A_DQ11

DD

B8

R_A_DQ9

DD

C3

R_A_DQ14

DD

C7

R_A_DQ8

DD

C2

R_A_DQ15

DD

C8

R_A_DQ13

DD

D3

R_A_DQ10

DD

D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

CD

1

9

.047U_0402_16V7K

2

+2

RD

.5V

DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD

DD
DD

DD
DD

DD
DD
DD

DD
DD
DD
DD

DD

1 2

41

240_0201_ 1%

DD
DD

DD
DD

33 0_02 01_5%DDP@

RD

R_A_BG1_R

DD

R_A_MA0
R_A_MA1
R_A_MA2
R_A_MA3
R_A_MA4
R_A_MA5
R_A_MA6
R_A_MA7
R_A_MA8
R_A_MA9
R_A_MA10
R_A_MA11
R_A_MA12
R_A_MA13
R_A_WE#

R_A_BA0
R_A_BA1

R_A_DM7
R_A_DM6

R_A_CLK0
R_A_CLK0#
R_A_CKE0

R_A_ODT0
R_A_CS0#
R_A_RAS#
R_A_CAS#

R_A_RST#

OBR@

R_A_ACT#
R_A_BG0

R_A_ALERT#
R_A_PAR

+1

1 2

.2V

M1

3

P

7

P

3

R

7

N

3

N

8

P

2

P

8

R

2

R

7

R
M3
T2
M7
T8
L2

N2
N8

E2
E7

K7
K8
K2

K3
L7
L8
M8

A7
B7
F3
G3

P1

9

F

L3
M2
N9
P9
T3

7

T
B1
R9

4

UD

EFCA

VR

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

0/AP

A1

1

A1

2/BC

A1

3

A1

4/WE

A1

0

BA

1

BA

U/DBIU

DM

L/DBIL

DM

_t

CK

_c

CK

E

CK

T

OD
CS

S

RA

S

CA

SU_c

DQ

SU_t

DQ

SL_c

DQ

SL_t

DQ

SET

RE

ZQ

T

AC

0

BG

N

TE

ERT

AL

R

PA

NC

P

VP

P

VP

-BALL

96

SDRAM DDR4

K4A8G165WB -BCPB_FBGA96

SA00008Z000

@

UD2

M1

OBR@

CD

1

1 . 047U_0402_16V7K

R_A_MA0

DD

R_A_MA1

DD

R_A_MA2

DD

R_A_MA3

DD

2

R_A_MA4

DD

R_A_MA5

DD

R_A_MA6

DD

R_A_MA7

DD

R_A_MA8

DD

R_A_MA9

DD

R_A_MA10

DD

R_A_MA11

DD

R_A_MA12

DD

R_A_MA13

DD

R_A_WE#

DD

R_A_BA0

DD

R_A_BA1

DD

R_A_DM3

DD

R_A_DM2

DD

R_A_CLK0

DD

R_A_CLK0#

DD

R_A_CKE0

DD

R_A_ODT0

DD

R_A_CS0#

DD

R_A_RAS#

DD

R_A_CAS#

DD

R_A_DQS3#<5>

DD

R_A_DQS3<5>

DD

R_A_DQS2#<5>

DD

R_A_DQS2<5>

DD

R_A_DQ48

DD

G2

R_A_DQ51

DD

L0

DQ

F7

R_A_DQ49

DD

L1

DQ

H3

R_A_DQ55

DD

L2

DQ

H7

R_A_DQ53

DD

L3

DQ

H2

R_A_DQ50

DD

L4

DQ

H8

R_A_DQ52

DD

L5

DQ

J3

R_A_DQ54

DD

L6

DQ

J7

L7

DQ

R_A_DQ56

DD

A3

R_A_DQ62

DD

U0

DQ

B8

R_A_DQ60

DD

U1

DQ

C3

R_A_DQ63

DD

U2

DQ

C7

R_A_DQ57

DD

U3

DQ

C2

R_A_DQ58

DD

U4

DQ

C8

R_A_DQ61

DD

U5

DQ

D3

R_A_DQ59

DD

U6

DQ

D7

U7

DQ

B3

D

VD

B9

D

VD

D1

D

VD

G7

D

VD

J1

D

VD

J9

D

VD

L1

D

VD

L9

D

VD

R1

D

VD

T9

D

VD

A1

DQ

VD

A9

DQ

VD

C1

DQ

VD

D9

DQ

VD

F2

DQ

VD

F8

DQ

VD

G1

DQ

VD

G9

DQ

VD

J2

DQ

VD

J8

DQ

VD

B2

S

VS

E1

S

VS

E9

S

VS

G8

S

VS

K1

S

VS

K9

S

VS

M9

S

VS

N1

S

VS

T1

S

VS

A2

SQ

VS

A8

SQ

VS

C9

SQ

VS

D2

SQ

VS

D8

SQ

VS

E3

SQ

VS

E8

SQ

VS

F1

SQ

VS

H1

SQ

VS

H9

SQ

VS

RD

DD

+2

1 2

39 0_02 01_5%DDP@

R_A_BG1_R

R_A_RST#

DD

1 2

36

OBR@

RD

240_0201_ 1%

R_A_ACT#

DD

R_A_BG0

DD

R_A_ALERT#

DD

R_A_PAR

DD

.5V

.2V

+1

VREFCA

3

P

A0

7

P

A1

3

R

A2

7

N

A3

3

N

A4

8

P

A5

2

P

A6

8

R

A7

2

R

A8

7

R

A9

M3

0/AP

A1

T2

1

A1

M7

2/BC

A1

T8

3

A1

L2

4/WE

A1

N2

0

BA

N8

1

BA

E2

U/DBIU

DM

E7

L/DBIL

DM

K7

_t

CK

K8

_c

CK

K2

E

CK

K3

T

OD

L7

CS

L8

S

RA

M8

S

CA

A7

SU_c

DQ

B7

SU_t

DQ

F3

SL_c

DQ

G3

SL_t

DQ

P1

SET

RE

9

F

ZQ

L3

T

AC

M2

0

BG

N9

N

TE

P9

ERT

AL

T3

R

PA

7

T

NC

B1

P

VP

R9

P

VP

-BALL

96

SDRAM DDR4

K4A8G165WB -BCPB_FBGA96

SA00008Z000

@

DDR_A_DQ16

G2

DDR_A_DQ19

DQL0

F7

DDR_A_DQ21

DQL1

H3

R_A_DQ22

DD

L2

DQ

H7

R_A_DQ20

DD

L3

DQ

H2

R_A_DQ23

DD

L4

DQ

H8

R_A_DQ17

DD

L5

DQ

J3

R_A_DQ18

DD

L6

DQ

J7

L7

DQ

R_A_DQ25

DD

A3

R_A_DQ31

DD

U0

DQ

B8

R_A_DQ30

DD

U1

DQ

C3

R_A_DQ26

DD

U2

DQ

C7

R_A_DQ24

DD

U3

DQ

C2

R_A_DQ29

DD

U4

DQ

C8

R_A_DQ28

DD

U5

DQ

D3

R_A_DQ27

DD

U6

DQ

D7

U7

DQ

B3

D

VD

B9

D

VD

D1

D

VD

G7

D

VD

J1

D

VD

J9

D

VD

L1

D

VD

L9

D

VD

R1

D

VD

T9

D

VD

A1

DQ

VD

A9

DQ

VD

C1

DQ

VD

D9

DQ

VD

F2

DQ

VD

F8

DQ

VD

G1

DQ

VD

G9

DQ

VD

J2

DQ

VD

J8

DQ

VD

B2

S

VS

E1

S

VS

E9

S

VS

G8

S

VS

K1

S

VS

K9

S

VS

M9

S

VS

N1

S

VS

T1

S

VS

A2

SQ

VS

A8

SQ

VS

C9

SQ

VS

D2

SQ

VS

D8

SQ

VS

E3

SQ

VS

E8

SQ

VS

F1

SQ

VS

H1

SQ

VS

H9

SQ

VS

.5V

+2

.2V

+1

1 2

34 0_02 01_5%DDP@

RD

R_A_BG1_R

DD

.2V

+1

33 0.22 U_0402_6.3V6K OBR@

CD

35 0.22 U_0402_6.3V6K OBR@

CD

37 0.22 U_0402_6.3V6K OBR@

CD

39 0.22 U_0402_6.3V6K OBR@

CD

41 0.22 U_0402_6.3V6K OBR@

CD

1U_0201_6.3V6M

10U 6.3V M X5R 0402

1U_0201_6.3V6M

CD

CD

CD

1

1

1

43

44

42

OBR@

@

OBR@

2

2

2

Closed to UD1 Closed to UD2 Closed to UD3

1 2

1 2

1 2

1 2

1 2

+0.6VS

.2V

+1

C

CD

CD

C

D

D

13

10 0.22U_0402_6.3V6K OBR@

11

12

1

1

1

0

0.

0

.

.

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

2

2

2

.5V

+2

1U_0201_6.3V6M

1U_0201_6.3V6M

C

CD

D

1

1

46

45

OBR@

@

2

2

1 2

RD3 39 _0402_5%OBR@

1 2

RD4 39 _0402_5%OBR@

1 2

RD5 39 _0402_5%OBR@

1 2

6 39_ 0402_5%OBR@

RD

1 2

7 39_ 0402_5%OBR@

RD

1 2

8 39_ 0402_5%OBR@

RD

1 2

9 39_ 0402_5%OBR@

RD

1 2

10 39_0 402_5%OBR@

RD

1 2

11 39_0 402_5%OBR@

RD

1 2

12 39_0 402_5%OBR@

RD

1 2

13 39_0 402_5%OBR@

RD

1 2

14 39_0 402_5%OBR@

RD

1 2

15 39_0 402_5%OBR@

RD

1 2

16 39_0 402_5%OBR@

RD

1 2

17 39_0 402_5%OBR@

RD

1 2

18 39_0 402_5%OBR@

RD

1 2

19 39_0 402_5%OBR@

RD

1 2

20 39_0 402_5%OBR@

RD

1 2

21 39_0 402_5%OBR@

RD

1 2

22 39_0 402_5%OBR@

RD

1 2

23 39_0 402_5%OBR@

RD

1 2

24 39_0 402_5%OBR@

RD

1 2

25 39_0 402_5%OBR@

RD

1 2

26 39_0 402_5%OBR@

RD

1 2

27 39_0 402_5%DDP@

RD

1 2

31 0_02 01_5%SDP@

RD

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD

DD
DD
DD

DD
DD
DD

DD
DD
DD
DD

R_A_BG1_R

DD

DRAM DOWN DECOUPLING

C

C

C

C
D
14

1

1

0
.
22U_0402_6.3V6K OBR@

2

2

1

2

C

C
D
15

1

0
.
22U_0402_6.3V6K OBR@

2

+0

10U 6.3V M X5R 0402

C
D
47

OBR@

C

C
D
16

1

0
.
22U_0402_6.3V6K OBR@

2

.6VS

C

D

D

D

D

D

D

17

19

18

20

21

22

1

1

1

1

1

0
.
22U_0402_6.3V6K OBR@

1

0

0

0

0

0

.

.

.

.

.

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

2

2

2

2

2

2

.6V_DDRA_VREFCA

+0

.5V

+2

1U_0201_6.3V6M

1U_0201_6.3V6M

C

C

D

D

1

1

49

48

OBR@

OBR@

2

2

R_A_MA4
R_A_MA5
R_A_MA6
R_A_MA7
R_A_MA8
R_A_MA9
R_A_MA10
R_A_MA11
R_A_MA12
R_A_MA13

R_A_WE#
R_A_CAS#
R_A_RAS#

R_A_ODT0
R_A_CS0#
R_A_CKE0

R_A_ACT#
R_A_BA0
R_A_BA1
R_A_BG0

1 2

30 0_02 01_5%DDP@

RD

C

C

C

C

C

D

D

D

D

D

24

25

26

27

23

1

1

1

1

1

0

0

0

0

0

.

.

.

.

.

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

2

2

2

2

2

1 2

34 0.1U_0201_1 0V6K OBR@

CD

1 2

36 0.1U_0201_1 0V6K OBR@

CD

1 2

38 0.1U_0201_1 0V6K OBR@

CD

1 2

40 0.1U_0201_1 0V6K OBR@

CD

.5V

+2

10U 6.3V M X5R 0402

C
D

1

1

50

@

2

2

Closed to UD4

R_A_BG1 <5>

DD

.6VS

+0

C

C

C

C

C

D

D

D

D

D

30

31

32

28

29

1

1

1

1

1

0

0

0

0

0

.

.

.

.

.

22U_0402_6.3V6K @

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K OBR@

22U_0402_6.3V6K @

2

2

2

2

2

.2V

+1

1U_0201_6.3V6M

1U_0201_6.3V6M

10U 6.3V M X5R 0402

C

C

C

D

D

D

1

1

52

51

53

@

OBR@

OBR@

2

2

curity Classification Compal Secret Data

curity Classification Compal Secret Data

curity Classification Compal Secret Data

Se

Se

Se

ssu

ssu

ssu

ed Date

ed Date

ed Date

I

I

I

HI

HI

HI

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

20

20

20

2

eciphered Date

eciphered Date

eciphered Date

D

D

D

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

Co

tle

tle

tle

Ti

Ti

Ti

DDR4_CHA Onboard

DDR4_CHA Onboard

DDR4_CHA Onboard

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

-H131P

-H131P

-H131P

L

L

L

Date: Sheet

Date: Sheet

Date: Sheet

1

f

f

f

12 46Monday, November 05, 2018

12 46Monday, November 05, 2018

12 46Monday, November 05, 2018

o

o

o

.

.

.

4

4

4

0

0

0

A

B

C

D

E

DDR4 - SO-DIMM (MEMORY CHANNEL B)

DDR_B_DQ[0..63]

DDR_B_DM[0..7]

DDR_B_MA[0..13]

out Note:

Lay
Place near JDIMM1.257,259

5V

+2.

CD7

10U 6.3V M X5R 0402

1

1

0

@

2

2

CD6

1U_0201_6.3V6M

1

JDIMM1A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1

109

CKE

110

CKE

49

1

S0#

57

1

S1#

162

S2#

165

S3#

155

ODT

161

ODT

15

1

BG0

13

1

BG1

50

1

BA0

45

1

BA1

4

14

A0

3

13

A1

2

13

A2

1

13

A3

8

12

A4

6

12

A5

7

12

A6

2

12

A7

5

12

A8

1

12

A9

146

A10

20

1

A11

19

1

A12

58

1

A13

151

A14

156

A15

152

A16

114

ACT

143

PAR

116

ALE

134

EVE

108

RES

54

2

SDA

53

2

SCL

66

1

SA2

60

2

SA1

56

2

SA0

92

CB0

91

CB1

101

CB2

105

CB3

88

CB4

87

CB5

100

CB6

104

CB7

97

DQS

95

DQS

12

DM0

33

DM1

54

DM2

75

DM3

178

DM4

199

DM5

220

DM6

241

DM7

96

DM8

LOTES_ADDR0205-P001A02~D

SP07001HW0L

ME@

CD6

1U_0201_6.3V6M

12

12

2

#(C)

0
1

/C0
/C1

0
1

_AP

_WE#
_CAS#
_RAS#

#

ITY
RT#
NT#
ET#

_NC
_NC
_NC
_NC
_NC
_NC
_NC
_NC
8(T)
8#(C)

#/DBI0#
#/DBI1#
#/DBI2#
#/DBI3#
#/DBI4#
#/DBI5#
#/DBI6#
#/DBI7#
#/DBI8#

1U_0201_6.3V6M

REVERS E

CD6

3

8

DQ0

7

DQ1

20

DQ2

2

DQ3

4

DQ4

3

DQ5

1

DQ6

1

DQ7

13

0(T)

DQS

11

0#(C)

DQS

2

DQ8

2

DQ9

41

0

DQ1

42

1

DQ1

24

2

DQ1

25

3

DQ1

38

4

DQ1

37

5

DQ1

34

1(T)

DQS

32

1#(C)

DQS

50

6

DQ1

49

7

DQ1

62

8

DQ1

63

9

DQ1

46

0

DQ2

45

1

DQ2

58

2

DQ2

59

3

DQ2

55

2(T)

DQS

53

2#(C)

DQS

70

4

DQ2

71

5

DQ2

83

6

DQ2

84

7

DQ2

66

8

DQ2

67

9

DQ2

79

0

DQ3

80

1

DQ3

76

3(T)

DQS

74

3#(C)

DQS

174

2

DQ3

173

3

DQ3

187

4

DQ3

186

5

DQ3

170

6

DQ3

169

7

DQ3

183

8

DQ3

182

9

DQ3

179

4(T)

DQS

177

4#(C)

DQS

195

0

DQ4

194

1

DQ4

207

2

DQ4

208

3

DQ4

191

4

DQ4

190

5

DQ4

203

6

DQ4

204

7

DQ4

200

5(T)

DQS

198

5#(C)

DQS

216

8

DQ4

215

9

DQ4

228

0

DQ5

229

1

DQ5

211

2

DQ5

212

3

DQ5

224

4

DQ5

225

5

DQ5

221

6(T)

DQS

219

6#(C)

DQS

237

6

DQ5

236

7

DQ5

249

8

DQ5

250

9

DQ5

232

0

DQ6

233

1

DQ6

245

2

DQ6

246

3

DQ6

242

7(T)

DQS

240

7#(C)

DQS

CD6

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

4

DDR_B_CLK0<5>
DDR_B_CLK0#<5>
DDR_B_CLK1<5>

_B_CLK1#<5>

DDR

_B_CKE0<5>

DDR

_B_CKE1<5>

1 1

2 2

_B_RST#

DDR

3 3

2V

+1.

1 2

9

CD6
100P_0402_50V8J

CD5

10U 6.3V M X5R 0402

1

4

2

ESD@

CD5

10U 6.3V M X5R 0402

1

5

NO_OBR@

2

DDR

_B_CS0#< 5>

DDR

_B_CS1#< 5>

DDR

_B_ODT0<5>

DDR

_B_ODT1<5>

DDR

_B_BG0<5>

DDR

_B_BG1<5>

DDR

_B_BA0<5>

DDR

_B_BA1<5>

DDR

_B_WE#<5>

DDR

_B_CAS#<5>

DDR

_B_RAS#<5>

DDR

_B_ACT#<5>

DDR

_B_PAR<5>

DDR

_B_ALERT#<5>

DDR

_B_EVENT#<5>

DDR

_B_RST#<5>

DDR

_2_SDA<8>

I2C

_2_SCL<8>

I2C

+3V

D

ES

CD5

CD5

10U 6.3V M X5R 0402

1

6

2

CD5

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1

1

7

8

NO_OBR@

2

2

DDR_B_CLK0
DDR_B_CLK0#
DDR_B_CLK1
DDR_B_CLK1#

_B_CKE0

DDR

_B_CKE1

DDR

_B_CS0#

DDR

_B_CS1#

DDR

_B_ODT0

DDR

_B_ODT1

DDR

_B_BG0

DDR

_B_BG1

DDR

_B_BA0

DDR

_B_BA1

DDR

_B_MA0

DDR

_B_MA1

DDR

_B_MA2

DDR

_B_MA3

DDR

_B_MA4

DDR

_B_MA5

DDR

_B_MA6

DDR

_B_MA7

DDR

_B_MA8

DDR

_B_MA9

DDR

_B_MA10

DDR

_B_MA11

DDR

_B_MA12

DDR

_B_MA13

DDR

_B_WE#

DDR

_B_CAS#

DDR

_B_RAS#

DDR

_B_ACT#

DDR

_B_PAR

DDR

_B_ALERT#

DDR

_B_EVENT#

DDR

_B_RST#

DDR

S

_B_DM0

DDR

_B_DM1

DDR

_B_DM2

DDR

_B_DM3

DDR

_B_DM4

DDR

_B_DM5

DDR

_B_DM6

DDR

_B_DM7

DDR

CD5

10U 6.3V M X5R 0402

CD6

1U_0201_6.3V6M

1

2

12

12

9

0

NO_OBR@

DDR_B_DQ1
DDR_B_DQ4
DDR_B_DQ3
DDR_B_DQ6

1

6
7

8
9

CD6

5

NO_OBR@

_B_DQ0

DDR

_B_DQ5

DDR

_B_DQ7

DDR

_B_DQ2

DDR

_B_DQS0

DDR

_B_DQS0#

DDR

_B_DQ12

DDR

_B_DQ13

DDR

_B_DQ10

DDR

_B_DQ14

DDR

_B_DQ8

DDR

_B_DQ9

DDR

_B_DQ11

DDR

_B_DQ15

DDR

_B_DQS1

DDR

_B_DQS1#

DDR

_B_DQ21

DDR

_B_DQ16

DDR

_B_DQ23

DDR

_B_DQ19

DDR

_B_DQ17

DDR

_B_DQ20

DDR

_B_DQ22

DDR

_B_DQ18

DDR

_B_DQS2

DDR

_B_DQS2#

DDR

_B_DQ25

DDR

_B_DQ28

DDR

_B_DQ26

DDR

_B_DQ27

DDR

_B_DQ24

DDR

_B_DQ29

DDR

_B_DQ30

DDR

_B_DQ31

DDR

_B_DQS3

DDR

_B_DQS3#

DDR

_B_DQ32

DDR

_B_DQ33

DDR

_B_DQ34

DDR

_B_DQ35

DDR

_B_DQ37

DDR

_B_DQ36

DDR

_B_DQ38

DDR

_B_DQ39

DDR

_B_DQS4

DDR

_B_DQS4#

DDR

_B_DQ40

DDR

_B_DQ41

DDR

_B_DQ42

DDR

_B_DQ43

DDR

_B_DQ44

DDR

_B_DQ45

DDR

_B_DQ46

DDR

_B_DQ47

DDR

_B_DQS5

DDR

_B_DQS5#

DDR

_B_DQ48

DDR

_B_DQ53

DDR

_B_DQ50

DDR

_B_DQ51

DDR

_B_DQ52

DDR

_B_DQ49

DDR

_B_DQ54

DDR

_B_DQ55

DDR

_B_DQS6

DDR

_B_DQS6#

DDR

_B_DQ56

DDR

_B_DQ57

DDR

_B_DQ58

DDR

_B_DQ59

DDR

_B_DQ60

DDR

_B_DQ61

DDR

_B_DQ62

DDR

_B_DQ63

DDR

_B_DQS7

DDR

_B_DQS7#

DDR

+1.

CD6

CD6

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

7

6

NO_OBR@

NO_OBR@

2V

1

+

8

CD6
330U_D3_2.5VY_R6M

@

2

_B_DQS0 <5>

DDR

_B_DQS0# <5>

DDR

_B_DQS1 <5>

DDR

_B_DQS1# <5>

DDR

_B_DQS2 <5>

DDR

_B_DQS2# <5>

DDR

_B_DQS3 <5>

DDR

_B_DQS3# <5>

DDR

_B_DQS4 <5>

DDR

_B_DQS4# <5>

DDR

_B_DQS5 <5>

DDR

_B_DQS5# <5>

DDR

_B_DQS6 <5>

DDR

_B_DQS6# <5>

DDR

_B_DQS7 <5>

DDR

_B_DQS7# <5>

DDR

10U 6.3V M X5R 0402

CD7

1

DDR_B_DQ[0..63] <5>

DDR_B_DM[0..7] <5>

DDR_B_MA[0..13] <5>

+VR

CD7

1U_0201_6.3V6M

12

2

@

EFB_CA

1

2

1

2

S

+3V

CD8

1000P_0402_50V7K

1

+0.

CD7

0.1U_0201_10V6K

3

2V

+1.

Layout Note:
Place near JDIMM1.258

6VS

CD7

1U_0201_6.3V6M

1

4

2

MM1B

JDI

111

1

VDD

112

2

VDD

117

3

VDD

118

4

VDD

123

5

VDD

124

6

VDD

129

7

VDD

130

8

VDD

135

9

VDD

136

10

VDD

255

SPD

VDD

164

FCA

VRE

1

1

VSS

2

2

VSS

5

3

VSS

6

4

VSS

9

5

VSS

10

6

VSS

14

7

VSS

15

8

VSS

18

9

VSS

19

10

VSS

22

11

VSS

23

12

VSS

26

13

VSS

27

14

VSS

30

15

VSS

31

16

VSS

35

17

VSS

36

18

VSS

39

19

VSS

40

20

VSS

43

21

VSS

44

22

VSS

47

23

VSS

48

24

VSS

51

25

VSS

52

26

VSS

56

27

VSS

57

28

VSS

60

29

VSS

61

30

VSS

64

31

VSS

65

32

VSS

68

33

VSS

69

34

VSS

72

35

VSS

73

36

VSS

77

37

VSS

78

38

VSS

81

39

VSS

82

40

VSS

85

41

VSS

86

42

VSS

89

43

VSS

90

44

VSS

93

45

VSS

94

46

VSS

98

47

VSS

262

1

GND

LOTES_ADDR0205-P001A02~D

SP07001HW0L

ME@

CD7

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1

1

5

2

2

ERSE

REV

C
D
7
6

@

2V

+1.

141

11

VDD

142

12

VDD

147

13

VDD

148

14

VDD

153

15

VDD

154

16

VDD

159

17

VDD

160

18

VDD

163

19

VDD

58

2

VTT

257

1

VPP

259

2

VPP

99

48

VSS

102

49

VSS

103

50

VSS

106

51

VSS

107

52

VSS

167

53

VSS

168

54

VSS

171

55

VSS

172

56

VSS

175

57

VSS

176

58

VSS

180

59

VSS

181

60

VSS

184

61

VSS

185

62

VSS

188

63

VSS

189

64

VSS

192

65

VSS

193

66

VSS

196

67

VSS

197

68

VSS

201

69

VSS

202

70

VSS

205

71

VSS

206

72

VSS

209

73

VSS

210

74

VSS

213

75

VSS

214

76

VSS

217

77

VSS

218

78

VSS

222

79

VSS

223

80

VSS

226

81

VSS

227

82

VSS

230

83

VSS

231

84

VSS

234

85

VSS

235

86

VSS

238

87

VSS

239

88

VSS

243

89

VSS

244

90

VSS

247

91

VSS

248

92

VSS

251

93

VSS

252

94

VSS

261

2

GND

S

+3V

2

1

6VS

+0.

5V

+2.

2V

+1.

DIMM Side

EFB_CA

+VR

EFB_CA

C

C

2.2U_0402_6.3V6M

0.1U_0201_10V6K
D

D

7

7

8

7

2

1

+VR

C

C

0.1U_0201_10V6K

0.1U_0201_10V6K

D

D8
7
9

0

2

2

@

1

1

RD4
1K_0402_1%

1 2

RD4
1K_0402_1%

1 2

2

3

4 4

urity Classification

urity Classification

urity Classification

Sec

Sec

Sec

ued Date

ued Date

ued Date

Iss

Iss

Iss

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

8/11/05 2019/11/05

8/11/05 2019/11/05

8/11/05 2019/11/05

201

201

201

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Tit

Size

Size

Size

ument Number Re v

ument Number Re v

ument Number Re v

Doc

Doc

Doc

C

C

C

Date: Sheet

onday, November 05, 2018

Date: Sheet

onday, November 05, 2018

Date: Sheet

onday, November 05, 2018

DDR

DDR

DDR

LA-

LA-

LA-

4 SO-DIMM

4 SO-DIMM

4 SO-DIMM

H131P

H131P

H131P

E

pal Electronics, Inc.

pal Electronics, Inc.

pal Electronics, Inc.

Com

Com

Com

le

le

le

Tit

Tit

3 4

3 4

3 4

o

1

o

1

o

1

0.4

0.4

0.4

f

f

f

6M

6M

6M

5

4

3

2

1

CAMERA POWER CIRCUIT

+3VS

D D

1 2

R3 0

_0603_5%@

W=20mils

.1U_0201_10V6K

0

+3VS_CMOS

1

2

1

C6

0U_0603_6.3V6M

1

@

2

C5

DISPLAY OFF

VS

+3

U2

74AHC1G08G-AL5-R_SOT 353-5

U

B

A

5

P

G

3

SA00000OH00

@

4

Y

_0402_5%@

SPOFF#

DI

R7

00K_0402_5%

1

1 2

C C

om PCH

Fr

From EC

BKL<7,28>

EN

OFF#<28>

BK

65

R2
100K_0402_5%

@

1 2

2

1

1 2

R1 0

TOUCH SCREEN POWER CIRCUIT

VS

B B

+3

W=20mils

64 0_0603_5%@

R2

1 2

C2

0.1U_0201_10V6K

30

VS_TS

+3

1

2

1

31

C2
10U_0603_6.3V6M

@

2

ESD COMPONENTS

6

B20_N3

US

A A

IC_CLK

DM

5

DT

3

O2

I/

2

GN

1

O1

I/

L30ESDL5V0C6-4_SOT23 -6

SC300004W00

@ESD@

O4

I/

D

VD

O3

I/

6

5

D

4

DM

US

IC_DAT

B20_P3

curity Classification

curity Classification

curity Classification

Se

Se

Se

ed Date

ed Date

ed Date

Issu

Issu

Issu

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI

THI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

LCD POWER SWITCH

+3VS +LCDVDD_CONN

W=60mils

12

C4

U_0201_6.3V6M

1

VDD<7>

EN

EDP CONNECTOR

B+ +L

1 2

R9 0_

eDP

Touch Screen

Camera

Microphone

18/11/05 2019/11/05

18/11/05 2019/11/05

18/11/05 2019/11/05

20

20

20

3

ED
ED

ED
ED

ED
ED

HU
HU

TS
US
US

DM
DM

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

0805_5%@

P_AUXN<7>
P_AUXP<7>

P_TXP0<7 >
P_TXN0<7>

P_TXP1<7 >
P_TXN1<7>

B_USB20_N1<22>
B_USB20_P1<22>

_DISABLE#<28>
B20_N3<9>
B20_P3<9>

IC_CLK<21>
IC_DAT<21>

Deciphered Date

Deciphered Date

Deciphered Date

U5

5

IN

4

EN

M5203AJ-20 SOT23 5P

E

SA00008R900

EDVDD

1

C7

.7U_0805_25V6-K

4

@

2

VTPWM<7>

IN

P_HPD<7>

ED

1 2
1 2

1 2
1 2

1 2
1 2

.1U_0201_10V K X5R
.1U_0201_10V K X5R

VS_TS

+3

VS_CMOS

+3

VS

+3

2

C8 0
C9 0

0 0.1U_0201_10V K X5R

C1

1 0.1U_0201_10V K X5R

C1

2 0.1U_0201_10V K X5R

C1

3 0.1U_0201_10V K X5R

C1

1

CDVDD

+L

T

OU

2

D

GN

3

OC

SPOFF#

DI

P_HPD

ED

P_AUXN_C

ED

P_AUXP_C

ED

P_TXP0_C

ED

P_TXN0_C

ED

P_TXP1_C

ED

P_TXN1_C

ED

Ti

Ti

Ti

Size

Size

Size

B

B

B

Date : Sheet

Date : Sheet

Date : Sheet

1 2

R2 0_

CDVDD_CONN

+L

Co

Co

tle

tle

tle

Co

Document Number Re v

Document Number Re v

Document Number Re v

0805_5%@

W=60mils

JEDP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

0

1

10

1

1

11

2

1

12

3

1

13

4

1

14

5

1

15

6

1

16

7

1

17

8

1

18

9

1

19

0

2

20

1

2

21

2

2

22

3

2

23

4

2

24

5

2

25

6

2

26

7

2

27

8

2

28

9

2

29

0

3

30

1

3

31

2

3

32

3

3

33

4

3

34

5

3

35

6

3

36

7

3

37

8

3

38

9

3

39

0

4

40

ILU_CVS3402M1RM-NH

CV

SP01002FV00

ME@

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

P/CAMERA

P/CAMERA

P/CAMERA

eD

eD

eD

-H131P

-H131P

-H131P

LA

LA

LA

1

2

GN
GN
GN
GN
GN

1

C3

.7U_0402_6.3V6M

4

41

D

42

D

43

D

44

D

45

D

o f

14 4

o f

14 4

o f

14 4

4

4

4

0.

0.

0.

6Monday, November 05, 2018

6Monday, November 05, 2018

6Monday, November 05, 2018