A

1 1

B

C

D

E

L

AC

2 2

3 3

Intel BayTrail M-Processor with DDRIIIL + NV (N15V-GM/N15S-GT) GPU

CFC Confidential

LU9 M/B Schematics Document

013-12-22

2

REV:0.2

4 4

itle

T

ecurity Classification

S

I

ssued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2

013/08/08

C Future Center Secret Data

L

D

eciphered Date

2013/08/05

D

T

C

over Page

ize Document Number Rev

S

C

ustom

M

onday, December 23, 2013

Date: Sheet

onday, December 23, 2013

ACLU9

E

o

f

1 59

f

1 59

f

1 59

0

.2

A

CIe Port5

P

ACLU9

LCFC confid

ential

N G

P

File Name :

V (N15V-GM/N15S-GT) B2B-64 Package

age 18~28

VRAM 256/128*16

DR3L*8 4GB/2GB/1GB

1 1

to USB Port

2 2

3 3

D

Page 19~28

J45 Conn.

R

Page 38

eDP Conn

Page 33

DMI Conn.

H

age 34

P

V

Page 36

nt. Camera

I

SB2.0 Port2

U

Int. MIC Conn.

RTL8111GUL (1G) RTL8106EUL (10M/100M)

Page 37

dec

Co

Conexant CX20752

Page 43

GA Conn.

Page 42

AN Realtek

L

ATA Port0

S

ATA Port1

S

PCIe Port1

SP

K Conn.

Page 43

B

P

CI-Express

x Gen2

2

H

DMI

RT

C

DP x2 Lane

e

SATA Gen2SATA HDD

SATA Gen1SATA ODD

PCIe 1x

HD Audio

Page 4~12

Ba

ytrail M (4.5W)

BGA-1170

25mm*27mm

C

M

emory BUS (DDR3L)

Dual Channel

1

.35V DDR3L 1333 MT/s

SB 3.0 1x

U

SB 2.0 1x

U

SB 2.0 1x

U

USB 2.0 1x

SB 2.0 1x

U

PCIe 1x

S

PI BUS

SB Left 3.0 Conn

U

SB 3.0 Port0

U

SB 2.0 Port0

U

SB Left 2.0 Conn

U

SB 2.0 Port3

to Camera

SB Hub

U

SB 2.0 Port1

U

PI ROM

S

MB

8

Page 07

P

D

DR3L-SO-DIMM

D

Page 41

age 41

P

USB2.0 1x

U

SB2.0 1x

U

SB2.0 1x

USB2.0 1x

age 16

UP TO 8G

U

Ca RTS5170

NGFF Card WLAN&BT

Page 40

ge 14

Pa

SB Right

USB2.0 Hub Port1

rdreader Realtek

U

SB2.0 Hub Port3

PCIe Port0

USB2.0 Hub Port4

E

/MMC Conn.

SD

USB Board

ouch Screen

T reserved

USB 2.0 Port2

b-board ( for 14")

Su

POWER BOARD

USB Board

Page 33

EC ITE IT8586E-LQFP

Page 44

HP&Mic Combo Conn.

Su

b-board ( for 15")

POWER BOARD

SB Board

U

4 4

Touch Pad Int.KBD

Page 45 Page 45

Thermal Sensor NCT7718W

Page 39

SB Board

U

OD

D Board

itle

T

ecurity Classification

S

ssued Date

I

TH

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2

013/08/08

L

C Future Center Secret Data

D

eciphered Date

D

2013/08/05

T

lock Diagram

B

S

ize Document Number Rev

ize Document Number Rev C

C

ustom

onday, December 23, 2013

M

Date: Sheet

ACLU9

E

o

f

2 59

f

2 59

f

2 59

0

.2

oltage Rails

V

A

,

X --> Means OFF )( O --> Means ON

B

C

D

E

+5VS

P

ower Plane

3VALW_SOC

B

+

+3VALW

3VL

+

1 1

S

tate

0

S

3

S

5 S4/AC Only

S

S5 S4

+5VALW

O

O O

+

1.0VALW

+ +1.8VALW

O O O

O X X

+

1.35V

O O

OO O X O

X

XX

+3VS +1.5VS +1.05VS +0.68VS CPU_CORE GFX_CORE

X

TATE

S

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

U

SB Port Table

Battery only

S5 S4 AC & Battery

2 2

XX

X

EHCI1

don't exist

STATE SLP_S3#SLP_S1#

Full ON

1(Power On Suspend)

S

S3 (Suspend to RAM)

S4 (Suspend to Disk) ON

S5 (Soft OFF)

SIGNAL

SLP_S4# +VS+V

HIGHHIGHHIGH

LOW

HIGH HIGH

LOW

LOW HIGH

LOW

LOW LOW

LOW OFF

+

VALW

ON

VALW_PCH

+

O

NONON

ONONON

ON

OFF

lock

C

ONON

ON

LOW

OFF OFF

OFF

USB HUB

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

USB 3.0USB 2.0 Port

XHCI

1

HIGH HIGH HIGH HIGH

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

LOW

LOW LOW LOW LOW

3 External USB Port

0 1

2 3

1 2

3 4

SB Port (Left Side)

U U

SB Port (Right Side)

U

SB Port (Left Side)

U

SB HUB

amera

C Cardreader B

T(WLAN)

TOUCH PANEL

ONONON ON

ON

OFF

ON

OFF

OM Structure Table

B

AOAC@ OPT@

UMA@ 14@ 15@

100M@

N15SGT@

N15VGM@

GIGA@

GC6@

TS@

RANKA@

RANKB@

ME@

CD@

@

ON

OFF

re

LOW

OFF

BTO ItemBOM Structu

AOAC support part

PU Part

G U

MA SKU ID part

For 14" part

F

or 15" part

00M LAN part

1 N

15SGT Part 15GSM Part

N

GIGA LAN Part

PU GC6 Part

G Touch Screen part

PU VRAM RANKA PART

G

PU VRAM RANKB PART

G C

onnector OST DOWN

C

ot stuff

N

S

MBUS Control Table

WLAN

GA BATT SODIMM

0

001 011X b eed to update

n

A

V

+

3VGS

X

V

X

3 3

EC_SMB_DA1

E

C_SMB_CK2

EC_SMB_DA2

P

CH_SMB_CLK

PCH_SMB_DATA

E

4 4

SOURCE

IT8586EEC_SMB_CK1

+

3VALW

IT8586E

+3VS

PCH

3VALW_PCH

+

C SM Bus1 address

D

evice

mart Battery

S C

harger

IT8586E

V

+

3VALW

V

X

+3VS

X X X

C SM Bus2 address

E

hermal Sensor EMC1403-2

T

X

V V

+3VS +3VS

D

evice

V

GA CH

P

WiMAX

X

V

A

ddress

1

001_100xb x9E

0 0

x96

B

Thermal Sensor

X XV

V

+3VS

+

3VALW_PCH

PCH

TP

harger

c

Module

XX

V

X

CH SM Bus address

P

D

evice Address

DR DIMMA

D

lan

W TP

X

1

001 000Xb

svd

R need to update

ecurity Classification

S

ssued Date

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

CIE PORT LIST

P

Port Device

1

D

iscrete GPU

2

D

iscrete GPU

3 4 5

LAN

W

AN

L

6 7 8

L

013/08/08

2

L

C Future Center Secret Data

eciphered Date

D

2013/08/05

H4T@ M4T@ S4T@@

H

ynix VRAM Part Micron VRAM Part Samsung VRAM Part

itle

T

N

otes List

ize Document Number Rev

S

C

ustom

M

onday, December 23, 2013

Date: Sheet

onday, December 23, 2013

ACLU9

E

o

f

3 59

f

3 59

f

3 59

0

.2

5

DI0_RCOMP_N

D

DI0_RCOMP_P

D

G

H H H H H H

H H

PIO_NC13

DMI_TX2+{34}

H

DMI_TX2-{34}

HDMI D2 HDMI D1 HDMI D0

DMI CLK

H

D D

C C

c

hange dual mos to one mos

B B

D

12

C1

R

R 402_0402_1%

402_0402_1%

D

DI0_RCOMP_N

DI0_RCOMP_P

PIO_NC13{12}

G

H

DMI_TX1+{34}

H

DMI_TX1-{34}

H

DMI_TX0+{34}

H

DMI_TX0-{34}

H

DMI_CLK+{34}

H

DMI_CLK-{34}

H

DMI_HPD{34}

H

DPB_DATA{34}

D

DPB_CLK{34}

D

DMI_TX2+ DMI_TX2DMI_TX1+ DMI_TX1DMI_TX0+ DMI_TX0-

DMI_CLK+ DMI_CLK-

CH_LCD_VDDEN_ Q

P

CH_BKLT_EN_Q

P

4

UC1C

AV3

DI0_TXP_0

D

V1P0Sx

AV2

DI0_TXN_0

D

AT2

V1P0Sx

DI0_TXP_1

D

V1P0Sx

AT3

DI0_TXN_1

D

V1P0Sx

AR3

DI0_TXP_2

D

V1P0Sx

AR1

DI0_TXN_2

D

V1P0Sx

AP3

DI0_TXP_3

D

AP2

V1P0Sx

DI0_TXN_3

D

V1P0Sx

AL3

DI0_AUXP

D

V1P0Sx

AL1

DI0_AUXN

D

V1P0Sx

D27

DI0_HPD

D

V1P8S V1P8S

C26

DI0_DDCDATA

D

C28

B28

C27

B26

K13

A

AK12 AM14 AM13

AM3 AM2

T2

T3 AB3 AB2

Y3

Y2

W3 W1

V2

V3

R3

R1 AD6 AD4 AB9 AB7

Y4

Y6

V4

V6

A29

C29

AB14

B30

C30

V1P8S

DI0_DDCCLK

D

V1P8S

DI0_VDDEN

D

V1P8S V1P8S

DI0_BKLTEN

D

V1P8S

DI0_BKLTCTL

D

V1P8S

DI0_RCOMP

D

V1P0Sx

DI0_RCOMP_P

D

V1P0Sx

ESERVED_AM14

R

ESERVED_AM13

R

SS_AM3

V

SS_AM2

V

ESERVED_T2

R

ESERVED_T3

R

ESERVED_AB3

R

ESERVED_AB2

R

ESERVED_Y3

R

ESERVED_Y2

R

ESERVED_W3

R

ESERVED_W1

R

ESERVED_V2

R

ESERVED_V3

R

ESERVED_R3

R

ESERVED_R1

R

ESERVED_AD6

R

ESERVED_AD4

R

ESERVED_AB9

R

ESERVED_AB7

R

ESERVED_Y4

R

ESERVED_Y6

R

ESERVED_V4

R

ESERVED_V6

R

PIO_S0_NC13

G

PIO_S0_NC14_C29

G

ESERVED_AB14

R

PIO_S0_NC12

G

ESERVED_C30

R

BAY-TRAIL-M-SOC_FCBGA1170

@

RESERVED_VS RESERVED_VSS1

2

G

1

2

G

1

3VALW

+

1.8VALW

+

1 4

2 3

1 6 D

11 S

1 4

2 3

1 6 D

11 S

S0

RESERVED_A2 RESERVED_C29

V1P8S

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

V1P8S V1P8S

RESERVED_VSS2 RESERVED_VSS3

VVGA_GPIO VVGA_GPIO

3VS

+

2 3 D

2 S

4

3VS

+

2 3 D

2 S

4

V1P8S RESERVED_D32 RESERVED_N32 RESERVED_J34 RESERVED_K28 RESERVED_F28 RESERVED_F32 RESERVED_D34 RESERVED_J28 RESERVED_D28 RESERVED_M32 RESERVED_F34

C1B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

C2B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

9

OF 13 REV = 1.15 ?

3

PC24

25

G

C1A

PC25

25

G

C2A

V1P0Sx V1P0Sx V1P0Sx V1P0Sx V1P0Sx V1P0Sx V1P0Sx V1P0Sx

V1P0Sx V1P0Sx

DI1_DDCDATA

D

DI1_DDCCLK

D

DI1_BKLTCTL

D

ESERVED_AH14

R

ESERVED_AH13

R

ESERVED_AF14

R

ESERVED_AF13

R

V GA_DDCDATA

V

ESERVED_T7

R

ESERVED_T9

R

ESERVED_AB13

R

ESERVED_AB12

R

ESERVED_Y12

R

ESERVED_Y13

R

ESERVED_V10

R

ESERVED_V9

R ESERVED_T12

R

ESERVED_T10

R

ESERVED_V14

R

ESERVED_V13

R

ESERVED_T14

R

ESERVED_T13

R

ESERVED_T6

R

ESERVED_T4

R ESERVED_P14

R

ESERVED_K34

R

PIO_S0_NC26

G

PIO_S0_NC25

G

PIO_S0_NC24

G

PIO_S0_NC23

G

PIO_S0_NC22

G

PIO_S0_NC21

G

PIO_S0_NC20

G

PIO_S0_NC18

G

PIO_S0_NC17

G

PIO_S0_NC16

G

PIO_S0_NC15

G

DI1_TXP_0

D

DI1_TXN_0

D

DI1_TXP_1

D

DI1_TXN_1

D

DI1_TXP_2

D

DI1_TXN_2

D

DI1_TXP_3

D

DI1_TXN_3

D

DI1_AUXP

D

DI1_AUXN

D

DI1_HPD

D

DI1_VDDEN

DI1_BKLTEN

SS_AH3

V

SS_AH2

V

GA_RED

V

GA_BLUE

V GA_GREEN

V

GA_IREF

V

GA_IRTN

V

GA_HSYNC

V

GA_VSYNC

V GA_DDCCLK

3

AG3 AG1 AF3 AF2 AD3 AD2 AC3 AC1

AK3 AK2

K30 P30

G30 N30

J30 M30

AH14 AH13 AF14 AF13 AH3 AH2

BA3 AY2 BA1 AW1 AY3

BD2 BF2

BC1 BC2

T7 T9 AB13 AB12 Y12 Y13 V10 V9 T12 T10 V14 V13 T14 T13 T6 T4 P14

K34 D32 N32 J34 K28 F28 F32 D34 J28 D28 M32 F34

CH_ENVDD {33}

P

CH_ENBKL {33}

P

PU_EDP_TX0+

C

PU_EDP_TX0-

C

PU_EDP_TX1+

C

PU_EDP_TX1-

C

PU_EDP_AUX

C

PU_EDP_AUX#

C

DP_HPD

E DI1_DDCDATA

D

CH_LCD_VDDEN_ Q

P

CH_BKLT_EN_Q

P

CH_BKLT_CTRL_Q

P

RT_R

C

RT_B

C

RT_G

C

RT_IREF

C

GA_HS

V

GA_VS

V

GA_DDC_CLK

V

GA_DDC_DAT

V

XDP

CH_BKLT_CTRL_Q

P

1

R

10K_0402_5%

2

P11@TP11@

T

+

C972

G

1

PU_EDP_TX0+ {33}

C

PU_EDP_TX0- {33}

C

PU_EDP_TX1+ {33}

C

PU_EDP_TX1- {33}

C

PU_EDP_AUX {33}

C

PU_EDP_AUX# {33}

C

DI1_DDCDATA {12}

D

V V

3VALW

12

R

C973

10K_0402_5%

1 6

Q

C198A

D

PJT138K_SOT363-6

11 S

RT_R {36}

C

RT_B {36}

C

RT_G {36}

C

GA_HS {36}

V

GA_VS {36}

V GA_DDC_CLK {36}

GA_DDC_DAT {3 6}

3VS

+

2 3 D

25

G

2 S

4

2

E

DP

C198B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

Port

DDI PROCESSOR Pin Names

Port 0

DDI0_TXP_0 DDI0_TXN_0 DDI0_TXP_1 DDI0_TXN_1 DDI0_TXP_2 DDI0_TXN_2 DDI0_TXP_3 DDI0_TXP_3 DDI0_HPD DDI0_DDCDATA DDI0_DDCCLK

Port

DDI PROCESSOR Pin Names

Port 1

DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_AUXP DDI1_AUXN DDI1_HPD

GA_DDC_CLK

V

GA_DDC_DAT

V

RT_R

C C C

C

n

4602 change from 10K to 1K,

R as Vienna

+

DP_HPD

E

C3

Q

604

0

R

RT_B

R

RT_G

R

RT_IREF

R

eed to change 357 1%

1.8VS

4602

R

R 1K_0402_1%

1K_0402_1%

1 2

13

D

2

G

S

2N7002KW_SOT32 3-3

EDP_HPD

CH_EDP_PWM {33 }

P

1

HDMI* Mapping HDMI_TX2+ HDMI_TX2HDMI_TX1+ HDMI_TX1HDMI_TX0+ HDMI_TX0HDMI_CLK+ HDMI_CLKHDMI_HPD DDPB_DAT DDPB_CLK

EDP* Mapping CPU_EDP_TX0+ CPU_EDP_TX0CPU_EDP_TX1+ CPU_EDP_TX1CPU_EDP_AUX CPU_EDP_AUX# EDP_HPD

PC16

R

23 14

2.2K_0404_4P2R_5%

12

C5 150_0402_1%

12

C6 150_0402_1%

12

C7 150_0402_1%

1 2

C4 357_0402_1%

PU_EDP_HPD {33}

C

12

4603

R

R 100K_0402_5%

100K_0402_5%

3VS

+

A A

itle

T

S

ecurity Classification

I

ssued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

013/03/2 6

C Future Center Secret Data

L

eciphered Date

D

2013/02/01

2

T

OC (DDI,EDP)

S

Size Document Number R ev

ize Document Number R ev

S

C

ustom

Date: Sheetof

ACLU9

onday, December 23, 2013

M

4 59

1

0

.2

5

UC1A

K45

D

DRA_MA0 DRA_MA1

D DDRA_MA2 D

DRA_MA3 DRA_MA4

12

CLK_DRAM_TERMN_0ICLK_DRAM_TERMN_0

I

12

I

CLK_DRAM_TERMN_1ICLK_DRAM_TERMN_1

DR_PWROK

D

DR_CORE_PWROK

D

S

M_RCOMP_0

S

M_RCOMP_1

S

M_RCOMP_2

D

DRA_MA5

D D

DRA_MA6 DRA_MA7

D DDRA_MA8 D

DRA_MA9 DRA_MA10

D

DRA_MA11

D D

DRA_MA12

D

DRA_MA13

D

DRA_MA14

D

DRA_MA15

DDRA_DM0 D

DRA_DM1 DRA_DM3

D

DRA_DM2

D D

DRA_DM4 DRA_DM6

D DDRA_DM7 D

DRA_DM5

DRAM_VREF

D D

Swap Group 2 to Group 3

Swap Group to 6\7\5

DDRA_RAS#{14} D

DRA_CAS#{14}

D

DRA_WE#{14}

DDRA_BS0#{14} D

DRA_BS1#{14}

DDRA_BS2#{14}

DRA_CS0#{14}

D D

DRA_CS1#{14}

D

DRA_CKE0{14}

C C

B B

DDRA_CKE1{14}

DRA_ODT0{14}

D D

DRA_ODT1{14}

DRA_CLK0{14}

D

DRA_CLK0#{14}

D

DRA_CLK1{14}

D

DRA_CLK1#{14}

D

DRA_DRAMRST#{14}

D

R

C19100K_0402_1%RC19100K_0402_1%

R

C20100K_0402_1%RC20100K_0402_1%

RAM0_MA_00

D

H47

RAM0_MA_11

D

L41

RAM0_MA_22

D

H44

RAM0_MA_33

D

H50

RAM0_MA_44

D

G53

RAM0_MA_55

D

H49

RAM0_MA_66

D

D50

RAM0_MA_77

D

G52

RAM0_MA_88

D

E52

RAM0_MA_99

D

K48

RAM0_MA_1010

D

E51

RAM0_MA_1111

D

F47

RAM0_MA_1212

D

J51

RAM0_MA_1313

D

B49

RAM0_MA_1414

D

B50

RAM0_MA_1515

D

G36

RAM0_DM_0 0

D

B36

RAM0_DM_1 1

D

F38

RAM0_DM_2 2

D

B42

RAM0_DM_3 3

D

P51

RAM0_DM_4 4

D

V42

RAM0_DM_5 5

D

Y50

RAM0_DM_6 6

D

Y52

RAM0_DM_7 7

D

45

M

RAM0_RAS

D

44

M

RAM0_CAS

D

51

H

RAM0_WE

D

K47

RAM0_BS_ 00

D

K44

RAM0_BS_ 11

D

D52

RAM0_BS_ 22

D

44

P

RAM0_CS_0

D

45

P

RAM0_CS_2

D

C47

RAM0_CKE_00

D

D48

ESERVED_ D48

R

F44

RAM0_CKE_22

D

E46

ESERVED_ E46

R

T41

RAM0_ODT_0

D

P42

RAM0_ODT_2

D

M50

RAM0_CKP_0

D

M48

D

RAM0_CKN_ 0

P50

RAM0_CKP_2

D

P48

D

RAM0_CKN_ 2

41

P

D

RAM0_DRAMRST

AF44

D

RAM_VREF

AH42

I

CLK_DRAM_ TERMN

AF42

CLK_DRAM_ TERMN_AF42

I

AD42

D

RAM_VDD_S 4_PWROK

AB42

RAM_CORE_ PWROK

D

AD44

RAM_RCOMP_ 00

D

AF45

RAM_RCOMP_ 11

D

AD45

RAM_RCOMP_ 22

D

AF40

ESERVED_ AF40

R

AF41

ESERVED_ AF41

R

AD40

ESERVED_ AD40

R

AD41

R

ESERVED_ AD41

BAY-TRAIL-M-SOC_FCBGA1170

@

ICLK_DRAM_T

ERM_1

EV = 1.15

4

1 OF 13

DDRA_DQ[63:0] {14}

DRA_MA[15:0] {14}

D D

DRA_DQS[7:0] {14}

DRA_DQS#[7:0] {14}

D

DRA_DM[7:0] {14}

D

?R

RAM0_DQ_00

D

RAM0_DQ_11

D

RAM0_DQ_22

D

RAM0_DQ_33

D

RAM0_DQ_44

D

RAM0_DQ_55

D

RAM0_DQ_66

D

RAM0_DQ_77

D

RAM0_DQ_88

D

RAM0_DQ09_C32

D

RAM0_DQ_1010

D

RAM0_DQ_1111

D

RAM0_DQ_1212

D

RAM0_DQ_1313

D

RAM0_DQ_1414

D

RAM0_DQ_1515

D

RAM0_DQ_1616

D

RAM0_DQ_1717

D

RAM0_DQ_1818

D

RAM0_DQ_1919

D

RAM0_DQ_2020

D

RAM0_DQ_2121

D

RAM0_DQ_2222

D

RAM0_DQ_2323

D

RAM0_DQ_2424

D

RAM0_DQ_2525

D

RAM0_DQ_2626

D

RAM0_DQ_2727

D

RAM0_DQ_2828

D

RAM0_DQ_2929

D

RAM0_DQ_3030

D

RAM0_DQ_3131

D

RAM0_DQ_3232

D

RAM0_DQ_3333

D

RAM0_DQ_3434

D

RAM0_DQ_3535

D

RAM0_DQ_3636

D

RAM0_DQ_3737

D

RAM0_DQ_3838

D

RAM0_DQ_3939

D

RAM0_DQ_4040

D

RAM0_DQ_4141

D

RAM0_DQ_4242

D

RAM0_DQ_4343

D

RAM0_DQ_4444

D

RAM0_DQ_4545

D

RAM0_DQ_4646

D

RAM0_DQ_4747

D

RAM0_DQ_4848

D

RAM0_DQ_4949

D D

RAM0_DQ_5050

D

RAM0_DQ_5151 RAM0_DQ_5252

D

RAM0_DQ_5353

D D

RAM0_DQ_5454 RAM0_DQ_5555

D

RAM0_DQ_5656

D

RAM0_DQ_5757

D D

RAM0_DQ_5858 RAM0_DQ_5959

D

RAM0_DQ_6060

D

RAM0_DQ_6161

D D

RAM0_DQ_6262 RAM0_DQ_6363

D

RAM0_DQSP_00

D D

RAM0_DQSN_00 RAM0_DQSP_11

D

RAM0_DQSN_11

D D

RAM0_DQSP_22

D

RAM0_DQSN_22 RAM0_DQSP_33

D

RAM0_DQSN_33

D

RAM0_DQSP_44

D

RAM0_DQSN_44

D

RAM0_DQSP_55

D

RAM0_DQSN_55

D D

RAM0_DQSP_66

D

RAM0_DQSN_66 RAM0_DQSP_77

D

RAM0_DQSN_77

D

M36 J36 P40 M40 P36 N36 K40 K42 B32 C32 C36 A37 C33 A33 C37 B38 F36 G38 F42 J42 G40 C38 G44 D42 A41 C41 A45 B46 C40 B40 B48 B47 K52 K51 T52 T51 L51 L53 R51 R53 T47 T45 Y40 V41 T48 T50 Y42 AB40 V45 V47 AD48 AD50 V48 V50 AB44 Y45 V52 W51 AC53 AC51 W53 Y51 AD52 AD51

J38 K38 C35 B34 D40 F40 B44 C43 N53 M52 T42 T44 Y47 Y48 AB52 AA51

D

DRA_DQ0 DRA_DQ1

D DDRA_DQ2 D

DRA_DQ3 DRA_DQ4

D

DRA_DQ5

D D

DRA_DQ6 DRA_DQ7

D DDRA_DQ8 D

DRA_DQ9 DRA_DQ10

D

DRA_DQ11

D D

DRA_DQ12

D

DRA_DQ13

D

DRA_DQ14

D

DRA_DQ15 DRA_DQ24

D DDRA_DQ25 D

DRA_DQ26 DRA_DQ27

D

DRA_DQ28

D D

DRA_DQ29 DRA_DQ30

D DDRA_DQ31 D

DRA_DQ16 DRA_DQ17

D

DRA_DQ18

D D

DRA_DQ19

D

DRA_DQ20

D

DRA_DQ21

D

DRA_DQ22 DRA_DQ23

D DDRA_DQ32 D

DRA_DQ33 DRA_DQ34

D

DRA_DQ35

D D

DRA_DQ36 DRA_DQ37

D DDRA_DQ38 D

DRA_DQ39 DRA_DQ48

D

DRA_DQ49

D D

DRA_DQ50

D

DRA_DQ51

D

DRA_DQ52

D

DRA_DQ53 DRA_DQ54

D DDRA_DQ55 D

DRA_DQ56 DRA_DQ57

D

DRA_DQ58

D D

DRA_DQ59 DRA_DQ60

D DDRA_DQ61 D

DRA_DQ62 DRA_DQ63

D

DRA_DQ40

D

DRA_DQ41

D

DRA_DQ42

D D

DRA_DQ43

D

DRA_DQ44

D

DRA_DQ45

DDRA_DQ46

DRA_DQ47

D

DRA_DQS0

D

DRA_DQS#0

D D

DRA_DQS1

D

DRA_DQS#1

D

DRA_DQS3 DRA_DQS#3

D

DRA_DQS2

D

DRA_DQS#2

D

DRA_DQS4

D D

DRA_DQS#4

D

DRA_DQS6

D

DRA_DQS#6

DDRA_DQS7

DRA_DQS#7

D

DRA_DQS5

D

DRA_DQS#5

D

3

Group 0

Group 1

Group 3

Swap Group 2 to Group 3

Group 2

Group 4

Group 6

S

wap Group to 6\7\5

Group 7

Group 5

Swap Group 2 to Group 3

Swap Group to 6\7\5

3VALW+1.35V

+

UC1B

AY45

RAM1_MA_00

D

BB47

RAM1_MA_11

D

AW41

RAM1_MA_22

D

BB44

RAM1_MA_33

D

BB50

RAM1_MA_44

D

BC53

RAM1_MA_55

D

BB49

RAM1_MA_66

D

BF50

RAM1_MA_77

D

BC52

RAM1_MA_88

D

BE52

RAM1_MA_99

D

AY48

RAM1_MA_1010

D

BE51

RAM1_MA_1111

D

BD47

RAM1_MA_1212

D

BA51

RAM1_MA_1313

D

BH49

RAM1_MA_1414

D

BH50

RAM1_MA_1515

D

BD38

RAM1_DM_0 0

D

BH36

RAM1_DM_1 1

D

BC36

RAM1_DM_2 2

D

BH42

RAM1_DM_3 3

D

AT51

RAM1_DM_4 4

D

AM42

RAM1_DM_5 5

D

AK50

RAM1_DM_6 6

D

AK52

RAM1_DM_7 7

D

V45

A

RAM1_RAS

D

V44

A

RAM1_CAS

D

B51

B

RAM1_WE

D

AY47

RAM1_BS_ 00

D

AY44

RAM1_BS_ 11

D

BF52

RAM1_BS_ 22

D

T44

A

RAM1_CS_0

D

T45

A

RAM1_CS_2

D

BG47

RAM1_CKE_00

D

BE46

ESERVED_ BE46

R

BD44

RAM1_CKE_22

D

BF48

ESERVED_ BF48

R

AP41

RAM1_ODT_0

D

AT42

RAM1_ODT_2

D

AV50

D

RAM1_CKP_0

AV48

D

RAM1_CKN_ 0

AT50

RAM1_CKP_2

D

AT48

RAM1_CKN_ 2

D

T41

A

RAM1_DRAMRST

D

BAY-TRAIL-M-SOC_FCBGA1170

@

2

BG38

RAM1_DQ_00

D

BC40

RAM1_DQ_11

D

BA42

RAM1_DQ_22

D

BD42

RAM1_DQ_33

D

BC38

RAM1_DQ_44

D

BD36

RAM1_DQ_55

D

BF42

RAM1_DQ_66

D

BC44

RAM1_DQ_77

D

BH32

RAM1_DQ_88

D

BG32

RAM1_DQ_99

D

BG36 BJ37 BG33 BJ33 BG37 BH38 AU36 AT36 AV40 AT40 BA36 AV36 AY42 AY40 BJ41 BG41 BJ45 BH46 BG40 BH40 BH48 BH47 AY52 AY51 AP52 AP51 AW51 AW53 AR51 AR53 AP47 AP45 AK40 AM41 AP48 AP50 AK42 AH40 AM45 AM47 AF48 AF50 AM48 AM50 AH44 AK45 AM52 AL51 AG53 AG51 AL53 AK51 AF52 AF51

BF40 BD40 BG35 BH34 BA38 AY38 BH44 BG43 AU53 AV52 AP42 AP44 AK47 AK48 AH52 AJ51

EV = 1.15

2 OF 13

RAM1_DQ_1010

D

RAM1_DQ_1111

D

RAM1_DQ_1212

D

RAM1_DQ_1313

D

RAM1_DQ_1414

D

RAM1_DQ_1515

D

RAM1_DQ_1616

D

RAM1_DQ_1717

D

RAM1_DQ_1818

D

RAM1_DQ_1919

D

RAM1_DQ_2020

D

RAM1_DQ_2121

D

RAM1_DQ_2222

D

RAM1_DQ_2323

D

RAM1_DQ_2424

D

RAM1_DQ_2525

D

RAM1_DQ_2626

D

RAM1_DQ_2727

D

RAM1_DQ_2828

D

RAM1_DQ_2929

D

RAM1_DQ_3030

D

RAM1_DQ_3131

D

RAM1_DQ_3232

D

RAM1_DQ_3333

D

RAM1_DQ_3434

D

RAM1_DQ_3535

D

RAM1_DQ_3636

D

RAM1_DQ_3737

D

RAM1_DQ_3838

D

RAM1_DQ_3939

D

RAM1_DQ_4040

D

RAM1_DQ_4141

D

RAM1_DQ_4242

D

RAM1_DQ_4343

D

RAM1_DQ_4444

D

RAM1_DQ_4545

D

RAM1_DQ_4646

D

RAM1_DQ_4747

D

RAM1_DQ_4848

D D

RAM1_DQ_4949

D

RAM1_DQ_5050 RAM1_DQ_5151

D

RAM1_DQ_5252

D D

RAM1_DQ_5353 RAM1_DQ_5454

D

RAM1_DQ_5555

D

RAM1_DQ_5656

D D

RAM1_DQ_5757 RAM1_DQ_5858

D

RAM1_DQ_5959

D

RAM1_DQ_6060

D D

RAM1_DQ_6161 RAM1_DQ_6262

D

RAM1_DQ_6363

D

RAM1_DQSP_00 RAM1_DQSN_00

D

RAM1_DQSP_11

D D

RAM1_DQSN_11

D

RAM1_DQSP_22 RAM1_DQSN_22

D

RAM1_DQSP_33

D

RAM1_DQSN_33

D

RAM1_DQSP_44

D

RAM1_DQSN_44

D

RAM1_DQSP_55

D D

RAM1_DQSN_55

D

RAM1_DQSP_66 RAM1_DQSN_66

D

RAM1_DQSP_77

D

RAM1_DQSN_77

D

?R

1

Q

C16A

2

G

3VALW

+

1 4

61

D

S

2013/02/01

2 3

R

PC14

10K_0404_4P2R_5%

C16B

Q

5

G

2N7002KDWH_SOT363-6

1.35V

+

C103

R

1 2

0_0402_5%

34

D

2N7002KDWH_SOT363-6

S

T

itle

S

OC (DDR3L)

ize Document Number Rev

S

C

M

Date: Sheet

DR_CORE_PWROK

D

ACLU9

onday, December 23, 2013

1

C18

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

5 5

o

f

.2

0

9

PC13

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

1 4

+

1.35V

12

C24

R

4.7K_0402_1%

C28

R

1 2

12

RC29

4.7K_0402_1%

A A

4.7K_0402_1%

0_0402_5%

5

RAM_VREF

D

1

C2

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

S

M_RCOMP_2 M_RCOMP_1

S

M_RCOMP_0

S

R

C25

23.2_0402_1%

1 2

D

DR3 Compensation Signal

WIDTH:20MIL SPACING: 25MIL Length: 500Mil

R

1 2

R

C27

162_0402_1%

V

DDQ_PGOOD{44,55}

1

2

R

C26

29.4_0402_1%

1 2

4

2 3

C5B

Q

5

G

61

C5A

Q

D

2

G

2N7002KDWH_SOT363-6

S

C3

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

ecurity Classification

S

ssued Date

I

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAI NS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

3

R

C23

1 2

0_0402_5%

34

D

2N7002KDWH_SOT363-6

S

D

DR_PWROK

013/03/26

2

1

C1

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

YS_PWROK{7,44}

S

C Future Center Secret Data

L

eciphered Date

D

1

2

C19

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

5

SATA_PTX_DRX_P0{42} S

ATA_PTX_DRX_N0{42}

DD

H

S

ATA_PRX_DTX_P0{42} ATA_PRX_DTX_N0{42}

S S

D D

RB USE SATA_GP0

C need check with BIOS

nly GPIO_S0_SC[0..7] can make SCI

o

C C

12

R

C30

402_0402_1%

ATA_RCOMP_DP

S

SATA_RCOMP_DN

ATA_PTX_DRX_P1{42}

SATA_PTX_DRX_N1{42}

DD

O

ATA_PRX_DTX_P1{42}

S S

ATA_PRX_DTX_N1{42}

S

OC_SCI#

1 2

R

C32 0_0402_5%

1 2

C35 49.9_0402_1%

R

1 2

R

C43 49.9_0402_1%

B B

+

1.8VS

R

PC9

2.2K_0404_4P2R_5%

1 4

2 3

O

DD_DA#_SOC

DD_DETECT#_SOC

O

A A

+

3VS

@

1 2

C957 10K_0402_5%

R

1 2

C965 10K_0402_5%

R

@

O

DD_DETECT#

O

DD_DA#

S

11

C17A

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

2

G1 D

1 6

@

+

1.8VS

2 5 G

2 3

D

4

S

2

C17B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

@

5

4

S

ATA_PTX_DRX_P0 ATA_PTX_DRX_N0

S S

ATA_PRX_DTX_P0 ATA_PRX_DTX_N0

S

ATA_PTX_DRX_P1

S SATA_PTX_DRX_N1

ATA_PRX_DTX_P1

S S

ATA_PRX_DTX_N1

DD_DETECT#_SOC

O O

DD_DA#_SOC

SATA_RCOMP_DP S

ATA_RCOMP_DN

S

DMMC1_RCOMP

DMMC3_RCOMP

S

4

AU16 AV16

BD10 BF10

AY16 BA16

BB10 BC10

BA12 AY14 A

AU18 AT18

AT22 AV20

AU22 AV22 AT20 AY24 AU26 AT26 AU20

AV26 B

AY18

BA18 AY20 BD20 BA20 B BC18

AY26 AT28 BD26 AU28 BA26 BC24 AV28 BF22 B

BF26

DD_DA# {42}

O

DD_DETECT# {42}

O

UC1D

BF6

ATA_TXP_0

S

BG7

ATA_TXN_0

S

ATA_RXP_0

S

ATA_RXN_0

S

ATA_TXP1

S

ATA_TXN_1

S

ATA_RXP_1

S

ATA_RXN_1

S

CLK_SATA_TERMP

I

CLK_SATA_TERMN

I

ATA_GP0

S

ATA_GP1

S

Y12

ATA_LED

S

ATA_RCOMP_P_AU18

S

ATA_RCOMP_N_AT18

S

MC1_CLK

M

MC1_D0

M

MC1_D1

M

MC1_D2

M

MC1_D3

M

MC1_D4

M

MC1_D5

M

MC1_D6

M

MC1_D7

M

MC1_CMD

M

A24

MC1_RST

M

MC1_RCOMP

M

D2_CLK

S

D2_D0

S

D2_D1

S S

D2_D2

D18

S

D2_D3_CD

S

D2_CMD

S

D3_CLK

S

D3_D0

S

D3_D1

S

D3_D2

S

D3_D3

S

D3_CD#

S

D3_CMD

S

D3_1P8EN

D22

S

D3_PWREN

S

D3_RCOMP

BAY-TRAIL-M-SOC_FCBGA1170

@

V1P8S V1P8S V1P8S

RESERVED_VS RESERVED_VSS5

?

? VLV_M_D

VLV_M_D

S4

RESERVED_VSS7 RESERVED_VSS6

P

V1P8S

P

V1P8S

P

V1P8S

P

V1P8S

CIE_RCOMP_P_AP14_AP14

P

CIE_RCOMP_N_AP13_AP13

P

R R

R

DA_LPE_RCOMP

H

VAUD VAUD VAUD VAUD VAUD VAUD

VAUD GPIO_S0_SC_14 GPIO_S0_SC_15

L

PE_I2S2_DATAOUT

L

PE_I2S2_DATAIN

R R

V1P0_S3

OF 13 REV = 1.15

4

CIE_TXP_0

P

CIE_TXN_0

P

CIE_RXP_0

P

CIE_RXN_0

P

CIE_TXP_1

P

CIE_TXN_1

P

CIE_RXP_1

P

CIE_RXN_1

P

CIE_TXP_2

P

CIE_TXN_2

P

CIE_RXP_2

P

CIE_RXN_2

P

CIE_TXP_3

P

CIE_TXN_3

P

CIE_RXP_3

P

CIE_RXN_3

P

SS_BB7

V

SS_BB5

V

CIE_CLKREQ_0 CIE_CLKREQ_1 CIE_CLKREQ_2 CIE_CLKREQ_3

D3_WP_BD5

S

ESERVED_BB4 ESERVED_BB3

ESERVED_AV10

ESERVED_AV9

H

DA_RST

H

DA_SYNC H

DA_CLK

H

DA_SDO

H

DA_SDI0

H

DA_SDI1

H

DA_DOCKRST

H

DA_DOCKEN

L

PE_I2S2_CLK

L

PE_I2S2_FRM

ESERVED_P34 ESERVED_N34

ESERVED_AK9 ESERVED_AK7

P

ROCHOT

?

3

et name changed to same as ACLU1

N

AY7

P

CIE_CTX_GRX_P0

AY6

CIE_CTX_GRX_N0

P

AT14

P

CIE_CRX_GTX_P0

AT13

CIE_CRX_GTX_N0

P

AV6

CIE_CTX_GRX_P1

P

AV4

PCIE_CTX_GRX_N1

AT10

CIE_CRX_GTX_P1

P

AT9

P

CIE_CRX_GTX_N1

AT7

P

CIE_PTX_DRX_P4

AT6

CIE_PTX_DRX_N4

P

AP12

P

CIE_PRX_DTX_P4

AP10

CIE_PRX_DTX_N4

P

AP6

CIE_PTX_DRX_P3

P

AP4

PCIE_PTX_DRX_N3

AP9

CIE_PRX_DTX_P3

P

AP7

P

CIE_PRX_DTX_N3

BB7 BB5

G3

B

G

PU_CLKREQ#_Q

D7

B

CIE_CLKREQ_2#

P

G5

B

W

LAN_CLKREQ#_Q

E3

B

AN_CLKREQ#_Q

L

BD5 AP14

CIE_RCOMP_DP

P

AP13

P

CIE_RCOMP_DN

BB4 BB3 AV10 AV9

BF20

DA_RCOMP

H

G22

B

HDA_RST_AUDIO#_R

BH20

H

DA_SYNC_AUDIO_R

BJ21

DA_BITCLK_AUDIO_R

H

BG20

H

DA_SDOUT_AUDIO_R

BG19 BG21

H18

B

G18

B BF28

BA30

I

2S_2_FS

BC30

I

2S_2_TXD

BD28 P34

N34 AK9

AK7

24

C

PU_PROCHOT#_R

ecurity Classification

S

ssued Date

I

TH

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2 1 2 1 2 1 2 1 2

1 2

C44 0_0402_5%

R

C36 49.9_0402_1%

R

R RC37 33_0402_5%RC37 33_0402_5% R

R

C38 33_0402_5%

C38 33_0402_5% C39 33_0402_5%

C39 33_0402_5%

R

R R

R

C40 33_0402_5%

2S_2_FS {12}

I

2S_2_TXD {12}

I

+

013/03/26

2

OPT@

12

C

C4.1U_0402_10V6-K

12

C5.1U_0402_10V6-K

C

OPT@

OPT@ OPT@

OPT@

12

C6.1U_0402_10V6-K

C

12

C

C7.1U_0402_10V6-K

OPT@

12

C

C104.1U_0402_10V6-K

12

C103.1U_0402_10V6-K

C

12

C105.1U_0402_10V6-K

C

12

C

C106.1U_0402_10V6-K

P

CIE_RCOMP_DP

P

CIE_RCOMP_DN

1.0VS

R

C42

73.2_0402_1%

@

1 2

H

C Future Center Secret Data

L

_PROCHOT# {44,51,52}

3

2

PCIE_CTX_C_GRX_P0 {19} P

CIE_CTX_C_GRX_N0 {19} CIE_CRX_GTX_P0 {19}

P P

CIE_CRX_GTX_N0 {19}

P

CIE_CTX_C_GRX_P1 {19}

PCIE_CTX_C_GRX_N1 {19} P

CIE_CRX_GTX_P1 {19} CIE_CRX_GTX_N1 {19}

P PCIE_PTX_C_DRX_P4 {40}

P

CIE_PTX_C_DRX_N4 {40} CIE_PRX_DTX_P4 {40}

P P

CIE_PRX_DTX_N4 {40}

P

CIE_PTX_C_DRX_P3 {37}

CIE_PTX_C_DRX_N3 {37}

P P

CIE_PRX_DTX_P3 {37} CIE_PRX_DTX_N3 {37}

P

C31

R

R 402_0402_1%

402_0402_1%

1 2

DA_RST_AUDIO# {43}

H

DA_SYNC_AUDIO {43}

DA_BITCLK_AUDIO {43}

H

DA_SDOUT_AUDIO {43}

H

DA_SDIN0 {43}

eciphered Date

D

2

0607

GPU

d

W

LAN

2013/02/01

AN_CLKREQ#_Q

L

MMBT3904WH_SOT323-3

WLAN_CLKREQ#_Q

MMBT3904WH_SOT323-3

G

PU_CLKREQ#_Q

12

OC_SCI#

S

1

+

1.8VS

PC1

R

AN_CLKREQ#_Q

L GPU_CLKREQ#_Q P

CIE_CLKREQ_2#

LAN_CLKREQ#_Q

W

AN_CLKREQ#

L W

LAN_CLKREQ#

+

MMBT3904WH_SOT323-3

+

R

C967

2.2K_0402_5%

G

3

S

Q

C13

PJA138K_SOT23-3

itle

T

S

OC (PCIE&HDA&SATA&STRAPS)

S

Size Document Number Rev

ize Document Number Rev

C

ustom

Date: Sheet

1 8 2 7 3 6 4 5

C968 10K_0402_5%

R

R R

R

C969 10K_0402_5%

1.8VS

12

C958

R

2.2K_0402_5%

2

B

E

31

C

Q

C6

1.8VS

12

R

C959

2.2K_0402_5%

2

B

E

31

C

C7

Q

+1.8VS

12

R

C960

2.2K_0402_5%

OPT@

2

B

E

31

C

OPT@

Q

C199

c

1.8VS

2

1

D

ACLU9

M

onday, December 23, 2013

10K_0804_8P4R_5%

12 12

3VS

+

LAN_CLKREQ# {37}

W

LAN_CLKREQ# {40}

G

PU_CLKREQ# {19}

hange mos to 3904

3VALW_R

+

R

C95

10K_0402_5%

@

1 2

E

C_SCI# {44}

o

f

6 59

f

6 59

f

6 59

1

0

.2

5

TAL25_IN

C12

C

C 18P_0402_50V8J

18P_0402_50V8J

1 2 3 4

C

1

C10

2

X

1

C13

C

C 10P_0402_50V8-J

10P_0402_50V8-J

2

C2

U

S#

C SO(IO1)

HOLD#(IO3)

W

S

P#(IO2)

V

S

SS

I(IO0)

GD25LQ64CVIGR_TSOP8

0605

C89 2 0K_0402_1%

R

1 2

C90 2 0K_0402_1%

R

1 2

1U_0402_6.3V6K

12

CMOS1

J

J SHORT PADS

SHORT PADS

@

JCMOS/JCMOS1

Place under Bo ttom

RTCRST#

S

pace 15Mil

C93 1M_0402 _5%

R

C2

Y

1

O

SC1

2

ND1

G

25MHZ_10PF_7V25000 014

8

CC

V

7

PI_HOLD#

S

6

CH_SPI_CLK

P

CLK

5

CH_SPI_SI

P

1 2

0mA

5

V

G O

CCRTC

ND2 SC2

TC_X1 R

1 2

C92 1 0M_0402_5%

R

1 2

C1

Y

32.768KHZ_12.5PF_2004 58-PG14

2

C11

C

D D

18P_0402_50V8J

1

1,Space 15MIL 2,No trace und er crystal

RYSTAL

C

1.8VALW_SPI

+

P

C C

SPI ROM

3,place on opp sosit side of MCP for temp i nfluence

1.8VALW

+

C82 0_0402_ 5%

R

1 2

PC15

R

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

hange 3.3K to 2.2K 4R8P

c

C85

R

1 2

CH_SPI_SO_R

22_0402_5%

RTC_RST#

S

TC_RST#

R

ME1

J

SHORT PADS

@

TC_X2 R

2

1

1.8VALW_SPI

+

PI_WP#

S

PI_HOLD#

S

CH_SPI_CS0#

P

CH_SPI_CS0#

P

CH_SPI_SO

P

PI_WP#

S

1U_0402_6.3V6K

1

12

C

C C9

C9

2

4 3

C14

C

10P_0402_50V8-J

1.8VALW_SPI

+

1

C8

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

TAL25_OUT X

1

2

RTC RST#

PC17

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

1 4

C15A

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

3VS

+

2 3 D

25

G

2 S

4

0603

OC_SMI#

S

OC_LID_OUT#

S

5

C15B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

+

0605

2 3

C104

R

R 100K_0402_5%

100K_0402_5%

1 2

1.8VALW

PC6

R

2.2K_0404_4P2R_5%

1 4

4

S

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

2

C14B

P

LT_RST# {19,37,40,44}

2 5 G

2 3

D

1.8VALW

+

2

1 G

1 6S11

D

C14A

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

3VALW_R

+

2 3

1 4

PC7

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

3VALW

+

B B

2 3

1 6 D

1

G

MC_PLTRST#

P

A A

2

11 S

_SERIRQ need change to level shift

0801 EC_INT

P

P P

E

C_SMI# {44}

E

C_LID_OUT# {44}

4

UC1E

AH12

TAL25_IN

X

TAL25_OUT

X

1 2

C70 4 .02K_0402_1%

R

1 2

C62 47.5_040 2_1%

R

LK_PCIE_GPU#{19}

C

LK_PCIE_GPU{19}

C

LK_PCIE_WLAN#{40}

C

LK_PCIE_WLAN{40}

C

LK_PCIE_LAN#{37}

C

LK_PCIE_LAN{37}

C

CLK_ICOMP

I

CLK_RCOMP

I

LK_PCIE_GPU#

C

LK_PCIE_GPU

C

C C

LK_PCIE_WLAN# LK_PCIE_WLAN

LK_PCIE_LAN# LK_PCIE_LAN

RTC_RST#

S

XDP

C81 2 2_0402_5%

R

1 2

CH_SPI_CS0#

1 2

CH_SPI_SI

C84 2 2_0402_5%

R

1 2

CH_SPI_CLK

C88 2 2_0402_5%

R

1 2

C91 4 9.9_0402_1%

R

T

he ALT_GPIO_SMI.CORE_GPIO_SMI_STS [31:24] & ALT_GPIO_SMI.CORE_GPIO_SMI _EN[15:8] register bits correspond to GPIO_S0_SC[7:0]. ALT_GPIO_SMI.SUS_GPIO_SMI_STS[23:16] & ALT_GPIO_SMI.SUS_GPIO_SMI_EN[7:0] correspond to GPIO_S5[7:0].

4

OC_KBRST#

S

MC_PWRBTN#

P

CH_SPI_CS0#_R

P

CH_SPI_SO_R

P

CH_SPI_SI_R

P

CH_SPI_CLK_R

P

OC_KBRST#

S

OC_LID_OUT#

S

OC_SMI#

S

PIO_RCOMP18

G

1.8VALW

+

1 4

2 3

AH10

AD9

AD14 AD13

AD10 AD12

AF6 AF4

AF9 AF7

AK4 AK6

AM4 AM6

AM10

AM9

BH7 BH5 BH4 BH8 BH6

BJ9 C12

D14

G

12 F14 F12

G16

D

18 F

16

AT34

C23 C

21 B22 A21 C22

B18 B16 C18 A17 C17 C16 B14 C15

C13 A13 C19

N26

PC4

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

4

2

S

C12B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

ICLK_OSCIN I

CLK_OSCOUT

ESERVED_AD9

R ICLK_ICOMP

I

CLK_RCOMP

ESERVED_AD10

R

ESERVED_AD12

R P

CIE_CLKN_00

P

CIE_CLKP_00 CIE_CLKN_11

P PCIE_CLKP_11

CIE_CLKN_22

P

CIE_CLKP_22

P P

CIE_CLKN_33

P

CIE_CLKP_33 ESERVED_AM10

R RESERVED_AM9

PMC_PLT_CLK_00 P

MC_PLT_CLK_11

P

MC_PLT_CLK_22 MC_PLT_CLK_33

P

MC_PLT_CLK_44

P PMC_PLT_CLK_55 I

LB_RTC_RST

AP_TCK

T

AP_TRST

T TAP_TMS T

AP_TDI

T

AP_TDO AP_PRDY

T

AP_PREQ

T RESERVED

P

CU_SPI_CS_00 CU_SPI_CS_11

P

CU_SPI_MISO

P PCU_SPI_MOSI P

CU_SPI_CLK

PIO_S5_0

G GPIO_S5_1 G

PIO_S5_2

G

PIO_S5_3 PIO_S5_4

G

PIO_S5_5

G GPIO_S5_6 G

PIO_S5_7

GPIO_S5_8 G

PIO_S5_9

G

PIO_S5_10

GPIO_RCOMP

BAY-TRAIL-M-SOC_FCBGA1170

@

1.8VALW

+

2

1 G

1 6S11

D

C12A

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

2 5 G

2 3

D

V1P8A V1P8A V1P8A V1P8A V1P8A

V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A

V1P8A V1P8A V1P8A

5 OF 13 ?REV = 1.15

3VALW_R

+

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

1 4

2 3

3

PC5

3

?

LV_M_D

V

GPIO_S5_14

Internal 20

GPIO_S5_17

K

P

V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8S

K(H)

V1P8A V1P8A V1P8A

VRTC VRTC

BRST# {44}

BTN_OUT# {44}

SIO_UART1_RXD S

IO_UART1_TXD

S

IO_UART1_RTS IO_UART1_CTS

S SIO_UART2_RXD

S

IO_UART2_TXD

S

IO_UART2_RTS IO_UART2_CTS

S

P

MC_SUSPWRDNACK

MC_SUSCLK0_G24

P

MC_SLP_S0IX

P

PMC_SLP_S4 P

G

PIO_S514_J20

MC_ACPRESENT

P MC_WAKE_PCIE_0

P

PMC_BATLOW P

MC_PWRBTN

P

PIO_S517_J24

G

PMC_SUS_STAT

LB_RTC_TEST

I

MC_RSMRST

P

MC_CORE_PWROK

P

LB_RTC_EXTPAD

I

V1P0S V1P0S V1P0S

S SIO_PWM_11

V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A

V1P8S

IO_SPI_MISO

S

V1P8S

IO_SPI_MOSI

S

V1P8S

SIO_SPI_CLK

V1P8S

MC_SLP_S3

MC_RSTBTN MC_PLTRST

I

LB_RTC_X1 LB_RTC_X2

I

VID_ALERT

S

SVID_DATA

S

VID_CLK

IO_PWM_00

GPIO_S5_22 G

PIO_S5_23

G

PIO_S5_24 PIO_S5_25

G

PIO_S5_26

G GPIO_S5_27 G

PIO_S5_28

G

PIO_S5_29 PIO_S5_30

G

S

IO_SPI_CS

P

MC_SLP_S3#

P

MC_SLP_S4#

AU34 AV34 BA34 A

Y34

BF34 BD34 BD32 B

F32

D26 G24 F

18 22

F D22 J20 D20 F

26 26

K J26 BG9 F

20

J24

18

G

C

11

B

10

B7

C9 A9 B8

B

24 A25 C25

AU32 AT32

K24 N24 M20 J18 M18 K18 K20 M22 M24

AV32 BA28 AY28 AY30

USPWRDNACK

S

MC_SUSCLK

P

MC_SLP_S0IX#

P

MC_SLP_S4#

P

MC_SLP_S3#

P

PIO_S514_J20

G

MC_ACIN

P

MC_PCIE_WAKE#

P

MC_BATLOW#

P

MC_PWRBTN#

P

MC_RSTBTN#

P

MC_PLTRST#

P

1

TC_RST#

R

C_RSMRST#

E

YS_PWROK

S

TC_X1

R

TC_X2

R

VCCRTC_EXTPAD

B

PU_SVID_ALRT#_R

C

PU_SVID_DAT_R

C

PU_SVID_CLK_R

C

1.8VALW

+

1 4

2 3

2

1

P9@TP9@

T

1

P10@TP10@

T

P1@TP1@

T

1 1

P3@TP3@

T

1.8VALW

3VALW_R

+

604

0

P4

1

@

R

1 2

R

P5@TP5@

T

C17 .1U_0402_10V6-K

C

C78 20_0402_1%

1 2

R

1 2

C79 16.9_0402_1%

R

1 2

C80 0_0402_5%

R

P4

T

C71 10K_0402_5%

C72 10K_0402_5%

C_RSMRST# {44}

E

YS_PWROK {5,44 }

S

1 2

1.8VALW

+

1.8VALW

+

PU_SVID_ALERT# {59}

C

PU_SVID_DAT {5 9}

C

PU_SVID_CLK {59}

C

MC_ACIN

P

C60

R

R 10K_0402_5%

10K_0402_5%

1 2

C63

R

R 10K_0402_5%

10K_0402_5%

1 2

C61

R

2.2K_0402_5%

@

1 2

3

S

Q

Q PJA138K_SOT23-3

PJA138K_SOT23-3

13

D

C9

@

C9

Q

S

2N7002KW_SOT32 3-3

2

G

need check pow er part if RES is staffed

C927

R

R 10K_0402_5%

10K_0402_5%

1 2

MC_PCIE_WAKE#

P

R

C75

10K_0402_5%

1 2

USPWRDNACK

S

+

1.8VALW

3VALW_R

+

R

PC2

10K_0404_4P2R_5%

@

4

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

PJT138K_SOT363-6

2 5 G

Q

D

2 3

PJT138K_SOT363-6

2

C11B

PC3

R

R 10K_0404_4P2R_5%

10K_0404_4P2R_5%

C11A

Q

1

1 4

2 3

G D

1 6S11

013/03/26

2

M_SLP_S3# {44}

P

M_SLP_S4# {44}

P

C Future Center Secret Data

L

eciphered Date

D

P

MC_SUSCLK

B

ay trail plaform susclk is 1.8VSA level, NGFF card need 3.3V

2013/02/01

1

1.8VS

+

1 2

MC_RSTBTN#

P

MC_SUSCLK

P

C_RSMRST#

E

C_RSMRST#

E

2

G

D

C203

0605

+

G

3

S

C168

Q

Q PJA138K_SOT23-3

PJA138K_SOT23-3

G

3

S

C10

Q

Q PJA138K_SOT23-3

PJA138K_SOT23-3

12

@

C73 10K_0402_5%

R

1 2

C83 10K_0402_5%@RC83 10K_0402_5%@

R

C930 100K_0402_5%

R

12

C113 0.01U_0402_25V7 K

1 2

C

@

f

or ACINneed ch eck with power team

1

1 2

C69

@RC69

@

R

0_0402_5%

@

1.8VALW

3VALW

+

12

C793

R

R 10K_0402_5%

10K_0402_5%

2

1

D

+

1.8VALW

2

1

D

@

+

1.8VALW

C932

R

2

2.2K_0402_5%

G

3

D

S

D

S

C200

Q

Q PJA138K_SOT23-3

PJA138K_SOT23-3

T

itle

S

OC (RTC&SPI&PM)

ize D ocument Number Rev

S

Size D ocument Number Rev

ustom

C

hursday, December 26, 2013

T

Date: Sheetof

Date: Sheet

3VALW_R

+

1

@

R

R 10K_0402_5%

10K_0402_5%

1 2

1

C_PRESENT {44}

A

CIN# {44,53}

A

CIE_WAKE# {37,40,44}

P

C74

USWARN# {44}

S

3VALW

+

R

C933

10K_0402_5%

@

1 2

ACLU9

USCLK {40}

S

7 59

o

0

f

.2

0801 EC_INT_SERIRQ need change to level shift

5

CH_CMOS_ON#_Q

P

DD_EN

O

DD_EN{42}

O

D D

SB20_P1{41 }

U

SB20_N1{41}

SB_OC0#{4 1}

U

SB_OC1#{4 5}

U

C113 45 .3_0402_1%

R

C114 45.3_0402_1%

R

C117 49.9_0402_1%

R

C118 22_0402_5%

R

C119 0_ 0402_5%

R

DD_EN

O

PIO52

G

PIO53

G

GPIO52 G

PIO53

XS_PWREN

P P

XS_RST#

5

U

SB20_P0{45 }

U

SB20_N0{45}

U

SB20_P2{41 }

U

SB20_N2{41}

U

SB20_P3{16 }

U

SB20_N3{16}

U

1 2

SB_OC0#

U

SB_OC1#

U

CH_SMB_DATA

P

CH_SMB_CLK

P

CH_SMB_ALERT#

P

PCB ID

EFT USB (3.0)

L

RIGHT USB (2.0)

LEFT USB (2.0) USB Hub

U

SB_RCOMP

Width 20Mil Space 15Mil Length 500Mil

C C

PC_AD0{44}

L

PC_AD1{44}

L

PC_AD2{44}

L

PC_AD3{44}

L

PC_FRAME#{44}

L

LK_PCI_EC{44}

C

OC_SERIRQ

S

B B

1.8VS

+

1 2

C120 10K_0 402_5%

R

1.8VALW

+

R

3VS

+

1 2

C964 10K_0402_5%

R

GC6@

1 2

C105 1K_ 0402_1%

R

1 2

C106 1K_ 0402_1%

R

1 2

C108 0_ 0402_5%@RC108 0_ 0402_5%@

R

A A

eserve for NV GPU

R

C954 10K_0402_ 5%@RC954 10K_0402_ 5%@

R

1 2 1 2

R

C955 10K_0402_ 5%@RC955 10K_0402_ 5%@

C17 100K_0402_5%@RC17 100K_0402_5%@

R

1 2

R

C18 10K_0402_5%@RC18 10K_0402_5%@

PC18

14 23

10K_0404_4P2R_5%

@

14 23

10K_0404_4P2R_5%

CH_SMB_ALERT#

P

SB_OC0#

U

SB_OC1#

U

PC19

R

CLK_USB_TERMN_0

I

CLK_USB_TERMN_1

I

SB_PLL_MON

U

12

P P P P

SB20_P1

U

SB20_N1

U

SB20_P0

U

SB20_N0

U

SB20_P2

U

SB20_N2

U

SB20_P3

U

SB20_N3

U

CLK_USB_TERMN_0

I

CLK_USB_TERMN_1

I

SBRBIAS

U

SB_PLL_MON

U

SB_HSIC_RCOMP

U

COMP_LPC_HVT

R

CH_PCI_CLK_R

P

CB_ID0

PCB_ID1

0 Reserve

1 GPU SKU

0 14’ panel

1 15’ panel

P P P P

0610

CB_ID0 CB_ID1 CB_ID2

B12

CB_ID3

M16 K16

J14

G14 K12

J12

K10 H10

D10 F10

C20 B

M13

BF18 BH16 BJ17

BJ13 BG14 BG17 BG15

BH14

G16

B BG13

BG12

BH10 B

G11

PCB_ID2 PCB_ID3

Reserve

Reserve Reserve

O

C54

C54 R

R

1 2

2.2K_0402_5%

CB_ID0 CB_ID1 CB_ID2 CB_ID3

U

C57

C57 R

R

1 2

2.2K_0402_5%

UC1F

G2

GPIO_S5_31

M3

PIO_S5_32

G

L1

PIO_S5_33

G

K2

GPIO_S5_34

K3

G

PIO_S5_35

M2

G

PIO_S5_36

N3

PIO_S5_37

G

P2

PIO_S5_38

G

L3

GPIO_S5_39

J3

PIO_S5_40

G

P3

GPIO_S5_41

H3

G

PIO_S5_42

G

PIO_S5_43

USB_DP0 U

SB_DN0 SB_DP1

U

SB_DN1

U U

SB_DP2

U

SB_DN2 SB_DP3

U USB_DN3

CLK_USB_TERMN_D10

I

CLK_USB_TERMN

I

U

SB_OC_00

20

SB_OC_11

U

D6

U

SB_RCOMPO

C7

SB_RCOMPI

U

SB_PLL_MON

B4

USB_HSIC0_DATA

B5

U

SB_HSIC0_STROBE

E2

SB_HSIC1_DATA

U

D2

USB_HSIC1_STROBE

A7

SB_HSIC_RCOMP

U

L

PC_RCOMP

LB_LPC_AD_00

I

LB_LPC_AD_11

I ILB_LPC_AD_22 I

LB_LPC_AD_33

I

LB_LPC_FRAME LB_LPC_CLK_00

I

LB_LPC_CLK_11

I ILB_LPC_CLKRUN I

LB_LPC_SERIRQ

P

CU_SMB_DATA CU_SMB_CLK

P

CU_SMB_ALERT

P

BAY-TRAIL-M-SOC_FCBGA1170

REV = 1.15

REV = 1.15 @

@

PT@

5@

1

C55

C55 R

R

1 2

2.2K_0402_5%

4@

MA@

1

C56

C56 R

R

1 2

2.2K_0402_5%

U

MA SKU

V1P8A

V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A V1P8A

V1P8A V1P8A V1P8A V1P8A

V1P8A V1P8A

1.8VALW

+

C944

C944 R

R

C946

C946 R

R

VLPC VLPC VLPC VLPC VLPC VLPC VLPC VLPC VLPC V1P8S

V1P8S V1P8S V1P8S

Description

@

1 2

2.2K_0402_5%

@

1 2

2.2K_0402_5%

ICLK_USB_TE

C945

C945 R

R

2.2K_0402_5%

C947

C947 R

R

2.2K_0402_5%

4

?

LV_M_D

V

RM_1

V1P8S V1P8S V1P8S V1P8S V1P8S V1P8S V1P8S

V1P8S

V1P8S V1P8S

6 OF 13

V1P8S V1P8S

@

+

1 2

SOC_SERIRQ

@

1 2

4

C15

C

.1U_0402_10V6-K

S

ERIRQ level shift need IC, not MOS for frequence

RESERVED_M10

R

ESERVED_M9 ESERVED_P7

R

ESERVED_P6

R

ESERVED_M7

SB3_REXT0

U

RESERVED_P10 R

ESERVED_P12

ESERVED_M4

R

ESERVED_M6

R

U

SB3_RXP0

U

SB3_RXN0 SB3_TXP0

U USB3_TXN0

ESERVED_H8

R RESERVED_H7

ESERVED_H5

R

ESERVED_H4

R

G

PIO_S0_SC_55 PIO_S0_SC_56

G

PIO_S0_SC_57

G GPIO_S0_SC_58 G

PIO_S0_SC_59

G

PIO_S0_SC_60 PIO_S0_SC_61

G

I

LB_8254_SPKR

S

IO_I2C0_DATA S

IO_I2C0_CLK

SIO_I2C1_DATA

S

IO_I2C1_CLK

IO_I2C2_DATA

S

SIO_I2C2_CLK

IO_I2C3_DATA

S

IO_I2C3_CLK

S

IO_I2C4_DATA

IO_I2C4_CLK

S

IO_I2C5_DATA S

IO_I2C5_CLK

SIO_I2C6_DATA

S

IO_I2C6_CLK

PIO_S0_SC_092

G

PIO_S0_SC_093

G

1.8VS

C96

R

R 0_0402_5%

0_0402_5%

1 2

1

2

M10 M9

P7 P6

M7 M12

P10 P12

M4 M6

D4 E3

K6 K7

H8 H7

H5 H4

BD12 BC12 BD14 BC14 BF14 BD16 BC16

BH12

BH22 BG23

BG24 BH24

BG25 BJ25

BG26 BH26

BF27 BG27

BH28 BG28

BJ29 BG29

BH30 BG30

?

C3

U

1

CCA

V

2

G

ND

3

4

A

G2129TL1U_SC70- 6

SB3_P1_REXT

U

SB30_RX_P1

U

SB30_RX_N1

U

SB30_TX_P1

U

SB30_TX_N1

U

P

CCB

V

E

O

B

XS_RST#_SOC

P

PIO_S0_SC_56

G

GA_PWRGD_SOC

V

PIO52_SOC

G

PIO53_SOC

G XS_PWREN_SOC

CH_WLAN_OFF# _Q

CH_BT_OFF#_Q

P

C97

R

0_0402_5%

6 5 4

4

1 2

C110 1.24K_0402_1%

R

3VS+1.8VS

+

R

R 10K_0402_5%

10K_0402_5%

1 2

1

C16

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

SB30_RX_P1 {41}

U

SB30_RX_N1 { 41}

U

SB30_TX_P1 {41}

U

SB30_TX_N1 {41}

U

PIO_S0_SC_56 {12}

G

CH_BEEP {43}

P

C98

3

LEFT USB (3.0)

ERIRQ {44 }

S

3

eserve for GPU

R

CH_PCI_CLK_R

P

EMC

2

3VS

+

1.8VS

+

12

C970

R

2

G

1

D

S

D

S

C4

Q

Q PJA138K_SOT23-3

PJA138K_SOT23-3

OPT@

CH_WLAN_OFF# {40}

P

1

2

013/03/26

R

2.2K_0402_5%

OPT@

CH_SMB_CLK

P

CH_SMB_DATA

P

2

XS_RST# {19}

P

CH_BT_OFF#_Q

P

GA_PWRGD {22,44}

V

1.8VS

+

1 4

2 3

C Future Center Secret Data

L

D

+

25

G

R

PC22

2.2K_0404_4P2R_5%

4

2

S

C20B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

eciphered Date

C948

R

R 10K_0402_5%

10K_0402_5%

OPT@

1 2

2

1

G

C966

R

2.2K_0402_5%

@

ssued Date

3VS

+

C115

R

R 10K_0402_5%

10K_0402_5%

1 2

C19A

Q

1 6 D

11 S

PJT138K_SOT363-6

1.8VS

+

2

G

3

D

S

D

S

C204

Q

Q PJA138K_SOT23-3

PJA138K_SOT23-3

@

3

XS_RST#_SOC

P

CH_WLAN_OFF# _Q

P

12

GA_PWRGD_SOC

V

C108

C

1 2

10P_0402_50V8-J

@

S

ecurity Classification

I

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3VS

C116

R

R 10K_0402_5%

10K_0402_5%

1 2

2 3 D

2 S

4

2 5 G

D

GA_GATE#{44}

V

P

C19B

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

+

Q

C20A

PJT138K_SOT363-6

2 3

2013/02/01

XS_PWREN_SOC

P

CH_BT_OFF# {40}

PIO52_SOC

G

PIO53_SOC

G

1.8VS

2

1 G

1 6S11

D

1

3VS

+

1.8VS

+

12

C971

R

2.2K_0402_5%

2

1

D

2

G

1

@

2

C18

Q

2

@

PJA138K_SOT23-3

1.8VS

+

2

C21A

Q

Q PJT138K_SOT363-6

PJT138K_SOT363-6

2 5 G

GC6@

2 3

D

onday, December 23, 2013

M

1

2.2K_0402_5%

OPT@

13

D

C201

Q

Q 2N7002KW_SOT32 3-3

2N7002KW_SOT32 3-3

S

3VS

+

C112

R

R 10K_0402_5%

10K_0402_5%

1 2

1

D

G

S

3

1 G

1 6S11

D

ACLU9

@

C956

R

R 10K_0402_5%

10K_0402_5%

OPT@

G

1 2

3

S

C8

Q

Q PJA138K_SOT23-3

PJA138K_SOT23-3

OPT@

1 2

C170

@RC170

@

R

0_0402_5%

C107

C

.1U_0402_10V6-K

@

CH_CMOS_ON#_Q

P

1.8VS

+

PC8

R

2.2K_0404_4P2R_5%

GC6@

1 4

2 3

4

2

S

Q

C21B

PJT138K_SOT363-6

GC6@

3VS

+

R

PC23

2.2K_0404_4P2R_5%

1 4

2 3

MB_CLK_S3 {14 ,40}

S

MB_DATA_S3 {14,40 }

S

T

itle

S

OC (USB&LPC&SMB)

ize D ocument Number Rev

S

Size D ocument Number Rev ustom

ustom

C

C Date: Sheetof

Date: Sheetof

Date: Sheet

XS_PWREN { 21,58}

P

MOS_ON# {33}

C

8 59

PIO52 {19}

G

PIO53 {19}

G

f

o

.2

0

5

+

CPU_CORE

12

R

C131 100_0402_1%

GFX_CORE

+

12

R

C130 100_0402_1%

D D

C C

12

C132 100_0402_1%

R

CC_SENSE

V

CC_AXG_SENSE

SS_SENSE

V

+

CPU_CORE

12 A

1

C

C22

10U_0603_6.3V6M

2

+

CPU_CORE

B B

1

C

C35

22U_0805_6.3V6M

CD@

2

1.35V

+

1

C

C23

4.7U_0402_6.3V6M

2

CD@

1

C

C36

22U_0805_6.3V6M

2

CC_SENSE{59}

V V

CC_AXG_SENSE{59} SS_SENSE{59}

V

1.35V

+

1 2

0_0603_5%

CPU_CORE

+

402 10uF SE00000UD8J

0 0402 4.7uF SE00000SO0J 0402 2.2uF SE00000888J 0402 1uF SE000000K0J

1

C

C24

4.7U_0402_6.3V6M

2

1

C

C37

22U_0805_6.3V6M

CD@

2

R

C129

4

VCC_SENSE V

CC_AXG_SENSE SS_SENSE

V

D

RAM_VDD_S4_CLK

1

C

C25

2.2U_0402_6.3V6M

2

33P_0402_50V8J

C

1

C109

2

@

or RF request

F

UC1G

P28

ORE_VCC_SENSE_P28

C

BB8

NCORE_VNN_ SENSE

U

N28

ORE_VSS_SENSE_N28

C

AD38

RAM_VDD_S 4_AD38

D

AF38

RAM_VDD_S 4_AF38

D

A48

RAM_VDD_S 4

D

AK38

RAM_VDD_S 4_AK38

D

AM38

RAM_VDD_S 4_AM38

D

AV41

RAM_VDD_S 4_AV41

D

AV42

RAM_VDD_S 4_AV42

D

BB46

RAM_VDD_S 4_BB46

D

AA27

ORE_VCC_S0IX_AA27

C

AA29

ORE_VCC_S0IX_AA29

C

AA30

ORE_VCC_S0IX_AA30

C

AC27

ORE_VCC_S0IX_AC2 7

C

AC29

ORE_VCC_S0IX_AC2 9

C

AC30

ORE_VCC_S0IX_AC3 0

C

AD27

ORE_VCC_S0IX_AD2 7

C

AD29

ORE_VCC_S0IX_AD2 9

C

AD30

ORE_VCC_S0IX_AD3 0

C

AF27

ORE_VCC_S0IX_AF2 7

C

AF29

ORE_VCC_S0IX_AF2 9

C

AG27

ORE_VCC_S0IX_AG27

C

AG29

ORE_VCC_S0IX_AG29

C

AG30

ORE_VCC_S0IX_AG30

C

P26

ORE_VCC_S0IX_P26

C

P27

ORE_VCC_S0IX_P27

C

U27

ORE_VCC_S0IX_U27

C

U29

ORE_VCC_S0IX_U29

C

V27

ORE_VCC_S0IX_V27

C

V29

ORE_VCC_S0IX_V29

C

V30

ORE_VCC_S0IX_V30

C

Y27

ORE_VCC_S0IX_Y27

C

Y29

ORE_VCC_S0IX_Y29

C

Y30

ORE_VCC_S0IX_Y30

C

AF30

P_CORE_V 1P05_S4

T

BAY-TRAIL-M-SOC_FCBGA1170

REV = 1.15

REV = 1.15 @

@

1

C

C26

2.2U_0402_6.3V6M

2

3

?

? VLV_M_D

VLV_M_D

U U U U U U U

U U

U

U U U U U U U U

NCORE_VNN_ S3_AM22

U

7 OF 13 ?

D

RAM_VDD_S4_CLK

Vienna is 0402 1uF SE000000K0J

RAM_VDD_S 4_BD49

D

RAM_VDD_S 4_BD52

D

RAM_VDD_S 4_BD53

D

RAM_VDD_S 4_BF44

D

RAM_VDD_S 4_BG51

D

RAM_VDD_S 4_BJ48

D

RAM_VDD_S 4_C51

D

RAM_VDD_S 4_D44

D

RAM_VDD_S 4_F49

D

RAM_VDD_S 4_F52

D

RAM_VDD_S 4_F53

D

RAM_VDD_S 4_H46

D

RAM_VDD_S 4_M41

D

RAM_VDD_S 4_M42

D

RAM_VDD_S 4_V38

D

RAM_VDD_S 4_Y38

D

NCORE_VNN_ S3_AA2 4 NCORE_VNN_ S3_AC22

NCORE_VNN_ S3_AC24

NCORE_VNN_ S3_AD22 NCORE_VNN_ S3_AD24 NCORE_VNN_ S3_AF22

NCORE_VNN_ S3_AF24 NCORE_VNN_ S3_AG2 2 NCORE_VNN_ S3_AG2 4

NCORE_VNN_ S3_AJ22

NCORE_VNN_ S3_AJ24 NCORE_VNN_ S3_AK2 2 NCORE_VNN_ S3_AK2 4 NCORE_VNN_ S3_AK2 5 NCORE_VNN_ S3_AK2 7 NCORE_VNN_ S3_AK2 9 NCORE_VNN_ S3_AK3 0 NCORE_VNN_ S3_AK3 2

P2_CORE_ VCC_S0IX

T

C

1

C20

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

CD@

2

1.35V

+

1.25 A

1

C27

C

2.2U_0402_6.3V6M

2

+

BD49 BD52 BD53 BF44 BG51 BJ48 C51 D44 F49 F52 F53 H46 M41 M42 V38 Y38

AA24 AC22 AC24 AD22 AD24 AF22 AF24 AG22 AG24 AJ22 AJ24 AK22 AK24 AK25 AK27 AK29 AK30 AK32 AM22

AA22

1.35V

GFX_CORE

+

AD NOTE:FOR PIN AD38 AND AF38

1

C21

C

1U_0402_6.3V6K

2

1

C

2.2U_0402_6.3V6M

2

1

C28

C29

C

2.2U_0402_6.3V6M

2

CD@

2

1

C32

C

2.2U_0402_6.3V6M

2

C31

C

33P_0402_50V8J

@

1

C

.1U_0402_10V6-K

2

1

2

For RF For RF

1

C30

C

.1U_0402_10V6-K

2

1

C33

C

33P_0402_50V8J

@

2

1

C34

GFX_CORE

+

33P_0402_50V8J

C

1

C

1U_0402_6.3V6K

2

GFX_CORE

+

2

C

10U_0603_6.3V6M

A A

ienna is 0402 10uF SE00000UD8J

V

5

10U_0603_6.3V6M

1

C40

C

1U_0402_6.3V6K

CD@

2

4 A

1

C41

C39

1

C42

C

1U_0402_6.3V6K

CD@

2

1

C110

C

1U_0402_6.3V6K

2

C43

C

10U_0603_6.3V6M

1

C

1

C38

2

@

For RF request

4

ecurity Classification

S

ssued Date

I

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAI NS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

3

013/03/26

2

C Future Center Secret Data

L

eciphered Date

D

2

2013/02/01

T

itle

S

OC (Power)

ize Document Number Rev

S

C

Date: Sheet

ACLU9

M

onday, December 23, 2013

9 5

o

f

1

f

.2

0

9

5

.0VS_SOC

+1

GA_V1P0_S3

V

D D

+1.05VS

+1

.0VALW_UNCORE_G3

实际是

1

.05VS

+1

.35VS_SOC

I

CLK_V1P35_S3

C C

+1.0VS +1.0VS_SOC

PJ_43x79_6

B B

.0VALW

+1

A A

PJ1

.35VS

1

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

@

1 2

R

C139 0_0603_5%

1 2

1.9 A+850 mA

1

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

CAD NOTE:FOR PINS AK19

1

C

C56

U_0402_6.3V6K

U_0402_6.3V6K 1

1

2

@

1

C

C67

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

@

.0VALW_UNCORE_G3

+1

R

C140 0_0603_5%

0611

C

C46

CD@

U_0402_6.3V6K

U_0402_6.3V6K 1

1

@

CAD NOTE:FOR PINS AJ18

1

C

C57

U_0402_6.3V6K

U_0402_6.3V6K 1

1

2

@

C68

1

C82

C

1U_0402_6.3V6K

2

1

C

C47

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

@

CAD NOTE:FOR PIN AM16

1

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

CAD NOTE:FOR PINS AM16

1

C

C58

2

C

C69

2U_0805_6.3V6M

2U_0805_6.3V6M 2

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

325 mA

1

C83

C

1U_0402_6.3V6K

CD@

2

.35VS_SOC

+1

C

AD NOTE:FOR

PIN AD35 AF35

1

C

C49

1U_0402_6.3V6K

CD@

2

1

C

C59

D@

C

2

CAD NOTE:FOR PIN AF16 AF18

1

C

C70

2

I

CLK_V1P35_S3

CAD NOTE:FOR PIN AF36

1

2

1

C

C61

D@

C

2U_0805_6.3V6M

2

CAD NOTE:FOR PIN Y18 G1 CAD NOTE:FOR

2

C

C71

D@

C

1

.01U_0402_25V7K

.01U_0402_25V7K 0

0

1

C84

C

1U_0402_6.3V6K

2

375 mA+45 mA

1

C

C98

10U_0603_6.3V6M

2

C

1U_0402_6.3V6K

1

2

C50

1

C

C62

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

C85

C

C 1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

2

CAD NOTE:FOR PIN V36

C89

C

1U_0402_6.3V6K

1

C

C99

22U_0805_6.3V6M

CD@

2

CAD NOTE:FOR PINS AJ36 AK35 AK36

1

C

C51

1U_0402_6.3V6K

2

CAD NOTE:FOR PINS AF21 AND AG21

1

C

C63

U_0402_6.3V6K

U_0402_6.3V6K 1

1

2

PIN AN25

1

C

C72

2

CAD NOTE:FOR PIN AD36

1

C90

C

1U_0402_6.3V6K

2

+1.0VS_SOC +1.0VS_SOC

+1.05VS_CORE_S3

+1.0VS_SOC +1.0VS_SOC +1.0VS_SOC

+1.05VS_CORE_S3 +1.05VS_CORE_S3

GA_V1P35_S3

V

CAD NOTE:FOR PINS V24 Y22 Y24

1

U_0402_6.3V6K

U_0402_6.3V6K 1

1

2

@

CAD NOTE:FOR PIN AN18

1

2

U_0402_6.3V6K

U_0402_6.3V6K 1

1

@

CAD NOTE:FOR PINS Y19 AND C3

2

C87

C

0.01U_0402_25V7K

CD@

1

CAD NOTE:FOR PIN AA25

1

C

C100

1U_0402_6.3V6K

CD@

2

CAD NOTE:FOR PINS AA36 Y35 Y36

1

2

C

C64

C

C73

CAD NOTE:FOR PIN AJ19

1

C

1U_0402_6.3V6K

2

C91

V32

BJ6 AD35 AF35 AF36 AA36 AJ36 AK35 AK36

Y35

Y36 AK19 AK21 AJ18 AM16

U22

V22 AN29 AN30 AF16 AF18

Y18

G1 AM21 AN21

AN18 AN19 AA33 AF21 AG21

V24 Y22 Y24 M14 U18 U19

AN25

Y19

C3

C5

B6 AC32

Y32

U36 AA25 AG32

V36

BD1 AF19 AG19 AJ19

AG18 AN16

U16

C

C52

1U_0402_6.3V6K

CAD NOTE:FOR PIN U18 U19

1

CC60

.1U_0402_10V6-K

2

CAD NOTE:FOR PIN V23

1

C

C74

1U_0402_6.3V6K

2

+1

.0VALW_UNCORE_G3

1

2

1

2

UC1H

S

VID_V1P0_S3_V32 GA_V1P0_S3_BJ6

V D

RAM_V1P0_S0IX_AD35 DRAM_V1P0_S0IX_AF35 D

RAM_V1P0_S0IX_AF36

RAM_V1P0_S0IX_AA36

D D

RAM_V1P0_S0IX_AJ36

RAM_V1P0_S0IX_AK35

D D

RAM_V1P0_S0IX_AK36 D

RAM_V1P0_S0IX_Y35 DRAM_V1P0_S0IX_Y36

DI_V1P0_S0IX_AK19

D

DI_V1P0_S0IX_AK21

D D

DI_V1P0_S0IX_AJ18 DDI_V1P0_S0IX_AM16 U

NCORE_V1P0_G3_U22

NCORE_V1P0_G3_V22

U V

IS_V1P0_S0IX_AN29 VIS_V1P0_S0IX_AN30 U

NCORE_V1P0_S3_AF16

NCORE_V1P0_S3_AF18

U U

NCORE_V1P0_S3_Y18

NCORE_V1P0_S3_G1

U P

CIE_V1P0_S3_AM21 P

CIE_V1P0_S3_AN21

CIE_GBE_SATA_V1P0_S3_AN18

P

ATA_V1P0_S3_AN19

S C

ORE_V1P05_S3_AA33 UNCORE_V1P0_S0IX_AF21 U

NCORE_V1P0_S0IX_AG21

IS_V1P0_S0IX_V24

V V

IS_V1P0_S0IX_Y22 VIS_V1P0_S0IX_Y24 U

SB_V1P0_S3_M14

SB_V1P0_S3_U18

U U

SB_V1P0_S3_U19

PIO_V1P0_S3_AN25

G U

SB3_V1P0_G3_Y19 U

SB3_V1P0_G3_C3 UNCORE_V1P0_G3_C5

NCORE_V1P0_G3_B6

U

ORE_V1P0_S3_AC32

C C

ORE_V1P0_S3_Y32 UNCORE_V1P35_S0IX_F4_U36 U

NCORE_V1P35_S0IX_F5_AA25

NCORE_V1P35_S0IX_F2_AG32

U U

NCORE_V1P35_S0IX_F3_V36 VGA_V1P35_S3_F1_BD1 U

NCORE_V1P35_S0IX_F6

NCORE_V1P35_S0IX_F1_AG19

U I

CLK_V1P35_S3_F1_AJ19

I

CLK_V1P35_S3_F2 VSSA_AN16

SB_VSSA_U16

U

BAY-TRAIL-M-SOC_FCBGA1170

REV = 1.15

REV = 1.15 @

@

CAD NOTE:FOR PINS AK21

1

C

C53

1U_0402_6.3V6K

2

CAD NOTE:FOR PIN AK18 AM18

1

C

C75

1U_0402_6.3V6K

CD@

2

CAD NOTE:FOR PIN V18

C

C86

1U_0402_6.3V6K

CAD NOTE:FOR

PIN AD36

PIN AA25

1

C92

C

1U_0402_6.3V6K

CD@

2

CAD NOTE:FOR

PIN U36

PIN AG32

1

C

C88

1U_0402_6.3V6K

CD@

2

CD@

+1.0VALW_UNCORE_G3 +1.0VALW_UNCORE_G3

CORE_V1P05_S3_AC32 CORE_V1P05_

+1

C102

C93

UNCORE_V1P0_S0IX_AN30 UNCORE_V1P0_S0IX_AN29

UNCORE_V1P0_S0IX_V24 UNCORE_V1P0_S0IX_Y22 UNCORE_V1P0_S0IX_Y24

S3_Y32

+1

.0VS_SOC

R

C300 0_0402_5%

+1.35VS_SOC

RC301 0_0603_5%

+1

.35VS_SOC_VGA

RC974 0_0603_5%RC974 0_0603_5%

.35VS_SOC

R

C302 0_0402_5%

CAD NOTE:FOR PIN AG19

1

C94

C

C 1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

2

?

? VLV_M_D

VLV_M_D

1 2

CAD NOTE:FOR PIN AF19

1

C

1U_0402_6.3V6K

2

4

D

RAM_V1P35_S0IX_F1_AD36

DA_LPE_V1P5V1P8_S3_AM32

H

U

NCORE_V1P8_S3_AM30 UNCORE_V1P8_S3_AN32 L

PC_V1P8V3P3_S3_AM27

NCORE_V1P8_G3_U24

U

SB_V3P3_G3_N18 SB_V3P3_G3_P18

U

NCORE_V1P8_S3_U38

V

GA_V3P3_S3_AN24 PCU_V1P8_G3_V25

CU_V3P3_G3_N22

P

D3_V1P8V3P3_S3_AN27

S

U

SB_HSIC_V1P2_G3_V18

NCORE_V1P8_G3_AA18

U

R

USB_V1P8_G3_N20

P

MU_V1P8_G3_U25

ORE_V1P05_S3_AF33

C C

ORE_V1P05_S3_AG33 ORE_V1P05_S3_AG35

C

ORE_V1P05_S3_U33

C

ORE_V1P05_S3_U35

CORE_V1P05_S3_V33

V

SS_BE53_BE53 V

V

SS_BG53_BG53

V VSS_BH2_BH2

SS_BH52_BH52

V

SS_BH53_BH53

V

SS_BJ49_BJ49

V V

SS_BJ51_BJ51

VSS_BJ52_BJ52

V

R

P

CIE_V1P0_S3_AK18

PCIE_V1P0_S3_AM18

@

CAD NOTE:FOR PIN BD1

CAD NOTE:FOR PIN AG18

C95

V

SS_AD16

VSS_AD18

TC_VCC_P22

SS_A3_A3

V

SS_A49_A49

V

SS_A5_A5 VSS_A51_A51 V

SS_A52_A52

SS_A6_A6

V V

SS_B2_B2 VSS_B52_B52 V

SS_B53_B53

SS_BE1_BE1 SS_BG1_BG1 SS_BH1_BH1

V

SS_BJ2_BJ2 VSS_BJ3_BJ3 V

SS_BJ5_BJ5

V

SS_C1_C1

SS_C53_C53

V

SS_E1_E1

SS_E53_E53

V ESERVED_F1

U_0402_6.3V6K

U_0402_6.3V6K 1

1

?8 OF 13

1

CC48

2

1

C101

C101 C

C

2

CLK_V1P35_S3

I

1

C

C111

1U_0402_6.3V6K

2

+1

AD36 AM32 AM30 AN32 AM27 U24 N18 P18 U38 AN24 V25 N22 AN27 AD16 AD18 V18 AA18 P22 N20 U25 AF33 AG33 AG35 U33 U35 V33 A3 A49 A5 A51 A52 A6 B2 B52 B53 BE1 BE53 BG1 BG53 BH1 BH2 BH52 BH53 BJ2 BJ3 BJ5 BJ49 BJ51 BJ52 C1 C53 E1 E53 F1 AK18 AM18

1U_0402_6.3V6K

.35VS_SOC

V

GA_V1P0_S3

C

AD NOTE:FOR

PIN BJ6

1

C115

C115 C

C

2

@

10U_0603_6.3V6M

+1

VSS_AD VSS_AD +1.0VALW_UNCORE_G3

+1

VGA_V1P35_S3

CLK_V1P35_S3

I

.5VS_HDA_S3

.0VS_SOC

.8VS_UNCORE_S3

+1

+3.3VS_SOC

+1

.05VS

1

C114

C

C 10U_0603_6.3V6M

10U_0603_6.3V6M

2

.5VS

+1

1 2

R

C136 0_0603_5%

1 2

C137 0_0603_5%

R

+1

.8VALW

1 2

RC138 0_0603_5%RC138 0_0603_5%

SS_AD

V

0531

删除

1.2VS预留 o use

BAY TRAIL n

0603

VALW_SOC

+3

.8VALW_SOC

.5VS_HDA_S3

+1

1

2

+1.8VS_UNCORE_S3+1.8VS

CAD NOTE:FOR PIN U38

1

C

C76

1U_0402_6.3V6K

2

+1

.8VALW_SOC

1 2

R

C141 0_0603_5%

.3VALW_USB/PCU_G3

+3

1.0 A

1

CC54

CC54 1U_0402_6.3V6K

1U_0402_6.3V6K

2

10 mA

C65

C

1U_0402_6.3V6K

10 mA

65 mA

1

C

C80

1U_0402_6.3V6K

CD@

2

V

CCRTC

1

2

.3VALW_USB/PCU_G3

+3

3

CAD NOTE:FOR PIN AM30 AN32

1

C

C77

1U_0402_6.3V6K

@

2

1

2

C

C112

.1U_0402_10V6-K

1

C96

C

C 1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

2

.05VS

+1

1

CC55

CC55 1U_0402_6.3V6K

1U_0402_6.3V6K

2

CAD NOTE:FOR PIN AA18

C

C81

1U_0402_6.3V6K

50 mA

VSS_AD

0603

VS

+3

1 2

RC135 0_0603_5%RC135 0_0603_5%

CAD NOTE:FOR PIN AM30 AN32

1

C

C78

1U_0402_6.3V6K

2

CAD NOTE:FOR PIN N18 P18

1

C97

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

+1

.0VALW_UNCORE_G3

.3VS_SOC

+3

1

CC116

CC116 10U_0603_6.3V6M

10U_0603_6.3V6M

CD@

2

CAD NOTE:FOR PIN AM30 AN32

1

C

C79

1U_0402_6.3V6K

@

2

8 mA+25 mA

AD NOTE:FOR

C PIN AM27

1

CC66

CC66 1U_0402_6.3V6K

1U_0402_6.3V6K

2

0531 Change

CCRTC

V

to UNCORE_V1P0_G3

2

1

T

itle

ecurity Classification

S

I

ssued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

013/03/26

C Future Center Secret Data

L

D

eciphered Date

2013/02/01

itle

OC (Power2)

S

ize Document Number Rev

D

D Date: Sheetof

Date: Sheetof

onday, December 23, 2013

M

1

ACLU9

0 59

1

.2

0

5

UC1I

A11

SS1

V

A15

SS2

V

A19

SS3

V

A23

SS4

V

A27

SS5

V

A31

SS6

V

A35

SS7

V

A39

SS8

V

D D

C C

B B

A43

SS9

V

A47

SS10

V

AA1

SS11

V

AA16

SS12

V

AA19

SS13

V

AA21

SS14

V

AA3

SS15

V

AA32

SS16

V

AA35

SS17

V

AA38

SS18

V

AA53

SS19

V

AB10

SS20

V

AB4

SS21

V

AB41

SS22

V

AB45

SS23

V

AB47

SS24

V

AB48

SS25

V

AB50

SS26

V

AB51

SS27

V

AB6

SS28

V

AC16

SS29

V

AC18

SS30

V

AC19

SS31

V

AC21

SS32

V

AC25

SS33

V

AC33

SS34

V

AC35

SS35

V

BAY-TRAIL-M-SOC_FCBGA1170

@

UC1L

BF30

SS211

V

BF36

SS212

V

BF4

SS213

V

BG31

SS214

V

BG34

SS215

V

BG39

SS216

V

BG42

SS217

V

BG45

SS218

V

BG49

SS219

V

BJ11

SS220

V

BJ15

V

SS221

BJ19

V

SS222

BJ23

SS223

V

BJ27

SS224

V

BJ31

V

SS225

BJ35

SS226

V

BJ39

SS227

V

BJ43

SS228

V

BJ47

V

SS229

BJ7

SS230

V

C14

SS231

V

C31

SS232

V

C34

V

SS233

C39

SS234

V

C42

SS235

V

C45

SS236

V

C49

V

SS237

D12

SS238

V

D16

SS239

V

D24

V

SS240

D30

V

SS241

D36

SS242

V

D38

SS243

V

E19

SS244

V

E35

SS245

V

BAY-TRAIL-M-SOC_FCBGA1170

@

SS36

V

SS37

V

SS38

V

SS39

V

SS40

V

SS41

V

SS42

V

SS43

V

SS44

V

SS45

V

SS46

V

SS47

V

SS48

V

SS49

V

SS50

V

SS51

V

SS52

V

SS53

V

SS54

V

SS55

V

SS56

V

SS57

V

SS58

V

SS59

V

SS60

V

SS61

V

SS62

V

SS63

V

SS64

V

SS65

V

SS66

V

SS67

V

SS68

V

SS69

V

SS70

V

SS246

V

SS247

V

SS248

V

SS249

V

SS250

V

SS251

V

SS252

V

SS253

V

SS254

V

SS255

V V

SS256

V

SS257 SS258

V

SS259

V V

SS260 SS261

V

SS262

V

SS263

V V

SS264 SS265

V

SS266

V

SS267

V V

SS268 SS269

V

SS270

V

SS271

V V

SS272 SS273

V

SS274

V V

SS275

V

SS276 SS277

V

SS278

V

SS279

V

SS280

V

?

LV_M_D

V

AC36 AC38 AD19 AD21 AD25 AD32 AD33 AD47 AD7 AE1 AE11 AE12 AE14 AE3 AE4 AE40 AE42 AE43 AE45 AE46 AE48 AE50 AE51 AE53 AE6 AE8 AE9 AF10 AF12 AF25 AF32 AF47 AG16 AG25 AG36

?

? V

V

E8 F19 F2 F24 F27 F30 F35 F5 F7 G10 G20 G22 G26 G28 G32 G34 G42 H19 H27 H35 J1 J16 J19 J22 J27 J32 J35 J40 J53 K14 K22 K32 K36 K4 K50

?REV = 1.15 9 OF 13

LV_M_D

4

UC1J

AG38

SS71

V

AH4

SS72

V

AH41

SS73

V

AH45

SS74

V

AH7

SS75

V

AH9

SS76

V

AJ1

SS77

V

AJ16

SS78

V

AJ21

SS79

V

AJ25

SS80

V

AJ27

SS81

V

AJ29

SS82

V

AJ3

SS83

V

AJ30

SS84

V

AJ32

SS85

V

AJ33

SS86

V

AJ35

SS87

V

AJ38

SS88

V

AJ53

SS89

V

AK10

SS90

V

AK14

SS91

V

AK16

SS92

V

AK33

SS93

V

AK41

SS94

V

AK44

SS95

V

AM12

SS96

V

AM19

SS97

V

AM24

SS98

V

AM25

SS99

V

AM29

SS100

V

AM33

SS101

V

AM35

SS102

V

AM36

SS103

V

AM40

SS104

V

M28

SS105

V

BAY-TRAIL-M-SOC_FCBGA1170

@

?12 OF 13REV = 1.15

SS106

V

SS107

V

SS108

V

SS109

V

SS110

V

SS111

V

SS112

V

SS113

V

SS114

V

SS115

V

SS116

V

SS117

V

SS118

V

SS119

V

SS120

V

SS121

V

SS122

V

SS123

V

SS124

V

SS125

V

SS126

V

SS127

V

SS128

V

SS129

V

SS130

V

SS131

V

SS132

V

SS133

V

SS134

V

SS135

V

SS136

V

SS137

V

SS138

V

SS139

V

SS140

V

?

LV_M_D

V

AH47 AH48 AH50 AH51 AH6 AM44 AM51 AM7 AN1 AN11 AN12 AN14 AN22 AN3 AN33 AN35 AN36 AN38 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN5 AN51 AN53 AN6 AN8 AN9 AP40 AT12 AT16 AT19

3

UC1K

AT24

SS141

V

AT27

SS142

V

AT30

SS143

V

AT35

SS144

V

AT38

SS145

V

AT4

SS146

V

AT47

SS147

V

AT52

SS148

V

AU1

SS149

V

AU24

SS150

V

AU3

SS151

V

AU30

SS152

V

AU38

SS153

V

AU51

SS154

V

AV12

SS155

V

AV13

SS156

V

AV14

SS157

V

AV18

SS158

V

AV19

SS159

V

AV24

SS160

V

AV27

SS161

V

AV30

SS162

V

AV35

SS163

V

AV38

SS164

V

AV47

SS165

V

AV51

SS166

V

AV7

SS167

V

AW13

SS168

V

AW19

SS169

V

AW27

SS170

V

AW3

SS171

V

AW35

SS172

V

AY10

SS173

V

AY22

SS174

V

AY32

SS175

V

BAY-TRAIL-M-SOC_FCBGA1170

?REV = 1.15 10 OF 13

BAY-TRAIL-M-SOC_FCBGA1170

@

SS176

V

SS177

V

SS178

V

SS179

V

SS180

V

SS181

V

SS182

V

SS183

V

SS184

V

SS185

V

SS186

V

SS187

V

SS188

V

SS189

V

SS190

V

SS191

V

SS192

V

SS193

V

SS194

V

SS195

V

SS196

V

SS197

V

SS198

V

SS199

V

SS200

V

SS201

V

SS202

V

SS203

V

SS204

V

SS205

V

SS206

V

SS207

V

SS208

V

SS209

V

SS210

V

UC1M

K9

V

L13

V

L19

V

L27

V

L35

V

M19

V

M26

V

M27

V

M34

V

M35

V

M38

V

M47

V

M51

V

N1

V

N16

V

N38

V

N51

V

P13

V

P16

V

P19

V

P20

V

P24

V

P32

V

P35

V

P38

V

P4

V

P47

V

P52

V

P9

V

T40

V

U1

V

U11

V

U12

V

U14

V

U21

V

BAY-TRAIL-M-SOC_FCBGA1170

@

SS281 SS282 SS283 SS284 SS285 SS286 SS287 SS288 SS289 SS290 SS291 SS292 SS293 SS294 SS295 SS296 SS297 SS298 SS299 SS300 SS301 SS302 SS303 SS304 SS305 SS306 SS307 SS308 SS309 SS310 SS311 SS312 SS313 SS314 SS315

2

?

LV_M_D

V

AY36 AY4 AY50 AY9 BA14 BA19 BA22 BA27 BA32 BA35 BA40 BA53 BB19 BB27 BB35 BC20 BC22 BC26 BC28 BC32 BC34 BC42 BD19 BD24 BD27 BD30 BD35 BE19 BE2 BE35 BE8 BF12 BF16 BF24 BF38

11 OF 13 ?REV = 1.15

?

? VLV_M_D

VLV_M_D

U3

SS316

V

U30

SS317

V

U32

SS318

V

U40

SS319

V

U42

SS320

V

U43

SS321

V

U45

SS322

V

U46

SS323

V

U48

V

SS324

U49

V

SS325

U5

SS326

V

U51

SS327

V

U53

V

SS328

U6

SS329

V

U8

SS330

V

U9

SS331

V

V12

V

SS332

V16

SS333

V

V19

SS334

V

V21

SS335

V

V35

V

SS336

V40

SS337

V

V44

SS338

V

V51

SS339

V

V7

V

SS340

Y10

SS341

V

Y14

SS342

V

Y16

V

SS343

Y21

V

SS344

Y25

SS345

V

Y33

SS346

V

Y41

SS347

V

Y44

SS348

V

Y7

SS349

V

Y9

SS350

V

13 OF 13 ?REV = 1.15

1

A A

T

itle

ecurity Classification

S

ssued Date

I

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAI NS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

3

013/03/26

2

C Future Center Secret Data

L

eciphered Date

D

2

2013/02/01

itle

S

OC (VSS)

ize Document Number Rev

S

C

Date: Sheet

ACLU9

M

onday, December 23, 2013

1

o

f

1 59

f

1 59

f

1

1 59

.2

0

5

D D

H

ardware STRAPS

(Follow up CRB& VIENNA)

+

1.8VS

4

G

PIO_NC13 MDSI_DDCDATA(Checklist repuest 10K pull down) GPIO_S0_SC_56 GPIO_S0_SC_56(Internal Pull-up) I2S_2_FS GPIO_S0_SC[063] (Internal Pull-up) I2S_2_TXD GPIO_S0_SC[065](Internal Pull-up) PCH_HDMI_DDC_DAT DDI1_DDCDATA DDI0_DDCDATA DDI0_DDCDATA

3

2

G

PIO_S0_SC_56: A16 Top Swap 0=Top address bit is unchanged 1=Top address bit is inverted

1

GPIO_S0_SC[063] Multiplexed with Hardware Straps Pin LPE_I2S2_FRM

R

C936

2.2K_0402_5%

C C

1 2

R 10K_0402_1%

10K_0402_1%

1 2

C938

R

R 10K_0402_1%

10K_0402_1%

@

1 2

R

C45

10K_0402_1%

@

1 2

R

C46

C47

10K_0402_1%

@

1 2

PIO_NC13

G GPIO_S0_SC_56 I

2S_2_FS 2S_2_TXD

I

DI1_DDCDATA

D

PIO_NC13 {4}

G

PIO_S0_SC_56 {8}

G

2S_2_FS {6}

I

2S_2_TXD {6}

I

DI1_DDCDATA {4}

D

BIOS Boot selection 0=LPC 1=SPI

G

PIO_S0_SC[065] Multiplexed with LPE_I2S2_DATAOUT Security Flash Descriptors 0=Override 1=Normal Operation

DDI0_DDCDATA: DDI0 strap

C963

R

R 10K_0402_1%

10K_0402_1%

@

1 2

B B

C941

R

R 10K_0402_1%

10K_0402_1%

@

1 2

C943

R

2.2K_0402_5%

@

1 2

C942

R

R 10K_0402_1%

10K_0402_1%

1 2

M

JUMP_43X39

I

2S_2_TXD

R

4.7K_0402_5%

1 2

1

E2

@

E2

@

1

13

D

2

S

0606

C961

C202

Q

2

G

2N7002KW_SOT323-3

C962

R

1 2

0_0402_5%

CH_ME_PROTECT {44}

P

0=DDI0 not detected 1=DDI0 detected DDI1_DDCDATA: DDI1 strap 0=DDI1 not detected 1=DDI1 detected

A A

T

itle

S

ecurity Classification

I

ssued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

013/08/08

L

C Future Center Secret Data

D

eciphered Date

2

2013/08/05

itle

OC (STRAPS & OTHERS)

S

ize Document Number Rev

ustom

C

M

Date: Sheet

ACLU9

onday, December 23, 2013

f

12 59

f

12 59

f

12 59

o

1

o

.2

0

5

D D

C C

4

3

2

1

B B

A A

T

itle

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

013/08/08

L

C Future Center Secret Data

D

eciphered Date

2

2013/08/05

itle

CP (OTHER)

M

ize Document Number Rev

S

ustom

C

M

Date: Sheet

ACLU9

onday, December 23, 2013

13 59

o

f

1

f

.2

0

5

D

DR Mapping table

D

DRA_DQ0---DQ0

D DDRA_DQ1---DQ1 DDRA_DQ6---DQ2 DDRA_DQ3---DQ3 DDRA_DQ4---DQ4 DDRA_DQ5---DQ5 DDRA_DQ7---DQ6

D D

DDRA_DQ2---DQ7 DDRA_DQ9----DQ8 DDRA_DQ13---DQ9 DDRA_DQ10---DQ10 DDRA_DQ11---DQ11 DDRA_DQ12---DQ12 DDRA_DQ8----DQ13 DDRA_DQ15---DQ14 DDRA_DQ14---DQ15 DDRA_DQ16---DQ16 DDRA_DQ17---DQ17 DDRA_DQ18---DQ18 DDRA_DQ19---DQ19 DDRA_DQ20---DQ20 DDRA_DQ21---DQ21 DDRA_DQ23---DQ22 DDRA_DQ22---DQ23 DDRA_DQ28---DQ24 DDRA_DQ25---DQ25 DDRA_DQ26---DQ26 DDRA_DQ27---DQ27 DDRA_DQ24---DQ28 DDRA_DQ29---DQ29 DDRA_DQ30---DQ30 DDRA_DQ31---DQ31 DDRA_DQ32---DQ32

C C

DDRA_DQ36---DQ33 DDRA_DQ35---DQ34 DDRA_DQ34---DQ35 DDRA_DQ37---DQ36 DDRA_DQ33---DQ37 DDRA_DQ38---DQ38 DDRA_DQ39---DQ39 DDRA_DQ40---DQ40 DDRA_DQ45---DQ41 DDRA_DQ42---DQ42 DDRA_DQ43---DQ43 DDRA_DQ44---DQ44 DDRA_DQ41---DQ45 DDRA_DQ47---DQ46 DDRA_DQ46---DQ47 DDRA_DQ48---DQ48 DDRA_DQ49---DQ49 DDRA_DQ50---DQ50 DDRA_DQ51---DQ51 DDRA_DQ52---DQ52 DDRA_DQ53---DQ53 DDRA_DQ55---DQ54 DDRA_DQ54---DQ55 DDRA_DQ56---DQ56 DDRA_DQ61---DQ57 DDRA_DQ58---DQ58

B B

DDRA_DQ59---DQ59 DDRA_DQ60---DQ60 DDRA_DQ57---DQ61 DDRA_DQ63---DQ62 DDRA_DQ62---DQ63

D10 0_0402_5%

R

1 2 1 2

R

D11 0_0402_5%

A A

2.2U_0603_6.3V6K

D

DR_DQ

.

1U_0402_10V6-K

D

DRA_DQ0 DRA_DQ1

D

1

C

D3

DRA_CKE0{5}

D

DRA_BS2#{5}

DRA_CLK0{5}

D

DRA_CLK0#{5}

D

DRA_BS0#{5} DRA_WE#{5}

D

DRA_CAS#{5}

D

DRA_CS1#{5}

S

A0

S

A1

+

3VS

C

1

C

D27

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

@

5

D

DRA_DM0

2

D

DRA_DQ6 DRA_DQ3

D D

DRA_DQ9

D

DRA_DQ13 DRA_DQS#1

D D

DRA_DQS1

D

DRA_DQ10

D

DRA_DQ11

D

DRA_DQ16

DDRA_DQ17 D

DRA_DQS#2

D

DRA_DQS2

DDRA_DQ18 D

DRA_DQ19

D

DRA_DQ28

D

DRA_DQ25

D

DRA_DM3 DRA_DQ26

D

DRA_DQ27

D

DRA_CKE0

DRA_BS2#

D D

DRA_MA12

D

DRA_MA9

DDRA_MA8

DRA_MA5

D

DRA_MA3

D

DRA_MA1

D D

DRA_CLK0

DDRA_CLK0#

DRA_MA10

D

DRA_BS0#

D D

DRA_WE#

D

DRA_CAS# DRA_MA13

D

DRA_CS1#

D

DRA_DQ32

D

DRA_DQ36 DRA_DQS#4

D

DRA_DQS4

D

DRA_DQ35

D D

DRA_DQ34

D

DRA_DQ40 DRA_DQ45

D

DRA_DM5

D

DRA_DQ42

D D

DRA_DQ43 DRA_DQ48

D

DRA_DQ49

D

DRA_DQS#6

D

DRA_DQS6

D D

DRA_DQ50

D

DRA_DQ51 DRA_DQ56

D

DRA_DQ61

D

DRA_DM7

D D

DRA_DQ58 DRA_DQ59

D

A0

S

A1

S

D28

DR3 SO-DIMM A

+

1.35V

A@1.5V

3

DDR1

J

1

REF_DQ

V

3

SS_1

V

5

Q0

D

7

Q1

D

9

SS_3

V

11

M0

D

13

SS_5

V

15

Q2

D

17

Q3

D

19

SS_7

V

21

Q8

D

23

Q9

D

25

SS_9

V

27

QS1#

D

29

QS1

D

31

SS_11

V

33

Q10

D

35

Q11

D

37

SS_13

V

39

Q16

D

41

Q17

D

43

SS_15

V

45

QS2#

D

47

QS2

D

49

SS_17

V

51

Q18

D

53

Q19

D

55

SS_19

V

57

Q24

D

59

Q25

D

61

SS_21

V

63

M3

D

65

SS_23

V

67

Q26

D

69

D

Q27

71

SS_25

V

73

KE0

C

75

DD_1

V

77

N

C_1

79

B

A2

81

DD_3

V

83

12/BC#

A

85

9

A

87

DD_5

V

89

8

A

91

A

5

93

V

DD_7

95

A

3

97

1

A

99

DD_9

V

101

K0

C

103

K0#

C

105

V

DD_11

107

A

10/AP

109

B

A0

111

DD_13

V

113

E#

W

115

AS#

C

117

V

DD_15

119

A

13

121

1#

S

123

DD_17

V

125

EST

T

127

SS_27

V

129

Q32

D

131

D

Q33

133

V

SS_29

135

QS4#

D

137

QS4

D

139

SS_31

V

141

Q34

D

143

Q35

D

145

V

SS_33

147

Q40

D

149

Q41

D

151

SS_36

V

153

M5

D

155

SS_37

V

157

D

Q42

159

D

Q43

161

V

SS_39

163

D

Q48

165

Q49

D

167

SS_41

V

169

QS6#

D

171

D

QS6

173

V

SS_43

175

D

Q50

177

Q51

D

179

SS_45

V

181

Q56

D

183

Q57

D

185

V

SS_47

187

D

M7

189

V

SS_49

191

Q58

D

193

Q59

D

195

SS_51

V

197

S

A0

199

V

DDSPD

201

S

A1

203

V

TT_1

205

ND1

G

207

OSS1

B

LCN_DAN06-K4406-0103

ME@

V

R

V

V V

V

V REF_CA

V

V V

V

V V

V

E

V

QS0#

D

V

D D

SS_10

ESET#

SS_12

D D

SS_14

D D

SS_16 SS_18

D D

SS_20

D D

SS_22

QS3#

D

SS_24

D D

SS_26

C DD_2

V

DD_4

V

DD_6

V

DD_8

DD_10

DD_12

R

DD_14

O

DD_16

O N

DD_18

SS_28

D D

SS_30 SS_32

D D

SS_34

D D

SS_35

QS5#

D

SS_38

D D

SS_40

D D

SS_42 SS_44

D D

SS_46

D D

SS_48

D

QS7#

D

SS_50

D D

SS_52

VENT#

V

G

OSS2

B

C

4

SS_2

D D

SS_4

QS0

SS_6

D D

SS_8

D

QS3

C

D

QS5

D

QS7

S S

TT_2

ND2

4

3

+

1.35V

or RF request

2 4

DRA_DQ4

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

D D

D

D D

D DDRA_DQ21

D D

DDRA_DQ22 DDRA_DQ24

D DDRA_DQS#3

D D

D

D D

D DDRA_MA6

D D

DDRA_CLK1# D

D D

.65A@0 .75V

0

D D

DRA_DQ5 DRA_DQS#0

DRA_DQS0 DRA_DQ7

DRA_DQ2 DRA_DQ12

DRA_DQ8 DRA_DM1

DRA_DQ15 DRA_DQ14

DRA_DQ20

DRA_DM2 DRA_DQ23

DRA_DQ29

DRA_DQS3 DRA_DQ30

DRA_DQ31

DRA_CKE1 DRA_MA15

DRA_MA14 DRA_MA11

DRA_MA7

DRA_MA4 DRA_MA2

DRA_MA0 DRA_CLK1

DRA_BS1# DRA_RAS#

DRA_CS0# DRA_ODT0

DRA_ODT1

DRA_DQ37 DRA_DQ33

DRA_DM4 DRA_DQ38

DRA_DQ39 DRA_DQ44

DRA_DQ41 DRA_DQS#5

DRA_DQS5 DRA_DQ47

DRA_DQ46 DRA_DQ52

DRA_DQ53 DRA_DM6 DRA_DQ55

DRA_DQ54 DRA_DQ60

DRA_DQ57 DRA_DQS#7

DRA_DQS7 DRA_DQ63

DRA_DQ62

Q4 Q5

Q6 Q7

Q12 Q13

M1

Q14 Q15

Q20 Q21

M2

Q22 Q23

Q28 Q29

Q30 Q31

KE1 A

15

A

14 11

A

7

A

6

A A

4

A

2 0

A K1

K1# B

A1

AS#

0#

S DT0

DT1 C_2

Q36 Q37

M4

Q38 Q39

Q44 Q45

Q46 Q47

Q52 Q53

M6

Q54 Q55

Q60 Q61

Q62 Q63

DA

CL

F

@

D

D D

D

.1U_0402_10V6-K

1

2

S

MB_DATA_S3 {8,40} MB_CLK_S3 {8,40}

S

0.675VS

+

DRA_CKE1 {5}

DRA_CLK1 {5} DRA_CLK1# {5}

DRA_BS1# {5} DRA_RAS# {5}

DRA_CS0# {5} DRA_ODT0 {5}

DRA_ODT1 {5}

DR_CA

33P_0402_50V8J

C

1

D4

@

2

DDRA_DRAMRST# {5}

C

C D21

D21

ecurity Classification

S

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

33P_0402_50V8J

C

1

D5

D6

@

2

Layout Note: Place near DIMM

1.35V

+

1

1 0U_0603_6.3V6M

0U_0603_6.3V6M

D7

C

1

2

ssued Date

I

3

OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4

1

0U_0603_6.3V6M

D8

C

+

1.35V

0U_0603_6.3V6M

D10

D9

C

1

2

D68

C

@

013/08/08

2

1

2

+

.

1U_0402_10V6-K

D69

C

1

2

@

1

0U_0603_6.3V6M

D11

C

1

2

1.35V

12

R

D1

4.7K_0402_1%

R

D5

1 2

0_0402_5%

12

D2

R

4.7K_0402_1%

.

1U_0402_10V6-K

D66

C

1

2

@

L

C Future Center Secret Data

eciphered Date

D

DRA_DQ[0..63] {5}

D

DRA_DQS[0..7] {5} DRA_DQS#[0..7] {5}

D

DRA_MA[0..15] {5}

D

DRA_DM[7:0] {5}

1

1 0U_0603_6.3V6M

0U_0603_6.3V6M

D12

1

2

D

DR_DQ

.

1U_0402_10V6-K

D67

1

2

@

2

1

1 0U_0603_6.3V6M

0U_0603_6.3V6M

D13

D14

C

1

2

@

ayout Note:

L Place near DIMM

2013/08/05

2

.

1

1 0U_0603_6.3V6M

0U_0603_6.3V6M

.

.1U_0402_10V6-K

1U_0402_10V6-K

D15

D16

C

1

2

1.35V

+

12

+

c

ost down bom to change 0.1uF

C

1

2

R

D3

4.7K_0402_1%

R

D6

1 2

0_0402_5%

D4

R

4.7K_0402_1%

0.675VS

C

D24

1

C

D23

1U_0402_6.3V6K

2

@

itle

T

D

DRIII SO-DIMM A

ize Document Number Rev

S

C

ustom

M

Date: Sheet

.

1U_0402_10V6-K

D17

D18

C

1

2

D

DR_CA

.

.1U_0402_10V6-K

1U_0402_10V6-K

C

D25

1

2

@

onday, December 23, 2013

1

.1U_0402_10V6-K

1

2

C

D26

1

2

@

ACLU9

1

@

CD64

10U_0603_6.3V6M

.

1U_0402_10V6-K

1

2

For RF request

14 59

1

+

C

C 220U_6.3V_M

220U_6.3V_M

2

10U_0603_6.3V6M

@

o

D19

C

C D65

D65

33P_0402_50V8J

C

1

D70

2

@

0

.2

f

5

D D

C C

4

3

2

1

B B

A A

itle

T

ecurity Classification

S

ssued Date

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

013/08/08

2

L

C Future Center Secret Data

eciphered Date

D

2

2013/08/05

T

D

DRIII SO-DIMM B

ize Document Number Rev

S

C

ustom

M

onday, December 23, 2013

Date: Sheet

onday, December 23, 2013

ACLU9

1

o

f

15 59

f

15 59

f

15 59

0

.2

5

1

U

UB_USB20_N0

H

UB_USB20_P0

H

UB_USB20_N1

H

UB_USB20_P1

H

D D

AVDD

+

UB_USB20_N2

H

UB_USB20_P2

H

REF_HUB

R

AVDD

+

TAL12_IN

X

TAL12_OUT

X

UB_USB20_N3

H

UB_USB20_P3

H

AVDD

+

C C

B B

A A

1

M0

D

2

P0

D

3

M1

D

4

P1

D

5

VDD

A

6

M2

D

7

P2

D

8

REF

R

9

VDD1

A

10

1

X

11

2

X

12

M3

D

13

P3

D

14

A

VDD2

29

P

AD

GL850G-OHY31_QFN28_5X5

SB20_N3{8}

U

SB20_P3{8}

U

GL850G

FN28

Q

WREN1#/SDA

P

VCUR1#/SMC

O

VCUR2#/SMD

O

SB20_N3

U

SB20_P3

P

VCUR3#

O

VCUR4#

O

EST/SCL

T

ESET#

R

28

33

V

27

5

V

26 25 24 23

GANG

22

SELF

21

VDD

D

20 19 18 17 16

P4

D

15

D

M4

1 2

VDD

+

5

V

DA_HUB

S

UB_USB_OC1#

H

GANG

P

SELF

P

EST/SCL

T

ESET#

R

UB_USB20_P4

H

UB_USB20_N4

H

1 2

H4 0_0402_5%

R

R C

M1

@CM1

@

DLP11SN900HL2L_4P

1 2

H8 0_0402_5%

R

UB_USB20_N1 {33}

H

UB_USB20_P1 {33}

H

UB_USB20_N2 {45}

H

UB_USB20_P2 {45}

H

UB_USB20_N3 {40}

H H

UB_USB20_P3 {40}

H

UB_USB20_N4 {33} UB_USB20_P4 {33}

H

4

1

P6 @TP6 @

T

B1

L

1 2

UPB100505T-121Y-N_2P

1

P7 @TP7 @

T

UB_USB20_N0

H

34

H

UB_USB20_P0

Camera Card reader BT

Touch panel

VDD

+

1

H1

C

C .1U_0402_10V6-K

.1U_0402_10V6-K

2

805 change

0

20P_0402_50V8

3

3VS

+

3VALW_SOC

604

R

+

H2 close to PIN28

C

5VALW

+

12

H6

@

ESET#

C

1

H11

2

0

12

H3

@

H3

@

R

10M_0402_5%

Y

H1

TAL12_IN X

1

H9

C

2

H1

1

SC1

O

2

ND1

G

12MHZ_10PF_7V12000008

A

s close to GL850G

3

SC2

O

4

ND2

G

TAL12_OUT X

1

H10

C

C 20P_0402_50V8

20P_0402_50V8

2

0604

10K_0402_5%

2

1 2

H20 0_0603_5%

R

1 2

H1 0_0603_5%@RH1 0_0603_5%@

R

* External regulator mode

*

Internal regulator mode

L

B2

0605

AVDD

+

1

C

H3

.1U_0402_10V6-K

2

ienna change to 619 ohm for Eye Diagram test

V

VDD

+

1 2

UPB100505T-121Y-N_2P

1

C

H2

10U_0603_6.3V6M

2

VDD

+

12

R

H7

10K_0402_5%

1U_0402_6.3V6K

47K_0402_5%

12

R

R H10

H10

@

1

5VALW

+

VDD

+

：

RH1上件，

：

RH1不上件，

AVDD

+

.1U_0402_10V6-K

C

1

H4

2

A

s close to GL850G

1 2

@

H2 0_0603_5%

R

RH2不上件

RH2上件

.1U_0402_10V6-K

C

1

H5

H6

2

5

V

1U_0402_6.3V6K

C

1

H8

H7

2

CH3 PIN5 CH4/CH5 PIN9 CH6/CH15 PIN14

H9

R

1 2

680_0402_1%

1 2

R

H11

100K_0402_5%

1 2

H12

R

10K_0402_5%

H

UB_USB_OC1#

Individual

+

VDD

Self-power

H628

R

1 2

10K_0402_5%@

VDD

+

P

R

GANG

SELF

REF_HUB

.1U_0402_10V6-K

Mode

T

itle

ecurity Classification

S

ssued Date

I

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

013/03/26

3

C Future Center Secret Data

L

D

eciphered Date

2013/02/01

2

itle

U

SB Hub GL850G-OHY31

Size Document Number Rev

ize Document Number Rev

S

B

M

onday, December 23, 2013

Date: Sheet

onday, December 23, 2013

ACLU9

1

o

f

6 59

f

6 59

f

6 59

1

.2

0

5

D D

C C

B B

4

3

2

1

A A

T

itle

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

013/08/08

L

C Future Center Secret Data

D

eciphered Date

2

2013/08/05

itle

lank

B

ize Document Number Rev

S

ustom

C

M

onday, December 23, 2013

Date: Sheet

onday, December 23, 2013

ACLU9

1

17 59

o

f

.2

0

5

15x GPIO

N

GPIO I/O ACTIVE Function Description

GPIO0

OUT

D D

GPIO1

GPIO2 GPIO3

GPIO4

GPIO5

GPIO6

GPIO7 GPIO8

GPIO9

GPIO10

UT

O

OUT OUT

OUT

IN

OUT I/O

I/O N/A

OUT

GPIO11

IN

GPIO12

OUT

C C

GPIO13

GPIO14

GPIO15

IN

GPIO16

IN

GPIO17

IN

GPIO18

IN

GPIO19

GPIO20

GPIO21

OUT GPU PCIe self-reset control

OVERT

B Enable for GC6 2.0-

F

N/A

N/A N/A

N/A

GPU power sequencing---3V3_MAIN_EN

GPU wake signal for GC6 2.0

-

N/A

System side PCIe reset Monitor

-

2.2K Pull-up

N/A

G

PU Core VDD PWM control signal-OUT

AC Power Detect Input Phase Shedding-

N/A

/A

N

N/A

N/A N/A

N/A

Active Low Thermal Catastrophic Over TemperatureOUT

4

3

P

erformance Mode P0 TDP at Tj = 102 C* (DDR3)

NVCLKMemGPU

MCLK

Products

N14X 128bit 2GB DDR3

/

2

NVVDD (1.05V) (3.3V)

(V)

TBDTBDTBD

TBDTBD

FBVDD (1.35V) (1.35V)

(W)(A)(W)(A) (W)(W)(A)

PCI ExpressFBVDDQ

(GPU+Mem)

(1.05V) (6)(1,5)(4)

TBDTBDTBDTBDTBD TBDTBDTBD TBDTBDTBD

1

I/O and PLLVDD

mA) (W)(W)(mA)

(

Other

(mA)(MHz)(W)(W)

N15x Multi-level Straps

(1

0K pull High)

hysical

P Strapping pin R

OM_SCLK ROM_SI R

OM_SO S

TRAP0 STRAP1 STRAP2 S

TRAP3 STRAP4

S

MBUS_ALT_ADDR

0

0x

9E (Default)

1

0x9C (Multi-GPU usage)

ower Rail

P

+3VGS +3VGS

3VGS

+ +3VGS +3VGS +3VGS +3VGS

3VGS

+

ogical

Logical Strapping Bit3

OR3_EXPOSED

S

DEVID_SEL

R

eserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)

Logical Strapping Bit2

SOR2_EXPOSED SOR1_EXPOSED R

AM_CFG[2]

PCIE_CFG

L Strapping Bit1

R

AM_CFG[1]RAM_CFG[3]

Logical Strapping Bit0

SOR0_EXPOSED R

AM_CFG[0]

V

GA_DEVICESMB_ALT_ADDR

Reserved(keep pull-up and pull-down footprint and not stuff by default)

15V-GM Power Sequence

N

B B

3VG_AON

+

+VGA_CORE

+1.35VGS

+1.05VS_VGA

tNVVDD >0

t

FBVDDQ >0

tPEX_VDD >0

1

. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

ther Power rail

O

+3VG_AON

T

power-off <10ms

1

.all GPU power rails should be turned off within 10ms

N15S-GT Power Sequence

+

3VG_AON

A A

+VGA_CORE

+1.05VS_VGA

+1.35VGS

t

NVVDD >0

tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

5

4

3

N15x Binary Straps

Physical Strapping pin ROM_SCLK

OM_SI

R ROM_SO STRAP0 STRAP1 STRAP2

TRAP3

S S

TRAP4

ecurity Classification

S

ssued Date

I

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAI NS CONFIDENTIAL

T

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF LC FUTU RE CENTER.

Power Rail

013/08/08

2

+ + +3VGS + +3VGS +3VGS +3VGS +3VGS

S

trap Mapping

3VGS

S

MB_ALT_ADDR

3VGS

UB_VENDOR

S VGA_DEVICE

3VGS

RAM_CFG[0] RAM_CFG[1] RAM_CFG[2]

AM_CFG[3]

R

P

CIE_MAX_SPEED

C Future Center Secret Data

L

eciphered Date

D

2013/08/05

2

T

itle

V

GA Notes List

ize Document Number Rev

S

C

M

Date: Sheet

ACLU9

onday, December 23, 2013

1

o

f

8 59

f

8 59

f

8 59

.2

0

Compal NM-A311 ACLU9, G40-30, G50-30 Schematic