Lecroy LW400A-OM3 User Manual

Appendix C

LW400-09A Digital Output Option

Introduction The LW400-09A Digital Output option provides 8-bit TTL and

ECL, digital outputs corresponding to the current value of the
channel 1 analog output. The latched digital data, which is held
for the duration of the sample clock, is available via two rear
panel mounted connectors. Digital data is available whenever
the channel 1 output is enabled.

LW400’s, with the digital output option, include a special digital
editing mode for the creation of user specified data patterns.
Byte wide data patterns or selected bits within the 8-bit wide
digital word may be programmed. Digital data patterns created
using this editor are identified as “Digital” waveforms. Digital
waveforms can be edited using the same “cut and paste” tools
available for analog waveforms. The major difference between
the two waveform types is that digital waveforms are not
processed to remove discontinuities at transitions. This also
means that Time editing functions, such as sub-sample Move,
are not useable with digital waveforms and are limited to analog
waveforms only.

Specifications
Digital outputs:

Digital output modes: ECL, TTL all available on output connectors simultaneously.
Mating output connector: SMB for ECL output

Maximum data
output clock rate: ECL, 400 MBytes/sec; TTL 100 MBytes/sec.

8 bits corresponding to the channel 1 analog output plus CLOCK
and CLOCK* (TTL only).

20 pin P/N 3M-3421-7020 for TTL output.

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Appendix C

ECL outputs: Levels:

Parameter Min Typ Max

Note: output load is 50 Ω to -2 Volts.

Timing:

Parameter Min Typ Max
Clock to
Analog Output
Setup Time * T-660 ps T-485 ps T-310 ps
Hold Time 310 ps 485 ps 660 ps
Data skew - 80 ps 250 ps

* T is clock period (i.e. 2.5 ns for 400 MHz clock)

TTL :

Levels:

Parameter Min Typ Max

V

V

V

OH

OL

OH

V

OL

-0.98 V -0.8 V -0.71V

-1.95 V -1.8 V -1.58 V

7 ns 8 ns 9.8 ns

2.00 V 2.60 V -

- 0.35 V 0.80 V

Timing:

Parameter Min Typ Max

Clock to

10 ns ­Analog
Output
Setup Time * T -5.7 ns T -0.5 ns T+3.9 ns
Hold Time -3.9 ns 0.5 ns 5.7 ns
Data skew - - 1 ns
* T is clock period (i.e. 10 ns for 100 MHz clock)

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CONNECTOR PINOUTS

Appendix C

Note1:

Note2: TTL outputs back terminated in 75 ohms

TTL Port 1 - TCLK 2 Ground

ECL Port J800 - D0 (LSB)

D7 signifies the bit which corresponds to analog signal most
significant bit (MSB), and D0 signifies the bit which corresponds
to the least significant bit (LSB).

3 - TCLK* 4 Ground
5 - D0 (LSB) 6 Ground
7 - D1 8 Ground

9 - D2 10 Ground
11 - D3 12 Ground
13 - D4 14 Ground
15 - D5 16 Ground
17 - D6 18 Ground
19 - D7 (MSB) 20 Ground

J700 - D1
J600 - D2
J500 D3

J400 - D4
J300 - D5
J200 - D6
J100 - D7 (MSB)

J900 - ECLOCK

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Appendix C

Interconnection Information:

TTL:

ECL: The LW400-09A provides 464 Ω internal pulldown resistors at

Cable Selection: For TTL output: Spectra Strip 843-132 - 280-020.

The LW400-09A includes 75 Ω back terminations on all the TTL
output lines. These resistors are used to match the transmission
line impedance taking into account the additional source
impedance of the TTL driver. The 75 Ω resistors match the 80
impedance of the flat cable fairly well. In this fashion, no
termination resistor is required or desired. The most important
consideration in this scheme is that the load should be as close
to an open circuit as possible. One, or at most, two TTL loads
should be placed at the termination of the line. Capacitance at
the termination will have a detrimental effect on the rise time of
the received signal. Every effort should be made to limit parasitic
capacitance at the termination of the cable to under 10 pF. All
grounds should be tied together at the load side of the cable.

the ECL output drivers. The ECL outputs need to be terminated
at the load side of the cable. The most optimum interconnection
would utilize ECL line receivers at the receiver end of the cable,
with termination resistors of 50 Ω tied to -2 Volts.

Ω

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