Kontron CP3002-RC, CP3002-RA User Manual

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P R E L I M I N A R Y

CP3002-RC/CP3002-RA

3U CompactPCI Processor Board based on

the Intel® Core™ i7 Processor with

the Intel® QM57 Chipset

Doc. ID: 1039-3625, Rev. 1.0

October 8, 2010

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Preface CP3002-RC/CP3002-RA

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P R E L I M I N A R Y

Revision History

Imprint

Kontron Modular Computers GmbH may be contacted via the following:

MAILING ADDRESS TELEPHONE AND E-MAIL

Kontron Modular Computers GmbH +49 (0) 800-SALESKONTRON Sudetenstraße 7 sales@kontron.com D - 87600 Kaufbeuren Germany

For further information about other Kontron products, please visit our Internet web site: www.kontron.com.

Disclaimer

Copyright © 2010 Kontron AG. All rights reserved. All data is for informatio n purposes only and not guaranteed for legal purposes. Information has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Kontron and the Kontron logo and all other trademarks or registered trademarks are the property of their respective owners and are recognized. Specifications are subject to change without notice.

Publication Title:

CP3002-RC/CP3002-RA: 3U CompactPCI Processor Board based on the Intel® Core™ i7 Processor with the Intel® QM57 Chipset

Doc. ID: 1039-3625

Rev. Brief Description of Changes Date of Issue

1.0 Initial issue 8-Oct-2010

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P R E L I M I N A R Y

Table of Contents

Revision History .........................................................................................................ii

Imprint ........................................................................................................................ii

Disclaimer ..................................................................................................................ii

Table of Contents ......................................................................................................iii

List of Tables ............................................................................................................vii

List of Figures ...........................................................................................................ix

Proprietary Note ........................................................................................................xi

Trademarks ...............................................................................................................xi

Environmental Protection Statement .........................................................................xi

Explanation of Symbols ...........................................................................................xii

For Your Safety .......................................................................................................xiii

High Voltage Safety Instructions .........................................................................xiii

Special Handling and Unpacking Instructions ....................................................xiii

General Instructions on Usage ...............................................................................xiv

Two Year Warranty ...................................................................................................xv

1. Introduction ............................................................................. 1 - 3

1.1 Board Overview .......................................................................................1 - 3

1.2 Board-Specific Information ......................................................................1 - 4

1.3 System Expansion Capabilities ...............................................................1 - 4

1.3.1 Serial ATA Flash Module ................................................................1 - 4

1.4 Board Diagrams ......................................................................................1 - 4

1.4.1 Functional Block Diagram ...............................................................1 - 5

1.4.2 CP3002-RA Front Panel .................................................................1 - 6

1.4.3 Board Layout ..................................................................................1 - 7

1.5 Technical Specification ............................................................................1 - 8

1.6 Standards for the CP3002-RC ..............................................................1 - 12

1.7 Standards for the CP3002-RA ...............................................................1 - 13

1.8 Related Publications .............................................................................1 - 14

2. Functional Description ........................................................... 2 - 3

2.1 Processor ................................................................................................2 - 3

2.2 Memory ...................................................................................................2 - 4

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2.3 Intel® QM57 Express Chipset .................................................................2 - 4

2.4 Timer ........................................................................................................2 - 5

2.5 Watchdog Timer ......................................................................................2 - 5

2.6 Battery .....................................................................................................2 - 5

2.7 Reset .......................................................................................................2 - 5

2.8 FLASH Memory .......................................................................................2 - 6

2.8.1 SPI FLASH for uEFI BIOS ..............................................................2 - 6

2.8.2 Serial ATA Flash Module (Optional) ................................................2 - 6

2.9 Trusted Platform Module 1.2 (On Request) .............................................2 - 6

2.10 Board Interfaces ......................................................................................2 - 7

2.10.1 Front Panel LEDs ............................................................................2 - 7

2.10.2 USB Interfaces ................................................................................2 - 8

2.10.3 Integrated Graphics Controller ........................................................2 - 9

2.10.3.1 Graphics Memory Usage ........................................................2 - 9

2.10.4 Serial Ports ......................................................................................2 - 9

2.10.5 Gigabit Ethernet Interfaces ...........................................................2 - 10

2.10.6 Serial ATA Interface .......................................................................2 - 10

2.10.7 GPI and GPO Signals ...................................................................2 - 10

2.10.8 Debug Interface .............................................................................2 - 10

2.10.9 CompactPCI Bus Interface ............................................................2 - 11

2.10.10CompactPCI Rear I/O Interface ....................................................2 - 11

2.10.10.1 CompactPCI Connectors J1 and J2 .....................................2 - 12

2.10.10.2 CompactPCI Connector Keying ............................................2 - 12

2.10.10.3 CompactPCI Connectors J1 and J2 Pinouts ........................2 - 13

2.10.10.4 Rear I/O Pin Description .......................................................2 - 15

2.10.11 CompactPCI Grounding Configuration ..........................................2 - 18

3. Installation ................................................................................3 - 3

3.1 Safety Requirements ...............................................................................3 - 3

3.2 Initial Installation Procedures for the CP3002-RC ................................................3 - 4

3.3 Standard Removal Procedures for the CP3002-RC ................................3 - 6

3.4 Initial Installation Procedures for the CP3002-RA ...................................3 - 7

3.5 Standard Removal Procedures for the CP3002-RA ................................3 - 8

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3.6 Hot Swap Procedures .............................................................................3 - 8

3.7 Installation of CP3002-RC/CP3002-RA Peripheral Devices ...................3 - 8

3.7.1 SATA Flash Module Installation ....................................................3 - 10

3.7.2 Rear I/O Device Installation ..........................................................3 - 10

3.8 Software Installation ..............................................................................3 - 10

4. Configuration ........................................................................... 4 - 3

4.1 Jumper Description .................................................................................4 - 3

4.1.1 COMB (RS-422) Termination Jumper Settings (JP1 and JP2) ....... 4 - 3

4.1.2 uEFI BIOS Configuration Jumper Settings (JP3 and JP4) ............4 - 3

4.2 I/O Address Map .....................................................................................4 - 4

4.3 CP3002-RC/CP3002-RA-Specific Registers ...........................................4 - 5

4.3.1 Status Register 0 (STAT0) ..............................................................4 - 5

4.3.2 Status Register 1 (STAT1) ..............................................................4 - 6

4.3.3 Control Register 0 (CTRL0) ............................................................4 - 7

4.3.4 Control Register 1 (CTRL1) ............................................................4 - 7

4.3.5 Device Protection Register (DPROT) .............................................4 - 8

4.3.6 Reset Status Register (RSTAT) ......................................................4 - 9

4.3.7 Board Interrupt Configuration Register (BICFG) ...........................4 - 10

4.3.8 Status Register 2 (STAT2) ............................................................ 4 - 11

4.3.9 Board ID High Byte Register (BIDH) ............................................. 4 - 11

4.3.10 Board and PLD Revision Register (BREV) ................................... 4 - 11

4.3.11 Geographic Addressing Register (GEOAD) .................................4 - 12

4.3.12 Watchdog Timer Control Register (WTIM) ...................................4 - 13

4.3.13 Board ID Low Byte Register (BIDL) ..............................................4 - 15

4.3.14 Debug LED Configuration Register (DLCFG) ...............................4 - 16

4.3.15 Debug LED Control Register (DLCTRL) .......................................4 - 17

4.3.16 General Purpose Output Register (GPOUT) ................................4 - 18

4.3.17 General Purpose Input Register (GPIN) .......................................4 - 18

5. Power Considerations ............................................................ 5 - 3

5.1 System Power .........................................................................................5 - 3

5.1.1 CP3002-RC/CP3002-RA Baseboard ..............................................5 - 3

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5.1.2 Backplane .......................................................................................5 - 4

5.1.3 Power Supply Units .........................................................................5 - 4

5.1.3.1 Start-Up Requirement .............................................................5 - 4

5.1.3.2 Power-Up Sequence ...............................................................5 - 4

5.1.3.3 Regulation ...............................................................................5 - 5

5.2 Power Consumption ................................................................................5 - 6

5.2.1 Power Consumption of the CP3002-RC/CP3002-RA Accessories..5 - 8

5.2.2 Power Consumption of the Gigabit Ethernet Controller ..................5 - 8

5.3 Start-Up Currents of the CP3002-RC/CP3002-RA ..................................5 - 8

6. Thermal Considerations .........................................................6 - 3

6.1 Board Internal Thermal Monitoring ..........................................................6 - 3

6.2 Processor Thermal Monitoring .................................................................6 - 3

6.2.1 Digital Thermal Sensor (DTS) .........................................................6 - 3

6.2.2 Adaptive Thermal Monitor ...............................................................6 - 4

6.2.3 Frequency/VID Control ...................................................................6 - 4

6.2.4 Clock Modulation .............................................................................6 - 4

6.2.5 Catastrophic Cooling Failure Sensor ..............................................6 - 5

6.3 Chipset Thermal Monitor Feature ............................................................6 - 5

6.4 Thermal Characteristics for the CP3002-RC ...........................................6 - 5

6.5 External Thermal Regulation of the CP3002-RA .....................................6 - 7

6.5.1 Operational Limits for the CP3002-RA .................................................6 - 9

6.5.2 Peripherals ......................................................................................6 - 9

A. SATA Flash Module ................................................................ A - 3

A.1 Technical Specifications .........................................................................A - 3

A.2 SATA Flash Module Layout ....................................................................A - 4

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List of Tables

1-1 CP3002-RC/CP3002-RA Main Specifications ........................................... 1 - 8

1-2 Standards for the CP3002-RC ................................................................. 1 - 12

1-3 Standards for the CP3002-RA ................................................................. 1 - 13

1-4 Related Publications ................................................................................ 1 - 14

2-1 Features of the Processor Supported on the CP3002-RC/CP3002-RA .... 2 - 4

2-2 Debug LEDs’ Function ............................................................................... 2 - 7

2-3 POST Code Sequence .............................................................................. 2 - 8

2-4 POST Code Example ................................................................................ 2 - 8

2-5 CompactPCI Bus Connector J1 System Controller Slot Pinout ............... 2 - 13

2-6 Rear I/O CompactPCI Bus Connector J2 Pinout ..................................... 2 - 14

2-7 COMA and COMB Signal Description ..................................................... 2 - 15

2-8 Gigabit Ethernet Signal Description ......................................................... 2 - 16

2-9 Serial ATA Signal Description .................................................................. 2 - 17

2-10 USB Signal Description ........................................................................... 2 - 17

2-11 VGA Signal Description ........................................................................... 2 - 17

2-12 GPI/GPO Signal Description ................................................................... 2 - 18

2-13 Power Signal Description ........................................................................ 2 - 18

4-1 JP1 Jumper Setting for RS-422 RXD Termination (COMB) ...................... 4 - 3

4-2 JP2 Jumper Setting for RS-422 TXD Termination (COMB) ....................... 4 - 3

4-3 uEFI BIOS Boot Settings Jumper (JP3) .................................................... 4 - 3

4-4 uEFI BIOS Boot Configuration Jumper (JP4) ............................................ 4 - 3

4-5 I/O Address Map ........................................................................................ 4 - 4

4-6 Status Register 0 (STAT0) ......................................................................... 4 - 5

4-7 Status Register 1 (STAT1) ......................................................................... 4 - 6

4-8 Control Register 0 (CTRL0) ....................................................................... 4 - 7

4-9 Control Register 1 (CTRL1) ....................................................................... 4 - 7

4-10 Device Protection Register (DPROT) ........................................................ 4 - 8

4-11 Reset Status Register (RSTAT) ................................................................. 4 - 9

4-12 Board Interrupt Configuration Register (BICFG) ..................................... 4 - 10

4-13 Status Register 2 (STAT2) ....................................................................... 4 - 11

4-14 Board ID High Byte Register (BIDH) ....................................................... 4 - 11

4-15 Board and PLD Revision Register (BREV) .............................................. 4 - 11

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4-16 Geographic Addressing Register (GEOAD) ............................................. 4 - 12

4-17 Watchdog Timer Control Register (WTIM) ............................................... 4 - 14

4-18 Board ID Low Byte Register (BIDL) ......................................................... 4 - 15

4-19 Debug LED Configuration Register (DLCFG) .......................................... 4 - 16

4-20 Debug LED Control Register (LCTRL) ..................................................... 4 - 17

4-21 General Purpose Output Register (GPOUT) ............................................ 4 - 18

4-22 General Purpose Input Register (GPIN) .................................................. 4 - 18

5-1 Maximum Input Power Voltage Limits ........................................................ 5 - 3

5-2 DC Operational Input Voltage Ranges ....................................................... 5 - 3

5-3 CP3002-RC/-RA in EFI Shell ..................................................................... 5 - 7

5-4 CP3002-RC/-RA with Win. XP and Processor and Graphics in Idle State.. 5 - 7 5-5 CP3002-RC/-RA with Win. XP and Typ. Proc. and Graph. Contr. Workload 5 - 7 5-6 CP3002-RC/-RA with Win. XP and Max. Processor and Graph. Workload 5 - 7

5-7 Power Consumption of CP3002-RC/CP3002-RA Accessories .................. 5 - 8

5-8 Power Consumption of the Gigabit Ethernet Controller ............................ 5 - 8

5-9 Start-Up Currents of the CP3002-RC/CP3002-RA ..................................... 5 - 8

6-1 Maximum Reference Point Temperature at 105°C CPU Die Temperature 6 - 6

A-1 SATA Flash Module Specifications ............................................................ A - 3

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List of Figures

1-1 CP3002-RC/CP3002-RA Functional Block Diagram ............................... 1 - 5

1-2 CP3002-RA Front Panel .......................................................................... 1 - 6

1-3 CP3002-RC/CP3002-RA Board Layout – Top View ............................... 1 - 7

1-4 CP3002-RC/CP3002-RA Board Layout – Bottom View ........................... 1 - 7

2-1 CPCI Connectors J1/J2 ......................................................................... 2 - 12

3-1 CP3002-RC with SATA Flash Module ...................................................... 3 - 9

3-2 CP3002-RA with SATA Flash Module ...................................................... 3 - 9

6-1 Position of the Reference Points on the CP3002-RC .............................. 6 - 6

6-2 CP3002-RA with i7-620LE, 2.0 GHz ........................................................ 6 - 9

A-1 SATA Flash Module Layout (Bottom View) .............................................. A - 4

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Proprietary Note

This document contains information proprietary to Kontron. It may not be copied or transmitted by any means, disclosed to others, or stored in any retrieval system or media without the prior written consent of Kontron or one of its authorized agents.

The information contained in this document is, to the best of our knowledge, entirely correct. However, Kontron cannot accept liability for any inaccuracies or the consequences thereof, or for any liability arising from the use or application of any circuit, product, or example shown in this document.

Kontron reserves the right to change, modify, or improve this document or the product described herein, as seen fit by Kontron without further notice.

Trademarks

Kontron, the PEP logo and, if occurring in this manual, “CXM” are trad emarks owned by Kontron, Kaufbeuren (Germany). In addition, this document may include names, company logos and trademarks, which are registered trademarks and, therefore, proprietary to their respective owners.

Environmental Protection Statement

This product has been manufactured to satisfy environmental protection requirements where possible. Many of the components used (structural parts, printed circuit boards, connectors, batteries, etc.) are capable of being recycled.

Final disposition of this product after its service life must be accomplished in accordance with applicable country, state, or local laws or regulations.

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Explanation of Symbols

Caution, Electric Shock!

This symbol and title warn of hazards due to electrical shocks (> 60V) when touching products or parts of them. Failure to observe the precautions indicated and/or prescribed by the law may endanger your life/health and/or result in damage to your material.

Please refer also to the section “High Voltage Safety Instructions” on the following page.

Warning, ESD Sensitive Device!

This symbol and title inform that electronic boards and their components are sensitive to static electricity. Therefore, care must be taken during all handling operations and inspections of this product, in order to ensure product integrity at all times.

Please read also the section “Special Handling and Unpacking Instructions” on the following page.

Warning!

This symbol and title emphasize points which, if not fully understood and taken into consideration by the reader, may endanger your health and/or result in damage to your material.

Note ...

This symbol and title emphasize aspects the reader should read through carefully for his or her own advantage.

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For Your Safety

Your new Kontron product was developed and tested carefully to provide all features necessary to ensure its compliance with electrical safety requirements. It was also designed for a long fault-free life. However, the life expect ancy of your product can be drastically reduced by improper treatment during unpacking and installation. The refore, in the interest of your own safety and of the correct operation of your new Kontron product, you are requested to conform with the following guidelines.

High Voltage Safety Instructions

Special Handling and Unpacking Instructions

Do not handle this product out of its protective enclosure while it is not used for operational purposes unless it is otherwise protected.

Whenever possible, unpack or pack this product only at EOS/ESD safe work stations. Where a safe work station is not guaranteed, it is important for the user to be electrically discharged before touching the product with his/her hands or tools. This is most easily done by touching a metal part of your system housing.

It is particularly important to observe standard anti-static precautions when changing piggybacks, ROM devices, jumper settings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not placed on conductive surfaces, including anti-static plastics or sponges. They can cause short circuits and damage the batteries or conduct ive circuits on the board.

Warning!

All operations on this device must be carried out by sufficiently skilled personnel only.

Caution, Electric Shock!

Before installing a not hot-swappable Kontron product into a system always ensure that your mains power is switched off. This applies also to the installation of piggybacks.

Serious electrical shock hazards can exist during all installation, repair and maintenance operations with this product. Therefore, always unplug the power cable and any other cables which provide external voltages before performing work.

ESD Sensitive Device!

Electronic boards and their components are sensitive to static electricity. Therefore, care must be taken during all handling operations and inspections of this product, in order to ensure product integrity at all times.

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General Instructions on Usage

In order to maintain Kontron’s product warranty, this product must not be altered or modified in any way . Chang es or modifications to the device , which are not explicitly approve d by Kontron and described in this manual or received from Kontron’s Technical Support as a special handling instruction, will void your warranty.

This device should only be installed in or connected to systems that fulfill all necessary technical and specific environmental requirements. This applies also to the operational temperature range of the specific board version, which must not be exceeded. If batteries are present, their temperature restrictions must be taken into account.

In performing all necessary installation and application operations, please follow only the instructions supplied by the present manual.

Keep all the original packaging material for future storage or warranty shipments. If it is necessary to store or ship the board, please re-pack it as nearly as possible in the manner in which it was delivered.

Special care is necessary when handling or unpacking the product. Please consult the spe cial handling and unpacking instruction on the previous page of this manual.

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Two Year Warranty

Kontron grants the original purchaser of Kontron’s products a TWO YEAR LIMITED HARDWARE

WARRANTY

as described in the following. However, no othe r warranties that may be granted or

implied by anyone on behalf of Kontron are valid unless the consumer has the express written consent of Kontron.

Kontron warrants their own products, excluding software, to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase. This warranty is not transferable nor extendible to cover any other users or long-term storage of the product. It does not cover products which have been modified, altered or repaired by any other party than Kontron or their authorized agents. Furthermore, any product which has been, or is suspected of being damaged as a result of negligence, improp er use, incorrect handling, servicing or maintenance, or which has been damaged as a result of excessive current/voltage or temperature, or which has had its serial number(s), any other markings or parts thereof altered, defaced or removed will also be excluded from this warranty.

If the customer’s eligibility for warranty has not been voided, in the event of any claim, he may return the product at the earliest possible convenience to the original place of purcha se, together with a copy of the original document of purchase, a full description of the application the product is used on and a description of the defect. Pack the product in such a way as to ensure safe transportation (see our safety instructions).

Kontron provides for repair or replacement of any p art, assembly or su b-assembly at their own discretion, or to refund the original cost of purchase, if appropriate. In the event of repair, refunding or replacement of any part, the ownership of the removed or replaced parts reverts to Kontron, and the remaining part of the original guarantee, or any new guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired items. Any extensions to the original guarantee are considered gestures of goodwill, and will be defined in the “Repair Report” issued by Kontron with the repaired or replaced item.

Kontron will not accept liability for any further claims resulting directly or indirectly from any warranty claim, other than the above specified repair, replacement or refunding. In particular, all claims for damage to any system or process in which the product was employed, or any loss incurred as a result of the product not functioning at any given time, are excluded. The extent of Kontron liability to the customer shall not exceed the original purchase price of the item for which the claim exists.

Kontron issues no warranty or representation, either explicit or implicit, with respect to its products’ reliability, fitness, quality, marketability or ability to fulfil any particular application or purpose. As a result, the products are sold “as is,” and the responsibility to ensure their suitability for any given task remains tha t of the purchaser. In no event will Kontron be liable for direct, indirect or consequential damages resulting from the use of our hardware or software products, or documentation, even if Kon tron were advised of the possibility of such claims prior to the purchase of the product or during any period since the date of its purchase.

Please remember that no Kontron employee, dealer or agent is authorized to make any modification or addition to the above specified terms, either verbally or in any other form, written or electronically transmitted, without the company’s consent.

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CP3002-RC/CP3002-RA Introduction

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Introduction

Chapter 1

P R E L I M I N A R Y

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1. Introduction

1.1 Board Overview

The CP3002-RC/CP3002-RA is a highly integrated 3U CompactPCI system controller board based on the multi-chip Intel® Core™ i7 processor combined with the mobile Intel® QM57 Express chipset.

The board supports the Intel® Core™ i7-620LE processor in 32 nm technology with 64 kB L1 cache, 256 kB L2 cache and 4 MB L3 cache in a BGA package with 2.0 GHz frequency. The processor and the memory are soldered on the CP3002-RC/CP3002-RA which results in higher Mean Time Between Failures (MTBF) and a significant improvement in cooling.

The CP3002-RC/CP3002-RA includes up to 8 GB, dual-channel Double Data Rate (DDR3) memory with Error Checking and Correcting (ECC) running at 1066 MHz. The graphics controller and the memory controller are integrated in the processor.

The CP3002-RC/CP3002-RA provides support for up to 32 GB SATA NAND Flash memory (SSD).

The board also includes one Quad Gigabit Ethernet controller, Intel® 82580EB, utilizing a x4 lane PCI Express interconnection to the processor and providing four 10Base-T/100Base-TX/ 1000Base-T Ethernet interfaces to the rear I/O.

The CP3002-RC/CP3002-RA comes with three Serial ATA interfaces with RAID support, one for the SATA Flash module, and two on the rear I/O as well as one high-resolution graphics interface (VGA). In addition, two USB 2.0 ports are available on the rear I/O. Further interfaces include two serial ports on the rear I/O, one RS-232 port and one RS-422/RS-232 port.

The board supports a configurable 32-bit, 33/66 MHz PCI CompactPCI interface. The CP3002-RC/CP3002-RA further provides safety and security features via a Trusted Platform

Module (TPM) 1.2 on request. The CP3002-RC is conductive-cooled, has an extended operating temperature range and is

ruggedized for high shock and vibration environments. The board is also available as a rugged, air-cooled version, CP3002-RA, providing a heat sink optimized for forced air cooling and a front panel.

Designed for stability , the board fits into applications situated in industrial environments, including I/O intensive applications where only one slot is available for the CPU, making it a perfect core technology for long-life applications. Components with high temperature tolerance have been selected from embedded technology programs, and therefore offer long-term availability.

The board is offered with various Board Support Packages including Windows and Linux operating systems. For further information concerning the operating systems available for the CP3002-RC/CP3002-RA

please contact Kontron.

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1.2 Board-Specific Information

The CP3002-RC/CP3002-RA is a CompactPCI single-board computer based on the Intel® Core™ i7 processor and specifically designed for use in highly integrated platforms with solid mechanical interfacing for a wide range of industrial environment applications.

Some of the CP3002-RC/CP3002-RA's outstanding features are:

• Support for the Intel® Core™ i7-620LE (LV) processor, 2.0 GHz

• Intel® QM57 Express chipset

• Up to 8 GB, dual-channel, DDR3 SDRAM memory with ECC running at 1066 MHz

• Integrated 3D high-performance graphics controller with one high-resolution graphics interfaces (VGA)

• 32-bit, 33/66 MHz PCI CompactPCI interface for support of up to four peripheral slots (4x REQ/GNT signals)

• One Quad Gigabit Ethernet controller , Intel® 82580EB, providing four 10Base-T/100BaseTX/1000Base-T Ethernet interfaces on the rear I/O

• Three Serial ATA interfaces with SATA RAID 0/1/5 support:

• One onboard Serial ATA interface

• Two Serial ATA interfaces on the rear I/O

• Socket for one Serial ATA Flash module (SSD)

• Two USB 2.0 ports on the rear I/O

• Two serial ports on the rear I/O:

• One RS-232 serial port

• One RS-422/RS-232 serial port

• TCG 1.2 compliant Trusted Platform Module (TPM), on request

• Two SPI Flash chips for redundant uEFI BIOS

• Watchdog timer

• Five general purpose inputs (GPI) and three general purpose outputs (GPO) on rear I/O

• Real-time clock (RTC)

• 4HP, 3U CompactPCI

• Rugged, conductive-cooled version with heat spreader or rugged, air-cooled version with heat sink for forced airflow cooling

• Rear I/O on the CompactPCI connector J2

• AMI Aptio®, a uEFI-compliant platform firmware

1.3 System Expansion Capabilities

1.3.1 Serial ATA Flash Module

The CP3002-RC/CP3002-RA provides support for up to 32 GB of Serial ATA Flash memory in combination with an optional Serial ATA Flash module, which is connected to an onboard extension connector. For further information concerning the Serial ATA Flash module, please refer to Appendix A.

1.4 Board Diagrams

The following diagrams provide additional information concerning board functionality and component layout.

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1.4.1 Functional Block Diagram

Figure 1-1: CP3002-RC/CP3002-RA Functional Block Diagram

Intel®

QM57

Debug

LEDs

FPGA

Board

Control

CompactPCI

Connector

SFF

XDP

Debug

SPI

EEPROM

3.3V and 5V

1st

uEFI BIOS

FLASH

DDR3 w ECC

Bank A

soldered

DDR3 w ECC

Bank B

soldered

Intel®

Core™ i7

BGA

DDR3 DDR3

DMI

1066 MHz

SATA Flash

Module

DMI

LPC

SATA

FDI

SATA

TPM

TPM (on request)

32-bit, 33/66 MHz PCI

4x REQ/GNT

USB

VGA

CRT

Dual

UART

SMBus

GPIO

TTL

USB

VGA

CRT

PCIe

Diode

Switch

Back-up

Voltage

RTC

Onboard

Power Supplies

DC/DC etc.

2nd

uEFI BIOS

FLASH

RS-232

RS-422

RS-232

COMB

RS-422 or

RS-232

COMA

RS-232

USB

Power

USB

power

10Base-T/100Base-TX/1000Base-T

PCIe to

PCI bridge

Intel

Quad GbE

82580EB

COPPER

COPPER COPPER

COPPER

5x GPI

3x GPO

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1.4.2 CP3002-RA Front Panel

Figure 1-2: CP3002-RA Front Panel

Legend:

Debug LEDs:

DLED0 (red/green): Debug LED 0 + POST DLED1 (red/green): Debug LED 1 + POST DLED2 (red/green): Debug LED 2 + POST DLED3 (red/green): Debug LED 3 + POST

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1.4.3 Board Layout

Figure 1-3: CP3002-RC/CP3002-RA Board Layout – Top View

Figure 1-4: CP3002-RC/CP3002-RA Board Layout – Bottom View

GbE

Contr.

Intel® Core™i7

CPUGMCH

Intel® QM57

DDR3 Memory

SATA Flash

Module

1112

DDR3 Memory

DLED 0

DLED 1

DLED 2

DLED 3

JP2

JP1

JP4JP3

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1.5 Technical Specification

Table 1-1: CP3002-RC/CP3002-RA Main Specifications

FEATURES SPECIFICATIONS

Processor and Memory

CPU The CP3002-RC/CP3002-RA supports the following microprocessor:

• Intel® Core™ i7-620LE (LV) processor, 2.0 GHz, 4 MB L3 cache

Further processor features:

• Two execution cores

• Intel® Hyper-Threading Technology (Intel® HT Technology)

• Intel® 64 Architecture

• Intel® Turbo Boost Technology

• Intel® Intelligent Power Sharing (IPS)

• System Memory interface with optimized support for dual-channel

DDR3 SDRAM memory at 1066 MHz with ECC

• Integrated 2D and 3D Graphics Engines

• DMI and FDI interfaces to the Intel® QM57 chipset

• Two x8 PCI Express 2.0 ports operating at 2.5 GT/s

Please contact Kontron for further information concerning the suitability of other Intel processors for use with the CP3002-RC/CP3002-RA.

Memory Main Memory:

• Up to 8 GB, dual-channel DDR3 SDRAM memory with ECC running at

1066 MHz

Cache Structure:

• 64 kB L1 cache for each core

• 32 kB instruction cache

• 32 kB data cache

• 256 kB L2 shared instruction/data cache for each core

• 4 MB L3 shared instruction/data cache shared between both cores

FLASH Memory:

• Two redundant SPI Flash chips (2 x 8 MB) for uEFI BIOS

• Up to 32 GB NAND Flash via an onboard Serial ATA Flash module

(SSD)

Serial EEPROM with 64 kbit

Chipset

Intel® QM57 Mobile Intel® QM57 Express Chipset:

• Two x4 or eight x1 PCI Express 2.0 ports operating at 2.5 GT/s (only one

x4 PCI Express port is used)

• SATA host controller with six ports, 3 Gbit/s data transfer rate and

RAID 0/1/5/10 support (only three ports are used, thus only RAID 0/1/5 support is available on the board)

• USB 2.0 host interface with up to 14 USB ports available (only two ports

are used)

• SPI Flash interface support

• Low Pin Count (LPC) interface

• PCI interface, 32-bit/33 MHz (not used)

• Power management logic support

• Enhanced DMA controller, interrupt controller, and timer functions

• System Management Bus (SMBus) compatible with most I²C™ devices

• DMI and FDI interfaces to the processor

• High Definition Audio (HDA) interface (not used)

• Analog display port

• Three digital display ports (not used)

• Integrated RTC

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Integrated

Controller

Graphics controller High-performance 3D graphics controller integrated in the processor:

• Supports resolutions up to 2048 x 1536 pixels @ 60 Hz

• Dynamic Video Memory Technology (DVMT)

Interfaces

CompactPCI

Compliant with CompactPCI Specification PICMG

2.0 R 3.0:

• System controller operation

• 32-bit, 33 /66 MHz PCI master interface with dedicated PCIe-to-PCI

bridge

• 3.3 V or 5 V signaling levels (universal signaling support)

• Support for up to four peripheral slots (4x REQ/GNT signals)

Rear I/O The following interfaces are routed to the rear I/O CompactPCI connector J2:

• 1 x COMA (RS-232 signaling)

• 1 x COMB (RS-422/RS-232 signaling)

• 2 x USB 2.0

• 1 x VGA analog port

• 4 x 10 Base-T/100 Base-TX/1000 Base-T Gigabit Ethernet interfaces

• 2 x SATA

• 5 x GPIs and 3x GPOs (LVTTL signaling)

• Back-up voltage (3.3 V)

Interfaces

Gigabit Ethernet

Up to four 10 Base-T/100 Base-TX/1000 Base-T Gigabit Ethernet interfaces based on the Intel® 82580EB Quad Gigabit Ethernet controller:

• Four ports on the rear I/O

• Automatic mode recognition (Auto-Negotiation)

• Automatic cabling configuration recognition (Auto-MDI/X)

USB

Two USB 2.0 ports on the rear I/O interface

Serial Two 16C550-compatible UARTs (RS-232/RS-422 signaling):

• One RS-232 port on the rear I/O, COMA

• One RS-422/RS-232 port on the rear I/O, COMB

Serial ATA Serial ATA Host Controllers integrated in the Intel® QM57 chipset:

• Provide support for three SATA ports, one onboard and two on rear I/O

• Data transfer rates up to 300 MB/s

• High-performance RAID 0/1/5 functionality on all SATA ports

Sockets

Onboard Connectors • One 34-pin extension connector, J3, for SATA Flash module (SSD)

• JTAG connector, J4

• XDP-SFF (debug) connector, J6

• CompactPCI Connectors J1 and J2

LEDs

Debug LEDs Debug LEDs:

• DLED0-3 (red/green): Onboard LEDs for debugging purposes

The DLEDs are located on the rear side of the board. On the CP3002-RA, the DLEDs are visible on the front panel.

Table 1-1: CP3002-RC/CP3002-RA Main Specifications (Continued)

FEATURES SPECIFICATIONS

Note ...

To operate the CP3002-RC/CP3002-RA, 3U CompactPCI backplane with maximum five slots and rear I/O support on the system slot is required.

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Timer

Watchdog Timer • Software-configurable, two-stage Watchdog with programmable timeout

ranging from 125 ms to 4096 s in 16 steps

• Serves for generating IRQ or hardware reset

System Timer

• The Intel® QM57 chipset contains three 8254-style counters which have

fixed uses

• In addition to the three 8254-style counters, the Intel® QM57 chipset in-

cludes eight individual high-precision event timers that may be used by the operating system. They are implemented as a single counter each with its own comparator and value register.

System Management

Thermal Management CPU and board overtemperature protection is provided by:

• Temperature sensors integrated in Intel® Core™ i7 processor:

• Two temperature sensors for monitoring the processor cores

• One temperature sensor for monitoring the graphics controller and

the memory controller

• One temperature sensor integrated in the Intel® QM57 chipset for mon-

itoring the chipset

• Specially designed heat sinks

Security

TPM Trusted Platform Module (TPM) 1.2 for enhanced hardware- and software-

based data and system security (on request)

Software

uEFI BIOS AMI Aptio®, AMI’s next-generation BIOS firmware based on the uEFI Specifi-

cation and the Intel Platform Innovation Framework for EFI.

• LAN boot capability for diskless systems (standard PXE)

• Redundant image; automatic fail-safe recovery in case of a damaged

image

• Non-volatile storage of setting in the SPI Flash (battery only required for

the RTC)

• Compatibility Support Module (CSM) providing legacy BIOS compatibil-

ity based on AMIBIOS8

• Command shell for diagnostics and configuration

• EFI shell commands executable from mass storage device in a Pre-OS

environment (open interface)

Operating Systems

The board is offered with various Board Support Packages including Windows and Linux operating systems. For further information concerning the operating systems available for the CP3002-RC/CP3002-RA, please contact Kontron.

Table 1-1: CP3002-RC/CP3002-RA Main Specifications (Continued)

FEATURES SPECIFICATIONS

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General

Mechanical 3U, 4HP, CompactPCI-compliant form factor Power Consumption See Chapter 5 for details. Temperature Ranges Operational: -40°C to +85°C Extended without TPM (CP3002-RC)

-40°C to +75°C Extended without TPM (CP3002-RA)

-25°C to +70°C Extended with TPM

Storage: -55°C to +85°C Without additional components

Back-up Voltage A back-up voltage input for the RTC can be connected via the rear I/O connec-

tor J2. Climatic Humidity 93% RH at 40 °C, non-condensing (acc. to IEC 60068-2-78) Dimensions 100 mm x 160 mm Board Weight CP3002-RC: 342 g (with heat sink but without mezzanine card)

CP3002-RA 403 g (with heat sink but without mezzanine card)

Table 1-1: CP3002-RC/CP3002-RA Main Specifications (Continued)

FEATURES SPECIFICATIONS

Note ...

When additional components are installed, refer to their operational specifications as this will influence the operational and storage temperature of the CP3002-RC/CP3002-RA.

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1.6 Standards for the CP3002-RC

The CP3002-RC complies with the requirements of the following standards:

Table 1-2: Standards for the CP3002-RC

TYPE ASPECT STANDARD REMARKS

CE Emission EN55022

EN61000-6-3

Immission EN55024

EN61000-6-2

Electrical Safety EN60950-1 -Mechanical Mechanical Dimensions VITA 30.1 -Environmental Climatic Humidity IEC60068-2-78 See note below

WEEE Directive 2002/96/EC Waste electrical and electronic equipment

RoHS Directive 2002/95/EC Restriction of the use of certain hazardous

substances in electrical and electronic equipment

Random Vibration

(Broadband)

VITA 47 (Class V3)

TBD

Single Shock VITA 47

(Class V3)

TBD

Temperature VITA 47, CC3

VITA 47, CC4

TBD

Note ...

Kontron performs comprehensive environmental testing of its product s in accordance with applicable standards.

Customers desiring to perform further environmental testing of Kontron products must contact Kontron for assistance prior to performing any such testing. This is necessary, as it is possible that environmental testing can be destructive when not performed in accordance with the applicable specifications.

In particular, for example, boards without conformal coating must not be exposed to a change of temperature exceeding 1K/minute, averaged over a period of not more than five minutes. Otherwise, condensation may cause irreversible damage, especially when the board is powered up again.

Kontron does not accept any responsibility for damage to products resulting from destructive environmental testing.

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1.7 Standards for the CP3002-RA

The CP3002-RA complies with the requirements of the following standards:

Table 1-3: Standards for the CP3002-RA

TYPE ASPECT STANDARD REMARKS

CE Emission EN55022

EN61000-6-3

Immission EN55024

EN61000-6-2

Electrical Safety EN60950-1 -Mechanical Mechanical Dimensions IEEE 1101.10 -Environmental Climatic Humidity IEC60068-2-78 See note below

WEEE Directive 2002/96/EC Waste electrical and electronic equipment

RoHS Directive 2002/95/EC Restriction of the use of certain hazardous

substances in electrical and electronic equipment

Vibration

(Sinusoidal)

IEC60068-2-6 TBD

Single Shock IEC60068-2-27 TBD

Permanent Shock IEC60068-2-29 TBD

Note ...

Kontron performs comprehensive environmental testing of it s produ cts in accordance with applicable standards.

In particular, for example, boards without conformal coating must not be exposed to a change of temperature exceeding 1K/ minute, averaged over a period of not more than five minutes. Otherwise, condensation may cause irreversible damage, especially when the board is powered up again.

Kontron does not accept any responsibility for damage to products resulting from destructive environmental testing.

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1.8 Related Publications

The following publications contain information relating to the CP3002-RC/CP3002-RA.

Table 1-4: Related Publications

PRODUCT PUBLICATION

CompactPCI Systems and Boards

CompactPCI Specification PICMG 2.0, Rev. 3.0 Kontron CompactPCI Backplane Manual, ID 24229

Platform Firmware Unified Extensible Firmware Interface (uEFI) Specification, Version 2.1 All Kontron products Product Safety and Implementation Guide, ID 1021-9142 Kontron CP3002-RC/CP3002-RA uEFI BIOS User Guide, ID 1042-8946

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Chapter 1

P R E L I M I N A R Y

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2. Functional Description

2.1 Processor

The CP3002-RC/CP3002-RA supports the low-power, high-performance, 64-bit, dual-core Intel® Core™ i7-620LE processor with 2.0 GHz clock speed.

The Intel® Core™ i7 multi-chip package processor used on the CP3002-RC/CP3002-RA includes an integrated high-performance graphics controller and a DDR3 dual-channel memory controller with ECC support as well as one x16 PCI Express 2.0 port operating at 2.5 GT/s. It support various technologies, such as:

• Intel® Hyper-Threading Technology

• Intel® Turbo Boost Technology

• Intel® Intelligent Power Sharing (IPS)

• Intel® SpeedStep® Technology

• Intel® Virtualization Technology

• Intel® Streaming SIMD Extensions 4.1

• Intel® Streaming SIMD Extensions 4.2

• Intel® 64 Architecture

• Execute Disable Bit

The Intel® Hyper-Threading Technology allows one execution core to function as two logical processors. When this feature is used on the CP3002-RC/CP3002-RA, four processor cores are present to the operating system. This results in higher processing throu ghput and improved performance on the multithreaded software.

The Intel® Turbo Boost Technology and the Intel® Intelligent Power Sharing technology allow the processor and the graphics controller to opportunistically and automatically run faster than its rated operating clock frequency if it is operating below power, temperature, and current limits.

The Intel® SpeedS tep® techno logy enables real-time dynamic switching of the voltage and frequency between several modes. This is achieved by switching the bus ratios, the core operating voltage, and the core processor speeds without resetting the system.

The Intel® Core™ i7 processor used on the CP3002-RC/CP3002-RA has the following multilevel cache structure:

• 64 kB L1 cache for each core

• 32 kB instruction cache

• 32 kB data cache

• 256 kB L2 instruction/data cache for each core

• 4 MB L3 shared instruction/data cache shared between both cores

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2.2 Memory

The CP3002-RC/CP3002-RA supports a soldered, dual-channel (144-bit), Double Data Rate (DDR3) memory with Error Checking and Correcting (ECC) running at 1066 MHz (memory error detection and reporting of 1-bit and 2-bit errors and correction of 1-bit failures). The available memory configuration can be either 4 GB or 8 GB.

However, when the internal graphics controller is enabled, the amount of memory available to applications is less than the total physical memory in the system. For example, the chipset’s Dynamic Video Memory Technology dynamically allocates the proper amount of system memory required by the operating system and the application.

2.3 Intel® QM57 Express Chipset

The CP3002-RC/CP3002-RA is equipped with the mobile Intel® QM57 Express Chipset, a highly integrated platform controller hub (PCH) with the following features:

• Two x4 or eight x1 PCI Express 2.0 ports operating at 2.5 GT/s (only one x1 PCI Express port is used)

• SATA host controller with six ports, 3 Gbit/s data transfer rate and RAID 0/1/5/10 support (only three ports are used, thus only RAID 0/1/5 support is available on the board)

• USB 2.0 host interface with up to 14 USB 2.0 ports available (only two ports are used)

• SPI interface support

• Low Pin Count (LPC) interface

• PCI interface, 32-bit/33 MHz (not used)

• Power management logic support

• Enhanced DMA controller, interrupt controller, and timer functions

• System Management Bus (SMBus)

• DMI and FDI interfaces to the processor

• Intel® High Definition Audio Interface (not used)

• Analog display port

• Three digital display ports (not used)

• Integrated RTC

Table 2-1: Features of the Processor Supported on the CP3002-RC/CP3002-RA

FEATURE Core™ i7-620LE (LV) 2.0 GHz

Processor Base Frequency 2.0 GHz Maximum Turbo Frequency 2.80 GHz L1 cache per core 64 kB L2 cache per core 256 kB L3 cache 4 MB DDR3 Memory up to 8 GB / 1066 MHz Graphics Base Frequency 266 MHz Graphics Max. Dynamic Frequency 566 MHz Thermal Design Power 25 W Package BGA (1288)

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2.4 Timer

The CP3002-RC/CP3002-RA is equipped with the following timers:

• Real-Time Clock The Intel® QM57 chipset integrates an MC146818B-compatible real-time clock with 256 Byte CMOS RAM. The CP3002-RC/CP3002-RA does not include a dedicated battery power source for RTC backup. If the board is switched off, the RTC will lose its data. All CMOS RAM data remain stored in an additional EEPROM device to prevent data loss. The RTC can optionally be powered from an external voltage source via the rear I/O connector J2 in order to retain the RTC data when the board is switched off.

• Counter/Timer Three 8254-style counter/timers are included on the CP3002-RC/CP3002-RA as defined for the PC/AT.

• The Intel® QM57 chipset integrates eight high-precision event timers.

2.5 Watchdog Timer

The CP3002-RC/CP3002-RA provides a Watchdog timer that is programmable for a timeout period ranging from 125 ms to 4096 s in 16 steps. Failure to trigger the W atchd og timer in time results in a system reset or an interrupt. In dual-stage mode, a combination of both interrupt and reset if the Watchdog is not serviced. A hardware st atus flag will be provided to determine if the Watchdog timer generated the reset.

2.6 Battery

The CP3002-RC/CP3002-RA does not include a dedicated battery power source for RTC backup. If the board is switched off, the RTC will lose its data. All CMOS RAM data remain stored in an additional EEPROM device to prevent data loss. The RTC can optionally be powered from an external voltage source via the rear I/O connector J2 in order to retain the RTC data when the board is switched off.

2.7 Reset

The CP3002-RC/CP3002-RA is automatically reset by a precision voltage monitoring circuit that detects a drop in voltage below the acceptable operating limit of 3.15 V for the 3.3 V line, or in the event of a power failure of the DC/DC converters. Other reset sources include the Watchdog timer. The CP3002-RC/CP3002-RA responds to any of these sources by initializing local peripherals.

A reset will be generated if one the following events occurs:

• +3.3 V supply falls below 3.15 V (typ.)

• Power failure of at least one onboard DC/DC converter

• Watchdog expired

• CompactPCI backplane PRST input

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2.8 FLASH Memory

The CP3002-RC/CP3002-RA provides Flash interfaces for redundant uEFI BIOS and the SATA Flash module.

2.8.1 SPI FLASH for uEFI BIOS

The CP3002-RC/CP3002-RA provides two SPI Flash chips (2 x 8 MB) for redundant uEFI BIOS. The fail-over mechanism for the uEFI BIOS recovery can be controlled via the jumper JP4.

The SPI Flash includes a hardware write protection option, which can be configured via the uEFI BIOS. If write protection is enabled, the SPI Flash cannot be written to.

2.8.2 Serial ATA Flash Module (Optional)

The CP3002-RC/CP3002-RA supports up to 32 GB of Serial ATA Flash memory in combination with an optional Serial A T A Flash module, which is connected to the onboard connector J3.

The Serial A TA Flash module is an SLC-based SAT A NAND Flash drive with a built-in full harddisk emulation and a high data transfer rate (sustained read rate with up to 100 MB/s a nd sustained write rate with up to 90 MB/s). It is optimized for embedded systems providing high performance, reliability and security.

2.9 Trusted Platform Module 1.2 (On Request)

The CP3002-RC/CP3002-RA has been designed to support the Trusted Platform Module (TPM) 1.2. This feature is available on request. TPM1.2 is a security chip sp ecifically designed to provide enhanced hardware- and software-based data and system security. It stores sensitive data such as encryption and signature keys, certificates and p asswords, and is able to withstand software attacks to protect the stored information.

Hardware features of the TPM 1.2:

• TCG 1.2 compliant Trusted Platform Module (TPM)

• Security architecture based on the Infineon SLE66CXxxPE security controller family

• EEPROM for TCG firmware enhancements and for user data and keys

• Advanced Crypto Engine (ACE) with RSA support up to 2048-bit key length

• Hardware accelerator for SHA-1 hash algorithm

• True Random Number Generator (TRNG)

• Tick counter with tamper detection

• Protection against Dictionary Attack

• Intel® Trusted Execution Technology Support

• Full personalization with Endorsement Key (EK) and EK certificate

Note ...

Write protection is available for this module. Contact Kontron for further assistance if write protection is required.

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2.10 Board Interfaces

2.10.1 Front Panel LEDs

he CP3002-RC/CP3002-RA is equipped with four Debug LEDs that can be configured via two onboard registers (see Chapter 4.3.14, “Debug LED Configura tion Register” and Chapter 4.3.15, "Debug LED Control Register").

Table 2-2: Debug LEDs’ Function

LED COLOR

FUNCTION

DURING POWER-UP

FUNCTION DURING

BOOT-UP

(if POST code config. is

enabled)

DEFAULT FUNCTION

AFTER BOOT-UP

DLED3 red When lit up during

power-up, it indicates a power failure.

-- Processor overtemperature above 125°C (blinking) and processor overtemperature above 105°C (on)

green -- uEFI BIOS POST bit 3

and bit 7

Default: Mode B, Gigabit Ethernet port D link

DLED2 red When lit up during

power-up, it indicates a clock failure.

-- Processor overtemperature above 125°C (blinking)

green -- uEFI BIOS POST bit 2

and bit 6

Default: Mode B, Gigabit Ethernet port C link

DLED1 red When lit up during

power-up, it indicates a hardware reset.

-- Processor overtemperature above 125°C (blinking)

green -- uEFI BIOS POST bit 1

and bit 5

Default: Mode B, Gigabit Ethernet port B link

DLED0 red When lit up during

power-up, it indicates a uEFI BIOS boot failure.

-- Processor overtemperature above 125°C (blinking)

green -- uEFI BIOS POST bit 0

and bit 4

Default: Mode B, Gigabit Ethernet port A link

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How to Read the 8-Bit POST Code

Due to the fact that only 4 bits are available and 8 bit s must be displayed, the Debug LEDs are multiplexed.

The following is an example of the Debug LEDs’ operation if uEFI BIOS POST configuration is enabled (see also Table 2-2, “Debug LEDs’ Function”).

2.10.2 USB Interfaces

The CP3002-RC/CP3002-RA supports two USB 2.0 port s on th e rear I /O. Both port s are highspeed, full-speed, and low-speed capable.

Table 2-3: POST Code Sequence

STATE DEBUG LEDs

0 All Debug LEDs are OFF; start of POST sequence 1 High nibble 2 Low nibble; state 2 is followed by state 0

Table 2-4: POST Code Example

LED3 LED2 LED1 LED0 RESULT

HIGH NIBBLE

off (0) on (1) off (0) off (0) 0x4

LOW NIBBLE

off (0) off (0) off (0) on (1) 0x1

POST CODE

0x41

Note ...

Under normal operating conditions, the Debug LEDs should not remain lit during boot-up. They are intended to be used only for debugging purposes. In the event that a Debug LED lights up during boot-up and the CP3002-RC/CP3002-RA does not boot, please contact Kontron.

If all Debug LEDs flash red on and off at regular intervals, they indicate that the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Once activated, the overtemperature event remains latched until a cold restart of the CP3002-RC/CP3002-RA is undertaken (all power off and then on again).

Note ...

The USB host interfaces can be used with maximum 500 mA continuous load current as specified in the Universal Serial Bus Specification, Revision 2.0. Short-circuit protection is provided.

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2.10.3 Integrated Graphics Controller

The Intel® Core™ i7 processor includes a highly integrated graphics accelerator delivering high performance 3D, 2D graphics capabilities.

Integrated 2D/3D graphics:

• Intel® Dynamic Video Memory Technology

• Intel® Graphics Performance Modulation Technology

• Intel® Smart 2D Display Technology

• High-performance MPEG-2 decoding

• WMV9/VC1 Hardware acceleration

• Analog display support for resolution up to 2048 x 1536 pixels @ 60 Hz

2.10.3.1 Graphics Memory Usage

The Intel® Core™ i7 processor supports the Dynamic Video Memory Technology (Intel® DVMT) with up to 352 MB memory. This technology ensures the most efficient use of all available memory for maximum 3D graphics performance. DVMT dynamically responds to application requirements allocating display and texturing memory resources as required.

2.10.4 Serial Ports

The CP3002-RC/CP3002-RA provides two serial ports, COMA (RS-232) and COMB (RS-232/

RS-422), both available on the rear I/O.

COMA and COMB are fully compatible with the 16550 controller. The rear I/O COMA port includes a complete set of handshaking and modem control signals. The COMA and COMB ports provide maskable interrupt generation. The data transfer on the COM po rts is up to 1 15.2 kbit/s.

Note ...

The CP3002-RC/CP3002-RA provides two jumpers, JP1 and JP2, used to activate the bus termination for the RS-422 (COMB) port.

For further information on the JP1 and JP2 jumpers, refer to Chapter 4.2, Jumper Description.

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2.10.5 Gigabit Ethernet Interfaces

The CP3002-RC/CP3002-RA supports up to four Gigabit Ethernet interfaces using one Intel® 82580EB Quad Gigabit Ethernet controller. Four Gigabit Ethernet copper ports (1000BASETX) are connected to the rear I/O.

The Intel® 82580EB Quad Gigabit Ethernet controller is optimized to deliver high-performance data throughput with the lowest power consumption. The Ethernet controller is directly connected to the Intel® Core™ i7 processor chipset using one x4 PCI Express port. The controller supports auto-negotiation (automatic speed detection), auto MDI-X (automatic wire switching), and boot from LAN.

Network features of the Intel® 82580EB Quad Gigabit Ethernet controller include:

• Intel® I/O Acceleration Technology

• Message Signaled Interrupts (MSI)

• Support of Virtual Machines Device queues (VMDq) per port

• IEEE 1588 Precision Time Protocol support and per-packet timestamp

• Support of various manageability and power saving features

2.10.6 Serial ATA Interface

The CP3002-RC/CP3002-RA provides three SATA I (1.5 Gbit/sec) and SATA II (3.0 Gbit/sec) compliant interfaces with RAID support (0/1/5). One interface is used for the SATA Flash module and two SATA interfaces are available only on the rear I/O.

For further information on the SATA Flash Modu le, refer to Appendix A.

2.10.7 GPI and GPO Signals

The CP3002-RC/CP3002-RA provides five general purpose inputs (GPI) and three general purpose outputs (GPO) on the rear I/O connector J2.

2.10.8 Debug Interface

The CP3002-RC/CP3002-RA provides several onboard options for hardware and software debugging, such as:

• Four bicolor debug LEDs (DLED0..3), which indicate hardware failures, uEFI BIOS POST codes and user-configurable outputs

• One JTAG connector, J4, for programming the onboard logic

• One XDP-SFF, processor JTAG connector, J6, for facilitating the debug and uEFI BIOS software development

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2.10.9 CompactPCI Bus Interface

The CP3002-RC/CP3002-RA supports a 32-bit/33 MHz or 32-bit/66 MHz PCI interface with universal V(I/O) signaling voltages (3.3 V and 5 V) and is capable of driving up to four CompactPCI slots with individual arbitration and clock signals.

The CP3002-RC/CP3002-RA is not hot-swappable but supports the addition or removal of other boards whilst in a powered-up state.

2.10.10 CompactPCI Rear I/O Interface

The CP3002-RC/CP3002-RA board provides rear I/O connectivity for peripherals. The CP3002-RC/CP3002-RA can be operated only in a 3U CompactPCI backplane with maximum five slots and rear I/O support on the system slot.

The CP3002-RC/CP3002-RA rear I/O interface provides the following interfaces (all sig nals are available on J2):

• One COMA port (RS-232 signaling); no buffer on the rear I/O module (RTM) is necessary

• One COMB port (RS-232/RS-422 signaling); no buffer on the rear I/O module is necessary

• Two USB 2.0 port

• One VGA analog port

• Four Gigabit Ethernet ports; magnetics on the rear I/O module are necessary

•Two SATA ports

• Five GPIs and three GPOs (TTL signaling)

• Back-up voltage (3.3 V)

• Geographic addressing (GA[4..0])

Warning!

The CP3002-RC/CP3002-RA can be operated only in a 3U CompactPCI backplane with maximum five slots and rear I/O support on the system slot. Do not plug a rear I/O configured board in a backplane without rear I/O support. Failure to comply with the above will result in damage to your board.

Note ...

The pinout of the rear I/O CompactPCI connector on the CP3002-RC/CP3002RA is not compatible with that of the CP305, CP307, CP308, CP3002 etc. For this reason, only rear I/O modules specially designed for the CP3002-RC/ CP3002-RA can be used with the board.

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2.10.10.1 CompactPCI Connectors J1 and J2

The complete CompactPCI connector configuration comprises two connectors named J1 and J2.

Their function is as follows:

• J1: 32-bit CompactPCI interface with PCI bus signals, arbitration, clock and power

• J2: arbitration, clock and rear I/O interface functionality

The CP3002-RC/CP3002-RA is designed for a CompactPCI bus architecture. The CompactPCI standard is electrically identical to the PCI local bus. However, these systems are enhanced to operate in rugged industrial environments and to support multiple slots.

2.10.10.2 CompactPCI Connector Keying

CompactPCI backplane connectors support guide lugs to ensure a correct polarized mating (3.3 V or 5 V V(I/O) coding).

The CP3002-RC/CP3002-RA supports universal (3.3 V and 5 V) PCI V(I/O) signaling voltages with one common termination resistor configuration. Therefore, the CP300 2RC/CP3002-RA can be inserted in both, 3.3 V and 5 V CompactPCI systems and provides itself no guide lug.

EDCBA

F Z

Note:

Pinrow F: GND Pinrow Z: NC

Figure 2-1: CPCI Connectors

J1/J2

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2.10.10.3 CompactPCI Connectors J1 and J2 Pinouts

The CP3002-RC/CP3002-RA is provided with two 2 mm x 2 mm pitch female Comp actPCI bus connectors, J1 and J2.

Table 2-5: CompactPCI Bus Connector J1 System Controller Slot Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

25 NC 5V REQ64# ENUM# 3.3V 5V GND 24 NC AD[1] 5V V(I/O) AD[0] ACK64# GND 23 NC 3.3V AD[4] AD[3] 5V AD[2] GND 22 NC AD[7] GND 3.3V AD[6] AD[5] GND 21 NC 3.3V AD[9] AD[8] M66EN C/BE[0]# GND 20 NC AD[12] GND V(I/O) AD[11] AD[10] GND 19 NC 3.3V AD[15] AD[14] GND AD[13] GND 18 NC SERR# GND 3.3V PAR C/BE[1]# G ND 17 NC 3.3V IPMB SCL IPMB SDA GND PERR# GND 16 NC DEVSEL# PCIXCAP V(I/O) STOP# LOCK# GND 15 NC 3.3V FRAME# IRDY# BDSEL# TRDY# GND

12-14 Key Area

11 NC AD[18] AD[17] AD[16] GND C/BE[2]# GND 10 NC AD[21] GND 3.3V AD[20] AD[19] GND

9 NC C/BE[3]# NC AD[23] GND AD[22] GND 8 NC AD[26] GND V(I/O) AD[25] AD[24] GND 7 NC AD[30] AD[29] AD[28] GND AD[27] GND 6 NC REQ0# CPCI_PRESENT# 3.3V CLK0 AD[31] GND 5NCNC NC RST#GNDGNT0#GND 4 NC IPMB PWR HEALTHY# V(I/O) RSV RSV GND 3 NC INTA# INTB# INTC# 5V INTD# GND 2NCTCK5V TMSNC TDI GND 1 NC 5V NC TRST# NC 5V GND

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Legend for Table 2-6:

Table 2-6: Rear I/O CompactPCI Bus Connector J2 Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

22 NC GA4 GA3 GA2 GA1 GA0 GND 21 NC GPI4 GND USB1+ USB0+ USB1_PWR_5V GND 20 NC GPO1 GND USB1- USB0- USB0_PWR_5V GND 19 NC GND GND Back-up 3.3V GPI2 3.3V GND 18 NC IPC_DA+ IPC_DA- GPO0 IPD_DA+ IPD_DA- GND 17 NC IPC_DB+ IPC_DB- PRST# IPD_DB+ IPD_DB- GND 16 NC IPC_DC+ IPC_DC- DEG# GND IPD_DC+ GND 15 NC IPC_DD+ IPC_DD- FAL# GPI0 IPD_DC- GND 14 NC lPB_DA+ lPB_DA- IPD_DD+ lPB_DC+ lPB_DC- GND 13 NC lPB_DB+ lPB_DB- IPD_DD- lPB_DD+ lPB_DD- GND 12 NC lPA_DA+ lPA_DA- RSVD lPA_DC+ lPA_DC- GND 11 NC lPA_DB+ lPA_DB- COMA_RI# lPA_DD+ lPA_DD- GND 10 NC GND GND VGA_RED COMA_DSR # GND GND

9 NC SATA0TX+ COMA_RXD VGA_HSYNC COMB_RX+/

RXD

SATA1TX+ GND

8 NC SATA0TX- COMA_CTS# VG A_BLUE COMB_RX-/

CTS#

SATA1TX- GND

7 NC GND GND VGA_DDC_DATA GND GND GND 6 NC SATA0RX+ COMA_RTS# VGA_GREEN COMB_TX+/

RTS#

SATA1RX+ GND

5 NC SATA0RX- COMA_TXD VGA_VSYNC COMB_TX-/

TXD

SATA1RX- GND

4 NC VI/O 5V VGA_DDC _CLK COMA_DCD# COMA_DTR# GND 3 NC GPI1 GND GNT3# GPI3 GPO2 GND 2 NC CLK2 CLK3 SYSEN# GNT2# REQ3# GND 1 NC CLK1 GND REQ1# GNT1# REQ2# GND

SATAx Serial ATA port lPx Gigabit Ethernet copper port USBx USB interface and power VGAx VGA signals COMAx COMA port RS-232 COMBx COMB port RS-232 or RS-422 GPI/GPO General purpose input / general purpose output signals 5V/3.3V/VI/O Power signals Back-up 3.3V Back-up voltage GND Ground signal NC Not connected

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2.10.10.4 Rear I/O Pin Description

Serial Ports

The CP3002-RC/CP3002-RA provides two serial ports, COMA (RS-232) and COMB (RS-232/

RS-422), both available on the rear I/O CompactPCI connector J2.

Table 2-7: COMA and COMB Signal Description

PIN on J2 SIGNAL FUNCTION DRIVEN BY SIGNALING VOLTAGE

B5 COMA_TXD TXD serial port (COMA) CP3002-RC/-RA RS-232 level B9 COMA_RXD RXD serial port (COMA) RTM RS-232 level B8 COMA_CTS# CTS signal serial port (COMA) RTM RS-232 level B6 COMA_RTS# RTS signal serial port (COMA) CP3002-RC/-RA RS-232 level

D10 COMA_DSR# DSR signal serial port (COMA) RTM RS-232 level

D4 COMA_DCD# DCD signal serial port (COMA) RTM RS-232 level E4 COMA_DTR# DTR signal serial port (COMA) CP3002-RC/-RA RS-232 level

C11 COMA_RI# RI signal serial port (COMA) RTM RS-232 level

D5 COMB_TX-/TXD TXD serial port (COMB) CP3002-RC/-RA RS-232 level

TX- serial port (COMB) CP3002-RC/-RA RS-422 level

D9 COMB_RX+/RXD RXD serial port (COMB) RTM RS-232 level

RX+ serial port (COMB) RTM RS-422 level

D8 COMB_RX-/CTS# CTS signal serial port (COMB) RTM RS-232 level

RX- signal serial port (COMB) RTM RS-422 level

D6 COMB_TX+/RTS# RTS signal serial port (COMB) CP3002-RC/-RA R S-232 level

TX+ signal serial port (COMB) CP3002-RC/-RA RS-422 level

Note ...

COMB default configuration is RS-422. To select the RS-232 signaling voltage for COMB, refer to Table 4-8, Control Register 0 (0x282) or via the uEFI BIOS, "kboardconfig" command.

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Ethernet Interfaces

The CP3002-RC/CP3002-RA provides four 10Base-T/100Base-TX/1000Base-T Ethernet interfaces on the rear I/O CompactPCI connector J2.

Table 2-8: Gigabit Ethernet Signal Description

PIN on J2 SIGNAL FUNCTION DRIVEN BY SIGNALING VOLTAGE

A12 IPA_DA+ Media-dependent interface port A Bidirectional Analog B12 IPA_DA- Media-dependent interface port A Bidirectional Analog A11 IPA_DB+ Media-dependent interface port A Bidirectional Analog B11 IPA_DB- Media-dependent interface port A Bidirectional Analog D12 IPA_DC+ Media-dependent interface port A Bidirectional Analog E12 IPA_DC- Media-dependent interface port A Bidirectional Analog D11 IPA_DD+ Media-dependent interface port A Bidirectional Analog E11 IPA_DD- Media-dependent interface port A Bidirectional Analog A14 IPB_DA+ Media-dependent interface port B Bidirectional Analog B14 IPB_DA- Media-dependent interface port B Bidirectional Analog A13 IPB_DB+ Media-dependent interface port B Bidirectional Analog B13 IPB_DB- Media-dependent interface port B Bidirectional Analog D14 IPB_DC+ Media-dependent interface port B Bidirectional Analog E14 IPB_DC- Media-dependent interface port B Bidirectional Analog D13 IPB_DD+ Media-dependent interface port B Bidirectional Analog E13 IPB_DD- Media-dependent interface port B Bidirectional Analog A18 IPC_DA+ Media-dependent interface port C Bidirectional Analog B18 IPC_DA- Media-dependent interface port C Bidirectional Analog A17 IPC_DB+ Media-dependent interface port C Bidirectional Analog B17 IPC_DB- Media-dependent interface port C Bidirectional Analog A16 IPC_DC+ Media-dependent interface port C Bidirectional Analog B16 IPC_DC- Media-dependent interface port C Bidirectional Analog A15 IPC_DD+ Media-dependent interface port C Bidirectional Analog B15 IPC_DD- Media-dependent interface port C Bidirectional Analog D18 IPD_DA+ Media-dependent interface port D Bidirectional Analog E18 IPD_DA- Media-dependent interface port D Bidirectional Analog D17 IPD_DB+ Media-dependent interface port D Bidirectional Analog E17 IPD_DB- Media-dependent interface port D Bidirectional Analog E16 IPD_DC+ Media-dependent interface port D Bidirectional Analog E15 IPD_DC- Media-dependent interface port D Bidirectional Analog C14 IPD_DD+ Media-dependent interface port D Bidirectional Analog C13 IPD_DD- Media-dependent interface port D Bidirectional Analog

Note ...

The Ethernet magnetics must be placed on the rear I/O module or the backplane. The Ethernet magnetics center tap should not be connected to a power supply.

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Serial ATA Interfaces

The CP3002-RC/CP3002-RA provides two Serial ATA interfaces on the rear I/O CompactPCI connector J2.

USB Interfaces

Two USB 2.0 ports are available on the rear I/O CompactPCI connector J2.

VGA Interface

The CP3002-RC/CP3002-RA provides one VGA analog port on the rear I/O Co mpactPCI connector J2.

Table 2-9: Serial ATA Signal Description

PIN on J2 SIGNAL FUNCTION DRIVEN B Y SIGNALING VOLTAGE

A6 S ATA0RX+ Positive input port 0 RTM Differential A5 SATA0RX- Negative input port 0 RTM Differential A9 SATA0TX+ Positive output port 0 CP3002-RC/-RA Differential A8 SATA0TX- Negative output port 0 CP3002-RC/-RA Differential E6 S ATA1RX+ Positive input port 1 RTM Differential E5 SATA1RX- Negative input port 1 RTM Differential E9 SATA1TX+ Positive output port 1 CP3002-RC/-RA Differential E8 SATA1TX- Negative output port 1 CP3002-RC/-RA Differential

Table 2-10: USB Signal Description

PIN on J2 SIGNAL FUNCTION DRIVEN BY SIGNALING VOLTAGE

D21 USB0+ Positive USB port 0 Bidirectional Differential D20 USB0- Negative USB port 0 Bidirectional Differential E20 USB0_PWR_5V USB power supply 5 V port 0 CP3002-RC/-RA 5 V C21 USB1+ Positive USB port 1 Bidirectional Differential C20 USB1- Negative USB port 1 Bidirectional Differential E21 USB1_PWR_5V USB power supply 5 V port 1 CP3002-RC/-RA 5 V

Table 2-11: VGA Signal Description

PIN on J2 SIGNAL FUNCTION DRIVEN BY SIGNALING VOLTAGE

C10 VGA_RED VGA analog red signal CP3002-RC/-RA Analog

C6 VGA_GREEN VGA analog green signal CP3002-RC/-RA Analog C8 VGA_BLUE VGA analog blue signal CP3002-RC/-RA Analog C9 VGA_HSYNC V GA horizontal synchroniza-

tion signal

CP3002-RC/-RA LVTTL

C5 VGA_VSYNC VGA vertical synchronization

signal

CP3002-RC/-RA LVTTL

C4 VGA_DDC_CLK Monitor control clock signal CP3002-RC/-RA TTL (5 V) C7 VGA_DDC_DATA Monitor control data signal Bidirectional TTL (5 V)

Note ...

The CP3002-RC/CP3002-RA provides 75 Ω termination resistors for the red, green and blue VGA signals. Thus, further termination resistors are not necessary on the rear I/O module.

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General Purpose Inputs/Output s

The CP3002-RC/CP3002-RA provides five general purpose inputs (GPI) and three general purpose outputs (GPO) on the rear I/O CompactPCI connector J2.

Power Signals

The CP3002-RC/CP3002-RA provides three power signals on the rear I/O CompactPCI connector J2.

For further information regarding the rear I/O signals, please contact Kontron.

2.10.11 CompactPCI Grounding Configuration

Table 2-12: GPI/GPO Signal Description

PIN on J2 SIGNAL FUNCTION DRIVEN BY SIGNALING VOLTAGE

D15 GPI0 General purpose input 0 RTM LVTTL (3.3 V)

A3 GPI1 General purpose input 1 RTM LVTTL (3.3 V)

D19 GPI2 General purpose input 2 RTM LVTTL (3.3 V)

D3 GPI3 General purpose input 3 RTM LVTTL (3.3 V) A21 GPI4 General purpose input 4 RTM LVTTL (3.3 V) C18 GPO0 General purpose output 0 CP3002-RC/-RA LVTTL (3.3 V) A20 GPO1 General purpose output 1 CP3002-RC/-RA LVTTL (3.3 V)

E3 GPO2 General purpose output 2 CP3002-RC/-RA LVTTL (3.3 V)

Note ...

The GPI signals tolerate only 3.3 V signaling and the inputs have internal pullup resistors.

Table 2-13: Power Signal Description

PIN on J2 SIGNAL FUNCTION DRIVEN BY SIGNALING VOLTAGE

B4 5V Power supply 5 V Backplane 5 V E19 3.3V Power supply 3.3 V Backplane 3.3 V

A4 VI/O Power supply VI/O Backplane 5 V or 3.3 V C19 Back-up 3.3V Back-up power supply 3.3 V Backplane 3.3 V C12 RSVD Reserved CP3002-RC/-RA --

Warning!

Pin C12 MUST NOT be connected to any signal, either within the backplane itself or within a rear I/O module.

Failure to comply with the above will result in damage to your board.

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P R E L I M I N A R Y

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3. Installation

The CP3002-RC/CP3002-RA has been designed for easy installation. However, the following standard precautions, installation procedures, and general information must be observed to ensure proper installation and to preclude damage to the board, other system co mponent s, or injury to personnel.

3.1 Safety Requirements

The following safety precautions must be observed when installing or operating the CP3002RC/CP3002-RA. Kontron assumes no responsibility for any damage resulting from failure to comply with these requirements.

Warning!

Due care should be exercised when handling the board due to the fact tha t the heat sink can get very hot. Do not touch the heat sink when installing or removing the board.

In addition, the board should not be placed on any surface or in any form of storage container until such time as the board and heat sink have cooled down to room temperature.

Caution!

If your board type is not specifically qualified as being hot swap capable, switch off the CompactPCI system power before installing the board in a free CompactPCI slot. Failure to do so could endanger your life or health and may damage your board or system.

Note...

Certain CompactPCI boards require bus master and/or rear I/O capability. If you are in doubt whether such features are required for the board you intend to install, please check your specific board and/or system documentation to make sure that your system is provided with an appropriate free slot in which to insert the board.

ESD Equipment!

This CompactPCI board contains electrostatically sensitive devices. Please observe the necessary precautions to avoid damage to your board:

• Discharge your clothing before touching the assembly . Tools must be discharged before use.

• Do not touch components, connector-pins or traces.

• If working at an anti-static workbench with professional discharging equipment, please do not omit to use it.

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3.2 Initial Installation Procedures for the CP3002-RC

The following procedures are applicable only for the initial installation of the CP3002-RC in a system. Procedures for standard removal of the CP3002-RC are found in their respective chapters.

To perform an initial installation of the CP3002-RC in a system, proceed as follows:

1. Ensure that the safety requirements indicated Chapter 3.1 are observed.

2. Ensure that the board is properly configured for operation in accordance with application requirements before installing. For information regarding the configuration of the CP3002-RC

refer to Chapter 4. For the installation of

CP3002-RC

specific peripheral de-

vices and rear I/O

devices refer to the appropriate sections in Chapter 3.

3. To install the CP3002-RC perform the following:

1. Ensure that no power is applied to the system before proceeding.

2. Ensure that the extractor handle retaining screw is properly fastened.

3. Before inserting the board in the system chassis, ensure that both the top and bottom

wedge-locks are fully relaxed. To relax the wedge-lock, turn the wedge-lock’s screw counter-clockwise using a

2.5 mm hex key until the screw is against the stop. The screw should turn lightly. If, when turning the screw, p erceptible resistance is encountered, it is at the stop. Do not apply more force than necessary.

4. Carefully insert the board into the slot designated by the application requirements for

the board until it makes contact with the backplane connectors.

Warning!

To operate the CP3002-RC, 3U CompactPCI backplane with maximum five slots and rear I/O support on the system slot is required. Do not plug a rear I/O configured board in a backplane without rear I/O support. Failure to comply with the above will result in damage to your board.

Warning!

Failure to comply with the instruction below may cause damage to the board or result in improper system operation.

Warning!

Care must be taken when applying the procedures below to ensure that neither the CP3002-RC nor other system boards are physically damaged by the application of these procedures.

Note ...

In ruggedized systems, the slot tolerances are very narrow. In the event the board jams during insertion, remove it and ensure that both wedgelocks are fully relaxed before proceeding with insertion. The board should allow insertion to the point of contact with the backplane connectors without applying undo force.

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5. Using both hands, steadily apply enough force on the top and bottom of the front surface of the board to engage it with the backplane.

6. Complete securing of the board by expanding the top and bottom wedge-locks. This is done using a torque screwdriver with a 2.5 mm hex socket head. The recommended torque value is 0.8 N-m (115 oz-in).

The CP3002-RC is now ready for initial operation. For operation of the CP3002-RC, refer to the appropriate CP3002-RC-specific software, application, and system documentation.

Note ...

The chassis of ruggedized systems do not necessarily provide an objective means of determining when the board is properly seated in the backplane. During insertion it is possible however, to sense when the board “gives way” and seats into the connector. At this point, the application of more force does not result in further movement of the board.

In the event more boards are installed in a chassis, it is possible to compare the board’s front plane with the other b oards. If they are all even with one another, then they are all properly seated.

If in doubt that the board is properly seated, remove it and repeat steps 3 and 4 above.

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3.3 Standard Removal Procedures for the CP3002-RC

To remove the board proceed as follows:

1. Ensure that the safety requirements indicated in Chapter 3.1 are observed. Particular attention must not only be paid to the warning regarding the heat sink, bu t the user must also be aware that the surrounding system components and chassis can get very hot!

2. Ensure that no power is applied to the system before proceeding.

3. Unfasten the ejector handle retaining screw.

4. Ensure that both the top and bottom wedge-locks are fully relaxed. To relax the wedge-lock, turn the wedge-lock’s screw counter-clockwise using a 2.5 mm

hex key until the screw is against the stop.

5. Disengage the board from the backplane using the ejector handle as required until the board is disengaged from the backplane.

6. After disengaging the board from the backplane, pull the board out of the slot.

7. Ensure that the ejector handle retaining screw is properly fastened.

8. Dispose of the board as required.

Warning!

Care must be taken when applying the procedures below to ensure that neither the CP3002-RC nor system boards are physically damaged by the application of these procedures.

Warning!

Due care should be exercised when handling the board due to the fact that the heat sink can get very hot - danger of burns. In a ddition, the surrou nding system components and chassis may be very hot.

If required, use protective gloves to handle the CP3002-RC when removing it.

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3.4 Initial Installation Procedures for the CP3002-RA

The following procedures are applicable only for the initial installation of the CP3002-RA in a system. Procedures for standard removal operations are found in their respective chapters.

To perform an initial installation of the CP3002-RA in a system proceed as follows:

1. Ensure that the safety requirements indicated in Chapter 3.1 are observed.

2. Ensure that the board is properly configured for operation in accordance with application requirements before installing. For information regarding the configuration of the CP3002-RA refer to Chapter 4. For the installation of CP3002-RA-specific peripheral devices and Rear I/O devices refer to the appropriate sections in Chapter 3.

3. To install the CP3002-RA perform the following:

1. Ensure that no power is applied to the system before proceeding.

2. Carefully insert the board into the slot designated by the application requirements for

the board until it makes contact with the backplane connectors.

Warning!

The CP3002-RA provides no ESD discharge strips. Always ensure that the CP3002-RA is discharged prior to installation in a CompactPCI backplane. Failure to comply with this instruction may cause damage to the board or result in improper system operation.

Warning!

On the CP3002-RA, the chassis ground and the digital ground are not isolated due to the direct mounting of the front panel to the heat sink. Thus, the CP3002-RA can be operated only in a system with common grounding. Failure to comply with this instruction may cause damage to the board or result in improper system operation.

Warning!

Failure to comply with the instruction below may cause damage to the board or result in improper system operation.

Warning!

Care must be taken when applying the procedures below to ensure that neither the CP3002-RA nor other system boards are physically damaged by the application of these procedures.

Warning!

When performing the next step, DO NOT push the board into the backplane connectors. Use the ejector handle to seat the board into the backplane connectors.

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3. Using the ejector handle, engage the board with the backplane. When the ejector handle is locked, the board is engaged.

4. Fasten the front panel retaining screws. The CP3002-RA is now ready for initial operation. For operation of the CP3002-RA,

refer to the appropriate CP3002-RA-specific software, application, and system documentation.

3.5 Standard Removal Procedures for the CP3002-RA

To remove the board proceed as follows:

1. Ensure that the safety requirements indicated in Chapter 3.1 are observed. Particular attention must be paid to the warning regarding the heat sink!

2. Ensure that no power is applied to the system before proceeding.

3. Unscrew the front panel retaining screws.

4. Disengage the board from the backplane by first unlocking the board ejection handle and then by pressing the handle as required until the board is disengaged.

5. After disengaging the board from the backplane, pull the board out of the slot.

6. Dispose of the board as required.

3.6 Hot Swap Procedures

The CP3002-RC/CP3002-RA is not designed for hot swap operation. Do not attempt the hot swap this board. However, the CP3002-RC/CP3002-RA supports the addition or removal of other boards whilst in a powered-up state.

3.7 Installation of CP3002-RC/CP3002-RA Peripheral Devices

The CP3002-RC/CP3002-RA is designed to accommodate a Serial ATA Flash module. The following figure shows the placement of the SATA Flash module on the CP3002-RC and the CP3002-RA.

Warning!

Care must be taken when applying the procedures below to ensure that neither the CP3002-RA nor system boards are physically damaged by the application of these procedures.

Warning!

Due care should be exercised when handling the board due to the fact that the heat sink can get very hot. Do not touch the heat sink when changing the board.

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Figure 3-1: CP3002-RC with SATA Flash Module

Figure 3-2: CP3002-RA with SATA Flash Module

SATA Flash

Module

SATA Flash

Module

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The following sections provide information regarding installation aspects of peripheral devices.

3.7.1 SATA Flash Module Installation

SATA Flash module may be connected to the

CP3002-RC/CP3002-RA

via the onboard con-

nector, J3. This optionally available module must be physically installed on the CP3002-RC/CP3002-RA

prior to installation of the CP3002-RC/CP3002-RA in a system. During installation it is necessary to ensure that the SATA Flash module is properly seated in

the onboard connector J3, i.e. the pins are aligned correctly and not bent.

3.7.2 Rear I/O Device Installation

For physical installation of rear I/O devices, refer to the documentation pro vided with the device itself.

3.8 Software Installation

The installation of the Ethernet and all other onboard peripheral drivers is described in detail in the relevant Driver Kit files.

Installation of an operating system is a function of the OS sof tware and is not addressed in this manual. Refer to appropriate OS software documentation for installation.

Note ...

Only qualified SATA Flash modules from Kontron are authorized for use with the CP3002-RC/CP3002-RA. Failure to comply with the above will void the warranty and may result in damage to the board or the system.

Note ...

Users working with pre-configured operating system installation images for Plug and Play compliant operating systems, for example Windows® XP, Windows® XP Embedded, must take into consideration that the stepping and revision ID of the chipset and/or other onboard PCI devices may change. Thus, a re-configuration of the operating system installation image deployed for a previous chipset stepping or revision ID is in most cases required. The corresponding operating system will detect new devices according to the Plug and Play configuration rules.

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4. Configuration

4.1 Jumper Description

The CP3002-RC/CP3002-RA has four jumpers JP1, JP2, JP3 and JP4. JP1 and JP2 are used to activate the bus termination for COMB (RS-422). JP3 is used for clearing the uEFI BIOS boot settings. JP4 is used for uEFI BIOS boot configuration. For the location of the jumpers, refer to Figure 1-4.

4.1.1 COMB (RS-422) Termination Jumper Settings (JP1 and JP2)

When COMB is used and is the last device on the RS-422 bus, then the RS-422 interface must provide termination resistance. The purpose of the jumpers JP1 and JP2 is to enable this line termination resistor (120 ohm).

The default setting is indicated by using italic bold.

4.1.2 uEFI BIOS Configuration Jumper Settings (JP3 and JP4)

The default setting is indicated by using italic bold. To clear the uEFI BIOS settings, proceed as follows:

1. Close jumper JP3.

2. Apply power to the system.

3. After successful boot from uEFI BIOS, remove power from the system.

4. Open jumper JP3.

Table 4-1: JP1 Jumper Setting for RS-422 RXD Termination (COMB)

JP1 DESCRIPTION

Open RXD termination inactive

Closed RXD termination active (soldered jumper or 0 ohm resistor in 0805 package)

Table 4-2: JP2 Jumper Setting for RS-422 TXD Termination (COMB)

JP2 DESCRIPTION

Open TXD termination inactive

Closed TXD termination active (soldered jumper or 0 ohm resistor in 0805 package)

Table 4-3: uEFI BIOS Boot Settings Jumper (JP3)

JP3 DESCRIPTION

Open Boot using the currently saved uEFI BIOS settings

Closed Clear the uEFI BIOS settings and use the default values

Table 4-4: uEFI BIOS Boot Configuration Jumper (JP4)

JP4 DESCRIPTION

Open Boot from default SPI Flash

Closed Boot from the alternative SPI Flash

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The default setting is indicated by using italic bold.

4.2 I/O Address Map

The following table indicates the CP3002-RC/CP3002-RA-specific registers.

Table 4-5: I/O Address Map

ADDRESS DEVICE

0x080 - uEFI BIOS POST Code Low Byte Register (POSTL)

0x081 uEFI BIOS POST Code High Byte Register (POSTH)

0x082 - 0x083 Reserved

0x084 Debug Low Byte Register (DBGL) 0x085 Debug High Byte Register (DBGH) 0x280 Status Register 0 (STAT0) 0x281 Status Register 1 (STAT1) 0x282 Control Register 0 (CTRL0) 0x283 Control Register 1 (CTRL1) 0x284 Device Protection Register (DPROT) 0x285 Reset Status Register (RSTAT) 0x286 Board Interrupt Configuration Register (BICFG) 0x287 Status Register 2 (STAT2) 0x288 Board ID High Byte Register (BIDH) 0x289 Board and PLD Revision Register (BREV) 0x28A Geographic Addressing Register (GEOAD) 0x28B Reserved 0x28C Watchdog Timer Control Register (WTIM) 0x28D Board ID Low Byte Register (BIDL)

0x28E - 0x28F Reserved

0x290 Debug LED Configuration Register (DLCFG) 0x291 Debug LED Control Register (DLCTRL) 0x292 General Purpose Output Register (GPOUT) 0x293 General Purpose Input Register (GPIN)

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4.3 CP3002-RC/CP3002-RA-Specific Registers

The following registers are special registers which the CP3002-RC/CP3002-RA uses t o watch the onboard hardware special features and the CompactPCI control signals.

Normally, only the system uEFI BIOS uses these registers, but they are documented here for application use as required.

4.3.1 Status Register 0 (STAT0)

The Status Register 0 holds general/common status information.

Note ...

Take care when modifying the contents of these registers as the system uEFI BIOS may be relying on the state of the bits under its control.

Table 4-6: Status Register 0 (STAT0)

ADDRESS 0x280

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 Res. Reserved 0 R 6 BBEI uEFI BIOS boot end indication:

0 = uEFI BIOS is booting 1 = uEFI BIOS boot is finished

5 - 4 BFSS Boot Flash selection status:

00 = Primary boot Flash active 01 = Secondary boot Flash active 10 = External boot Flash active 11 = R es erve d

N/A R

3 DIP4 uEFI BIOS boot settings jumper, JP3

0 = Clear uEFI BIOS settings and use the default values 1 = Boot using the currently saved uEFI BIOS settings

N/A R

2 Res. Reserved 0 R 1 DIP2 uEFI BIOS boot configuration jumper, JP4

0 = Boot from alternative SPI Flash 1 = Boot from default SPI Flash

N/A R

0 Res. Reserved 0 R

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4.3.2 Status Register 1 (STAT1)

The Status Register 1 holds board-specific status information.

Table 4-7: Status Register 1 (STAT1)

ADDRESS 0x281

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 C66EN CPCI PCI speed (M66EN signal):

0 = 33 MHz 1 = 66 MHz

N/A R

6 - 4 Res. Reserved 000 R

3 CSYS CPCI system slot identification (SYSEN signal):

0 = Installed in a system slot

1 = Installed in a peripheral slot (the board is not intended to be operated in a peripheral slot)

N/A R

2 CENUM CPCI system enumeration (ENUM signal):

0 = Indicates the insertion or removal of a hot swap peripheral board 1 = No hot swap event

N/A R

1 CFAL CPCI power supply status (FAL signal):

0 = Power supply failure 1 = Power in normal state

0 CDEG CPCI power supply status (DEG signal):

0 = Power derating 1 = Power in normal state

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4.3.3 Control Register 0 (CTRL0)

The Control Register 0 holds one bit for specifying the boot Flash to be updated.

4.3.4 Control Register 1 (CTRL1)

The Control Register 1 holds board-specific control information.

Table 4-8: Control Register 0 (CTRL0)

ADDRESS 0x282

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 - 6 Res. Reserved 00 R

5 BFUS Boot Flash update selection:

0 = Select default boot Flash for update 1 = Select alternative boot Flash for update

0R/W

3 - 2 CPMC2 COMB port mode configuration:

00 = RS-232 mode 01 = RS-422 mode 10 = Reserved 11 = Re serv ed

01 R/W

1 - 0 Res. Reserved 00 R

Table 4-9: Control Register 1 (CTRL1)

ADDRESS 0x283

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 SRST SATA Flash module configuration:

0 = Reset of SATA Flash module 1 = SATA Flash module running

1R/W

6 VRST Integrated graphics controller configuration:

0 = Graphics controller disabled 1 = Graphics controller enabled

5 TRST Trusted Platform Module (TPM) configuration:

0 = TPM disabled 1 = TPM enabled

1R/W

4 - 0 Res. Reserved 00000 R

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4.3.5 Device Protection Register (DPROT)

The Device Protection Register holds the write protect signals for Flash devices.

Table 4-10: Device Protection Register (DPROT)

ADDRESS 0x284

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 - 3 Res. Reserved 00000 R

2 SFWP SATA Flash module write protection:

0 = SATA Flash module not write protected 1 = SATA Flash module write protected Writing a ’1’ to this bit sets the bit. If this bit is set, it cannot be cleared.

0R/W

1 EEWP EEPROM write protection:

0 = EEPROM not write protected 1 = EEPROM write protected Writing a ’1’ to this bit sets the bit. If this bit is set, it cannot be cleared.

0R/W

0 BFWP Boot Flash write protection:

0 = Boot Flash not write protected 1 = Boot Flash write protected Writing a ’1’ to this bit sets the bit. If this bit is set, it cannot be cleared.

0R/W

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4.3.6 Reset Status Register (RSTAT)

The Reset Status Register is used to determine the host’s reset source.

Table 4-11: Reset Status Register (RSTAT)

ADDRESS 0x285

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 P ORS Power-on reset status:

0 = System reset generated by software (warm reset) 1 = System reset generated by power-on (cold reset)

Writing a ’1’ to this bit clears the bit.

N/A R/W

6 - 2 Res. Reserved 00000 R

1 CPRS CompactPCI reset status (PRST signal):

0 = System reset not generated by CPCI reset input 1 = System reset generated by CPCI reset input

Writing a ’1’ to this bit clears the bit.

0R/W

0 WTRS Watchdog timer reset status:

0 = System reset not generated by Watchdog timer 1 = System reset generated by Watchdog timer

Writing a ’1’ to this bit clears the bit.

0R/W

Note ...

The reset status register is set to the default values by power-on reset, not by a warm reset.

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4.3.7 Board Interrupt Configuration Register (BICFG)

The Board Interrupt Configuration Register holds a series of bits defining the interrupt routing.

Table 4-12: Board Interrupt Configuration Register (BICFG)

ADDRESS 0x286

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 UICF UART IRQ3 and IRQ4 interrupt configuration:

0 = Disabled 1 = Enabled

1R/W

6 CFICF CPCI fail signal interrupt configuration (FAL signal):

0 = IRQ5 disabled 1 = IRQ5 enabled

0R/W

5 CEICF CPCI enumeration signal interrupt configuration (ENUM signal):

0 = IRQ5 disabled 1 = IRQ5 enabled

0R/W

4 CDICF CPCI derate signal interrupt configuration (DEG signal):

0 = IRQ5 disabled 1 = IRQ5 enabled

0R/W

3 - 2 Res. Reserved 00 R 1 - 0 WICF Watchdog interrupt configuration:

00 = Disabled 01 = IRQ5 10 = Reserved 11 = R eser ve d

00 R/W

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4.3.8 Status Register 2 (STAT2)

The Status Register 2 holds status information related to the rear I/O configuration.

4.3.9 Board ID High Byte Register (BIDH)

Each Kontron board is provided with a unique 16-bit board-type identifier in the form of a hexadecimal number. The Board ID High Byte Register is located in the address 0x288. The Board ID Low Byte Register is located in the address 0x28D.

4.3.10 Board and PLD Revision Register (BREV)

The Board and PLD Revision Register signals to the software when differences in the board and the Programmable Logic Device (PLD) require different handling by the software. It starts with the value 0x00 and will be incremented with each change in hardware as development continues.

Table 4-13: Status Register 2 (STAT2)

ADDRESS 0x287

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 - 6 Res. Reserved 00 R 5 - 4 RCFG Rear I/O configuration:

00 = Reserved 01 = COMA, COMB, GPIO 10 = Reserved 11 = R es erve d

01 R

3 - 0 Res. Reserved 0000 R

Table 4-14: Board ID High Byte Register (BIDH)

ADDRESS 0x288

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 - 0 BIDH Board identification:

CP3002-RC/CP3002-RA: 0xB330

0xB3 R

Table 4-15: Board and PLD Revision Register (BREV)

ADDRESS 0x289

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 - 4 BREV Board revision N/A R 3 - 0 PREV PLD revision N/A R

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4.3.11 Geographic Addressing Register (GEOAD)

This register holds the CompactPCI geographic address.

Table 4-16: Geographic Addressing Register (GEOAD)

ADDRESS 0x28A

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 - 5 Res. Reserved 000 R 4 - 0 GA Geographic address N/A R

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4.3.12 Watchdog Timer Control Register (WTIM)

The CP3002-RC/CP3002-RA has one Watchdog timer provided with a programmable timeout ranging from 125 msec to 4096 sec. Failure to strobe the Watchdog timer within a set time period results in a system reset or an interrupt. The interrupt mode can be configured via the Board Interrupt Configuration Register (0x286).

There are four possible modes of operation involving the Watchdog timer:

• Timer only mode

• Reset mode

• Interrupt mode

• Dual stage mode

At power on the Watchdog is not enabled. If not required, it is not necessary to enable it. If required, the bits of the Wat chdog Timer Control Register must be set according to the application requirements. To operate the Watchdog, the mode and time period required must first be set and then the Watchdog enabled. Once enabled, the Watchdog can only be disabled or the mode changed by powering down and then up again. To prevent a Watchdog timeout, the Watchdog must be retriggered before timing out. This is done by writing a ’1 ’ to the WTR bit. In the event a Watchdog timeout does occur, the WTE bit is set to ’1’. What transpires after this depends on the mode selected.

The four operational Watchdog timer modes can be configured by the WMD[1:0] bits, and are described as follows:

Timer only mode - In this mode the W atchdog is enabled using the required timeout period. Normally , the W atchdog is ret riggered by writing a ’1’ t o the WTR bit. In the event a timeout occurs, the WTE bit is set to ’1’. This bit can then be polled by the application and handled accordingly . To continue using the Watchdog, write a ’1’ to the WTE bit, and then retrigger the Watchdog using WTR. The WTE bit retains its setting as long as no power down-up is done. Therefore, this bit may be used to verify the status of the Watchdog.

Reset mode - This mode is used to force a hard reset in the event of a Watchdog timeout. In addition, the WTE bit is not reset by the hard reset, which makes it available if necessary to determine the status of the Watchdog prior to the reset.

Interrupt mode - This mode causes the generation of an interrupt in the event of a Watchdog timeout. The interrupt handling is a function of the application. If required, the WTE bit can be used to determine if a Watchdog timeout has occurred.

Dual stage mode - This is a complex mode where in the event of a timeout two things o ccur: 1) an interrupt is generated, and 2) the Watchdog is retriggered automatically. In the event a second timeout occurs immediately following the first timeout, a hard reset will be generated. If the Watchdog is retriggered normally, operation continues. The interrupt generated at the first timeout is available to the application to handle the first timeout if required. As with all of the other modes, the WTE bit is available for application use.

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Table 4-17: Watchdog Timer Control Register (WTIM)

ADDRESS 0x28C

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 WTE Watchdog timer expired status bit

0 = Watchdog timer has not expired 1 = Watchdog timer has expired.

Writing a ’1’ to this bit resets it to 0.

0R/W

6 - 5 WMD Watchdog mode

00 = Timer only mode 01 = Reset mode 10 = Interrupt mode 11 = Cascaded mode (dual-stage mode)

00 R/W

4 WEN/WTR Watchdog enable/Watchdog trigger control bit:

0 = Watchdog timer not enabled

Prior to the Watchdog being enabled, this bit is known as WEN. After the Watchdog is enabled, it is known as WTR. Once the Watchdog timer has been enabled, this bit cannot be reset to 0. As long as the Watchdog timer is enabled, it will indicate a ’1’.

1 = Watchdog timer enabled

Writing a ’1’ to this bit causes the Watchdog to be retriggered to the timer value indicated by bits WTM[3:0].

0R/W

3 - 0 WTM Watchdog timeout settings:

0000 = 0.125 s 0001 = 0.25 s 0010 = 0.5 s 0011 = 1 s 0100 = 2 s 0101 = 4 s 0110 = 8 s 0111 = 16 s 1000 = 32 s 1001 = 64 s 1010 = 128 s 1011 = 256 s 1100 = 512 s 1101 = 1024 s 1110 = 2048 s 1111 = 4096 s

0000 R/W

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4.3.13 Board ID Low Byte Register (BIDL)

Each Kontron board is provided with a unique 16-bit board-type identifier in the form of a hexadecimal number. The Board ID Low Byte Register is located in the address 0x28D. The Board ID High Byte Register is located in the address 0x288.

Table 4-18: Board ID Low Byte Register (BIDL)

ADDRESS 0x28D

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7 - 0 BIDL Board identification:

CP3002-RC/CP3002-RA: 0xB330

30 R

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4.3.14 Debug LED Configuration Register (DLCFG)

The Debug LED Configuration Register holds a series of bits defining the onboard configuration of the onboard debug LEDs (DLED 0..3). For the location of the debug LEDs, refer to Figure 1-4.

In uEFI BIOS POST mode, the Debug LEDs build a binary vector to display uEFI BIOS POST code during the pre-boot phase. In doing so, the higher 4-bit nibble of the 8-bit uEFI BIOS POST code is displayed followed by the lower nibble followed by a pause. uEFI BIOS POST code is displayed in general in green color.

DLED3: POST bit 3 and bit 7 (green) DLED2: POST bit 2 and bit 6 (green) DLED1: POST bit 1 and bit 5 (green) DLED0: POST bit 0 and bit 4 (green)

Configured for Mode A (General Purpose Mode), the Debug LEDs are dedicated to functions as follows:

DLED3: Debug LED 3, controlled by host (green /red) DLED2: Debug LED 2, controlled by host (green /red) DLED1: Debug LED 1, controlled by host (green /red) DLED0: Debug LED 0, controlled by host (green /red)

Configured for Mode B, the Debug LEDs are dedicated to functions as follows: DLED3: Gigabit Ethernet port D link status (green)

DLED2: Gigabit Ethernet port C link status (green) DLED1: Gigabit Ethernet port B link status (green) DLED0: Gigabit Ethernet port A link status (green)

Beside the configurable functions described above, the Debug LEDs fulfill also a basic debug function during the power-up phase as long as the first access to Port 80 is processed. If an LED lights red and stays red, than a basic error is present on the board. The following debug functions are defined and displayed during this initialization phase.

DLED3: PGOOD, Power Good status not reached (red) DLED2: CPU catastrophic error (red) DLED1: RST, PCI reset active / not deactivated (red) DLED0: uEFI BIOS boot failure (red)

Table 4-19: Debug LED Configuration Register (DLCFG)

ADDRESS 0x290

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7-4 Res. Reserved 0000 R 3-0 DLCON Debug LED Configuration

0000 = POST

0001 = Mode A (General Purpose Mode)

0010 = Mode B

0011 - 1111 = Re se rv e d

0001 R/W

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4.3.15 Debug LED Control Register (DLCTRL)

This register is used to switch on and off the Debug LEDs.

Table 4-20: Debug LED Control Register (LCTRL)

ADDRESS 0x291

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7-4 DLCMD Debug LED command:

0000 = Get DLED 0 0001 = Get DLED 1 0010 = Get DLED 2 0011 = Get DLED 3 0100 - 0111 = Reserved 1000 = Set DLED 0 1001 = Set DLED 1 1010 = Set DLED 2 1011 = Set DLED 3 1100 - 1111 = Re se rv e d

0000 R/W

3-0 DLCOL Debug LED color:

0000 = Off 0001 = Green 0010 = Red 0011 = Red+green 0100 - 1111 = R es erve d

0000 R/W

Note ...

This register can only be used if the Debug LEDs indicated in the “Debug LED Configuration Register” (Table 4-18) are configured in Mode A.

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4.3.16 General Purpose Output Register (GPOUT)

This register is used to control the general purpose output signals on the rear I/O Comp actPCI connector J2.

4.3.17 General Purpose Input Register (GPIN)

This register is used to control the general purpose input signals on the rear I/O CompactPCI connector J2.

Table 4-21: General Purpose Output Register (GPOUT)

ADDRESS 0x292

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7-3 Res. Reserved 00000 R

2 GPO2 General Purpose Output 2:

0 = Output low 1 = Output high

0R/W

1 GPO1 General Purpose Output 1:

0 = Output low 1 = Output high

0R/W

0 GPO0 General Purpose Output 0:

0 = Output low 1 = Output high

0R/W

Table 4-22: General Purpose Input Register (GPIN)

ADDRESS 0x293

BIT NAME DESCRIPTION

RESET VALUE

ACCESS

7-5 Res. Reserved 000 R

4 GPI4 General P urpose Input 4:

0 = Input low 1 = Input high

3 GPI3 General P urpose Input 3:

0 = Input low 1 = Input high

2 GPI2 General P urpose Input 2:

0 = Input low 1 = Input high

1 GPI1 General P urpose Input 1:

0 = Input low 1 = Input high

0 GPI0 General P urpose Input 0:

0 = Input low 1 = Input high

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5. Power Considerations

5.1 System Power

The considerations presented in the ensuing chapters must be taken into account by system integrators when specifying the CP3002-RC/CP3002-RA system environment.

5.1.1 CP3002-RC/CP3002-RA Baseboard

The CP3002-RC/CP3002-RA baseboard itself has been designed for optimal power input and distribution. Still it is necessa ry to observe certain criteria essential for application stability and reliability.

The table below indicates the absolute maximum input voltage ratings that must not be exceeded. Power supplies to be used with the CP3002-RC/CP3002-RA should be carefully tested to ensure compliance with these ratings.

The following table specifies the ranges for the different input power voltages within which the board is functional. The CP3002-RC/CP3002-RA is not guaranteed to function if the board is not operated within the prescribed limits.

Table 5-1: Maximum Input Power Voltage Limits

SUPPLY VOLTAGE

MAXIMUM PERMITTED

VOLTAGE

3.3 V 3.6 V 5 V 5.5 V

Warning!

The maximum permitted voltage indicated in the table above must not be exceeded. Failure to comply with the above may result in damage to your board.

Table 5-2: DC Operational Input Voltage Ranges

INPUT SUPPLY

VOLTAGE

ABSOLUTE RANGE RECOMMENDED RANGE

3.3 V 3.2 V min. to 3.47 V max. 3.3 V min. to 3.47 V max. 5 V 4.85 V min. to 5.25 V max. 5.0 V min. to 5.25 V max.

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5.1.2 Backplane

Backplanes to be used with the CP3002-RC/CP3002-RA must be adequately specified. The backplane must provide optimal power distribution for the 3.3 V and 5 V power inputs.

Input power connections to the backplane itself should be carefully specified to ensure a minimum of power loss and to guarantee operational stability. Long input lines, under-dimensioned cabling or bridges, high resistance connections, etc. must be avoided. It is recommended to use POSITRONIC or M-type connector backplanes and power supplies where possible.

5.1.3 Power Supply Units

Power supplies for the CP3002-RC/CP3002-RA must be specified with enough reserve for the remaining system consumption. In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires.

As the design of the CP3002-RC/CP3002-RA has been optimized for minimal power consumption, the power supply unit shall be stable even without minimum load.

Where possible, power supplies which support voltage sensing should be used. Depending on the system configuration this may require an appropriate backplane. The power supply should be sufficient to allow for backplane input line resistance variations due to temperature changes, etc.

5.1.3.1 Start-Up Requirement

Power supplies must comply with the following guidelines, in order to be used with the CP3002RC/CP3002-RA:

• Beginning at 10% of the nominal output voltage, the voltage must rise within > 0.1 ms to < 20 ms to the specified regulation range of the voltage. Typically: > 5 ms to < 15 ms.

• There must be a smooth and continuous ramp of each DC output voltage from 10% to 90% of the regulation band.

• The slope of the turn-on waveform shall be a positive, almost linear voltage increase and have a value from 0 V to nominal Vout.

5.1.3.2 Power-Up Sequence

The 5 V output level must always be equal to or higher than the 3.3 V output during power-up and normal operation. Both voltages must reach their minimum in-regulation level not later than 20 ms after the output power ramp start.

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5.1.3.3 Regulation

The power supply shall be unconditionally stable under line, load, unload and transient load conditions including capacitive loads. The operation of the power supply must be consistent even without the minimum load on all output lines.

Warning!

All of the input voltages must be functionally coupled to each other so that if one input voltage fails, all other input voltages must be regulated proportionately to the failed voltage. For example, if the 5 V begins to decrease, all other input voltages must decrease accordingly. This is required in order to preclude cross currents within the CP3002-RC/CP3002-RA.

Failure to comply with above may result in damage to the board or improper system operation.

Note ...

If the main power input is switched off, the supply voltages will not go to 0 V instantly. It will take a couple of seconds until the capacitors are discharged. If the voltage rises again before it has gone below a certain level, the circuits may enter a latch-up state where even a hard RESET will not help any more. The system must be switched off for at least 3 seconds before it may be switched on again. If problems still occur, turn off the main power for 30 seconds before turning it on again.

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5.2 Power Consumption

The goal of this description is to provide a method to calculate the power consumption for the CP3002-RC/CP3002-RA baseboard and for additional configurations. The processor dissipates the majority of the thermal power.

The power consumption tables below list the voltage and the power specifications for the CP3002-RC/CP3002-RA board and its accessories. The values were measured using an 8-slot passive CompactPCI backplane with two power supplies, one for the CPU, and the other for the hard disk.

The operating systems used were uEFI shell and Windows® XP, 32-bit, with Intel® Turbo Boost Technology and Intel® Intelligent Power Sharing enabled. All measurements were conducted at a temperature of 25°C. The measured values varied, because the power consumption was dependent on the processor activity.

The power consumption was measured using the following processor:

• Intel® Core™ i7-620LE (LV) processor with ECC, 2.0 GHz, 4 MB L3 cache

with the following firmware and under the following testing conditions:

• CP3002-RC/CP3002-RA in EFI shell For this measurement the processor cores were active (no power management enabled) and the graphics controller was in idle state (no application running).

• CP3002-RC/CP3002-RA with Windows® XP, 32-bit, processor and graphics controller in idle state For this measurement all processor cores and the graphics controller were in idle state (power management enabled and no application running).

• CP3002-RC/CP3002-RA with Win.® XP , 32-bit, typical processor and graphics controller workload For this measurement all processor cores and the graphics controller were operating at a typical workload. These values represent the power dissipation reached under realistic, OS-controlled applications with the processor operating at typical performance.

• CP3002-RC/CP3002-RA with Win.® XP, 32-bit, maximum processor and graphics controller workload These values represent the maximum power dissipation achieved through the use of specific tools to heat up the processor and graphics controller. These values are unlikely to be reached in real applications.

The following tables indicate the power consumption of the CP3002-RC/CP3002-RA with 4 GB DDR3 SDRAM in dual-channel mode. The measurements were made with the CP3002-RC/ CP3002-RA in EFI Shell mode as well as with the Windows® XP operating system, 32-bit.

Note ...

The power consumption values indicated in the tables below can vary depending on the ambient temperature or the system performance. This can result in deviations of the power consumption values of up to 10%.

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Table 5-3: CP3002-RC/-RA in EFI Shell

POWER

(typ.)

Intel® Core™ i7-620LE (LV) 2.0 GHz

5 V 18.0 W

3.3 V 7.0 W To tal 25 .0 W

Table 5-4: CP3002-RC/-RA with Win. XP and Processor and Graphics in Idle State

POWER

(typ.)

Intel® Core™ i7-620LE (LV) 2.0 GHz

5 V 4.0 W

3.3 V 7.0 W To tal 1 1.0 W

T able 5-5 :

CP3002-RC/-RA

with Win. XP and Typ. Proc. and Graphics Controller Workload

POWER

(typ.)

Intel® Core™ i7-620LE (LV) 2.0 GHz

5 V 21.0 W

3.3 V 10.0 W To tal 31 .0 W

Table 5-6: CP3002-RC/-RA with Win. XP and Max. Processor and Graphics Workload

POWER

(typ.)

Intel® Core™ i7-620LE (LV) 2.0 GHz

5 V 26.0 W

3.3 V 11.0 W To tal 37 .0 W

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5.2.1 Power Consumption of the CP3002-RC/CP3002-RA Accessories

The following table indicates the power consumption of the CP3002-RC/CP3002-RA accessories.

5.2.2 Power Consumption of the Gigabit Ethernet Controller

The following table indicates the power consumption of the Intel® 82580EB GbE controller.

5.3 Start-Up Currents of the CP3002-RC/CP3002-RA

The following table indicates the basic start-up curren ts of the CP3002-RC/CP3002-RA during the first 2-3 seconds after power has been applied (power-on).

For further information on the start-up current, please contact Kontron.

Table 5-7: Power Consumption of CP3002-RC/CP3002-RA Accessories

MODULE POWER 5 V POWER 3.3 V

Keyboard approx. 0.1 W — DDR3 SDRAM update from 4 GB to 8 GB — approx. 1.0 W SATA Flash module — approx. 0.5 W

Table 5-8: Power Consumption of the Gigabit Ethernet Controller

ETHERNET PORT POWER 5 V POWER 3.3 V

Intel® 82580EB, one 1000Base-T Ethernet port plugged — approx. 0.5 W Intel® 82580EB, two 1000Base-T Ethernet ports plugged — approx. 1.0 W Intel® 82580EB, three 1000Base-T Ethernet ports plugged — approx. 1.5 W Intel® 82580EB, four 1000Base-T Ethernet ports plugged — approx. 2.0 W

Table 5-9: Start-Up Currents of the CP3002-RC/CP3002-RA

POWER Intel® Core™ i7-620LE (LV) 2.0 GHz

5 V peak 3.2 A

3.3 V peak 4.0 A

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Chapter 1

P R E L I M I N A R Y

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6. Thermal Considerations

The following chapters provide system integrators with the necessary information to satisfy thermal and airflow requirements when implementing CP3002-RC/CP3002-RA applications. The CP3002-RC is a rugged, conductive-cooled version with a heat spreader. The CP3002-RA is a rugged, air-cooled version with a front panel and a heat sink for forced airflow cooling.

6.1 Board Internal Thermal Monitoring

To ensure optimal operation and long-term reliability of the CP3002-RC/CP3002-RA, all onboard components must remain within the maximum temperature specifications. The most critical component on the CP3002-RC/CP3002-RA is the processor. Operating the CP3002-RC/ CP3002-RA above the maximum operating limits will result in permanent damage to the board.

The board includes three integrated temperature sensors to measure the processor and the chipset temperature:

• Two thermal sensors integrated in the processor

• One thermal sensor integrated in the chipset

6.2 Processor Thermal Monitoring

To allow optimal operation and long-term reliability of the CP3002-RC/CP3002-RA, the Intel® Core™ i7 processor must remain within the maximu m die temperature specific ations. The maximum die temperature for Intel® Core™ i7-610E and i7-620LE multi-chip processors is as follows:

• Processor die: 105°C

• Graphics and memory controller die: 100°C

The Intel® Core™ i7 processor uses the Adaptive Thermal Monitor feature to protect the processor from overheating and includes the following on-die temperature sensors:

• Two Digital Thermal Sensors (DTS) for the processor cores

• One Digital Thermal Sensor (DTS) for the graphics controller and the memory controller

• Catastrophic Cooling Failure Sensor (THERMTRIP#)

These sensors are integrated in the processor and work without any interoperability of the uEFI BIOS or the software application. Enabling the Thermal Control Circuit in the uEFI BIOS allows the processor to maintain a safe operating temperature without the need for special software drivers or interrupt handling routines.

6.2.1 Digital Thermal Sensor (DTS)

The Intel® Core™ i7 processor includes three on-die Digital Thermal Sensors (DTS), two for the processor cores and one for the graphics controller and the memory controller. They can be read via an internal register of the processor. The temperature returned by the Digital Thermal Sensor will always be at or below the maximum operating temperature. Via the Digital Thermal Sensors, the uEFI BIOS or the application software can measure the processor die temperature.

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6.2.2 Adaptive Thermal Monitor

The Adaptive Thermal Monitor feature reduces the processor power consumption and the temperature when the processor silicon exceeds the Thermal Control Circuit (TCC) activation temperature until the processor operates at or below its maximum operating temperature. The temperature at which the Adaptive Thermal Monitor activates the Thermal Con trol Circuit is not user-configurable.

The processor core power reduction is achieved by:

• Frequency/VID Control (by reducing of processor core voltage)

• Clock Modulation (by turning the internal processor core clocks off and on)

Adaptive Thermal Monitor dynamically selects the appropriate method. uEFI BIOS is not required to select a specific method as with previous-generation processors supporting Intel® Thermal Monitor 1 (TM1) and Intel® Thermal Monitor 2 (TM2).

The Adaptive Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.

6.2.3 Frequency/VID Control

Frequency/VID Control reduces the processor’s operating frequency (using the core ratio multiplier) and the input voltage (using VID signals). This combination of lower frequency and VID results in a reduction of the processor power consumption. This method is similar to Intel® Thermal Monitor 2 (TM2) in previous generation processors.

Running the processor at the lower frequency and voltage will reduce power consumption and should allow the processor to cool off. If the processor temperature does not drop below the TCC activation point, a second frequency and voltage transition will take place . This sequence of temperature checking and Frequency/VID reduction will continue until either the minimum frequency has been reached of the processor temperature has dropped belo w the TCC activation point. If the processor temperature remains above the TCC activation point even after the minimum frequency has been reached, then Clock Modulation at that minimum frequency will be initiated.

6.2.4 Clock Modulation

Clock Modulation reduces power consumption by rapidly turning the internal processor core clocks off and on at a duty cycle that should reduce power dissipation (typically a 30-50 % duty cycle). This method is similar to Intel® Thermal Monitor 1 (TM1) in previous generation processors.

Once the temperature has dropped below the maximum operating temperature, the TCC goes inactive and clock modulation ceases.

Note ...

When the Debug LED on the front panel is lit after boot-up, it indicates that the processor die temperature is above 105°C or the graphics and memory controller die temperature is above 100°C.

Note ...

When the Debug LED on the front panel is lit after boot-up, it indicates that the processor die temperature is above 105°C or the graphics and memory controller die temperature is above 100°C.

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6.2.5 Catastrophic Cooling Failure Sensor

The Catastrophic Cooling Failure Sensor protects the processor from cat astrophic overheating. The Catastrophic Cooling Failure Sensor threshold is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all executions when the junction temperature exceeds approximately 125°C. Once activated, the event remains latched until the CP3002-RC/CP3002-RA undergoes a power-on restart (all p ower off and then on again).

This function cannot be enabled or disabled in the uEFI BIOS. It is always enabled to ensure that the processor is protected in any event.

6.3 Chipset Thermal Monitor Feature

The Intel® QM57 chipset includes one on-die thermal sensor to measure the chipset die temperature.

The maximum Intel® QM57 chipset case temperature is 111 °C

6.4 Thermal Characteristics for the CP3002-RC

The thermal concept of the CP3002-RC is based on a specially designed full-board heat spreader and wedge lock clamping mechanisms.

The heat spreader provides optimal heat transfer to the board’s top and bottom edges as well as enhanced structural support for ruggedized environments.

The wedge locks serve two functions. First, they provide a highly stable mechanical fixation of the board in the chassis slot. When expanded using the proper torque value, they form with the heat spreader practically a single physical unit capable of withstanding very high sh ock and vibration forces. Second, they are the primary mechanism for conduction of heat from the board to the system chassis.

Cooling of the CP3002-RC is a function of the system chassis which must provide adequate conduction cooling capability. To determine cooling performance, the board temperature can be measured at the reference point indicated in the figure below.

Note ...

When all Debug LED on the front panel are blinking, it indicates that the processor temperature is above 125°C.

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Figure 6-1: Position of the Reference Points on the CP3002-RC

The following table provides the maximum reference point temperatures for the CPU ind icated at typical processor and graphics controller workload and at maximum processor and graphics controller workload. Operation at temperatures above those specified for the table below can result in reduced system performance.

Table 6-1: Maximum Reference Point Temperature at 105°C CPU Die Temperature

MAXIMUM REFERENCE POINT TEMPERATURE

AT 105°C CPU DIE TEMPERATURE

CPU VERSION

MAXIMUM PROCESSOR AND GRAPHICS

CONTROLLER WORKLOAD

TYPICAL PROCESSOR AND GRAPHICS

CONTROLLER WORKLOAD

Point 1 Point 2 Point 1 Point 2

Intel® Core™ i7-620LE

2.0 GHz

80°C 80°C 85 °C 85°C

Note ...

The temperature values indicated in the tables above can vary depending on the location of the measurement point or the system performance.

Warning!

As Kontron assumes no responsibility for any damage to the CP3002-RC or other equipment resulting from overheating of the CPU, it is highly recommended that system integrators as well as end users confirm that the operational environment of the CP3002-RC complies with the thermal considerations set forth in this document.

Reference Point 2

Reference Point 1

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6.5 External Thermal Regulation of the CP3002-RA

To ensure the best possible basis for operational stability and long-term reliability, the CP3002RA is equipped with a heat sink. Coupled together with system chassis, which provides variable configurations for forced airflow, controlled active thermal energy dissipation is guaranteed. The physical size, shape, and construction of the heat sink and ensures the lowest possible thermal resistance. In addition, the CP3002-RA has been specifically designed to efficiently support forced airflow as found in modern CompactPCI systems.

Thermal Characteristic Graphs

The thermal characteristic graphs shown on the following sections illustrate the maximum ambient air temperature as a function of the volumetric airflow rate f or th e p ower consump tion indicated. The diagrams are intended to serve as guidance for reconciling board and system with the required computing power considering the thermal aspect. One diagram per CPU version and ruggedization level is provided. There are up to two curves representing upper level working points based on different levels of a verag e CPU utilization . Whe n ope ratin g below the corresponding curve, the CPU runs steadily without any intervention of thermal supervision. When operated above the corresponding curve, various thermal protection mechanisms may take effect resulting in temporarily reduced CPU performance or finally in an emergency stop in order to protect the CPU and the chipset from thermal destruction. In real applications this means that the board can be operated temporarily at a higher ambient temperature or at a reduced flow rate and still provide some margin for temporarily requested peak performance before thermal protection will be activated.

An airflow of 2.0 m/s is a typical value for a standard Kontron ASM rack. For other racks or housings the available airflow will differ . The maximum ambient operating temperature must be recalculated and/or measured for such environments. For the calculation of the maximum ambient operating temperature, the processor and chipset junction temperature must never exceed the specified limit for the involved processor and chipset.

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Thermal characteristic curves

• Thermal characteristic curve of the CP3002-RA with typical processor and graphics controller workload This load complies with the typical processor and graphics controller workload indicated in Chapter 5.2, “Power Consumption”, Table 5-5.

• Thermal characteristic curve of the CP3002-RA with maximum processor and graphics controller workload This load complies with the maximum processor and graphics controller workload indicated in Chapter 5.2, “Power Consumption”, Table 5-6.

How to read the diagram

Choose a specific working point. For a given flow rate there is a maximum airflow input temperature (= ambient temperature) provided. Below this operating point, thermal supervision will not be activated. Above this operating point, thermal supervision will become active protecting the CPU from thermal destruction. The minimum airflow rate provided must be more than the value specified in the diagram.

Volumetric flow rate

The volumetric flow rate refers to an airflow through a fixed cross-sectional area (i.e. slo t width x depth. The volumetric flow rate is specified in m³/h (cubic-meter-per-hour) or cfm (cubic-feetper-minute) respectively.

Conversion: 1 cfm = 1.7 m³/h; 1 m³/h = 0.59 cfm

Airflow

At a given cross-sectional area and a required flow rate, an average, homogeneous airflow speed can be calculated using the following formula:

Airflow = Volumetric flow rate / area. The airflow is specified in m/s (meter-per-second) or in fps (feet-per-second) respectively. Conversion: 1 fps = 0.3048 m/s; 1 m/s = 3.28 fps The following figures illustrate the operational limits of the CP3002-RA taking into consideration

power consumption vs. ambient air temperature vs. airflow rate. The measurements were made based on a 4HP slot and with both processor cores enabled.

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6.5.1 Operational Limits for the CP3002-RA

Figure 6-2: CP3002-RA with i7-620LE, 2.0 GHz

6.5.2 Peripherals

When determining the thermal requirements for a given app lication, peripherals to be used with the CP3002-RC/CP3002-RA must also be considered. Devices such as SATA Flash modules which are directly attached to the CP3002-RC/CP3002-RA must also be capable of being operated at the temperatures foreseen for the application. It may very well be necessary to revise system requirements to comply with operational environment conditions. In most cases, this will lead to a reduction in the maximum allowable ambient operating temperature or even require active cooling of the operating environment.

Warning!

As Kontron assumes no responsibility for any damage to the CP3002-RC/ CP3002-RA or other equipment resulting from overheating of the CPU, it is highly recommended that system integrators as well as end users confirm that the operational environment of the CP3002-RC/CP3002-RA complies with the thermal considerations set forth in this document.

Volumetric Flow Rate (CFM)

Volumetric Flow Rate (m /h)

Airflow (m/s)

Typical Processor and Graphics Controller Workload

recommended operating range

Maximum Processor and Graphics Controller Workload

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A. SATA Flash Module

The CP3002-RC/CP3002-RA provides an optional SA T A Flash module with up to 32 GB NAND Flash memory. The SATA Flash module is connected to the CP3002-RC/CP3002-RA via the board-to-board connectors J3 located on the CP3002-RC/CP3002-RA and J1 located on the SA TA Flash module. The SATA Flash module has been optimized for embedded systems providing high performance, reliability and security.

A.1 Technical Specifications

Note ...

Write protection is available for this module. Please contact Kontron for further assistance if write protection is required.

Table A-1: SATA Flash Module Specifications

SATA FLASH MODULE SPECIFICATIONS

Interface

Board-to-Board Connector One 34-pin, male, board-to-board connector, J1

Memory

Memory Up to 32 GB SLC-based NAND Flash memory

• Built-in full hard disk emulation

• Up to 100 MB/s read rate

• Up to 90 MB/s write rate

General

Power Consumption typ. 0.5 W

3.3 V supply

Temperature Range Operational: 0°C to +60°C Standard

-40°C to +85°C Extended

Storage: -40°C to +85°C Climatic Humidity 93% RH at 40°C, non-condensing (acc. to IEC 60068-2-78) Dimensions 70 mm x 28 mm Board Weight ca. 14 grams

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A.2 SATA Flash Module Layout

The SATA Flash module includes one board-to-board connector, J1, for connection to the CP3002-RC/CP3002-RA.

Figure A-1: SATA Flash Module Layout (Bottom View)

NAND

Flash

NAND

Flash

33 1

234