5
IEEE-488 Programming
Figure 5. I
Figure S-2
Figure S-3
Figure 5-4
Figure 5-5
t’igurc 5-6
Figure 5-7
Figure s-x
Figurc 5-9
Figure 5. IO
Figurc 5-11
Figurc 5-12
Figurc 5. I3
Figure S- I4
Figure 5. IS
Figurc S- I6
Figurc 5-17
Figure 5-18
Figure 5-19
Figure S-20
Figure S-21
Figure 5-22
Figure 5-23
Flowchart ol’cxamplc program
....................................................................................................................
5-2
IEEE-488 connector..
...................................................................................................................................
5-3
IEEE-48X connections
.................................................................................................................................
S-3
IEEE-488 connector location
5-4
........................................................................................................................
Contacl assignments ....................................................................................................................................
5-4
IEEE-488 bus connector and rotary sclcction
switchcs..
............................................................................. S-6
IEEE-488 indicllrors .....................................................................................................................................
5-8
Digital I/O status display mode
5-9
....................................................................................................................
External trigger pulse..
...............................................................................................................................
5 I5
Matrix reedy pulse
.....................................................................................................................................
S- I6
GO and Cl full output formats..
.................................................................................................................
S-21
G2 and G3 inspect output Cormats
.............................................................................................................
S-22
G4 and G5 condensed output formats
....................................................................................................... 5-22
G6
and G7 binary output formats
..............................................................................................................
S-23
SRQ mask and serial poll byte format..
.....................................................................................................
S-26
KEADY and MATRIX READY signal timing
......................................................................................... 5-3 I
UO machine status word
.............................................................................................................................
5-33
Ul error status word ..................................................................................................................................
5-33
U3 relay step pointer ..................................................................................................................................
5-34
U4 number ot” slaves ..................................................................................................................................
5-35
U5 card idcn(lfxatmn ...................................................................................................................................
5-35
U6 relay setthng tmx.. ................................................................................................................................
5-3s
U7 digital input ..........................................................................................................................................
5-36
6
Figure 6. I
Figurc 6-2
Figure 6-3
Figure 6-4
Figure 6-S
Figure 6-6
Figure 6-7
Figure 6-X
Figure 6-9
IFigure 6-10
Figure 6. I I
Figure 6. I2
7
Maintenance
Figure 7. I
Rack mstalla~~on
............................................................................................................................................ 7-2
Figure 7-2
Screw and dress panel removal
....................................................................................................................
7-4
Figure 7-3
Fuse FAA250 location..
..................................................................................................................................
7-5
Figure 7-4
Shield removal .............................................................................................................................................
7-6
Figure 7-5
W 101 jumper location .................................................................................................................................
7-7
Figure 7-6
Model 708 exploded view
...........................................................................................................................
l-9
Figure 7-7
Troubleshooting programs. ........................................................................................................................
7 -IO
Figure 7-8
Relay control wavcCorms
........................................................................................................................... 7-14
Figure 7-9
Display interface waveforms .....................................................................................................................
7 I4
Principles of Operation
Model 708 block diagram ............................................................................................................................
6 -I
Digital board block diagram.. ......................................................................................................................
6-2
RAM and battery backup .............................................................................................................................
6-4
Matrix card interface simplified schematic
.................................................................................................
6-S
Matrix card interlaw timing diagram..
........................................................................................................ 6-6
Typical matrix card logic block diagram
.....................................................................................................
6-7
IDDATA timing diagram ............................................................................................................................
6-7
Display board block diagram .......................................................................................................................
6-9
Display interface simplified schematic
........................................................................................................
6-9
..
Light pen interface simph~xd schematic
...................................................................................................
6.12
..
Master/slave interface simphfied schematic
..............................................................................................
6- I3
Digital l/O interlace simplified schematic
.................................................................................................
6 I5