JVC TU-HD500A Schematics

Page 1

TU-HD500A

STANDARD CIRCUIT DIAGRAM

CONTENTS

BLOCK DIAGRAM
USING P.W. BOARD
P.W.B ASS'Y name P.W.B ASS'Y nubmer MAIN PWB
FRONT PWB POWER PWB
GTR300MBAJ10 GTR300FBAJ10
GTR300PBA010
2-3
No.YA227
2-1
Page 2
2-2
No.YA227
Page 3

BLOCK DIAGRAM

A
A
FRONT CONTROL PWB
UF2
FRONT DISPAY
UF3
REMOTE CONTROL
RECEIVER
FRONT KEY
MODE SELECT
SWITCH
RS-232C
UF1
FRONT CPU
U5
FREME MEMORY
SDRAM
(2*32Mbit)
HD MPEG DECODER
FREME MEMORY
U7
Video Stream + OSD
U6
SDRAM
(2*32Mbit)
Digital Video
Control
Tri Level Sync Control
U30
INTERFACE
LOGIC
LATTICE CPLD
HD H Sync
Sync Delete Control
HD Digital
YPbPr
U24
HD
VIDEO DAC
HD Analog YPbPr
U26
HIGH SPEED
SWITCH+BUFFER
SYNC DELETE
ANALOG COLOUR
SPACE
CONVERTER
HD H SYNC
HD Y
HD Pb
HD Pr
HD R
HD G
HD B
BUFFER
EMI/ EMC
EMI/ EMC
EMI/ EMC
EMI/ EMC
EMI/ EMC
EMI/ EMC
EMI/ EMC
R
G
B
H
SYNC
Y
Pb
HD
Pr
HD
VG
ANT IN
LOOP
OUT
UDIO 1
AUDIO 2
DIGITAL
AUDIO
AUDIO
L/R
AUDIO
L/R
SPDIF COAX
SPDIF
OPTICAL
DEMODULATOR CHIPSET
TU1
COFDM TUNER
with
EMI/ EMC
EMI/ EMC
EMI/ EMC
BUFFER
BUFFER
Serial TS
Tuner Control
BUFFER
U22
AUDIO DAC
S/P DIF
CPU with SD MPEG DECODER
/ DOLBY DIGITAL AUDIO
Digital Audio
U1
Logic Control
U8
SYSTEM MEMORY
(FLASH 16Mbit)
U9
SYSTEM MEMORY
(SD RAM 4*16 Mbit)
U4
SYSTEM MEMORY
(EEPROM 64Kbit)
HD V Sync
SD Video
SD Video DAC Control
U33
SD VIDEO
DAC
HD V SYNC
SD G/Y
SD B/Pb
SD R/Pr
SD S-VIDEO Y
SD S-VIDEO C
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
EMI/ EMC
EMI/ EMC
EMI/ EMC
EMI/ EMC
EMI/ EMC
EMI/ EMC
SYNC
V
S
Y/G
Pb/B
Pr/R
SD
Y/C
POWER SUPPLY
AC100~250V
30 W
50/60Hz
MAIN PWB
SD CVBS
BUFFER
EMI/ EMC
TV V
No.YA227 No.YA2272-3 2-4
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