intersil X9C303 User Manual

®

www.BDTIC.com/Intersil

X9C303

Logarithmic Digitally Controlled Potentiometer (XDCP™)

Data Sheet January 24, 2007

Terminal Voltage ±5V, 100 T aps, Log Taper
Description

The Intersil X9C303 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a three-wire interface.

The resistor array is composed of 99 resistive elements.
Between each element and at either end are tap points
accessible to the wiper terminal. The position of the wiper
element is controlled by the CS
position of the wiper can be stored in nonvolatile memory
and then be recalled upon a subsequent power-up
operation.

The device can be used as a three-terminal potentio-meter
or as a two-terminal variable resistor in a wide variety of
applications ranging from control, to signal processing, to
parameter adjustment. Digitally
provide three powerful application advantages; (1) the
variability and reliability of a solid-state potentiometer, (2) the
flexibility of computer-based digital controls, and (3) the use
of nonvolatile memory for potentiometer settings retention.

, U/D, and INC inputs. The

-

controlled potentiometers

Features

• Solid-state potentiometer

• Three-wire serial interface

• 100 wiper tap points

- Wiper position stored in nonvolatile memory and
recalled on power-up

• 99 resistive elements, log taper

- Temperature compensated

- End to end resistance, 32kΩ ±15%

- Terminal voltages, ±5V

• Low power CMOS
= 5V

-V

CC

- Active current, 3mA max.

- Standby current, 750µA max.

• High reliability

- Endurance, 100,000 data changes per bit

- Register data retention, 100 years

• Packages

- 8 Ld TSSOP

- 8 Ld SOIC

- 8 Ld PDIP

FN8223.1

Block Diagram

U/D
INC

CS

V

CC

V

SS

7-Bit

Up/Down

Counter

7-Bit

Nonvolatile

Memory

Store and

Recall

Control

Circuitry

One

of

One­Hundred
Decoder

99

98

97

96

RH/V

H

Transfer

Gates

2

1

0

Resistor

Array

RL/V

RW/V

L

W

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9C303

www.BDTIC.com/Intersil

Ordering Information

PART NUMBER PART MARKING TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. #

X9C303P X9C303P 0 to +70 8 Ld PDIP MDP0031
X9C303PI X9C303P I -40 to +85 8 Ld PDIP MDP0031
X9C303PIZ (Note) X9C303P ZI -40 to +85 8 Ld PDIP (300 mil) (Pb-free) MDP0031
X9C303PZ (Note) X9C303P Z 0 to +70 8 Ld PDIP (300 mil) (Pb-free) MDP0031
X9C303S8* X9C303S 0 to +70 8 Ld SOIC (150 mil) MDP0027
X9C303S8I* X9C303S I -40 to +85 8 Ld SOIC (150 mil) MDP0027
X9C303S8IZ* (Note) X9C303S ZI -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027
X9C303S8Z* (Note) X9C303S Z 0 to +70 8 Ld SOIC (150 mil) (Pb-free) MDP0027
X9C303V8* 9C303 0 to +70 8 Ld TSSOP (4.4mm) M8.173
X9C303V8I* C303 I -40 to +85 8 Ld TSSOP (4.4mm) M8.173
X9C303V8IZ* (Note) C303 IZ -40 to +85 8 Ld TSSOP (4.4mm) (Pb-free) M8.173
X9C303V8Z* (Note) 9CC303 Z 0 to +70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173
X9C303S8I-2.7 X9C303S G -40 to +85 8 Ld SOIC (150 mil) MDP0027
X9C303S8IZ-2.7 (Note) X9C303S ZG -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "T1" suffix for tape and reel.

Pin Descriptions

VH and V

The high (VH) and low (VL) terminals of the device are
equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is –5V and the
maximum is +5V. It should be noted that the terminology of
V

and VH references the relative position of the terminal in

L

relation to wiper movement direction selected by the U/D
input and not the voltage potential on the terminal.

V

W

VW is the wiper terminal, equivalent to the movable terminal
of a mechanical potentiometer. The position of the wiper
within the array is determined by the control inputs. The
wiper terminal series resistance is typically 40Ω.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement
and whether the counter is incriminated or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D

Chip Select (CS)

The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS
the store operation is complete the device will be placed in
the low power standby mode until the device is selected
once again.

L

input.

is returned HIGH while the INC input is also HIGH. After

Pinout

X9C303

(8 LD SOIC, 8 LD TSSOP, 8 LD PDIP)

INC

(CS)

(V

)

U/D

CC

)

(INC

V

H

(U/D

)

V

SS

TOP VIEW

1

2

X9C303

3

4

Pin Names

SYMBOL DESCRIPTION

V

H

V

W

V

L

V

SS

V

CC

U/D
INC

CS
NC No Connection

High Terminal (Potentiometer)
Wiper Terminal (Potentiometer)
Low Terminal (Potentiometer)
Ground
Supply Voltage
Up/Down Control Input
Increment Control Input
Chip Select Control Input

8

7

6

5

CS

V

V

CC

L

W

L

(V

)

W

)

(V

SS

(V

)

H

(V

)

V

2

FN8223.1

January 24, 2007

X9C303

www.BDTIC.com/Intersil

Potentiometer Relationships

S100

V

H

(VS)

R99

R98

R2

R1

V

L

Gi20Log

R1R2. . . R

(Refer Test Circuit 1)

R1R2. . . R

-------------------------------------------------

+++ R

S99

S98

S3

S2

S1

+++

R

TOTAL

=

99

TOTAL

V

W

V

i

W

--------- VL0V=()==
V

S

Principles of Operation

There are three sections of the X9C303: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the
resistor array to the wiper output. Under the proper
conditions the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 99 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.

The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for t
R

value for the device can temporarily be reduced by a

TOTAL

significant amount if the wiper is moved several positions.

(INC to VW change). The

IW

Instructions and Programming

The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS
selected and enabled to respond to the U/D
HIGH to LOW transitions on INC
(depending on the state of the U/D

set LOW the device is

and INC inputs.

will increment or decrement

input) a seven-bit counter.
The output of this counter is decoded to select one of one­hundred wiper positions along the resistive array.

The value of the counter is stored in nonvolatile memory
whenever CS

transitions HIGH while the INC input is also

HIGH.
The system may select the X9C303, move the wiper, and

deselect the device without having to store the latest wiper
position in nonvolatile memory. The wiper movement is
performed as described above; once the new position is
reached, the system would the keep INC
CS

HIGH. The new wiper position would be maintained until

LOW while taking

changed by the system or until a power-down/up cycle
recalled the previously stored data.

This would allow the system to always power-up to a preset
value stored in nonvolatile memory; then during system
operation minor adjustments could be made. The
adjustments might be based on user preference: system
parameter changes due to temperature drift, etc...

The state of U/D

may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.

Mode Selection

CS INC U/D MODE

L H Wiper Up
L L Wiper Down

H X Store Wiper Position

H X X Standby Current

L X No Store, Return to Standby
L H Wiper Up (not recommended)
L L Wiper Down (not recommended)

When the device is powered-down, the last counter position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the counter is reset to the value last stored.

3

FN8223.1

January 24, 2007

Symbol Table

www.BDTIC.com/Intersil

WAVEFORM INPUTS OUTPUTS

X9C303

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Typical Electrical Taper

100.0%

90.0%

80.0%

70.0%

60.0%

50.0%

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

40.0%

30.0%

% TOTAL RESISTANCE

20.0%

10.0%

0.0%

R(VH - VW)
R(V

W

0

- VL)

Test Circuit #1

V

S

3

6

9

1215182124273033363942

Test Circuit #2

V

H

Test Point

V

W

V

L

V

V

4851545760636669727578818487909396

45

TAP

Circuit #3 SPICE Macro Model

H

R

Test Point

V

W

Force

L

Current

H

C

10pF

R

H

TOTAL

R

99

R

L

C

C

W

25pF

W

L

10pF

4

FN8223.1

January 24, 2007

X9C303

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS
Voltage on V
ΔV = |V

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

, INC, U/D and VCC with Respect to VSS . -1V to +7V

and VL Referenced to VSS . . . . . . . . . . . . -8V to +8V

H

- VL| X9C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V

H

Analog Specifications Over recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

R

TOTAL

V

V

R

C

H/CL/CW

(Note 3)

H

L

W

End-to-End Resistance 32 κΩ
End-to-End Resistance Tolerance -15 +15 %

Terminal Voltage -5 +5 V

V

H

Terminal Voltage -5 +5 V

V

L

Wiper Resistance Max Wiper Current ±1mA 40 100 Ω
Tap position relative step size error Error = log (Vw(n)) - log (Vw(n - 1))

for tap n = 2 - 99, V

Resistor Noise At 1kHz 23 nV(RMS)/

Charge Pump Noise At 2.5MHz 20 mV(RMS)
End-to-End Resistance

Temperature Coefficient
Ratiometric Temperature Coefficient Tap position 84 ±20 ppm/°C
Potentiometer Capacitance See Circuit 3 10/10/25 pF

T = -40°C to +85°C ±400 ppm/°C

Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C

Military Temperature Range. . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

Power Rating at +25°C X9C303 . . . . . . . . . . . . . . . . . . . . . . .10mW

Physical Characteristics

Marking Includes
Manufacturer’s Trademark
Resistance Value or Code
Date Code

LIMITS

TYP

H-VL

= 10V

(NOTE 1)

0.005 0.115 dB

MAX

UNITMIN

√Hz

DC Electrical Specifications Over recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC

I

SB

I

LI

V

IH

V

IL

C

(Note 3) CS

IN

Vcc Active Current CS

Standby Supply Current CS

, INC, U/D Input Leakage Current VIN = VSS to V

CS

, INC, U/D Input HIGH Voltage 2 V

CS

, INC, U/D Input LOW voltage 0.8 V

CS

, INC, U/D Input Capacitance VCC = 5V, VIN = VSS,

= VIL, U/D = VIL or VIH and

= 0.4V to 2.4V @ Max t

INC

= VCC - 0.3V , U/D and INC =VSS or

VCC - 0.3V

CC

TA = +25°C, f = 1MHz

CYC

5

LIMITS

TYP

(NOTE 1)

13mA

200 750 µA

-10 +10 µA

10 pF

MAX

UNITMIN

FN8223.1

January 24, 2007

X9C303

www.BDTIC.com/Intersil

DC Electrical Specifications Over recommended operating conditions unless otherwise specified. (Continued)

LIMITS

TYP

SYMBOL PARAMETER TEST CONDITIONS

EEPROM SPECS

EEPROM Endurance Wiper storage operations over

recommended operation conditions

EEPROM Retention At +55°C 100 Years

100,000 Cycles

Standard Parts

PART NUMBER MAXIMUM RESISTANCE WIPER INCREMENTS MINIMUM RESISTANCE

X9C303 32kΩ Log Taper 40Ω Typical

NOTES:

1. Typical values are for T

= +25°C and nominal supply voltage.

A

A.C. Conditions of Test

Input pulse levels 0V to 3V
Input rise and fall times 10ns
Input reference levels 1.5V

(NOTE 1)

MAX

UNITMIN

AC Electrical Specifications Over recommended operating conditions unless otherwise specified.

LIMITS

SYMBOL PARAMETER

t

Cl

t

lD

t

DI

t

lL

t

lH

t

lC

t

CPH

t

(Note 3) INC

IW

t

CYC

t

(Note 3) INC

R, tF

t

(Note 3) Power-up to Wiper Stable 500 µs

PU

tR V

CC

(Note 3) V

to INC Set-up 100 ns

CS

HIGH to U/D Change 100 ns

INC
U/D to INC Set-up 2.9 µs

LOW Period 1 µs

INC

HIGH Period 1 µs

INC
INC Inactive to CS Inactive 1 µs

Deselect Time 20 ms

CS

to VW Change 100 µs
Cycle Time 2 µs

INC

Input Rise and Fall Time 500 ns

Power-up Rate 0.2 50 mV/µs

CC

UNITMIN TYP (Note 2) MAX

6

FN8223.1

January 24, 2007

A.C. Timing

www.BDTIC.com/Intersil

CS

INC

X9C303

t

CYC

t

CI

t

IL

t

IH

t

IC

t

CPH

90% 90%

10%

U/D

V

t

ID

t

IW

W

t

DI

(Note 4)

MI

NOTES:

2. Typical values are for T

= +25°C and nominal supply voltage.

A

3. This parameter is not 100% tested.

4. MI in the A.C. timing diagram refers to the minimum incremental change in the V

t

F

output due to a change in the wiper position.

W

t

R

7

FN8223.1

January 24, 2007

X9C303

www.BDTIC.com/Intersil

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE
PLANE

0.25

0.010

A2

L

c

M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N8 87

o

α

0

o

8

o

0

o

8

Rev. 1 12/00

NOTESMIN MAX MIN MAX

-

8

FN8223.1

January 24, 2007

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

X9C303

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL SO-8 SO-14

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 ­A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 ­D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic ­L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28) TOLERANCE NOTES

A

0.010

Rev. L 2/01

9

FN8223.1

January 24, 2007

Plastic Dual-In-Line Packages (PDIP)

www.BDTIC.com/Intersil

X9C303

SEATING
PLANE

D

A2

A

L

L

e

b

A1

NOTE 5

c

E

eA

eB

N

PIN #1

E1

INDEX

12 N/2

b2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

Rev. B 2/99

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10

FN8223.1

January 24, 2007