intersil X98021 DATA SHEET
®
X98021
Data Sheet June 2, 2005
210MHz Triple Video Digitizer with
Digital PLL
The X98021 3-channel, 8-bit Analog Front End (AFE)
contains all the components necessary to digitize analog
RGB or YUV graphics signals from personal computers,
workstations and video set-top boxes. The fully differential
analog design provides high PSRR and dynamic
performance to meet the stringent requirements of the
graphics display industry. The AFE’s 210MSPS conversion
rate supports resolutions up to UXGA at 75Hz refresh rate,
while the front end's high input bandwidth ensures sharp
images at the highest resolutions.
To minimize noise, the X98021's analog section features 2
sets of pseudo-differential RGB inputs with programmable
input bandwidth, as well as internal DC restore clamping
(including mid-scale clamping for YUV signals). This is
followed by the programmable gain/offset stage and the
three 210MSPS Analog-to-Digital Converters (ADCs).
Automatic Black Level Compensation (ABLC™) eliminates
part-to-part offset variation, ensuring perfect black level
performance in every application.
The X98021's digital PLL generates a pixel clock from the
analog source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 210MHz
with sampling clock jitter of 250ps peak to peak.
FN8219.0
Features
• 210MSPS maximum conversion rate
• Low PLL clock jitter (250ps p-p @ 210MSPS)
• 64 interpixel sampling positions
• 0.35V
p-p
to 1.4V
video input range
p-p
• Programmable bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
• RGB and YUV 4:2:2 output formats
• 5 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
• Trilevel sync detection
• 1.1W typical P
@ 210MSPS
D
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD Monitors and Projectors
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
Simplified Block Diagram
RGB/YPbPr
RGB/YPbPr
HSYNC
VSYNC
SOG
1
IN
2
IN
1/2
IN
1/2
IN
1/2
IN
3
3
Voltage
Clamp
PGA
Sync
Processing
AFE Configuration and Control
• Scan Converters
Offset
DAC
+
Digital PLL
8 bit ADC
ABLC™
8 or 16
x3
RGB/YUV
HSYNC
OUT
VSYNC
OUT
HS
OUT
PIXELCLK
OUT
OUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
Ordering Information
X98021
PART NUMBER
MAXIMUM PIXEL
RATE
TEMP RANGE
(°C) PACKAGE PART MARKING
X98021L128-3.3 210MHz 0 to 70 128 MQFP X98021L-3.3
X98021L128-3.3-Z
210MHz 0 to 70 128 MQFP (Pb-free) X98021L-3.3Z
(See Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
V
RIN1
RIN2
GIN1
RGB
GND
GIN2
RGB
GND
BIN1
BIN2
SOGIN1
SOG
IN
HSYNCIN1
HSYNC
IN
VSYNCIN1
VSYNC
IN
CLOCKINV
XTAL
XTAL
OUT
SCL
SDA
SADDR
CLAMP
VIN+
-
V
IN
V
1
2
2
VIN+
V
IN
VIN+
V
IN
-
V
-
PGA
CLAMP
PGA
CLAMP
PGA
Sync
2
2
IN
Processing
Digital PLL
Serial
Interface
Offset
+
Offset
+
Offset
+
10
DAC
8 bit ADC
10
DAC
8 bit ADC
10
DAC
8 bit ADC
ABLC™
ABLC™
ABLC™
AFE Configuration
and Control
8
[7:0]
R
8
8
8
P
8
[7:0]
R
S
8
[7:0]
G
P
8
[7:0]
G
S
8
[7:0]
B
P
8
[7:0]
B
S
Output Data Formatter
DATACLK
DATACLK
HS
OUT
VS
OUT
HSYNC
OUT
VSYNC
OUT
XTALCLK
OUT
2
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June 2, 2005
X98021
Absolute Maximum Ratings Recommended Operating Conditions
Voltage on VA, VD, or V
(referenced to GNDA=GNDD=GNDX) . . . . . . . . . . . . . . . . . . . 4.0V
Voltage on any analog input
(referenced to GND
Voltage on any digital input
(referenced to GND
X
pin
) . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VA
A
pin
) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
D
Current into any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20mA
Operating Temperature range . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
T
Electrical Specifications Specifications apply for V
= VD = VX = 3.3V, pixel rate = 210MHz, f
A
unless otherwise noted
SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT
FULL CHANNEL CHARACTERISTICS
ADC Resolution 8Bits
Missing Codes Guaranteed monotonic None
Conversion Rate Per Channel 10 210 MHz
DNL Differential Non-Linearity ±0.6 +1.0
INL Integral Non-Linearity ±1.25 ±3.25 LSB
Gain Adjustment Range ±6 dB
Gain Adjustment Resolution 8Bits
Gain Matching Between Channels Percent of full scale ±1 %
Full Channel Offset Error, ABLC™ enabled ADC LSBs, over time and temperature ±0.125 ±0.5 LSB
Offset Adjustment Range, ABLC™
enabled or disabled
ADC LSBs (see ABLC™ applications
information section)
Overvoltage Recovery Time For 150% overrange, maximum bandwidth
setting
ANALOG VIDEO INPUT CHARACTERISTICS (R
1, GIN1, BIN1, RIN2, GIN2, BIN2)
IN
Input Range 0.35 0.7 1.4 V
Input Bias Current DC restore clamp off ±0.01 ±1 µA
Input Capacitance 5pF
Full Power Bandwidth Programmable 780 MHz
INPUT CHARACTERISTICS (SOG
V
IH/VIL
Input Threshold Voltage Programmable - See Register Listing for
1, SOGIN2)
IN
Details
Hysteresis Centered around threshold voltage 40 mV
Input capacitance 5pF
INPUT CHARACTERISTICS (HSYNC
V
IH/VIL
Input Threshold Voltage Programmable - See Register Listing for
1, HSYNCIN2)
IN
Details
Hysteresis Centered around threshold voltage 240 mV
R
Input impedance 1.2 kΩ
IN
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . V
= 25MHz, TA = 25°C,
XTAL
= VD = VX = 3.3V
A
LSB
-0.9
±127 LSB
5ns
P-P
0 to
V
-0.3
0.4 to 3.2 V
3
FN8219.0
June 2, 2005
X98021
Electrical Specifications Specifications apply for V
= VD = VX = 3.3V, pixel rate = 210MHz, f
A
= 25MHz, TA = 25°C,
XTAL
unless otherwise noted (Continued)
SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT
Input capacitance 5pF
DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINV
V
V
Input HIGH Voltage 2.0 V
IH
Input LOW Voltage 0.8 V
IL
I Input leakage current RESET
, RESET)
IN
has a 70kΩ pullup to V
D
±10 nA
Input capacitance 5pF
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC
V
+ Low to High Threshold Voltage 1.45 V
T
1, VSYNCIN2)
IN
VT- High to Low Threshold Voltage 0.95 V
I Input leakage current ±10 nA
Input capacitance 5pF
DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK
V
V
DIGITAL OUTPUT CHARACTERISTICS (R
V
V
R
Output HIGH Voltage, IO = 16mA 2.4 V
OH
Output LOW Voltage, IO = -16mA 0.4 V
OL
, GP, BP, RS, GS, BS, HS
P
Output HIGH Voltage, IO = 8mA 2.4 V
OH
Output LOW Voltage, IO = -8mA 0.4 V
OL
Pulldown to GNDD when three-state RP, GP, BP, RS, GS, BS only 58 kΩ
TRI
DIGITAL OUTPUT CHARACTERISTICS (SDA, XTALCLK
V
V
Output HIGH Voltage, IO = 4mA XTALCLK
OH
Output LOW Voltage, IO = -4mA 0.4 V
OL
OUT
)
, VS
OUT
OUT
, HSYNC
OUT
, VSYNC
OUT
)
)
only; SDA is open-drain 2.4 V
OUT
POWER SUPPLY REQUIREMENTS
V
V
V
P
Analog Supply Voltage 3 3.3 3.6 V
A
Digital Supply Voltage 3 3.3 3.6 V
D
Crystal Oscillator Supply Voltage 3 3.3 3.6 V
X
I
Analog Supply Current Operating 185 200 mA
A
I
Digital Supply Current Operating (grayscale) 145 160 mA
D
I
Crystal Oscillator Supply Current 0.7 2 mA
X
Total Power Dissipation Operating (average) 1.1 1.3 W
D
Power-down Mode 50 80 mW
Θ
Thermal Resistance, Junction to Ambient 30 °C/W
JA
AC TIMING CHARACTERISTICS
PLL Jitter 250 450 ps p-p
Sampling Phase Steps 5.6° per step 64
Sampling Phase Tempco ±1 ps/°C
Sampling Phase Differential Nonlinearity Degrees out of 360° ±3 °
HSYNC Frequency Range 10 150 kHz
f
XTAL
Crystal Frequency Range 23 25 27 MHz
4
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June 2, 2005
X98021
Electrical Specifications Specifications apply for V
= VD = VX = 3.3V, pixel rate = 210MHz, f
A
= 25MHz, TA = 25°C,
XTAL
unless otherwise noted (Continued)
SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT
t
SETUP
DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
1.3 ns
(Note 1)
t
HOLD
DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
2.0 ns
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
f
SCL
SCL Clock Frequency 0 400 kHz
Maximum width of a glitch on SCL that will
2 XTAL periods min 80 ns
be suppressed
t
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
SCL LOW to SDA Data Out Valid 5 XTAL periods plus SDA’s RC time
AA
constant
Time the bus must be free before a new
1.3 µs
See
comment
transmission can start
Clock LOW Time 1.3 µs
Clock HIGH Time 0.6 µs
Start Condition Setup Time 0.6 µs
Start Condition Hold Time 0.6 µs
Data In Setup Time 100 ns
Data In Hold Time 0ns
Stop Condition Setup Time 0.6 µs
Data Output Hold Time 4 XTAL periods min 160 ns
DH
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
µs
SCL
SDA IN
SDA OUT
t
SU:ST
t
HD:STA
5
t
F
t
SU:DAT
t
HIGH
t
LOW
t
HD:DAT
t
R
t
SU:STO
t
t
DH
AA
t
BUF
FIGURE 1. 2 WIRE INTERFACE TIMING
FN8219.0
June 2, 2005
DATACLK
DATACLK
Pixel Data
X98021
t
t
SETUP
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
HOLD
HSYNC
Analog
Video In
DATACLK
RP/GP/BP[7:0]
RS/GS/BS[7:0]
HS
OUT
HSYNC
Analog
Video In
IN
P
P
0
1
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
t
HSYNCin-to-HSout
P
2
= 7.5ns + (PHASE/64 +8.5)*t
P
P
3
P
4
5
P
PIXEL
6
P
P
7
P
8
P
9
10
P
P
11
12
8.5 DATACLK Pipeline Latency
D
D
0
D
1
D
2
3
Programmable
Width and Polarity
FIGURE 3. 24 BIT OUTPUT MODE
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AF E’s output signals
t
HSYNCin-to-HSout
P
P
0
P
1
= 7.5ns + (PHASE/6 4 +8.5)*t
P
2
3
PIXEL
P
P
4
P
5
P
6
P
7
8
P
P
9
P
10
P
11
12
DATACLK
GP[7:0]
RP[7:0]
BP[7:0]
HS
OUT
8.5 DATACLK Pipeline Latency
Programmable
Width and Polarity
FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
6
G0 (Yo) G1 (Y1)G2 (Y2)
(Uo)R1 (V1)B2 (U2)
B
0
FN8219.0
June 2, 2005
X98021
HSYNC
Analog
Video In
DATACLK
RP/GP/BP[7:0]
RS/GS/BS[7:0]
HS
OUT
HSYNC
IN
P
0
The HSY NC edge (programm able leading or trailing) that the DP LL is locked to.
The s a mpling p h a s e se ttin g d e te rmine s its r ela tiv e po s itio n to th e r e st o f th e AFE’s o u tp ut sig n a ls
t
HSYNCin-to-HSout
P
P
1
2
= 7.5ns + (PHASE/64 +10.5)*t
P
P
3
4
PIXEL
P
P
P
P
5
6
7
P
8
9
P
P
10
P
11
12
D
0
D
1
D
2
D
3
Programmable
Width and Polarity
FIGURE 5. 48 BIT OUTPUT MODE
IN
The HSYNC edge (programmable leading or trailing) tha t the DPLL is lock ed to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
Analog
Video In
P
P
P
P
P
P
P
P
P
P
1
2
3
4
5
6
7
0
8
P
9
10
DATACLK
RP/GP/BP[7:0] D
RS/GS/BS[7:0]
HS
OUT
Programmable
Width and Polarity
D
0
D
1
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
P
11
2
7
FN8219.0
June 2, 2005
Pinout
NC
NC
GND
V
BYPASS
GND
RIN1
GND
V
BYPASS
GND
GIN1
RGB
GND
SOG
IN
GND
V
BYPASS
GND
BIN1
GND
RIN2
GND
GIN2
RGB
GND
SOG
IN
GND
BIN2
GND
V
COREADC
GND
HSY NCIN1
HSY NC
IN
GND
GND
X98021
X98021
(128-PIN MQFP)
TOP VIEW
OUT
OUT
OUT
OUT
HSY NC
VS
HS
126
125
VDGNDDDATAC L K
124
123
122
VSYNC
128
127
1
2
3
A
4
5
A
6
V
A
7
8
A
9
10
A
11
V
A
12
13
1
14
1
15
A
16
17
A
18
V
A
19
20
V
A
21
A
22
23
A
24
25
2
26
2
27
A
28
29
V
A
30
A
31
32
D
33
34
2
35
V
A
36
A
37
X
38
V
X
DATAC L K
121
GNDDR
120
0
P
119
1
P
R
118
2
P
R
117
3
P
R
116
4
P
R
115
5
P
R
114
6
P
R
113
7
P
R
112
D
V
111
GNDDV
110
CORE
109
GNDDR
108
0
S
107
1
S
R
106
2
S
R
105
3
S
R
104
4
S
R
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
RS5
R
6
S
R
7
S
V
D
GND
GP0
G
1
P
G
2
P
G
3
P
G
4
P
G
5
P
G
6
P
G
7
P
V
D
GND
GS0
G
1
S
G
2
S
G
3
S
G
4
S
5
G
S
G
6
S
G
7
S
V
CORE
GND
V
D
GND
BP0
B
1
P
B
2
P
3
B
P
B
4
P
5
B
P
6
B
P
7
B
P
V
D
GND
VRE G
D
D
D
D
D
IN
39404142434445464748495051525354555657585960616263
1
2
IN
OUT
XTAL
XTAL
D
IN
CLOCKINV
IN
PLL
V
IN
GND
VSYNC
OUT
RESET
S ADDR
VSYNC
D
SCL
SDA
CORE
GND
V
DVD
GND
7
6
5
4
3
2
1
S
S
S
S
B
B
S
B
B
B
0
S
S
S
B
B
B
XTALCLOCK
8
NC
64
OUT
VRE G
FN8219.0
June 2, 2005
X98021
Pin Descriptions
SYMBOL PIN DESCRIPTION
R
1 7 Analog input. Red channel 1. DC couple or AC couple through 0.1µF.
IN
G
1 12 Analog input. Green channel 1. DC couple or AC couple through 0.1µF.
IN
1 19 Analog input. Blue channel 1. DC couple or AC couple through 0.1µF.
B
IN
RGB
HSYNC
VSYNC
RGB
HSYNC
VSYNC
CLOCKINV
XTAL
XTALCLK
DATACLK 121 3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 48
DATACLK
1 13 Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
GND
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
SOG
1 14 Analog input. Sync on Green. Connect to GIN1 through a 0.01µF capacitor in series with a 500Ω resistor.
IN
1 33 Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GNDA. Connect to channel 1's HSYNC
IN
1 44 Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.
IN
R
2 22 Analog input. Red channel 2. DC couple or AC couple through 0.1µF.
IN
signal through a 680Ω series resistor.
.
A
GIN2 24 Analog input. Green channel 2. DC couple or AC couple through 0.1µF.
B
2 28 Analog input. Blue channel 2. DC couple or AC couple through 0.1µF.
IN
2 25 Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.
GND
SOG
2 26 Analog input. Sync on Green. Connect to GIN1 through a 0.01µF capacitor in series with a 500Ω resistor.
IN
2 34 Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GNDA. Connect to channel 2's HSYNC
IN
2 45 Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.
IN
41 Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame
46 Digital input, 5V tolerant, active low, 70kΩ pull-up to VD. Take low for at least 1µs and then high again to
39 Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
40 Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
47 3.3V digital output. Buffered crystal clock output at f
RESET
XTAL
OUT
IN
IN
OUT
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
.
A
signal through a 680Ω series resistor.
rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to
D
if unused.
GND
reset the X98021. This pin is not necessary for normal use and may be tied directly to the V
recommended loading). Typical oscillation amplitude is 1.0V
recommended loading). Typical oscillation amplitude is 1.0V
system components.
XTAL
centered around 0.5V.
P-P
centered around 0.5V.
P-P
or f
/2. May be used as system clock for other
XTAL
supply.
D
SADDR 48 Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A
including R/W bit) when tied high.
SCL 50 Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA 49 Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
R
[7:0] 112-119 3.3V digital output. Red channel, primary pixel data. 58K pulldown when three-stated.
P
[7:0] 100-107 3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated.
R
S
G
[7:0] 90-97 3.3V digital output. Green channel, primary pixel data. 58K pulldown when three-stated.
P
G
[7:0] 80-87 3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated.
S
[7:0] 68-75 3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated.
B
P
B
[7:0] 55-62 3.3V digital output. Blue channel, secondary pixel data. 58K pulldown when three-stated.
S
bit mode.
122 3.3V digital output. Inverse of DATACLK.
9
FN8219.0
June 2, 2005
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