intersil X95840 DATA SHEET

®

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X95840

Quad Digital Controlled Potentiometers (XDCP™)

Data Sheet July 5, 2006

Low Noise/Low Power/I2C® Bus/256 Taps

The X95840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the four
DCP’s IVR to the corresponding WRs.

The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.

Ordering Information

FN8213.2

Features

• Four Potentiometers in One Package

• 256 Resistor Taps-0.4% Resolution

•I2C Serial Interface

- Three address pins, up to eight devices/bus

• Wiper Resistance: 70Ω Typical @ 3.3V

• Non-Volatile Storage of Wiper Position

• Standby Current < 5µA Max

• Power Supply: 2.7V to 5.5V

•50kΩ, 10kΩ Total Resistance

• High Reliability

- Endurance: 150,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ 75°C

• 20 Ld TSSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

PART

PART NUMBER

X95840WV20I-2.7* X95840WV G 10kΩ 20 Ld TSSOP
X95840WV20IZ-2.7*

(Note)
X95840UV20I-2.7* X95840UV G 50kΩ 20 Ld TSSOP
X95840UV20IZ-2.7*

(Note)
*Add “T1” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

MARKING

X95840WV Z G 10kΩ 20 Ld TSSOP

X95840UV Z G 50kΩ 20 Ld TSSOP

RESISTANCE

OPTION PACKAGE

(Pb-free)

(Pb-free)

Pinouts

RH3

RL3

RW3

A2

SCL

SDA

GND

RW2

RL2

RH2

X95840

(20 LD TSSOP)

TOP VIEW

1

2

3

4

5

6

7

8

9

10

RW0

20

RL0

19

RH0

18

WP

17

V

16

CC

A1

15

A0

14

13

RH1

12

RL1

11

RW1

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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SDA

SCL

A2

A1

A0

I2C

INTERFACE

POWER-UP,

INTERFACE,

CONTROL AND

StAtus LOGIC

NON-VOLATILE

REGISTERS

X95840

V

CC

WR3

WR2

WR1

WR0

DCP3

DCP2

DCP1

DCP0

R

H3

R

W3

R

L3

R

H2

R

W2

R

L2

R

H1

R

W1

R

L1

R

H0

R

W0

R

L0

WP

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1 RH3 “High” terminal of DCP3
2 RL3 “Low” terminal of DCP3
3 RW3 “Wiper” terminal of DCP3
4 A2 Device address for the
5SCLI

2

C interface clock
6 SDA Serial data I/O for the
7 GND Device ground pin
8 RW2 “Wiper” terminal of DCP2
9 RL2 “Low” terminal of DCP2

10 RH2 “High” terminal of DCP2
11 RW1 “Wiper” terminal of DCP1
12 RL1 “Low” terminal of DCP1
13 RH1 “High” terminal of DCP1
14 A0 Device address for the
15 A1 Device address for the
16 V

CC

17 WP

Power supply pin
Hardware write protection pin. Active low. Prevents any “Write” operation of the I

18 RH0 “High” terminal of DCP0
19 RL0 “Low” terminal of DCP0
20 RW0 “Wiper” terminal of DCP0

I2C interface

I2C interface

I2C interface
I2C interface

2

C interface.

2

FN8213.2

July 5, 2006

X95840

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL

INL (Note 6) Integral Non-linearity -1 1 LSB

DNL (Note 5) Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

ZSerror
(Note 3)

FSerror
(Note 4)

V

MATCH

(Note 7)

(Note 8) Ratiometric Temperature Coefficient DCP Register set to 80 hex ±4 ppm/°C

TC

V

RESISTOR MODE (Measurements between RW

RINL

(Note 12)

RDNL

(Note 11)

Roffset

(Note 10)

R

MATCH

(Note 13)

TC

(Note 14)

RH to RL Resistance W, U versions respectively 10, 50 kΩ

to RL Resistance Tolerance -20 +20 %

R

H

Wiper Resistance VCC = 3.3V @ 25°C

Potentiometer Capacitance (Note 15) 10/10/25 pF
Leakage on DCP Pins (Note 15) Voltage at pin from GND to V

; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)

i

Zero-scale Error U option 0 1 7 LSB

Full-scale Error U option -7 -1 0 LSB

DCP to DCP Matching Any two DCPs at same tap position, same

and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0, 1, 2 or 3)

i

Integral Non-linearity DCP register set between 20 hex and

Differential Non-linearity -0.5 0.5 MI

Offset U option 0 1 7 MI

DCP to DCP Matching Any two DCPs at the same tap position with

Resistance Temperature Coefficient DCP register set between 20 hex and FF hex ±45 ppm/°C

R

+0.3

CC

CC

Wiper current = V

W option 0 0.5 2

W option -2 -1 0

voltage at all RH terminals, and same voltage
at all RL terminals

FF hex. Monotonic over all tap positions

W option 0 0.5 2 MI

the same terminal voltages.

Temperature Range (Industrial). . . . . . . . . . . . . . . . . .-40°C to 85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(Note 1) MAX UNIT

70 200 Ω

CC/RTOTAL

CC

-2 2 LSB

-1 1 MI

-2 2 MI

0.1 1 µA

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

3

FN8213.2

July 5, 2006

X95840

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Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

CC

CC

2

C,

2

C,

-0.3 0.3*V

0.7*V

0.05*
V

1300 ns

600 ns

600 ns

.

I

CC1

I

CC2

I

SB

I

LkgDig

t

DCP

(Note 15)

Vpor Power-on Recall Voltage Minimum V

VccRamp VCC Ramp Rate 0.2 V/ms

(Note 15) Power-up Delay VCC above Vpor, to DCP Initial Value Register recall

t

D

EEPROM SPECS

SERIAL INTERFACE SPECS

V

IL

V

IH

Hysteresis

(Note 15)

V

(Note 15) SDA outPut Buffer LOW

OL

Cpin

(Note 15)

f

SCL

(Note 15) Pulse Width Suppression

t

IN

(Note 15) SCL Falling Edge to SDA

t

AA

t

BUF

(Note 15)

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

VCC Supply Current
(Volatile write/read)

VCC Supply Current
(nonvolatile write)

VCC Current (standby) V

Leakage Current, at
Pins A0, A1, A2, SDA, SCL,

Pins

and WP
DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to wiper

EEPROM Endurance 150,000 Cycles
EEPROM Retention Temperature

WP, A2, A1, A0, SDA, and
SCL Input Buffer LOW
Voltage

WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage

SDA and SCL Input Buffer
Hysteresis

Voltage, Sinking 4mA

, A2, A1, A0, SDA, and

WP
SCL Pin Capacitance

SCL frEquency 400 kHz

Time at SDA and SCL Inputs

Output Data Valid
Time the Bus Must be Free

Before the Start of a New
Transmission

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns
START Condition Setup

Time
START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL

f

= 400kHz; SDA = Open; (for I

SCL

Active, Read and Volatile Write States only)
f

= 400kHz; SDA = Open; (for I

SCL

Active, Nonvolatile Write State only)

= +5.5V, I

CC

= +3.6V, I

V

CC

Voltage at pin from GND to V

change

completed, and

2

C Interface in Standby State 5 µA

2

C Interface in Standby State 2 µA

at which memory recall occurs 1.8 2.6 V

CC

I2C Interface in standby state

≤ 75°C 50 Years

Any pulse narrower than the max spec is suppressed. 50 ns

SCL falling edge crossing 30% of VCC, until SDA exits
the 30% to 70% of V

SDA crossing 70% of V
SDA crossing 70% of V
condition.

SCL rising edge to SDA falling edge. Both crossing
70% of V

falling edge crossing 70% of V

CC

.

window.

CC

during a STOP condition, to

CC

during the following STAR T

CC

(Note 1) MAX UNITS

1mA

3mA

-10 10 µA

1µs

3ms

CC

CC

CC

00.4V

VCC+0.3 V

10 pF

900 ns

V

V

4

FN8213.2

July 5, 2006

X95840

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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

(Note 15) Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA

DH

t

(Note 15) SDA and SCL Rise Time From 30% to 70% of V

R

(Note 15) SDA and SCL Fall Time From 70% to 30% of V

t

F

(Note 15) Capacitive Loading of SDA

Cb

Rpu

(Note 15) SDA and SCL Bus Pull-up

Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to

SCL rising edge crossing 30% of V

CC

Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA

entering the 30% to 70% of V

window.

CC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA

rising edge crossing 30% of V

CC

.

STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both

crossing 70% of V

enters the 30% to 70% of V

CC

.

window.

CC

CC

CC

Total on-chip and off-chip 10 400 pF

or SCL

Maximum is determined by tR and tF.

Resistor Off-chip

For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ

t

WP

(Notes 15, 16)

t

SU:WPA

t

HD:WPA

Non-volatile Write Cycle
Time

A2, A1, A0, and WP Setup
Time

A2, A1, A0, and WP Hold
Time

Before START condition 600 ns

After STOP condition 600 ns

100 ns

600 ns

600 ns

20 +

0.1 * Cb
20 +

0.1 * Cb

(Note 1) MAX UNITS

0ns

0ns

1kΩ

TYP

250 ns

250 ns

12 20 ms

SDA vs SCL Timing

SCL

t

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SDA

t

HD:STA

t

F

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

R

t

SU:STO

t

t

DH

AA

t

BUF

5

FN8213.2

July 5, 2006

WP, A0, A1, and A2 Pin Timing

T

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X95840

STOP

SCL

SDA IN

WP, A0, A1, or A2

START

t

SU:WPA

Clk 1

t

HD:WPA

NOTES:

1. Typical values are for T

2. LSB: [V(RW)
incremental voltage when changing from one tap to an adjacent tap.

255

3. ZS error = V(RW)

4. FS error = [V(RW)

5. DNL = [V(RW)

6. INL = [V(RW)

7. V

MATCH

8.

C

V

- V(RW)

i

– (i • LSB – V(RW)0)]/LSB for i = 1 to 255.

i

= [V(RWx)i - V(RWy)i] / LSB, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

Max V RW()

()Min V RW()

--------------------------------------------------------------------------------------------- -

()Min V RW()

Max V RW()

= 25°C and 3.3V supply voltage.

A

- V(RW)0] / 255. V(RW)

/ LSB.

0

- VCC] / LSB.

255

] / LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

()–

i

()+[]2⁄

i

i

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively . LSB is the

255

6

10

i

---------------- -

×=

125°C

for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.

|R

- R

9. MI =

255

10. Roffset = R
Roffset = R

11. RDNL = (R

12. RINL = [R

13. R

14.

= (R

MATCH

--------------------------------------------------------------- -

C

R

Max Ri()Min Ri()+[]2⁄

| / 255. R

0

/ MI, when measuring between RW and RL.

0

/ MI, when measuring between RW and RH.

255

- R

) / MI, for i = 32 to 255.

i

i-1

- (MI • i) - R0] / MI, for i = 32 to 255.

i

- R

i,x

i,y

Max Ri()Min Ri()–[]

and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255

) / MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

6

10

---------------- -

×=

125°C

for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.

15. This parameter is not 100% tested.

is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a

16. t

WC

valid STOP condition at the end of a Write sequence of a I

2

C serial interface Write operation, to the end of the self-timed internal non-volatile

write cycle.

6

FN8213.2

July 5, 2006

Typical Performance Curves

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X95840

160

140

VCC = 2.7, T = -40°C

120

100

80

60

40

WIPER RESISTANCE (Ω)

20

VCC = 5.5, T = -40°C

0

0 50 100 150 200 250

TAP POSITION (DECIMAL)

V

= 2.7, T = 85°C

CC

VCC = 5.5, T = 25°C

VCC = 2.7, T = 25°C

VCC = 5.5, T = 85°C

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

0.2

0.15

0.05

-0.05

DNL (LSB)

-0.15

0.1

-0.1

-0.2

VCC = 2.7, T = 25°C

0

VCC = 2.7, T = 85°C

0 50 100 150 200 250

CC/RTOTAL

VCC = 5.5, T = -40°C

VCC = 5.5, T = 25°C

TAP POSITION (DECIMAL)

] FOR 50kΩ (U)

VCC = 2.7, T = -40°C

VCC = 5.5, T = 85°C

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

1.8

1.6

1.4

1.2

(µA)

1.0

CC

0.8

0.6

STANDBY I

0.4

0.2

0.0

2.7 3.2 3.7 4.2 4.7 5.2

FIGURE 2. STANDBY I

0.3

VCC = 5.5, T = -40°C

0.2

0.1

0

INL (LSB)

-0.1

-0.2

-0.3

= 2.7, T = 85°C

V

CC

0 50 100 150 200 250

-40°C

25°C

V

(V)

CC

CC

V

= 2.7, T = -40°C

CC

= 2.7, T = 25°C

V

CC

TAP POSITION (DECIMAL)

85°C

vs V

CC

VCC = 5.5, T = 85°C

V

= 5.5, T = 25°C

CC

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

0.4

0.35

0.3

0.25

ZSerror (LSB)

0.2

0.15

-40-200 20406080

2.7V

5.5V

TEMPERATURE (°C)

FIGURE 5. ZSerror vs TEMPERATURE

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

FSerror (LSB)

-0.7

-0.8

-0.9

-1

-40

FIGURE 6. FSerror vs TEMPERATURE

7

-20

= 5.5V

V

CC

VCC = 2.7V

0

20 40 60 80

TEMPERATURE (°C)

FN8213.2

July 5, 2006

Typical Performance Curves (Continued)

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X95840

0.3

= 5.5, T = 25°C

V

0.2

0.1

0

DNL (LSB)

-0.1

-0.2

-0.3
32 82 132 182 232

CC

V

= 5.5, T = 85°C

CC

VCC = 2.7, T = -40°C

TAP POSITION (DECIMAL)

VCC = 2.7, T = 25°C

VCC = 2.7, T = 85°C

VCC = 5.5, T = -40°C

FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR

50kΩ (U)

1.50

1.00

0.50

CHANGE (%)

5.5V

0.00

TOTAL

-0.50

-1.00

END TO END R

-1.50

-40-200 20406080

FIGURE 9. END TO END R

2.7V

TEMPERATURE (°C)

TEMPERATURE

% CHANGE vs

TOTAL

0.5

0.4

0.3

0.2

0.1

0

-0.1

INL (LSB)

-0.2

-0.3

= 2.7, T = 85°C

V

-0.4

CC

-0.5
32 82 132 182 232

VCC = 5.5, T = 25°C

TAP POSITION (DECIMAL)

VCC = 5.5, T = 85°C

VCC = 2.7, T = 25°C

VCC = 5.5, T = -40°C

VCC = 2.7, T = -40°C

FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR

50kΩ (U)

20

10

0

TC (ppm/°C)

-10

-20

32 82 132 182 232

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

35

25

15

5

TC (ppm/°C)

-5

-15

-25
32 57 82 107 132 157 182 207 232

TAP POSITION (DECIMAL)

Tap Position = Mid Point
R

TOTAL

FIGURE 12. FREQUENCY RESPONSE (2.2MHz)

FIGURE 11. TC FOR Rheostat MODE IN ppm

8

OUTPUT

= 9.4K

INPUT

FN8213.2

July 5, 2006

Typical Performance Curves (Continued)

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X95840

Signal at Wiper (Wiper Unloaded)

Wiper Movement Mid Point
From 80h to 7fh

FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)

Principles of Operation

The X95840 in as integrated circuit incorporating four DCPs
with their associated registers, non-volatile memory, and a

2

I

C serial interface providing direct communication between

a host and the potentiometers and memory.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP cont ains all zeroes (WR<7: 0>: 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (RW) is closest to its “High” terminal (RH).
As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.

While the X95840 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH. Soon after the power supply
voltage becomes large enough for reliable non-volatile
memory reading, the X95840 reads the value stored on four
different non-volatile Initial Value Registers (IVRs) and loads
them into their corresponding WRs.

The WRs and IVRs can be read or written directly using the

2

I

C serial interface as described in the following sections.

SCL

Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)

FIGURE 14. LARGE SIGNAL SETTLING TIME

Memory Description

The X95840 contains eight non-volatile bytes. they are
accessed by I
through 7 decimal. The first four non-volatile bytes at
addresses 0, 1, 2, and 3, contain the initial value loaded at
power-up into the volatile Wiper Registers (WRs) of DCP0,
DCP1, DCP2, and DCP3 respectively. Bytes at addresses 4,
5, and 6 are available to the user as general purpose
registers. The byte at address 7 is reserved; the user should
not write to it, and its value should be ignored if read.

The volatile WR, and the non-volatile Initial Value Register
(IVR) of a DCP are accessed with the same Address Byte.

A volatile byte at address 8 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.

When the byte at address 8 is all zeroes, which is the default
at power up:

• A read operation to addresses 0, 1, 2 or 3 outputs the
value of the non-volatile IVRs.

• A write operation to addresses 0, 1, 2, or 3 writes the
same value to the WR and IVR of the corresponding DCP.

When the byte at address 8 is 80h (128 decimal):

• A read operation to addresses 0, 1, 2, or 3 outputs the
value of the volatile WR.

• A write operation to addresses 0, 1, 2, or 3 only writes to
the corresponding volatile WR.

It is not possible to write to an IVR without writing the same
value to its corresponding WR.

00h and 80h are the only values that should be written to
address 8. All other values are reserved and must not be
written to address 8.

2

C interface operations with Address Bytes 0

To access the general purpose bytes at addresses 4, 5, or 6, the value at address 8 must be all zeros.

9

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X95840

www.BDTIC.com/Intersil

The X95840 is pre-programed with 80h in the four IVRs.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

8 — Access Control
7 Reserved
6

5
4

3
2
1
0

General Purpose Not Available

IVR3
IVR2
IVR1
IVR0

WR3
WR2
WR1
WR0

WR: Wiper Register, IVR: Initial value Register.

I2C Serial Interface

The X95840 supports a bidirectional I2C bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the X95840
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power up of the X95840 the SDA pin is in the
input mode.

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X95840 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See

2

C interface is conducted by

Figure 15). A START condition is ignored during the power
up sequence and during internal non-volatile write cycles.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).

The X95840 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
X95840 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB in the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation. See Table 2.

TABLE 2. IDENTIFICATION BYTE FORMAT

Logic values at pins A2, A1, and A0 respectively

1 0 1 0 A2 A1 A0 R/W

(MSB) (LSB)

SCL

SDA

START DATA DATA STOP

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

STABLE CHANGE

DATA

STABLE

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SCL from Master

www.BDTIC.com/Intersil

X95840

81 9

SDA Output from

Transmitter

SDA Output from

Receiver

Signals from the

Signals from the

High Impedance

START ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

Write

S

Master

Signal at SDA

X95840

t

Identification

a

r
t

Byte

10100

FIGURE 17. BYTE WRITE SEQUENCE

Address

Byte

000 0A2A1A0

A
C
K

A
C
K

Data
Byte

High Impedance

S

t
o
p

A
C
K

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
X95840 responds with an ACK. At this time, if the Data Byte
is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the X95840 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
X95840 enters its standby state (See Figure 17).

The byte at address 00001000 bin (8 decimal) determines if
the Data Byte is to be written to volatile and/or non-volatile
memory. See “Memory Description” on page 9.

Data Protection

The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.

is active (LOW) the

A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0, 1, 2, 3, or 8 decimal, the
Data Byte is transferred to the appropriate Wiper Register
(WR) or to the Access Control Register, at the falling edge of
the SCL pulse that loads the last bit (LSB) of the Data Byte.
If the Address Byte is between 0 and 6 (inclusive), and the
Access Control Register is all zeros (default), then the STOP
condition initiates the internal write cycle to non-volatile
memory.

Read Operation

A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W
Address Byte, a second START, and a second Identification
byte with the R/W

bit set to “1”. After each of the three bytes,
the X95840 responds with an ACK. Then the X95840
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eight bit of each
byte. The master terminates the read operation (issuing a

bit set to “0”, an

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X95840

www.BDTIC.com/Intersil

STOP condition) following the last bit of the last Data Byte
(See Figure 18).

The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 08h (8 decimal) the

S

Identification

Signals

from the

Master

Signal at SDA

t
a
r
t

Byte
with

R/W

=0

Address

Byte

10100

Signals from the

Slave

A
C
K

A
C
K

FIGURE 18. READ SEQUENCE

S

Identification

t
a
r
t

11100

pointer “rolls over” to 00h, and the device continues to output
data for each ACK received.

The byte at address 00001000 bin (8 decimal) determines if
the Data Bytes being read are from volatile or non-volatile
memory. See “Memory Description” on page 9.

Byte
with

R/W

=1

A
C

First Read Data

K

Byte

A
C
K

A
C
K

Last Read Data

Byte

S

t
o
p

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X95840

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Thin Shrink Small Outline Package Family (TSSOP)

C

SEATING
PLANE

N LEADS

0.25 CAB

M

E

E1

B

0.10 C

N

1

TOP VIEW

e

b

SEE DETAIL “X”

(N/2)+1

SIDE VIEW

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

H

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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13

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July 5, 2006