intersil X95840 DATA SHEET

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X95840

Quad Digital Controlled Potentiometers (XDCP™)

Data Sheet July 5, 2006

Low Noise/Low Power/I2C® Bus/256 Taps

The X95840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the

C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR), that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power up the device recalls the contents of the four DCP’s IVR to the corresponding WRs.

The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.

Ordering Information

FN8213.2

Features

• Four Potentiometers in One Package

• 256 Resistor Taps-0.4% Resolution

•I2C Serial Interface

- Three address pins, up to eight devices/bus

• Wiper Resistance: 70Ω Typical @ 3.3V

• Non-Volatile Storage of Wiper Position

• Standby Current < 5µA Max

• Power Supply: 2.7V to 5.5V

•50kΩ, 10kΩ Total Resistance

• High Reliability

- Endurance: 150,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ 75°C

• 20 Ld TSSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

PART

PART NUMBER

X95840WV20I-2.7* X95840WV G 10kΩ 20 Ld TSSOP X95840WV20IZ-2.7*

(Note) X95840UV20I-2.7* X95840UV G 50kΩ 20 Ld TSSOP X95840UV20IZ-2.7*

(Note) *Add “T1” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

X95840WV Z G 10kΩ 20 Ld TSSOP

X95840UV Z G 50kΩ 20 Ld TSSOP

RESISTANCE

OPTION PACKAGE

(Pb-free)

Pinouts

RH3

RL3

RW3

SCL

SDA

GND

RW2

RL2

RH2

X95840

(20 LD TSSOP)

TOP VIEW

RW0

RL0

RH0

RH1

RL1

RW1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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SDA

SCL

I2C

INTERFACE

POWER-UP,

INTERFACE,

CONTROL AND

StAtus LOGIC

NON-VOLATILE

REGISTERS

X95840

WR3

WR2

WR1

WR0

DCP3

DCP2

DCP1

DCP0

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1 RH3 “High” terminal of DCP3 2 RL3 “Low” terminal of DCP3 3 RW3 “Wiper” terminal of DCP3 4 A2 Device address for the 5SCLI

C interface clock 6 SDA Serial data I/O for the 7 GND Device ground pin 8 RW2 “Wiper” terminal of DCP2 9 RL2 “Low” terminal of DCP2

10 RH2 “High” terminal of DCP2 11 RW1 “Wiper” terminal of DCP1 12 RL1 “Low” terminal of DCP1 13 RH1 “High” terminal of DCP1 14 A0 Device address for the 15 A1 Device address for the 16 V

17 WP

Power supply pin Hardware write protection pin. Active low. Prevents any “Write” operation of the I

18 RH0 “High” terminal of DCP0 19 RL0 “Low” terminal of DCP0 20 RW0 “Wiper” terminal of DCP0

I2C interface

I2C interface I2C interface

C interface.

FN8213.2

July 5, 2006

X95840

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

TOTAL

H/CL/CW

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL

INL (Note 6) Integral Non-linearity -1 1 LSB

DNL (Note 5) Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

ZSerror (Note 3)

FSerror (Note 4)

MATCH

(Note 7)

(Note 8) Ratiometric Temperature Coefficient DCP Register set to 80 hex ±4 ppm/°C

RESISTOR MODE (Measurements between RW

RINL

(Note 12)

RDNL

(Note 11)

Roffset

(Note 10)

MATCH

(Note 13)

(Note 14)

RH to RL Resistance W, U versions respectively 10, 50 kΩ

to RL Resistance Tolerance -20 +20 %

Wiper Resistance VCC = 3.3V @ 25°C

Potentiometer Capacitance (Note 15) 10/10/25 pF Leakage on DCP Pins (Note 15) Voltage at pin from GND to V

; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)

Zero-scale Error U option 0 1 7 LSB

Full-scale Error U option -7 -1 0 LSB

DCP to DCP Matching Any two DCPs at same tap position, same

and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0, 1, 2 or 3)

Integral Non-linearity DCP register set between 20 hex and

Differential Non-linearity -0.5 0.5 MI

Offset U option 0 1 7 MI

DCP to DCP Matching Any two DCPs at the same tap position with

Resistance Temperature Coefficient DCP register set between 20 hex and FF hex ±45 ppm/°C

+0.3

Wiper current = V

W option 0 0.5 2

W option -2 -1 0

voltage at all RH terminals, and same voltage at all RL terminals

FF hex. Monotonic over all tap positions

W option 0 0.5 2 MI

the same terminal voltages.

Temperature Range (Industrial). . . . . . . . . . . . . . . . . .-40°C to 85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(Note 1) MAX UNIT

70 200 Ω

CC/RTOTAL

-2 2 LSB

-1 1 MI

-2 2 MI

0.1 1 µA

(Note 2)

(Note 9)

FN8213.2

July 5, 2006

X95840

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

-0.3 0.3*V

0.7*V

0.05* V

1300 ns

600 ns

CC1

CC2

LkgDig

DCP

(Note 15)

Vpor Power-on Recall Voltage Minimum V

VccRamp VCC Ramp Rate 0.2 V/ms

(Note 15) Power-up Delay VCC above Vpor, to DCP Initial Value Register recall

EEPROM SPECS

SERIAL INTERFACE SPECS

Hysteresis

(Note 15)

(Note 15) SDA outPut Buffer LOW

Cpin

(Note 15)

SCL

(Note 15) Pulse Width Suppression

(Note 15) SCL Falling Edge to SDA

BUF

(Note 15)

LOW

HIGH

SU:STA

HD:STA

VCC Supply Current (Volatile write/read)

VCC Supply Current (nonvolatile write)

VCC Current (standby) V

Leakage Current, at Pins A0, A1, A2, SDA, SCL,

Pins

and WP DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to wiper

EEPROM Endurance 150,000 Cycles EEPROM Retention Temperature

WP, A2, A1, A0, SDA, and SCL Input Buffer LOW Voltage

WP, A2, A1, A0, SDA, and SCL Input Buffer HIGH Voltage

SDA and SCL Input Buffer Hysteresis

Voltage, Sinking 4mA

, A2, A1, A0, SDA, and

WP SCL Pin Capacitance

SCL frEquency 400 kHz

Time at SDA and SCL Inputs

Output Data Valid Time the Bus Must be Free

Before the Start of a New Transmission

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns START Condition Setup

Time START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL

= 400kHz; SDA = Open; (for I

SCL

Active, Read and Volatile Write States only) f

= 400kHz; SDA = Open; (for I

SCL

Active, Nonvolatile Write State only)

= +5.5V, I

= +3.6V, I

Voltage at pin from GND to V

change

completed, and

C Interface in Standby State 5 µA

C Interface in Standby State 2 µA

at which memory recall occurs 1.8 2.6 V

I2C Interface in standby state

≤ 75°C 50 Years

Any pulse narrower than the max spec is suppressed. 50 ns

SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of V

SDA crossing 70% of V SDA crossing 70% of V condition.

SCL rising edge to SDA falling edge. Both crossing 70% of V

falling edge crossing 70% of V

window.

during a STOP condition, to

during the following STAR T

(Note 1) MAX UNITS

1mA

3mA

-10 10 µA

1µs

3ms

00.4V

VCC+0.3 V

10 pF

900 ns

FN8213.2

July 5, 2006

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