intersil X9530 DATA SHEET

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Data Sheet November 11, 2005

X9530

FN8211.1

Temperature Compensated Laser Diode
Controller

FEATURES

• Compatible with Popular Fiber Optic Module
Specifications such as Xenpak, SFF, SFP, and
GBIC

• Package
—14 Ld TSSOP

• Two Programmable Current Generators
—±1.6 mA max.
—8-bit (256 Step) Resolution

• Integrated 6 bit A/D Converter

• Temperature Compensation
—Internal or External Sensor
—-40°C to +100°C Range
—2.2°C/step Resolution
—EEPROM Look-up Tables

• Hot Pluggable

• 2176-bit EEPROM
—17 Pages
—16 Bytes per Page

• Write Protection Circuitry
—Intersil BlockLock™
—Logic Controlled Protection
—2-wire Bus with 3 Slave Address Bits

• 3V to 5.5V, Single Supply Operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

LASER DIODE BIAS CONTROL APPLICATIONS

• SONET and SDH Transmission Systems

• 1G and 10G Ethernet, and Fibre Channel Laser
Diode Driver Circuits

DESCRIPTION

The X9530 is a highly integrated laser diode bias
controller which incorporates two digitally controlled
Programmable Current Generators, temperature
compensation with dedicated look-up tables, and
supplementary EEPROM array. All functions of the
device are controlled via a 2-wire digital serial interface.

Two temperature compensated Programmable Current
Generators, vary the output current with temperature
according to the contents of the associated nonvolatile
look-up table. The look-up table may be programmed
with arbitrary data by the user, via the 2-wire serial port,
and either an internal or external temperature sensor
may be used to control the output current response.
These temperature compensated pro-grammable
currents maybe used to control the modulation current
and the bias current of a laser diode.

The integrated General Purpose EEPROM is included
for product data storage and can be used for transceiver
module information storage in laser diode applications.

PART

NUMBER

X9530V14I* X9530V -40 to 100 14 LEAD TSSOP
X9530V14IZ*

(Note)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PART

MARKING

X9530V Z -40 to 100 14 LEAD TSSOP

TEMP RANGE

(°C) PACKAGE

(Pb-free)

PIN CONFIGURATION

1

A0
A1

A2
Vcc
WP

SCL

SDA

2
3

4
5
6

7

14
13

12
11
10

9
8

I2
VRef
VSense

Vss
R2

R1
I1

TSSOP 14L

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

TYPICAL APPLICATION

www.BDTIC.com/Intersil

High Speed
Data Input

X9530

GBIC / SFP / XFP Module

V

CC

MPDLD

MOD_DEF

MOD_DEF

(0)

(1)

BLOCK DIAGRAM

VSense

X9530

SDA

SCK

Reference

Temperature

Sensor

SDA

SCL

WP

I

1

I

2

Voltage

I

MODSET

I

PINSET/IBIASSET

ADC

2-Wire

Interface

Mux

Mux

Laser
Diode
Driver

Circuit

Look-up

Table 2

Look-up

Table 1

Control

& Status

General
Purpose
Memory

Mux

Mux

I

LD

DAC 2

DAC 1

I

MON

R2

I2VRef

I1

R1

A2, A1, A0

DEVICE DESCRIPTION

The X9530 combines two Programmable Current
Generators, and integrated EEPROM with Block
Lock™ protection, in one package. The
Programmable Current Generators are ideal for use in
fiber optic Modulation Current require temperature
control. The combination of the X9530 functionality
and Intersil’s Chip-Scale package lowers system cost,
increases reliability, and reduces board space
requirements.

Two on-chip Programmable Current Generators may
be independently programmed to either sink or source
current. The maximum current generated is
determined by using an externally connected
programming resistor, or by selecting one of three

2

predefined values. Both current generators have a
maximum output of ±1.6 mA, and may be controlled to
an absolute resolution of 0.39% (256 steps / 8 bit).

Both current generators may be driven using an on­board temperature sensor, an external sensor, or
Control Registers. The internal temperature sensor
operates over a very broad temperature range (-40
to +100

°C). The sensor output (internal or external)

°C

drives a 6-bit A/D converter, whose output selects one
of 64 bytes from each nonvolatile look-up table (LUT).

The contents of the selected LUT row (8-bit wide)
drives the input of an 8-bit D/A converter, which
generates the output current.

All control and setup parameters of the X9530,
including the look-up tables, are programmable via the
2-wire serial port.

FN8211.1

November 11, 2005

X9530

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The general purpose memory portion of the device is a
CMOS serial EEPROM array with Intersil’s Block

TM

Lock

protection. This memory may be used to store
fiber optic module manufacturing data, serial numbers,
or various other system parameters.

The EEPROM array is internally organized as 272 x 8
bits with 16-Byte pages, and utilizes Intersil’s
proprietary Direct Write™ cells, providing a minimum
endurance of 100,000 Page Write cycles and a
minimum data retention of 100 years.

PIN ASSIGNMENTS

TSSOP

Pin

1A0Device Address Select Pin 0. This pin determines the LSB of the device address

2A1Device Address Select Pin 1. This pin determines the intermediate bit of the device address re-

3A2Device Address Select Pin 2. This pin determines the MSB of the device address required to

4VccSupply Voltage.

5WP

6SCLSerial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling

7SDASerial Data. This pin is the 2-wire interface data into or out of the device. It is TTL

8I1Current Generator 1 Output. This pin sinks or sources current. The magnitude and direction of

9R1Current Programming Resistor 1. A resistor between this pin and Vss can set the maximum

10 R2 Current Programming Resistor 2. A resistor between this pin and Vss can set the maximum

11 Vss Ground.

12 VSense Sensor Voltage Input. This voltage input may be used to drive the input of the on-chip A/D con-

13 VRef Reference Voltage Input or Output. This pin can be configured as either an Input or an Output.

14 I2 Current Generator 2 Output. This pin sinks or sources current. The magnitude and direction of

Pin

Name Pin Description

required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor.

quired to communicate using the 2-wire interface. The A1 pin has an on-chip pull-down resistor.

communicate using the 2-wire interface. The A2 pin has an on-chip pull-down resistor.

Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection
is enabled preventing any “Write” operation. When HIGH, various areas of the memory can be
protected using the Block Lock bits BL1 and BL0. The WP
which enables the Write Protection when this pin is left floating.

data input and output at the SDA pin.

compatible when used as an input, and it is Open Drain when used as an output. This pin requires
an external pull up resistor.

the current is fully programmable and adaptive. The resolution is 8 bits.

output current available at pin I1. If no resistor is used, the maximum current must be selected
using control register bits.

output current available at pin I2. If no resistor is used, the maximum current must be selected
using control register bits.

verter.

As an Input, the voltage at this pin is provided by an external source. As an Output, the voltage
at this pin is a buffered output voltage of the on-chip bandgap reference circuit. In both cases, the
voltage at this pin is the reference for the A/D
converter and the two D/A converters.

the current is fully programmable and adaptive. The resolution is 8 bits.

pin has an on-chip pull-down resistor,

3

FN8211.1

November 11, 2005

X9530

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PRINCIPLES OF OPERATION

CONTROL AND STATUS REGISTERS

The Control and Status Registers provide the user
with a mechanism for changing and reading the value
of various parameters of the X9530. The X9530
contains seven Control, one Status, and several
Reserved registers, each being one Byte wide (See
Figure 1). The Control registers 0 through 6 are
located at memory addresses 80h through 86h
respectively. The Status register is at memory address
87h, and the Reserved registers at memory address
88h through 8Fh.

All bits in Control register 6 always power-up to the
logic state “0”. All bits in Control registers 0 through 5
power-up to the logic state value kept in their
corresponding nonvolatile memory cells. The
nonvolatile bits of a register retain their stored values
even when the X9530 is powered down, then powered
back up. The nonvolatile bits in Control 0 through
Control 5 registers are all preprogrammed to the logic
state “0” at the factory.

Bits indicated as “Reserved” are ignored when read,
and must be written as “0”, if any Write operation is
performed to their registers.

A detailed description of the function of each of the
Control and Status register bits follows:

Control Register 0

This register is accessed by performing a Read or
Write operation to address 80h of memory.

BL1, BL0: B

ON-VOLATILE)

(N

These two bits are used to inhibit any write operation
to certain addresses within the memory array. The
protected region of memory is determined by the
values of the two bits as shown in the table below:

BL1

0 0 None (Default) None (Default)

0 1 00h to 7Fh (128 bytes)

1 0 00h to 7Fh and 90h to

1 1 00h to 7Fh and 90h to

If the user attempts to perform a write operation to a
protected region of memory, the operation is aborted
without changing any data in the array.

LOCK LOCK PROTECTION BITS

Protected Addresses

BL0

(Size)

CFh (192 bytes)

10Fh (256 bytes)

Partition of array

locked

GPM

GPM, LUT1

GPM, LUT1, LUT2

Notice that if the Write Protect (WP
X9530 is active (LOW), then any write operation to
the memory is inhibited, irrespective of the Block
Lock bit settings.

VRM: V
(N

The VRM bit configures the Voltage Reference pin
(VRef) as either an input or an output. When the VRM
bit is set to “0” (default), the voltage at pin VRef is an
output from the X9530’s internal voltage reference.
When the VRM bit is set to “1”, the voltage reference
for the VRef pin is external. See Figure 2.

ADCIN: A/D C
(NON-VOLATILE)

The ADCIN bit selects the input of the on-chip A/D
converter. When the ADCIN bit is set to “0” (default),
the output of the on-chip temperature sensor is the
input to the A/D converter. When the ADCIN bit is set
to “1”, the input to the A/D converter is the voltage at
the VSense pin. See Figure 4.

ADC
(N

When this bit is “1”, the status register at 87h is
updated after every conversion of the ADC. When this
bit is “0” (default), the status register is updated after
four consecutive conversions with the same result.

NV1234: C

TILITY MODE SELECTION BIT (NON-VOLATILE)

When the NV1234 bit is set to “0” (default), bytes
written to Control registers 1, 2, 3, and 4 are stored in
volatile cells, and their content is lost when the X9530
is powered down. When the NV1234 bit is set to “1”,
bytes written to Control registers 1, 2, 3, and 4 are
stored in both volatile and nonvolatile cells, and their
value doesn’t change when the X9530 is powered
down and powered back up. See “Writing to Control
Registers” on page 17.

I1DS: C
(N

The I1DS bit sets the polarity of Current Generator 1,
DAC1. When this bit is set to “0” (default), the Current
Generator 1 of the X9530 is configured as a Current
Source. Current Generator 1 is configured as a
Current Sink when the I1DS bit is set to “1”. See
Figure 5.

OLTAGE REFERENCE PIN MODE

ON-VOLATILE)

ONVERTER INPUT SELECT

FILTOFF: ADC FILTERING CONTROL

ON-VOLATILE)

ONTROL REGISTERS 1, 2, 3, AND 4 VOLA-

URRENT GENERATOR 1 DIRECTION SELECT BIT

ON-VOLATILE)

) input pin of the

4

FN8211.1

November 11, 2005

Figure 1. Control and Status Register Format

www.BDTIC.com/Intersil

X9530

Byte

Address

80h

Non-Volatile

81h

Volatile or

Non-Volatile

82h

Volatile or

Non-Volatile

83h

Volatile or

Non-Volatile

84h

Volatile or

Non-Volatile

MSB LSB

7

6

5

4

3

21

BL1 BL0I1DS NV1234I2DS ADCfiltOff ADCIN VRM

I1 and I2 Direction
0: Source
1: Sink

Control
1, 2, 3, 4
Volatility
0: Volatile
1: Non-

volatile

ADC
filtering

0: On
1: Off

ADC Input
0: Internal
1: External

Voltage Block Lock
Reference
Mode
0: Internal
1: External

00: None Locked
01: GPM Locked
10: GPM, LUT1, Locked
11: GPM, LUT1, LUT2

Locked

Direct Access to LUT1

Reserved Reserved L1DA5 L1DA4 L1DA3 L1DA2 L1DA1 L1DA0

Direct Access to LUT2

Reserved Reserved L2DA5 L2DA4 L2DA3 L2DA2 L2DA1 L2DA0

Direct Access to DAC1

D1DA7 D1DA6 D1DA5 D1DA4 D1DA3 D1DA2 D1DA1 D1DA0

Direct Access to DAC2

D2DA7 D2DA6 D2DA5 D2DA4 D2DA3 D2DA2 D2DA1 D2DA0

Register

0

Name

Control 0

Control 1

Control 2

Control 3

Control 4

85h

Non-Volatile

86h

Volatile

87h

Volatile

D2DAS L2DAS D1DAS L1DAS I2FSO1 I2FSO0 I1FSO1 I1FSO0

Direct
Access
to DAC2
0: Disabled
1: Enabled

Direct Direct Direct R2 Selection
Access
to LUT2
0: Disabled
1: Enabled

Access
to DAC1
0: Disabled 0: Disabled
1: Enabled 1: Enabled

Access
to LUT1

00: External
01: Low Internal
10: Middle Internal
11: High Internal

R1 Selection
00: External
01: Low Internal
10: Middle Internal
11: High Internal

WEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Write
Enable
Latch
0: Write

Disabled

1: Write

Enabled

ADC Output

AD5 AD4 AD3 AD2 AD1 AD0 Reserved Reserved

Registers in byte addresses 88h through 8Fh are reserved.

Control 5

Control 6

Status

5

FN8211.1

November 11, 2005

X9530

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I2DS: CURRENT GENERATOR 2 DIRECTION SELECT BIT

ON-VOLATILE)

(N

The I2DS bit sets the polarity of Current Generator 2,
DAC2. When this bit is set to “0” (default), the Current
Generator 2 of the X9530 is configured as a Current
Source. Current Generator 2 is configured as a
Current Sink when the I2DS bit is set to “1”. See
Figure 5.

Control Register 1

This register is accessed by performing a Read or Write
operation to address 81h of memory. This byte’s volatility
is determined by bit NV1234 in Control register 0.

L1DA5 - L1DA0: LUT1 D

IRECT ACCESS BITS

When bit L1DAS (bit 4 in Control register 5) is set to
“1”, LUT1 is addressed by these six bits, and it is not
addressed by the output of the on-chip A/D converter.
When bit L1DAS is set to “0”, these six bits are ignored
by the X9530. See Figure 7.

A value between 00h (00

) and 3Fh (6310) may be

10

written to these register bits, to select the corresponding
row in LUT1. The written value is added to the base
address of LUT1 (90h).

Control Register 2

This register is accessed by performing a read or write
operation to address 82h of memory. This byte’s
volatility is determined by bit NV1234 in Control
register 0.

L2DA5 - L2DA0: LUT2 D

IRECT ACCESS BITS

When bit L2DAS (bit 6 in Control register 5) is set to
“1”, LUT2 is addressed by these six bits, and it is not
addressed by the output of the on-chip A/D converter.
When bit L2DAS is set to “0”, these six bits are ignored
by the X9530. See Figure 7.

A value between 00h (00

) and 3Fh (6310) may be

10

written to these register bits, to select the corresponding
row in LUT2. The written value is added to the base
address of LUT2 (D0h).

D1DA7 - D1DA0: D/A 1 D

IRECT ACCESS BITS

When bit D1DAS (bit 5 in Control register 5) is set to
“1”, the input to the D/A converter 1 is the content of
bits D1DA7 - D1DA0, and it is not a row of LUT1.
When bit D1DAS is set to “0” (default) these eight bits
are ignored by the X9530. See Figure 6.

Control Register 4

This register is accessed by performing a Read or
Write operation to address 84h of memory. This byte’s
volatility is determined by bit NV1234 in Control
register 0.

D2DA7 - D2DA0: D/A 2 D

IRECT ACCESS BITS

When bit D2DAS (bit 7 in Control register 5) is set to
“1”, the input to the D/A converter 2 is the content of
bits D2DA7 - D2DA0, and it is not a row of LUT2.
When bit D2DAS is set to “0” (default) these eight bits
are ignored by the X9530. (See Figure 6).

Control Register 5

This register is accessed by performing a Read or
Write operation to address 85h of memory.

I1FSO1 - I1FSO0: C

UTPUT SET BITS (NON-VOLATILE)

O

URRENT GENERATOR 1 FULL SCALE

These two bits are used to set the full scale output
current at the Current Generator 1 pin, I1. If both bits
are set to “0” (default), an external resistor connected
between pin R1 and Vss, determines the full scale
output current available at pin I1. The other three
options are indicated in the table below. The direction
of this current is set by bit I1DS in Control register 0.
See Figure 5.

I1FSO1 I1FSO0 I1 Full Scale Output Current

0 0 Set externally via pin R1 (Default)
01 ±0.4mA*
10 ±0.85 mA*
11 ±1.3 mA*

*No external resistor should be connected in these cases between
R1 and V

SS

.

Control Register 3

This register is accessed by performing a Read or Write
operation to address 83h of memory. This byte’s volatility
is determined by bit NV1234 in Control register 0.

6

FN8211.1

November 11, 2005

X9530

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I2FSO1–I2FSO0: CURRENT GENERATOR 2 FULL

CALE OUTPUT CURRENT SET BITS (NON-VOLATILE)

S

These two bits are used to set the full scale output
current at the Current Generator 2 pin, I2. If both bits
are set to “0” (default), an external resistor connected
between pin R2 and Vss, determines the full scale
output current available at pin I2. The other three
options are indicated in the table below. The direction
of this current is set by bit I2DS in Control Register 0.

I2FSO1 I2FSO0 I2 Full Scale Output Current

0 0 Set externally via pin R2 (Default)

01 ±0.4mA*

10 ±0.85 mA*

11 ±1.3 mA*

*No external resistor should be connected in these cases between
R2 and V

SS

.

L1DAS: LUT1 DIRECT ACCESS SELECT BIT (NON-

VOLATILE)

When bit L1DAS is set to “0” (default), LUT1 is
addressed by the output of the on-chip A/D converter.
When bit L1DAS is set to “1”, LUT1 is addressed by
bits L1DA5 - L1DA0.

D1DAS: D/A 1 D

VOLATILE)

IRECT ACCESS SELECT BIT (NON-

When bit D1DAS is set to “0” (default), the input to the
D/A converter 1 is a row of LUT1. When bit D1DAS is
set to “1”, that input is the content of the Control
register 3.

L2DAS: LUT2 D

VOLATILE)

IRECT ACCESS SELECT BIT (NON-

When bit L2DAS is set to “0” (default), LUT2 is
addressed by the output of the on-chip A/D converter.
When bit L2DAS is set to “1”, LUT2 is addressed by
bits L2DA5 - L2DA0.

D2DAS: D/A 2 D

VOLATILE)

IRECT ACCESS SELECT BIT (NON-

When bit D2DAS is set to “0” (default), the input to the
D/A converter 2 is a row of LUT2. When bit D2DAS is
set to “1”, that input is the content of the Control
register 4.

Control Register 6

This register is accessed by performing a Read or
Write operation to address 86h of memory.

WEL: W

RITE ENABLE LATCH (VOLATILE)

The WEL bit controls the Write Enable status of the
entire X9530 device. This bit must be set to “1” before
any other Write operation (volatile or nonvolatile).
Otherwise, any proceeding Write operation to memory
is aborted and no ACK is issued after a Data Byte.

The WEL bit is a volatile latch that powers up in the “0”
state (disabled). The WEL bit is enabled by writing
10000000

to Control register 6. Once enabled, the

2

WEL bit remains set to “1” until the X9530 is powered
down, and then up again, or until it is reset to “0” by
writing 00000000

to Control register 6.

2

A Write operation that modifies the value of the WEL
bit will not cause a change in other bits of Control
register 6.

Status Register - ADC Output

This register is accessed by performing a Read
operation to address 87h of memory.

AD5 - AD0: A/D C

ONLY)

ONVERTER OUTPUT BITS (READ

These six bits are the binary output of the on-chip A/D
converter. The output is 000000
and 111111

for full scale input.

2

for minimum input

2

7

FN8211.1

November 11, 2005

X9530

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VOLTAGE REFERENCE

The voltage reference to the A/D and D/A converters
on the X9530, may be driven from the on-chip voltage
reference, or from an external source via the VRef pin.
Bit VRM in Control Register 0 selects between the two
options (See Figure 2).

The default value of VRM is “0”, which selects the
internal reference. When the internal reference is
selected, it’s output voltage is also an output at pin
VRef with a nominal value of 1.21 V. If an external
voltage reference is preferred, the VRM bit of the
Control Register 0 must be set to “1”.

Figure 2. Voltage Reference Structure

VRM: bit 2 in Control register 0.

VRef Pin

On-chip

Voltage

Reference

A/D Converter and
D/A Converters reference

A/D CONVERTER

The X9530 contains a general purpose, on-chip, 6-bit
Analog to Digital (A/D) converter whose output is
available at the Status Register as bits AD[5:0]. By

default these output bits are used to select a row in the
look-up tables associated with the X9530’s Current
Generators. When bit ADCfiltOff is “0” (default), bits
AD[5:0] are updated each time the ADC performs four
consecutive conversions with the same exact result.
When bit ADCfiltOff is “1”, these bits are updated after
every ADC conversion.

A block diagram of the A/D converter is shown in
Figure 3. The voltage reference input (see “VOLTAGE
REFERENCE” for details), sets the maximum
amplitude of the ramp generator output. The A/D
converter input signal (see “A/D Converter Input
Select” below for details) is compared to the ramp
generator output. The control and encode logic
produces a binary encoded output, with a minimum
value of 00h (0

).

(63

10

The A/D converter input voltage range (VIN

), and a full scale output value of 3Fh

10

ADC

) is

from 0 V to V(VRef).

A/D Converter Input Select

The input signal to the A/D converter on the X9530,
may be the output of the on-chip temperature sensor,
or an external source via the VSense pin. Bit ADCIN in
Control register 0 selects between the two options
(See Figure 4). It’s default value is “0”, which selects
the internal temperature sensor.

If an external source is intended as the input to the
A/D converter, the ADCIN bit of the Control register 0
must be set to “1”.

Figure 3. A/D Converter Block Diagram

A/D Converter Input

From VRef

Ramp

Generator

8

Comparator

Conversion Reset

Clock

Control and

Encode Logic

6

A/D Converter

Output

(To LUTs

and Status

Register)

FN8211.1

November 11, 2005

X9530

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Figure 4. A/D Converter Input Select Structure

ADCIN: bit 3 in Control register 0.

VSense

Pin

On-chip

Temperature

Sensor

VRef

To A/D
Converter
Input

A/D Converter Range

From Figure 3 we can see that the operating range of
the A/D converter input depends on the voltage
reference. And from Figure 4 we see that the internal
temperature Sensor output also varies with the voltage
reference (VRef).

The table below summarizes the voltage range
restrictions on the VSense and VRef pins in different
configurations :

VSense and VRef ranges

VRef A/D Converter Input Ranges

Internal Internal Temp. Sensor Not Applicable

Internal VSense Pin 0 ≤ V(VSense) ≤

V(VRef)

External VSense Pin 0 ≤ V(VRef) ≤ 1.3 V

0 ≤ V(VSense) ≤

V(VRef)

External Internal Temp. Sensor Not a Valid Case

All voltages referred to Vss.

LOOK-UP TABLES

The X9530 memory array contains two 64-byte look-up
tables. One is associated to pin I1’s output current
generator and the other to pin I2’s output current
generator, through their corresponding D/A converters.
The output of each look-up table is the byte contained in
the selected row. By default these bytes are the inputs
to the D/A converters driving pins I1 and I2.

The byte address of the selected row is obtained by
adding the look-up table base address (90h for LUT1,
and D0h for LUT2) and the appropriate row selection
bits. See Figure 6.

By default the look-up table selection bits are the 6-bit
output of the A/D converter. Alternatively, the A/D
converter can be bypassed and the six row selection
bits are the six LSBs of Control Registers 1 and 2, for
the LUT1 and LUT2 respectively. The selection
between these options is illustrated in Figure 7, and
described in “I2DS: Current Generator 2 Direction Select
Bit (Non-volatile)” on page 6, and “Control Register 2”
on page 6.

CURRENT GENERATOR BLOCK

The Current Generator pins I1 and I2 are outputs of
two independent current mode D/A converters.

D/A Converter Operation

The Block Diagram for each of the D/A converters is
shown in Figure 5.

The input byte of the D/A converter selects a voltage
on the non-inverting input of an operational amplifier.
The output of the amplifier drives the gate of a FET,
whose source is connected to ground via resistor R1.
This node is also fed back to the inverting input of the
amplifier. The drain of the FET is connected to the
output current pin (I1) via a “polarity select” circuit
block.

9

FN8211.1

November 11, 2005