intersil X9523 DATA SHEET

®

www.BDTIC.com/Intersil

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Data Sheet January 3, 2006

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Laser Diode Control for Fiber Optic Modules

X9523

FN8209.1

Dual DCP, POR, Dual Voltage Monitors

FEATURES

• Two Digitally Controlled Potentiometers (DCPs)
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Nonvolatile
—Write Protect Function

• 2-Wire Industry Standard Serial Interface

• Power-On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset

• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages

• Single Supply Operation
—2.7V to 5.5V

• Hot Pluggable

• 20 Pin Package
—TSSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

DESCRIPTION

The X9523 combines two Digitally Controlled Potenti­ometers (DCPs), V1 / Vcc Power-on Reset (POR) cir­cuitry, qnd two programmable voltage monitor inputs
with software and hardware indicators. All functions of
the X9523 are accessed by an industry standard 2-Wire
serial interface.

The DCPs of the X9523 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The programmable POR circuit may be
used to ensure that V1 / Vcc is stable before power is
applied to the laser diode / module. The programmable
voltage monitors may be used for monitoring various
module alarm levels.

The features of the X9523 are ideally suited to simpli­fying the design of fiber optic modules . The integra­tion of these functions into one package significantly
reduces board area, cost and increases reliability of
laser diode modules.

BLOCK DIAGRAM

WP

SDA

SCL

MR

V3

V2

V1 / Vcc

DATA

REGISTER

COMMAND
DECODE &
CONTROL

LOGIC

THRESHOLD

RESET LOGIC

VTRIP

VTRIP

VTRIP

R

WIPER

COUNTER

PROTECT LOGIC

8

CONSTAT

REGISTER

2

-

+

3

-

+

2

POWER-ON /

+

-

1

LOW VOLTAGE

RESET

GENERATION

REGISTER

7 - BIT

NONVOLATILE

MEMORY

WIPER
COUNTER
REGISTER

8 - BIT

NONVOLATILE

MEMORY

R

R

R

R

R

V3RO

V2RO

V1RO

H1

W1

L1

H2

W2

L2

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

X9523

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Ordering Information

PART

NUMBER

X9523V20I-A X9523VIA -40 to +85 20 Ld TSSOP
X9523V20I-B X9523VIB -40 to +85 20 Ld TSSOP
X9523V20IZ-A

(Note)
X9523V20IZ-B

(Note)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

DETAILED DEVICE DESCRIPTION

The X9523 combines two Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/Vcc power-on reset
control, V1/Vcc low voltage reset control, and two sup­plementary voltage monitors in one package. These
functions are suited to the control, support, and monitor­ing of various system parameters in fiber optic modules.
The combination of the X9523 functionality lowers sys­tem cost, increases reliability, and reduces board space
requirements.

Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.

Applying voltage to V
circuit which allows the V1RO output to go HIGH, until
the supply the supply voltage stabilizes for a period of
time (selectable via software). The V1RO output then
goes LOW. The Low Voltage Reset circuitry allows the
V1RO output to go HIGH when V
mum V

trip point. V1RO remains HIGH until V

CC

returns to proper operating level. A Manual Reset (MR)
input allows the user to externally trigger the V1RO out­put (HIGH).

PART

MARKING

X9523VZIA -40 to +85 20 Ld TSSOP

X9523VZIB -40 to +85 20 Ld TSSOP

TEMP RANGE

(°C) PACKAGE

(Pb-free)

(Pb-free)

activates the Power-on Reset

CC

falls below the mini-

CC

CC

PIN CONFIGURATION

20 Pin TSSOP

R

H2

R

W2 2

R

V3

V3RO

MR

WP

SCL

SDA

V

SS

1

3

L2

4
5
6

7
8

9

10

20
19
18
17

16
15
14
13
12
11

V1 / Vcc

V1RO

V2RO
V2
NC

NC

NC
R

H1

R

W1

R

L1

NOT TO SCALE

Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware out­put (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two moni­tor outputs can be read out via the 2-wire serial port.

Intersil’s unique circuits allow for all internal trip volt­ages to be individually programmed with high accu­racy. This gives the designer great flexibility in
changing system parameters, either at the time of
manufacture, or in the field.

The device features a 2-Wire interface and software

2

protocol allowing operation on an I

C™ compatible

serial bus.

2

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

PIN ASSIGNMENT

Pin Name Function

1

2

3

R

H2

R

w2

R

L2

4V3

5V3RO

6MR

7WP

8SCL

9SDA

10 Vss Ground.

11

12

13

R

L1

R

w1

R

H1

17 V2

18 V2RO

19 V1RO

20 V1 / Vcc Supply Voltage.

14, 15,

16,

NC No Connect.

Connection to end of resistor array for (the 256 Tap) DCP 2.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.

Connection to other end of resistor array for (the 256 Tap) DCP 2.

V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3
input is higher than the

V3 to V

when not used.

SS

V

TRIP3

threshold voltage, V3RO makes a transition to a HIGH level. Connect

V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than

V

and goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO

TRIP3

pin requires the use of an external “pull-up” resistor.

Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset
cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time t

returned to it’s normally LOW state. The reset time can be selected using bits POR1 and POR0 in the
CONSTAT Register. The MR pin requires the use of an external “pull-down” resistor.

Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the device DCP Write Lock feature is active (i.e. the DCP Write Lock bit is
“1”), then no “write” (volatile or nonvolatile) operations can be performedon the wiper position of any of
the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” re­sistor, thus if left floating the write protection feature is disabled.

Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.

Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up re­sistor.

Connection to other end of resistor for (the 100 Tap) DCP 1.

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.

Connection to end of resistor array for (the 100 Tap) DCP 1.

V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2
input is greater than the

V2 to V

when not used.

SS

V

threshold voltage, V2RO makes a transition to a HIGH level. Connect

TRIP2

V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than

V

, and goes LOW when V2 is less than V

TRIP2

pin. The V2RO pin requires the use of an external “pull-up” resistor.

V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active whenever

V

V1 / Vcc falls below
after the power supply stabilizes (t

. V1RO becomes active on power-up and remains active for a time t

TRIP1

can be changed by varying the POR0 and POR1 bits of the

purst

internal control register). The V1RO pin requires the use of an external “pull-up” resistor. The V1RO
pin can be forced active (HIGH) using the manual reset (MR) input pin.

after MR has

purst

. There is no power-up reset delay circuitry on this

TRIP2

purst

3

FN8209.1

January 3, 2006

SCL

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SDA

X9523

Data Stable Data Change Data Stable

Figure 1. Valid Data Changes on the SDA Bus

PRINCIPLES OF OPERATION

SERIAL INTERFACE

Serial Interface Conventions

The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera­tions. Therefore, the X9523 operates as a slave in all
applications.

Serial Clock and Data

Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1.On power-up of the X9523, the SDA pin is
in the input mode.

Serial Start Condition

All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.

Serial Stop Condition

All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.

Serial Acknowledge

An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The trans­mitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3.

The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subse­quent eight bit word.

In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will ter-

SCL

SDA

Start Stop

Figure 2. Valid Start and Stop Conditions

4

FN8209.1

January 3, 2006

SCL

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SCL

from

from

Master

Master

Data Output

from

Transmitter

Data Output

from

Receiver

X9523

81 9

Start Acknowledge

Figure 3. Acknowledge Response From Receiver

minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.

DEVICE INTERNAL ADDRESSING

Addressing Protocol Overview

The user addressable internal components of the X9523
can be split up into two main parts:

—Two Digitally Controlled Potentiometers (DCPs)

—Control and Status (CONSTAT) Register

Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte proto­col is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9523 to
be addressed, and specifies if a Read or Write opera­tion is to be performed.

It should be noted that in order to perform a write opera­tion to a DCP, the Write Enable Latch (WEL) bit must first
be set (See “WEL: Write Enable Latch (Volatile)” on
page 10.).

Slave Address Byte

—The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 111 internally
selects the DCP structures in the X9523. The CON­STAT Register may be selected using the Internal
Device Address 010.

—The Least Significant Bit of the Slave Address (SA0)

Byte is the R/W

bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W

bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)

Nonvolatile Write Acknowledge Polling

After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CON­STAT Register) has been correctly issued (including the

SA6SA7

SA5

1010

DEVICE TYPE

IDENTIFIER

SA4

SA3 SA2

INTERNAL

DEVICE

ADDRESS

SA1

SA0

R/W

READ /
WRITE

Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-

Internal Address

(SA3 - SA1)

sists of three parts:

—The Device Type Identifier which consists of the most

significant four bits of the Slave Address (SA7 - SA4).

All Others

The Device Type Identifier must always be set to 1010
in order to select the X9523.

Bit SA0 Operation

Figure 4. Slave Address Format

5

Internally Addressed

Device

010

111

0WRITE

1 READ

CONSTAT Register

DCP

RESERVED

January 3, 2006

FN8209.1

final STOP condition), the X9523 initiates an internal high

www.BDTIC.com/Intersil

voltage write cycle. This cycle typically requires 5 ms.
During this time, no further Read or Write commands can
be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.

To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no
ACKNOWLEDGE will be returned. If the device has
completed the write operation, an ACKNOWLEDGE will
be returned and the host can then proceed with a read or
write operation. (Refer to Figure 5.).

Byte load completed

by issuing STOP.

Enter ACK Polling

X9523

)

N

WIPER
COUNTER
REGISTER

(WCR)

NON

VOLATILE

MEMORY

(NVM)

DECODER

“WIPER”

FET

SWITCHES

2

1

0

Figure 6. DCP Internal Structure

RESISTOR

ARRAY

R

Hx

R

Lx

R

Wx

Issue START

Issue Slave Address
Byte (Read or Write)

ACK

returned?

YES

High Voltage Cycle

complete. Continue

command sequence?

YES

Continue normal

Read or Write

command sequence

PROCEED

Issue STOP

NO

NO

Issue STOP

Figure 5. Acknowledge Polling Sequence

DIGITALLY CONTROLLED POTENTIOMETERS

DCP Functionality

The X9523 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs - where x = 1,2).

At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper

) output. Within each individual array, only one

(R

x

w

switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.

On power-up of the X9523, wiper position data is auto­matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.

DCP Initial Values Before Recall

/ 100 TAP VL / TAP = 0

R

1

/ 256 TAP VH / TAP = 255

R

2

and R

Hx

Lx

6

FN8209.1

January 3, 2006

V1/Vcc

www.BDTIC.com/Intersil

X9523

V1/Vcc (Max.)

V

TRIP1

t

trans

0

The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.

t

purst

Figure 7. DCP Power-up

Hot Pluggability

Figure 7 shows a typical waveform that the X9523 might
experience in a Hot Pluggable situation. On power-up,
V1 / Vcc applied to the X9523 may exhibit some amount
of ringing, before it settles to the required value.

The device is designed such that the wiper terminal

) is recalled to the correct position (as per the last

(R

Wx

stored in the DCP NVM), when the voltage applied to
V1/Vcc exceeds V
Power-on Reset time, set in the CONSTAT Register ­See “CONTROL AND STATUS REGISTER” on
page 10.).

Therefore, if
Vcc to settle above V
wiper terminal position is recalled by (a maximum) time:

t

+ t

trans

by system hot plug conditions.

t

trans

. It should be noted that t

purst

for a time exceeding t

TRIP1

is defined as the time taken for V1 /

(Figure 7): then the desired

TRIP1

trans

is determined

purst

(the

DCP Operations

In total there are three operations that can be performed
on any internal DCP structure:

—DCP Nonvolatile Write

—DCP Volatile Write

—DCP Read

A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after V1/Vcc of
the X9523 is powered down and then powered back up.

t

Maximum Wiper Recall time

A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1/Vcc to the
device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.

Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)

A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).

Instruction Byte

While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.

The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0

- 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit of
the Instruction Byte (I7), determines the Write Type (WT)
performed.

If WT is “1”, then a Nonvolatile Write to the DCP
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated

occurs.

7

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

I5I6I7 I4 I3 I2 I1 I0

00WT 0 0 0 P1 P0

WRITE TYPE

†

WT

Select a Volatile Write operation to be performed

0

on the DCP pointed to by bits P1 and P0

Select a Nonvolatile Write operation to be per-

1

formed on the DCP pointed to by bits P1 and P0

†

This bit has no effect when a Read operation is being performed.

Description

DCP SELECT

Figure 8. Instruction Byte Format

WCR and NVM. Therefore, the new “wiper position” set­ting is recalled into the WCR after V1/Vcc of the X9523
has been powered down then powered back up.

If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There­fore, when V1/Vcc to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.

DCP Write Operation

A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.

In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg­ister must first be set (See “WEL: Write Enable Latch
(Volatile)” on page 10.).

The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9523 after the Slave Address, if it has
been received correctly.

Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9523.

Following the Instruction Byte, a Data Byte is issued to
the X9523 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 29).

The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).

P1- P0 DCPx # Taps Max. Data Byte

0 0 RESERVED

0 1 x = 1 100 Refer to Appendix 1

1 0 x = 2 256 FFh

1 1 RESERVED

Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.

For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There­fore, the Data Byte 00001111 (15

) corresponds to set-

10

ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28

) corresponds to setting the

10

“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1”. An example of a simple C lan­guage function which “translates” between the tap posi­tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2”.

10101110

S
T
A
R
T

SLAVE ADDRESS BYTE

A

WT 0 0 0 0 0 P1 P0 A
C
K

INSTRUCTION BYTE

C
K

Figure 9. DCP Write Command Sequence

8

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

S

A

T

C

O

K

P

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

S

WRITE Operation

Signals from
the Master

t

a

r

Slave

Address

Instruction

Byte

t

SDA Bus

Signals from
the Slave

101 11100

“Dummy” write

W

00 000

T

A
C
K

Figure 10. DCP Read Sequence

It should be noted that all writes to any DCP of the
X9523 are random in nature. Therefore, the Data
Byte of consecutive write operations to any DCP can
differ by an arbitrary number of bits. Also, setting the
bits P1 = 1, P0 = 1 is a reserved sequence, and will
result in no ACKNOWLEDGE after sending an
Instruction Byte on SDA.

The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-

R

sponds to having the “wiper teminal”

(x = 1,2) at the

WX

“lowest” tap position, Therefore, the resistance between

R

and RLX is a minimum (essentially only the Wiper

WX

Resistance,

R

).

W

DCP Read Operation

A read of DCPx (x = 1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.

S

READ Operation

t

Slave

a

r

Address

Data Byte

t

P

P
1

101 11110

0

A
C
K

A
C
K

MSB

S

t
o
p

-

“-” = DON’T CARE

LSB

DCPx

x = 1

x = 2

The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9523 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9523.

Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W

bit set to 1. Then the X9523
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.

S

Signals from

the Master

SDA Bus

Signals from

the Slave

t

a

r
t

1

Address

01

WRITE Operation

Slave

0

0

0

0

Internal
Device

Address

Address

Byte

0

A
C
K

A
C
K

Figure 11. EEPROM Byte Write Sequence

9

Data

Byte

S

t
o
p

A
C
K

FN8209.1

January 3, 2006

CS6CS7 CS4

www.BDTIC.com/Intersil

CS5

POR1

NV

Bit(s) Description

POR1 Power-on Reset bit

V2OS V2 Output Status flag

V1OS V1 Output Status flag

CS4 Always set to “0” (RESERVED)

DWLK Sets the DCP Write Lock

RWEL Register Write Enable Latch bit

WEL Write Enable Latch bit

POR0 Power-on Reset bit

NOTE: Bits labelled NV ar e no nv olat ile (Se e “CONTRO L A ND STATUS REGISTER”).

V2OS

V3OS

CS3

CS2 CS1 CS0

0

DWLK

RWEL

WEL

POR0

NV

NV

Figure 12. CONSTAT Register Format

It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).

CONTROL AND STATUS REGISTER

The Control and Status (CONSTAT) Register pro­vides the user with a mechanism for changing and
reading the status of various parameters of the
X9523 (See Figure 12).

The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON­STAT register retain their stored values even when
V1/Vcc is powered down, then powered back up. The
volatile bits however, will always power-up to a known
logic state “0” (irrespective of their value at power-down).

X9523

The WEL bit is a volatile latch that powers up in the dis­abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT regis­ter) or until the X9523 powers down, and then up again.

Writes to the WEL bit do not cause an internal high volt­age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 13).

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9523. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.

It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").

The RWEL bit will reset itself to the default “0” state, in
one of two cases:

—After a successful write operation to any bits of

the CONSTAT register has been completed (See
Figure 13).

—When the X9523 is powered down.

DWLK: DCP Write Lock bit - (Nonvolatile)

The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).

When the DCP Write Lock bit of the CONSTAT register
is set to “1”, then the “wiper position” of the DCPs can­not be changed - i.e. DCP write operations cannot be
conducted:

A detailed description of the function of each of the CON­STAT register bits follows:

WEL: Write Enable Latch (Volatile)

The WEL bit controls the Write Enable status of the
entire X9523 device. This bit must first be enabled before
ANY write operation (to DCPs, or the CONSTAT regis­ter). If the WEL bit is not first enabled, then ANY pro­ceeding (volatile or nonvolatile) write operation to DCPs
or the CONSTAT register, is aborted and no ACKNOWL-

DWLK DCP Write Operation Permissible

0 YES (Default)

1NO

The factory default setting for this bit is DWLK = 0.

IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9523 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").

EDGE is issued after a Data Byte.

10

FN8209.1

January 3, 2006

SCL

www.BDTIC.com/Intersil

SDA

X9523

S

1 010010R/W
T
A
R

T

SLAVE ADDRESS BYTE

A

11111111 A
C
K

ADDRESS BYTE

Figure 13. CONSTAT Register Write Command Sequence

POR1, POR0: Power-on Reset bits - (Nonvolatile)

Applying voltage to V

activates the Power-on Reset

CC

circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the V
period of time, t

(See Figure 25).

PURST

threshold for a

TRIP1

The Power-on Reset bits, POR1 and POR0 of the
CONSTAT register determine the tPURST delay time of
the Power-on Reset circuitry (See "VOLTAGE MONI­TORING FUNCTIONS"). These bits of the CONSTAT
register are nonvolatile, and therefore power-up to the
last written state.

The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:

POR1 POR0

0 0 50ms

0 1 100ms (Default)

1 0 200ms

1 1 300ms

Power-on Reset delay (t

PUV1RO

)

The default for these bits are POR1 = 0, POR0 = 1.

V2OS, V3OS: Voltage Monitor Status Bits (Volatile)

Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.

At power-up the VxOS (x = 2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropri­ate value to the CONSTAT register. To provide consis­tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corre­sponding VxRO output is HIGH.

CS7 CS6
C
K

CONSTAT REGISTER DATA IN

CS5 CS4 CS3

CS2 CS1

CS0

S

A

T

C

O

K

P

Once the VxOS bits have been set to “1”, they will be
reset to “0” if:

—The device is powered down, then back up,

—The corresponding VxRO output becomes LOW.

CONSTAT Register Write Operation

The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis­ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK, POR1 and
POR0 bits. The X9523 will not ACKNOWLEDGE any
data bytes written after the first byte is entered (Refer to
Figure 13.).

When writing to the CONSTAT register, the bit CS4 must
always be set to “0”. Writing a “1” to bit CS4 of the CON­STAT register is a reserved operation.

Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps

—Write a 02H to the CONSTAT Register to set the Write

Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).

—Write a 06H to the CONSTAT Register to set the Reg-

ister Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).

11

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

S

WRITE Operation

Signals from
the Master

t

a

r

Slave

Address

Address

Byte

t

SDA Bus

0 1 0 0 1 011 0 1 0 0 1 0

0

A

Signals from
the Slave

C

K

“Dummy” Write

Figure 14. CONSTAT Register Read Command Sequence

—Write a one byte value to the CONSTAT Register that

has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, t is the DCP Write Lock
(DWLK) bit, and qr are the Power-on Reset delay time
(t

PUV1RO

) control bits (POR1 - POR0). This operation
is proceeded by a START and ended with a STOP bit.
Since this is a nonvolatile write cycle, it will typically
take 5ms to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this third
step (qxys t11r) then the RWEL bit is set, but the
V2OS, V3OS, POR1, POR0, and DWLK bits remain
unchanged. Writing a second byte to the control regis­ter is not allowed. Doing so aborts the write operation
and the X9523 does not return an ACKNOWLEDGE.

For example, a sequence of writes to the device CON­STAT register consisting of [02H, 06H, 02H] will reset all
of the nonvolatile bits in the CONSTAT Register to “0”.

It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect
pin of the X9523 is active (HIGH) (See "WP: Write
Protection Pin").

A
C
K

S

READ Operation

t

a

r
t

Slave

Address

S

t
o
p

CS7 … CS0

1

A

C

Data

K

CONSTAT Register Read Operation

The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 14).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each reg­ister read operation. The X9523 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.

After setting the WEL and / or the RWEL bit(s) to a “1”,
a CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write
operation.

When performing a read operation on the CONSTAT
registerm, bit CS4 will always return a “0” value.

DATA PROTECTION

There are a number of levels of data protection fea­tures designed into the X9523. Any write to the device
first requires setting of the WEL bit in the CONSTAT
register. A write to the CONSTAT register itself, further
requires the setting of the RWEL bit. DCP Write Lock
protection of the device enables the user to inhibit
writes to all the DCPs. One further level of data protec­tion in the X9523, is incorporated in the form of the
Write Protection pin.

X9523 Write Permission Status

DWLK

(DCP Write Lock

bit status)

1 1 NO NO NO NO

01YESNONONO

1

0

WP

(Write Protect pin

status)

0

0

12

DCP Volatile Write

Permitted

NO NO YES YES

YES YES YES YES

DCP Nonvolatile

Write Permitted

Write to CONSTAT Register

Volatile Bits Nonvolatile Bits

Permitted

FN8209.1

January 3, 2006

WP: Write Protection Pin

www.BDTIC.com/Intersil

When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9523.

The table (X9523 Write Permission Status) summarizes
the effect of the WP pin (and DCP Write Lock), on the
write permission status of the device.

X9523

Vx

VxRO

V

TRIPx

0V

0V

Additional Data Protection Features

In addition to the preceding features, the X9523 also
incorporates the following data protection functionality:

—The proper clock count and data bit sequence is

required prior to the STOP bit in order to start a nonvol­atile write cycle.

VOLTAGE MONITORING FUNCTIONS

V1 / Vcc Monitoring

The X9523 monitors the supply voltage and drives the
V1RO output HIGH (using an external “pull up” resistor)
if V1/Vcc is lower than V
output will remain HIGH until V1/Vcc exceeds V
for a minimum time of t
V1RO pin is driven to a LOW state. See Figure 25.

For the Power-on/Low Voltage Reset function of the
X9523, the V1RO output may be driven HIGH down to a
V1/Vcc of 1V (V

). See Figure 25. Another feature

RVALID

of the X9523, is that the value of t
in software via the CONSTAT register (See “POR1,
POR0: Power-on Reset bits - (Nonvolatile)” on page 11.).

threshold. The V1RO

TRIP1

. After this time, the

PURST

may be selected

PURST

TRIP1

V1 / Vcc

V

TRIP1

0 Volts

(x = 2,3)

Figure 16. Voltage Monitor Response

It is recommended to stop communication to the device
while while V1RO is HIGH. Also, setting the Manual
Reset (MR) pin HIGH overrides the Power-on/Low
Voltage circuitry and forces the V1RO output pin HIGH
(See "Manual Reset").

Manual Reset

The V1RO output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connect­ing a push-button directly from V1/Vcc to the MR pin.

V1RO remains HIGH for time t

after MR has

PURST

returned to its LOW state (See Figure 15). An external
“pull down” resistor is required to hold this pin (nor­mally) LOW.

V1 / Vcc

0 Volts

MR

V1RO

0 Volts

0 Volts

Figure 15. Manual Reset Response

13

t

PURST

V

TRIP1

V2 monitoring

The X9523 asserts the V2RO output HIGH if the volt­age V2 exceeds the corresponding V

TRIP2

threshold
(See Figure 16). The bit V2OS in the CONSTAT regis­ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).

The V2RO output may remain active HIGH with V

CC

down to 1V.

V3 monitoring

The X9523 asserts the V3RO output HIGH if the volt­age V3 exceeds the corresponding V
(See Figure 16). The bit V3OS in the CONSTAT regis­ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).

The V3RO output may remain active HIGH with V
down to 1V.

TRIP3

threshold

CC

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

V1 / Vcc

V2, V3

V

TRIPx

WP

V

TRIPX

01234567

SCL

SDA

S
T
A
R

T

A0h

Figure 17. Setting V

THRESHOLDS (X = 1,2,3)

†

01234567

01h† sets V

09h† sets V

0Dh† sets V

TRIPx

The X9523 is shipped with pre-programmed threshold
(V

) voltages. In applications where the required

TRIPx

thresholds are different from the default values, or if a
higher precision/tolerance is required, the X9523 trip
points may be adjusted by the user, using the steps
detailed below.

Setting a V

Voltage (x = 1,2,3)

TRIPx

There are two procedures used to set the threshold
voltages (V

), depending if the threshold voltage

TRIPx

to be stored is higher or lower than the present value.
For example, if the present V
new V
directly into the V

is 3.2 V, the new voltage can be stored

TRIPx

cell. If however, the new setting

TRIPx

is 2.9 V and the

TRIPx

is to be lower than the present setting, then it is neces­sary to “reset” the V

voltage before setting the

TRIPx

new value.

V

P

01234567

00h

TRIP1

TRIP2

TRIP3

Data Byte

to a higher level (x = 1,2,3).

Setting a Higher V

To set a V
higher than the present threshold, the user must apply
the desired V
sponding input pin (V1/Vcc, V2 or V3). Then, a pro­gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by
the Byte Address 01h for V
0Dh for V
gram V

TRIP3

TRIPx

operation initiates the programming sequence. Pin WP
must then be brought LOW to complete the operation
(See Figure 18). The user does not have to set the
WEL bit in the CONSTAT register before performing
this write sequence.

threshold to a new voltage which is

TRIPx

threshold voltage to the corre-

TRIPx

, and a 00h Data Byte in order to pro-

. The STOP bit following a valid write

†

†

All others Reserved.

Voltage (x = 1,2,3)

TRIPx

, 09h for V

TRIP1

TRIP2

, and

V

P

WP

01234567

00h

Data Byte

Level

SCL

SDA

01234567

†

S
T
A
R

T

A0h

14

01234567

03h† Resets

0Bh† Resets

0Fh† Resets

VTRIP1

VTRIP2

VTRIP3

Figure 18. Resetting the V

TRIPx

†

†

All others Reserved.

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

Setting a Lower V

In order to set V
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V

Voltage (x = 1,2,3).

TRIPx

to a lower voltage than the

TRIPx

must first be “reset” accord-

TRIPx

can be set to the desired

TRIPx

TRIPx

voltage using the procedure described in “Setting a
Higher V

Resetting the V

To reset a V

TRIPx

Voltage”.

Voltage (x = 1,2,3).

TRIPx

voltage, apply the programming volt-

TRIPx

age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for

, 0Bh for V

V

TRIP1

by 00h for the Data Byte in order to reset V

, and 0Fh for V

TRIP2

TRIP3

, followed

. The

TRIPx

STOP bit following a valid write operation initiates the
programming sequence. Pin WP must then be brought
LOW to complete the operation (See Figure 18).The
user does not have to set the WEL bit in the CON­STAT register before performing this write sequence.

After being reset, the value of V

becomes a nomi-

TRIPx

nal value of 1.7V.

V

The accuracy with which the V

Accuracy (x = 1,2,3).

TRIPx

thresholds are set,

TRIPx

can be controlled using the iterative process shown in
Figure 19.

If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage (x = 1,2,3)." ) .

The desired threshold voltage is then applied to the
appropriate input pin (V1/Vcc, V2 or V3) and the proce­dure described in Section “Setting a Higher V

TRIPx

Voltage“ must be followed.

Once the desired V

threshold has been set, the

TRIPx

error between the desired and (new) actual set threshold
can be determined. This is achieved by applying V1/Vcc
to the device, and then applying a test voltage higher
than the desired threshold voltage, to the input pin of the
voltage monitor circuit whose V
For example, if V

was set to a desired level of 3.0V,

TRIP2

was programmed.

TRIPx

then a test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In the case of setting of V

TRIP1

then
only V1/Vcc need be applied. In all cases, care should be
taken not to exceed the maximum input voltage limits.

After applying the test voltage to the voltage monitor
input pin, the test voltage can be decreased (either in dis­crete steps, or continuously) until the output of the volt­age monitor circuit changes state. At this point, the error
between the actua measured, and desired threshold lev­els is calculated.

For example, the desired threshold for V

TRIP2

is set to

3.0V, and a test voltage of 3.4V was applied to the input
pin V2 (after applying power to V1/Vcc). The input volt­age is decreased, and found to trip the associated output
level of pin V2RO from a LOW to a HIGH, when V2
reaches 3.09V. From this, it can be calculated that the
programming error is 3.09 - 3.0 = 0.09V.

If the error between the desired and measured V

TRIPx

less than the maximum desired error, then the program­ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
iteration of the V

programming sequence can be

TRIPx

performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.

If the calculated error is greater than zero, then the
V
a value equal to the previously set V

must first be “reset”, and then programmed to the

TRIPx

minus the cal-

TRIPx

culated error. If it is the case that the error is less than
zero, then the V
equal to the previously set V

must be programmed to a value

TRIPx

plus the absolute value

TRIPx

of the calculated error.

Continuing the previous example, we see that the calcu­lated error was 0.09V. Since this is greater than zero, we
must first “reset” the V

threshold, then apply a volt-

TRIP2

age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
must apply V

= 2.91 V to pin V2 and execute the

TRIP2

programming sequence (See "Setting a Higher VTRIPx
Voltage (x = 1,2,3)" ) .

Using this process, the desired accuracy for a particu­lar V

threshold may be attained using a succes-

TRIPx

sive number of iterations.

is

15

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

New Vx applied =

Old Vx applied

+ | Error |

V

NO

Set Vx = desired

Apply Vcc & Voltage

> Desired V

NO

Programming

TRIPx

Desired V

present value?

Execute

V

TRIPx

Sequence

Execute

Set Higher

Sequence

Decrease Vx

Output

switches?

TRIPx

YES

Reset

V

TRIPx

<

V

TRIPx

to Vx

TRIPx

Note: X = 1,2,3.

Let: MDE = Maximum Desired Error

Desired Value

New Vx applied =

Old Vx applied

Execute

V

Reset

Sequence

+

MDE

–

MDE

Error = Actual – Desired

- | Error |

TRIPx

Acceptable

Error Range

Error < MDE

Figure 19. V

YES

–

Actual V

- Desired V

= Error

TRIPx

TRIPx

Error >MDE

| Error | < | MDE |

DONE

Setting / Reset Sequence (x = 1,2,3)

TRIPx

+

16

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Parameter Min. Max. Units

Temperature under Bias -65 +135 C
Storage Temperature -65 +150 C
Voltage on WP pin (With respect to Vss) -1.0 +15 V
Voltage on other pins (With respect to Vss) -1.0 +7 V

| Voltage on R

- Voltage on R

Hx

D.C. Output Current (SDA,V1RO,V2RO,V3RO)

| (x = 0,1,2. Referenced to Vss)

Lx

0

Lead Temperature (Soldering, 10 seconds) 300 C
Supply Voltage Limits (Applied V1/Vcc voltage, referenced to Vss) 2.7 5.5 V

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max. Units

Industrial -40 +85

NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended peri­ods may affect device reliability

V1/Vcc V

5mA

C

Figure 20. Equivalent A.C. Circuit

Figure 21. DCP SPICE Macromodel

SDA

V2RO
V3RO
V1RO

R

Hx

10pF

V1 / Vcc = 5V

R

TOTAL

C

H

R

Wx

100pF

R

W

C

25pF

2300Ω

W

C

10pF

L

R

Lx

(x=0,1,2)

17

FN8209.1

January 3, 2006

TIMING DIAGRAMS

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Figure 22. Bus Timing

X9523

SCL

t

SU:STA

SDA IN

t

HD:STA

SDA OUT

Figure 23. WP Pin Timing

START

SCL

SDA IN

WP

t

F

t

SU:DAT

t

SU:WP

t

HIGH

t

LOW

t

HD:DAT

t

R

t

AA

Clk 1 Clk 9

t

HD:WP

t

DH

t

BUF

t

SU:STO

Figure 24. Write Cycle Timing

SCL

SDA

8th bit of last byte ACK

Stop

Condition

t

WC

Start

Condition

18

FN8209.1

January 3, 2006

Figure 25. Power-Up and Power-Down Timing

www.BDTIC.com/Intersil

X9523

t

R

V1/Vcc

0 Volts

t

PURST

V1RO

0 Volts

MR

Figure 26. Manual Reset Timing Diagram

0 Volts

MR

0 Volts

t

V1RO

0 Volts

MRD

t

RPD

t

MRPW

t

PURST

t

F

t

PURST

V

TRIP1

V1 / Vcc

Figure 27. V2, V3 Timing Diagram

t

Rx

Vx

t

RPDx

VxRO

V1/Vcc

Note : x = 2,3.

t

RPDx

t

RPDx

t

V

RVALID

Fx

t

RPDx

V

TRIPx

V1/Vcc

V

TRIP1

0 Volts

0 Volts

V

TRIP1

0 Volts

19

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

Figure 28. V

V Vcc, V2, V3

t

TSU

V

P

WP

SCL

SDA

Programming Timing Diagram (x = 1,2,3).

TRIPX

t

VPS

NOTE : V1/Vcc must be greater than V2, V3 when programming.

Figure 29. DCP “Wiper Position” Timing

Rwx (x = 0,1,2)

V

TRIPx

00h

t

THD

t

VPO

t

wc

t

VPH

SCL

SDA

R

wx(n)

n = tap position

10101110

S
T
A
R

T

SLAVE ADDRESS BYTE

t

wr

A

WT 0 0 0 0 0 P1 P0 A
C
K

INSTRUCTION BYTE

R

wx(n + 1)

R

wx(n - 1)

D7 D6 D5 D4 D3 D2 D1 D0

C
K

DATA BYTE

Time

S

A

T

C

O

K

P

20

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS

Symbol Parameter Min Typ Max Unit Test Conditions / Notes

Current into VCC Pin

(1)

I

CC1

(2)

I

CC2

I

LI

I

ai

I

LO

V

TRIP1PR

V

TRIPxPR

V

TRIP1

V

TRIP2

V

TRIP3

I

Vx

(7)

VIL

(7)

V

IH

V

OLx

(6)

(6)

(6)

Write nonvolatile memory

Current into VCC Pin

With 2-Wire bus activity

Input Leakage Current (SCL, SDA, MR) 0.1 10 μA

Input Leakage Current (WP) 10 μA

Analog Input Leakage 1 10 µA

Output Leakage Current (SDA, V1RO,
V2RO, V3RO)

V

Programming Range

TRIP1

V

Programming Range (x = 2,3)

TRIPx

Pre - programmed V

Pre - programmed V

Pre - programmed V

V2 Input leakage current
V3 Input leakage current

Input LOW Voltage (SCL, SDA, WP, MR) -0.5 0.8 V

Input HIGH Voltage (SCL,SDA, WP, MR) 2.0

V1RO, V2RO, V3RO, SDA Output Low
Voltage

(X9523: Active)

Read memory array

(X9523:Standby)

No 2-Wire bus activity

threshold

TRIP1

threshold

TRIP2

threshold

TRIP3

(3)

(3)

0.1 10 μA

2.75 4.70 V

1.8 4.70 V

2.85

4.55

1.65

2.85

1.65

2.85

3.0

4.7

1.8

3.0

1.8

3.0

0.4

1.5

50
50

3.05

4.75

1.85

3.05

1.85

3.05

1
1

V

CC

+0.5

0.4 V

= 400kHz

f

mA

SCL

V

SDA

= V

CC

MR = Vss
WP = Vss or Open/Floating

μA

V

= V

SCL

else f

V

IN

= VSS to VCC with all other an-

V

IN

(when no bus activity

CC

= 400kHz)

SCL

(4)

= GND to V

alog pins floating

(5)

V

OUT

= GND to V

X9523 is in Standby

Factory shipped default option A

V

Factory shipped default option B

Factory shipped default option A

V

Factory shipped default option B

Factory shipped default option A

V

Factory shipped default option B

= V

V

μA

SDA

Others=GND or V

SCL

= VCC

V

= 2.0mA

I

SINK

CC.

CC

CC.
(2)

Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200nS after a STOP ending a read operation; or t

Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that initiates a

high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.

Notes: 3. Current through external pull up resistor not included.

V

Notes: 4.

Notes: 5.

Notes: 6. See Ordering Information on page 2.

Notes: 7. V

= Voltage applied to input pin.

IN

V

= Voltage applied to output pin.

OUT

Min. and VIH Max. are for reference only and are not tested

IL

after a STOP ending a write operation.

WC

21

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)

Symbol Parameter

f

SCL

(5)

t

IN

(5)

t

AA

(5)

t

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

(5)

t

DH

(5)

t

R

(5)

t

F

t

SU:WP

t

HD:WP

(5)

Cb

SCL Clock Frequency 0 400 kHz

Pulse width Suppression Time at inputs 50 ns

SCL LOW to SDA Data Out Valid 0.1 0.9 μs

Time the bus free before start of new transmission 1.3 μs

Clock LOW Time 1.3 μs

Clock HIGH Time 0.6 μs

Start Condition Setup Time 0.6 μs

Start Condition Hold Time 0.6 μs

Data In Setup Time 100 ns

Data In Hold Time 0 μs

Stop Condition Setup Time 0.6 μs

Data Output Hold Time 50 ns

SDA and SCL Rise Time

SDA and SCL Fall Time

WP Setup Time 0.6 μs

WP Hold Time 0 μs

Capacitive load for each bus line 400 pF

400kHz

Min Max Units

20 +.1Cb

20 +.1Cb

(2)

(2)

300 ns

300 ns

A.C. TEST CONDITIONS

to 0.9V

Input Pulse Levels

0.1V

CC

CC

Input Rise and Fall Times 10ns

Input and Output Timing Levels

0.5V

CC

Output Load See Figure 20

NONVOLATILE WRITE CYCLE TIMING

Symbol Parameter Min. Typ.(1) Max. Units

(4)

t

WC

CAPACITANCE (T

Symbol Parameter Max Units Test Conditions

(5)

C

OUT

(5)

C

IN

Notes: 1. Typical values are for TA = 25°C and VCC = 5.0V
Notes: 2. Cb = total capacitance of one bus line in pF.

Notes: 3. Over recommended operating conditions, unless otherwise specified

Notes: 4. t

Notes: 5. This parameter is not 100% tested.

is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

WC

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Nonvolatile Write Cycle Time 5 10 ms

= 25°C, F = 1.0 MHZ, VCC = 5V)

A

Output Capacitance (SDA, V1RO, V2RO, V3RO) 8 pF

Input Capacitance (SCL, WP, MR) 6 pF

V

OUT

V

IN

= 0V

= 0V

22

FN8209.1

January 3, 2006

POTENTIOMETER CHARACTERISTICS

www.BDTIC.com/Intersil

Symbol Parameter

R

TOL

V

RHx

V

RLx

P

R

R

W

I

W

C

H/CL/CW

End to End Resistance Tolerance -20 +20 %

RH Terminal Voltage (x = 0,1,2)

RL Terminal Voltage (x = 0,1,2)

Power Rating

(1)(6)

DCP Wiper Resistance

Wiper Current

(6)

Noise

Absolute Linearity

Relative Linearity

R

Temperature Coefficient

TOTAL

(2)

(3)

Potentiometer Capacitances

X9523

Limits

Vss

Vss

200 400 Ω

400 1200 Ω

-1 +1

-1 +1

±300 ppm/C

±300 ppm/C

10/10/25

V

V

CC

CC

V

V

10 mW

5mW

4.4 mA

mV/

sqt(Hz)

mV/

sqt(Hz)

(4)

MI

(4)

MI

pF

Test Conditions/NotesMin. Typ. Max. Units

R

R

= 10kΩ (DCP0, DCP1)

TOTAL

= 100kΩ (DCP2)

TOTAL

IW = 1mA, VCC = 5V, V
V

= Vss (x = 0,1,2).

RLx

I

= 1mA, V

W

V

RHx

= Vcc, V

CC

RLx

= 2.7V,

= Vss

(x = 0,1,2)

R

R

R

R

R

R

= 10kΩ (DCP0, DCP1)

TOTAL

= 100kΩ (DCP2)

TOTAL

w(n)(actual)

w(n + 1)

TOTAL

TOTAL

- R

w(n)(expected)

- [R

w(n) + MI

= 10kΩ (DCP0, DCP1)

= 100kΩ (DCP2)

]

See Figure 21.

RHx

= Vcc,

t

wr

Notes: 1. Power Rating between the wiper terminal R

Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R

Notes: 3. Relative Linearity is a measure of the error in step size between taps = R

Notes: 4. 1 Ml = Minimum Increment = R

Notes: 5. Typical values are for T

Notes: 6. This parameter is periodically sampled and not 100% tested.

Wiper Response time

Ml Maximum (x = 0,1,2).

A

(6)

and the end terminals RHX or RLX - for ANY tap position n, (x = 0,1,2).

WX(n)

/ (Number of taps in DCP - 1).

TOT

= 25C and nominal supply voltage.

200 μs See Figure 29.

Wx(n+1)

- [R

+ Ml] = ±1 Ml (x = 0,1,2)

wx(n)

(actual) - R

wx(n)

(expected)) = ±1

wx(n)

23

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

V

(X = 1,2,3) PROGRAMMING PARAMETERS (See Figure 28)

TRIPX

Parameter Description Min Typ Max Units

V

t

VPS

t

VPH

t

TSU

t

THD

t

VPO

t

wc

V

P

V

ta

V

tv

Notes: The above parameters are not 100% tested.

Program Enable Voltage Setup time

TRIPx

V

Program Enable Voltage Hold time

TRIPx

V

Setup time

TRIPx

V

Hold (stable) time

TRIPx

V

Program Enable Voltage Off time

TRIPx

(Between successive adjustments)

V

Write Cycle time

TRIPx

10 μs

10 μs

10 μs

10 μs

1ms

510 ms

Programming Voltage 10 15 V

V

Program Voltage accuracy

TRIPx

(Programmed at 25

V

Program variation after programming (-40 - 85oC).

TRIP

o

C.)

(Programmed at 25oC.)

-100 +100 mV

-25 +10 +25 mV

V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 25, Figure 26, Figure 27)

Symbol Description Condition Min. Typ. Max. Units

POR1 = 0, POR0 = 0 25 50 75 ms

t

PURST

t

MRD

t

MRDPW

t

RPDx

(5)

t

Fx

(5)

t

Rx

V

RVALID

(5)

(26)(2)(5)

(5)

(5)

(5)

Power-on Reset delay time

MR to V1RO propagation delay

MR pulse width 500 ns

V Vcc, V2, V3 to V1RO, V2RO,
V3RO propagation
delay (respectively)

V1/Vcc, V2, V3 Fall Time 20 mV/μs

V1/Vcc, V2, V3 Rise Time 20 mV/μs

V1/Vcc for V1RO, V2RO, V3RO

(3)

Valid

.

POR1 = 0, POR0 = 1 50 100 150 ms

POR1 = 1, POR0 = 0 100 200 300 ms

POR1 = 1, POR0 = 1 150 300 450 ms

See

(1)(2)(4)

5 μs

20 μs

1V

Notes: 1. See Figure 26 for timing diagram.

Notes: 2. See Figure 20 for equivalent load.

Notes: 3. This parameter describes the lowest possible V1/Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to

their inputs (V1/Vcc, V2, V3).

Notes: 4. From MR rising edge crossing V

Notes: 5. The above parameters are not 100% tested.

, to V1RO rising edge crossing VOH.

IH

24

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

APPENDIX 1

DCP1 (100 Tap) Tap position to Data Byte translation Table

Tap

Position

0 0 0000 0000

1 1 0000 0001

.
.

23 23 0001 0111

24 24 0001 1000

25 56 0011 1000

26 55 0011 0111

.
.

48 33 0010 0001

49 32 0010 0000

50 64 0100 0000

51 65 0100 0001

.
.

73 87 0101 0111

74 88 0101 1000

75 120 0111 1000

76 119 0111 0111

.
.

98 97 0110 0001

99 96 0110 0000

Decimal Binary

.
.

.
.

.
.

.
.

Data Byte

.
.

.
.

.
.

.
.

25

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

APPENDIX 2

DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)

unsigned DCP1_TAP_Position(int tap_pos)
{

int block;
int i;
int offset;
int wcr_val;

offset= 0;
block = tap_pos / 25;

if (block < 0) return ((unsigned)0);

else if (block <= 3)
{ switch(block)

{ case (0): return ((unsigned)tap_pos) ;

}

case (1):
{

wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);

}

case (2):
{

wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);

}

case (3):
{

wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);

}

}
}
return((unsigned)01100000);

26

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

APPENDIX 2

DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)

unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0); /* set to min val */
else if (tap_pos >99) return ((unsigned) 96); /* set to max val */

/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}

27

FN8209.1

January 3, 2006

X9523

www.BDTIC.com/Intersil

20-LEAD PLASTIC, TSSOP PACKAGE TYPE V

.025 (.65) BSC

0° - 8°

.0075 (.19)
.0118 (.30)

.252 (6.4)
.260 (6.6)

.019 (.50)
.029 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

(1.78)

(0.42)

(0.65)

(4.16)

(7.72)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

28

ALL MEASUREMENTS ARE TYPICAL

FN8209.1

January 3, 2006