intersil X9523 DATA SHEET
®
www.BDTIC.com/Intersil
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Data Sheet January 3, 2006
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Laser Diode Control for Fiber Optic Modules
X9523
FN8209.1
Dual DCP, POR, Dual Voltage Monitors
FEATURES
• Two Digitally Controlled Potentiometers (DCPs)
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Nonvolatile
—Write Protect Function
• 2-Wire Industry Standard Serial Interface
• Power-On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset
• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Pin Package
—TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9523 combines two Digitally Controlled Potentiometers (DCPs), V1 / Vcc Power-on Reset (POR) circuitry, qnd two programmable voltage monitor inputs
with software and hardware indicators. All functions of
the X9523 are accessed by an industry standard 2-Wire
serial interface.
The DCPs of the X9523 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The programmable POR circuit may be
used to ensure that V1 / Vcc is stable before power is
applied to the laser diode / module. The programmable
voltage monitors may be used for monitoring various
module alarm levels.
The features of the X9523 are ideally suited to simplifying the design of fiber optic modules . The integration of these functions into one package significantly
reduces board area, cost and increases reliability of
laser diode modules.
BLOCK DIAGRAM
WP
SDA
SCL
MR
V3
V2
V1 / Vcc
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
VTRIP
VTRIP
VTRIP
R
WIPER
COUNTER
PROTECT LOGIC
8
CONSTAT
REGISTER
2
-
+
3
-
+
2
POWER-ON /
+
-
1
LOW VOLTAGE
RESET
GENERATION
REGISTER
7 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
R
R
R
R
R
V3RO
V2RO
V1RO
H1
W1
L1
H2
W2
L2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9523
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Ordering Information
PART
NUMBER
X9523V20I-A X9523VIA -40 to +85 20 Ld TSSOP
X9523V20I-B X9523VIB -40 to +85 20 Ld TSSOP
X9523V20IZ-A
(Note)
X9523V20IZ-B
(Note)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
DETAILED DEVICE DESCRIPTION
The X9523 combines two Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/Vcc power-on reset
control, V1/Vcc low voltage reset control, and two supplementary voltage monitors in one package. These
functions are suited to the control, support, and monitoring of various system parameters in fiber optic modules.
The combination of the X9523 functionality lowers system cost, increases reliability, and reduces board space
requirements.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.
Applying voltage to V
circuit which allows the V1RO output to go HIGH, until
the supply the supply voltage stabilizes for a period of
time (selectable via software). The V1RO output then
goes LOW. The Low Voltage Reset circuitry allows the
V1RO output to go HIGH when V
mum V
trip point. V1RO remains HIGH until V
CC
returns to proper operating level. A Manual Reset (MR)
input allows the user to externally trigger the V1RO output (HIGH).
PART
MARKING
X9523VZIA -40 to +85 20 Ld TSSOP
X9523VZIB -40 to +85 20 Ld TSSOP
TEMP RANGE
(°C) PACKAGE
(Pb-free)
(Pb-free)
activates the Power-on Reset
CC
falls below the mini-
CC
CC
PIN CONFIGURATION
20 Pin TSSOP
R
H2
R
W2 2
R
V3
V3RO
MR
WP
SCL
SDA
V
SS
1
3
L2
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V1 / Vcc
V1RO
V2RO
V2
NC
NC
NC
R
H1
R
W1
R
L1
NOT TO SCALE
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port.
Intersil’s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in
changing system parameters, either at the time of
manufacture, or in the field.
The device features a 2-Wire interface and software
2
protocol allowing operation on an I
C™ compatible
serial bus.
2
FN8209.1
January 3, 2006
X9523
www.BDTIC.com/Intersil
PIN ASSIGNMENT
Pin Name Function
1
2
3
R
H2
R
w2
R
L2
4V3
5V3RO
6MR
7WP
8SCL
9SDA
10 Vss Ground.
11
12
13
R
L1
R
w1
R
H1
17 V2
18 V2RO
19 V1RO
20 V1 / Vcc Supply Voltage.
14, 15,
16,
NC No Connect.
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3
input is higher than the
V3 to V
when not used.
SS
V
TRIP3
threshold voltage, V3RO makes a transition to a HIGH level. Connect
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than
V
and goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO
TRIP3
pin requires the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset
cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time t
returned to it’s normally LOW state. The reset time can be selected using bits POR1 and POR0 in the
CONSTAT Register. The MR pin requires the use of an external “pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the device DCP Write Lock feature is active (i.e. the DCP Write Lock bit is
“1”), then no “write” (volatile or nonvolatile) operations can be performedon the wiper position of any of
the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2
input is greater than the
V2 to V
when not used.
SS
V
threshold voltage, V2RO makes a transition to a HIGH level. Connect
TRIP2
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than
V
, and goes LOW when V2 is less than V
TRIP2
pin. The V2RO pin requires the use of an external “pull-up” resistor.
V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active whenever
V
V1 / Vcc falls below
after the power supply stabilizes (t
. V1RO becomes active on power-up and remains active for a time t
TRIP1
can be changed by varying the POR0 and POR1 bits of the
purst
internal control register). The V1RO pin requires the use of an external “pull-up” resistor. The V1RO
pin can be forced active (HIGH) using the manual reset (MR) input pin.
after MR has
purst
. There is no power-up reset delay circuitry on this
TRIP2
purst
3
FN8209.1
January 3, 2006
SCL
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SDA
X9523
Data Stable Data Change Data Stable
Figure 1. Valid Data Changes on the SDA Bus
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive operations. Therefore, the X9523 operates as a slave in all
applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1.On power-up of the X9523, the SDA pin is
in the input mode.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subsequent eight bit word.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will ter-
SCL
SDA
Start Stop
Figure 2. Valid Start and Stop Conditions
4
FN8209.1
January 3, 2006
SCL
www.BDTIC.com/Intersil
SCL
from
from
Master
Master
Data Output
from
Transmitter
Data Output
from
Receiver
X9523
81 9
Start Acknowledge
Figure 3. Acknowledge Response From Receiver
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9523
can be split up into two main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9523 to
be addressed, and specifies if a Read or Write operation is to be performed.
It should be noted that in order to perform a write operation to a DCP, the Write Enable Latch (WEL) bit must first
be set (See “WEL: Write Enable Latch (Volatile)” on
page 10.).
Slave Address Byte
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally
selects the DCP structures in the X9523. The CONSTAT Register may be selected using the Internal
Device Address 010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W
bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W
bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CONSTAT Register) has been correctly issued (including the
SA6SA7
SA5
1010
DEVICE TYPE
IDENTIFIER
SA4
SA3 SA2
INTERNAL
DEVICE
ADDRESS
SA1
SA0
R/W
READ /
WRITE
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
Internal Address
(SA3 - SA1)
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
All Others
The Device Type Identifier must always be set to 1010
in order to select the X9523.
Bit SA0 Operation
Figure 4. Slave Address Format
5
Internally Addressed
Device
010
111
0WRITE
1 READ
CONSTAT Register
DCP
RESERVED
January 3, 2006
FN8209.1
final STOP condition), the X9523 initiates an internal high
www.BDTIC.com/Intersil
voltage write cycle. This cycle typically requires 5 ms.
During this time, no further Read or Write commands can
be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no
ACKNOWLEDGE will be returned. If the device has
completed the write operation, an ACKNOWLEDGE will
be returned and the host can then proceed with a read or
write operation. (Refer to Figure 5.).
Byte load completed
by issuing STOP.
Enter ACK Polling
X9523
)
N
WIPER
COUNTER
REGISTER
(WCR)
NON
VOLATILE
MEMORY
(NVM)
DECODER
“WIPER”
FET
SWITCHES
2
1
0
Figure 6. DCP Internal Structure
RESISTOR
ARRAY
R
Hx
R
Lx
R
Wx
Issue START
Issue Slave Address
Byte (Read or Write)
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
YES
Continue normal
Read or Write
command sequence
PROCEED
Issue STOP
NO
NO
Issue STOP
Figure 5. Acknowledge Polling Sequence
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9523 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
) output. Within each individual array, only one
(R
x
w
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
On power-up of the X9523, wiper position data is automatically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
DCP Initial Values Before Recall
/ 100 TAP VL / TAP = 0
R
1
/ 256 TAP VH / TAP = 255
R
2
and R
Hx
Lx
6
FN8209.1
January 3, 2006
V1/Vcc
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X9523
V1/Vcc (Max.)
V
TRIP1
t
trans
0
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.
t
purst
Figure 7. DCP Power-up
Hot Pluggability
Figure 7 shows a typical waveform that the X9523 might
experience in a Hot Pluggable situation. On power-up,
V1 / Vcc applied to the X9523 may exhibit some amount
of ringing, before it settles to the required value.
The device is designed such that the wiper terminal
) is recalled to the correct position (as per the last
(R
Wx
stored in the DCP NVM), when the voltage applied to
V1/Vcc exceeds V
Power-on Reset time, set in the CONSTAT Register See “CONTROL AND STATUS REGISTER” on
page 10.).
Therefore, if
Vcc to settle above V
wiper terminal position is recalled by (a maximum) time:
t
+ t
trans
by system hot plug conditions.
t
trans
. It should be noted that t
purst
for a time exceeding t
TRIP1
is defined as the time taken for V1 /
(Figure 7): then the desired
TRIP1
trans
is determined
purst
(the
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after V1/Vcc of
the X9523 is powered down and then powered back up.
t
Maximum Wiper Recall time
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1/Vcc to the
device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
Instruction Byte
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit of
the Instruction Byte (I7), determines the Write Type (WT)
performed.
If WT is “1”, then a Nonvolatile Write to the DCP
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated
occurs.
7
FN8209.1
January 3, 2006
X9523
www.BDTIC.com/Intersil
I5I6I7 I4 I3 I2 I1 I0
00WT 0 0 0 P1 P0
WRITE TYPE
†
WT
Select a Volatile Write operation to be performed
0
on the DCP pointed to by bits P1 and P0
Select a Nonvolatile Write operation to be per-
1
formed on the DCP pointed to by bits P1 and P0
†
This bit has no effect when a Read operation is being performed.
Description
DCP SELECT
Figure 8. Instruction Byte Format
WCR and NVM. Therefore, the new “wiper position” setting is recalled into the WCR after V1/Vcc of the X9523
has been powered down then powered back up.
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. Therefore, when V1/Vcc to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See “WEL: Write Enable Latch
(Volatile)” on page 10.).
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9523 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9523.
Following the Instruction Byte, a Data Byte is issued to
the X9523 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 29).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
P1- P0 DCPx # Taps Max. Data Byte
0 0 RESERVED
0 1 x = 1 100 Refer to Appendix 1
1 0 x = 2 256 FFh
1 1 RESERVED
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. Therefore, the Data Byte 00001111 (15
) corresponds to set-
10
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28
) corresponds to setting the
10
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1”. An example of a simple C language function which “translates” between the tap position (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2”.
10101110
S
T
A
R
T
SLAVE ADDRESS BYTE
A
WT 0 0 0 0 0 P1 P0 A
C
K
INSTRUCTION BYTE
C
K
Figure 9. DCP Write Command Sequence
8
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
A
T
C
O
K
P
FN8209.1
January 3, 2006
X9523
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S
WRITE Operation
Signals from
the Master
t
a
r
Slave
Address
Instruction
Byte
t
SDA Bus
Signals from
the Slave
101 11100
“Dummy” write
W
00 000
T
A
C
K
Figure 10. DCP Read Sequence
It should be noted that all writes to any DCP of the
X9523 are random in nature. Therefore, the Data
Byte of consecutive write operations to any DCP can
differ by an arbitrary number of bits. Also, setting the
bits P1 = 1, P0 = 1 is a reserved sequence, and will
result in no ACKNOWLEDGE after sending an
Instruction Byte on SDA.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-
R
sponds to having the “wiper teminal”
(x = 1,2) at the
WX
“lowest” tap position, Therefore, the resistance between
R
and RLX is a minimum (essentially only the Wiper
WX
Resistance,
R
).
W
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
S
READ Operation
t
Slave
a
r
Address
Data Byte
t
P
P
1
101 11110
0
A
C
K
A
C
K
MSB
S
t
o
p
-
“-” = DON’T CARE
LSB
DCPx
x = 1
x = 2
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9523 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9523.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W
bit set to 1. Then the X9523
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
S
Signals from
the Master
SDA Bus
Signals from
the Slave
t
a
r
t
1
Address
01
WRITE Operation
Slave
0
0
0
0
Internal
Device
Address
Address
Byte
0
A
C
K
A
C
K
Figure 11. EEPROM Byte Write Sequence
9
Data
Byte
S
t
o
p
A
C
K
FN8209.1
January 3, 2006
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