intersil ISL6225 DATA SHEET

Memory Power System Solution

ISL6225 Dual PWM Controller Provides Complete DDR

Application Note December 2001

Introduction

As computer memory bandwidth is pushed further and further to multi-Gb/s levels, new memory technologies are emerging. The DDR (Dual Data Rate) memory is an evolutionary step on this path that along with increased data rate maintains the low cost legacy of SDRAMs and thus will dominate most PC markets for several years to come [1]. The DDR memory not only increases the memory bandwidth but also reduces memory power consumption. The major contributors to reduced power consumption are lower operating voltage, lower signal voltage swing associated with SSTL_2 logic, and reduced time spent in an active mode. All these features make DDR memory a desirable component for mobile, battery-powered applications [2, 3].

DDR Memory Power Requirements

The new memory comes with some additional requirements. The increased bandwidth made available by SSTL_2 signaling require special clock techniques, proper layout, a power source tracking reference signal, and line termination.

AN9995

Author: Vladimir A. Muratov, Steven P. Laur

memory operates with a double rate. Practically, the VTT current gets dramatically averaged in output capacitors due to a low duty factor (~15 to 30%) of read-write states [4]. The terminating VTT power supply requirements depend only on the number of lines and value of the terminating resistors used and does not vary with memory size. Measurements done in practical circuits show typical current levels in a range of 0.5A. Tests show that the more memory is engaged by the software, the lower is VTT current. All these suggests that the same optimized solution can be used for various computer applications.

The VDDQ power supply usually provides current not only to the memory banks, but to a ‘north bridge’ controller and some other circuitry as well. The current has a permanent base level in a range of 2.0–3.0A. The base level depends on how aggressive the power management scheme of a memory controller isand also varies with memory size. The bigger memory draws more current on background. Depending on the computing task performed, the current can peak up to 4.0A.

The important part of SSTL_2 signaling is that bus signals are referenced to the reference voltage VREF that is usually held symmetrically between VDDQ and VSS. It is important that VREF stays symmetrically positioned between VDDQ and VSS levels over variations in environmental and supply parameters, Figure 1. The termination voltage VTT should be within ±40mV of VREF. The VDDQ voltage, currently 2.5V nominal value, should have ±200mV tolerance.

VTT=VDDQ/2

VDDQ

Transmitter

=50Ω

RS=22Ω

FIGURE 1. DDR MEMORY TERMINATION

Line

50Ω

VREF=VDDQ/2

VDDQ

Receiver

Each terminated line consumes 16.2 mA. With about 125 lines compliant with SSTL_2 speciﬁcations, this theoretically makes maximum current capability of VTT supply Imax=2.025A, sourcing or sinking. In reality, the front bus is operating on frequency of 100MHz, 133MHz and any given memory state is actively present on the bus for a very short moment of time of several tens of nanoseconds as DDR

ISL6225–Provides Complete Power Solution for DDR Memory

The ISL6225 dual switcher accomplishes all of the goals associated with DDR memory power by combining two synchronous PWM voltage regulators into a single IC. Its unique design allows the IC to both source and sink current on one of the channels. This ability allows the IC to be adapted very effectively to a DDR memory power solution when the DDR pin is set high.

The ﬁrst PWM channel is used to regulate 2.5VDC (V a typical “buck” regulator fashion. The output voltage of the ﬁrst channel is set to the required VDDQ level by the external voltage divider. This makes the chip compatible not only with current DDR memory speciﬁcations, but, also, with future DDR II requirements. To provide the required tracking function, the output of this regulated voltage is divided down to 1.25VDC by an external R/R divider and fed back into the IC as a tracking reference voltage.The reference voltage VREF required by the DDR memory chips is provided via the PG2/REF pin that can source up to 10mA. This output also serves as a reference for the VTT channel. The second channel will then regulate to 1.25VDC (V

) with high

precision.

Please refer to the ISL6225 datasheet, FN9049, for more information [5].

DDQ

)in

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

JP2

FCCM

JP5

VINPRG

Jumper View

Application Note AN9995

Quick Start Evaluation

Out Of The Box

The ISL6225EVAL1 comes in a “ready-to-test” state. The board comes equipped with several jumpers pre-populated for battery operation. Use Table 1, which describes jumper function, for test setup. Table 2 illustrates the input and output voltage and current speciﬁcations.

NOTE: Note: This Application Note is for the DDR solution only.

Required Test Equipment

To fully test the ISL6225 chip functionality characterized by this Application Note, the follow equipment is needed:

•4 channel oscilloscope with probes

•2 electronic loads

•2 bench power supplies

• precision digital multi-meters

• Digital pulse generator

TABLE 1. JUMPER FUNCTIONALITY

Jumper # State Function

JP1 POP Normal Operation

NOP Measure operating current I

JP2 POS1 Enable hysteretic operation

POS2 FCCM mode

JP3 POP Connect EN1 to VCC

NOP External EN1

JP4 POP Connect EN2 to VCC

NOP External EN2

JP5 POS1 Operate in Battery Mode

POS2 Operate in 5V Mode

Power Connections

With the all supplies turned OFF, connect the 0-24V power supply positive terminal to the VIN post (J2) on the EVAL board and the negative terminal to the nearest GND post (J3). Then connect the 0-5V power supply positive terminal to the VCC post (J4) and the negative terminal to the nearest GND post (J1)

It should be noted that VIN must be powered up prior to VCC in all cases.

TABLE 2. INPUT/OUTPUT VOLTAGE/CURRENT

OPERATING SPECIFICATIONS.

VIN VCC VDDQ VTT

Voltage

Imax

Inom

5-24V 5V 2.5V 1.25V

3A 3A 6A 3A

--3A2A

VCC

Load Connections

Connect the ﬁrst electronic load positive terminal to VDDQ (J5) and the negative terminal to GND (J6). Connect the positive terminal of the second electronic load to VTT (J6) and negative terminal to the nearest GND post (J9).

Performance Characterization

This section will show measured performance data from a standard bench setup. It will include descriptions of each experiment performed and how to recreate them.

NOTES:

•Jumper JP1 should be populated.

•Connect JP2 in FCCM mode

•Connect JP5 in the EN5V position.

•VIN = 5V, VCC = 5V.

Modes of Operation

Figure 10 shows a typical circuit for One-Step Conversion. This is accomplished by populating jumper JP5 in POS1. In this arrangement, V battery voltage. V V

output. This setup has the advantage of not requiring

DDQ

a regulated system voltage to supply the power train.

Tw o-Step Conversion is also available on the ISL6225 DDR evaluation board. This approach requires a regulated 5 volt system rail to provide power to the converters. The V converter takes the system rail voltage while the V converter is cascaded from V tied to GND through a 100kOhm resistor. This is done by populating jumper JP5 in POS2 and tying the V terminals together on the application board.

Soft-Start

In a start up event, the IC is required to ramp both output voltages smoothly to their programmed level. To do this, the chip must disable the undervoltage and pgood circuitry until the output has risen to within 75% of its target. Only then is PGOOD released and the part allowed to operate normally.

With I Figure 2.

• Connect the digital pulse generator to JP3 and JP4 to allow for external enabling of the chip.

• Set the scope to trigger on EN (J12).

VDDQ

= I

VTT

is converted directly from the

DDQ

is then converted directly from the

DDQ

and V

must be

. In this case, V

DDQ

= 3A, the start up event is captured in

FIGURE 4. LOAD TRANSIENT (VTT - GND)

VDDQ, 50mV/div

VTT, 50mV/div

20us / div

2.5V

1.25V

Load Current, 2A/div

FIGURE 5. LOAD TRANSIENT (VDDQ - VTT)

VTT, 50mV/div

VDDQ, 50mV/div

Load Current, 2A/div

20us/div

1.25V

2.5V

Application Note AN9995

EN, 5V/div

VDDQ, 1V/div

VTT, 1V/div

PGOOD, 5V/div

1ms/div

FIGURE 2. INITIAL START UP

Steady-State Operation

Under normal operating conditions, the ISL6225 should regulate 2.5V and 1.25V with minimal effort and output voltage ripple. Figure 3 illustrates converter waveforms during normal operating conditions.

VDDQ, 50mV/div

2.5V

Sinking Mode (V

DDQ

to V

)

The output voltage excursion under a load transient in sinking mode is shown in Figure 5. The load swings 0-3A from V between V

DDQ

into V

DDQ

. Reconﬁgure the second electronic load

and V

for this experiment.

PHASE_VDDQ, 10V/div

1.25V

PHASE_VTT, 2V/div

5us/div

FIGURE 3. NORMAL OPERATION

VTT, 50mV/div

Transient Response

The ISL6225 in DDR applications is required to handle load transients of 0-3A on V load of 3A from V

DDQ

Sourcing Mode (V

The output voltage excursion under a load transient event is shown in Figure 4. The load swings 0-3A from V

. For these tests, there is a static

to GND.

to GND)

Efﬁciency

It is important to illustrate that each channel of the ISL6225 is highly efﬁcient, which contributes to an overall high system efﬁciency. Figures 6...9 demonstrate all perspectives of efﬁciency for the ISL6225 in DDR mode.

NOTE:

•Measure voltage at board terminals

•Allow thermal equilibrium

•TA = 25C

•No forced air

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