Intersil Corporation ICL7137, ICL7136 Datasheet

December 1997

ICL7136, ICL7137

31/2 Digit LCD/LED, Low Power Display, A/D Converters with Overrange Recovery

Features

•First Reading Overrange Recovery in One Conversion Period

•Guaranteed Zero Reading for 0V Input on All Scales

•True Polarity at Zero for Precise Null Detection

•1pA Typical Input Current

•True Differential Input and Reference, Direct Display Drive

-LCD ICL7136

-LED lCL7137

•Low Noise - Less Than 15μVP-P

•On Chip Clock and Reference

•No Additional Active Circuits Required

•Low Power - Less Than 1mW

•Surface Mount Package Available

•Drop-In Replacement for ICL7126, No Changes Needed

Ordering Information

	TEMP.
PART NUMBER	RANGE (oC)		PACKAGE	PKG. NO.
ICL7136CPL	0 to 70	40 Ld PDIP		E40.6
ICL7136RCPL	0 to 70	40	Ld PDIP (Note)	E40.6
ICL7136CM44	0 to 70	44 Ld MQFP		Q44.10x10
ICL7137CPL	0 to 70	40	Ld PDIP	E40.6
ICL7137RCPL	0 to 70	40	Ld PDIP (Note)	E40.6
ICL7137CM44	0 to 70	44 Ld MQFP		Q44.10x10

NOTE: “R” indicates device with reversed leads.

Description

The Intersil ICL7136 and ICL7137 are high performance, low power 31/2 digit, A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7136 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7137 will directly drive an instrument size, light emitting diode (LED) display.

The ICL7136 and ICL7137 bring together a combination of high accuracy, versatility, and true economy. It features autozero to less than 10μV, zero drift of less than 1μV/oC, input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7136), enables a high performance panel meter to be built with the addition of only 10 passive components and a display.

The ICL7136 and ICL7137 are improved versions of the ICL7126, eliminating the overrange hangover and hysteresis effects, and should be used in its place in all applications. It can also be used as a plug-in replacement for the ICL7106 in a wide variety of applications, changing only the passive components.

Pinouts

(PDIP)	(MQFP)
TOP VIEW	TOP VIEW

	V+	1
	D1	2
	C1	3
	B1	4
(1’s)	A1	5

F1

6

G1

7

E1	8
D2	9

C2	10
B2	11
(10’s)	12
A2
F2	13

E2

14

D3

15

B3	16
(100’s)	17
F3
E3	18

(1000) AB4 19

POL 20

(MINUS)

40

OSC 1

REFHI

REFLO

C

C

COMMON

HIIN

LOIN

Z-A

BUFF

INT

-V

+

-

39

OSC 2

REF

REF

38

OSC 3

37

TEST

36

REF HI

35	REF LO		NC	44 43 42 41 40	39 38		37 36		35 34	NC
34	CREF+			1					33
			NC	2					32	G2
33	CREF-
			TEST	3					31	C3
32	COMMON
			OSC 3	4					30	A3
31	IN HI
			NC	5					29	G3
30	IN LO
			OSC 2	6					28	BP/GND
29	A-Z
			OSC 1	7					27	POL
28	BUFF
			V+	8					26	AB4
27	INT
			D1	9					25	E3
26	V-
			C1	10					24	F3
25	G2 (10’s)
				11					23
24	C3		B1		17	18	19			B3
				12 13 14 15 16				20 21 22
23	A3	(100’s)
22	G3
21	BP/GND			A1 F1 G1 E1 D2 C2 B2			A2 F2 E2 D3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.	File Number 3086.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1

ICL7136, ICL7137

Absolute Maximum Ratings

Supply Voltage

ICL7136, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V ICL7137, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V ICL7137, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V- Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-

Clock Input

ICL7136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ ICL7137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+

Thermal Information

Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(MQFP - Lead Tips Only)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1.Input voltages may exceed the supply voltages provided the input current is limited to ±100μA.

2.θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications (Note 3)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNITS
	SYSTEM PERFORMANCE
	Zero Input Reading	VIN = 0V, Full Scale = 200mV	-000.0	±000.0	+000.0	Digital
						Read-
						ing
	Ratiometric Reading	VlN = VREF, VREF = 100mV	999	999/	1000	Digital
				1000		Read-
						ing
	Rollover Error	-VIN = +VlN 200mV Difference in Reading for Equal	-	±0.2	±1	Counts
		Positive and Negative Inputs Near Full Scale
	Linearity	Full Scale = 200mV or Full Scale = 2V Maximum	-	±0.2	±1	Counts
		Deviation from Best Straight Line Fit (Note 5)
	Common Mode Rejection Ratio	VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5)	-	50	-	μV/V
	Noise	VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not	-	15	-	μV
		Exceeded 95% of Time) (Note 5)
	Leakage Current Input	VlN = 0V (Note 5)	-	1	10	pA
	Zero Reading Drift	VlN = 0V, 0oC To 70oC (Note 5)	-	0.2	1	μV/oC
	Scale Factor Temperature Coefficient	VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/oC) (Note 5)	-	1	5	ppm/oC
	COMMON Pin Analog Common Voltage	25kΩ Between Common and Positive Supply (With	2.4	3.0	3.2	V
		Respect to + Supply)
	Temperature Coefficient of Analog	25kΩ Between Common and Positive Supply (With	-	150	-	ppm/oC
	Common	Respect to + Supply) (Note 5)
	SUPPLY CURRENT ICL7136
	V+ Supply Current	VIN = 0 (Does Not Include Common Current) 16kHz	-	70	100	μA
		Oscillator (Note 6)
	SUPPLY CURRENT ICL7137
	V+ Supply Current	VIN = 0 (Does Not Include Common Current) 16kHz	-	70	200	μA
		Oscillator (Note 6)
	V- Supply Current		-	40	-	μA
	DISPLAY DRIVER ICL7136 ONLY
	Peak-To-Peak Segment Drive Voltage	V+ = to V- = 9V (Note 4)	4	5.5	6	V
	Peak-To-Peak Backplane Drive Voltage

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ICL7136, ICL7137

Electrical Specifications (Note 3)		(Continued)
	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNITS
DISPLAY DRIVER ICL7137 ONLY
Segment Sinking Current		V+ = 5V, Segment Voltage = 3V
	(Except Pins 19 and 20)		5	8	-	mA
	Pin 19 Only		10	16	-	mA
	Pin 20 Only		4	7	-	mA

NOTES:

3.Unless otherwise noted, specifications apply to both the ICL7136 and ICL7137 at TA = 25oC, fCLOCK = 48kHz. ICL7136 is tested in the circuit of Figure 1. ICL7137 is tested in the circuit of Figure 2.

4.Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV.

5.Not tested, guaranteed by design.

6.48kHz oscillator increases current by 20μA (Typ).

Typical Applications and Test Circuits

			+	-	9V
			IN	+	-
	R1		R5
R3	R4	C1	C5 C2 R2		C3
	C4				DISPLAY

40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21
OSC 1	OSC 2	OSC 3	TEST	REF HI	REF LO	+	-	COM	IN HI	IN LO	A-Z	BUFF	INT	V-	G2	C3	A3	G3	BP
						REF	REF
						C	C
									ICL7136

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB4

POL

1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
									DISPLAY

C1 = 0.1μF

C2 = 0.47μF

C3 = 0.047μF

C4 = 50pF

C5 = 0.01μF

R1 = 240kΩ

R2 = 180kΩ

R3 = 180kΩ

R4 = 10kΩ

R5 = 1MΩ

FIGURE 1. ICL7136 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE

	+5V		+ -				-5V
			IN
	R1		R5
	R4	C1	C5	C2	R	2	C3
R3
	C4						DISPLAY

40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21
OSC 1	OSC 2	OSC 3	TEST	REF HI	REF LO	+	-	COM	IN HI	IN LO	A-Z	BUFF	INT	V-	G2	C3	A3	G3	GND
						REF	REF
						C	C
									ICL7137

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB4

POL

1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
									DISPLAY

C1 = 0.1μF

C2 = 0.47μF

C3 = 0.047μF

C4 = 50pF

C5 = 0.01μF

R1 = 240kΩ

R2 = 180kΩ

R3 = 180kΩ

R4 = 10kΩ

R5 = 1MΩ

FIGURE 2. ICL7137 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE

3

ICL7136, ICL7137

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

fOSC = 0.45/RC

COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 48kHz

• OSCILLATOR PERIOD

tOSC = RC/0.45

• INTEGRATION CLOCK FREQUENCY

fCLOCK = fOSC/4

• INTEGRATION PERIOD

tINT = 1000 x (4/fOSC)

• 60/50Hz REJECTION CRITERION

tINT/t60Hz or tlNT/t50Hz = Integer

• OPTIMUM INTEGRATION CURRENT

IINT = 1μA

• FULL SCALE ANALOG INPUT VOLTAGE

VlNFS (Typ) = 200mV or 2V

• INTEGRATE RESISTOR

VINFS

RINT = ----------------

IINT

• INTEGRATE CAPACITOR

(tINT)(IINT)

CINT = -------------------------------

VINT

• INTEGRATOR OUTPUT VOLTAGE SWING

(tINT)(IINT)

VINT = -------------------------------

CINT

• VINT MAXIMUM SWING:

(V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V

• DISPLAY COUNT

× VIN

COUNT = 1000 --------------

VREF

• CONVERSION CYCLE

tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000

when fOSC = 48kHz; tCYC = 333ms

• COMMON MODE INPUT VOLTAGE

(V- + 1V) < VlN < (V+ - 0.5V)

• AUTO-ZERO CAPACITOR

0.01μF < CAZ < 1μF

• REFERENCE CAPACITOR

0.1μF < CREF < 1μF

• VCOM

Biased between V+ and V-.

• VCOM V+ - 2.8V

Regulation lost when V+ to V- < 6.8V.

If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off.

• ICL7136 POWER SUPPLY: SINGLE 9V

V+ - V- = 9V

Digital supply is generated internally VTEST V+ - 4.5V

• ICL7136 DISPLAY: LCD

Type: Direct drive with digital logic supply amplitude.

• ICL7137 POWER SUPPLY: DUAL±5.0V

V+ = +5V to GND V- = -5V to GND

Digital Logic and LED driver supply V+ to GND

• ICL7137 DISPLAY: LED

Type: Non-Multiplexed Common Anode

Typical Integrator Amplifier Output Waveform (INT Pin)

AUTO ZERO PHASE	SIGNAL INTEGRATE	DE-INTEGRATE PHASE
(COUNTS)	PHASE FIXED	0 - 1999 COUNTS
2999 - 1000	1000 COUNTS

TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC

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ICL7136, ICL7137

Pin Descriptions

PIN NUMBER
	44 PIN
40 PIN DIP	FLATPACK	NAME	FUNCTION	DESCRIPTION
1	8	V+	Supply	Power Supply.
2	9	D1	Output	Driver Pin for Segment “D” of the display units digit.
3	10	C1	Output	Driver Pin for Segment “C” of the display units digit.
4	11	B1	Output	Driver Pin for Segment “B” of the display units digit.
5	12	A1	Output	Driver Pin for Segment “A” of the display units digit.
6	13	F1	Output	Driver Pin for Segment “F” of the display units digit.
7	14	G1	Output	Driver Pin for Segment “G” of the display units digit.
8	15	E1	Output	Driver Pin for Segment “E” of the display units digit.
9	16	D2	Output	Driver Pin for Segment “D” of the display tens digit.
10	17	C2	Output	Driver Pin for Segment “C” of the display tens digit.
11	18	B2	Output	Driver Pin for Segment “B” of the display tens digit.
12	19	A2	Output	Driver Pin for Segment “A” of the display tens digit.
13	20	F2	Output	Driver Pin for Segment “F” of the display tens digit.
14	21	E2	Output	Driver Pin for Segment “E” of the display tens digit.
15	22	D3	Output	Driver pin for segment “D” of the display hundreds digit.
16	23	B3	Output	Driver pin for segment “B” of the display hundreds digit.
17	24	F3	Output	Driver pin for segment “F” of the display hundreds digit.
18	25	E3	Output	Driver pin for segment “E” of the display hundreds digit.
19	26	AB4	Output	Driver pin for both “A” and “B” segments of the display thousands digit.
20	27	POL	Output	Driver pin for the negative sign of the display.
21	28	BP/GND	Output	Driver pin for the LCD backplane/Power Supply Ground.
22	29	G3	Output	Driver pin for segment “G” of the display hundreds digit.
23	30	A3	Output	Driver pin for segment “A” of the display hundreds digit.
24	31	C3	Output	Driver pin for segment “C” of the display hundreds digit.
25	32	G2	Output	Driver pin for segment “G” of the display tens digit.
26	34	V-	Supply	Negative power supply.
27	35	INT	Output	Integrator amplifier output. To be connected to integrating capacitor.
28	36	BUFF	Output	Input buffer amplifier output. To be connected to integrating resistor.
29	37	A-Z	Input	Integrator amplifier input.To be connected to auto-zero capacitor.
30	38	IN LO	Input	Differential inputs. To be connected to input voltage to be measured. LO and HI
31	39	IN HI		designators are for reference and do not imply that LO should be connected to
				lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI.
32	40	COMMON	Supply/	Internal voltage reference output.
			Output
33	41	CREF-		Connection pins for reference capacitor.
34	42	CREF+
35	43	REF LO	Input	Input pins for reference voltage to the device. REF HI should be positive
36	44	REF HI		reference to REF LO.
37	3	TEST	Input	Display test. Turns on all segments when tied to V+.
38	4	OSC3	Output	Device clock generator circuit connection pins.
39	6	OSC2	Output
40	7	OSC1	Input

5

ICL7136, ICL7137

Detailed Description

Analog Section

Figure 3 shows the Analog Section for the ICL7136 and ICL7137. Each measurement cycle is divided into four phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE), (4) zero integrate (ZI).

Auto-Zero Phase

During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10μV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined.

De-Integrate Phase

The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input

high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is:

æ VIN ö

DISPLAY READING = 1000ç--------------÷ .

èVREFø

Zero Integrator Phase

The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Finally, a feedback loop is closed around the system to IN HI to cause the integrator output to return to zero. Under normal conditions, this phase lasts for between 11 to 140 clock pulses, but after a “heavy” overrange conversion, it is extended to 740 clock pulses.

Differential Input

The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity.

STRAY	CREF		STRAY
				RINT			CAZ	CINT
+	REF HI	REF LO	CREF -	BUFFER	V+		A-Z	INT
CREF
34	36	35	33	28	1	29		27
V+
	A-Z,	A-Z,	-				INTEGRATOR
	ZI	ZI
10μA			+				-	-	TO
									DIGITAL
							+	+
31				2.8V					SECTION
IN HI
INT	DE-	DE+	INPUT			6.2V	A-Z
			HIGH
A-Z							COMPARATOR
				-
			N				ZI
	DE+	DE-		+
32
COMMON
INT	A-Z AND DE(±)						INPUT
	AND ZI						LOW
30

IN LO

26

V-

FIGURE 3. ANALOG SECTION OF ICL7136 AND ICL7137

6