The HA-5127/883 monolithic operational amplifier features
an excellent combination of precision DC and wideband high
speed characteristics. Utilizing the Intersil D.I. technology
and advanced processing techniques, this unique design
unites low noise precision instrumentation performance with
high speed, wideband capability.
This amplifier’s impressive list of features include low V
OS
,
wide gain-bandwidth, high open loop gain, and high CMRR.
Additionally, this flexible device operates over a wide supply
range while consuming only 120mW of power.
Using the HA-5127/883 allows designers to minimize errors
while maximizing speed and bandwidth.
This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5127/883’s qualities include instrumentation amplifiers,
pulse or RF amplifiers, audio preamplifiers, and signal
conditioning circuits.
Ordering Information
PART
NUMBER
HA2-5127/883 HA2-5127/883 -55 to +125 8 Pin CanT8.C
PAR T
MARKING
TEMP
RANGE
(°C)PACKAGE
PKG.
DWG. #
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V
PARAMETERSSYMBOLCONDITIONS
Output Current+I
Quiescent Power
Supply Current
Power Supply
Rejection Ratio
Offset Voltage
Adjustment
NOTE:
1. Offset adjustment range is [V
2. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.
SUPPLY
= ±15V, R
SOURCE
= 50Ω, R
LOAD
= 100kΩ, V
= 0V, Unless Otherwise Specified.
OUT
GROUP A
SUBGROUPSTEMPERATURE
V
OUT
-I
OUT
+I
CC
-I
CC
+PSRR∆V
-PSRR∆V
= -10V4+25oC16.5-mA
OUT
V
= +10V4+25oC--16.5mA
OUT
V
= 0V, I
OUT
V
= 0V, I
OUT
= 14V1+25oC86-dB
SUP
∆V
= 13.5V2, 3+125oC, -55oC86 - dB
SUP
= 14V1+25oC86-dB
SUP
= 13.5V2, 3+125oC, -55oC86 - dB
∆V
SUP
= 0mA1+25oC-4mA
OUT
o
2, 3+125
= 0mA1+25oC-4-mA
OUT
2, 3+125
C, -55oC- 4mA
o
C, -55oC-4 - mA
+VIOAdjNote 11+25oCV
o
2, 3+125
AdjNote 11+25oCV
-V
IO
2, 3+125
(Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V.
IO
C, -55oCV
o
C, -55oCV
LIMITS
-1-mV
IO
-1-mV
IO
+1-mV
IO
+1-mV
IO
UNITSMINMAX
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
SUPPLY
= ±15V, R
SOURCE
= 50Ω, R
PARAMETERSSYMBOLCONDITIONS
Slew Rate+SRV
-SRV
Rise and Fall Timet
R
= -3V to +3V7+25oC7-V/µs
OUT
= +3V to -3V7+25oC7-V/µs
OUT
V
= 0 to +200mV
OUT
10% ≤ T
V
t
F
= 0 to -200mV
OUT
10% ≤ T
Overshoot+OSV
-OSV
= 0 to +200mV7+25oC-40%
OUT
= 0 to -200mV7+25oC-40%
OUT
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: V
SUPPLY
= ±15V, R
LOAD
PARAMETERSSYMBOLCONDITIONSNOTESTEMPERATURE
Average Offset Voltage DriftV
Differential Input ResistanceR
TCVCM = 0V1-55oC to +125oC- 1.8µV/oC
IO
IN
LOAD
≤ 90%
R
≤ 90%
F
= 2kΩ, C
= 2kΩ, C
= 50pF, AV = +1V/V, Unless Otherwise Specified.
LOAD
LOAD
= 50pF, A
= +1V/V, Unless Otherwise Specified.
VCL
GROUP A
SUBGROUPTEMPERATURE
7+25
7+25
o
C-150ns
o
C-150ns
LIMITS
UNITSMINMAX
LIMITS
MINMAXUNITS
VCM = 0V1+25oC0.8-MΩ
3
FN3751.3
January 16, 2006
Device Characterized at: V
www.BDTIC.com/Intersil
SUPPLY
HA-5127/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
= ±15V, R
LOAD
= 2kΩ, C
= 50pF, AV = +1V/V, Unless Otherwise Specified.
LOAD
LIMITS
PARAMETERSSYMBOLCONDITIONSNOTESTEMPERATURE
Low Frequency Peak-to-Peak
Noise
Input Noise Voltage DensityE
Input Noise Current DensityI
Unity Gain BandwidthUGBWVO = 100mV1+25oC5-MHz
Full Power BandwidthFPBWV
Minimum Closed Loop Stable
Gain
Settling Timet
Output ResistanceR
Quiescent Power ConsumptionPCV
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πV
3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on output.)
E
NP-P
N
N
CLSGR
S
OUT
0.1Hz to 10Hz1+25oC-0.25µV
RS = 20Ω, fO = 10Hz1+25oC-10.0nV/√Hz
RS = 20Ω, fO = 100Hz1+25oC-5.6nV/√Hz
RS = 20Ω, fO = 1kHz1+25oC-4.5nV/√Hz
RS = 2MΩ, fO = 10Hz1+25oC-4.0pA/√Hz
RS = 2MΩ, fO = 100Hz1+25oC-2.3pA/√Hz
RS = 2MΩ, fO = 1kHz1+25oC-0.6pA/√Hz
= 10V1, 2+25oC111-kHz
PEAK
= 2kΩ, CL = 50pF1-55oC to +125oC±1-V/V
L
To 0.1% for a 10V Step1+25oC-2µs
Open Loop1+25oC-100Ω
OUT
= 0V, I
= 0mA1, 3-55oC to +125oC- 120 mW
OUT
PEAK
MINMAXUNITS
P-P
).
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTSSUBGROUPS (SEE TABLES 1 AND 2) (NOTE 2)
Interim Electrical Parameters (Pre Burn-In)1
Final Electrical Test Parameters1 (Note 1), 2, 3, 4, 5, 6, 7
Group A Test Requirements1, 2, 3, 4, 5, 6, 7
Groups C and D Endpoints1
NOTES:
1. PDA applies to Subgroup 1 only.
2. The Subgroup assignments of the parameters in these tables were patterned after Mil-M-38510/135, with the exception of V
is Subgroups 1, 2, 3.
4
, which
IO
FN3751.3
January 16, 2006
Die Characteristics
www.BDTIC.com/Intersil
SUBSTRATE POTENTIAL (Powered Up): V-
TRANSISTOR COUNT: 63
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5127/883
HA-5127/883
BAL
BAL
-IN
+IN
V+
OUT
V-
NC
5
FN3751.3
January 16, 2006
Metal Can Packages (Can)
www.BDTIC.com/Intersil
HA-5127/883
HA-5127/883
REFERENCE PLANE
A
ØD ØD1
F
Q
Øb1
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
α is the basic spacing from the centerline of the tab to terminal 1
3.
and β is the basic spacing of each lead or lead position (N -1
places) from
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
6
FN3751.3
January 16, 2006
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