intersil HA-5101-883 DATA SHEET

®
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HA-5101/883
Data Sheet August 17, 2005 FN3931.1
Low Noise, High Performance Operational Amplifier
The HA-5101/883 is a dielectrically isolated operational amplifier featuring low noise and high performance. This amplifier has an excellent noise voltage density of
DC characteristics of the HA-5101/883 assure accurate performance. The 3mV (max) offset voltage is externally adjustable and offset voltage drift is just 3µV/°C. Low bias currents (200nA max) reduce input current errors and the high open loop voltage gain of 100kV/V, over temperature, increases the loop gain for low distortion amplification.
The HA-5101/883 is ideal for audio applications, especially low-level signal amplifiers such as microphone, tape head and preamplifiers. Additionally, it is well suited for low distortion oscillators, low noise function generators and high Q filters.
(max) at 1kHz. The unity gain stable
Features
• This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• Low Noise Voltage @ 1kHz . . . . . . . . . . . 4.5nV/√Hz
• Low Noise Current @ 1kHz . . . . . . . . . . . . . 3pA/√Hz
Max
Max
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . .10MHz Min
• High Gain (Full Temp) . . . . . . . . . . . . . . . . . .100kV/V Min
(Room Temp) . . . . . . . . . . . . . . . . . 1MV/V Typ
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/µs Min
• High CMRR/PSRR (Full Temp) . . . . . . . . . . . . . 80dB Min
• High Output Drive Capability (Full Temp). . . . . . . . . 25mA
Applications
• High Quality Audio Preamplifiers
• High Q Active Filters
• Low Noise Function Generators
• Low Distortion Oscillators
• Low Noise Comparators
Pinouts
BAL
-IN
+IN
HA7-5101/883 (CERDIP)
TOP VIEW
1
2
3
4
V-
Ordering Information
TEMP.
PART NUMBER
HA7-5101/883 -55 to 125 8 Ld CerDIP F8.3A
5962-89636012A -55 to 125 20 Ld Ceramic LCC J20.A
8NC
NC
V+
-
+
7
OUT
6
5
BAL
-IN
NC
+IN
NC
RANGE (°C) PACKAGE
5962-896360 (CLCC)
TOP VIEW
NC
BAL
NC
NC
3212019
4
5
6
7
8
NC
-
+
10 11 12 139
V-
NC
BAL
NC
NC
NC
18
V+
17
NC
16
OUT
15
NC
14
PKG.
DWG. #
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright © Intersil Americas Inc. 1994, 2005. All Rights Reserved
HA-5101/883
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Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . V+ to V-
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Junction Temperature (T
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300°C
). . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
J
Thermal Resistance θ
Ceramic DIP Package . . . . . . . . . . . . . 120 30
Ceramic LCC Package. . . . . . . . . . . . . 86 26
Package Power Dissipation Limit at +75°C for T
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.22W
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.35W
Package Power Dissipation Derating Factor Above +75°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . .12.2mW/°C
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/°C
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C
Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . ±5V to ±15V
1/2 (V+ - V-)
V
INcm
500
R
L
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
PARAMETER SYMBOL TEST CONDITIONS
Input Offset Voltage V
Input Bias Current +I
Input Offset Current I
Common Mode Range +CMR V+ = 3V
Large Signal Voltage Gain +A
Common Mode Rejection Ratio +CMRR ∆V
= ±15V, RS = 100Ω, RL = 500kΩ, V
S
VCM = 0V 1 +25 -3 3 mV
IO
VCM = 0V
B
-I
B
IO
-CMR V+ = 27V
VOL
-A
VOL
-CMRR ∆V
= 100k
+R
S
-RS = 100
VCM = 0V +R
= 100
S
-RS = 100k
VCM = 0V
= 100k
+R
S
-RS = 100k
V- = -27V
V- = -3V
V
= 0V and +10V
OUT
= 2k
R
L
V
= 0V and −10V
OUT
= 2k
R
L
CM
V+ =+5V V- = -25V
= -10V
V
OUT
CM
V+ = +25V V- = -5V
= +10V
V
OUT
= +10V
= -10V
= 0V, Unless Otherwise Specified
OUT
GROUP A
SUBGROUP TEMP (°C)
2, 3 +125, -55 -4 4 mV
1 +25 -200 200 nA
2, 3 +125, -55 -325 325 nA
1 +25 -200 200 nA
2, 3 +125, -55 -325 325 nA
1+25-7575nA
2, 3 +125, -55 -125 125 nA
1 +25 12 - V
2, 3 +125, -55 12 - V
1 +25 - -12 V
2, 3 +125, -55 - -12 V
4 +25 100 - kV/V
5, 6 +125, -55 100 - kV/V
4 +25 100 - kV/V
5, 6 +125, -55 100 - kV/V
1 +25 80 - dB
2, 3 +125, -55 80 - dB
1 +25 80 - dB
2, 3 +125, -55 80 - dB
(°C/W) θJC (°C/W)
JA
+175°C
J
LIMITS
UNITSMIN MAX
2
FN3931.1
August 17, 2005
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
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Device Tested at: V
= ±15V, RS = 100Ω, RL = 500kΩ, V
S
PARAMETER SYMBOL TEST CONDITIONS
Output Voltage Swing +V
Output Current +I
OUT1RL
-V
OUT1RL
+V
OUT2VS
-V
OUT2VS
OUT
-I
OUT
R
R
V V
V V
Quiescent Power Supply Current +I
-I
CC
CC
V I
OUT
V I
OUT
Power Supply Rejection Ratio +PSRR ∆V
V+ = +10V, V- = -15V V+ = +20V, V- = -15V
-PSRR ∆V
V+ = +15V, V- = -10V V+ = +15V, V- = -20V
Offset Voltage Adjustment +V
Adj Note 4
IO
R A
Adj 1 +25 VIO+1 - mV
-V
IO
HA-5101/883
= 0V, Unless Otherwise Specified
OUT
GROUP A
SUBGROUP TEMP (°C)
= 2k 1 +25 12 - V
2, 3 +125, -55 12 - V
= 2k 1 +25 - -12 V
2, 3 +125, -55 - -12 V
= ±18V = 600
L
= ±18V = 600
L
= -15V
OUT
= ±18V
S
= +15V
OUT
= ±18V
S
= 0V
OUT
= 0mA
= 0V
OUT
= 0mA
= 10V
S
1 +25 15 - V
2, 3 +125, -55 15 - V
1 +25 - -15 V
2, 3 +125, -55 - -15 V
1 +25 25 - mA
2, 3 +125, -55 25 - mA
1 +25 - -25 mA
2, 3 +125, -55 - -25 mA
1+25-6mA
2, 3 +125, -55 - 6 mA
1+25-6-mA
2, 3 +125, -55 -6 - mA
1 +25 80 - dB
2, 3 +125, -55 80 - dB
= 10V
S
1 +25 80 - dB
2, 3 +125, -55 80 - dB
1+25V
= 2kΩ, CL = 50pF
L
= +1V/V
V
2, 3 +125, -55 V
2, 3 +125, -55 V
LIMITS
-1 - mV
IO
-1 - mV
IO
+1 - mV
IO
UNITSMIN MAX
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
= ±15V, RS = 50Ω, RL = 2kΩ, CL = 50pF, A
S
= +1V/V, Unless Otherwise Specified
VCL
GROUP A
PARAMETER SYMBOL TEST CONDITIONS
Slew Rate +SR V
-SR V
Rise and Fall Time t
R
t
F
Overshoot +OS V
= -3V to +3V 4+256-V/µs
OUT
= +3V to -3V 4+256-V/µs
OUT
V
= 0V to +200mV
OUT
10% ≤ t
V 10% ≤ t
90%
R
= 0V to -200mV
OUT
90%
F
= 0V to +200mV 4+25-35%
OUT
SUBGROUP TEMP (°C)
4 +25 - 200 ns
5, 6 +125, -55 - 400 ns
4 +25 - 200 ns
5, 6 +125, -55 - 400 ns
5, 6 +125, -55 - 35 %
-OS V
= 0V to -200mV 4+25-35%
OUT
5, 6 +125, -55 - 35 %
3
LIMITS
UNITSMIN MAX
FN3931.1
August 17, 2005
HA-5101/883
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Device Characterized at: V
PARAMETER SYMBOL TEST CONDITIONS NOTES TEMP (°C)
Differential Input Resistance R
Low Frequency Peak-to-Peak Noise E
Input Noise Voltage Density E
Input Noise Current Density I Unity Gain Bandwidth UGBW VO = 100mV 1 +25 10 - MHz Full Power Bandwidth FPBW V
Minimum Closed Loop Stable Gain CLSG 1 -55 to +125 +1 - V/V
Output Resistance R
Quiescent Power Consumption PC V
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation.
2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πV
3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
4. Offset adjustment range is [V
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
IN
nP-P
n
OUT
IO (Measured)
= ±15V, RL = 2kΩ, CL = 50pF, AV = +1, Unless Otherwise Specified
S
VCM = 0V 1 +25 250 - k
0.1Hz to 10Hz 1+25-0.2µV RS = 20Ω, fo = 1000Hz 1 +25 - 4.5 nV/Hz
n
RS = 2MΩ, fo = 1000Hz 1 +25 - 3 pA/Hz
= 10V 1, 2 +25 95 - kHz
PEAK
Open Loop 1 +25 - 150
= 0V, I
OUT
±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V.
= 0mA 1, 3 -55 to +125 - 180 mW
OUT
PEAK
LIMITS
UNITSMIN MAX
).
P-P
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 & 2)
Interim Electrical Parameters (Pre Burn-in) 1
Final Electrical Test Parameters 1*, 2, 3, 4, 5, 6
Group A Test Requirements 1, 2, 3, 4, 5, 6
Groups C & D Endpoints 1
*PDA applies to Subgroup 1 only.
4
FN3931.1
August 17, 2005
HA-5101/883
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t
R
5
t
F
t
R
t
F
FN3931.1
August 17, 2005
Burn-in Circuits
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HA-5101/883
CERAMIC MINI-DIP
1
2
3
V-
D2C2R
4
1
-
+
CERAMIC LCC
8
7
6
5
C
C
3
1
V+
D
1
NOTES:
= 1MΩ, ±5%, 1/4W (Min)
R
1
C
= C2 = 0.01µF/Socket (Min) or 0.1µF/Row, (Min)
1
= 0.01µF/Socket, 10%
C
3
= D2 = 1N4002 or Equivalent/Board
D
1
(V+) - (V-) = 30V
6
FN3931.1
August 17, 2005
Schematic
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HA-5101/883
-IN D
D
2
1
+IN
V+
R
19A
R
R
36
Q
36
22
Q
22
Q
19B
R
24
Q
24
R
35
R
37
Q
37
Q
35
Q
21
R
20
Q
20
Q
R
19A
R
25
19B
R
23
Q
23
Q
25
Q
L41
Q
45
Q
L2
Q2AQ2BQ
10
R
10
Q
Q33Q
Q
12
46
32
R
12
Q
31
Q
Q
3
27
R
27
Q
44
Q
41
Q
Q
11
R
11
BAL
30
R
3A
3.65K
R
38
830
R
26
Q
26
Q
R
34
Q
43
Q
29
Q
38
L1
Q
1B
Q
1A
R
60
Q
47
Q
C
Q
5
Q
9
Q
34
R
4A
Q
3.65K
39
R
4B
830
Q
6
Q
4
Q
Q
Q
49
50
Q
1
7
C
2
R
58
Q
Q
48
51
R
28
Q
28
Q
16
Q
Q
14
15
8
R
15
OUTPUT
8
Q
42
Q
8
R
13
18
17A
Q
17
R
18
V-
BAL
7
FN3931.1
August 17, 2005
Die Characteristics
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DIE DIMENSIONS
70 X 70 X 19 mils ±1mil 1790 x 1780 x 483µm ±25.4µm
METALLIZATION
Type: AI, 1% Cu Thickness: 16k
GLASSIVATION
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12k Nitride Thickness: 3.5kÅ ±1.5kÅ
WORST CASE CURRENT DENSITY:
1.38 x 105A/cm
SUBSTRATE POTENTIAL (Powered Up): V­TRANSISTOR COUNT: 54 PROCESS: Bipolar Dielectric Isolation
Å ±2kÅ
Å ±2kÅ
2
Metallization Mask Layout
BAL NC
HA-5101/883
HA-5101/883
-IN
+IN
V+
OUT
BALV-
8
FN3931.1
August 17, 2005
HA-5101/883
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1
LEAD FINISH
-A-
-B-
bbb C A - B
S
BASE
PLANE
SEATING
PLANE
S1
b2
b
ccc C A - BMD
D
A
A
e
S
S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass overrun.
6. Dimension Q shall be measured from the seating plane to the base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
-D-
BASE
E
D
S
S
Q
A
-C-
L
METAL
b1
M
(b)
SECTION A-A
α
(c)
M
eA
eA/2
aaa CA - B
M
c
D
S
S
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES MILLIMETERS
SYMBOL
A-0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3
D-0.405 - 10.29 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 -7
o
α
90
105
o
90
o
105
aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M-0.0015 - 0.038 2, 3
N8 88
NOTESMIN MAX MIN MAX
o
Rev. 0 4/94
-
9
FN3931.1
August 17, 2005
HA-5101/883
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Ceramic Leadless Chip Carrier Packages (CLCC)
j x 45
E1
o
B
h x 45
-E-
E2
e1
o
A
-F-
0.010 EHS S
L
D
D3
0.007 EFM S HS
B1
L2
D1
-H-
D2
B2
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.060 0.100 1.52 2.54 6, 7
A1 0.050 0.088 1.27 2.23 -
B-----
B1 0.022 0.028 0.56 0.71 2, 4
E
E3
S
0.010 EF
A1
PLANE 2
PLANE 1
e
L3
B3
L1
S
B2 0.072 REF 1.83 REF ­B3 0.006 0.022 0.15 0.56 -
D 0.342 0.358 8.69 9.09 -
D1 0.200 BSC 5.08 BSC ­D2 0.100 BSC 2.54 BSC ­D3 - 0.358 - 9.09 2
E 0.342 0.358 8.69 9.09 -
E1 0.200 BSC 5.08 BSC ­E2 0.100 BSC 2.54 BSC ­E3 - 0.358 - 9.09 2
e 0.050 BSC 1.27 BSC -
e1 0.015 - 0.38 -2
h 0.040 REF 1.02 REF 5
j 0.020 REF 0.51 REF 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1.40 ­L2 0.075 0.095 1.91 2.41 ­L3 0.003 0.015 0.08 0.38 -
ND 5 5 3
NE 5 5 3
N20 203
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic layers.
7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
NOTESMIN MAX MIN MAX
Rev. 0 5/18/94
10
FN3931.1
August 17, 2005
®
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HA-5101
DESIGN INFORMATION
Data Sheet August 17, 2005 FN3931.1
The information contained on the following pages has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves Unless Otherwise Specified: V
8
7
Hz)
6
5
4
3
2
INPUT NOISE VOLTAGE (nV/
1
0
10 100 1K 10K 100K
VOLTAGE
CURRENT
FREQUENCY (Hz)
FIGURE 1. NOISE SPECTRUM
Hz)
INPUT NOISE CURRENT (pA/
= ±15V, TA = +25°C
S
1500
V)
µ
1000
500
OFFSET VOLTAGE (
0
TEMPERATURE (°C)
FIGURE 2. OFFSET VOLTAGE vs TEMPERATURE
1251007550250-25-50
= 25,000, VS = ±15V (12.89mV
A
A
= 25,000, VS = ±15V (0.09nV
V
PEAK-TO-PEAK NOISE 0.1Hz TO 10Hz
P-P
RTI)
V
PEAK-TO-PEAK TOTAL NOISE 0.1Hz TO 1MHz
11
RTO or 0.52µV
P-P
P-P
RTI)
SLEW
RATE
(NORMALIZED)
HA-5101
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Typical Performance Curves Unless Otherwise Specified: V
20
0
-20
-40
INPUT OFFSET CURRENT (nA)
-60
-55 -25 0 25 50 75 100 125
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE
30
20
10
0
-10
OFFSET CHANGE (µV)
-20
= ±15V, TA = +25°C (Continued)
S
250
200
150
100
BIAS CURRENT (nA)
50
0
-55 -25 0 25 50 75 100 125
TEMPERATURE (°C)
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
5
MAXIMUM
4
3
2
SUPPLY CURRENT (mA)
1
TYPICAL
MINIMUM
-30
TIME (s)
400350300250200150100500
FIGURE 5. INPUT OFFSET WARMUP DRIFT vs TIME
450 500
0
SUPPLY VOLTAGE (±V)
181614121086420
FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE
20
(NORMALIZED TO ZERO FINAL VALUE) (SIX REPRESENTATIVE UNITS)
1.1
RISE TIME
1.0
SLEW RATE
0.9
0.8
0.7
RL = 2K, CL = 50pF
0.6
-60 -40 0 20 60 80 100 120
TEMPERATURE (°C)
FIGURE 7. SLEW RATE/RISE TIME vs TEMPERATURE FIGURE 8. SHORT CIRCUIT CURRENT vs TIME
40-20
1.1
1.0
0.9
0.8
0.7
0.6
RISE TIME (NORMALIZED)
60
D
50
B
40
30
20
OUTPUT CURRENT (mA)
A+15mV ±15V B-15mV ±15V
10
C+15mV 0V D -15mV 0V
0
C
A
V
V
IN
OUT
160140120100806040200
TIME (s)
12
FN3931.1
August 17, 2005
HA-5101
www.BDTIC.com/Intersil
Typical Performance Curves Unless Otherwise Specified: V
10M
(140)
1M
(120)
100K (100)
OPEN LOOP VOLTAGE GAIN V/V(dB)
10K (80)
SUPPLY VOLTAGE (±V)
FIGURE 9. DC OPEN-LOOP VOLTAGE GAIN vs SUPPLY
VO LTAGE
6
3
0
-3
-6
-9
-12
PHASE
AV = 1V/V
CLOSED LOOP VOLTAGE GAIN (dB)
= 2K, CL = 50pF
R
L
FREQUENCY (Hz)
FIGURE 11. CLOSED LOOP GAIN AND PHASE AT HIGH AND
LOW TEMPERATURES
125°C
1510 185
125°C
GAIN
10M1M100K10K
-55°C GAIN
-55°C PHASE
100M
0
-45
-90
-135
-180
-225
PHASE SHIFT (DEGREES)
= ±15V, TA = +25°C (Continued)
S
V
ERROR
1mV
2.65µs
TIME (1.5µs/DIV)
FIGURE 10. SETTLING WAVEFORM
40
30
20
10
GAIN (dB)
0
-10
-20
RL = 2K, CL = 50pF
AV = 100
AV = 10
AV = 1
10M1M100K10K
FREQUENCY (Hz)
FIGURE 12. CLOSED-LOOP VOLTAGE GAIN vs FREQUENCY
AT DIFFERENT CLOSED LOOP GAINS
100M
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FN3931.1
August 17, 2005
HA-5101
www.BDTIC.com/Intersil
Typical Performance Curves Unless Otherwise Specified: V
140
120
100
80
GAIN
FREQUENCY (Hz)
0
45
90
PHASE SHIFT (DEGREES)
135
180
100M
10M1M100K10K1K10010
VOLTAGE GAIN (dB)
60
40
20
0
PHASE
= ±15V, TA = +25°C (Continued)
S
-40
-60
-80
-100
REJECTION RATIO (dB)
-120
100 1K 10K 100K 1M
FREQUENCY (Hz)
-PSRR/CMRR
+PSRR
FIGURE 13. OPEN-LOOP GAIN/PHASE vs FREQUENCY FIGURE 14. REJECTION RATIOS vs FREQUENCY
VIN = V Timescale = 500ns/Div., Scale: Input = 5V/Div, Output = 2V/Div
= ±3V, AV = +1, RL = 2kΩ, CL = 50pF
OUT
FIGURE 15. SLEW RATE WAVEFORM
Rise Time and Overshoot
VIN = V Timescale = 20ns/Div.
= 0V to +200mV, AV = +1, RL = 2K, CL = 50pF
OUT
FIGURE 16. SMALL SIGNAL WAVEFORM
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FN3931.1
August 17, 2005
HA-5101
www.BDTIC.com/Intersil
Applications Information
Operation At ±5V Supply
The HA-5101 performs well at VS = ±5V exhibiting typical characteristics as listed below:
ICC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV
V
IO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56nA
I
BIAS
A
(VO = ±3V). . . . . . . . . . . . . . . . . . 106kV/V
VOL
. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7V
V
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13mA
I
OUT
CMRR (∆V PSRR (∆V
Unity Gain Bandwidth . . . . . . . . . . . . . . 10MHz
Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . 7V/µs
Input Protection
The HA-5101 has built-in back-to-back protection diodes which will limit the differential input voltage to approximately 7V. If the HA-5101 will be used in conditions where that volt­age may be exceeded, then current limiting resistors must be used. No more than 25mA should be allowed to flow in the HA-5101’s input.
Output Saturation
When an op amp is overdriven, output devices can saturate and sometimes take a long time to recover. Saturation can be avoided (sometimes) by using circuits such as:
= ±2.5V) . . . . . . . . . . . . . 90dB
CM
= 0.5V). . . . . . . . . . . . . . . 90dB
CC
V+
R
1
Offset Adjustment
The following is the recommended VIO adjust configuration:
+15V
7
3
+
2
-
4
(NOTE)
-15V
NOTE: Proper decoupling is always recommended, 0.1µF high quality capacitor should be at or very near the device’s supply pins.
(NOTE)
5
1
R
P
RP = 100k
6
Comparator Circuit
V+
7
-
+
4
V-
VINMAX 7V()
---------------------------------------------- -
25m A
6
2R
LIM
V
IN
Choose R
R
LIM
R
LIM
Such That:
LIM
2
3
R
2
+
-
R
3
V
SOURCE
R
4
V-
If saturation cannot be avoided the HA-5101 recovers from a 25% overdrive in about 6.5µs (see photo).
IN
OUT
Output is overdriven negative and recovers in 6µs.
Bottom: Output, 5V/Div., 2µs/Div.
Top: Input
15
FN3931.1
August 17, 2005
HA-5101
www.BDTIC.com/Intersil
TABLE 1. TYPICAL PERFORMANCE CHARACTERISTICS
Device Characterized At: V
PARAMETER TEST CONDITIONS TEMP (°C) TYP DESIGN LIMITS UNITS
Offset Voltage V
Offset Voltage Average Drift Versus Temperature -55 to +125 3 7 µV/°C
Offset Current Average Drift Versus Temperature -55 to +125 100 250 pA/°C
Input Bias Current V
Input Offset Current V
Differential Input Resistance VCM = 0V +25 500 Table 3 k Input Noise Voltage Density f
Input Noise Current Density fo = 10Hz +25 6 20 pA/Hz
Large Signal Voltage Gain V
Slew Rate V
Full Power Bandwidth V Rise and Fall Times V Overshoot V Settling Time To 0.1% for 10V Step +25 4.5 6 µs
Output Short Circuit Current t < 10s, V
Output Resistance Open Loop +25 110 Table 3
Supply Current No Load +25 4.3 Table 1 mA Minimum Supply Voltage Functional Operation Only,
= ±15V, RL = 2kΩ, CL = 50pF, A
S
= 0V +25 0.8 Table 1 mV
CM
= 0V +25 65 Table 1 nA
CM
= 0V +25 35 Table 1 nA
CM
= 10Hz +25 5.4 9 nV/Hz
o
fo = 100Hz +25 3.4 5.5 nV/Hz fo = 1kHz +25 3.2 Table 3 nV/Hz
fo = 100Hz +25 1.5 5 pA/Hz fo = 1kHz +25 0.52 Table 3 pA/Hz
= ±10V -55 400K Table 1 V/V
OUT
= ±3V -55 to +125 10 5.4 V/µs
OUT
= 10V, (Note 2) -55 to +125 159 85 kHz
PEAK
= ±200mV -55 to +125 50 Table 2 ns
OUT
= ±200mV -55 to +125 20 35 %
OUT
To 0.01% for 10V Step +25 6 10 µs
= ±15V +25 ±35 ±50 mA
OUT
Other Parameters Will Vary
= +1V/V, Unless Otherwise Specified
VCL
+25 1M Table 1 V/V
+125 1M Table 1 V/V
+25 ±4 ±5 V
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN3931.1
August 17, 2005
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