The HA-5101/883 is a dielectrically isolated operational
amplifier featuring low noise and high performance. This
amplifier has an excellent noise voltage density of
4.5nV/√Hz
HA-5101/883 yields a 10MHz unity gain bandwidth and a
6V/µs slew rate.
DC characteristics of the HA-5101/883 assure accurate
performance. The 3mV (max) offset voltage is externally
adjustable and offset voltage drift is just 3µV/°C. Low bias
currents (200nA max) reduce input current errors and the
high open loop voltage gain of 100kV/V, over temperature,
increases the loop gain for low distortion amplification.
The HA-5101/883 is ideal for audio applications, especially
low-level signal amplifiers such as microphone, tape head
and preamplifiers. Additionally, it is well suited for low
distortion oscillators, low noise function generators and high
Q filters.
(max) at 1kHz. The unity gain stable
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
= ±15V, RS = 50Ω, RL = 2kΩ, CL = 50pF, A
S
= +1V/V, Unless Otherwise Specified
VCL
GROUP A
PARAMETERSYMBOLTEST CONDITIONS
Slew Rate+SRV
-SRV
Rise and Fall Timet
R
t
F
Overshoot+OSV
= -3V to +3V4+256-V/µs
OUT
= +3V to -3V4+256-V/µs
OUT
V
= 0V to +200mV
OUT
10% ≤ t
V
10% ≤ t
≤ 90%
R
= 0V to -200mV
OUT
≤ 90%
F
= 0V to +200mV4+25-35%
OUT
SUBGROUP TEMP (°C)
4+25-200ns
5, 6+125, -55-400ns
4+25-200ns
5, 6+125, -55-400ns
5, 6+125, -55-35%
-OSV
= 0V to -200mV4+25-35%
OUT
5, 6+125, -55-35%
3
LIMITS
UNITSMINMAX
FN3931.1
August 17, 2005
HA-5101/883
www.BDTIC.com/Intersil
Device Characterized at: V
PARAMETERSYMBOLTEST CONDITIONSNOTESTEMP (°C)
Differential Input ResistanceR
Low Frequency Peak-to-Peak NoiseE
Input Noise Voltage DensityE
Input Noise Current DensityI
Unity Gain BandwidthUGBWVO = 100mV1+2510-MHz
Full Power BandwidthFPBWV
Minimum Closed Loop Stable GainCLSG1-55 to +125+1-V/V
Output ResistanceR
Quiescent Power ConsumptionPCV
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πV
3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
1. Index area: A notch or a pin one identification mark shall be
located adjacent to pin one and shall be located within the
shaded area shown. The manufacturer’s identification shall not
be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
-D-
BASE
E
D
S
S
Q
A
-C-
L
METAL
b1
M
(b)
SECTION A-A
α
(c)
M
eA
eA/2
aaaCA - B
M
c
D
S
S
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The
maximum “A” dimension is package height before being solder
dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
NOTESMINMAXMINMAX
Rev. 0 5/18/94
10
FN3931.1
August 17, 2005
®
www.BDTIC.com/Intersil
HA-5101
DESIGN INFORMATION
Data SheetAugust 17, 2005FN3931.1
The information contained on the following pages has been developed through characterization by Intersil Semiconductor and is
for use as application and design information only. No guarantee is implied.
Typical Performance Curves Unless Otherwise Specified: V
8
7
Hz)
√
6
5
4
3
2
INPUT NOISE VOLTAGE (nV/
1
0
101001K10K100K
VOLTAGE
CURRENT
FREQUENCY (Hz)
FIGURE 1. NOISE SPECTRUM
Hz)
√
INPUT NOISE CURRENT (pA/
= ±15V, TA = +25°C
S
1500
V)
µ
1000
500
OFFSET VOLTAGE (
0
TEMPERATURE (°C)
FIGURE 2. OFFSET VOLTAGE vs TEMPERATURE
1251007550250-25-50
= 25,000, VS = ±15V (12.89mV
A
A
= 25,000, VS = ±15V (0.09nV
V
PEAK-TO-PEAK NOISE 0.1Hz TO 10Hz
P-P
RTI)
V
PEAK-TO-PEAK TOTAL NOISE 0.1Hz TO 1MHz
11
RTO or 0.52µV
P-P
P-P
RTI)
SLEW
RATE
(NORMALIZED)
HA-5101
www.BDTIC.com/Intersil
Typical Performance Curves Unless Otherwise Specified: V
20
0
-20
-40
INPUT OFFSET CURRENT (nA)
-60
-55-250255075100125
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE
30
20
10
0
-10
OFFSET CHANGE (µV)
-20
= ±15V, TA = +25°C (Continued)
S
250
200
150
100
BIAS CURRENT (nA)
50
0
-55-250255075100125
TEMPERATURE (°C)
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
5
MAXIMUM
4
3
2
SUPPLY CURRENT (mA)
1
TYPICAL
MINIMUM
-30
TIME (s)
400350300250200150100500
FIGURE 5. INPUT OFFSET WARMUP DRIFT vs TIME
450 500
0
SUPPLY VOLTAGE (±V)
181614121086420
FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE
20
(NORMALIZED TO ZERO FINAL VALUE)
(SIX REPRESENTATIVE UNITS)
1.1
RISE TIME
1.0
SLEW RATE
0.9
0.8
0.7
RL = 2K, CL = 50pF
0.6
-60 -400206080 100 120
TEMPERATURE (°C)
FIGURE 7. SLEW RATE/RISE TIME vs TEMPERATUREFIGURE 8. SHORT CIRCUIT CURRENT vs TIME
40-20
1.1
1.0
0.9
0.8
0.7
0.6
RISE TIME (NORMALIZED)
60
D
50
B
40
30
20
OUTPUT CURRENT (mA)
A+15mV ±15V
B-15mV ±15V
10
C+15mV 0V
D-15mV0V
0
C
A
V
V
IN
OUT
160140120100806040200
TIME (s)
12
FN3931.1
August 17, 2005
HA-5101
www.BDTIC.com/Intersil
Typical Performance Curves Unless Otherwise Specified: V
10M
(140)
1M
(120)
100K
(100)
OPEN LOOP VOLTAGE GAIN V/V(dB)
10K
(80)
SUPPLY VOLTAGE (±V)
FIGURE 9. DC OPEN-LOOP VOLTAGE GAIN vs SUPPLY
VO LTAGE
6
3
0
-3
-6
-9
-12
PHASE
AV = 1V/V
CLOSED LOOP VOLTAGE GAIN (dB)
= 2K, CL = 50pF
R
L
FREQUENCY (Hz)
FIGURE 11. CLOSED LOOP GAIN AND PHASE AT HIGH AND
LOW TEMPERATURES
125°C
1510185
125°C
GAIN
10M1M100K10K
-55°C
GAIN
-55°C
PHASE
100M
0
-45
-90
-135
-180
-225
PHASE SHIFT (DEGREES)
= ±15V, TA = +25°C (Continued)
S
V
ERROR
1mV
2.65µs
TIME (1.5µs/DIV)
FIGURE 10. SETTLING WAVEFORM
40
30
20
10
GAIN (dB)
0
-10
-20
RL = 2K, CL = 50pF
AV = 100
AV = 10
AV = 1
10M1M100K10K
FREQUENCY (Hz)
FIGURE 12. CLOSED-LOOP VOLTAGE GAIN vs FREQUENCY
AT DIFFERENT CLOSED LOOP GAINS
100M
13
FN3931.1
August 17, 2005
HA-5101
www.BDTIC.com/Intersil
Typical Performance Curves Unless Otherwise Specified: V
140
120
100
80
GAIN
FREQUENCY (Hz)
0
45
90
PHASE SHIFT (DEGREES)
135
180
100M
10M1M100K10K1K10010
VOLTAGE GAIN (dB)
60
40
20
0
PHASE
= ±15V, TA = +25°C (Continued)
S
-40
-60
-80
-100
REJECTION RATIO (dB)
-120
1001K10K100K1M
FREQUENCY (Hz)
-PSRR/CMRR
+PSRR
FIGURE 13. OPEN-LOOP GAIN/PHASE vs FREQUENCYFIGURE 14. REJECTION RATIOS vs FREQUENCY
The HA-5101 has built-in back-to-back protection diodes
which will limit the differential input voltage to approximately
7V. If the HA-5101 will be used in conditions where that voltage may be exceeded, then current limiting resistors must
be used. No more than 25mA should be allowed to flow in
the HA-5101’s input.
Output Saturation
When an op amp is overdriven, output devices can saturate
and sometimes take a long time to recover. Saturation can
be avoided (sometimes) by using circuits such as:
= ±2.5V) . . . . . . . . . . . . . 90dB
CM
= 0.5V). . . . . . . . . . . . . . . 90dB
CC
V+
R
1
Offset Adjustment
The following is the recommended VIO adjust configuration:
+15V
7
3
+
2
-
4
(NOTE)
-15V
NOTE: Proper decoupling is always recommended, 0.1µF high quality
capacitor should be at or very near the device’s supply pins.
(NOTE)
5
1
R
P
RP = 100kΩ
6
Comparator Circuit
V+
7
-
+
4
V-
∆VINMAX 7V–()
---------------------------------------------- -
25m A
6
≤
2R
LIM
∆V
IN
Choose R
R
LIM
R
LIM
Such That:
LIM
2
3
R
2
+
-
R
3
V
SOURCE
R
4
V-
If saturation cannot be avoided the HA-5101 recovers from a
25% overdrive in about 6.5µs (see photo).
IN
OUT
Output is overdriven negative and recovers in 6µs.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN3931.1
August 17, 2005
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