查询IRU1030供应商
Data Sheet No. PD94124
IRU1030
3A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURES
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
APPLICATIONS
Low Voltage Processor Applications such as:
P54C, P55C, Cyrix M2,
POWER PC, AMD
GTL+ Termination
PENTIUM PRO, KLAMATH
Low Voltage Memory Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
DESCRIPTION
The IRU1030 is a low dropout three-terminal adjustable
regulator with minimum of 3A output current capability.
This product is specifically designed to provide well regulated supply for low voltage IC applications such as
Pentium P54C, P55C as well as GTL+ termination for Pentium Pro and Klamath processor appli-
cations. The IRU1030 is also well suited for other processors such as Cyrix, AMD and Power PC appli-
cations. The IRU1030 is guaranteed to have <1.3V dropout at full load current making it ideal to provide well
regulated outputs of 2.5V to 3.3V with 4.75V to 7V input
supply.
C1
1500uF
V
IN
3
V
OUT
Adj
2
R1
121
1
R2
200
IRU1030
Figure 1 - Typical Application of IRU1030 in a 5V to 3.3V regulator.
Notes: Pentium P54C, P55C, Klamath, Pentium Pro, VRE are trademarks of Intel Corp.Cyrix M2 is trademark of Cyrix Corp.
Power PC is trademark of IBM Corp.
3.3V / 3A
C2
1500uF
PACKAGE ORDER INFORMATION
TJ (°C) 2-PIN PLASTIC 3-PIN PLASTIC 3-PIN PLASTIC
TO-252 (D-Pak) TO-263 (M) TO-220 (T)
0 To 150 IRU1030CD IRU1030CM IRU1030CT
Rev. 1.3
08/20/02
www.irf.com
1
IRU1030
ABSOLUTE MAXIMUM RATINGS
Input Voltage (V IN) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range ..................... 0°C To 150°C
PACKAGE INFORMATION
2-PIN PLASTIC TO-252 (D-Pak ) 3-PIN PLASTIC TO-263 (M) 3-PIN PLASTIC TO-220 (T)
Tab is
V
OUT
1.238
1.225
3.1
60
FRONT VIEW
1.250
1.250
1.1
5
0.01
70
55
0.2
0.5
0.3
0.003
3
2
1
1.262
1.275
0.2
0.4
1.3
10
0.02
120
5
1
V
IN
V
OUT
Adj
V
%
%
V
A
mA
%/W
dB
mA
mA
%
%
%VO
Tab is
V
OUT
FRONT VIEW
3
V
IN
1
Adj
Tab is
V
OUT
FRONT VIEW
3
V
IN
2
V
OUT
1
Adj
θJA=70°C/W for 0.5" Square pad θJA=35°C/W for 1" Square pad θJT=2.7°C/W θJA=60°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over CIN=1mF, COUT=10mF, and TJ=0 to 1508C.
Typical values refer to TJ=258C.
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Reference Voltage
Line Regulation
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
Minimum Load Current (Note 3)
Thermal Regulation
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Temperature Stability
Long Term Stability
RMS Output Noise
VREF
DVO
Io=10mA, TJ=258C, (V IN-Vo)=1.5V
Io=10mA, (V IN-Vo)=1.5V
Io=10mA, 1.3V<(V IN-Vo)<7V
VIN=3.3V, VADJ=0, 10mA<Io<3A
Note 2, Io=3A
VIN=3.3V, DVo=100mV
VIN=3.3V, VADJ=0V
30ms Pulse, VIN-Vo=3V, Io=3A
f=120Hz, Co=25mF Tantalum,
Io=1.5A, VIN-Vo=3V
Io=10mA, VIN-Vo=1.5V, TJ=258C,
IADJ
Io=10mA, VIN-Vo=1.5V
Io=10mA, VIN-Vo=1.5V, TJ=258C
VIN=3.3V, VADJ=0V, Io=10mA
TJ=1258C, 1000Hrs
TJ=258C, 10Hz<f<10KHz
Note 1: Low duty cycle pulse testing with Kelvin connections is required in order to maintain accurate data.
Note 2: Dropout voltage is defined as the minimum differential voltage between VIN and VOUT required to maintain regulation at VOUT. It is measured when the output
voltage drops 1% below its nominal value.
2
www.irf.com
Note 3: Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor
dividers are selected such that this current is automatically maintained.
Rev. 1.3
08/20/02
PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1
Adj
A resistor divider from VOUT to Adj pin to ground sets the output voltage.
IRU1030
2
3
VOUT
VIN
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
to ground to insure stability.
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than VOUT
in order for the device to regulate properly.
BLOCK DIAGRAM
VIN 3
CURRENT
LIMIT
2 VOUT
+
+
1.25V
THERMAL
SHUTDOWN
Figure 2 - Simplified block diagram of the IRU1030.
APPLICATION INFORMATION
Introduction
The IRU1030 adjustable Low Dropout (LDO) regulator is
a three-terminal device which can easily be programmed
with the addition of two external resistors to any voltages within the range of 1.25 to 5.5V. This regulator unlike the first generation of the three-terminal regulators
such as LM117 that required 3V differential between the
input and the regulated output, only needs 1.3V differential to maintain output regulation. This is a key requirement for today’s microprocessors that need typically
3.3V supply and are often generated from the 5V supply. Another major requirement of these microprocessors such as the Intel P54C is the need to switch the
load current from zero to several amps in tens of nano-
1 Adj
seconds at the processor pins, which translates to an
approximately 300 to 500ns current step at the regulator. In addition, the output voltage tolerances are also
extremely tight and they include the transient response
as part of the specification. For example Intel VRE
specification calls for a total of ±100mV including initial
tolerance, load regulation and 0 to 4.6A load step.
The IRU1030 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage, reducing the overall system cost with the
need for fewer output capacitors.
Rev. 1.3
08/20/02
www.irf.com
3
IRU1030
Output Voltage Setting
The IRU1030 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
VOUT = VREF3 1+ +IADJ3R2
R2
( )
R1
Where:
VREF = 1.25V Typically
IADJ = 50mA Typically
R1 and R2 as shown in Figure 3:
VIN
VIN
IRU1030
Adj
VOUT
IADJ = 50uA
VREF
R1
R2
VOUT
Figure 3 - Typical application of the IRU1030
for programming the output voltage.
The IRU1030 keeps a constant 1.25V between the output pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, adding to the IADJ current and into the R2 resistor producing
a voltage equal to the (1.25/R1)3R2 + IADJ3R2 which
will be added to the 1.25V to set the output voltage.
This is summarized in the above equation. Since the
minimum load current requirement of the IRU1030 is
10mA, R1 is typically selected to be 121V resistor so
that it automatically satisfies the minimum current requirement. Notice that since IADJ is typically in the range
of 50mA it only adds a small error to the output voltage
and should only be considered when a very precise output voltage setting is required. For example, in a typical
3.3V application where R1=121V and R2=200V the error due to IADJ is only 0.3% of the nominal set point.
Load Regulation
Since the IRU1030 is only a three-terminal device, it is
not possible to provide true remote sensing of the output
voltage at the load. Figure 4 shows that the best load
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the VOUT pin of the
regulator and not to the load. In fact, if R1 is connected
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+R2/
R1), or the effective resistance will be RP(eff)=RP3(1+R2/
R1). It is important to note that for high current applications, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to minimize this effect.
PARASITIC LINE
RESISTANCE
R
V
V
V
IN
IN
IRU1030
Adj
OUT
P
R
R1
R2
L
Figure 4 - Schematic showing connection
for best load regulation.
Stability
The IRU1030 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor applications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100mV and an output
capacitance of 500 to 1000mF. Fortunately as the capacitance increases, the ESR decreases resulting in a
fixed RC time constant. The IRU1030 takes advantage
of this phenomena in making the overall regulator loop
stable. For most applications a minimum of 100mF aluminum electrolytic capacitor such as Sanyo MVGX series, Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
Thermal Design
The IRU1030 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction temperatures in the range of 1508C, it is recommended that the
selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. The example below
shows the steps in selecting the proper regulator heat
sink for the GTL+ terminator using a separate regulator
for each end.
4
www.irf.com
Rev. 1.3
08/20/02
IRU1030
Assuming the following specifications:
VIN = 3.3V
VOUT = 1.5V
IOUT(MAX) = 2.7A
TA = 358C
The steps for selecting a proper heat sink to keep the
junction temperature below 135°C is given as:
1) Calculate the maximum power dissipation using:
PD = IOUT3(VIN - VOUT)
PD = 2.73(3.3 - 1.5) = 4.86W
2) Select a package from the regulator data sheet and
record its junction to case (or tab) thermal resistance.
Selecting TO-220 package gives us:
uJC = 2.78C/W
3) Assuming that the heat sink is black anodized, cal-
culate the maximum heat sink temperature allowed:
Assume, ucs=0.05°C/W (heat-sink-to-case thermal
resistance for black anodized)
TS = TJ - PD3(uJC + uCS)
TS = 135 - 4.863(2.7 + 0.05) = 121.78C
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal resistance (uSA) is calculated by first calculating the
temperature rise above the ambient as follows:
DT = TS - TA = 121.7 - 35 = 86.78C
∆T=Temperature Rise Above Ambient
DTPD86.7
uSA = = = 17.88C/W
5) Next, a heat sink with lower uSA than the one calcu-
lated in step 4 must be selected. One way to do this
is to simply look at the graphs of the “Heat Sink Temp
Rise Above the Ambient” vs. the “Power Dissipation”
and select a heat sink that results in lower temperature rise than the one calculated in the previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
4.86
Air Flow (LFM)
0 100 200 300
Thermalloy 6109PB 6110PB 7141 7178
AAVID 575002 507302 576802B 577102
Note: For further information regarding the above companies and their latest product offerings and application
support contact your local representative or the numbers listed below:
AAVID................PH# (603) 528 3400
Thermalloy..........PH# (214) 243-4321
Designing for Microprocessor Applications
As it was mentioned before the IRU1030 is designed
specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V
supply. These processors demand a fast regulator that
supports their large load current changes. The worst case
current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from “Stop
Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the order of 15 to 20ns, however the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
frequency low ESR and low ESL output capacitors is
imperative in the design of these regulator circuits.
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instantaneous drop equal to the (∆VESR=ESR3∆I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (∆VESL
=L3∆I/∆t). The output capacitance effect is a droop in
the output voltage proportional to the time it takes for the
regulator to respond to the change in the current,
(∆Vc=∆t3∆I/C) where ∆t is the response time of the
regulator.
Rev. 1.3
08/20/02
www.irf.com
5
IRU1030
V
ESR
V
ESL
LOAD
CURRENT
T
1030plt1-1.0
LOAD CURRENT RISE TIME
V
C
Figure 5 - Typical regulator response to
the fast load current step.
An example of a regulator design to meet the Intel
Pentium Pro GTL+ specification is given below.
Assume the specification for the processor as shown in
Table 1:
Type of VOUT IMAX Max Allowed
Processor Nominal Output Tolerance
Pentium Pro 1.50 V 2.7 A ±150 mV
Table 1 - GTL+ Specification for Pentium Pro
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR:
1) Assuming the regulator’s initial accuracy plus the resistor divider tolerance is ≈ ±30mV (±2% of 1.5V nomi-
nal), then the total step allowed for the ESR and the
ESL, is −120 mV.
Assuming that the ESL drop is −10mV, the remain-
ing ESR step will be −110mV. Therefore the output
capacitor ESR must be:
ESR [ = 40mV
110
2.7
The Sanyo MVGX series is a good choice to achieve
both price and performance goals. The 6MV1500GX,
1500mF, 6.3V has an ESR of less than 36mV typ.
Selecting a single capacitor achieves our design goal.
2) With the output capacitance being 1500mF:
DVc = = = 3.6mV
Dt 3 DIC2 3 2.7
1500
Where:
Dt = 2ms is the regulator response time
To set the output DC voltage, we need to select R1 and
R2:
3) Assuming R1 = 121V, 0.5%:
VOUT
R2 = 3R1 = 3121 = 24.2V
( )
VREF
-1
1.5
1.25
-1
( )
Select R2 = 24.3V, 0.5%
Selecting both R1 and R2 resistors to be 0.5% toler-
ance, results in the least amount of error introduced
by the resistor dividers leaving ≈ ±1.3% error budget
for the IRU1030 reference which is within the initial
accuracy of the device.
Finally, the input capacitor is selected as follows:
4) Assuming that the input voltage can drop 150mV be-
fore the main power supply responds, and that the
main power supply response time is ≈ 50ms, then
the minimum input capacitance for a 2.7A load step
is given by:
2.7 3 50
CIN = = 900mF
0.15
The ESR should be less than:
ESR =
(VIN - VOUT - DV - VDROP)
DI
Where:
VDROP L Input voltage drop allowed in step 4
DV L Maximum regulator dropout voltage
DI L Load current step
ESR = = 0.16V
(3.3 - 1.5 - 1.2 - 0.15)
2.7
The next step is to calculate the drop due to the capacitance discharge and make sure that this drop in
voltage is less than the selected ESL drop in the
previous step.
6
Selecting a single 1500mF the same type as the output
capacitors exceeds our requirements. However, the same
input capacitor can also support the second regulator
for the other end of termination.
www.irf.com
Rev. 1.3
08/20/02
IRU1030
Figure 6 shows the completed schematic for our example.
3.3V
1500uF
C1
IRU1030
Adj
VOUTVIN
R1
121
0.5%
R2
24.3
0.5%
R3
150
0.5%
R4
75
0.5%
1.5V
C2
1500uF
V
REF
Figure 6 - Final schematic for half of the
GTL+ termination regulator.
Layout Consideration
The output capacitors must be located as close to the
VOUT terminal of the device as possible. It is recommended to use a section of a layer of the PC board as a
plane to connect the VOUT pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
Rev. 1.3
08/20/02
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
www.irf.com
7
IRU1030
(D) TO-252 Package
2-Pin
R
K
O
S
MIN
6.477
5.004
0.686
7.417
9.703
0.635
2.286 BSC
4.521
&1.52
2.184
0.762
1.016
5.969
1.016
0
0.534
R0.31 TYP
R0.51 TYP
0.428
L
M
N
P
MAX
6.731
5.207
0.838
8.179
10.084
0.889
4.623
&1.62
2.388
0.864
1.118
6.223
1.118
0.102
0.686
0.588
A
BC
7
45
8
D
E
F
G
H
C
L
J
R1
8
Q
SYMBOL
A
B
C
D
E
F
G
H
J
K
L
M
N
O
P
Q
R
R1
S
8
www.irf.com
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
(M) TO-263 Package
3-Pin
IRU1030
A
K
S
B
H
GD
C
C
L
E
V
M
L
P
N
R
U
SYMBOL
A
B
C
D
E
G
H
K
L
M
N
P
R
S
U
V
MIN
10.05
8.28
4.31
0.66
1.14
2.54 REF
14.73
1.40
0.00
2.49
0.33
2.286
08
2.41
6.50 REF
7.75 REF
MAX
10.312
8.763
4.572
0.91
1.40
15.75
1.68
0.254
2.74
0.58
2.794
88
2.67
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
www.irf.com
9
IRU1030
e
e1
e3
(T) TO-220 Package
3-Pin
H1
L
b1
Q
C
E
L
C1
J1
b
R
SYMBOL
A
a
b
b1
C1
CP
D
E
e
e1
e3
F
H1
J1
L
Q
R
E-PIN CP
a (5x)
D
MIN
4.06
0.63
1.14
0.38
3.71D
14.22
9.78
2.29
4.83
1.14
1.14
5.94
2.29
13.716
2.62
5.588
38
MAX
4.83
7.58
1.02
1.52
0.56
3.96D
15.062
10.54
2.79
5.33
1.40
1.40
6.55
2.92
14.22
2.87
6.17
A
C
F
L
10
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
www.irf.com
Rev. 1.3
08/20/02
PACKAGE SHIPMENT METHOD
IRU1030
PKG
DESIG
D
M
T
PACKAGE
DESCRIPTION
TO-252, (D-Pak)
TO-263
TO-220
1 1 1 111
Feed Direction
Figure A
PIN
COUNT
2
3
3
PARTS
PER TUBE
75
50
50
PARTS
PER REEL
2500
750
---
Feed Direction
FigureB
T & R
Orientation
Fig A
Fig B
---
Rev. 1.3
08/20/02
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
www.irf.com
11
Loading...