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Data Sheet No. PD94128
IRU1075
7.5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURES
1V Dropout at Full Load Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
APPLICATIONS
Low Voltage Processor Applications such as:
P54C,P55C, Cyrix M2,
POWER PC, AMD
GTL+ Termination
PENTIUM PRO, KLAMATH
Low Voltage Memory Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
DESCRIPTION
The IRU1075 is a low dropout three-terminal adjustable
regulator with minimum of 7.5A output current capability. This product is specifically designed to provide well
regulated supply for low voltage IC applications such as
Pentium P54C, P55C as well as GTL+ termination for Pentium Pro and Klamath processor appli-
cations. The IRU1075 is also well suited for other pro-
cessors such as Cyrix, AMD and Power PC appli-
cations. The IRU1075 is guaranteed to have <1.2V dropout at full load current making it ideal to provide well
regulated outputs such as 3.3V with input supply voltage as low as 4.5V minimum.
C1
1500uF
Vin
3
Vou t
Adj
2
1
R1
121
R2
200
IRU1075
1075app1-1.0
Typical application of IRU1075 in a 5V to 3.3V regulator
Notes: Pentium P54C, P55C, Klamath, Pentium Pro, VRE are trademarks of Intel Corp. Cyrix M2 is trademark of Cyrix Corp.
Power PC is trademark of IBM Corp.
3.3V
C2
2x 1500uF
PACKAGE ORDER INFORMATION
Tj (°C) 3-PIN PLASTIC 3-PIN PLASTIC 3-PIN PLASTIC
TO-220 (T) TO-263 (M) Ultra Thin-Pak (P)
0 To 150 IRU1075CT IRU1075CM IRU1075CP
Rev. 1.1
06/29/01
1
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IRU1075
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range ..................... 0°C To 150°C
PACKAGE INFORMATION
3-PIN PLASTIC TO-220 (T) 3-PIN PLASTIC TO-263 (M) 3-PIN PLASTIC ULTRA THIN-PAK (P)
FRONT VIEW
Tab is
Vou t
3
2
1
Vin
Vou t
Adj
Tab is
θJT=2.7°C/W θJA=60°C/W θJA=35°C/W for 1" Square pad θJA=35°C/W for 1" Square pad
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Cin=1µF, Cout=10µF, and Tj=0 to 150!C.
Typical values refer to Tj=25!C.
Vou t
FRONT VIEW
FRONT VIEW
3
Vin
2
Vou t
1
Adj
Tab is
Vou t
3
Vin
2
Vou t
1
Adj
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Reference Voltage Vref Io=10mA, Tj=25!C, (Vin-Vo)=1.5V 1.238 1.250 1.262 V
Io=10mA, (Vin-Vo)=1.5V 1.225 1.250 1.275
Line Regulation Io=10mA, 1.3V<(Vin-Vo)<7V 0.2 %
Load Regulation (Note 1) Vin=3.3V, Vadj=0, 10mA<Io<7.5A 0.4 %
Dropout Voltage Io=7.5A 1.0 1.2 V
(Note 2) ∆Vo Io=4A 0.92 1.1
Current Limit Vin=3.3V, dVo=100mV 7.6 9 A
Minimum Load Current Vin=3.3V, Vadj=0V 5 10 mA
(Note 3)
Thermal Regulation 30ms Pulse, Vin-Vo=3V, Io=7.5A 0.02 %/W
Ripple Rejection f=120Hz, Co=25µF Tantalum,
Io=7.5A, Vin-Vo=3V 60 70 dB
Adjust Pin Current Iadj Io=10mA, Vin-Vo=1.5V, Tj=25!C,
Io=10mA, Vin-Vo=1.5V 55 120 µA
Adjust Pin Current Change Io=10mA, Vin-Vo=1.5V, Tj=25!C 0.2 5 µA
Temperature Stability Vin=3.3V, Vadj=0V, Io=10mA 0.5 %
Long Term Stability Tj=125!C, 1000Hrs 0.3 %
RMS Output Noise Tj=25!C, 10Hz<f<10KHz 0.003 %V
Note 1: Low duty cycle pulse testing with Kelvin connections is required in order to maintain accurate data.
Note 3: Minimum load current is defined as the minimum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
Note 2: Dropout voltage is defined as the minimum differential voltage between Vin and Vout required to main-
dividers are selected such that it automatically main-
tains this current.
tain regulation at Vout. It is measured when the output
voltage drops 1% below its nominal value.
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PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1
Adj
A resistor divider from this pin to the Vout pin and ground sets the output voltage.
IRU1075
2
3
Vout
Vin
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
to ground to insure stability.
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than Vout
in order for the device to regulate properly.
BLOCK DIAGRAM
Vin 3
CURRENT
LIMIT
2 Vout
+
1.25V
+
THERMAL
SHUTDOWN
Figure 2 - Simplified block diagram of the IRU1075
APPLICATION INFORMATION
Introduction
The IRU1075 adjustable Low Dropout (LDO) regulator
is a three-terminal device which can easily be programmed with the addition of two external resistors to
any voltages within the range of 1.25 to 5.5 V. This regulator unlike the first generation of the three-terminal regulators such as LM117 that required 3V differential between the input and the regulated output, only needs
1.3V differential to maintain output regulation. This is a
key requirement for today’s microprocessors that need
typically 3.3V supply and are often generated from the
5V supply. Another major requirement of these micro-
processors such as the Intel P54C is the need to switch
the load current from zero to several amps in tens of
1075blk1-1.0
nanoseconds at the processor pins, which translates to
an approximately 300 to 500ns current step at the regulator. In addition, the output voltage tolerances are also
extremely tight and they include the transient response
as part of the specification. For example Intel VRE
specification calls for a total of ±100mV including initial
tolerance, load regulation and 0 to 4.6A load step.
The IRU1075 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage, reducing the overall system cost with the
need for fewer output capacitors.
1 Adj
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IRU1075
Output Voltage Setting
The IRU1075 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
R2
VOUT = VREF ×
oo
o1 +
oo
Where:
VREF = 1.25V Typically
IADJ = 50µA Typically
R1 and R2 as shown in figure 3:
Vin
IRU1075
pp
p + IADJ × R2
pp
R1
VoutVin
Vout
regulator and the load is gained up by the factor of (1+R2/
R1), or the effective resistance will be, Rp(eff)=Rp*(1+R2/
R1). It is important to note that for high current applica-
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
PARASITIC LINE
RESISTANCE
Rp
Vin
Vou tVin
IRU1075
Adj
R1
R
L
Adj
IAdj = 50uA
Vref
R1
R2
1075app2-1.0
Figure 3 - Typical application of the IRU1075
for programming the output voltage
The IRU1075 keeps a constant 1.25V between the output pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, adding to the Iadj current and into the R2 resistor producing
a voltage equal to the (1.25/R1)*R2 + Iadj*R2 which will
be added to the 1.25V to set the output voltage. This is
summarized in the above equation. Since the minimum
load current requirement of the IRU1075 is 10mA, R1 is
typically selected to be 121Ω resistor so that it automatically satisfies the minimum current requirement.
Notice that since Iadj is typically in the range of 50µA it
only adds a small error to the output voltage and should
only be considered when a very precise output voltage
setting is required. For example, in a typical 3.3V application where R1=121Ω and R2=200Ω the error due to
Iadj is only 0.3% of the nominal set point.
Load Regulation
Since the IRU1075 is only a three-terminal device, it is
not possible to provide true remote sensing of the output
voltage at the load. Figure 4 shows that the best load
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the Vout pin of the
regulator and not to the load. In fact, if R1 is connected
to the load side, the effective resistance between the
R2
1075app3-1.0
Figure 4 - Schematic showing connection
for best load regulation
Stability
The IRU1075 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor ap-
plications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100 mΩ and an output
capacitance of 500 to 1000µF. Fortunately as the ca-
pacitance increases, the ESR decreases resulting in a
fixed RC time constant. The IRU1075 takes advantage
of this phenomena in making the overall regulator loop
stable. For most applications a minimum of 100µF alu-
minum electrolytic capacitor such as Sanyo MVGX se-
ries, Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
Thermal Design
The IRU1075 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 150!C, it is recommended that the
selected heat sink be chosen such that during maxi-
mum continuous load operation the junction tempera-
ture is kept below this number. The example below
shows the steps in selecting the proper regulator heat
sink for the worst case current consumption using Intel
200MHz microprocessor as the load.
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IRU1075
Assuming the following specifications:
VIN = 5V
VOUT = 3.5V
IOUT(MAX) = 4.6A
TA = 35!C
The steps for selecting a proper heat sink to keep the
junction temperature below 135°C is given as:
1) Calculate the maximum power dissipation using:
PD = IOUT × (VIN - VOUT)
PD = 4.6 × (5 - 3.5) = 6.9W
2) Select a package from the regulator data sheet and
record its junction to case (or tab) thermal resistance.
Selecting TO-220 package gives us:
θJC = 2.7!C/W
3) Assuming that the heat sink is black anodized, calculate the maximum heat sink temperature allowed:
Assume, θcs = 0.05°C/W (heat-sink-to-case ther-
mal resistance for black anodized)
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal re-
sistance (θ
SA) is calculated by first calculating the
temperature rise above the ambient as follows:
S - TA = 116 - 35 = 81!C
∆T = T
∆T = Temperature Rise Above Ambient
∆T
θSA = = = 11.7!C/W
81
P
D
6.9
5) Next, a heat sink with lower θsa than the one calcu-
lated in Step 4 must be selected. One way to do this
is to simply look at the graphs of the “Heat Sink Temp
Rise Above the Ambient” vs. the “Power Dissipation”
and select a heat sink that results in lower temperature rise than the one calculated in previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Air Flow (LFM)
0 100 200 300 400
Thermalloy 6021PB 6021PB 6073PB 6109PB 7141D
AAVID 534202B 534202B 507302 575002 576802B
TS = TJ - PD × (θJC + θCS)
TS = 135 - 6.9 × (2.7 + 0.05) = 116!C
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IRU1075 Notes
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IR WORLD HEADQUARTERS : 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 02/01
Rev. 1.1
06/29/01
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