• Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage dV/dt immune
• Application-specific gate drive range:
Motor Drive: 12 V to 20 V (IRS2127/IRS2128)
Automotive: 9 V to 20 V (IRS21271/IRS21281)
• Undervoltage lockout
• 3.3 V, 5 V, and 15 V input logic compatible
IO+/-200 mA / 420 mA
V
V
OFFSET
12 V - 20V 9 V - 20 V
OUT
600 V max.
(IRS2127/IR2128) (IRS21271/IR21281)
• FAULT lead indicates shutdown has occured
• Output in phase with input (IRS2127/IRS21271)
V
CSth
250 mV or 1.8 V
• Output out of phase with input (IRS2128/IRS21281)
• RoHS compliant
t
on/off
(typ.)150 ns & 150 ns
Description
The IRS2127/IRS2128/IRS21271/IRS21281 are
high voltage, high speed power MOSFET and IGBT
drivers. Proprietary HVIC and latch immune CMOS
technologies enable ruggedized monolithic construction. The logic input is compatible with standard
CMOS or LSTTL outputs, down to 3.3 V. The protection circuity detects over-current in the driven power
transistor and terminates the gate drive voltage. An
open drain
FAULT
signal is provided to indicate that
an over-current shutdown has occurred. The output
driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side or low-side configuration which
operates up to 600 V.
Packages
8-Lead PDIP8-Lead SOIC
Typical Connection
V
CC
IN
FAULT
(Refer to Lead Assignments for correct pin configuration).
These diagrams show electrical connections only. Please
refer to our Application Notes and DesignTips for proper
circuit board layout.
www.irf.com1
V
CC
IN
FAULT
COM
HO
V
B
CS
V
S
IRS2127/IRS21271
FAULT
V
CC
IN
V
CC
IN
FAULT
COM
HO
V
B
CS
V
S
IRS2128/IRS21281
IRS212(7, 71, 8, 81)(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
SymbolDefinitionMin.Max.Units
V
B
V
S
V
HO
V
CC
V
IN
V
FLT
V
CS
dVs/dtAllowable offset supply voltage transient—50V/ns
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15 V differential.