Datasheet IRLZ34N Datasheet (Philips)

Page 1

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N Logic level TrenchMOS

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT level field-effectpowertransistorina plastic envelope using ’trench’V technology.Thedevicefeatures very I low on-state resistance and has P integral zener diodes giving ESD T protectionupto 2kV. Itis intended for R useinswitchedmodepowersupplies resistance VGS = 10 V and general purpose switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 gate 2 drain 3 source

transistor

tot j

DS(ON)

Drain-source voltage 55 V Drain current (DC) 30 A Total power dissipation 68 W Junction temperature 175 ˚C Drain-source on-state 35 mΩ

tab

tab drain

123

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DSS

DGR

Drain-source voltage Tj = 25 ˚C to 175˚C - 55 V Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -55V Gate-source voltage - ± 13 V Continuous drain current Tmb = 25 ˚C - 30 A

Tmb = 100 ˚C - 21 A

Tj, T

Pulsed drain current Tmb = 25 ˚C - 110 A Total power dissipation Tmb = 25 ˚C - 68 W Operating junction and - 55 175 ˚C

stg

storage temperature

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R R

th j-mb

th j-a

Thermal resistance junction - 2.2 K/W to mounting base Thermal resistance junction 60 - K/W to ambient

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

February 1999 1 Rev 1.000

Electrostatic discharge Human body model (100 pF, 1.5 kΩ)-2kV capacitor voltage, all pins

Page 2

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N

Logic level TrenchMOS

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(BR)DSS

(BR)GSS

GS(TO)

DS(ON)

GSS

DSS

g(tot)

d on

d off

iss

oss

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V voltage Tj = -55˚C 50 - - V Gate-source breakdown IG = ±1 mA; 10 - - V voltage Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V

Drain-source on-state VGS = 5 V; ID = 17 A - 28 46 mΩ resistance VGS = 10 V; ID = 17 A - 26 35 mΩ

Forward transconductance VDS = 25 V; ID = 15 A 12 40 - S Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA

Zero gate voltage drain VDS = 55 V; VGS = 0 V; - 0.05 10 µA current Tj = 175˚C - - 500 µA

Total gate charge ID = 30 A; V Gate-source charge - 6 - nC Gate-drain (Miller) charge - 11 - nC

Turn-on delay time VDD = 30 V; ID = 25 A; - 14 21 ns Turn-on rise time VGS = 5 V; RG = 10 Ω - 77 110 ns Turn-off delay time Resistive load - 55 80 ns Turn-off fall time - 48 65 ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

Internal source inductance Measured from source lead to source - 7.5 - nH

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 1400 pF Output capacitance - 205 245 pF Feedback capacitance - 113 150 pF

transistor

(SOT78 package only) bond pad

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

Tj = 175˚C - - 74 mΩ

Tj = 175˚C - - 20 µA

= 44 V; VGS = 5 V - 22.5 - nC

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

February 1999 2 Rev 1.000

Continuous source current - - 30 A (body diode) Pulsed source current (body - - 110 A diode) Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 34 A; VGS = 0 V - 1.0 - V

Reverse recovery time IF = 34 A; -dIF/dt = 100 A/µs; - 40 - ns Reverse recovery charge VGS = -10 V; VR = 30 V - 0.16 - µC

Page 3

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N

Logic level TrenchMOS

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DSS

Drain-source non-repetitive ID = 20 A; VDD ≤ 25 V; VGS = 5 V; - 45 mJ unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C energy

PD%

120 110 100

90 80 70 60 50 40 30 20 10

0 20 40 60 80 100 120 140 160 180

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

transistor

Normalised Power Derating

= f(Tmb)

D 25 ˚C

1000

ID/A

100

1 10 100

RDS(ON) = VDS/ID

VDS/V

tp = 1 us

10us

100 us

1 ms 10ms

100ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

ID%

120 110 100

90 80 70 60 50 40 30 20 10

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

ZTH/ (K/W)

0.5

0.2

0.1

0.05

0.1

0.02

0.01

1.0E-06 0.0001 0.01 1 100

t/s

Fig.4. Transient thermal impedance.

= f(t); parameter D = tp/T

th j-mb

D =

February 1999 3 Rev 1.000

Page 4

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N Logic level TrenchMOS

Drain current, ID (A)

100

0246810

Fig.5. Typical output characteristics, Tj = 25 ˚C

RDS(ON)/mOhm

VGS/V =

Drain-source voltage, VDS (V)

ID = f(VDS); parameter V

transistor

VGS = 6.0 V

4.2

4.4

5.6

5.0

4.6

4.0

3.6

3.0

Transconductance, gfs (S)

0 10203040506070

Fig.8. Typical transconductance, Tj = 25 ˚C

Drain current, ID (A)

gfs = f(ID); conditions: VDS = 25 V

2.5

BUK959-60

Rds(on) normlised to 25degC

0 102030405060

ID/A

4.6

4.8 5

Fig.6. Typical on-state resistance, Tj = 25 ˚C

= f(ID); parameter V

DS(ON)

ID/A

Tj/C = 175 25

01234567

VGS/V

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

1.5

0.5

-100 -50 0 50 100 150 200

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

VGS(TO) / V

2.5 max.

typ.

1.5

min.

0.5

-100 -50 0 50 100 150 200

Tmb / degC

= f(Tj); ID = 17 A; VGS = 5 V

BUK959-60

Tj / C

Fig.10. Gate threshold voltage.

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

February 1999 4 Rev 1.000

Page 5

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N Logic level TrenchMOS

1E-01

1E-02

1E-03

1E-04

1E-05

0 0.5 1 1.5 2 2.5 3

Fig.11. Sub-threshold drain current.

ID = f(V

2.5

2.0

1.5

1.0

Thousands pF

0.5

0.01 0.1 1 10 100

Fig.12. Typical capacitances, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

2% typ

; conditions: Tj = 25 ˚C; VDS = V

GS)

transistor

Sub-Threshold Conduction

98%

VDS/V

, C

iss

oss

rss

Ciss

Coss

Crss

100

IF/A

Tj/C = 175 25

0 0.5 1 1.5

VSDS/V

Fig.14. Typical reverse diode current.

IF = f(V

120 110 100

90 80 70 60 50 40 30 20 10

); conditions: V

SDS

WDSS%

20 40 60 80 100 120 140 160 180

= 0 V; parameter T

Tmb / C

Fig.15. Normalised avalanche energy rating.

% = f(Tmb); conditions: ID = 20 A

DSS

VGS/V

0 5 10 15 20 25

VDS = 14V

VDS = 44V

QG/nC

Fig.13. Typical turn-on gate-charge characteristics.

= f(QG); conditions: ID = 30 A; parameter V

VDS

VGS

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

= 0.5 ⋅LI

DSS

⋅BV

DSS

/(BV

R 01

shunt

DSS−VDD

VDD

-ID/100

)

February 1999 5 Rev 1.000

Page 6

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N

Logic level TrenchMOS

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78

transistor

(1)

123

max.

3.0

(1)

3.8

3.0

3.6

2.7

EUROPEAN

PROJECTION

2.6

2.2

ISSUE DATE

97-06-11

DIMENSIONS (mm are the original dimensions)

UNIT

Note

1. Terminals in this zone are not tinned.

OUTLINE VERSION

SOT78 TO-220

4.5

1.39

4.1

1.27

0.9

0.7

IEC JEDEC EIAJ

0.7

1.3

0.4

1.0

0 5 10 mm

15.8

6.4

15.2

5.9

REFERENCES

scale

10.3

9.7

2.54

15.0

13.5

3.30

2.79

Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

February 1999 6 Rev 1.000

Page 7

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N

Logic level TrenchMOS

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.

transistor

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

February 1999 7 Rev 1.000