Intel Corporation VQ87C196KD, VQ87C196KC, VA87C196KD, VA87C196KC Datasheet
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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
February 1996COPYRIGHT©INTEL CORPORATION, 1996 Order Number: 271116-005
M87C196KC/M87C196KD
16-BIT HIGH-PERFORMANCE CHMOS
MICROCONTROLLERS WITH ON-CHIP EPROM
Special Environment
M87C196KCÐ16 KBytes EPROM, 512 Bytes RAM
M87C196KDÐ32 KBytes EPROM, 1024 Bytes RAM
Y
M87C196KC: 16 MHz Operation
Y
M87C196KD: 16 and 20 MHz Operation
Y
Register-to-Register Architecture
Y
28 Interrupt Sources/16 Vectors
Y
Peripheral Transaction Server
Y
1.4 ms 16 x 16 Multiply (20 MHz)
Y
1.75 ms 16 x 16 Multiply (16 MHz)
Y
2.4 ms 32/16 Divide (20 MHz)
Y
3.0 ms 32/16 Divide (16 MHz)
Y
Powerdown and Idle Modes
Y
Five 8-Bit I/O Ports
Y
16-Bit Watchdog Timer
Y
Available in 68-Lead PGA and 68-Lead
Ceramic Quad Flatpack Packages
Y
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y
Full Duplex Serial Port
Y
High Speed I/O Subsystem
Y
16-Bit Timer
Y
16-Bit Up/Down Counter with Capture
Y
3 Pulse-Width-Modulated Outputs
Y
Four 16-Bit Software Timers
Y
8- or 10-Bit A/D Converter with
Sample/Hold
Y
HOLD/HLDA Bus Protocol
Y
Product Grades
Ð SE1 (QML):
b
55§Ctoa125§C
Ð SE2 (QML):
b
40§Ctoa125§C
(M87C196KD only)
The M87C196KC/KD 16-bit microcontroller is a high performance member of the MCSÉ-96 microcontroller
family. The M87C196KC/KD is an enhanced M80C196KB device with on-chip RAM and EPROM. Intel’s
CHMOS III-E process provides a high performance processor along with low power consumption.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
For bus design information, configuration, and programming, please see the 8XC196KC/8XC196KD User’s
Manual (order
Ý
272238).
MCSÉ-96 is a registered trademark of Intel Corporation.
M87C196KC/M87C196KD
271116– 1
Figure 1. M87C196KC/KD Block Diagram
PACKAGING
PGA CQFP Signal
1 9 ACH7/P0.7
2 8 ACH6/P0.6
3 7 ACH2/P0.2
4 6 ACH0/P0.0
5 5 ACH1/P0.1
6 4 ACH3/P0.3
7 3 NMI
82EA
91V
CC
10 68 V
SS
11 67 XTAL1
12 66 XTAL2
13 65 CLKOUT
14 64 BUSWIDTH
15 63 INST
16 62 ALE/ADV
17 61 RD
18 60 AD0/P3.0
19 59 AD1/P3.1
20 58 AD2/P3.2
21 57 AD3/P3.3
22 56 AD4/P3.4
23 55 AD5/P3.5
PGA CQFP Signal
24 54 AD6/P3.6
25 53 AD7/P3.7
26 52 AD8/P4.0
27 51 AD9/P4.1
28 50 AD10/P4.2
29 49 AD11/P4.3
30 48 AD12/P4.4
31 47 AD13/P4.5
32 46 AD14/P4.6
33 45 AD15/P4.7
34 44 T2CLK/P2.3
35 43 READY
36 42 T2RST/P2.4/AINC
37 41 BHE/WRH
38 40 WR/WRL
39 39 PWM0/P2.5
40 38 T2CAPTURE/P2.7/PACT
41 37 V
PP
42 36 V
SS
43 35 HS0.3
44 34 HS0.2
45 33 T2UP-DN/P2.6
46 32 P1.7/HOLD
PGA CQFP Signal
47 31 P1.6/HLDA
48 30 P1.5/BREQ
49 29 HSO.1
50 28 HSO.0
51 27 HSO.5/HSI.3
52 26 HSO.4/HSI.2
53 25 HSI.1
54 24 HSI.0
55 23 P1.4/PWM2
56 22 P1.3/PWM1
57 21 P1.2
58 20 P1.1
59 19 P1.0
60 18 TXD/P2.0
61 17 RXD/P2.1
62 16 RESET
63 15 EXTINT/P2.2
64 14 V
SS
65 13 V
REF
66 12 ANGND
67 11 ACH4/P0.4
68 10 ACH5/P0.5
Figure 2. Pin Definitions
2
M87C196KC/M87C196KD
PACKAGING
The M87C196KC/KD is available in a ceramic pin grid array, shown in Figure 3, and a leaded ceramic quad
pack shown in Figure 4.
271116– 33
Figure 3. 68-Pin Grid Array Pinout
3
M87C196KC/M87C196KD
271116– 2
Figure 4. 68-Pin Ceramic Quad Flatpack
4
M87C196KC/M87C196KD
PIN DESCRIPTIONS
Symbol Name and Function
V
CC
Main supply voltage (5V).
V
SS
Digital circuit ground (0V). There are three VSSpins, all of which must be connected.
V
REF
Reference voltage for the A/D converter (5V). V
REF
is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as
V
SS
.
V
PP
Timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to
V
SS
anda1MXresistor to VCC. If this function is not used VPPmay be tied to VCC. This pin
is the programming voltage on the EPROM device.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency.
RESET Reset input to the chip.
BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM. EA equal to
a TTL-low causes accesses to those locations to be directed to off-chip memory.
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV
, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
RD Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL
will go low only for external writes where an even byte is
being written. WR
/WRL is activated only during external memory writes.
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE
e
0 selects the bank of memory that is connected to the high byte of the data bus. A0e0
selects the bank of memory that is connected to the low byte of the data bus. Thus
accesses to a 16-bit wide memory can be to the low byte only (A0
e
0, BHEe1), to the
high byte only (A0e1, BHEe0), or both bytes (A0e0, BHEe0). If the WRH function is
selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE
/WRH
is valid only during 16-bit external memory write cycles.
5
M87C196KC/M87C196KD
PIN DESCRIPTIONS (Continued)
Symbol Name and Function
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1 8-bit quasi-bidirectional I/O port.
Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the M87C196KC.
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD Bus Hold input requesting control of the bus.
HLDA Bus Hold acknowledge output indicating release of the bus.
BREQ Bus Request output activated when the bus controller has a pending external memory
cycle.
6
M87C196KC/M87C196KD
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings*
Case Temperature
Under Bias ААААААААААААААААА
b
55§Ctoa125§C
Storage Temperature ААААААААААb65§Ctoa150§C
Voltage On Any Pin to VSSААААААААb0.5V toa7.0V
Power DissipationАААААААААААААААААААААААААА1.5W
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
OPERATING CONDITIONS
Symbol Description Min Max Units
TC(SE1) Case Temperature (Instant On)
b
55
a
125
§
C
TC(SE2) Case Temperature (Instant On)
b
40
a
125
§
C
V
CC
Digital Supply Voltage 4.50 5.50 V
V
REF
Analog Supply Voltage 4.50 5.50 V
F
OSC
Oscillator Frequency 3.5 16 MHz
F
OSC
Oscillator Frequency (M87C196KD-20 only) 3.5 20 MHz
NOTE:
ANGND and V
SS
should be nominally at the same potential.
DC Characteristics (Over Specified Operating Conditions)
Symbol Description Min Max Units Test Conditions
V
IL
Input Low Voltage
b
0.5 0.8 V
V
IH
Input High Voltage (Note 1) 0.2 V
CC
a
1.0 V
CC
V
V
IH1
Input High Voltage on XTAL 1, EA 0.7 V
CC
V
CC
V
V
IH2
Input High Voltage on RESET 2.32 V
CC
V
V
OL
Output Low Voltage 0.3 V I
OL
e
200 mA
0.45 V I
OL
e
2.8 mA
1.5 V I
OL
e
7mA
V
OL1
Output Low Voltage
0.8 V
I
OL
ea
0.4 mA
in RESET on P2.5 (Note 2)
NOTES:
1. All pins except RESET, XTAL1 and EA.
2. Violating these specifications in Reset may cause the part to enter test modes.
7
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