USB930HxADBD
Adapter Board
User’s Manual
April 1997
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth-
erwise, to any intellectua l proper ty rights is grante d by this docum ent. Exce pt as prov ided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
*Third-party brands and names are the property of their respective owners.
Copies of d ocuments whi ch have a n or deri ng nu mber a nd are re ference d i n this doc umen t, or o ther Inte l lite ratur e, ma y be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
Copyright © IN TEL CORPO RATION, 1996 , 1997
CONTENTS
CONTENTS
1.0 INTRODUCTION.......... .... ........... .... .. ............. .. .. ............. .. ............. .. .. ............. .. .. ............. 1
2.0 INSTALLATION ................................................................................................................ 1
2.1 Installi ng the Adapter Board .................................... ............................................ ........ .1
2.2 Installing the new EPROM ...........................................................................................4
3.0 BOARD LAYOUT.............................................................................................................. 5
4.0 FEATURES....................................................................................................................... 5
4.1 CPU Foot Print .............................................................................................................5
4.2 External Clock Oscillator/Crystal ..................................................................................5
4.3 Test Points ...................................................................................................................6
4.4 Jumpers .......................................................................................................................6
4.5 Evaluation Board Interface ...........................................................................................6
4.6 S e ria l C o m m u n ic a tio n s . ....... ... ....... .. ........ .. ....... ... ....... ... ....... .. ... ....... .. ........ .. ....... ... .....6
4.6.1 Using the External Serial Port .................................................................................7
4.6.2 Using the Internal Serial Port ..................................................................................7
5.0 8X930XX ADAPTER BOARD SCHEMATICS .................................................................. 7
FIGURES
8X930 MICROCONTROLLER LOCATION ...................................................................................2
ADAPTER BOARD ORIENTATION ..............................................................................................3
EPROM ORIENTATION ...............................................................................................................4
ADAPTER BOARD LAYOUT ........................................................................................................5
i
1.0 INTRODUCTION
This manual describes how to connect the USB930HxADBD daughte r card to the 8x 930 F amily
USB Evaluation Board Rev B. The 8x930Hx chip supports one upstream USB port and four
downstream USB ports.
NOTE
Due to pin incompatibilities, this daughter card can be used with the four-port
8x930 Family USB Evaluation Board Rev B only.
2.0 INSTALLATION
2.1 Installing the Adapter Board
1. Remove the 8x930Ax device inst alled on the 8x930 Fa mi ly USB Evaluation Board Rev B
from the U3 socket prior to installing the adapter board. Refer to Figure 1 for the location
of socket U3
2. Place the adapter on the evaluation board, ensuring that the connectors are properly
aligned, and press the adapter onto the evaluation board until the connectors are fully
engaged. Refer to Figure 2 for the correct orientation for the adapter board.
1
USB930HXADBD ADAPTER BOARD USER’S GUIDE
U18
S3
RESET
INT
RP5
JW19
SOF
JW20
INT1
U13U12U11
RP3
S1
S2
U14
RP4
U15
TP10
JW22
1
JW23
U17
UART
49 50
INT0
JW21
U6U5
REMOVE
Page
JW15
U8
JW14
Non-Page
U7
JW16
39
microcontroller
JW17
U9
TP9
39
40
Serial I/O
40
Y1
U10
TP7
JW18
GND
in socket U3
TP8
U16
TP11
GND
J1J2
I/O Expansion
JW8
P5V
Socket Justify
PLL2 PLL1 PLL0 Data Freq
2-3 2-3 1-2 3 MHz
1-2 2-3 2-3 6 MHz1.5
1-2 1-2 2-3 12 MHz12
1
JW10
(PLL2)
JW11
(PLL1)
JW12
(PLL0)
1
JW13
+5V
GND
P9
A12
*
U3
1.5
GND
JW9
TP5
21
20
P10
TP4
TP
TP
TP6
A12
1
2
1
2
P7
JW6 JW5
Full
1
2
RP1
RP2
JW3
P5
P12V
U1
SOCKET A
U2
SOCKET B
SRAM Only
P6
TP3
JW7
8x930 Family EVAL BD
REV B
GND TP2
TP
12
DP1
DM1
TP
13
TP
14
DP2
DM2
TP
15
TP
16
DP3
DM3
TP
17
TP
18
DP4
DM4
TP
19
Q1
JW4
U4
TP1
Low
PORT
P8
Port1/5
Port2
Port3
Port4
+
C1
VR1
JW2
UPSTREAM
F1
JW1
Figure 1. 8x930 Mic rocontroller Location
2
A5525-01
USB930HXADBD ADAPTER BOARD USER’S GUIDE
U18
S3
RESET
INT
RP5
INT0
JW21
U6U5
TP8
49 50
Page
U8
JW14
JW15
Non-Page
39
39 40
40
U9
U7
JW16
I/O Expansion
P6
U1
JW8
P5V
Socket Justify
A12
JW9
*
PLL2 PLL1 PLL0 Data Freq
2-3 2-3 1-2 3 MHz
1-2 2-3 2-3 6 MHz1.5
1-2 1-2 2-3 12 MHz12
1.5
U2
U3
A12
JW3
1
1
2
2
1
P5
2
RP1
RP2
P12V
U1
U2
SRAM Only
P6
JW19
SOF
JW20
INT1
U13U12U11
S1
U14
RP4RP3
U15
S2
PLL2 PLL1 PLL0
JW17
1-2 1-2
1-2 2-3 2-3 61.5
TP10
JW22
UART
1
JW23
U17
U16
2-3 1212
TP11
GND
J1J2
2-3 2-3 1-2
31.5
DataFreq
TP9
39
39
40
40
Serial I/O
Y1
U10
TP7
JW18
Y1
GND
1
JW10
(PLL2)
JW11
(PLL1)
JW12
(PLL0)
1
P7
JW13
+5V
GND
P9
GND
TP5
21
20
P10
TP4
TP
TP
10µ
16v
TP6
1
1
P7
2
2
JW6 JW5
JW7
Full
GND TP2
TP
12
SOCKET A
DP1
DM1
TP
13
TP
14
DP2
DM2
TP
15
SOCKET B
TP
16
DP3
DM3
TP
17
TP
18
DP4
DM4
TP
19
Q1
TP3
TP1
Low
P8
8x930 Family EVAL BD
REV B
Port1/5
Port2
Port3
Port4
F1
JW1
+
C1
JW4
U4
VR1
JW2
UPSTREAM
PORT
A5527-01
Figure 2. Adapter Board Orientation
3
USB930HXADBD ADAPTER BOARD USER’S GUIDE
2.2 Installing the new EPROM
If an EPROM is included in the upgrade package, you must use it to replace the EPROM that is
installed in Socket A of the evaluation board. This upgraded EPROM has the same pinout as th e
original, however, it contains new RISM (Reduced Instruction Set Monitor) code. No jumper
changes are requi red.
NOTE
Socket A can accept either a 32K, 64K, or 128K EPROM. Because of this,
when you install the 32K EPROM provided by Inte l there will be four holes
left open by the notch. See Figure 3 for the correct orient ation of the EPROM.
INT
RP5
INT0
JW21
U6U5
49 50
Page
JW14
JW15
I/O Expansion
Non-Page
Leave 4 holes
by notch OPEN
U7
J
JW8
P5V
Socket Justify
A12
*
JW9
A12
1
P5
2
RP1
RP2
P12V
JW3
U1
SOCKET A
U2
SRA
JW19
SOF
JW20
INT1
U11
U13U12
RP3
S1
U14
GND TP2
DP1
DM1
DP2
DM2
SOCKE
TP
12
TP
13
TP
14
TP
15
TP
16
8x930 Family EVAL BD
REV B
Port1/5
Port2
Port3
A5528-01
Figure 3. EPROM Orientation
4
USB930HXADBD ADAPTER BOARD USER’S GUIDE
3.0 BOARD LAYOUT
Figure 4 shows the layout of the board and the major components.
1
2
U2
3"
P6
U1
39 40
Y1
PLL2 PLL1 PLL0 DataFreq
2-3 2-3 1-2 31.5
1-2 2-3 2-3 61.5
1-2 1-2 2-3 1212
3"
Top View
Side View
Interfaces to 82930
USBM Eval Board
Figure 4. Adapter Bo ard Layout
2
1
16v
10µ
P7
40
39
A5526-01
4.0 FEATURES
4.1 CPU Foot Print
The Adapter Board has the foot print for a 68-pin PLCC socket to match the pinout of the
8x930Hx.
4.2 E xternal Clock Osci llator/Cr ystal
The board prov ides spac e for a cryst al and a c apacito r to use the i nternal o scillator of the 8x930Hx
and also contains a clock oscillator that produces an independent external clock source for the
8x930Hx. Only one clo ck sou rce ca n be us ed at a ti me. By defaul t t he clo ck oscil lator i s us ed and
the crystal and capacitor are not populated. To use the internal oscillator, you must cut Jumper
JW1 and inst all the appropr iate crystal and capacitor.
5
USB930HXADBD ADAPTER BOARD USER’S GUIDE
4.3 Test Poi nts
The board contains test points for CLK12MHZ, XTAL2, and AVCC.
4.4 Jumpers
The board cont ains jumper s to allow the 8x93 0Hx device to be reconfigur ed. Three 3- pin jumpers
are used to select the core operating frequency and the USB data rate. Figu re 1 illustr ates jumper
configurations:
Table 1. Jumper Configuration
PLL2 JW4 PLL1 JW3 PLL0 JW2
2-3 2-3 1-2 1.5 Mbps 3 MHz 6 MHz
1-2 2-3 2-3 1.5 Mbps 6 MHz 12 MHz
1-2 1-2 2-3 12 Mbps 12 MHz 12 MHz
USB Data
Rate
Core
Frequency
XTAL1
JW1 allows the clock oscillator to be disconnected from the 8x930Hx so that a crystal can be
used. To install you r own cryst al, you m ust either cut JW1 or r emove the existing c lock oscil lator.
NOTE
When selecting 1.5Mbps with a 3MHz core, a 6MHz crystal must be installed
on the board.
4.5 E valuation Boa rd Interface
The 8x930Hx Adapter Board interfaces to the 8x930 Family Evaluation. Board. Rev B through
two 40-pin female headers. The headers are surface mounted on the solder side of the board. The
interface is “duplicated” physically and electrically on the component side of the board to allow
probing access.
4.6 S erial Commu nicati ons
The adapte r board contains the new 8x930Hx USB chip. This device has a d efault start-up internal frequency of 3 MHz. You can change thi s frequency to 12 MHz by clearing the LC bit located
in the PCON register. You can switch back to 3 MHz by setting the LC bit. Readers are encouraged to consult the 8x930Ax, 8x930Hx Universal Serial Bus Microcontroller User’s Manual
(order number 272949) for more information on this subject.
6
USB930HXADBD ADAPTER BOARD USER’S GUIDE
The flexibility of frequency change s for power savi ng has a direct im pact on baud rate and serial
communication. To allow debugging sessions without risk of board-PC communication loss, a
number of change s have been add ed to th e RISM code. To estab lis h communi catio n between the
evaluation board and the d ebugger (Keil , PLC, or Tasking softwa re) use either the external serial
link (recommended) or the internal serial link.
4.6.1 Using the Exter nal Serial Port
You are encouraged strongly to use the external serial port to communicate with the debugger
environment . When this serial por t is us ed, the baud r ate i s 19200 (make su re you set th e debugger
software to use the same rate) and all internal timers are available. The internal serial port is then
free and can be used by your application. One interrupt (intr0), however, is used by the UART
and cannot be used. The priority shoul d not be changed.
The ex ternal seria l port is label ed “U ART” o n the bo ard To enab le this p ort, se t the UARTC
switch to the “ON” position.
When using t his p ort, you can se t or cle ar the LC bi t u sing t he S ETB and C LR ins truct ion s. The re
are no restrictions to your code.
4.6.2 Using the Internal Serial Port
The use of the internal se rial port to communicate with the debugger is not recommended. When
you use this serial port, the baud rate is fixed at 9600 (you must set the debugger software to use
the same rate) and timer-two is used by the RISM to generate the baud rate, making this timer
unavailable for your application. The internal serial port is no longer available since it used to
communicate with the debugger. Do not change the interrupt priority. The external interrupts,
intr0 and intr1, are both available.
When using t his p ort, yo u can stil l se t or cle ar the LC bi t. Howe ver, y ou c annot use t he SETB and
CLR instructions to do. So you must use an extended call to a routine inside the RISM that sets
or clears the bit. Instead of using “SETB LC” you must use “ECALL 0FF0083” and instead of
using “CLR LC” use “ECALL 0FF0 08B”.
5.0 8X930XX ADAPTER BOARD SCHEMATICS
The pages that follow provide you with schematics for the adapter board. These files are also
available on the Intel World-Wide Web sit at www.intel.com.
7
USB930HXADBD ADAPTER BOARD USER’S GUIDE
8
D
6
SOF*
PSEN*
EA*
ALE
AVCC
54321
AVCC
EA*
ALE
PSEN*
SOF*
2468101214161820222426283032343638
C
B
A
A
SheetDrawn by Date
0001
DWG No. Rev
FCSM No.
B
Size
11:13:132-Apr-1997
DP0
DM0
DP1
DM1
UPWEN*
DP0
DM0
DP1
DM1
UPWEN*
DP4
DP3
DP2
DM3
DM2
DP4
DM4
DP2
DM2
DM4
OVRI*
RESET
DP3
DM3
OVRI*
RESET
USB930HxADBD Adapter Bd.
Intel Corporation2CEG System Engineering Boards and ASICs
5000 W. Chandler Blvd.
Chandler, AZ 85226
DP0
DM0
DP1
DM1
UPWEN*
40
2468101214161820222426283032343638
DP3
DP2
DM3
DM2
DP4
DM4
RESET
OVRI*
40
P7
13579
111315171921232527293133353739
P5V P5V
EA*
ALE
PSEN*
P3.1
P0.4
P0.2
P0.0
P2.6P2.5
P2.4
P2.2
P2.0
2468101214161820222426283032343638
P6
13579
111315171921232527293133353739
P5V
P2.7
P2.3
P2.1
J7
13579
111315171921232527293133353739
P5V P5V
EA*
ALE
SOF*
AVCC
P1.1
P1.3
P1.5
P1.7
P3.3
P3.5
P3.7
40
P1.0
P1.2
P1.4
P1.6
PSEN*
P3.1
P3.3
P3.5
P0.4
P0.2
P0.0
P2.6P2.5
P2.4
P2.2
P2.0
2468101214161820222426283032343638
J6
13579
111315171921232527293133353739
P5V
P2.7
P2.3
P2.1
AVCC
SOF*
P1.1
P1.3
P1.5
P1.7
P3.7
40
P1.0
P1.2
P1.4
P1.6
HELSCON.SCH CMJ of 2
File
P0.[0:7]
P3.[0:7]
P1.[0:7]
P2.[0:7]
D
P3.0
P3.2
P3.4
P3.0
P3.2
P3.4
P3.6
P0.7
P0.7
P0.5 P0.6
P0.3
P0.1
C
P0.5 P0.6
P3.6
P0.3
P0.1
B
1 2 3 4 56
Although Intel has verified this design to be functional,
Intel assumes no responsibility for any errors which may
appear in the design. Intel reserves the right to modify
this design without notice.
A
D
6
EA*
ALE
PSEN*
UPWEN*
OVRI*
C
B
A
A
DP1
DM1
DP0
DM0
DP3
DM3
DP2
DP4
DM4
SOF*
DM2
RESET
AVCC
SheetDrawn by Date
0001
11:13:332-Apr-1997
DWG No. Rev
54321
PSEN*
ALE
EA*
OVRI*
UPWEN*
C9
0.1 uF
C6
0.1 uF
C5
0.1 uF
C7
C4
0.1 uF
ECAP
OVRI#
61
UPWEN#
62
Reserved
63
Reserved
64
PSEN#
65
ALE
66
EA#
67
Vcc
68
Vss
1
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
A15/P2.7
2
A14/P2.6
3
A13/P2.5
4
A12/P2.4
5
A11/P2.3
6
A10/P2.2
7
A9/P2.1
8
A8/P2.0
9
P3.7
PLLSEL2
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
PLLSEL1
RESET
AVCC
FCSM No.
USB930HxADBD Adapter Bd.
Intel Corporation1CEG System Engineering Boards and ASICs
5000 W. Chandler Blvd.
Chandler, AZ 85226
0.1 uF
C3
1
TP3
AVCC
1
TP2
XTAL2
C2
30 pF
Y1
12.000 MHz
C1
XTAL1
30 pF
B
Size
HELSSOC.SCH CMJ of 2
File
DP4
DM4
DP1
DM1
DP0
DP3
DM0
DM3
DM2
DP2
SOF*
PLLSEL2 PLLSEL1 PLLSEL0 USB data rate Core frequenc y XTAL1
2-3 2-3 1- 2 1.5 Mbps 3 MHz 6 MHz
1-2 2-3 2- 3 1.5 Mbps 6 MHz 12 MHz
1-2 1-2 2- 3 12 Mbps 12 MHz 12 MHz
JW4
13
2
JW3
13
2
PLLSEL0
1 uF
60
59
DP5
DM5
P5V
50
56
55
58
54
57
DP0
DP1
DM0
DM1
Reserved
47
53
52
51
Vssp
Vccp
ECAP
SOF#
44
46
49
45
48
DP2
DP3
DM2
DM3
Reserved
PLLSEL0
U2
HELSINKI
2
JW2
13
PLLSEL2
43
PLLSEL1
42
RESET
41
AVcc
40
XTAL2
39
XTAL1
38
Vss
37
Vcc
36
A17/P1.7/CEX4/WCLK
35
P1.6/CEX3/WAIT#
34
P1.5/CEX2
33
P1.4/CEX1
32
P1.3/CEX0
31
P1.2/ECI
30
P1.1/T2EX
29
P1.0/T2
28
A16/P3.7/RD#
27
P5V
P2.[0:7]
D
AD7/P0.710AD6/P0.611AD5/P0.512AD4/P0.413AD3/P0.314AD2/P0.215AD1/P0.116AD0/P0.017Vssp18Vccp19P3.0/RXD20P3.1/TXD21P3.2/INT0#22P3.3/INT1#23P3.4/T024P3.5/T125P3.6/WR#
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.[0:7]
P3.0
P3.1
P3.2
P3.3
C
26
P3.4
P3.5
P3.6
C8
10 uF
P5V
P3.[0:7]
P1.[0:7]
B
JW1
1 2
1
TP1
CLK12MHZ
P5V
5
8
VCC
OUT
U1
NC1GND
Clock Osc.
12.000 MHz
4
1 2 3 4 56
Although Intel has verified this design to be functional,
Intel assumes no responsibility for any errors which may
appear in the design. Intel reserves the right to modify
this design without notice.
A
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