Intel SE7525RP2, SE7320EP2 Technical Manual
Intel® Server Board
SE7320EP2 / Intel® Server
Board SE7525RP2
Technical Product Specification
Intel order number D24635-001
Revision 1.0
April 29, 2005
Enterprise Platforms and Services Division - Marketing
Revision History Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2
Revision History
Date Revision Number Modifications
2/01/2005 0.5 Initial release
4/29/2005 0.95
Added BIOS section information, updated HW information to include
latest product developments.
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining
applications. Intel may make changes to specifications and product descriptions at any time,
without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 may contain design
defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2005. All rights reserved.
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Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 Table of Contents
Table of Contents
1. Introduction ........................................................................................................................11
1.1 Server Board Use Disclaimer ................................................................................ 11
2. Intel® Server Board SE7320EP2 / SE7525RP2 Overview ...............................................12
2.1 Intel® Server Boards SE7320EP2 and SE7525RP2 Feature Set .........................12
3. Functional Architecture.....................................................................................................14
3.1 Processor and Memory Subsystem....................................................................... 14
3.1.1 Processor Support ................................................................................................. 14
3.1.2 Memory Subsystem ............................................................................................... 17
3.2 Intel® E7320 / E7525 Chipset ...............................................................................20
3.2.1 MCH Memory Architecture Overview..................................................................... 21
3.2.2 Memory Controller Hub (MCH) .............................................................................. 22
3.2.3 6300ESB ICH ........................................................................................................22
3.3 Super I/O ...............................................................................................................25
3.3.1 GPIOs .................................................................................................................... 26
3.3.2 Serial Ports ............................................................................................................ 27
3.4 BIOS Flash ............................................................................................................27
3.5 SM Bus Block Diagram.......................................................................................... 28
4. Clock Generation and Distribution...................................................................................29
5. PCI I/O Subsystem .............................................................................................................31
5.1 PCI Subsystem ...................................................................................................... 31
5.1.1 P32-A: 32-bit/33-MHz PCI Subsystem................................................................... 31
5.1.2 P64-B 66-MHz PCI-X Subsystem.......................................................................... 32
5.1.3 PCI Express x8 ...................................................................................................... 33
5.1.4 PCI Express x16 (E7525 MCH support only)......................................................... 33
5.2 Video Controller ..................................................................................................... 34
5.2.1 Video Modes..........................................................................................................34
5.2.2 Video Memory Interface......................................................................................... 35
5.2.3 Host Bus Interface ................................................................................................. 35
5.3 Network Interface Controller (NIC) ........................................................................ 36
5.3.1 NIC Connector and Status LEDs ........................................................................... 36
5.4 Interrupt Routing .................................................................................................... 36
5.4.1 Legacy Interrupt Routing .......................................................................................36
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5.4.2 APIC Interrupt Routing........................................................................................... 37
5.4.3 Serialized IRQ Support .......................................................................................... 38
5.5 PCI Error Handling................................................................................................. 40
6. BIOS.....................................................................................................................................41
6.1 BIOS Architecture .................................................................................................. 41
6.1.1 BIOS Identification String....................................................................................... 41
6.2 System Initialization ............................................................................................... 42
6.2.1 Processors.............................................................................................................42
6.2.2 Memory Subsystem ............................................................................................... 45
6.2.3 PCI.........................................................................................................................51
6.2.4 PCI Express........................................................................................................... 52
6.2.5 Keyboard/Mouse.................................................................................................... 53
6.2.6 Universal Serial Bus (USB).................................................................................... 53
6.2.7 IDE.........................................................................................................................53
6.2.8 Removable Media Drives....................................................................................... 53
6.2.9 Flash ROM............................................................................................................. 54
6.3 BIOS POST ........................................................................................................... 54
6.3.1 User Interface ........................................................................................................ 54
6.3.2 System Diagnostic Screen..................................................................................... 55
6.3.3 Quiet Boot / OEM Splash Screen .......................................................................... 55
6.3.4 BIOS Boot Popup Menu ........................................................................................ 56
6.4 BIOS Setup Utility .................................................................................................. 56
6.4.1 Localization............................................................................................................56
6.4.2 Console Redirection ..............................................................................................57
6.4.3 Configuration Reset ............................................................................................... 57
6.4.4 Keyboard Commands ............................................................................................ 57
6.4.5 Entering BIOS Setup .............................................................................................58
6.5 Security..................................................................................................................75
6.5.1 Operating Model .................................................................................................... 75
6.5.2 Administrator/User Passwords and F2 Setup Usage Model.................................. 76
6.5.3 Password Clear Jumper ........................................................................................77
6.6 Flash Architecture and Flash Update Utility........................................................... 78
6.6.1 Flash Update Utility................................................................................................ 78
6.6.2 Update OEM Logo ................................................................................................. 80
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7. Hardware and System Management.................................................................................82
7.1 Hardware Management ......................................................................................... 82
7.1.1 Fan Speed Control Diagram .................................................................................. 82
7.1.2 Chassis Intrusion ................................................................................................... 83
7.2 Intel® Server Management (ISM) Software Support .............................................83
7.3 Additional System Management Components....................................................... 83
7.3.1 Console Redirection ..............................................................................................83
7.3.2 Wired For Management (WFM) ............................................................................. 84
7.3.3 Vital Product Data (VPD) ....................................................................................... 84
7.3.4 PXE BIOS Support ................................................................................................ 84
7.3.5 System Management BIOS (SMBIOS) .................................................................. 84
8. Sleep Support.....................................................................................................................85
8.1 Advanced Configuration and Power Interface (ACPI) ........................................... 85
8.2 Sleep and Wake Functionality ............................................................................... 86
8.2.1 Power Switch Off to On ......................................................................................... 86
8.2.2 On to Off (operating system absent)...................................................................... 86
8.2.3 On to Off (operating system present) .................................................................... 86
8.2.4 On to Sleep (ACPI) ................................................................................................ 87
8.2.5 Sleep to On (ACPI) ................................................................................................ 87
8.2.6 System Sleep States .............................................................................................87
9. Error Logging .....................................................................................................................88
9.1 Error Sources and Types....................................................................................... 88
9.2 SMI Handler........................................................................................................... 88
9.2.1 PCI Bus Error......................................................................................................... 88
9.2.2 Processor Bus Error ..............................................................................................89
9.2.3 Memory Bus Error.................................................................................................. 89
9.2.4 Logging Format Conventions................................................................................. 89
9.3 Single-bit ECC Error Throttling Prevention ............................................................ 89
9.4 Error Messages and Error Codes .......................................................................... 89
9.4.1 POST Progress Codes and Messages.................................................................. 89
9.4.2 BIOS Messages..................................................................................................... 95
9.4.3 POST Error Messages and Handling .................................................................. 100
9.4.4 Boot Block Error Beep Codes.............................................................................. 102
9.4.5 POST Error Beep Codes ..................................................................................... 103
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9.4.6 "POST Error Pause" option.................................................................................. 103
10. Server Board SE7320EP2 and SE7525RP2 Connectors...............................................104
10.1 Main Power Connector ........................................................................................ 104
10.2 Memory Module Connector ................................................................................. 105
10.3 Processor Socket................................................................................................. 107
10.4 I2C Header ........................................................................................................... 110
10.5 PCI Slot Connector .............................................................................................. 111
10.6 Front Panel Connector......................................................................................... 114
10.7 VGA Connector.................................................................................................... 115
10.8 NIC Connector ..................................................................................................... 115
10.9 IDE Connector ..................................................................................................... 116
10.10 SATA Connector.................................................................................................. 116
10.11 USB Connector.................................................................................................... 117
10.12 Floppy Connector ................................................................................................118
10.13 Serial Port Connector ..........................................................................................118
10.14 Keyboard and Mouse Connector ......................................................................... 119
10.15 Miscellaneous Headers .......................................................................................119
10.15.1 Fan Header..........................................................................................................119
10.15.2 Intrusion Cable Connector ................................................................................... 120
10.15.3 System Recovery and Update Jumpers ..............................................................120
11. General Specifications.....................................................................................................122
11.1 Absolute Maximum Ratings ................................................................................. 122
11.2 Mean Time Between Failure (MTBF)................................................................... 122
11.3 Processor Power Support.................................................................................... 123
11.4 Power Supply Specifications ...............................................................................123
11.4.1 Power Timing....................................................................................................... 123
11.4.2 Voltage Recovery Timing Specifications .............................................................126
12. Product Regulatory Compliance.....................................................................................128
12.1 Product Safety Compliance ................................................................................. 128
12.1.1 Product EMC Compliance ................................................................................... 128
12.1.2 Mandatory/Standard: Certifications, Registration, Declarations .......................... 129
12.1.3 Product Regulatory Compliance Markings .......................................................... 129
12.2 Electromagnetic Compatibility Notices ................................................................129
12.2.1 Europe (CE Declaration of Conformity) ............................................................... 129
12.2.2 Australian Communications Authority (ACA) (C-Tick Declaration of Conformity) 129
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12.2.3 Ministry of Economic Development (New Zealand) Declaration of Conformity ...130
12.2.4 BSMI (Taiwan) ..................................................................................................... 130
12.3 Replacing the Back up Battery ............................................................................130
Appendix A: Integration and Usage Tips..............................................................................131
Glossary...................................................................................................................................132
List of Figures
Figure 1. Block Diagram of Intel® Server Boards SE7320EP2 and SE7525RP2....................... 13
Figure 2. CEK ‘Passive’ Component Stackup............................................................................. 16
Figure 3. Memory Sub-system Block Diagram............................................................................ 17
Figure 4. Memory Bank Label Definition..................................................................................... 19
Figure 5. Intel® Server Boards SE7320EP2 and SE7525RP2 SMBUS Block Diagram............. 28
Figure 6. Intel® Server Boards SE7320EP2 and SE7525RP2 Clock Distribution Diagram .......30
Figure 7. Video Controller PCI Bus Interface..............................................................................35
Figure 8. Interrupt Routing Diagram ...........................................................................................38
Figure 9. Interrupt Routing Diagram ...........................................................................................39
Figure 10. BIOS Identification String...........................................................................................41
Figure 11. Fan Speed Control Block Diagram ............................................................................ 82
Figure 12. System Recovery and Update Jumpers (J17) ......................................................... 120
Figure 13. Output Voltage Timing ............................................................................................. 124
Figure 14. Turn On / Turn Off Timing........................................................................................ 126
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List of Tables Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2
List of Tables
Table 1. Processor Support Matrix .............................................................................................14
Table 2. Memory Bank Labels .................................................................................................... 18
Table 3. I
Table 4. Supported DDR2 Technology ....................................................................................... 21
Table 5. 6300ESB ICH GPIO Usage Table ................................................................................ 24
Table 6. Super I/O GPIO Usage Table ....................................................................................... 26
Table 7. PCI Bus Segment Characteristics................................................................................. 31
Table 8. P32-A Configuration IDs ............................................................................................... 31
Table 9. P32-A Arbitration Connections...................................................................................... 32
Table 10. P64-B Configuration IDs ............................................................................................. 32
Table 11. P64-B Arbitration Connections.................................................................................... 33
2
C Addresses for Memory Module SMB ......................................................................19
Table 12. PCI Express x8 Connections ...................................................................................... 33
Table 13. PCI Express x16 (Port B) Connections....................................................................... 33
Table 14. Video Modes ............................................................................................................... 34
Table 15. PCI AND PCI-X Interrupt Routing/Sharing.................................................................. 37
Table 16. Interrupt Definitions.....................................................................................................37
Table 17. Supported DIMM Module Capacities .......................................................................... 45
Table 18. Supported DDR2-400 DIMM Populations ................................................................... 47
Table 19. Memory Error Handling in RAS Mode......................................................................... 47
Table 20. Memory Error Handling in non-RAS Mode.................................................................. 48
Table 21. Sample BIOS Popup Menu......................................................................................... 56
Table 22. BIOS Setup Keyboard Command Bar Options ........................................................... 57
Table 23. BIOS Setup, Main Menu Options................................................................................ 58
Table 24. BIOS Setup, Advanced Menu Options........................................................................ 59
Table 25. BIOS Setup, Processor Configuration Sub-menu Options ......................................... 60
Table 26. BIOS Setup IDE Configuration Menu Options ............................................................ 61
Table 27. Mixed PATA-SATA Configuration with only Primary PATA ........................................63
Table 28. BIOS Setup, IDE Device Configuration Sub-menu Selections ................................... 63
Table 29. BIOS Setup, Floppy Configuration Sub-menu Selections........................................... 64
Table 30. BIOS Setup, Super I/O Configuration Sub-menu........................................................ 65
Table 31. BIOS Setup, USB Configuration Sub-menu Selections .............................................. 65
Table 32. BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections........... 66
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Table 33. BIOS Setup, PCI Configuration Sub-menu Selections ............................................... 67
Table 34. BIOS Setup, Memory Configuration Sub-menu Selections......................................... 68
Table 35. BIOS Setup, Boot Menu Selections ............................................................................ 69
Table 36. BIOS Setup, Boot Settings Configuration Sub-menu Selections ................................ 69
Table 37. BIOS Setup, Boot Device Priority Sub-menu Selections ............................................70
Table 38. BIOS Setup, Hard Disk Drive Sub-Menu Selections................................................... 70
Table 39. BIOS Setup, Removable Drives Sub-menu Selections............................................... 70
Table 40. BIOS Setup, CD/DVD Drives Sub-menu Selections................................................... 71
Table 41. BIOS Setup, Security Menu Options........................................................................... 71
Table 42. BIOS Setup, Server Menu Selections......................................................................... 72
Table 43. BIOS Setup, System Management Sub-menu Selections.......................................... 72
Table 44. BIOS Setup, Serial Console Features Sub-menu Selections ..................................... 73
Table 45. BIOS Setup, Event Log Configuration Sub-menu Selections ..................................... 74
Table 46. BIOS Setup, Exit Menu Selections .............................................................................74
Table 47. Security Features Operating Model ............................................................................ 75
Table 48. Monitored Components............................................................................................... 82
Table 49. Supported Wake Events ............................................................................................. 87
Table 50. POST Code Checkpoints............................................................................................90
Table 51. Boot Block Initialization Code Checkpoints................................................................. 92
Table 52. Boot Block Recovery Code Checkpoints .................................................................... 93
Table 53. DIM Code Checkpoints ............................................................................................... 94
Table 54. ACPI Runtime Checkpoints ........................................................................................95
Table 55. Memory BIOS Messages ............................................................................................ 95
Table 56. Boot BIOS Messages.................................................................................................. 95
Table 57. Storage Device BIOS Messages ................................................................................96
Table 58. Virus Related BIOS Messages ...................................................................................98
Table 59. System Configuration BIOS Messages....................................................................... 98
Table 60. CMOS BIOS Messages .............................................................................................. 99
Table 61. Miscellaneous BIOS Messages .................................................................................. 99
Table 62. USB BIOS Error Messages....................................................................................... 100
Table 63. SMBIOS BIOS Error Messages ................................................................................100
Table 64. POST Error Messages and Handling........................................................................ 101
Table 65. Boot Block Error Beep Codes ................................................................................... 102
Table 66. POST Error Beep Codes ..........................................................................................103
Table 67. Troubleshooting BIOS Beep Codes..........................................................................103
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Table 68. Power Connector Pin-out (J12)................................................................................. 104
Table 69. Auxiliary Signal Connector (J5)................................................................................. 104
Table 70. Auxiliary CPU Power Connector Pin-out (J22) ......................................................... 105
Table 71. DIMM Connectors (J16,J18,J20,J21) .......................................................................105
Table 72. Socket 604 Processor Socket Pin-out (J36, J37) .....................................................107
Table 73. HSBP Header Pin-out (J30,J54) ............................................................................... 110
Table 74. OEM RMC Header Pin-out (J33) .............................................................................. 110
Table 75. P32-A 5V 32-bit/33-MHz PCI Slot Pin-out (J10, J11) ............................................... 111
Table 76. P64-B 3.3V 64-bit/66-MHz PCI-X Slot Pin-out (J8, J9)............................................. 112
Table 77. PCI Express Slot Pin-out (J13 for x8, J14 for x16) ................................................... 113
Table 78. Front Panel 34-Pin Header Pin-out (J38).................................................................. 114
Table 79. VGA Connector Pin-out (J4) ..................................................................................... 115
Table 80. NIC1-82541PI(10/100/1000) Connector Pin-out (JA1,JA2) ...................................... 115
Table 81. ATA 40-pin Connector Pin-out (J43).........................................................................116
Table 82. SATA Connector Pin-out (J28, J32).......................................................................... 116
Table 83. USB Connectors Pin-out (J55).................................................................................. 117
Table 84. Optional USB Connection Header Pin-out (J31)....................................................... 117
Table 85. Legacy 34-pin Floppy Connector Pin-out (J47) ........................................................118
Table 86. 9-pin Header Serial B Port Pin-out (J15) ..................................................................118
Table 87. Keyboard and Mouse PS/2 Connectors Pin-out (J2) ................................................ 119
Table 88. 3-pin Fan Headers Pin-out (J1, J48).........................................................................119
Table 89. 4-pin Fan Headers Pin-out (J7, J44, J45, J46) ......................................................... 119
Table 90. 6-pin Fan Headers Pin-out (J50)............................................................................... 120
Table 91. IntruSuper IOn Cable Connector (J19)Pin-Out ......................................................... 120
Table 92. System Recovery and Update Jumper Options........................................................ 121
Table 93. Absolute Maximum Ratings ...................................................................................... 122
Table 94. MTBF Calculation .....................................................................................................122
Table 95. Intel® Xeon™ Processor DP TDP Guidelines .......................................................... 123
Table 96. Power Supply Voltage Specification ......................................................................... 123
Table 97. Voltage Timing Parameters ......................................................................................124
Table 98. Turn On / Off Timing ................................................................................................. 125
Table 99. Transient Load Requirements................................................................................... 127
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Introduction
1. Introduction
The Intel® Server Board SE7320EP2 / SE7525RP2 Technical Product Specification provides
technical details for the server board’s functional architecture and feature set. It also provides a
high-level detail of some of the board’s functional sub-systems.
This document is intended to be the technical reference for this board. Updates to this
document will be made via the Specification Update that is published monthly following the date
of the product launch.
1.1 Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel ensures through its own chassis
development and testing that when Intel server building blocks are used together, the fully
integrated system will meet the intended thermal requirements of these components. It is the
responsibility of the system integrator who chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of air
flow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
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Intel® Server Board SE7320EP2 / SE7525RP2 Overview
2. Intel® Server Board SE7320EP2 / SE7525RP2
Overview
The Intel® Server Boards SE7320EP2 and SE7525RP2 are monolithic printed circuit boards
with features that were designed to support the general purpose, pedestal server market. The
Intel Server Board SE7525RP2 also meets the needs of a high-end workstation system. The
architecture is based around the Intel® E7320/E7525 chipset and is capable of supporting one
or two Intel® Xeon™ processors with 1MB or 2MB L2 cache and up to 8GB of memory.
2.1 Intel® Server Boards SE7320EP2 and SE7525RP2 Feature Set
The Intel Server Boards SE7320EP2 and SE7525RP2 support the following feature set:
Processor/FSB support
- Dual Intel Xeon processors with 1MB or 2MB L2 cache using the 604-pin FCPGA
processor package
- 800 MHz FSB
- 6.4 GB/sec bus bandwidth
- One version 10.1 compliant VRD to supply each CPU core voltage
Intel E7320/E7525 chipset components
- MCH memory controller
- 6300ESB ICH I/O controller
Support for up to four DDR2-400 compliant ECC DDR2 DIMMs providing up to 8GB
memory support.
Three separate and independent PCI buses:
- Segment A: Two PCI 32-bit/33-MHz, 5 V connectors supporting full-length PCI add-
in cards and two embedded devices:
2D/3D graphics controller: ATI* Rage* XL video controller with 8 MB of SDRAM
One Intel 10/100/1000 82541PI Fast Ethernet Controller
- Segment B: Two PCI-X* 64-bit/66-MHz, 3.3 V slots supporting full-length PCI / PCI-X
add-in cards
- Segment C:
One x4 PCI Express* slot supporting x1/x2/x4/x8 PCI Express add-in card (up to
x 4 connection)
One x16 PCI Express (Server Board SE7525RP2 only) supporting
x1/x2/x4/x8/x16 PCI Express add-in card.
One x1 PCI Express bus supporting the Marvell* Yukon* 88E8050 10/100/1000
gigabit Ethernet controller
LPC (Low Pin Count) bus segment with one embedded devices:
- Super I/O (Super I/O) controller chip, National Semiconductor* PC8374L, providing
all PC-compatible I/O (floppy, serial, keyboard, mouse) and integrated hardware
monitoring
Two external Universal Serial Bus (USB) ports with an additional internal header
providing two optional USB ports for front panel support
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Intel® Server Board SE7320EP2 / SE7525RP2 Overview
One IDE connector, supporting up to two ATA-100 compatible devices
Two SATA connectors, supporting up to two SATA devices and RAID 0/1
Support for up to five system fans and two processor fans
SSI-compliant connectors for SSI interface support: front panel and power connectors
The following figure below shows the functional blocks of the server boards and the plug-in
modules that they support.
Figure 1. Block Diagram of Intel® Server Boards SE7320EP2 and SE7525RP2
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Functional Architecture
3. Functional Architecture
This chapter provides a high-level description of the functionality distributed between the
architectural blocks of the Intel® Server Boards SE7320EP2 and SE7525RP2.
3.1 Processor and Memory Subsystem
The Intel® chipset E7320 / E7525 provides a 36-bit address, 64-bit data processor host bus
interface, operating at 800 MHz in the AGTL+ signaling environment. The MCH component of
the chipset provides an integrated memory controller, an 8-bit hub interface, one x8 PCI
Express interface (programmable into separate x 4 interface), and a x16 PCI Express interface
(E7525 MCH only).
The x4 PCI Express interface provides
The interface to x8 PCI Express slot (Lane 0-3)
The interface to Marvell (Lane 4)
The x16 PCI Express interface provides
The interface to x16 PCI Express slot
The 32-bit/33-MHz PCI buses via the 6300ESB ICH
The board directly supports up to 8GB of ECC memory, using four DDR2-400 compliant ECC
DIMMs. The ECC implementation in the MCH can detect and correct single-bit errors (SBE),
detect multiple-bit errors (MBE), and supports Intel® x4 Single Data Device Correction (Intel®
x4 SDDC) feature with x4 DIMMs.
3.1.1 Processor Support
The Intel Server Boards SE7320EP2 and SE7525RP2 support one or two processors in the
604-pin FCPGA package. When two processors are installed, both must be of identical revision,
core voltage, and bus/core speed. When only one processor is installed, it must be in the socket
labeled CPU0. The other socket must be empty. The support circuitry on the server boards
consist of the following:
Dual 604-pin processor sockets supporting 800MHz FSB Intel® Xeon™ processors.
Processor host bus AGTL+ support circuitry.
Table 1. Processor Support Matrix
Processor Family Package Type Frequency Cache Size Front Side Bus Speed
Intel® Xeon™ MPGA604 2.8~3.6GHz 1 MB 800MHz
Intel® Xeon™ MPGA604 3.0~3.6GHz 2 MB 800MHz
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Functional Architecture
Notes:
Processors must be populated in sequential order. Processor socket 1 must be
populated before processor socket 2.
The board is designed to provide up to 105A of current per processor. Processors with
higher current requirements are not supported.
No terminator is required in the second processor socket when using a uni-processor
configuration.
In addition to the circuitry described above, the processor subsystem contains the following:
Reset configuration logic
Processor module presence detection logic
Server management registers and sensors
3.1.1.1 Processor VRD
The Intel Server Boards SE7320EP2 and SE7525RP2 have two Voltage Regulator Downs
(VRDs) to support two processors. This is compliant with the VRM 10.1 specification and
provides a maximum of 210 Amps, which is capable of supporting the requirements for two
Intel® Xeon™ processors.
The board hardware must monitor the processor VTTEN (Output enable for VTT) pin for each
processor before turning on the VRD. If the VTTEN pin of the two processors are not identical,
then the Power on Logic will not turn on the VRD.
3.1.1.2 Reset Configuration Logic
The BIOS determines the processor stepping, cache size, and other information through the
CPUID instruction. The requirements are as follows:
All processors in the system must operate at the same frequency, have the same cache
sizes, and same VID. No mixing of product families is supported.
Processors run at a fixed speed and cannot be programmed to operate at a lower or
higher speed.
The processor information is read at every system power-on.
Note: The processor speed is the processor power on reset default value. No manual processor
speed setting options exist either in the form of a BIOS setup option or jumpers.
3.1.1.3 Processor Module Presence Detection
Logic is provided on the server boards to detect the presence and identity of installed
processors. The Power On logic checks the logic and will not turn on the system DC power
unless the VTTENs of both the processors match in a DP configuration.
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Functional Architecture
3.1.1.4 Interrupts and APIC
Interrupt generation and notification to the processors is done by the APICs in the 6300ESB ICH
using messages on the front side bus.
3.1.1.5 Common Enabling Kit (CEK) Design Support
The server boards have been designed to comply with the Intel® Common Enabling Kit (CEK)
processor mounting and thermal solution. The server boards ship from Intel’s factory with a CEK
spring snapped onto the underside of the board, beneath each processor socket. The CEK
spring is removable to allow the use of non-Intel heat sink retention solutions.
Heatsink assembly
with integrated
hardware
TIM
Server Board
CEK Spring
Chassis
Note: When installing either of these server boards into an Intel® Server Chassis SC5300, the
passive heatsink solution (no fan) must be used.
Figure 2. CEK ‘Passive’ Component Stackup
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3.1.2 Memory Subsystem
The server boards supports up to four DIMM slots for a maximum memory capacity of 8 GB. The
DIMM organization is x72, which includes eight ECC check bits. The memory interface runs at
400MT/s. The memory controller supports memory scrubbing, single-bit error correction and
multiple-bit error detection and Intel x4 SDDC support with x4 DIMMs. Memory can be
implemented with either single-sided (one row) or double-sided (two row) DIMMs.
The figure below provides a block diagram of the memory sub-system implemented on the
board.
Figure 3. Memory Sub-system Block Diagram
3.1.2.1 Memory DIMM Support
The board supports DDR2-400 compliant ECC DIMMS operating at 400MT/s. Only DIMMs
tested and qualified by Intel or a designated memory test vendor are supported on this board.
All DIMMs are supported by design, but only fully qualified DIMMs will be supported on the
board.
The minimum supported DIMM size is 256MB. Therefore, the minimum main memory
configuration is 1 x 256MB or 256MB. The largest size DIMM supported is a 2GB registered
DDR2-400 ECC DIMM based on 1Gb technology. Therefore, the maximum main memory
configuration is 4 x 2GB or 8GB.
Only registered DDR2-400 compliant, ECC, DDR2 memory DIMMs are supported
ECC single-bit errors (SBE) are corrected and multiple-bit error (MBE) are detected.
The server boards support Intel® x4 SDDC with x4 DIMMs.
The maximum memory capacity is 8GB
The minimum memory capacity is 256MB
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3.1.2.2 Memory Configuration
The memory interface between the MCH and the DIMMs is 144 bits wide (72 bits for each
bank).
There are two banks of DIMMs, Bank 1 and Bank 2. Bank 1 contains DIMM socket locations 1A
and 1B. Bank 2 contains 2A and 2B. The sockets associated with each bank are located next to
each other and the DIMM socket identifiers are marked on the server board silkscreen, near the
DIMM socket.
For designs that require a lower price point, a single 256MB DIMM can be populated in the
DIMM 1B socket. When a single DIMM is installed, interleaving and Intel x4 SDDC are not
available. Bank 2 will only operate with two DIMMs installed.
The server boards’ signal integrity and cooling are optimized when memory banks are
populated in order. Before populating either DIMM socket in Bank 2, both DIMMs in Bank 1
must be populated. No empty DIMM sockets are allowed between populated DIMMs.
DIMM and memory configurations must adhere to the following:
DDR2-400 ECC, registered DIMM modules
DIMM organization: x72 with ECC
Pin count: 240
DIMM capacity: 256 MB, 512 MB, 1 GB, 2 GB DIMMs
Serial PD: JEDEC Rev 2.0
Voltage options: 1.8 V (VDD/VDDQ)
Interface: SSTL-1.8
Table 2. Memory Bank Labels
Memory DIMM Bank
J18 (DIMM 1A), J16 (DIMM 1B) 1
J21 (DIMM 2A), J20 (DIMM 2B) 2
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J16 J18 J20 J21
1B 2B 1A 2A
Bank 2
Figure 4. Memory Bank Label Definition
2
3.1.2.3 I
2
The I
C bus is used by the system BIOS to retrieve DIMM information needed to program the
MCH memory registers, which are required to boot the system. The following table provides the
2
I
C addresses for each DIMM slot.
C Bus
Table 3. I2C Addresses for Memory Module SMB
Device Address
DIMM 1A 0xA6
DIMM 1B 0xAE
DIMM 2A 0xA4
DIMM 2B 0xAC
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3.1.2.4 DRAM ECC
The ECC used for DRAM provides Intel® x4 SDDC technology for x4 SDRAMs. DRAMs that
are x8 use the same algorithm but will not have Intel x4 SDDC technology, since at most only
four bits can be corrected with this ECC.
The method provides more ECC bits so each ECC word can correct more than a single-bit
failure. This is possible because different mathematical algorithms provide multiple-bit
correction with the right number of data bits and ECC bits. For example, a 144-bit ECC word
that consists of 128 data bits and 16 ECC bits can be used to correct up to 4-bit errors within
certain bit fields of data. These four bits must be adjacent, not random. Even though the ratio of
the ECC bits to data bits is the same as the previous example (16/128 vs. 8/64), the longer ECC
word allows for a correction and detection algorithm that is more efficient.
3.2 Intel® E7320 / E7525 Chipset
The Intel Server Boards SE7320EP2 and SE7525RP2 are designed around the Intel E7320 /
E7525 chipset. The chipset provides an integrated I/O bridge and memory controller, and a
flexible I/O subsystem core (PCI Express). This is targeted for multiprocessor systems and
standard high-volume servers. The chipset consists of two components:
MCH: Memory Control Hub. The MCH accepts access requests from the host
(processor) bus and directs those accesses to memory or to one of the PCI buses. The
MCH monitors the host bus, examining addresses for each request. Accesses may be
directed to a memory request queue for subsequent forwarding to the memory
subsystem, or to an outbound request queue for subsequent forwarding to one of the
PCI buses. The MCH also accepts inbound requests from the 6300ESB ICH. The MCH
is responsible for generating the appropriate controls to control data transfer to and from
memory.
6300ESB ICH: The 6300ESB ICH controller has several components. It provides the
interface for a 32-bit/33-MHz PCI bus and the interface for a 64-bit/66MHz PCI-X bus.
The 6300ESB ICH can be both a master and a target on that PCI bus. The 6300ESB
ICH also includes a USB 2.0 controller and an IDE controller. The 6300ESB ICH is also
responsible for much of the power management functions, with ACPI control registers
built in. The 6300ESB ICH also provides a number of GPIO pins and has the LPC bus to
support low speed legacy I/O.
The MCH and 6300ESB ICH chips provide the pathway between processor and I/O systems.
The MCH is responsible for accepting access requests from the host (processor) bus, and
directing all I/O accesses to one of the PCI buses or legacy I/O locations. If the cycle is directed
to one of the PCI Express segments, the MCH communicates with the PCI Express Devices
(add-in card, on board devices) through the PCI Express interface. If the cycle is directed to the
6300ESB ICH, the cycle is output on the MCH’s 8-bit HI 1.5 bus.
The E7320 MCH supports one x8 port configuration PCI Express interface. The E7525MCH
supports one x8 port and one x16 port configuration PCI Express interface. The x8 interface is
capable of logically dividing into separate x4 interface. Each with half the bandwidth of x8
interface and fully compliant to the specification. Maximum theoretical peak bandwidth on each
x8 PCI Express interfaces of 2.5Gb/s in each direction simultaneously, for 5 Gb/s per port.
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All I/O for the board, including PCI and PC-compatible I/O, is directed through the MCH and
then through the 6300ESB ICH provided PCI buses.
The 6300ESB ICH provides one 32-bit/33-MHz PCI bus, hereafter called P32-A.
The 6300ESB ICH provides one 64-bit/66-MHz PCI-X bus, hereafter called P64-B.
This independent bus structure allows both PCI buses to operate independently and
concurrently, providing additional bandwidth to the system.
3.2.1 MCH Memory Architecture Overview
The MCH supports a 144-bit wide memory sub-system that can support up to 16GB of
DDR2-400 memory, using 4 GB DIMMs. This configuration needs external registers for
buffering the memory address and control signals. The four chip selects are registered inside
the MCH and need no external registers for chip selects.
The memory interface runs at 400MT/s. The memory interface supports a 72-bit or 144-bit wide
memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 256 Mb,
512 Mb, 1 Gb DRAM densities. The DDR2 DIMM interface supports memory scrubbing, singlebit error correction, and multiple bit error detection and Intel x4 SDDC with x4 DIMMs.
3.2.1.1 DDR2 Configurations
The DDR2 interface supports up to 8GB of main memory and supports single- and doubledensity DIMMs. DDR2 can be any industry-standard DDR2. The following table shows the
DDR2 DIMM technology supported.
Table 4. Supported DDR2 Technology
Technology Organization DRAM Components / DIMM Row / Column
Address Bits
4M X 8 X 4bks 8 12/10 128Mb
8M X 4 X 4bks 16 12/11
8M X 8 X 4bks 8 13/10 256Mb
16M X 4 X 4bks 16 13/11
16M X 8 X 4bks 8 14/10 512Mb
32M X 4 X 4bks 16 14/11
32M X 8 X 8bks 8 14/10 1Gb
64M X 4 X 8bks 16 14/11
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3.2.2 Memory Controller Hub (MCH)
The MCH is a 1077-ball FC-BGA device and uses the proven components of previous
generations like the Intel® Xeon™ processor bus interface unit, the hub interface unit, and the
DDR2 memory interface unit. In addition, the MCH incorporates a PCI Express interface. The
PCI Express interface allows the MCH to directly interface with the PXH/PXHD or PCI Express
devices. The MCH also increases the main memory interface bandwidth and maximum memory
configuration with a 144-bit wide memory interface.
The MCH integrates the following main functions:
An integrated high performance main memory subsystem
An PCI Express bus which provides an interface to the PXH/PXHD or PCI Express
devices
A HL 1.5 bus which provides an interface to the 6300ESB ICH
Other features provided by the MCH include the following:
Full support of ECC on the processor bus
Full support of Intel x4 SDDC on the memory interface with x4 DIMMs
Twelve deep in-order queue, two deep defer queue
Full support of registered DDR2-400 ECC DIMMs
Support for 2GB DDR2 memory modules
Memory scrubbing
3.2.3 6300ESB ICH
The 6300ESB ICH is a multi-function device, housed in a 689-pin BGA device, providing a HI
1.5 to PCI bridge, a PCI 32-bit/33MHz interface, a 64-bit/66MHz PCI-X interface, a PCI IDE
interface, a PCI USB controller, and a power management controller. Each function within the
6300ESB ICH has its own set of configuration registers. Once configured, each appears to the
system as a distinct hardware controller sharing the same PCI bus interface.
The primary role of the 6300ESB ICH is to provide the gateway to all PC-compatible I/O devices
and features. The board uses the following the 6300ESB ICH features:
PCI, PCI-X bus interface
LPC bus interface
IDE interface, with Ultra DMA 100 capability
Universal Serial Bus (USB) 2.0 interface
PC-compatible timer/counter and DMA controllers
APIC and 8259 interrupt controller
Power management
System RTC
General purpose I/O (GPIO)
The following are the descriptions of how each supported feature is used on the board.
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3.2.3.1 PCI Bus P32-A I/O Subsystem
The 6300ESB ICH provides a legacy 32-bit PCI subsystem and acts as the central resource on
this PCI interface. P32-A supports the following embedded devices and connectors:
An ATI Rage XL video controller with 3D/2D graphics accelerator
One Intel
Two 5V expansion slots capable of supporting full-length PCI add-in cards operating at
®
82541PI network controller
33 MHz
3.2.3.2 PCI Bus P64-B I/O Subsystem
The 6300ESB ICH provides a legacy 64-bit PCI-X subsystem and acts as the central resource
on this PCI interface. P64-B supports two 3.3V expansion slots. These support full-length PCI-X
add-in cards operating at 66 MHz.
3.2.3.3 PCI Bus Master IDE Interface
The 6300ESB ICH acts as a PCI-based Ultra DMA 100 IDE controller that supports
programmed I/O transfers and bus master IDE transfers. The 6300ESB ICH supports two IDE
channels, supporting two drives each (drives 0 and 1). The Intel Server Boards SE7320EP2 and
SE7525RP2 implement one 40-pin IDE connector to access the IDE functionality.
The IDE interface supports Ultra DMA 100 Synchronous DMA Mode transfers on the 40-pin
connector.
3.2.3.4 USB Interface
The 6300ESB ICH contains one EHCI USB 2.0 controller and four USB ports. The USB
controller moves data between the main memory and up to four USB connectors. All ports
function identically and with the same bandwidth. The Server Boards SE7320EP2 and
SE7525RP2 implement four ports on the board.
The server boards provide two external USB ports on the back. The dual-stack USB connector
is located within the standard ATX I/O panel area next to the keyboard and mouse housing. The
USB specification defines the external connectors.
The third and fourth USB ports are optional and can be accessed by cabling from an internal 9pin connector on the server boards to an external USB port either at the front or the rear of a
chassis.
3.2.3.5 Two port SATA Interface
The 6300ESB ICH contains one SATA controller and two SATA ports. The data transfer rates
up to 150Mbyte/s. Alternate Device ID and RAID Class Code options support Soft RAID.
3.2.3.6 Compatibility Interrupt Control
The 6300ESB ICH provides the functionality of two 82C59 PIC devices for ISA-compatible
interrupt handling.
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3.2.3.7 APIC
The 6300ESB ICH integrates an I/O APIC capability with 24 interrupts.
3.2.3.8 General Purpose Input and Output Pins
The 6300ESB ICH provides a number of general purpose input and output pins. Many of these
pins have alternate functions, and thus all are not available. The following table lists the GPI
and GPO pins used on the board and gives a brief description of their function.
Table 5. 6300ESB ICH GPIO Usage Table
Pin Name (Powe
Well)
GPIO0/PXREQ2# Core Input HR_PAREQ2_N PXREQ2#
GPIO1/PXREQ3# Core Input HR_PAREQ3_N PXREQ3#
GPIO2/PIRQE# Core Input PCI_PIRQE_N PIRQE#
GPIO3/PIRQF# Core Input PCI_PIRQF_N PIRQF#
GPIO4/PIRQG# Core Input PERR_LOG Parity Error Log
GPIO5/PIRQH# Core Input PCI_PIRQH_N PIRQH#
GPIO6 Core Input SKU_VER_ID1 SKU Version ID 1
GPIO7 Core Input MCHPME_N MCH Power Management Event
GPIO8 Resume Input FP_NMI_BTN_N Input: NMI Button
GPIO11/SMBALERT# Resume Input PS_ALERT_N SM Bus alert from power supply
GPIO12 Resume Input MANUF_DET_N Manufacture Mode detect
GPIO13 Resume Input SIO_SMI_N SMI# source from Super I/O
GPIO16/PXGNT2# Core Output HR_PAGNT2_N PXGNT2#
GPIO17/PXGNT3# Core Output HR_PAGNT3_N PXGNT3#
GPIO18 Core Output TP_GPIO_FAN_N Unused
GPIO19 Core Output GPIO_RST_N Generate a hardware reset
GPIO20 Core Output Reserved Reserved
GPIO21 Core Output HR_FLASH_WP_N Active Low to enable flash BOM Write
GPIO23 Core Output POST_STATUS_N Active Low to report POST status
GPIO24 Resume Input/Output DIMM_FRULED-A1_N Output: DIMM FRU LED for 1A
GPIO25 Resume Input/Output DIMM_FRULED-A2_N Output: DIMM FRU LED for 2A
GPIO27 Resume Input/Output NC Unused
GPIO28 Resume Input/Output NC Unused
GPIO32/WDT_TOUT# Core Input/Output SKU_VER_ID2 Input: SKU Version ID 1
GPIO33/PXIRQ0# Core Input/Output HR_PAIRQA_N PXIRQ0#
GPIO34/PXIRQ1# Core Input/Output HR_PAIRQB_N PXIRQ1#
GPIO35/PXIRQ2# Core Input/Output HR_PAIRQC_N PXIRQ2#
GPIO36/PXIRQ3# Core Input/Output HR_PAIRQD_N PXIRQ3#
GPIO37 Core Input/Output PASSWORD_CLEAR_N Input: Password clear selection
GPIO38 Core Input/Output BIOS_RCVR_N Input: BIOS Recover boot selection
GPI / GPO /
Function
Signal Name Function Description
protect
L: Clear Password; H: Normal
L: Recovery; H: Normal
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Functional Architecture
Pin Name (Powe
Well)
GPIO39 Core Input/Output DIS_VGA_N Output: Active Low to disable on
GPIO40 Core Input/Output CMOS_CLEAR_N Input: CMOS Clear selection
GPIO41 Core Input/Output SKU_VER_ID0 Input: SKU Version ID 0
GPIO42 Core Input/Output IDE_PRI_CBLSNS Input: Primary IDE cable type sense
GPIO43 Core Input/Output MROMB_PRESENT_N Input: ZCR card present
GPIO56 Resume Output KNI_DISABLE_N Output: Active Low to disable on
GPIO57 Resume Output YKN_DIS_N_A Output: Active Low to disable on
GPI / GPO /
Function
Signal Name Function Description
board VGA
L: Clear CMOS; H: Normal
L: 80 conductor cable; H: 40
conductor cable
board 82541PI
board 88E8050
3.2.3.9 Power Management
One of the embedded functions of the 6300ESB ICH is a power management controller. This is
used to implement ACPI-compliant power management features. The server boards support
sleep states S0, S1, S4, and S5.
3.3 Super I/O
The National Semiconductor* 8374L Super I/O device contains all of the necessary circuitry to
control two serial ports, one parallel port, floppy disk, PS/2-compatible keyboard and mouse and
hardware monitor controller. The server boards implement the following features:
GPIOs
Two serial ports
Floppy
Keyboard and mouse
Local hardware monitoring
Wake up control
System health support
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3.3.1 GPIOs
The Super I/O provides a number of general-purpose input/output pins that the server boards
utilize. The following table identifies the pin and the signal name used in the schematics:
Table 6. Super I/O* GPIO Usage Table
Pin Power Pin
Number
GPIOE00/SWD Standby 103 SIO_TEMP_SENSOR I/O: LMPCIF
GPIOE01/FANTACH3 Standby 104 FAN_TACH_REAR1 Input: Rear fan tach 1
GPIOE02/FANTACH4 Standby 105 FAN_TACH_6PIN Input: 6-pin fan tach
GPIOE03/FANPWM1 Standby 106 FANPWM_FRONT1 Output: Front fan
GPIOE04/FANPWM2 Standby 108 FAN_PWM_REAR1 Output: Rear fan
GPIOE05/FANPWM3 Standby 109 FAN_PWM_6PIN Output: 6-pin fan
GPIOE06/FANTACH1 Standby 111 FAN_TACH_FRONT1 Input: Front fan tach 1
GPIOE07/FANTACH2 Standby 112 FAN_TACH_FRONT2 Input: Front fan tach 2
GPIOE00/RI2_N/IRTX VDD3 118 SIO_RI2_N COM2
GPIOE01/SIN2/RI2* VDD3 119 SIO_SIN2 COM2
GPIOE02/SOUT2/IRRX VDD3 120 SIO_SOUT2 COM2
GPIOE03/DSR2_N_SIN2 VDD3 121 SIO_DSR2_N COM2
GPIOE04/CTS2_N/DSR2* VDD3 124 SIO_CTS2_N COM2
GPIOE05/DCD2_N/CTS2* VDD3 126 SIO_DCD2_N COM2
GPIOE06/IRRX/DTR_BOUT2 VDD3 127 RISER_PRESENT2 Input: riser card
GPIOE07/IRTX/DCD2* VDD3 128 2U_RISER_DETECT Input: 2U riser card
GPIOE10/5V_DDCSDA Standby 116 HR_SMB_P5VSB_DAT SMB
GPIOE11/5V_DDCSCL Standby 114 HR_SMB_P5VSB_CLK SMB
GPIOE12/CC_DDCSDA Standby 115 HR_SMB_3V3SB_DAT SMB
GPIOE13/CC_DDCSCL Standby 113 HR_SMB_3V3SB_CLK SMB
GPIOE12/PCIRST_OUT2_N Standby 74 PCIRST_N_R Output: PCIRST
GPIOE13 Standby 75 PCIE_WAKE_N Input: PCIE-Wake up
GPIOE14 Standby 101 PME_N Input: PCI PME#
GPIOE16 Standby 100 DIMM_FRULED_B1_N Output: DIMM FRU
GPIOE17 Standby 80 PME_PCIX_N Input: PCI-X PME#
GPO11/VsbStrap1 Standby 117 SIO_VSBSTRAP1 SIO Strapping
GPO12/RTS2_N/SOUT2/VddStrap1 VDD3 122 SIO_RTS2_N COM2
GPO13/DTR_BOUT2/RTS2_N/VddStrap2 VDD3 125 SIO_DTR2_N COM2
GPIO15 Standby 91 DIMM_FRULED_B2_N Output: DIMM FRU
Signal Name Function Description
PWM 1
PWM 1
PWM
present
detect
buffer
signal
LED for 1B
LED for 2B
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Functional Architecture
3.3.2 Serial Ports
The board provides two serial ports, an external serial port, and an internal serial header. The
following sections provide details on the use of the serial ports.
3.3.2.1 Serial A
Serial A is a standard DB9 interface located at the rear I/O panel of the server boards, to the left
of the video connector below the parallel port connector. Serial A is designated by as “Serial A”
on the silkscreen. The reference designator is J4.
3.3.2.2 Serial B
Serial B is an optional port, accessed through a 9-pin internal header. A standard DH-10 to DB9
cable can be used to direct serial B to an external connector on any given chassis. The serial B
interface follows the standard RS232 pinout. The server boards have a “Serial_B” silkscreen
label next to the connector and is located beside the PCI-X slot 1 connector.
3.3.2.3 Floppy Disk Controller
The floppy disk controller (FDC) in the Super I/O is functionally compatible with floppy disk
controllers in the DP8473 and N844077. All FDC functions are integrated into the Super I/O
including analog data separator and 16-byte FIFO. The server boards provide a standard 34-pin
interface for the floppy disk controller.
3.3.2.4 Keyboard and Mouse
Two external PS/2 ports, located on the back of the server boards, provide access to the
keyboard and mouse functions.
3.3.2.5 Wake-up Control
The Super I/O contains functionality that allows various events to control the power-on and
power-off the system.
3.4 BIOS Flash
The board incorporates an Intel® FWH flash memory component. The 82802AC is a highperformance 8-megabit memory component and non-volatile storage space. The flash device is
connected through the LPC interface of 6300ESB.
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3.5 SM Bus Block Diagram
See below for the SM Bus block diagram and device addresses.
Figure 5. Intel® Server Boards SE7320EP2 and SE7525RP2 SMBUS Block Diagram
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Clock Generation and Distribution
4. Clock Generation and Distribution
All buses on the Intel Server Boards SE7320EP2 / SE7525RP2 operate using synchronous
clocks. Clock synthesizer/driver circuitry on the server board generates clock frequencies and
voltage levels as required, including the following:
200 MHz at 0.7V current-mode: For processor 0, processor 1, debug port and MCH
66 MHz at 3.3 V logic levels: For MCH, 6300ESB ICH
48 MHz at 3.3V logic levels: For 6300ESB ICH
33 MHz at 3.3V logic levels: For 6300ESB ICH, PCI connector, Super I/O
14.318 MHz at 2.5 V logic levels: For 6300ESB ICH , Super I/O and video
The following figure illustrates clock generation and distribution on the board.
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Clock Generation and Distribution
Figure 6. Intel® Server Boards SE7320EP2 and SE7525RP2 Clock Distribution Diagram
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