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Revision 1.7
February, 2018
Intel Server Products and Solutions
Intel® Server Board S1200SP
Product Family
Technical Product Specification
A document providing an overview of product features, functions, architecture, and
support specifications
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Intel® Server Board S1200SP Family Technical Product Specification
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Intel® Server Board S1200SP Family Technical Product Specification
Date
Revision
Number
Modifications
Dec. 2015
1.0
Initial version
March 2016
1.1
Added S1200SPO.
September, 2016
1.2
Add TPM2.0 support; Update Enterprise M.2 support
January , 2017
1.3
Added E3-1200 V6 processors support
March, 2017
1.4
Added Intel® SGX for E3-1200 V6
November, 2017
1.5
Updated Table 62. POST Progress Codes. Changed 34h instead of 32h CPU
Init
December, 2017
1.6
Replace RAID key name RKSATA8R5 with RKSATA4R5 in sections 2.1 and
3.4.3
Added commercial name AXXTPMSPE6 on TPM2.0, sections 4.3 and 8.3.2
February, 2018
1.7
Modified note of 2400Mhz DIMMs usage
Revision History
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Intel® Server Board S1200SP Family Technical Product Specification
Disclaimers
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this
document.
Intel disclaims all express and implied warranties, including without limitation, the implied warranties of
merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from
course of performance, course of dealing, or usage in trade.
This document contains information on products, services and/or processes in development. All information
provided here is subject to change without notice. Contact your Intel representative to obtain the latest TPS.
The products and services described may contain defects or errors known as errata which may cause
deviations from published specifications. Current characterized errata are available on request.
Intel, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others
© 2018 Intel Corporation.
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Intel® Server Board S1200SP Family Technical Product Specification
Table of Contents
1 Introduction .................................................................................................................................................................. 1
1.1 Chapter Outline ............................................................................................................................................................................ 1
1.2 Server Board Use Disclaimer ................................................................................................................................................... 1
2 Overview ....................................................................................................................................................................... 2
2.1 Intel® Server Board S1200SP Family Feature Set ........................................................................................................... 2
2.2 Server Board Layout ................................................................................................................................................................... 4
2.2.1 Server Board Connector and Component Layout .................................................................................................. 5
2.2.2 Server Board Mechanical Drawings .............................................................................................................................. 8
2.2.3 Server Board Rear I/O Layout ...................................................................................................................................... 14
3 Functional Architecture ........................................................................................................................................... 15
3.1 Processor Subsystem .............................................................................................................................................................. 15
3.1.1 Intel® Xeon® processor E3-1200 V5 Product Family ........................................................................................... 16
3.1.2 The 6th Generation Intel® Core™ i3 Processors ....................................................................................................... 16
3.2 Processor Function Overview ............................................................................................................................................... 16
3.3 Integrated Memory Controller (IMC) and Memory Subsystem ............................................................................... 17
3.3.1 Supported Memory .......................................................................................................................................................... 18
3.3.2 Memory RAS Features ..................................................................................................................................................... 21
3.3.3 Post Error Codes ................................................................................................................................................................ 21
3.3.4 Processor Integrated I/O Module (IIO) ...................................................................................................................... 22
3.3.5 Intel® Integrated RAID Option ....................................................................................................................................... 22
3.3.6 Optional I/O Module Support ...................................................................................................................................... 23
3.3.7 Intel® I/O Acceleration Technolgy 2 (Intel® I/O AT2) ............................................................................................. 23
3.4 Intel® C230 Series Chipset PCH Functional Overview ................................................................................................ 23
3.4.1 Digital Media Interface (DMI) ........................................................................................................................................ 24
3.4.2 PCI Express* Interface ..................................................................................................................................................... 24
3.4.3 Serial ATA (SATA) Controller ......................................................................................................................................... 24
3.4.4 Low Pin Count (LPC) Interface ..................................................................................................................................... 26
3.4.5 Serial Peripheral Interface (SPI) ................................................................................................................................... 26
3.4.6 Universal Serial Bus (USB) Controller ....................................................................................................................... 26
3.4.7 Gigabit Ethernet Controller ........................................................................................................................................... 27
3.4.8 Serial Ports ........................................................................................................................................................................... 28
3.4.9 KVM/Serial Over LAN (SOL) Function ....................................................................................................................... 28
3.4.10 System Management Bus (SMBus* 2.0) .................................................................................................................. 29
3.4.11 Intel® Virtualization Technology for Direct I/O (Intel® VT-d) ........................................................................... 29
3.5 Integrated Baseboard Management Controller (BMC) Overview .......................................................................... 29
3.5.1 Super I/O Controller ......................................................................................................................................................... 30
3.5.2 Remote Keyboard, Video, Mouse, and Storage (KVMS) .................................................................................... 31
3.5.3 Graphics Controller and Video Support .................................................................................................................. 31
4 System Security ........................................................................................................................................................ 33
4.1 BIOS Password Protection ..................................................................................................................................................... 33
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4.2 Trusted Platform Module (TPM) Support ........................................................................................................................ 34
4.2.1 TPM security BIOS ............................................................................................................................................................ 34
4.2.2 Physical Presence .............................................................................................................................................................. 35
4.2.3 TPM Security Setup Options ........................................................................................................................................ 35
4.3 Intel® Trusted Execution Technology ................................................................................................................................. 37
5 Intel® Technology Support ...................................................................................................................................... 38
5.1 Intel® Trusted Execution Technology ................................................................................................................................. 38
5.2 Intel® Virtualization Technology – Intel® VT-x/VT-d/VT-c ......................................................................................... 38
5.3 Intel® Intelligent Power Node Manager ............................................................................................................................ 39
5.3.1 Hardware Requirements ................................................................................................................................................. 41
6 Platform Management Functional Overview ..................................................................................................... 42
6.1 Baseboard Management Controller (BMC) Firmware Feature Support .............................................................. 42
6.1.1 IPMI 2.0 Features ............................................................................................................................................................... 42
6.1.2 Non-IPMI Features ............................................................................................................................................................ 43
6.2 Basic and Advanced Features ............................................................................................................................................. 43
6.3 Advanced Configuration and Power Interface (ACPI) ................................................................................................ 44
6.4 Power Control Sources ............................................................................................................................................................ 45
6.5 BMC Watchdog .......................................................................................................................................................................... 45
6.6 Fault Resilient Booting (FRB) ................................................................................................................................................ 46
6.7 Sensor Monitoring .................................................................................................................................................................... 47
6.8 Field Replaceable Unit (FRU) Inventory Device ............................................................................................................. 47
6.9 System Event Log (SEL) .......................................................................................................................................................... 47
6.10 System Fan Management..................................................................................................................................................... 47
6.10.1 Thermal and Acoustic Management ........................................................................................................................ 48
6.10.2 Thermal Sensor Input to Fan Speed Control ....................................................................................................... 48
6.10.3 Auto Profiles ...................................................................................................................................................................... 49
6.10.4 Memory Thermal Throttling ....................................................................................................................................... 50
6.11 Messaging Interfaces ............................................................................................................................................................. 50
6.11.1 User Model ......................................................................................................................................................................... 51
6.11.2 IPMB Communication Interface ................................................................................................................................. 51
6.11.3 LAN Interface ..................................................................................................................................................................... 52
6.11.4 Address Resolution Protocol (ARP) .......................................................................................................................... 57
6.11.5 Internet Control Message Protocol (ICMP) ............................................................................................................ 57
6.11.6 Virtual Local Area Network (VLAN) .......................................................................................................................... 57
6.11.7 Secure Shell (SSH) ........................................................................................................................................................... 58
6.11.8 Serial-over-LAN (SOL 2.0) ............................................................................................................................................ 58
6.11.9 Platform Event Filter (PEF) ........................................................................................................................................... 58
6.11.10 LAN Alerting .................................................................................................................................................................... 59
6.11.11 Alert Policy Table .......................................................................................................................................................... 59
6.11.12 SM-CLP (SM-CLP Lite) ................................................................................................................................................. 60
6.11.13 Embedded Web Server .............................................................................................................................................. 60
6.11.14 Virtual Front Panel ........................................................................................................................................................ 62
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6.11.15 Embedded Platform Debug ...................................................................................................................................... 63
6.11.16 Data Center Management Interface (DCMI) ....................................................................................................... 65
6.11.17 Lightweight Directory Access Protocol (LDAP) ................................................................................................. 65
7 Advanced Management Feature Support (RMM4) ............................................................................................ 66
7.1 Dedicated Management Port ............................................................................................................................................... 66
7.2 Keyboard, Video, and Mouse (KVM) Redirection .......................................................................................................... 66
7.2.1 Remote Console ................................................................................................................................................................. 67
7.2.2 Performance ........................................................................................................................................................................ 68
7.2.3 Security .................................................................................................................................................................................. 68
7.2.4 Availability ............................................................................................................................................................................ 68
7.2.5 Usage ...................................................................................................................................................................................... 68
7.2.6 Force-enter BIOS Setup .................................................................................................................................................. 68
7.3 Media Redirection ..................................................................................................................................................................... 68
7.3.1 Availability ............................................................................................................................................................................ 69
7.3.2 Network Port Usage ......................................................................................................................................................... 69
8 On-board Connector/Header Overview .............................................................................................................. 70
8.1 Board Connector Information .............................................................................................................................................. 70
8.2 Power Connectors ..................................................................................................................................................................... 71
8.3 System Management Headers ............................................................................................................................................ 72
8.3.1 Intel® Remote Management Module 4 Lite Connector ....................................................................................... 72
8.3.2 TPM Connector .................................................................................................................................................................. 73
8.3.3 Intel® ESRT2 RAID Upgrade Key Connector............................................................................................................ 73
8.3.4 HSBP SMBUS Header ...................................................................................................................................................... 73
8.3.5 Chassis Intrusion Header ............................................................................................................................................... 74
8.3.6 SATA SGPIO Header ......................................................................................................................................................... 74
8.3.7 IPMB Connector ................................................................................................................................................................. 74
8.4 Front Panel Connector ............................................................................................................................................................ 74
8.4.1 Power/Sleep Button and LED Support..................................................................................................................... 75
8.4.2 System ID Button and LED Support .......................................................................................................................... 75
8.4.3 System Reset Button Support...................................................................................................................................... 75
8.4.4 NMI Button Support ......................................................................................................................................................... 76
8.4.5 NIC Activity LED Support ............................................................................................................................................... 76
8.4.6 Hard Drive Activity LED Support ................................................................................................................................. 76
8.4.7 System Status LED Support .......................................................................................................................................... 76
8.5 I/O Connectors ........................................................................................................................................................................... 76
8.5.1 VGA Connector ................................................................................................................................................................... 76
8.5.2 Display Port Connector ................................................................................................................................................... 77
8.5.3 SATA Connectors ............................................................................................................................................................... 77
8.5.4 M.2 SATA Connector (J2G1) .......................................................................................................................................... 78
8.5.5 Serial Port Connector ...................................................................................................................................................... 79
8.5.6 USB Connector ................................................................................................................................................................... 80
8.5.7 I/O Module Connector ..................................................................................................................................................... 81
8.5.8 SAS/ROC Module Connector ........................................................................................................................................ 82
8.5.9 NIC Connector .................................................................................................................................................................... 83
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8.6 Fan Headers ................................................................................................................................................................................ 83
9 Jumper Blocks ........................................................................................................................................................... 85
9.1 BIOS Default Jumper (J4C1) ................................................................................................................................................. 86
9.2 BIOS Recovery Jumper (J7B1) ............................................................................................................................................. 86
9.3 Password Clear Jumper (J1F4) ............................................................................................................................................ 87
9.4 Management Engine (ME) Firmware Force Update Jumper (J1F1) ...................................................................... 88
9.5 BMC Force Update Jumper (J4B1) ..................................................................................................................................... 88
10 Intel® Light Guided Diagnostics .......................................................................................................................... 90
10.1 System ID LED ........................................................................................................................................................................... 90
10.2 System Status LED .................................................................................................................................................................. 90
10.3 BMC Boot/Reset Status LED Indicators .......................................................................................................................... 92
10.4 Post Code Diagnostic LEDs .................................................................................................................................................. 93
10.5 5 Volt Stand-By Present LED ............................................................................................................................................... 93
11 Environmental Limits Specification .................................................................................................................. 94
11.1 Processor Thermal Design Power (TDP) Support ....................................................................................................... 94
11.2 MTBF ............................................................................................................................................................................................. 95
12 Server Board Power Distribution ...................................................................................................................... 96
12.1 DC Output Specification ....................................................................................................................................................... 96
12.1.1 Output Power/Currents ................................................................................................................................................. 96
12.1.2 Standby Output ................................................................................................................................................................ 97
12.1.3 Voltage Regulation .......................................................................................................................................................... 97
12.1.4 Dynamic Loading ............................................................................................................................................................. 97
12.1.5 Capacitive Loading .......................................................................................................................................................... 97
12.1.6 Grounding ........................................................................................................................................................................... 98
12.1.7 Closed loop stability ....................................................................................................................................................... 98
12.1.8 Residual Voltage Immunity in Standby Mode ...................................................................................................... 98
12.1.9 Common Mode Noise .................................................................................................................................................... 98
12.1.10 Soft Starting .................................................................................................................................................................... 98
12.1.11 Zero Load Stability Requirements.......................................................................................................................... 99
12.1.12 Hot Swap Requirements............................................................................................................................................. 99
12.1.13 Forced Load Sharing .................................................................................................................................................... 99
12.1.14 Ripple / Noise ................................................................................................................................................................. 99
Appendix A. Integration and Usage Tips ............................................................................................................... 102
Appendix B. Integrated BMC Sensor Tables.......................................................................................................... 103
Appendix C. POST Code Diagnostic LED Decoder ............................................................................................... 120
Appendix D. POST Code Errors ................................................................................................................................ 126
Appendix E. Supported Intel® Server Chassis ....................................................................................................... 129
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Glossary ........................................................................................................................................................................... 130
Reference Documents ................................................................................................................................................... 133
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List of Figures
Figure 1. Intel® Server Board S1200SP Layout (S1200SPL) ..................................................................................................... 4
Figure 2. Intel® Server Board S1200SPL Layout ......................................................................................................................... 5
Figure 3. Intel® Server Board S1200SPS Layout ........................................................................................................................ 6
Figure 4. Intel® Server Board S1200SPO Layout ........................................................................................................................ 7
Figure 5. Intel® Server Board S1200SP – Mounting Hole Locations ........................................................................................ 8
Figure 6. Intel® Server Board S1200SP – Mounting Hole Locations (continued) .................................................................. 9
Figure 7. Intel® Server Board S1200SP – Major Connector Pin-1 Locations ........................................................................ 10
Figure 8. Intel® Server Board S1200SP – Major Connector Pin-1 Locations (continued) .................................................. 11
Figure 9. Intel® Server Board S1200SP – Primary Side Keepout Zone ................................................................................. 12
Figure 10. Intel® Server Board S1200SP – Second Side Keepout Zone ............................................................................... 13
Figure 11. Intel® Server Board S1200SPL Rear I/O Layout ..................................................................................................... 14
Figure 12. Intel® Server Board S1200SPS Rear I/O Layout ..................................................................................................... 14
Figure 13. Intel® Server Board S1200SPO Rear I/O Layout .................................................................................................... 14
Figure 13. Intel® Server Board S1200SP Functional Block Diagram ..................................................................................... 15
Figure 14. Intel® Server Board S1200SP DIMM Slot Layout ................................................................................................... 20
Figure 15. Intel® Server Board S1200SP Series USB Mapping Diagram............................................................................... 26
Figure 16. Integrated BMC Functional Block Diagram ............................................................................................................ 30
Figure 17. Setup Utility – TPM Configuration Screen ............................................................................................................. 36
Figure 18. Fan Speed Control Process ...................................................................................................................................... 49
Figure 19. Intel® RMM4 Lite Activation Key Installation ......................................................................................................... 66
Figure 20. Installing M.2 Device ................................................................................................................................................. 78
Figure 21. Installing Intel® Integrated RAID Module ............................................................................................................... 82
Figure 22. Fan Headers on the Server Borad ........................................................................................................................... 84
Figure 23. Jumper Blocks (J4B1, J1F1, J1F4 J7B1, J4C1) ..................................................................................................... 85
Figure 24. On-Board LED Placement ......................................................................................................................................... 90
Figure 25. Power Distribution Block Diagram .......................................................................................................................... 96
Figure 26. Differential Noise Test Setup ................................................................................................................................... 99
Figure 27. Turn On/Off Timing (Power Supply Signals) ....................................................................................................... 101
Figure 28. POST Code Diagnostic LEDs .................................................................................................................................. 120
Figure 29. Processor Heatsink Installation ............................................................................................................................ 129
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List of Tables
Table 1. Intel® Server Board S1200SP Feature Set .................................................................................................................... 2
Table 2. Limiting Conditions of PCIe* Card Form Factor .......................................................................................................... 3
Table 3. UDIMM Support Guidelines ......................................................................................................................................... 18
Table 4. Intel® Server Board S1200SP DIMM Nomenclature .................................................................................................. 19
Table 5. Intel® Server Board S1200SP DIMM Maximum Configuration ................................................................................ 20
Table 6. Intel® C230 Series Chipset Features ........................................................................................................................... 23
Table 7. External RJ45 NIC Port LED Definition ...................................................................................................................... 28
Table 8. Onboard Video Resolution and Refresh Rate (Hz) .................................................................................................... 31
Table 9. TPM Setup Utility – Security Configuration Screen Fields ...................................................................................... 36
Table 10. Intel® Intelligent Power Node Manager .................................................................................................................... 39
Table 11. Intel® Intelligent Power Node Manager Capabilities and Features (SPS 4.x) ...................................................... 40
Table 12. Basic and Advanced Features .................................................................................................................................... 43
Table 13. ACPI Power States ...................................................................................................................................................... 44
Table 14. Power Control Initiators ............................................................................................................................................. 45
Table 15. Messaging Interfaces .................................................................................................................................................. 50
Table 16. Factory Configured PEF Table Entries...................................................................................................................... 59
Table 17. Diagnostic Data ........................................................................................................................................................... 64
Table 18. Additional Diagnostics on Error ................................................................................................................................ 65
Table 19. Intel® Remote Management Module 4 (RMM4) Options ........................................................................................ 66
Table 20. Board Connector Matrix ............................................................................................................................................. 70
Table 21. Main Power Connector Pin-out (J9H1) .................................................................................................................... 71
Table 22. CPU Power Connector Pin-out (J9B1) ...................................................................................................................... 71
Table 23. PMBUS SSI Connector Pin-out (J9F1) ...................................................................................................................... 72
Table 24. Battery Holder (BT2F1) .............................................................................................................................................. 72
Table 25. Stacked connector of USB 3.0+ dedicated RJ45 Management Port Pin-out (JA5A1) ....................................... 72
Table 26. Intel® RMM4 – Lite Connector Pin-out (J3B1) .......................................................................................................... 73
Table 27. TPM Connector Pin-out (J8K1) ................................................................................................................................. 73
Table 28. Intel® ESRT2 RAID Upgrade Key Connector Pin-out (J9K1) .................................................................................. 73
Table 29. HSBP SMBUS Header Pin-out (J3K3) ....................................................................................................................... 73
Table 30. Chassis Intrusion Header Pin-out (J9B2) ................................................................................................................ 74
Table 31. SATA SGPIO Header Pin-out (J2K5, J2K6) .............................................................................................................. 74
Table 32. IPMB Connector Pin-out (J1G2) ................................................................................................................................ 74
Table 33. Front Panel 24-pin Connector Pin-out (J9E1)......................................................................................................... 75
Table 34. Power/Sleep LED Functional States ......................................................................................................................... 75
Table 35. NMI Signal Generation and Event Logging .............................................................................................................. 76
Table 36. VGA Connector Pin-out (J8A1) ................................................................................................................................. 77
Table 37. Display Port Connector Pin-out (J4A1) ................................................................................................................... 77
Table 38. SATA/SATADOM capable Connector Pin-out (J1K4, J1K1, J1K5, J1K2, J2K4, J2K3, J2K1, J2K2) ................. 78
Table 39. M.2 SATA Connector Pinout ...................................................................................................................................... 79
Table 40. Internal 9-pin Serial Header Pin-out (J9A1) ........................................................................................................... 79
Table 41. USB 2.0 FP Header (J1J2) .......................................................................................................................................... 80
Table 42. USB3.0 FP Header (J1J1) ........................................................................................................................................... 80
Table 43. USB 2.0 Connector (Rear IO) (J6A1) ......................................................................................................................... 80
Table 44. Internal Type A USB Port Pin-out (J1K3) ................................................................................................................. 80
Table 45. I/O Module Connector Pin-out (J1C1) ..................................................................................................................... 81
Table 45. I/O Module Connector Pin-out (J4J1) ...................................................................................................................... 82
Table 46. NIC Connector Pin-out (JA7A1, J6A2) ..................................................................................................................... 83
Table 47. SSI 4-pin Fan Header Pin-out (J3K2, J8B1, J7K1, J8K2, J8K3) ............................................................................ 84
Table 48. Server Board Jumpers (J4B1, J1F1, J1F4, J7B1, J4C1) ......................................................................................... 86
Table 49. System Status LED State Definitions........................................................................................................................ 91
Table 50. BMC Boot/Reset Status LED Indicators ................................................................................................................... 93
Table 51. Server Board Design Specifications ......................................................................................................................... 94
Table 52. MTBF Estimate ............................................................................................................................................................ 95
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Table 53. Minimum Load Ratings............................................................................................................................................... 96
Table 54. Voltage Regulation Limits .......................................................................................................................................... 97
Table 55. Transient Load Requirements ................................................................................................................................... 97
Table 56. Capacitive Loading Conditions ................................................................................................................................. 98
Table 57. Ripples and Noise ....................................................................................................................................................... 99
Table 58. Timing Requirements ............................................................................................................................................... 100
Table 59. Integrated BMC Core Sensors ................................................................................................................................. 105
Table 60. POST Progress Code LED Example ........................................................................................................................ 121
Table 61. POST Progress Codes ............................................................................................................................................... 121
Table 62. MRC Progress Codes ................................................................................................................................................. 123
Table 63. POST Progress LED Codes ....................................................................................................................................... 124
Table 64. POST Error Codes and Messages ............................................................................................................................ 126
Table 65. POST Error Beep Codes ........................................................................................................................................... 128
Table 66. Integrated BMC Beep Codes .................................................................................................................................... 128
Table 67. Compatible Intel® Server Chassis P4000S Family ................................................................................................ 129
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Intel® Server Board S1200SP Family Technical Product Specification
1 Introduction
This Technical Product Specification (TPS) provides board specific information detailing the features,
functionality, and high-level architecture of the Intel® Server Board S1200SP family.
Design-level information related to specific server board components and subsystems can be obtained by
ordering External Product Specifications (EPS) or External Design Specifications (EDS) related to this server
generation. EPS and EDS documents are made available under NDA with Intel® and must be ordered through
your local Intel® representative. See the Reference Documents section for a list of available documents.
1.1 Chapter Outline
This document is divided into the following chapters:
• Chapter 1 – Introduction
• Chapter 2 – Overview
• Chapter 3 – Functional Architecture
• Chapter 4 – System Security
• Chapter 5 – Intel® Technology Support
• Chapter 6 – Platform Management Functional Overview
• Chapter 7 – Advanced Management Feature Support (RMM4)
• Chapter 8 – On-board Connector/Header Overview
• Chapter 9 – Jumper Blocks
• Chapter 10 – Intel® Light Guided Diagnostics
• Chapter 11 – Environmental Limits Specifications
• Chapter 12 – Server Board Power Distribution
• Appendix A – Integration and Usage Tips
• Appendix B – Integrated BMC Sensor Tables
• Appendix C – POST Code Diagnostic LED Decoder
• Appendix D – POST Code Errors
• Appendix E – Supported Intel® Server Chassis
• Glossary
• Reference Documents
1.2 Server Board Use Disclaimer
Intel® server boards support add-in peripherals and contain a number of high-density Very Large Scale
Integration (VLSI) and power delivery components that need adequate airflow to cool. Intel ensures through
its own chassis development and testing that when Intel server building blocks are used together, the fully
integrated system will meet the intended thermal requirements of these components. It is the responsibility
of the system integrator who chooses not to use Intel® developed server building blocks to consult vendor
datasheets and operating parameters to determine the amount of airflow required for their specific application
and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server
board does not operate correctly when used outside any of their published operating or non-operating limits.
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Intel® Server Board S1200SP Family Technical Product Specification
S1200SPL
S1200SPS
S1200SPO
Form Factor
MicroATX 9.6”x9.6” compliant form factor
Processor
Support for one Intel
®
Xeon® E3-1200 V5 and V6 processor in an LGA 1151 Socket H4 package with
Thermal Design Power up to 80W
S1200SPL supports Intel
®
Xeon® processor E3-1200 V5 and V6 processor graphics (GT2 or 4+2),
S1200SPS and S1200SPO supports Intel® Xeon® processor E3-1200 V5 and V6 without processor
graphics (GT0 or 4+0).
8 GT/s point-to-point DMI 3.0 interface to PCH
Chipset
Intel® C236 Platform Controller
Hub (PCH) chipset
Intel® C232 Platform Controller
Hub (PCH) chipset
Intel® C236 Platform Controller
Hub (PCH) chipset
Memory
Two memory channels, four memory DIMMs (Two memory DIMMs per channel)
Support for 2133 MT/s Unbuffered (UDIMM DDR4 ECC memory)
Max Memory
64GB
Add-in PCI Express*
Slots and Module
Connectors Number
4
See Note.
3
See Note.
3
Add-in PCI Express*
Slots and Module
Connectors
Configuration
PCI Express* Gen3 x8 electrical
with x16 physical connector, from
processor
PCI Express* Gen3 x8 electrical
with x16 physical connector, from
processor
PCI Express* Gen3 x 8 electrical
with x16 physical connectors,
from processor
PCI Express* Gen3 x4 electrical
with x8 physical connector, from
PCH
PCI Express* Gen3 x4 electrical
with x8 physical connector, from
PCH
PCI Express* Gen3 x8 I/O module
connector, from processor
PCI Express* Gen3 x8 electrical
with x8 physical connector, from
processor
PCI Express* Gen3 x8 electrical
with x8 physical connector, from
processor
PCI Express* Gen3 x4 SAS
module connector, from PCH
PCI Express* Gen3 x4 SAS
module connector, from PCH
Ethernet
Two Gigabit Ethernet Ports through the two Intel® Ethernet Controller I210 PHYs
Storage
8x SATA connectors at 6Gbps
2x SGPIO
1x HSBP I
2
C
1x SATADOM connector
(SATA port 4)
6x SATA connectors at 6Gbps
1x SGPIO
1x HSBP I
2
C
1x SATADOM connector
(SATA port 4)
8x SATA connectors at 6Gbps
2x SGPIO
1x HSBP I
2
C
1x SATADOM connector
(SATA port 4)
SSD
1x 75 pin connector for
enterprise M.2 SATA SSD (2242
form factor)
N/A
1x 75 pin connector for
enterprise M.2 SATA SSD (2242
form factor)
SW RAID
Intel
®
RSTe 4.x SW RAID through onboard SATA connectors provides SATA RAID 0/1/10/5.
Intel
®
Embedded Server RAID Technology II through onboard SATA connectors provides SATA RAID
0/1/10 and optional RAID 5 support provided by the Intel® RAID Activation Key RKSATA4R5.
2 Overview
The Intel® Server Board S1200SP product family consist of S1200SPS and S1200SPL. The server boards are
monolithic printed circuit boards (PCBs) with features designed to support the pedestal or rack server markets.
These server boards are designed to support the Intel® Xeon® processor E3-1200 V5 and V6 product family.
Previous generation Intel® Xeon® processors are not supported. Many of the features and functions of these
three server boards are common. A board will be identified by name when a described feature or function is
unique to it.
2.1 Intel
®
Server Board S1200SP Family Feature Set
Table 1. Intel® Server Board S1200SP Feature Set
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Intel® Server Board S1200SP Family Technical Product Specification
S1200SPL
S1200SPS
S1200SPO
Video
Display Port from CPU
Integrated 2D video controller
in BMC
Integrated 2D video controller
in BMC
Integrated 2D video controller
in BMC
Video Connector
1x Display Port
1x DB-15 video connector
1x DB-15 video connector
ISM
BMC
IPMI 2.0
1x on-board dedicated RMM4
NIC connector
BMC
IPMI 2.0
BMC
IPMI 2.0
1x on-board dedicated RMM4
NIC connector
Intel® Remote Management
Module 4 Lite solutions
N/A
Intel® Remote Management
Module 4 Lite solutions
TPM
TPM 2.0 based on LPC
N/A
TPM 2.0 based on LPC
USB
2x USB 3.0 ports at the back
of the board
2x USB 2.0 ports at the back
of the board
One 2x10 pin USB 3.0 header,
providing front panel support
for two USB ports respectively
One 2x5 pin USB 2.0 header,
providing front panel support
for two USB ports respectively
1x internal Type-A USB 2.0
port
2x USB 3.0 ports at the back
of the board
2x USB 2.0 ports at the back
of the board
One 2x5 pin USB 2.0 header,
providing front panel support
for two USB ports respectively
1x internal Type-A USB 2.0
port
2x USB 3.0 ports at the back
of the board
2x USB 2.0 ports at the back
of the board
One 2x10 pin USB 3.0 header,
providing front panel support
for two USB ports respectively
One 2x5 pin USB 2.0 header,
providing front panel support
for two USB ports respectively
1x internal Type-A USB 2.0
port
PCIe Slot #
Conditions for full height and half length card
Conditions for full height and ¾ length card
4
Mezzanine SAS module is installed or SATA port 4-7 are
occupied.
Mezzanine slot and SATA port 4-7 are not occupied.
5
Mezzanine SAS module is installed or SATA port 0-3 are
occupied.
Mezzanine slot and SATA port 0-3 are not occupied.
6
Mezzanine SAS module is installed.
Mezzanine slot is not occupied.
Note: The server board S1200SPL and S1200SPS support full height full length PCIe* cards. See the
following table for the limitations when the server boards is installed in server chassis P4000XXSFDR.
Table 2. Limiting Conditions of PCIe* Card Form Factor
3
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Intel® Server Board S1200SP Family Technical Product Specification
2.2 Server Board Layout
Figure 1. Intel® Server Board S1200SP Layout (S1200SPL)
4
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Intel® Server Board S1200SP Family Technical Product Specification
2.2.1 Server Board Connector and Component Layout
Each connector and major component is identified in the figure below.
Figure 2. Intel® Server Board S1200SPL Layout
5
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Intel® Server Board S1200SP Family Technical Product Specification
Figure 3. Intel® Server Board S1200SPS Layout
6
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Intel® Server Board S1200SP Family Technical Product Specification
Figure 4. Intel® Server Board S1200SPO Layout
7
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Intel® Server Board S1200SP Family Technical Product Specification
2.2.2 Server Board Mechanical Drawings
Figure 5. Intel® Server Board S1200SP – Mounting Hole Locations
8
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Intel® Server Board S1200SP Family Technical Product Specification
Figure 6. Intel® Server Board S1200SP – Mounting Hole Locations (continued)
9
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Intel® Server Board S1200SP Family Technical Product Specification
Figure 7. Intel® Server Board S1200SP – Major Connector Pin-1 Locations
10
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Intel® Server Board S1200SP Family Technical Product Specification
Figure 8. Intel® Server Board S1200SP – Major Connector Pin-1 Locations (continued)
11
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Intel® Server Board S1200SP Family Technical Product Specification
Figure 9. Intel® Server Board S1200SP – Primary Side Keepout Zone
12
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Intel® Server Board S1200SP Family Technical Product Specification
Figure 10. Intel® Server Board S1200SP – Second Side Keepout Zone
13
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Intel® Server Board S1200SP Family Technical Product Specification
2.2.3 Server Board Rear I/O Layout
The following drawing shows the layout of the rear I/O components for the server boards.
Figure 11. Intel® Server Board S1200SPL Rear I/O Layout
Figure 12. Intel® Server Board S1200SPS Rear I/O Layout
Figure 13. Intel® Server Board S1200SPO Rear I/O Layout
14
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Intel® Server Board S1200SP Family Technical Product Specification
PCIe Gen3 x 4 P5-P8
FLASHFLASH
LPC
PORT 80
LED
RMII
VIDEO
FLASHFLASH
BMC Boot
Flash
SPI
Zoar
BMC
Pilot III
Springville
Ch A Ch B
DDR4 (Ch B)
XDP0
DMI Gen3 x 4
PCIe Gen3 x 1 P12
PCIe Gen3 x 1 P11
USB 2.0
4 DDR4
UDIMM
GbE
GbE
DDR4 (Ch A)
FLASH
DRAM
SERIAL A
Back
Panel
Back
Panel
Back
Panel
SPI
DDR4-2133 (POR)
SGPIO
Springville
USB
2
USB 3.0
(include 2.0 pair)
USB
1.1
USB
2.0
14
6
HDD
8
SATA 6G
Back
Panel
USB 3.0
LPC TPM Header
PCIe Gen3 x4 P1-P4
2
P13-16,17-20
P1-P2
Front Panel
USB 3.0
Header
SAS
Module
Silver Pass Block Diagram
CPLD
Phy
GbE
Mgmt LAN
Back
Panel
RGMII
Misc
VR s
VCC[0:2]
Vddq
Vtt
VCCio
VCCsa
VDDq
Vtt
Vpp
Slot 6
(x16 connector)
(x8 connectors)
Resister
Switch
Slot 5
Slot 4
(LC/SE SKU)
(x8 connectors)
PCIe Gen3 x 1 P10
P1 P5
P3-P4
2
P2,P4
USB
Back
Panel
USB 2.0
2
P10,P12
2
P9,P11
Skylake-S
SKT-H4
PCIe Gen3 x8 P0-P7
SKL PCH-H
PCH
PCIe Gen3 x8 P8-P15
IOM
(RO SKU)
Resistor
MUX
Note: Slot4 and IOM is exclusive
M.2 SATA SSD (2242
Form-Factor)
Note: A Separate
Cable Connection to
either 8 SATA Pin
required to support M.2
SATA SSD
RMM4 Lite
Front Panel
USB 2.0
Header
P6,P8
2
Internal
Type-A
P3
PCIe Gen3 x 1 P9
Note: NA for SE SKU.
Note: Work in Gen1 Mode
Note: Work in Gen1 Mode
Note: Work in Gen1 Mode
Note: Build-in SATADOM
Support on SATA P4
DP x1 Rear
Panel
VCCgt[0:3]
VCCopio
VCCEDRAM
VCCgtu
V1V8_EDRAM
Note: unslice,
OPIO, EDRAM,
P1V8_EDRAM
is reserved for
44e Support.
FLASH
DP to VGA
FLASH
MUX
3 Functional Architecture
The architecture and design of the Intel® Server Board S1200SP is based on the Intel® C230 series chipset. The
chipset is designed for systems based on the Intel® Xeon® processor in an LGA 1151 Socket H4 package.
The Intel® Server Board S1200SPS uses Intel® C232 chipset. The Intel® Server Board S1200SPL and Intel® Server
Board S1200SPO use Intel® C236 chipset.
The Intel® Xeon® Processor E3-1200 V5 and V6 Processors are made up of multi-core processors based on the
14nm processor technology. The 6th Intel® Core™ i3 Processors are made up of dual-core processors based on
the 14nm processor technology.
This chapter provides a high-level description of the functionality associated with each chipset component
and the architectural blocks that make up the server boards.
3.1 Processor Subsystem
The Intel® Server Board S1200SP supports the following processor:
• Intel® Xeon® processor E3-1200 V5 and V6 product family
• The 6th Generation Intel® Core™ i3 processors
Note: The previous generation Intel® Xeon® processors are not supported on the Intel® server board described
in this document.
15
Figure 14. Intel® Server Board S1200SP Functional Block Diagram
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Intel® Server Board S1200SP Family Technical Product Specification
3.1.1 Intel
Intel® Xeon® processor E3-1200 V5 and V6 product family highly integrated solution variant is composed of
quad processor cores:
• LGA 1151 socket package with 8 GT/s
• Up to 80 W Thermal Design Power (TDP)
The list of supported processors may be found at:
https://intelserver.exaltsolutions.com/exodus/page?eventType=1&targetPageId=1201
Note: The workstation processor is not supported in this platform.
®
Xeon® processor E3-1200 V5 and V6 Product Family
3.1.2 The 6
The 6th Generation Intel® Core™ i3 Processors highly integrated solution variant is composed of Duo cores:
• FC-LGA 1151 socket package with 8 GT/s
• Up to 65 W Thermal Design Power (TDP); processors with higher TDP are not supported
The list of supported processors may be found at:
https://intelserver.exaltsolutions.com/exodus/page?eventType=1&targetPageId=1201
th
Generation Intel® Core™ i3 Processors
3.2 Processor Function Overview
With the release of the Intel® Xeon® processor E3-1200 V5 and V6 product family, several key system
components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been
combined into a single processor package and feature; up to 20 lanes of Gen 3 PCI Express* links.
The following sections provide an overview of the key processor features and functions that help to define the
performance and architecture of the server board. For more comprehensive processor specific information,
refer to the Intel® Xeon® processor E3-1200 V5 and V6 product family documents listed in the Reference
Documents list.
Processor feature details:
• Up to four execution cores
• Each core supports two threads (Intel® Hyper-Threading Technology), up to 8 threads per socket
Supported technologies:
• Intel® Virtualization Technology (Intel® VT)
• Intel® Active Management Technology 11.0 (Intel® AMT 11.0)
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Hyper-Threading Technology (Intel® HT Technology)
• Intel® 64 Architecture
• Execute Disable Bit
• Intel® Turbo Boost Technology 2.0
• Intel® Advanced Vector Extensions 2 (Intel® AVX2)
• Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
• PCLMULQDQ (Perform Carry-Less Multiplication Quad word) Instruction
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Intel® Server Board S1200SP Family Technical Product Specification
• Intel® Secure Key
• Intel® Transactional Synchronization Extensions (Intel® TSX-NI)
• PAIR – Power Aware Interrupt Routing
• SMEP – Supervisor Mode Execution Protection
• On-package Cache Memory
• Intel® Memory Protection Extensions (Intel® MPX)
• GMM Scoring Accelerator
• Intel® Image Signal Processor (Intel® ISP)
• Intel® Processor Trace
3.2.1 Intel® SGX Software Guard Extensions
Note: Intel® SGX is available for family processors Intel®E3-1200 V5 and Intel®E3-1200 V6. This feature is
currently enabled on S1200SPOR.
Intel® SGX is a system of architectural enhancement defined to help protect application integrity and
confidentiality of data, and to withstand SW and certain HW attacks. Intel® SGX will allow the application
developer to provide application security without dependency on the correctness of the OS, VMM, BIOS,
drivers, etc.
Protect
• Enables trusted memory regions (trusted enclaves)
• Isolates enclaves from malware and privileged
software attacks
• Processor controls access, prevents intrusion,
encrypts transported/stored data
Limitations
• Intel® Server Board S1200SP family firmware does not support monotonic counters and trusted time
features
• Some SGX use models such as distributed ledger with Proof of Elapsed Time (PoET) consensus
algorithm can’t be supported
3.3 Integrated Memory Controller (IMC) and Memory Subsystem
Integrated into the processor is a memory controller. Only ECC memory is supported on this platform. Each
processor provides two DDR4 Unbuffered Dual In-Line Memory Modules (UDIMM) channels that support the
following:
• ECC Unbuffered DDR4
• Single-channel and dual-channel memory organization modes
• Data burst length of eight cycles for all memory organization modes
• Memory DDR4 data transfer rates of 1866, and 2133 MT/s
• 64-bit wide channels
• DDR4 I/O Voltage of 1.2 V
• Theoretical maximum memory bandwidth of:
- 29.8 GB/s in dual-channel mode assuming 1867 MT/s
- 34.1 GB/s in dual-channel mode assuming 2133 MT/s
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Intel® Server Board S1200SP Family Technical Product Specification
Ranks
Per
DIMM
and
Data
Width
Memory Capacity Per DIMM
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)
2 Slots per Channel
1DPC
2DPC
1.2V
1.2V
SRx8
ECC
4GB
8GB
1866, 2133
1866, 2133
2400 (only Intel E3-1200 V6)
2400 (only Intel E3-1200 V6)
DRx8
ECC
8GB
16GB
1866, 2133
1866, 2133
2400 (only Intel E3-1200 V6)
2400 (only Intel E3-1200 V6)
• Gb and 8 Gb DDR4 DRAM device technologies are supported
- Using 4 Gb DRAM device technologies, the largest system memory capacity possible is 32 GB,
assuming Dual Channel Mode with four x8 dual ranked DIMM memory configuration
• The memory channels are named as Channel A and Channel B.
• The memory slots are named as Slot1 and Slot2 on each channel. Slot2 is the nearest from the processor
socket.
• DIMMs are named to reflect the channel and slot in which they are installed:
- Channel A, Slot1 is DIMM_A1.
- Channel A, Slot2 is DIMM_A2.
- Channel B, Slot1 is DIMM_B1.
- Channel B, Slot2 is DIMM_B2.
3.3.1 Supported Memory
• Single Ranked x8 unbuffered ECC
• Dual Ranked x8 unbuffered ECC
Table 3. UDIMM Support Guidelines
Note: Note: In case of using 2400 MHz memory modules with Intel E3-1200 v5 processor, the speed of the
memory will be reduced to 2133 MHz.
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Intel® Server Board S1200SP Family Technical Product Specification
(0)
Channel A
(1)
Channel B
A1
A2
B1
B2
Notes:
1. No support for RDIMMs.
2. No support for SODIMM.
3. All channels in a system run at the fastest common frequency.
4. Mixing ECC and non-ECC UDIMMs anywhere on the platform is not supported.
5. Static CLTT supported using BMC (requires ECC DIMMs with thermal sensor).
3.3.1.1 Memory Population Rules
Note: Although mixed DIMM configurations are supported, Intel® only performs platform validation on
systems that are configured with identical DIMMs installed.
The processor provides two channels of memory, each capable of supporting up to two DIMMs.
• DIMMs are organized into physical slots on DDR4 memory channels that belong to processor socket.
• The silk screened DIMM slot identifiers on the board provide information about the channel. For example,
DIMM_A1 is the first slot on Channel A on processor.
• Channel A and Channel B are independent and are not required to have the same number of DIMMs
installed. Either channel may be used for a single-DIMM configuration.
• When only one memory channel is populated, the memory runs in Single Channel mode, with no
interleaving.
• When using one or two memory modules, populate the farthest slot in the channel. On Intel® Server Board
S1200SP, the farthest slot in the channels are A2 and B2 with blue connectors.
On the Intel® Server Board S1200SP, a total of 4 DIMM slots is provided. The nomenclature for DIMM
sockets is detailed in the following table.
Table 4. Intel® Server Board S1200SP DIMM Nomenclature
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Intel® Server Board S1200SP Family Technical Product Specification
Max Memory Possible
4Gb DRAM Technology
8Gb DRAM Technology
Single Rank UDIMM
16GB
(4 x 4GB DIMMs)
32GB
(4 x 8GB DIMMs)
Dual Rank UDIMMs
32GB
(4x 8GB DIMMs)
64GB
(4 x 16GB DIMMs)
Figure 15. Intel® Server Board S1200SP DIMM Slot Layout
Table 5. Intel® Server Board S1200SP DIMM Maximum Configuration
3.3.1.2 Publishing System Memory
• The BIOS displays the Total Memory of the system during POST if Display Logo is disabled in the BIOS
setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual
sizes of installed DDR4 DIMMs in the system.
• The BIOS displays the Effective Memory of the system in the BIOS setup. The term Effective Memory
refers to the total size of all DDR4 DIMMs that are active (not disabled).
• The BIOS provides the total memory of the system in the main page of the BIOS setup. This total is the
same as the amount described by the first bullet above.
• If Display Logo is disabled, the BIOS displays the total system memory on the diagnostic screen at the end
of POST. This total is the same as the amount described by the first bullet above.
Note: Some server operating systems do not display the total physical memory installed. What is displayed is
the amount of physical memory minus the approximate memory space used by system BIOS components.
These BIOS components include, but are not limited to:
1. ACPI (may vary depending on the number of PCI devices detected in the system)
2. ACPI NVS table
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Intel® Server Board S1200SP Family Technical Product Specification
3. Processor microcode
4. Memory Mapped I/O (MMIO)
5. Manageability Engine (ME)
6. BIOS flash
3.3.2 Memory RAS Features
For Intel® Server Board S1200SP product family, the form of Memory RAS provided is Error Correction Code
(ECC). ECC uses extra bits – 64-bit data in a 72-bit DRAM array – to add an 8-bit calculated Hamming Code to
each 64 bits of data. This additional encoding enables the memory controller to detect and report single or
double bit errors, and to correct single-bit errors.
There is a specific step in memory initialization in which all of memory is cleared to zeroes before the ECC
function is enabled, in order to bring the ECC codes into agreement with memory contents.
During operation, in the process of every fetch from memory, the data and ECC bits are examined for each 64bit data plus 8-bit ECC group. If the ECC computation indicates that a single bit Correctable Error has occurred,
it is corrected and the corrected data is passed on to the processor. If a double-bit Uncorrectable Error is
detected, it cannot be corrected. In each case, a Correctable or Uncorrectable ECC Error event is generated.
For Correctable Errors, there is a certain tolerance observed, since a Correctable Error can be generated by
something as random as a stray Cosmic Ray impacting the DIMM. Correctable Errors are counted on a perDIMM basis, but are just silently recorded until the tolerance threshold is crossed. The Correctable Error
Threshold for Intel® Server Board S1200SP product family board is set at 10 events. When the 10th CE occurs,
a single Correctable Error event is logged.
3.3.3 Post Error Codes
The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST, this same range
of POST code values is used for reporting other system errors.
• 0xE8 – No Usable Memory Error: If no usable memory is available, the BIOS emits a beep code and
displays POST Diagnostic LED code 0xE8 and halts the system.
• This can also occur if all memory in the system fails and/or has become disabled during memory
initialization. For example, if a DDR4 DIMM has no SPD information, the BIOS treats the DIMM slot as if no
DDR4 DIMM is present on it. Therefore, if this is the only DDR4 DIMM installed in the system, there is no
usable memory, and the BIOS goes to a memory error code 0xE8 as described above.
• 0x53/0x55/0XE8: DIMM SPD does not respond or DIMM SPD Read Error, the DIMM will not be detected,
if the SPD does not respond, which could result in No memory Installed or No Usable Memory Error Halt
0X53, 0x55, or 0xE8, or could result later in an invalid configuration if the no SPD DIMM is in Slot 1 on the
channel.
• 0x51 – Memory SPD Error: If the DIMM does respond but the SPD cannot be successfully read, that would
cause a Memory SPD Error, memory error halt 0X51. For each memory channel, once the DIMM SPD
parameters have been read, they are checked to verify that the DIMMs on the channel are a valid
configuration, DIMM speed and size, ECC capability, and in which memory slot the DIMMs are installed. An
invalid configuration will cause the system to halt.
• 0xEA – Channel Training Error: If the memory initialization process is unable to properly perform the
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Intel® Server Board S1200SP Family Technical Product Specification
Data/Data Strobe timing training on a memory channel, the BIOS emits a beep code and displays POST
Diagnostic LED code 0xEA momentarily during the beeping. If there is usable memory in the system on
the other channel, POST memory initialization continues. Otherwise, the system beeps and halts with
POST Diagnostic LED code 0xEA staying displayed.
• 0x54/0xEB – Memory Test Error: If a DDR4 DIMM or a set of DDR4 DIMMs on the same memory channel
fails memory testing but usable memory remains available, the BIOS emits a beep code and displays POST
Diagnostic LED code 0xEB momentarily during the beeping, then continues POST. If all of the memory fails
memory testing, then system memory error code 0xE8 (No Usable Memory) as described above.
• 0xED – Population Error or Invalid DIMM: If the installed memory contains an invalid DIMM configuration
on either channel in the system, the system beeps and halts with POST Diagnostic LED code 0xED. The
DIMM are installed incorrectly, not following the Fill Farthest First rule (Slot 2 must be filled before Slot 1).
This will result in a DIMM Population Error, with a Memory Error Halt 0xED.
3.3.4 Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset components.
The integrated I/O module provides the following features:
PCI Express* Interfaces
The integrated I/O module incorporates the PCI Express* interface and supports up to 16 lanes of PCI
Express*. Following are key attributes of the PCI Express* interface:
- Gen3 speeds at 8 GT/s (no 8b/10b encoding)
- Can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s
The Intel® Server Board S1200SPL and Intel® Server Board S1200SPS support PCIe* slots:
- Slot 6: PCI Express* Gen3 x8 electrical with x16 physical connector, from processor.
- Slot 5: PCI Express* Gen3 x4 electrical with x8 physical connector, from PCH.
- Slot 4: PCI Express* Gen3 x8 electrical with x8 physical connector, from processor.
The Intel® Server Board S1200SPO supports PCIe slot:
- Slot 6: PCI Express* Gen3 x8 electrical with x16 physical connector, from processor.
Direct Media Interface (DMI)
Direct Media Interface (DMI) connects the processor and the PCH. DMI2.0 is supported.
Note: Only DMI Gen3 x4 configuration is supported.
- DMI 2.0 support
- Compliant to Direct Media Interface Second Generation (DMI2).
- Four lanes in each direction.
- 8 GT/s point-to-point DMI interface to PCH is supported.
3.3.5 Intel
The Intel® Server Board S1200SPL and S1200SPO provide a SAS/ROC Mezzanine slot (J4J1) to a high density
80-pin connector labeled SAS_MOD for the installation of an optional Intel® Integrated RAID Module.
Features of this option include:
22
®
Integrated RAID Option
Page 37
Intel® Server Board S1200SP Family Technical Product Specification
C232
C236
Flex I/O Support
Yes
Yes
Total SATA 3.0 Ports
6
Up to 8
Total PCIe* Lanes
14
UP to 20
Total USB 3.0 Ports
6
Up to 10
Total USB 2.0 Ports
12
14
ME FW
SPS
SPS and ME11
SATA Express Capable Port
No
Up to 3
CPU pGFX
No
Yes
• SKU options to support full or entry level hardware RAID
• Dual-core 6Gb SAS/SATA ROC/IOC (LSI* 2208 and 2308)
• 12Gb SAS ROC/IOC (LSI* 3008 and 3108)
• 4 or 8 ports and SAS/SATA or SATA
• SKU options to support 512MB or 1GB embedded memory
• Intel® designed flash plus optional support for Intel® RAID Maintenance Free Backup Units
(AXXRMFBU2/AXXRMFBU5) or Intel® RAID Smart Battery AXXRSBBU9.
For supported SAS modules, refer to the document Intel® Server Boards S1200SP Configuration Guide and
Spares/Accessories List.
For additional product information, refer to the document Intel® Integrated RAID Module RMS25KB080,
RMS25KB040, RMS25CB080, and RMS25CB040 Hardware User’s Guide.
3.3.6 Optional I/O Module Support
To broaden the standard on board feature set, the Intel® Server Board S1200SPO provides support for one of
several available IO Module options. The I/O Module attaches to a high density 80-pin connectors on the server
board (J1C1) labeled I/O_MOD and is supported by up to x8 PCIe Gen 3 signals from IIO module of the
processor.
For supported I/O Modules, refer to the document Intel® Server Boards S1200SP Configuration Guide and
Spares/Accessories List
3.3.7 Intel
®
I/O Acceleration Technolgy 2 (Intel® I/O AT2)
Intel® I/O AT2 is not supported.
3.3.7.1 Direct Cache Access (DCA)
Direct Cache Access (DCA) is not supported on Intel® Xeon® Processor E3-1200 V5 and V6 series.
3.4 Intel
The following subsections provide an overview of the key features and functions of the Intel® C230 series
chipset PCH used on the server board. For more comprehensive chipset specific information, refer to the Intel®
C230 series chipset documents listed in the Reference Document list.
®
C230 Series Chipset PCH Functional Overview
Table 6. Intel® C230 Series Chipset Features
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Intel® Server Board S1200SP Family Technical Product Specification
On the Intel® Server Boards S1200SP, the chipset provides support for the following on-board functions:
• Digital Media Interface (DMI) to Processor
• PCI Express* Interface
• Serial ATA (SATA) Controller
• AHCI
• Rapid Storage Technology enterprise (RSTe)
• Low Pin Count (LPC) interface
• Serial Peripheral Interface (SPI)
• Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
• Advanced Programmable Interrupt Controller (APIC)
• Universal Serial Bus (USB) Controller
• Gigabit Ethernet Controller
• RTC
• GPIO
• Enhanced Power Management
• Manageability
• System Management Bus (SMBus* 2.0)
• Integrated NVSRAM controller
• Virtualization Technology for Direct I/O (Intel® VT-d)
• JTAG Boundary-Scan
• KVM/Serial Over LAN (SOL) Function
3.4.1 Digital Media Interface (DMI)
Digital Media Interface (DMI) is the chip-to-chip connection between the processor and the Intel® C230 series
chipset. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic
and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting
current and legacy software to operate normally.
3.4.2 PCI Express* Interface
The Intel® C230 series chipset provides up to 20 PCI Express* Root Ports, supporting the PCI Express* Base
Specification, Revision 3.0. Each Root Port x1 lane supports up to 8 Gb/s bandwidth in each direction (16 Gb/s
concurrent). On the Intel® Server Board S1200SPL and S1200SPO, PCI Express* Root Ports 1-4 are configured
to support one Gen3 x4 port widths of SAS Module connector; on the Intel® Server Board S1200SPL and
S1200SPS, PCI Express* Root Ports 5-8 are configured to support one Gen3 x4 port widths of slot 5. On the
Intel® Server Boards S1200SP family product, PCI Express* Root Port 10 is configured to support one Gen1 x1
widths connection with the BMC chip; PCI Express* Root Port 11 and 12 are configured to support two Gen1
x1 widths connection with the two Intel® I210 Gigabit Ethernet Network controller.
3.4.3 Serial ATA (SATA) Controller
The Intel® C230 series chipset provides:
• SATA host controllers that support independent DMA operation on up to eight ports and supports data
transfer rates of up to 6.0 Gb/s (600 MB/s). The SATA controller contains two modes of operation – a legacy
mode using I/O space, and an AHCI mode using memory space. Software that uses legacy mode will not
have AHCI capabilities. The Intel® C230 series chipset supports the Serial ATA Specification, Revision 3.0.
24
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Intel® Server Board S1200SP Family Technical Product Specification
The Intel® C230 series also supports several optional sections of the Serial ATA II: Extensions to Serial ATA
1.0 Specification, Revision 1.0 (AHCI support is required for some elements).
• One M.2 SATA SSD 2242 Module with a separate SATA cable to any of the on-board SATA Connector
• Two 5-pin SATA SGPIO connectors, one to cover drive 0-3 with SDATAOUT0, the other to cover drive 4-7
with SDATAOUT1
• SATADOM with native power from SATA connector directly on port 4 (cable-less)
• AHCI
The Intel® C230 series chipset provides hardware support for Advanced Host Controller Interface (AHCI), a
standardized programming interface for SATA host controllers. Platforms supporting AHCI may take
advantage of performance features such as no master/slave designation for SATA devices—each device is
treated as a master—and hardware assisted native command queuing. AHCI also provides usability
enhancements such as Hot-Plug. AHCI requires appropriate software support (for example, an AHCI driver)
and for some features, hardware support in the SATA device or additional platform hardware.
The server board includes support for two embedded software RAID options:
• Intel® Embedded Server RAID Technology 2 (ESRT2) based on LSI* MegaRAID SW RAID technology
• Intel® Rapid Storage Technology (RSTe)
Using the <F2> BIOS Setup Utility, accessed during system POST, options are available to enable/disable SW
RAID, and select which embedded software RAID option to use.
3.4.3.1 Intel
The Intel® C230 series chipset provides support for Intel® Rapid Storage Technology enterprise, providing both
AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability
provides high-performance RAID 0, 1, 5, and 10 functionality on up to 8 SATA ports of the Intel® C230 series
chipset. RSTe RAID support is provided to allow multiple RAID levels to be combined on a single set of hard
drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot-spare support, SMART alerting,
and RAID 0 auto replace. Software components include an Option ROM for pre-boot configuration and boot
functionality, a Microsoft Windows* compatible driver, and a user interface for configuration and management
of the RAID capability of the Intel® C230 series chipset.
3.4.3.2 Intel
Features of the embedded software RAID option Intel® Embedded Server RAID Technology 2 (ESRT2) include
the following:
• Based on LSI* MegaRAID Software Stack
• Software RAID with system providing memory and CPU utilization
• Supported RAID Levels – 0, 1, 10
• RAID 5 support provides with upgrade key of RKSATA4R5. RAID 5 under legacy BIOS mode is not
supported.
• Open Source Compliance = Binary Driver (includes Partial Source files) or Open Source using MDRAID layer
in Linux*
• OS Support = Microsoft Windows 2012*, Microsoft Windows 2008*, RHEL*, SLES, and other Linux* variants
using partial source builds
• Utilities = Microsoft Windows* GUI and CLI, Linux* GUI and CLI, DOS CLI, and EFI CLI
®
Rapid Storage Technology Enterprise
®
Embedded Server RAID Technology 2 (ESRT2)
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Intel® Server Board S1200SP Family Technical Product Specification
3.4.4 Low Pin Count (LPC) Interface
The Intel® C230 series chipset implements an LPC Interface as described in the LPC 1.1 Specification and
provides support for up to two Master/DMI devices. On the server board, the LPC interface is utilized as an
interconnection between the chipset and the Integrated Base Board Management Controller as well as
providing support for the optional Trusted Platform Module (TPM).
3.4.5 Serial Peripheral Interface (SPI)
The Intel® C230 series chipset implements an SPI Interface as an alternative interface for the BIOS flash device.
3.4.6 Universal Serial Bus (USB) Controller
The Intel® C230 series chipset contains an eXtensible Host Controller Interface (xHCI) host controller which
supports up to fourteen USB 2.0 ports and up to six USB 3.0 ports. This controller allows data transfers of up
to 5Gb/s. The controller supports SuperSpeed (SS), high-speed (HS), full-speed (FS), and low speed (LS) traffic
on the bus.
Figure 16. Intel® Server Board S1200SP Series USB Mapping Diagram
3.4.6.1 Native USB Support
During the power-on self-test (POST), the BIOS initializes and configures the USB subsystem. The BIOS can
initialize and use the following types of USB devices:
• USB Specification-compliant keyboards
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Intel® Server Board S1200SP Family Technical Product Specification
• USB Specification-compliant mouse
• USB Specification-compliant storage devices that utilize bulk-only transport mechanism
USB devices are scanned to determine if they are required for booting.
The BIOS supports USB 2.0 mode of operation, and as such supports USB 1.1 and USB 2.0 compliant devices
and host controllers.
During the pre-boot phase, the BIOS automatically supports the hot addition and hot removal of USB devices
and a short beep is emitted to indicate such an action. For example, if a USB device is hot plugged, the BIOS
detects the device insertion, initializes the device, and makes it available to the user. During POST, when the
USB controller is initialized, it emits a short beep for each USB device in the system as if they were all just “hot
added”.
Only on-board USB controllers are initialized by BIOS. This does not prevent the operating system from
supporting any available USB controllers including add-in cards.
3.4.6.2 Legacy USB Support
The BIOS supports PS/2 emulation of USB keyboards and mouse. During POST, the BIOS initializes and
configures the root hub ports and searches for a keyboard and/or a mouse on the USB hub and then enables
the devices that are recognized.
3.4.7 Gigabit Ethernet Controller
Network connectivity is provided by means of two onboard Intel® Ethernet Controller I210 providing up to two
10/100/1000 Mb Ethernet ports. The Intel® Ethernet Controller I210 is single, compact, low-power
components that offer a fully-integrated Gigabit Ethernet Media Access Control (MAC) and Physical Layer
(PHY) port. The Intel® Ethernet Controller I210 uses the PCI Express* architecture from the Intel® C230 series
PCH and provides a single-port implementation in a relatively small area so it can be used for server and client
configurations as a LAN on Motherboard (LOM) design.
External interfaces provided on the I210:
• PCIe Rev. 2.0 (2.5 GHz) x1
• MDI (Copper) standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASETX, and 10BASE-T
applications (802.3, 802.3u, and 802.3ab)
• NC-SI or SMBus* connection to a Manageability Controller (MC)
• EEE 1149.1 JTAG (note that BSDL testing is NOT supported)
Each Ethernet port drives two LEDs located on each network interface connector. The LED at the right of the
connector is the link/activity LED and indicates network connection when on, and transmit/receive activity
when blinking. The LED at the left of the connector indicates link speed as defined in the following table.
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Intel® Server Board S1200SP Family Technical Product Specification
LED Color
LED State
NIC State
Green/Amber (Right)
Off
10 Mbps
Amber
100 Mbps
Green
1000 Mbps
Green (Left)
On
Active Connection
Blinking
Transmit/Receive activity
Table 7. External RJ45 NIC Port LED Definition
3.4.7.1 MAC Address Definition
Intel® Server Board S1200SPL and S1200SPO have the following MAC addresses assigned to them at the
factory:
• NIC 1 MAC address (for OS usage)
• NIC 2 MAC address = NIC 1 MAC address + 1 (for OS usage)
• BMC LAN channel 1 MAC address = NIC1 MAC address + 2
• BMC LAN channel 2 MAC address = NIC1 MAC address + 3
• BMC LAN channel 3 (DMN) MAC address = NIC1 MAC address + 4
Intel® Server Board S1200SPS has the following MAC addresses assigned to it at the factory:
• NIC 1 MAC address (for OS usage)
• NIC 2 MAC address = NIC 1 MAC address + 1 (for OS usage)
• BMC LAN channel 1 MAC address = NIC1 MAC address + 2
• BMC LAN channel 2 MAC address = NIC1 MAC address + 3
3.4.8 Serial Ports
The server board provides a nine-pin internal DH-10 serial header. You can use a standard DH-10 to DB9 cable
to direct serial A port to the rear of a chassis.
3.4.9 KVM/Serial Over LAN (SOL) Function
These functions support redirection of keyboard, mouse, and text screen to a terminal window on a remote
console. The keyboard, mouse, and text redirection enables the control of the client machine through the
network without the need to be physically near that machine. Text, mouse, and keyboard redirection allows
the remote machine to control and configure the client by entering BIOS setup. The KVM/SOL function
emulates a standard PCI serial port and redirects the data from the serial port to the management console
using LAN. KVM has additional requirements of internal graphics and SOL may be used when KVM is not
supported.
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Intel® Server Board S1200SP Family Technical Product Specification
3.4.10 System Management Bus (SMBus* 2.0)
The Intel® C230 series chipset contains a SMBus* Host interface that allows the processor to communicate with
SMBus* slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented.
The Intel® C230 series chipset’s SMBus* host controller provides a mechanism for the processor to initiate
communications with SMBus* peripherals (slaves). Also, the Intel® C230 series chipset supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols
of the SMBus* interface (see System Management Bus (SMBus*) Specification, Version 2.0): Quick Command,
Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The Intel® C230 series chipset’s SMBus* also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus* devices.
3.4.11 Intel
The Intel® C230 series chipset provides hardware support for implementation of Intel® Virtualization
Technology with Directed I/O (Intel® VT-d). Intel® VT-d Technology consists of technology components that
support the virtualization of platforms based on Intel® Architecture Processors. Intel® VT-d Technology enables
multiple operating systems and applications to run in independent partitions. A partition behaves like a Virtual
Machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset
of host physical memory.
®
Virtualization Technology for Direct I/O (Intel® VT-d)
3.5 Integrated Baseboard Management Controller (BMC)
Overview
The Integrated BMC is provided by an embedded ARM9* controller and associated peripheral functionality
that is required for IPMI-based server management. Firmware usage of these hardware features is platform
dependent.
The following is a summary of the Integrated BMC management hardware features that comprise the BMC:
• IPMI 2.0 Compliant
• 400MHz 32-bit ARM9* processor with memory management unit (MMU)
• Two independent 10/100/1000 Mb/s Ethernet Controllers with RMII/RGMII support
• DDR2/3 16-bit interface with up to 800 MHz operation
• Sixteen 10-bit ADCs
• Sixteen fan tachometers
• Eight Pulse Width Modulators (PWM)
• Chassis intrusion logic
• JTAG Master
• Eight I2C interfaces with master-slave and SMBus* timeout support. All interfaces are SMBus* 2.0
compliant.
• Parallel general-purpose I/O Ports (16 direct, 32 shared)
• Serial general-purpose I/O Ports (80 in and 80 out)
• Three UARTs
• Platform Environmental Control Interface (PECI)
• Six general-purpose timers
• Interrupt controller
• Multiple Serial Peripheral Interface (SPI) flash interfaces
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Intel® Server Board S1200SP Family Technical Product Specification
Graphics
Controller
BMC & KVMS Subsystem
Super I/O Subsystem Graphics Subsystem
RTC &
General Purpose
TImers (6)
UART
(3)
I2C
(8)
Crypto
Accelerator
LPC to SPI
Flash Bridge
Watchdog
Timer
Real Time Clock
Interface
(external RTC)
LPC
Interface
To Host
RGB
Video
Output
PCIe x1
Interface
DDR-II/III
(800MHz)
JTAG
Master
BMC Boot
Flash
USB
to Host
Integrated BMC Pilot-3 Block Diagram
System
Wakeup
Control
KCS
BT &
Mailboxes
GPIO/SGPIOUART (2)
LPC
Interface
ARM926EJ-S
16K D & I
Cache
400MHz
Interrupt
Controller
Fan Tach (16)
PWM (8)
ADC(16)
PECI3.0
10/100/1000
Ethernet MAC
with
RMII/RGMII (2)
USB 1.1
&
USB 2.0
SPI Flash
BOOT & BKUP
DDR-II/III
16-bit
Memory
Controller
JTAG
Debug
Port
JTAG
Master
LPC
Master
LPC
Master
BMC Data
Flash
RMII/RGMII
To LAN/PHY
• NAND/Memory interface
• Sixteen mailbox registers for communication between the BMC and host
• LPC ROM interface
• BMC watchdog timer capability
• SD/MMC card controller with DMA support
• LED support with programmable blink rate controls on GPIOs
• Port 80h snooping capability
• Secondary Service Processor (SSP), which provides the HW capability of offloading time critical processing
tasks from the main ARM* core.
Figure 17. Integrated BMC Functional Block Diagram
Emulex* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller with the following
features:
3.5.1 Super I/O Controller
The integrated super I/O controller provides support for the following features as implemented on the server
board:
• Keyboard Style/BT interface for BMC support
• Two Fully Functional Serial Ports, compatible with the 16C550
• Serial IRQ Support
• Up to 16 Shared GPIO available for host processor
• Programmable Wake-up Event Support
• Plug and Play Register Set
• Power Supply Control
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Intel® Server Board S1200SP Family Technical Product Specification
2D Mode
2D Video Mode Support (Color Bit)
Resolution
8 bpp
16 bpp
24 bpp
32 bpp
640x480
60, 72, 75, 85
60, 72, 75, 85
Not supported
60, 72, 75, 85
800x600
60, 72, 75, 85
60, 72, 75, 85
Not supported
60, 72, 75, 85
1024x768
60, 70, 75, 85
60, 70, 75, 85
Not supported
60, 70, 75, 85
1152x864
75
75
75
75
1280x800
60
60
60
60
1280x1024
60
60
60
60
1440x900
60
60
60
60
3.5.2 Remote Keyboard, Video, Mouse, and Storage (KVMS)
The Integrated BMC contains a remote KVMS subsystem with the following features:
• USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and floppy
• USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse
• Hardware Based Video Compression and Redirection Logic
• Supports both text and Graphics redirection
• Hardware assisted Video redirection using the Frame Processing Engine
• Direct interface to the Integrated Graphics Controller registers and Frame buffer
• Hardware-based encryption engine
3.5.2.1 Integrated BMC Embedded LAN Channel
The Integrated BMC hardware includes two dedicated 10/100 Mb/s network interfaces. These interfaces are
not shared with the host system. At any time, only one dedicated interface may be enabled for management
traffic. The default active interface is the NIC 1 port.
For these channels, support can be enabled for IPMI-over-LAN and DHCP. For security reasons, embedded
LAN channels have the following default settings:
• IP Address: Static
• All users disabled
3.5.3 Graphics Controller and Video Support
The integrated graphics controller provides support for the following features as implemented on the server
board:
• Integrated Graphics Core with 2D Hardware accelerator
• DDR-3 memory interface supporting up to 128MB of memory, 16MB allocated to graphic
• Supports display resolutions up to 1920 x 1200 16bpp @ 60Hz
• High speed Integrated 24-bit RAMDAC
• Single lane PCI Express* host interface running at Gen 1 speed
The integrated video controller supports all standard IBM VGA modes. The following table shows the 2D
modes supported for both CRT and LCD.
Table 8. Onboard Video Resolution and Refresh Rate (Hz)
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Intel® Server Board S1200SP Family Technical Product Specification
2D Mode
2D Video Mode Support (Color Bit)
Resolution
8 bpp
16 bpp
24 bpp
32 bpp
1600x1200
60
60
Not Supported
Not Supported
1680x1050
60
60
Not Supported
Not Supported
1920x1080
60
60
Not Supported
Not Supported
1920x1200
60
60
Not Supported
Not Supported
Note: Video resolutions at 1600x1200 and higher are only supported through the external video connector
located on the rear I/O section of the server board.
On Intel® Server Board S1200SPL, the display port is supported from the processor. A display port to VGA
convertor and a VGA mux are implemented to enable VGA output from processor graphics. Users can set
“Primary Display” option in BIOS to Add-in Graphics or VGA Port or Display Port and set “VGA Port Output”
option to Onboard Video or Processor Graphics.
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Intel® Server Board S1200SP Family Technical Product Specification
4 System Security
4.1 BIOS Password Protection
The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict
entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering.
There is also an option to require a Power On password entry in order to boot the system. If the Power On
Password function is enabled in Setup, the BIOS will halt early in POST to request a password before
continuing POST.
Both Administrator and User passwords are supported by the BIOS. An Administrator password must be
installed in order to set the User password. The maximum length of a password is 14 characters. A password
can have alphanumeric (a-z, A-Z, 0-9) characters and it is case sensitive. Certain special characters are also
allowed, from the following set:
! @ # $ % ^ & * ( ) - _ + = ?
The Administrator and User passwords must be different from each other. An error message will be displayed
if there is an attempt to enter the same password for one as for the other.
The use of Strong Passwords is encouraged, but not required. In order to meet the criteria for a Strong
Password, the password entered must be at least 8 characters in length, and must include at least one each of
alphabetic, numeric, and special characters. If a weak password is entered, a popup warning message will be
displayed, although the weak password will be accepted.
Once set, a password can be cleared by changing it to a null string. This requires the Administrator password,
and must be done through BIOS Setup or other explicit means of changing the passwords. Clearing the
Administrator password will also clear the User password.
Alternatively, the passwords can be cleared by using the Password Clear jumper if necessary. Resetting the
BIOS configuration settings to default values (by any method) has no effect on the Administrator and User
passwords.
Entering the User password allows the user to modify only the System Time and System Date in the Setup
Main screen. Other setup fields can be modified only if the Administrator password has been entered. If any
password is set, a password is required to enter the BIOS setup.
The Administrator has control over all fields in the BIOS setup, including the ability to clear the User password
and the Administrator password.
It is strongly recommended that at least an Administrator Password be set, since not having set a password
gives everyone who boots the system the equivalent of administrative access. Unless an Administrator
password is installed, any User can go into Setup and change BIOS settings at will.
In addition to restricting access to most Setup fields to viewing only when a User password is entered, defining
a User password imposes restrictions on booting the system. In order to simply boot in the defined boot order,
no password is required. However, the F6 Boot popup prompts for a password, and can only be used with the
Administrator password. Also, when a User password is defined, it suppresses the USB Reordering that occurs,
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Intel® Server Board S1200SP Family Technical Product Specification
if enabled, when a new USB boot device is attached to the system. A User is restricted from booting in anything
other than the Boot Order defined in the Setup by an Administrator.
As a security measure, if a User or Administrator enters an incorrect password three times in a row during the
boot sequence, the system is placed into a halt state. A system reset is required to exit out of the halt state.
This feature makes it more difficult to guess or break a password.
In addition, on the next successful reboot, the Error Manager displays a Major Error code 0048, which also logs
a SEL event to alert the authorized user or administrator that a password access failure has occurred.
4.2 Trusted Platform Module (TPM) Support
Trusted Platform Module (TPM) option is a hardware-based security device that addresses the growing
concern on boot process integrity and offers better data protection. TPM protects the system start-up process
by ensuring it is tamper-free before releasing system control to the operating system. A TPM device provides
secured storage to store data, such as security keys and passwords. In addition, a TPM device has encryption
and hash functions. The server board implements TPM as per TPM PC Client Specifications, revision 1.2, by
the Trusted Computing Group (TCG).
A TPM device is optionally installed onto a high density 14-pin connector labeled TPM and is secured from
external software attacks and physical theft. A pre-boot environment, such as the BIOS and operating system
loader, uses the TPM to collect and store unique measurements from multiple factors within the boot process
to create a system fingerprint. This unique fingerprint remains the same unless the pre-boot environment is
tampered with. Therefore, it is used to compare to future measurements to verify the integrity of the boot
process.
After the system BIOS completes the measurement of its boot process, it hands off control to the operating
system loader and in turn to the operating system. If the operating system is TPM-enabled, it compares the
BIOS TPM measurements to those of previous boots to make sure the system was not tampered with before
continuing the operating system boot process. Once the operating system is in operation, it optionally uses
TPM to provide additional system and data security (for example, Microsoft Vista* supports Bitlocker drive
encryption).
4.2.1 TPM security BIOS
The BIOS TPM support conforms to the TPM PC Client Specific – Implementation Specification for
Conventional BIOS, version 1.2, and to the TPM Interface Specification, version 1.2. The BIOS adheres to the
Microsoft Windows BitLocker* requirement. The role of the BIOS for TPM security includes the following:
• Measures and stores the boot process in the TPM microcontroller to allow a TPM enabled operating
system to verify system boot integrity.
• Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM.
• Produces ACPI TPM device and methods to allow a TPM-enabled operating system to send TPM
administrative command requests to the BIOS.
• Verifies operator physical presence. Confirms and executes operating system TPM administrative
command requests.
• Provides BIOS Setup options to change TPM security states and to clear TPM ownership.
For additional details, refer to the TCG PC Client Specific Implementation Specification, the TCG PC Client
Specific Physical Presence Interface Specification, and the Microsoft BitLocker* Requirement documents.
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Intel® Server Board S1200SP Family Technical Product Specification
4.2.2 Physical Presence
Administrative operations to the TPM require TPM ownership or physical presence indication by the operator
to confirm the execution of administrative operations. The BIOS implements the operator presence indication
by verifying the setup Administrator password.
A TPM administrative sequence invoked from the operating system proceeds as follows:
1. User makes a TPM administrative request through the operating system’s security software.
2. The operating system requests the BIOS to execute the TPM administrative command through TPM ACPI
methods and then resets the system.
3. The BIOS verifies the physical presence and confirms the command with the operator.
4. The BIOS executes TPM administrative commands, inhibits BIOS Setup entry, and boots directly to the
operating system which requested the TPM commands.
4.2.3 TPM Security Setup Options
The BIOS TPM Setup allows the operator to view the current TPM state and to carry out rudimentary TPM
administrative operations. Performing TPM administrative options through the BIOS setup requires TPM
physical presence verification.
Using BIOS TPM Setup, the operator can turn ON or OFF TPM functionality and clear the TPM ownership
contents. After the requested TPM BIOS Setup operation is carried out, the option reverts to No Operation.
The BIOS TPM Setup also displays the current state of the TPM, whether TPM is enabled or disabled and
activated or deactivated. Note that while using TPM, a TPM-enabled operating system or application may
change the TPM state independent of the BIOS setup. When an operating system modifies the TPM state, the
BIOS Setup displays the updated TPM state.
The BIOS Setup TPM Clear option allows the operator to clear the TPM ownership key and allows the operator
to take control of the system with TPM. You use this option to clear security settings for a newly initialized
system or to clear a system for which the TPM ownership security key was lost.
4.2.3.1 Security Screen
To enter the BIOS Setup, press the <F2> function key during boot time when the OEM or Intel® logo displays.
The following message displays on the diagnostics screen and under the Quiet Boot logo screen:
Press <F2> to enter setup
When the Setup is entered, the Main screen displays. The BIOS Setup utility provides the Security screen to
enable and set the user and administrative passwords and to lock out the front panel buttons so they cannot
be used. The Intel® Server Board S1200SP provides TPM settings through the security screen.
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Intel® Server Board S1200SP Family Technical Product Specification
Main
Advanced
Security
Server
Management
Boot Options
Boot Manager
Error! Reference source not
ound.
<Installed/Not Installed>
Error! Reference source not
ound.
<Installed/Not Installed>
Error! Reference source not
ound.
[123aBcDeFgH$#@]
Error! Reference source not
ound.
[123aBcDeFgH$#@]
Error! Reference source not
ound.
Enabled/Disabled
Error! Reference source not
ound.
Enabled/Disabled
Error! Reference source not
ound.
<Displays current TPM Device State>
Error! Reference source not
ound.
No Operation/Turn On/Turn Off/Clear
Ownership
Setup Item
Options
Help Text
Comments
TPM State*
Enabled and
Activated
Enabled and
Deactivated
Disabled and
Activated
Disabled and
Deactivated
Information only.
Shows the current TPM device state.
A disabled TPM device will not execute
commands that use TPM functions and TPM
security operations will not be available.
An enabled and deactivated TPM is in the same
state as a disabled TPM except setting of TPM
ownership is allowed if not present already.
An enabled and activated TPM executes all
commands that use TPM functions and TPM
security operations will be available.
TPM
Administrative
Control**
No Operation
Turn On
Turn Off
Clear Ownership
[No Operation] - No changes to current
state.
[Turn On] - Enables and activates TPM.
[Turn Off] - Disables and deactivates
TPM.
Any Administrative Control operation selected
will require the system to perform a Hard Reset
in order to become effective.
To access this screen from the Main screen, select the Security option.
Figure 18. Setup Utility – TPM Configuration Screen
Table 9. TPM Setup Utility – Security Configuration Screen Fields
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Intel® Server Board S1200SP Family Technical Product Specification
Setup Item
Options
Help Text
Comments
[Clear Ownership] - Removes the TPM
ownership authentication and returns the
TPM to a factory default state.
Note: The BIOS setting returns to [No
Operation] on every boot cycle by
default.
4.3 Intel
®
Trusted Execution Technology
The Intel® Xeon® Processor E3-1200 V5 and V6 Product Family support Intel® Trusted Execution Technology
(Intel® TXT), which is a robust security environment. Designed to help protect against software-based attacks,
Intel® Trusted Execution Technology integrates new security features and capabilities into the processor,
chipset, and other platform components. When used in conjunction with Intel® Virtualization Technology, Intel®
Trusted Execution Technology provides hardware-rooted trust for your virtual applications.
This hardware-rooted security provides a general-purpose, safer computing environment capable of running
a wide variety of operating systems and applications to increase the confidentiality and integrity of sensitive
information without compromising the usability of the platform.
Intel® Trusted Execution Technology requires a computer system with Intel® Virtualization Technology enabled
(both VT-x and VT-d), an Intel® Trusted Execution Technology-enabled processor, chipset, and BIOS,
Authenticated Code Modules, and an Intel® Trusted Execution Technology compatible measured launched
environment (MLE). The MLE could consist of a virtual machine monitor, an OS, or an application. In addition,
Intel® Trusted Execution Technology requires the system to include a TPM v2.0 AXXTPMSPE6, as defined by
the Trusted Computing Group TPM PC Client Specification, Revision 1.2.
When available, Intel® Trusted Execution Technology can be enabled or disabled in the processor using a BIOS
Setup option.
For general information about Intel® TXT, visit the Intel® Trusted Execution Technology website
http://www.intel.com/technology/security/.
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Intel® Server Board S1200SP Family Technical Product Specification
5 Intel
5.1 Intel
The Intel® Xeon® Processor E3-1200 V5 and V6 Product Family support Intel® Trusted Execution Technology
(Intel® TXT), which is a robust security environment designed to help protect against software-based attacks.
Intel® Trusted Execution Technology integrates new security features and capabilities into the processor,
chipset, and other platform components. When used in conjunction with Intel® Virtualization Technology and
Intel® VT for Directed IO, with an active TPM, Intel® Trusted Execution Technology provides hardware-rooted
trust for your virtual applications.
5.2 Intel
Intel® Virtualization Technology consists of three components which are integrated and interrelated, but which
address different areas of Virtualization.
• Intel® Virtualization Technology (VT-x) is processor-related and provides capabilities needed to provide
hardware assist to a Virtual Machine Monitor (VMM).
• Intel® Virtualization Technology for Directed I/O (VT-d) is primarily concerned with virtualizing I/O
efficiently in a VMM environment. This would generally be a chipset I/O feature, but in the Second
Generation Intel® Core™ Processor Family there is an Integrated I/O unit embedded in the processor, and
the IIO is also enabled for VT-d.
• Intel® Virtualization Technology for Connectivity (VT-c) is primarily concerned I/O hardware assist features,
complementary to but independent of VT-d.
Intel® VT-x is designed to support multiple software environments sharing same hardware resources. Each
software environment may consist of OS and applications. The Intel® Virtualization Technology features can
be enabled or disabled in the BIOS setup. The default behavior is disabled.
®
®
®
Technology Support
Trusted Execution Technology
Virtualization Technology – Intel® VT-x/VT-d/VT-c
Intel® VT-d is supported jointly by the Intel® Xeon® Processor E3-1200 V5 and V6 Product Families and The
Intel® C230 series chipset. Both support DMA remapping from inbound PCI Express* memory Guest Physical
Address (GPA) to Host Physical Address (HPA). PCI devices are directly assigned to a virtual machine leading
to a robust and efficient virtualization.
The Intel® S1200SP Server Board Family BIOS publishes the DMAR table in the ACPI Tables. For each DMA
Remapping Engine in the platform, one exact entry of DRHD (DMA Remapping Hardware Unit Definition)
structure is added to the DMAR. The DRHD structure in turn contains a Device Scope structure that describes
the PCI endpoints and/or sub-hierarchies handled by the particular DMA Remapping Engine.
Similarly, there are reserved memory regions typically allocated by the BIOS at boot time. The BIOS marks
these regions as either reserved or unavailable in the system address memory map reported to the OS. Some
of these regions can be a target of DMA requests from one or more devices in the system, while the OS or
executive is active. The BIOS reports each such memory region using exactly one RMRR (Reserved Memory
Region Reporting) structure in the DMAR. Each RMRR has a Device Scope listing the devices in the system that
can cause a DMA request to the region.
For more information on the DMAR table and the DRHD entry format, refer to the Intel® Virtualization
Technology for Directed I/O Architecture Specification. For more general information about VT-x, VT-d, and
VT-c, a good reference is Enabling Intel® Virtualization Technology Features and Benefits White Paper.
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Intel® Server Board S1200SP Family Technical Product Specification
IT Challenge
Requirement
Over-allocation of power
Ability to monitor actual power consumption
Control capability that can maintain a power budget to enable dynamic
power allocation to each server
Under-population of rack space
Control capability that can maintain a power budget to enable increased rack
population
High energy costs
Control capability that can maintain a power budget to ensure that a set
energy cost can be achieved
Capacity planning
Ability to monitor actual power consumption to enable power usage
modeling over time and a given planning period
Ability to understand cooling demand from a temperature and airflow
perspective
Detection and correction of hot
spots
Control capability that reduces platform power consumption to protect a
server in a hot-spot
Ability to monitor server inlet temperatures to enable greater rack
utilization in areas with adequate cooling
5.3 Intel
®
Intelligent Power Node Manager
Data centers are faced with power and cooling challenges that are driven by increasing numbers of servers
deployed and server density in the face of several data center power and cooling constraints. In this type of
environment, Information Technology (IT) needs the ability to monitor actual platform power consumption
and control power allocation to servers and racks in order to solve specific data center problems including the
following issues.
Table 10. Intel® Intelligent Power Node Manager
The requirements listed above are those that are addressed by the Intel® C230 series chipset Management
Engine (ME) and Intel® Intelligent Power Node Manager (NM) technology. The ME/NM combination is a power
and thermal control capability on the platform, which exposes external interfaces that allow IT (through
external management software) to query the ME about platform power capability and consumption, thermal
characteristics, and specify policy directives (for example, set a platform power budget).
Node Manager (NM) is a platform resident technology that enforces power capping and thermal-triggered
power capping policies for the platform. These policies are applied by exploiting subsystem knobs (such as
processor P and T states) that can be used to control power consumption. NM enables data center power
management by exposing an external interface to management software through which platform policies can
be specified. It also implements specific data center power management usage models such as power limiting
and thermal monitoring.
The NM feature is implemented by a complementary architecture utilizing the ME, BMC, BIOS, and an ACPIcompliant OS. The ME provides the NM policy engine and power control/limiting functions (referred to as Node
Manager or NM) while the BMC provides the external LAN link by which external management software can
interact with the feature. The BIOS provides system power information utilized by the NM algorithms and also
exports ACPI Source Language (ASL) code used by OS-Directed Power Management (OSPM) for negotiating
processor P and T state changes for power limiting. PMBus*-compliant power supplies provide the capability
to monitoring input power consumption, which is necessary to support NM.
Following are the some of the applications of Intel® Intelligent Power Node Manager technology:
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Intel® Server Board S1200SP Family Technical Product Specification
Value Vector
Capabilities and Features
SPS 4.x
Node Mgr API
ACPI power meter support
DCMI API support
Node Manager IPMI API support
ACPI support
Monitoring
Platform power telemetry (per node, in multinode systems)
CPU and Memory power telemetry
Support voltage regulators & current monitor
configuration
PMBus 1.2 support
BMC power readings support
Hot-swap controller support
Shared power supply support consistent with
SPS 2.0 (Romley)
Limiting
Platform-level policy limits (16 policies)
Boot mode selection
Core disable
Power limit during boot
Running average power limit
Dynamic core allocation
Hardware Protection
SMART/CLST
Performance &
Characterization
Node Mgr Power Thermal Utility (PTU)
• Platform Power Monitoring and Limiting: The ME/NM monitors platform power consumption and holds
average power over duration. It can be queried to return actual power at any given instance. The power
limiting capability is to allow external management software to address key IT issues by setting a power
budget for each server. For example, if there is a physical limit on the power available in a room, IT can
decide to allocate power to different servers based on their usage – servers running critical systems can
be allowed more power than servers that are running less critical workload.
• Inlet Air Temperature Monitoring: The ME/NM monitors server inlet air temperatures periodically. If there
is an alert threshold in effect, ME/NM issues an alert when the inlet (room) temperature exceeds the
specified value. The threshold value can be set by policy.
• Memory Subsystem Power Limiting: The ME/NM monitors memory power consumption. Memory power
consumption is estimated using average bandwidth utilization information
• Processor Power monitoring and limiting: The ME/NM monitors processor or socket power consumption
and holds average power over duration. It can be queried to return actual power at any given instant. The
monitoring process of the ME will be used to limit the processor power consumption through processor
P-states and dynamic core allocation.
• Core allocation at boot time: Restrict the number of cores for OS/VMM use by limiting how many cores
are active at boot time. After the cores are turned off, the CPU will limit how many working cores are visible
to BIOS and OS/VMM. The cores that are turned off cannot be turned on dynamically after the OS has
started. It can be changed only at the next system reboot.
• Core allocation at run-time: This particular use case provides a higher level processor power control
mechanism to a user at run-time, after booting. An external agent can dynamically use or not use cores in
the processor subsystem by requesting ME/NM to control them, specifying the number of cores to use or
not use.
Table 11. Intel® Intelligent Power Node Manager Capabilities and Features (SPS 4.x)
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Intel® Server Board S1200SP Family Technical Product Specification
5.3.1 Hardware Requirements
NM is supported only on platforms that have the NM FW functionality loaded and enabled on the Management
Engine (ME) in the SSB and that have a BMC present to support the external LAN interface to the ME. NM power
limiting feature requires a means for the ME to monitor input power consumption for the platform. This
capability is generally provided by means of PMBus*-compliant power supplies although an alternative model
using a simpler SMBus* power monitoring device is possible (there is potential loss in accuracy and
responsiveness using non-PMBus* devices). The NM SmaRT/CLST feature requires specific PMBus*-compliant
power supplies as well as additional hardware on the baseboard.
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Intel® Server Board S1200SP Family Technical Product Specification
6 Platform Management Functional Overview
Platform management functionality is supported by several hardware and software components integrated
on the server board that work together to control system functions, monitor and report system health, and
control various thermal and performance features in order to maintain (when possible) server functionality in
the event of component failure and/or environmentally stressed conditions.
This chapter provides a high level overview of the platform management features and functionality
implemented on the server board. For more in depth and design level Platform Management information, refer
to the BMC Core Firmware External Product Specification (EPS) and BIOS Core External Product Specification
(EPS) for Intel® Server products based on the Intel® Xeon® processor E3-1200 V5 and V6 product family.
6.1 Baseboard Management Controller (BMC) Firmware Feature
Support
The following sections outline features that the integrated BMC firmware can support. Support or utilization
for some features is dependent on the server platform in which the server board is integrated and any
additional system level components and options that may be installed.
6.1.1 IPMI 2.0 Features
• Baseboard management controller (BMC)
• IPMI Watchdog timer
• Messaging support, including command bridging and user/session support
• Chassis device functionality, including power/reset control and BIOS boot flags support
• Event receiver device: The BMC receives and processes events from other platform subsystems.
• Field Replaceable Unit (FRU) inventory device functionality: The BMC supports access to system FRU
devices using IPMI FRU commands.
• System Event Log (SEL) device functionality: The BMC supports and provides access to a SEL.
• Sensor Data Record (SDR) repository device functionality: The BMC supports storage and access of system
SDRs.
• Sensor device and sensor scanning/monitoring: The BMC provides IPMI management of sensors. It polls
sensors to monitor and report system health.
• IPMI interfaces
- Host interfaces including system management software (SMS) with receive message queue support,
and server management mode (SMM)
- IPMB interface
- LAN interface that supports the IPMI-over-LAN protocol Remote Management Control Protocol
(RMCP, RMCP+)
• Serial-over-LAN (SOL)
• ACPI state synchronization: The BMC tracks ACPI state changes that are provided by the BIOS.
• BMC self-test: The BMC performs initialization and run-time self-tests and makes results available to
external entities.
See also the Intelligent Platform Management Interface Specification Second Generation v2.0.
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Intel® Server Board S1200SP Family Technical Product Specification
Feature
Basic*
Advanced**
IPMI 2.0 Feature Support
Yes
Yes
In-circuit BMC Firmware Update
Yes
Yes
FRB 2
Yes
Yes
Chassis Intrusion Detection
Yes
Yes
Fan Redundancy Monitoring
Yes
Yes
6.1.2 Non-IPMI Features
The BMC supports the following non-IPMI features. This list does not preclude support for future
enhancements or additions.
• In-circuit BMC firmware update
• Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality.
• Chassis intrusion detection
• Basic fan speed control using Control version 2 SDRs
• Fan redundancy monitoring and support
• Power supply redundancy monitoring and support
• Hot-swap fan support
• Acoustic management: Support for multiple fan profiles
• Signal testing support: The BMC provides test commands for setting and getting platform signal states.
• The BMC generates diagnostic beep codes for fault conditions.
• System GUID storage and retrieval
• Front panel management: The BMC controls the system status LED and chassis ID LED. It supports secure
lockout of certain front panel functionality and monitors button presses. The chassis ID LED is turned on
using a front panel button or a command.
• Power state retention
• Power fault analysis
• Intel® Light-Guided Diagnostics
• Power unit management: Support for power unit sensor. The BMC handles power-good dropout
conditions.
• DIMM temperature monitoring: New sensors and improved acoustic management using closed-loop fan
control algorithm taking into account DIMM temperature readings.
• Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs).
• Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs).
• Platform environment control interface (PECI) thermal management support
• E-mail alerting
• Embedded web server:
• Integrated KVM
• Integrated Remote Media Redirection
• Lightweight Directory Access Protocol (LDAP) support
• Intel® Intelligent Power Node Manager support
6.2 Basic and Advanced Features
The following table lists basic and advanced feature support. Individual features may vary by platform. See the
appropriate Platform Specific EPS addendum for more information.
43
Table 12. Basic and Advanced Features
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Intel® Server Board S1200SP Family Technical Product Specification
Feature
Basic*
Advanced**
Hot-Swap Fan Support
Yes
Yes
Acoustic Management
Yes
Yes
Diagnostic Beep Code Support
Yes
Yes
Power State Retention
Yes
Yes
ARP/DHCP Support
Yes
Yes
PECI Thermal Management Support
Yes
Yes
E-mail Alerting
Yes
Yes
Embedded Web Server
Yes
Yes
SSH Support
Yes
Yes
Integrated KVM
Yes
Integrated Remote Media Redirection
Yes
Lightweight Directory Access Protocol (LDAP)
Yes
Yes
Intel® Intelligent Power Node Manager
Support***
Yes
Yes
SMASH CLP
Yes
Yes
State
Supported
Description
S0
Yes
Working
The front panel power LED is on (not controlled by the BMC).
The fans spin at the normal speed, as determined by sensor inputs.
Front panel buttons work normally.
S1
No
Not supported
S2
No
Not supported
S3
No
Supported only on Workstation platforms. See appropriate Platform Specific
Information for more information.
S4
No
Not supported
S5
Yes
Soft off
The front panel buttons are not locked.
The fans are stopped.
The power-up process goes through the normal boot process.
The power, reset, front panel NMI, and ID buttons are unlocked.
* Basic management features provided by Integrated BMC
**Advanced management features available with optional Intel® Remote Management Module 4
*** Intel® Intelligent Power Node Manager Support requires PMBus*-compliant power supply
6.3 Advanced Configuration and Power Interface (ACPI)
The server board supports the following ACPI states.
Table 13. ACPI Power States
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Intel® Server Board S1200SP Family Technical Product Specification
Source
External Signal Name or
Internal Subsystem
Capabilities
Power button
Front panel power button
Turns power on or off
BMC watchdog timer
Internal BMC timer
Turns power off, or power cycle
Command
Routed through command processor
Turns power on or off, or power cycle
Power state retention
Implemented by means of BMC internal
logic
Turns power on when AC power returns
Chipset
Sleep S4/S5 signal (same as POWER_ON)
Turns power on or off
CPU Thermal
CPU Thermtrip
Turns power off
WOL(Wake On LAN)
LAN
Turns power on
PCH Thermal
PCH Thermtrip
Pops up warning message.
Turns power off when temperature has
cross the threshold
Fan and Temperature
Fan failure and temperature critical
Turns power off *
Power Supply
Power Supply Over Current/Over
Temperature
Turns power off * **
6.4 Power Control Sources
The server board supports several power control sources which can initiate a power-up or power-down
activity.
Table 14. Power Control Initiators
* Not applicable to all products. Applies only to Multi-Node products.
** Not applicable to all products. Applies only to Node3 and Node4 on Multi-Node products when the Shutdown policy feature is
enabled.
6.5 BMC Watchdog
The BMC FW is increasingly called upon to perform system functions that are time-critical in that failure to
provide these functions in a timely manner can result in system or component damage. Intel® server board
S1200SP introduces a BMC watchdog feature to provide a safe-guard against this scenario by providing an
automatic recovery mechanism. It also can provide automatic recovery of functionality that has failed due to a
fatal FW defect triggered by a rare sequence of events or a BMC hang due to some type of HW glitch (for
example, power).
This feature is comprised of a set of capabilities whose purpose is to detect misbehaving subsections of BMC
firmware, the BMC CPU itself, or HW subsystems of the BMC component, and to take appropriate action to
restore proper operation. The action taken is dependent on the nature of the detected failure and may result
in a restart of the BMC CPU, one or more BMC HW subsystems, or a restart of malfunctioning FW subsystems.
• The BMC watchdog feature is designed to provide protection against the problems listed below regardless
of the state of the BMC FW and BMC component’s internal HW when the problem is detected.
• Linux* “kernel panic” – Results in reset of the entire FW stack (see Note1 below).
• Hangs in individual threads/processes – Offending process may be reset or entire FW stack reset may be
required.
• BMC CPU and/or BMC HW subsystems going into a faulted or unusable state due to triggers external to
the BMC component (for example, power glitches) – HW watchdog may be used to reset the BMC CPU
and/or affected BMC HW subsystems.
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Intel® Server Board S1200SP Family Technical Product Specification
• Low or out-of-memory condition – The platform management subsystem will reset itself upon detection
of this condition.
The BMC watchdog feature only allows up to three resets of the BMC CPU (such as HW reset) or entire FW
stack (such as a SW reset) before giving up and remaining in the uBOOT code. This count is cleared upon
cycling of power to the BMC or upon continuous operation of the BMC without a watchdog-generated reset
occurring for a period of greater than 30 minutes. The BMC FW logs a SEL event indicating that a watchdoggenerated BMC reset (either soft or hard reset) has occurred. This event may be logged after the actual reset
has occurred. Refer to sensor section for details for the related sensor definition. The BMC will also indicate a
degraded system status on the Front Panel Status LED after a BMC HW reset or FW stack reset. This state
(which follows the state of the associated sensor) will be cleared upon system reset or (AC or DC) power cycle.
Note: A reset of the BMC may result in the following system degradations that will require a system reset or
power cycle to correct:
1. Timeout value for the rotation period can be set using this parameter. Potentially, there will be incorrect
ACPI Power State reported by the BMC.
2. Reversion of temporary test modes for the BMC back to normal operational modes.
3. FP status LED and DIMM fault LEDs may not reflect BIOS detected errors.
6.6 Fault Resilient Booting (FRB)
Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support that allow a
multiprocessor system to boot even if the bootstrap processor (BSP) fails. Only FRB2 is supported using
watchdog timer commands.
FRB2 refers to the FRB algorithm that detects system failures during POST. The BIOS uses the BMC watchdog
timer to back up its operation during POST. The BIOS configures the watchdog timer to indicate that the BIOS
is using the timer for the FRB2 phase of the boot operation.
After the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit and loads the
watchdog timer with the new timeout interval.
If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if so configured) logs a
watchdog expiration event showing the FRB2 timeout in the event data bytes. The BMC then hard resets the
system, assuming the BIOS-selected reset as the watchdog timeout action.
The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan and before
displaying a request for a boot password. If the processor fails and causes an FRB2 timeout, the BMC resets
the system.
The BIOS gets the watchdog expiration status from the BMC. If the status shows an expired FRB2 timer, the
BIOS enters the failure in the system event log (SEL). In the OEM bytes entry in the SEL, the last POST code
generated during the previous boot attempt is written. FRB2 failure is not reflected in the processor status
sensor value.
The FRB2 failure does not affect the front panel LEDs.
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Intel® Server Board S1200SP Family Technical Product Specification
6.7 Sensor Monitoring
The BMC monitors system hardware and reports system health. Some of the sensors include those for
monitoring:
• Component, board, and platform temperatures
• Board and platform voltages
• System fan presence and tach
• Chassis intrusion
• Front Panel NMI
• Front Panel Power and System Reset Buttons
• SMI timeout
• Processor errors
The information gathered from physical sensors is translated into IPMI sensors as part of the IPMI Sensor
Model. The BMC also reports various system state changes by maintaining virtual sensors that are not
specifically tied to physical hardware.
See Appendix B – Integrated BMC Sensor Tables for additional sensor information.
6.8 Field Replaceable Unit (FRU) Inventory Device
The BMC implements the interface for logical FRU inventory devices as specified in the Intelligent Platform
Management Interface Specification, Version 2.0. This functionality provides commands used for accessing
and managing the FRU inventory information. These commands can be delivered through all interfaces.
The BMC provides FRU device command access to its own FRU device and to the FRU devices throughout the
server. The FRU device ID mapping is defined in the Platform Specific Information. The BMC controls the
mapping of the FRU device ID to the physical device.
6.9 System Event Log (SEL)
The BMC implements the system event log as specified in the Intelligent Platform Management Interface
Specification, Version 2.0. The SEL is accessible regardless of the system power state through the BMC's in-
band and out-of-band interfaces.
The BMC allocates 95231bytes (approx. 93 KB) of non-volatile storage space to store system events. The SEL
timestamps may not be in order. Up to 3,638 SEL records can be stored at a time. Because the SEL is circular,
any command that results in an overflow of the SEL beyond the allocated space will overwrite the oldest
entries in the SEL, while setting the overflow flag.
Events logged to the SEL can be viewed using Intel’s SELVIEW utility, Embedded Web Server, and Active
System Console.
6.10 System Fan Management
The BMC controls and monitors the system fans. Each fan is associated with a fan speed sensor that detects
fan failure and may also be associated with a fan presence sensor for hot-swap support. For redundant fan
configurations, the fan failure and presence status determines the fan redundancy sensor state.
The system fans are divided into fan domains, each of which has a separate fan speed control signal and a
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Intel® Server Board S1200SP Family Technical Product Specification
separate configurable fan control policy. A fan domain can have a set of temperature and fan sensors
associated with it. These are used to determine the current fan domain state.
A fan domain has three states: sleep, nominal, and boost. The sleep and boost states have fixed (but
configurable through OEM SDRs) fan speeds associated with them. The nominal state has a variable speed
determined by the fan domain policy. An OEM SDR record is used to configure the fan domain policy.
The fan domain state is controlled by several factors. They are listed below in order of precedence, high to low:
• Boost
- Associated fan is in a critical state or missing. The SDR describes which fan domains are boosted in
response to a fan failure or removal in each domain. If a fan is removed when the system is in ‘Fansoff’ mode it will not be detected and there will not be any fan boost till system comes out of ‘Fans-off;
mode.
- Any associated temperature sensor is in a critical state. The SDR describes which temperature-
threshold violations cause fan boost for each fan domain.
- The BMC is in firmware update mode, or the operational firmware is corrupted.
- If any of the above conditions apply, the fans are set to a fixed boost state speed.
• Nominal
- A fan domain’s nominal fan speed can be configured as static (fixed value) or controlled by the state
of one or more associated temperature sensors.
- Hysteresis can be specified to minimize fan speed oscillation and to smooth fan speed transitions.
6.10.1 Thermal and Acoustic Management
This feature refers to enhanced fan management to keep the system optimally cooled while reducing the
amount of noise generated by the system fans. Aggressive acoustics standards might require a trade-off
between fan speed and system performance parameters that contribute to the cooling requirements, primarily
memory bandwidth. The BIOS, BMC, and SDRs work together to provide control over how this trade-off is
determined.
This capability requires the BMC to access temperature sensors on the individual memory DIMMs.
6.10.2 Thermal Sensor Input to Fan Speed Control
The BMC uses various IPMI sensors as input to the fan speed control. Some of the sensors are IPMI models of
actual physical sensors whereas some are virtual sensors whose values are derived from physical sensors
using calculations and/or tabular information.
The following IPMI thermal sensors are used as input to the fan speed control:
• Front Panel Temperature Sensor1
• CPU Margin Sensors
• DIMM Thermal Margin Sensors
• Exit Air Temperature Sensor
• PCH Temperature Sensor
• Add-In Intel SAS Module Temperature Sensors
• PSU Thermal Sensor
• CPU VR Temperature Sensors
• DIMM VR Temperature Sensors
• BMC Temperature Sensor
• Global Aggregate Thermal Margin Sensors7
• Hot Swap Backplane Temperature Sensors
2,4,5
3, 8
2,4
1, 7, 9
3,5
3, 5
3, 6
3, 6
3, 6
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Intel® Server Board S1200SP Family Technical Product Specification
• I/O module Temperature Sensor (With option installed)
• Intel® ROC Module (With option installed)
• Riser Card Temperature Sensors
• Intel® Xeon Phi™ coprocessor (With option installed)
Notes:
1. For fan speed control in Intel® chassis
2. Temperature margin from throttling threshold
3. Absolute temperature
4. PECI value or margin value
5. On-die sensor
6. On-board sensor
7. Virtual sensor
8. Available only when PSU has PMBus
9. Calculated estimate
The following illustration provides a simple model showing the fan speed control structure that implements
the resulting fan speeds.
Figure 19. Fan Speed Control Process
6.10.3 Auto Profiles
PCSD board implements auto profile feature to improve upon previous platform configuration-dependent FSC
and maintain competitive acoustics within the market. This feature is not available for third party customization.
BIOS and BMC will handshake to automatically understand configuration details and automatically select the
optimal fan speed control profile in the BMC.
Customers will only select a performance or an acoustic profile selection from the BIOS menu for EPSD system
and the fan speed control will be optimal for the configuration loaded.
There will be no manual selection of profiles at different altitudes, but altitude impact will be well covered by
auto profile.
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Intel® Server Board S1200SP Family Technical Product Specification
Channel ID
Interface
Supports
Sessions
0
Primary IPMB
No
1
LAN 1
Yes 2 LAN 2
Yes 3 LAN31
Yes
Users can still choose performance or acoustic profile in BIOS setting. Default is acoustic. Performance option
is recommended if customer installs M.2 SSD or any other PCI-e add-in cards which requires excessive cooling,
e.g., boundary condition of 55C and 300LFM.
To support PCI-e add-in cards:
• Acoustic option is targeted to meet boundary condition of 55C&200LFM.
• Performance option is targeted to meet boundary condition beyond 55C&200LFM. e.g., boundary
condition of 55C and 300LFM.
6.10.4 Memory Thermal Throttling
The system shall support thermal management through static closed loop throttling (Static-CLTT) of system
memory based on the platform as well as availability of valid temperature sensors on the installed memory
DIMMs. Throttling levels are changed dynamically to cap throttling based on memory and system thermal
conditions as determined by the system and DIMM power and thermal parameters. Support for CLTT on
mixed-mode DIMM populations (that is, some installed DIMMs have valid temp sensors and some do not) is
not supported. The BMC fan speed control functionality is related to the memory throttling mechanism used.
The following terminology is used for the various memory throttling options:
• Static Closed Loop Thermal Throttling (Static-CLTT): CLTT control registers are configured by BIOS MRC
during POST. The memory throttling is run as a closed-loop system with the DIMM temperature sensors
as the control input. Otherwise, the system does not change any of the throttling control registers in the
embedded memory controller during runtime.
• Intel® Server Systems supporting the Intel® Xeon® processor E3-1200 V5 and V6 product family introduce
a new type of CLTT which is referred to as Hybrid CLTT for which the Integrated Memory Controller
estimates the DRAM temperature in between actual reads of the TSODs. Hybrid CLTTT shall be used on
all Intel® Server Systems supporting the Intel® Xeon® processor E3-1200 V5 and V6 product family that
have DIMMs with thermal sensors. Therefore, the terms Dynamic-CLTT and Static-CLTT are really referring
to this ‘hybrid’ mode. Note that if the IMC’s polling of the TSODs is interrupted, the temperature readings
that the BMC gets from the IMC shall be these estimated values.
6.11 Messaging Interfaces
The BMC supports the following communications interfaces:
• Host SMS interface by means of low pin count (LPC)/keyboard controller style (KCS) interface
• Host SMM interface by means of low pin count (LPC)/keyboard controller style (KCS) interface
• Intelligent Platform Management Bus (IPMB) I2C interface
• LAN interface using the IPMI-over-LAN protocols
Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. The following table shows the standard
channel assignments.
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Table 15. Messaging Interfaces
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Intel® Server Board S1200SP Family Technical Product Specification
Channel ID
Interface
Supports
Sessions
(Provided by the Intel® Dedicated Server
Management NIC)
4
Reserved
Yes
5
USB2
No 6 Secondary IPMB
No 7 SMM
No
8 – 0Dh
Reserved
–
0Eh
Self3
–
0Fh
SMS/Receive Message Queue
No
Notes:
1. Optional hardware supported by the server system.
2. Reserve USB channel number, current BMC firmware does not support communication through a USB
channel.
3. Refers to the actual channel used to send the request.
6.11.1 User Model
The BMC supports the IPMI 2.0 user model. 15 user IDs are supported. These 15 users can be assigned to any
channel. The following restrictions are placed on user-related operations:
1. User names for User IDs 1 and 2 cannot be changed. These are always “” (Null/blank) and “root”
respectively.
2. User 2 (“root”) always has the administrator privilege level.
3. All user passwords (including passwords for 1 and 2) may be modified.
4. User IDs 3-15 may be used freely, with the condition that user names are unique. Therefore, no other
users can be named “” (Null), “root,” or any other existing user name.
6.11.2 IPMB Communication Interface
The IPMB communication interface uses the 100 KB/s version of an I2C bus as its physical medium. For more
information on I2C specifications, see The I2C Bus and How to Use It. The IPMB implementation in the BMC is
compliant with the IPMB v1.0, revision 1.0.
The BMC IPMB slave address is 20h.
The BMC both sends and receives IPMB messages over the IPMB interface. Non-IPMB messages received by
means of the IPMB interface are discarded.
Messages sent by the BMC can either be originated by the BMC, such as initialization agent operation, or by
another source. One example is KCS-IPMB bridging.
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6.11.3 LAN Interface
The BMC implements both the IPMI 1.5 and IPMI 2.0 messaging models. These provide out-of-band local area
network (LAN) communication between the BMC and the network.
See the Intelligent Platform Management Interface Specification Second Generation v2.0 for details about the
IPMI-over-LAN protocol.
Run-time determination of LAN channel capabilities can be determined by both standard IPMI defined
mechanisms.
6.11.3.1 RMCP/ Alert Standards Forum (ASF Messaging)
The BMC supports RMCP ping discovery in which the BMC responds with a pong message to an RMCP/ASF
ping request. This is implemented per the Intelligent Platform Management Interface Specification Second
Generation v2.0.
6.11.3.2 BMC LAN Channels
The BMC supports three RMII/RGMII ports that can be used for communicating with Ethernet devices. Two
ports are used for communication with the on-board NICs and one is used for communication with an Ethernet
PHY located on the onboard dedicated RMM4 NIC.
6.11.3.2.1 Baseboard NICs
The on-board Ethernet controller provides support for a Network Controller Sideband Interface (NC-SI)
manageability interface. This provides a sideband high-speed connection for manageability traffic to the BMC
while still allowing for a simultaneous host access to the OS if desired.
The NC-SI is a DMTF industry standard protocol for the side band management LAN interface. This protocol
provides a fast multi-drop interface for management traffic.
The baseboard NICs are connected to a single BMC RMII/RGMII port that is configured for RMII operation. The
NC-SI protocol is used for this connection and provides a 100 Mb/s full-duplex multi-drop interface which
allows multiple NICs to be connected to the BMC. The physical layer is based upon RMII, however RMII is a
point-to-point bus whereas NC-SI allows 1 master and up to 4 slaves. The logical layer (configuration
commands) is incompatible with RMII.
The server board provides support for a dedicated management channel that can be configured to be hidden
from the host and only used by the BMC. This mode of operation is configured using a BIOS setup option.
6.11.3.2.2 Dedicated Management Channel
An additional LAN channel dedicated to BMC usage is supported using the on-board RMM4 NIC. The BMC has
a built-in MAC module that uses the RGMII interface to link with the RMM4 NIC’s PHY. Therefore, for this
dedicated management interface, the PHY and MAC are located in different devices.
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The PHY on the RMM4 connects to the BMC’s other RMII/RGMII interface (that is, the one that is not connected
to the baseboard NICs). This BMC port is configured for RGMII usage.
In addition to the use of the on-board dedicated RMM4 NIC for a dedicated management channel, on systems
that support multiple Ethernet ports on the baseboard, the system BIOS provides a setup option to allow one
of these baseboard ports to be dedicated to the BMC for manageability purposes. When this is enabled, that
port is hidden from the OS. By default, this interface is disabled and must be configured via the BIOS, EWS, or
IPMI commands.
6.11.3.2.3 Concurrent Server Management Use of Multiple Ethernet Controllers
The BMC FW supports concurrent OOB LAN management sessions for the following combination:
• 2 on-board NIC ports
• 1 on-board NIC and the on-board dedicated RMM4 NIC
• 2 on-board NICs and the on-board dedicated RMM4 NIC
All NIC ports must be on different subnets for the concurrent usage models above.
MAC addresses are assigned for management NICs from a pool of up to 3 MAC addresses allocated specifically
for manageability.
The server board has seven MAC addresses programmed at the factory. MAC addresses are assigned as
follows:
• NIC 1 MAC address (for OS usage)
• NIC 2 MAC address = NIC 1 MAC address + 1 (for OS usage)
• BMC LAN channel 1 MAC address = NIC1 MAC address + 2
• BMC LAN channel 2 MAC address = NIC1 MAC address + 3
• BMC LAN channel 3 (RMM4) MAC address = NIC1 MAC address + 4
The printed MAC address on the server board and/or server system is assigned to NIC1 on the server board.
For security reasons, embedded LAN channels have the following default settings:
• IP Address: Static
• All users disabled
IPMI-enabled network interfaces may not be placed on the same subnet. This includes the Intel® Dedicated
Server Management NIC and either of the BMC’s embedded network interfaces.
Host-BMC communication over the same physical LAN connection – also known as loopback – is not
supported. This includes ping operations.
On server boards with more than two onboard NIC ports, only the first two ports can be used as BMC LAN
channels. The remaining ports have no BMC connectivity.
Maximum bandwidth supported by BMC LAN channels are as follows:
• BMC LAN1 (Baseboard NIC port) – 100Mb (10Mb in DC off state)
• BMC LAN 2 (Baseboard NIC port) – 100Mb (10Mb in DC off state)
• BMC LAN 3 (Dedicated NIC) – 1000Mb
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6.11.3.3 IPV6 Support
In addition to IPv4, the server board supports IPv6 for manageability channels. Configuration of IPv6 is
provided by extensions to the IPMI Set and Get LAN Configuration Parameters commands as well as through
a Web Console IPv6 configuration web page.
The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and completely
independently. For example, IPv4 can be DHCP configured while IPv6 is statically configured or vice versa.
The parameters for IPv6 are similar to the parameters for IPv4 with the following differences:
• An IPv6 address is 16 bytes vs. 4 bytes for IPv4.
• An IPv6 prefix is 0 to 128 bits whereas IPv4 has a 4 byte subnet mask.
• The IPv6 Enable parameter must be set before any IPv6 packets are sent or received on that channel.
• There are two variants of automatic IP Address Source configuration vs. just DHCP for IPv4.
The three possible IPv6 IP Address Sources for configuring the BMC are:
• Static (Manual): The IP, Prefix, and Gateway parameters are manually configured by the user. The BMC
ignores any Router Advertisement messages received over the network.
• DHCPv6: The IP comes from running a DHCPv6 client on the BMC and receiving the IP from a DHCPv6
server somewhere on the network. The Prefix and Gateway are configured by Router Advertisements from
the local router. The IP, Prefix, and Gateway are read-only parameters to the BMC user in this mode.
• Stateless auto-config: The Prefix and Gateway are configured by the router through Router
Advertisements. The BMC derives its IP in two parts: the upper network portion comes from the router
and the lower unique portion comes from the BMC’s channel MAC address. The 6-byte MAC address is
converted into an 8-byte value per the EUI-64* standard. For example, a MAC value of 00:15:17:FE:2F:62
converts into a EUI-64 value of 215:17ff:fefe:2f62. If the BMC receives a Router Advertisement from a
router at IP 1:2:3:4::1 with a prefix of 64, it would then generate for itself an IP of 1:2:3:4:215:17ff:fefe:2f62.
The IP, Prefix, and Gateway are read-only parameters to the BMC user in this mode.
IPv6 can be used with the BMC’s Web Console, JViewer* (remote KVM and Media), and Systems Management
Architecture for Server Hardware – Command Line Protocol (SMASH-CLP) interface (SSH). There is no standard
yet on how IPMI RMCP or RMCP+ should operate over IPv6 so that is not currently supported.
6.11.3.4 LAN Failover
The BMC FW provides a LAN failover capability so that the failure of the system HW associated with one LAN
link will result in traffic being rerouted to an alternate link. This functionality is configurable using IPMI
methods as well as the BMC’s Embedded UI, allowing for user to specify the physical LAN links constitute the
redundant network paths or physical LAN links constitute different network paths. BMC supports only an all
or nothing approach – that is, all interfaces bonded together, or none are bonded together.
The LAN Failover feature applies only to BMC LAN traffic. It bonds all available Ethernet devices but only one
is active at a time. When enabled, if the active connection’s leash is lost, one of the secondary connections is
automatically configured so that it has the same IP address. Traffic immediately resumes on the new active
connection.
The LAN Failover enable/disable command may be sent at any time. After it has been enabled, standard IPMI
commands for setting channel configuration that specify a LAN channel other than the first will return an error
code.
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6.11.3.5 BMC IP Address Configuration
Enabling the BMC’s network interfaces requires using the Set LAN Configuration Parameter command to
configure LAN configuration parameter 4, IP Address Source. The BMC supports this parameter as follows:
• 1h, static address (manually configured): Supported on all management NICs. This is the BMC’s default
value.
• 2h, address obtained by BMC running DHCP: Supported only on embedded management NICs.
IP Address Source value 4h, address obtained by BMC running other address assignment protocol, is not
supported on any management NIC.
Attempting to set an unsupported IP address source value has no effect, and the BMC returns error code 0xCC,
Invalid data field-in request. Note that values 0h and 3h are no longer supported, and will return a 0xCC error
completion code.
6.11.3.5.1 Static IP Address (IP Address Source Values 0h, 1h, and 3h)
The BMC supports static IP address assignment on all of its management NICs. The IP address source
parameter must be set to static before the IP address; the subnet mask or gateway address can be manually
set.
The BMC takes no special action when the following IP address source is specified as the IP address source for
any management NIC: 1h – Static address (manually configured).
The Set LAN Configuration Parameter command must be used to configure LAN configuration parameter 3, IP
Address, with an appropriate value.
The BIOS does not monitor the value of this parameter, and it does not execute DHCP for the BMC under any
circumstances, regardless of the BMC configuration.
6.11.3.5.2 Static LAN Configuration Parameters
When the IP Address Configuration parameter is set to 01h (static), the following parameters may be changed
by the user:
• LAN configuration parameter 3 (IP Address)
• LAN configuration parameter 6 (Subnet Mask)
• LAN configuration parameter 12 (Default Gateway Address)
When changing from DHCP to Static configuration, the initial values of these three parameters will be
equivalent to the existing DHCP-set parameters. Additionally, the BMC observes the following network safety
precautions:
1. The user may only set a subnet mask that is valid, per IPv4 and RFC 950 (Internet Standard Subnetting
Procedure). Invalid subnet values return a 0xCC (Invalid Data Field in Request) completion code, and the
subnet mask is not set. If no valid mask has been previously set, default subnet mask is 0.0.0.0.
2. The user may only set a default gateway address that can potentially exist within the subnet specified
above. Default gateway addresses outside the BMC’s subnet are technically unreachable and the BMC will
not set the default gateway address to an unreachable value. The BMC returns a 0xCC (Invalid Data Field
in Request) completion code for default gateway addresses outside its subnet.
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3. If a command is issued to set the default gateway IP address before the BMC’s IP address and subnet mask
are set, the default gateway IP address is not updated and the BMC returns 0xCC.
If the BMC’s IP address on a LAN channel changes while a LAN session is in progress over that channel, the
BMC does not take action to close the session except through a normal session timeout. The remote client
must re-sync with the new IP address. The BMC’s new IP address is only available in-band through the Get LAN
Configuration Parameters command.
6.11.3.5.3 Enabling/Disabling Dynamic Host Configuration (DHCP) Protocol
The BMC DHCP feature is activated by using the Set LAN Configuration Parameter command to set LAN
configuration parameter 4, IP Address Source, to 2h: “address obtained by BMC running DHCP”. Once this
parameter is set, the BMC initiates the DHCP process within approximately 100 ms.
If the BMC has previously been assigned an IP address through DHCP or the Set LAN Configuration Parameter
command, it requests that same IP address to be reassigned. If the BMC does not receive the same IP address,
system management software must be reconfigured to use the new IP address. The new address is only
available in-band, through the IPMI Get LAN Configuration Parameters command.
Changing the IP Address Source parameter from 2h to any other supported value will cause the BMC to stop
the DHCP process. The BMC uses the most recently obtained IP address until it is reconfigured.
If the physical LAN connection is lost (that is, the cable is unplugged), the BMC will not re-initiate the DHCP
process when the connection is re-established.
6.11.3.5.4 DHCP-related LAN Configuration Parameters
Users may not change the following LAN parameters while the DHCP is enabled:
• LAN configuration parameter 3 (IP Address)
• LAN configuration parameter 6 (Subnet Mask)
• LAN configuration parameter 12 (Default Gateway Address)
To prevent users from disrupting the BMC’s LAN configuration, the BMC treats these parameters as read-only
while DHCP is enabled for the associated LAN channel. Using the Set LAN Configuration Parameter command
to attempt to change one of these parameters under such circumstances has no effect, and the BMC returns
error code 0xD5, “Cannot Execute Command. Command, or request parameter(s) are not supported in present
state.”
6.11.3.6 DHCP BMC Hostname
The BMC allows setting a DHCP Hostname using the Set/Get LAN Configuration Parameters command.
• DHCP Hostname can be set regardless of the IP Address source configured on the BMC. But this parameter
is only used if the IP Address source is set to DHCP.
• When Byte 2 is set to Update in progress, all the 16 Block Data Bytes (Bytes 3 – 18) must be present in the
request.
• When Block Size is less than 16, it must be the last Block request in this series. In other words Byte 2 is
equal to “Update is complete” on that request.
• Whenever Block Size is less than 16, the Block data bytes must end with a NULL Character or Byte (=0).
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• All Block write requests are updated into a local Memory byte array. When Byte 2 is set to Update is
Complete, the Local Memory is committed to the NV Storage. Local Memory is reset to NULL after changes
are committed.
• When Byte 1 (Block Selector = 1), firmware resets all the 64 bytes local memory. This can be used to undo
any changes after the last Update in Progress.
• User should always set the hostname starting from block selector 1 after the last Update is complete. If
the user skips block selector 1 while setting the hostname, the BMC will record the hostname as NULL,
because the first block contains NULL data.
• This scheme effectively does not allow a user to make a partial Hostname change. Any Hostname change
needs to start from Block 1.
• Byte 64 ( Block Selector 04h byte 16) is always ignored and set to NULL by BMC which effectively means
we can set only 63 bytes.
• User is responsible for keeping track of the Set series of commands and Local Memory contents.
While BMC firmware is in Set Hostname in Progress (Update not complete), the firmware continues using the
Previous Hostname for DHCP purposes.
6.11.4 Address Resolution Protocol (ARP)
The BMC can receive and respond to ARP requests on BMC NICs. Gratuitous ARPs are supported, and disabled
by default.
6.11.5 Internet Control Message Protocol (ICMP)
The BMC supports the following ICMP message types targeting the BMC over integrated NICs:
• Echo request (ping): The BMC sends an Echo Reply.
• Destination unreachable: If message is associated with an active socket connection within the BMC, the
BMC closes the socket.
6.11.6 Virtual Local Area Network (VLAN)
The BMC supports VLAN as defined by IPMI 2.0 specifications. VLAN is supported internally by the BMC, not
through switches. VLAN provides a way of grouping a set of systems together so that they form a logical
network. This feature can be used to set up a management VLAN where only devices which are members of
the VLAN will receive packets related to management and members of the VLAN will be isolated from any
other network traffic. Note that VLAN does not change the behavior of the host network setting, and it only
affects the BMC LAN communication.
LAN configuration options are now supported (by means of the Set LAN Config Parameters command,
parameters 20 and 21) that allow support for 802.1Q VLAN (Layer 2). This allows VLAN headers/packets to be
used for IPMI LAN sessions. VLAN IDs are entered and enabled by means of parameter 20 of the Set LAN Config
Parameters IPMI command. When a VLAN ID is configured and enabled, the BMC only accepts packets with
that VLAN tag/ID. Conversely, all BMC generated LAN packets on the channel include the given VLAN tag/ID.
Valid VLAN IDs are 1 through 4094, and VLAN IDs of 0 and 4095 are reserved, per the 802.1Q VLAN
specification.
Parameter 21 (VLAN Priority) of the Set LAN Config Parameters IPMI command is now implemented and a
range from 0 to 7 will be allowed for VLAN Priorities. Note that bits 3 and 4 of Parameter 21 are considered
Reserved bits.
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Parameter 25 (VLAN Destination Address) of the Set LAN Config Parameters IPMI command is not supported
and returns a completion code of 0x80 (parameter not supported) for any read/write of parameter 25.
If the BMC IP address source is DHCP, the following behavior is seen:
• If the BMC is first configured for DHCP (prior to enabling VLAN), when VLAN is enabled, the BMC performs
a discovery on the new VLAN in order to obtain a new BMC IP address.
• If the BMC is configured for DHCP (before disabling VLAN), when VLAN is disabled, the BMC performs a
discovery on the LAN in order to obtain a new BMC IP address.
If the BMC IP address source is Static, the following behavior is seen:
• If the BMC is first configured for static (prior to enabling VLAN), when VLAN is enabled, the BMC has the
same IP address as configured before. It is left to the management application to configure a different IP
address if that is not suitable for VLAN.
• If the BMC is configure for static (prior to disabling VLAN), when VLAN is disabled, the BMC has the same
IP address as configured before. It is left to the management application to configure a different IP address
if that is not suitable for LAN.
6.11.7 Secure Shell (SSH)
Secure Shell (SSH) connections are supported for SMASH-CLP sessions to the BMC.
There is a maximum of one SMASH-CLP session allowed.
6.11.8 Serial-over-LAN (SOL 2.0)
The BMC supports IPMI 2.0 SOL.
IPMI 2.0 introduced a standard serial-over-LAN feature. This is implemented as a standard payload type (01h)
over RMCP+.
Three commands are implemented for SOL 2.0 configuration:
• Get SOL 2.0 Configuration Parameters and Set SOL 2.0 Configuration Parameters: These commands are
used to get and set the values of the SOL configuration parameters. The parameters are implemented on
a per-channel basis.
• Activating SOL: This command is not accepted by the BMC. It is sent by the BMC when SOL is activated to
notify a remote client of the switch to SOL.
• Activating a SOL session requires an existing IPMI-over-LAN session. If encryption is used, it should be
negotiated when the IPMI-over LAN session is established.
6.11.9 Platform Event Filter (PEF)
The BMC includes the ability to generate a selectable action, such as a system power-off or reset, when a match
occurs to one of a configurable set of events. This capability is called Platform Event Filtering, or PEF. One of
the available PEF actions is to trigger the BMC to send a LAN alert to one or more destinations.
The BMC supports 20 PEF filters. The first twelve entries in the PEF filter table are pre-configured (but may be
changed by the user). The remaining entries are left blank, and may be configured by the user.
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Event Filter
Number
Offset Mask
Events
1
Non-critical, critical and nonrecoverable
Temperature sensor out of
range
2
Non-critical, critical and nonrecoverable
Voltage sensor out of range
3
Non-critical, critical and nonrecoverable
Fan failure
4
General chassis intrusion
Chassis intrusion (security
violation)
5
Failure and predictive failure
Power supply failure
6
Uncorrectable ECC
BIOS
7
POST error
BIOS: POST code error
8
FRB2
Watchdog Timer expiration for
FRB2
9
Policy Correction Time
Node Manager
10
Power down, power cycle, and
reset
Watchdog timer
11
OEM system boot event
System restart (reboot)
12
Drive Failure, Predicted Failure
Hot Swap Controller
Table 16. Factory Configured PEF Table Entries
Additionally, the BMC supports the following PEF actions:
• Power off
• Power cycle
• Reset
• OEM action
• Alerts
The Diagnostic interrupt action is not supported.
6.11.10 LAN Alerting
The BMC supports sending embedded LAN alerts, called SNMP PET (Platform Event traps), and SMTP email
alerts.
The BMC supports a minimum of four LAN alert destinations.
6.11.10.1 SNMP Platform Event Traps (PETs)
This feature enables a target system to send SNMP traps to a designated IP address by means of LAN. These
alerts are formatted per the Intelligent Platform Management Interface Specification Second Generation v2.0.
A Modular Information Block (MIB) file associated with the traps is provided with the BMC firmware to facilitate
interpretation of the traps by external software. The format of the MIB file is covered under RFC 2578.
6.11.11 Alert Policy Table
Associated with each PEF entry is an alert policy that determines which IPMI channel the alert is to be sent.
There is a maximum of 20 alert policy entries. There are no pre-configured entries in the alert policy table
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because the destination types and alerts may vary by user. Each entry in the alert policy table contains four
bytes for a maximum table size of 80 bytes.
6.11.11.1 E-mail Alerting
The Embedded Email Alerting feature allows the user to receive e-mails alerts indicating issues with the server.
This allows e-mail alerting in an OS-absent (for example, Pre-OS and OS-Hung) situation. This feature provides
support for sending e-mail by means of SMTP, the Simple Mail Transport Protocol as defined in Internet RC
821. The e-mail alert provides a text string that describes a simple description of the event. SMTP alerting is
configured using the embedded web server.
6.11.12 SM-CLP (SM-CLP Lite)
SMASH refers to Systems Management Architecture for Server Hardware. SMASH is defined by a suite of
specifications, managed by the DMTF, that standardize the manageability interfaces for server hardware. CLP
refers to Command Line Protocol. SM-CLP is defined by the Server Management Command Line Protocol
Specification (SM-CLP) ver1.0, which is part of the SMASH suite of specifications. The specifications and further
information on SMASH can be found at the DMTF website (http://www.dmtf.org/).
The BMC provides an embedded lite version of SM-CLP that is syntax-compatible but not considered fully
compliant with the DMTF standards.
The SM-CLP utilized by a remote user by connecting a remote system using one of the system NICs. It is
possible for third-party management applications to create scripts using this CLP and execute them on server
to retrieve information or perform management tasks such as reboot the server, configure events, and so on.
The BMC embedded SM-CLP feature includes the following capabilities:
• Power on/off/reset the server.
• Get the system power state.
• Clear the System Event Log (SEL).
• Get the interpreted SEL in a readable format.
• Initiate/terminate a Serial Over LAN session.
• Support “help” to provide helpful information.
• Get/set the system ID LED.
• Get the system GUID.
• Get/set configuration of user accounts.
• Get/set configuration of LAN parameters.
• Embedded CLP communication should support SSH connection.
• Provide current status of platform sensors including current values. Sensors include voltage, temperature,
fans, power supplies, and redundancy (power unit and fan redundancy).
6.11.13 Embedded Web Server
The embedded web server is supported over any system NIC port that is enabled for server management
capabilities.
BMC Base manageability provides an embedded web server and an OEM-customizable web GUI which exposes
the manageability features of the BMC base feature set. It is supported over all on-board NICs that have
management connectivity to the BMC as well as an optional RMM4 dedicated add-in management NIC. At least
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two concurrent web sessions from up to two different users is supported. The embedded web user interface
supports the following client web browsers:
• Microsoft Internet Explorer 9.0*
• Microsoft Internet Explorer 10.0*
• Mozilla Firefox 24*
• Mozilla Firefox 25*
The embedded web user interface supports strong security (authentication, encryption, and firewall support)
since it enables remote server configuration and control. Embedded web server uses ports #80 and #443. The
user interface presented by the embedded web user interface authenticates the user before allowing a web
session to be initiated. Encryption using 128-bit SSL is supported. User authentication is based on user ID and
password.
The GUI presented by the embedded web server authenticates the user before allowing a web session to be
initiated. It presents all functions to all users but grays-out those functions that the user does not have privilege
to execute. (For example, if a user does not have privilege to power control, the item will be displayed in greyout font in that user’s UI display). The web GUI also provides a launch point for some of the advanced features,
such as KVM and media redirection. These features are grayed out in the GUI unless the system has been
updated to support these advanced features. The embedded web server only displays US English or Chinese
language output.
Additional features supported by the web GUI includes:
• Present all the Basic features to the users.
• Power on/off/reset the server and view current power state.
• Display BIOS, BMC, ME, and SDR version information.
• Display overall system health.
• Configuration of various IPMI over LAN parameters for both IPV4 and IPV6.
• Configuration of alerting (SNMP and SMTP).
• Display system asset information for the product, board, and chassis.
• Display of BMC-owned sensors (name, status, current reading, enabled thresholds), including color-code
status of sensors.
• Provide ability to filter sensors based on sensor type (Voltage, Temperature, Fan, and Power supply
related).
• Automatic refresh of sensor data with a configurable refresh rate.
• Online help
• Display/clear SEL (display is in easily understandable human readable format).
• Support major industry-standard browsers (Microsoft Internet Explorer* and Mozilla Firefox*).
• The GUI session automatically times-out after a user-configurable inactivity period. By default, this
inactivity period is 30 minutes.
• Embedded Platform Debug feature: Allows the user to initiate a diagnostic dump to a file that can be sent
to Intel for debug purposes.
• Virtual Front Panel: The Virtual Front Panel provides the same functionality as the local front panel. The
displayed LEDs match the current state of the local panel LEDs. The displayed buttons (for example, power
button) can be used in the same manner as the local buttons.
• Display of ME sensor data. Only sensors that have associated SDRs loaded are displayed.
• Ability to save the SEL to a file.
• Ability to force HTTPS connectivity for greater security. This is provided through a configuration option in
the UI.
• Display of processor and memory information as is available over IPMI over LAN.
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• Ability to get and set Node Manager (NM) power policies.
• Display of power consumed by the server.
• Ability to view and configure VLAN settings.
• Warn user the reconfiguration of IP address will cause disconnect.
• Capability to block logins for a period of time after several consecutive failed login attempts. The lock-out
period and the number of failed logins that initiates the lock-out period are configurable by the user.
• Server Power Control: Ability to force into Setup on a reset.
• System POST results – The web server provides the system’s Power-On Self-Test (POST) sequence for the
previous two boot cycles, including timestamps. The timestamps may be viewed in relative to the start of
POST or the previous POST code.
• Customizable ports – The web server provides the ability to customize the port numbers used for SMASH,
http, https, KVM, secure KVM, remote media, and secure remote media. The ports provided must be unique.
If two identical ports are provided, the associated services will not function properly. Some ports are
reserved and cannot be assigned to any of these services because they are used internally; these ports are
623, 8080, and 8282.
• Ability to update SDR. Upload new sensor data repository records and configuration files. Enable/disable
SDR auto-configuration.
• Display users currently logged in to the BMC.
• Ability to Restore BMC Defaults
• Ability to select the BMC network interfaces to carry SOL data.
• Ability to view and configure KVM settings.
• Ability to generate and download SOL log file
• Ability to view and configure SOL log feature setting
6.11.14 Virtual Front Panel
• Virtual Front Panel is the module present as Virtual Front Panel on the left side in the embedded web
server when remote Control tab is clicked.
• Main Purpose of the Virtual Front Panel is to provide the front panel functionality virtually.
• Virtual Front Panel (VFP) will mimic the status LED and Power LED status and Chassis ID alone. It is
automatically in sync with BMC every 40 seconds.
• For any abnormal status LED state, Virtual Front Panel will get the reason behind the abnormal or status
LED changes and displayed in VFP side.
• As Virtual Front Panel uses the Chassis Control command for power actions. It won’t log the Front button
press event since Logging the front panel press event for Virtual Front Panel press will mislead the
administrator.
• For Reset from Virtual Front Panel, the reset will be done by a Chassis Control command.
• During Power action, Power button/Reset button will not accept the next action until current Power action
is complete and the acknowledgment from BMC is received.
• Embeded Web Server (EWS) will provide a valid message during Power action until it completes the
current Power action.
• The VFP does not have any effect on whether the front panel is locked by Set Front Panel Enables
command.
• The chassis ID LED provides a visual indication of a system being serviced. The state of the chassis ID LED
is affected by the following actions:
- Toggled by turning the chassis ID button on or off.
- There is no precedence or lock-out mechanism for the control sources. When a new request arrives,
previous requests are terminated. For example, if the chassis ID button is pressed, the chassis ID LED
changes to solid on. If the button is pressed again, the chassis ID LED turns off.
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- Note that the chassis ID will turn on because of the original chassis ID button press and will reflect in
the Virtual Front Panel after VFP sync with BMC. Virtual Front Panel will not reflect the chassis LED
software blinking from the software command as there is no mechanism to get the chassis ID Led
status.
- Only Infinite chassis ID ON/OFF from the software command will reflect in EWS during automatic
/manual EWS sync up with BMC.
• Virtual Front Panel help is available for virtual panel module.
• At present, NMI button in VFP is disabled. It can be used in future.
6.11.15 Embedded Platform Debug
The Embedded Platform Debug feature supports capturing low-level diagnostic data (applicable MSRs, PCI
config-space registers, and so on). This feature allows a user to export this data into a file that is retrievable
from the embedded web GUI, as well as through host and remote IPMI methods, for the purpose of sending
to an Intel engineer for an enhanced debugging capability. The files are compressed, encrypted, and password
protected. The file is not meant to be viewable by the end user but rather to provide additional debugging
capability to an Intel support engineer.
A list of data that may be captured using this feature includes but is not limited to:
• Platform sensor readings – This includes all readable sensors that can be accessed by the BMC FW and
have associated SDRs populated in the SDR repository. This does not include any event-only sensors. (All
BIOS sensors and some BMC and ME sensors are event-only; meaning that they are not readable using an
IPMI Get Sensor Reading command but rather are used just for event logging purposes).
• SEL – The current SEL contents are saved in both hexadecimal and text format.
• CPU/memory register data – Useful for diagnosing the cause of the following system errors: CATERR,
ERR[2], SMI timeout, PERR, and SERR. The debug data is saved and time stamped for the last 3 occurrences
of the error conditions.
- First 256 byte of PCI configuration space and the advanced error reporting registers
- Processor Machine Check Architecture registers
- Integrated Memory Controller (iMC) Machine Check Architecture registers
- Integrated I/O (IIO) Global error registers
• BMC configuration data
- BMC FW debug log (that is, SysLog) – Captures FW debug messages.
- Non-volatile storage of captured data – Some of the captured data is stored persistently in the BMC’s
non-volatile flash memory and preserved across AC power cycles. Due to size limitations of the BMC’s
flash memory, it is not feasible to store all of the data persistently.
• SMBIOS table data – The entire SMBIOS table is captured from the last boot.
• PCI configuration data for on-board devices and add-in cards – The first 256 bytes of PCI configuration
data is captured for each device for each boot.
• Power supplies debug capability
- Capture of power supply black box data and power supply asset information –Power supply vendors
are adding the capability to store debug data within the power supply itself. The platform debug
feature provides a means to capture this data for each installed power supply. The data can be
analyzed by Intel® for failure analysis and possibly provided to the power supply vendor as well. The
BMC gets this data from the power supplied from the PMBus* manufacturer-specific commands.
- Storage of system identification in power supply – The BMC copies board and system serial numbers
and part numbers into the power supply whenever a new power supply is installed in the system or
when the system is first powered on. This information is included as part of the power supply black
box data for each installed power supply.
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Category
Data
Internal BMC Data
BMC uptime/load
Process list
Free Memory
Detailed Memory List
Filesystem List/Info
BMC Network Info
BMC Syslog
BMC Configuration Data
External BMC Data
Sensor readings
Hex SEL listing
Human-readable SEL listing
Human-readable sensor listing
External BIOS Data
POST codes for the two most recent boots
System Data
SMBIOS table for the current boot
Power Supply Unit data
• Accessibility through IPMI interfaces – The platform debug file can be accessed using an external IPMI
interface (KCS or LAN).
• POST code sequence for the two most recent boots – This is a best-effort data collection by the BMC as
the BMC real-time response cannot guarantee that all POST codes are captured.
- SDR data.
- Signal debugging dumps, if available.
• Support for multiple debug files –The platform debug feature provides the ability to save data to two
separate files that are encrypted with different passwords.
- File #1 is strictly for viewing by Intel engineering and may contain BMC log messages (that is, syslog)
and other debug data that Intel FW developers deem useful in addition to the data specified in this
document.
- File #2 can be viewed by Intel partners who have signed an NDA with Intel and its contents are
restricted to specific data items specified in this with the exception of the BMC syslog messages and
power supply black box data.
6.11.15.1 Output Data Format
The diagnostic feature outputs a password-protected compressed HTML file containing specific BMC and
system information. This file is not intended for end-customer usage. This file is for customer support and
engineering only.
6.11.15.2 Output Data Availability
The diagnostic data is available on-demand from the embedded web server, KCS, or IPMI Over LAN commands.
6.11.15.3 Output Data Categories
The following tables list the data to be provided in the diagnostic output. For items in Table 17, this data is
collected on detection of CATERR, ERR2, PERR, SERR, and SMI timeout. The data in Table 18 is accumulated
for the three most recent overall errors.
Table 17. Diagnostic Data
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Intel® Server Board S1200SP Family Technical Product Specification
Category
Data
System Data
First 256 bytes of PCI config data for each PCI device
PCI advanced error reporting registers
Processor Machine Check Architecure registers
iMC Machine Check Architecure registers
IIO Global error registers
Table 18. Additional Diagnostics on Error
6.11.16 Data Center Management Interface (DCMI)
The DCMI Specification is an emerging standard that is targeted to provide a simplified management interface
for Internet Portal Data Center (IPDC) customers. It is expected to become a requirement for server platforms
which are targeted for IPDCs. DCMI is an IPMI-based standard that builds upon a set of required IPMI standard
commands by adding a set of DCMI-specific IPMI OEM commands. Intel® S1200SP Server Platforms implement
the mandatory DCMI features in the BMC firmware (DCMI 1.5 compliance). Refer to DCMI 1.5 spec for details.
Only mandatory commands are supported. No support for optional DCMI commands. Optional power
management and SEL roll over feature is not supported. DCMI Asset tag is independent of baseboard FRU
asset Tag.
6.11.17 Lightweight Directory Access Protocol (LDAP)
The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the BMC for the
purpose of authentication and authorization. The BMC user connects with an LDAP server for login
authentication. This is only supported for non-IPMI logins including the embedded web UI and SM-CLP. IPMI
users/passwords and sessions are not supported over LDAP. LDAP can be configured (IP address of LDAP
server, port, and so on) using the BMC’s Embedded Web UI. LDAP authentication and authorization is
supported over the any NIC configured for system management. The BMC uses a standard Open LDAP
implementation for Linux*. Only open LDAP is supported by BMC. Microsoft Windows* and Novell* LDAP are
not supported.
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Intel Product Code
Description
Kit Contents
Benefits
AXXRMM4LITE
Intel® Remote Management
Module 4 Lite
RMM4 Lite Activation Key
Enables KVM & media
redirection
7 Advanced Management Feature Support (RMM4)
The integrated BMC has support for basic and advanced server management features. Basic management
features are available by default. Advanced management features are enabled with the addition of an
optionally installed Remote Management Module 4 Lite (RMM4 Lite) key.
Table 19. Intel® Remote Management Module 4 (RMM4) Options
When the BMC FW initializes, it attempts to access the Intel® RMM4 Lite. If the attempt to access the Intel®
RMM4 Lite is successful, then the BMC activates the advanced features.
On the server board Intel® RMM4 Lite key is installed at the following locations.
7.1 Dedicated Management Port
The Intel® server board S1200SPL and S1200SPO include a dedicated 1GbE RJ45 Management Port. The
management port is active with or without the RMM4 Lite key installed.
7.2 Keyboard, Video, and Mouse (KVM) Redirection
The BMC firmware supports keyboard, video, and mouse redirection (KVM) over LAN. This feature is available
remotely from the embedded web server as a Java applet. This feature is only enabled when the Intel® RMM4
lite is present. The client system must have a Java Runtime Environment* (JRE*) version 6.0 or later to run the
KVM or media redirection applets.
The BMC supports an embedded KVM application (Remote Console) that can be launched from the embedded
web server from a remote console. USB1.1 or USB 2.0 based mouse and keyboard redirection are supported.
It is also possible to use the KVM-redirection (KVM-r) session concurrently with media-redirection (media-r).
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Figure 20. Intel® RMM4 Lite Activation Key Installation
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Intel® Server Board S1200SP Family Technical Product Specification
This feature allows a user to interactively use the keyboard, video, and mouse functions of the remote server
as if the user were physically at the managed server.
KVM redirection console supports the following keyboard layouts: English, Dutch, French, German, Italian,
Russian, and Spanish.
KVM redirection includes a soft keyboard function. The soft keyboard is used to simulate an entire keyboard
that is connected to the remote system. The soft keyboard functionality supports the following layouts:
English, Dutch, French, German, Italian, Russian, and Spanish.
The KVM-redirection feature automatically senses video resolution for best possible screen capture and
provides high-performance mouse tracking and synchronization. It allows remote viewing and configuration
in pre-boot POST and BIOS setup, once BIOS has initialized video.
Other attributes of this feature include:
• Encryption of the redirected screen, keyboard, and mouse
• Compression of the redirected screen
• Ability to select a mouse configuration based on the OS type
• Supports user definable keyboard macros
KVM redirection feature supports the following resolutions and refresh rates:
• 640x480 at 60Hz, 72Hz, 75Hz, 85Hz, 100Hz
• 800x600 at 60Hz, 72Hz, 75Hz, 85Hz
• 1024x768 at 60Hz, 72Hz, 75Hz, 85Hz
• 1280x960 at 60Hz
• 1280x1024 at 60Hz
• 1600x1200 at 60Hz
• 1920x1080 (1080p),
• 1920x1200 (WUXGA)
• 1650x1080 (WSXGA+)
7.2.1 Remote Console
The Remote Console is the redirected screen, keyboard and mouse of the remote host system. To use the
Remote Console window of your managed host system, the browser must include a Java* Runtime
Environment plug-in. If the browser has no Java support, such as with a small handheld device, the user can
maintain the remote host system using the administration forms displayed by the browser.
The Remote Console window is a Java Applet that establishes TCP connections to the BMC. The protocol that
is run over these connections is a unique KVM protocol and not HTTP or HTTPS. This protocol uses ports
#7578 for KVM, #5120 for CDROM media redirection, and #5123 for Floppy/USB media redirection. When
encryption is enabled, the protocol uses ports #7582 for KVM, #5124 for CDROM media redirection, and
#5127 for Floppy/USB media redirection. The local network environment must permit these connections to
be made, that is, the firewall and, in case of a private internal network, the NAT (Network Address Translation)
settings have to be configured accordingly.
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7.2.2 Performance
The remote display accurately represents the local display. The feature adapts to changes to the video
resolution of the local display and continues to work smoothly when the system transitions from graphics to
text or vice versa. The responsiveness may be slightly delayed depending on the bandwidth and latency of the
network.
Enabling KVM and/or media encryption will degrade performance. Enabling video compression provides the
fastest response while disabling compression provides better video quality.
For the best possible KVM performance, a 2Mb/sec link or higher is recommended.
The redirection of KVM over IP is performed in parallel with the local KVM without affecting the local KVM
operation.
7.2.3 Security
The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual
algorithm that is used is negotiated with the client based on the client’s capabilities.
7.2.4 Availability
The remote KVM session is available even when the server is powered-off (in stand-by mode). No re-start of
the remote KVM session is required during a server reset or power on/off. A BMC reset (for example, due to a
BMC Watchdog initiated reset or BMC reset after BMC FW update) requires the session to be re-established.
KVM sessions persist across system reset, but not across an AC power loss.
7.2.5 Usage
As the server is powered up, the remote KVM session displays the complete BIOS boot process. The user can
interact with BIOS setup, change and save settings as well as enter and interact with option ROM configuration
screens.
At least two concurrent remote KVM sessions are supported. It is possible for at least two different users to
connect to the same server and start remote KVM sessions.
7.2.6 Force-enter BIOS Setup
KVM redirection can present an option to force-enter BIOS Setup. This enables the system to enter F2 setup
while booting which is often missed by the time the remote console redirects the video.
7.3 Media Redirection
The embedded web server provides a Java applet to enable remote media redirection. This may be used in
conjunction with the remote KVM feature, or as a standalone applet.
The media redirection feature is intended to allow system administrators or users to mount a remote IDE or
USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server. Once mounted, the remote
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Intel® Server Board S1200SP Family Technical Product Specification
device appears just like a local device to the server, allowing system administrators or users to install software
(including operating systems), copy files, update BIOS, and so on, or boot the server from this device.
The following capabilities are supported:
• The operation of remotely mounted devices is independent of the local devices on the server. Both remote
and local devices are useable in parallel.
• Either IDE (CD-ROM, floppy) or USB devices can be mounted as a remote device to the server.
• It is possible to boot all supported operating systems from the remotely mounted device and to boot from
disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. See the Tested/supported Operating System List
for more information.
• Media redirection supports redirection for both a virtual CD device and a virtual Floppy/USB device
concurrently. The CD device may be either a local CD drive or else an ISO image file; the Floppy/USB device
may be a local Floppy drive, a local USB device, or a disk image file.
• The media redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual
algorithm that is used is negotiated with the client based on the client’s capabilities.
• A remote media session is maintained even when the server is powered-off (in standby mode). No restart
of the remote media session is required during a server reset or power on/off. A BMC reset (for example,
due to a BMC reset after BMC FW update) requires the session to be re-established
• The mounted device is visible to (and useable by) managed system’s OS and BIOS in both pre-boot and
post-boot states.
• The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to
boot from this remote device.
• It is possible to install an operating system on a bare metal server (no OS present) using the remotely
mounted device. This may also require the use of KVM-r to configure the OS during install.
USB storage devices appear as floppy disks over media redirection. This allows for the installation of device
drivers during OS installation.
If either a virtual IDE or virtual floppy device is remotely attached during system boot, both the virtual IDE and
virtual floppy are presented as bootable devices. It is not possible to present only a single-mounted device
type to the system BIOS.
7.3.1 Availability
The default inactivity timeout is 30 minutes and is not user-configurable. Media redirection sessions persist
across system reset but not across an AC power loss or BMC reset.
7.3.2 Network Port Usage
The KVM and media redirection features use the following ports:
• 5120 – CD Redirection
• 5123 – FD Redirection
• 5124 – CD Redirection (Secure)
• 5127 – FD Redirection (Secure)
• 7578 – Video Redirection
• 7582 – Video Redirection (Secure)
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Connector
Quantity
Reference Designators
Connector Type
Pin Count
Power supply
3
J9H1
J9B1
J9F1
Main power
CPU power
PS AUX
24
8
5
CPU 1 U6F1
CPU sockets
1151
Main memory
4
J7C1, J8C2, J8C3, J9C1
DIMM sockets
240
PCI Express* x8 mechanical
2
J1B1, J2B1
Card edge
98
PCI Express* x16 mechanical
1
J3B2
Card edge
164
RJ45+USB 3.0 connector
1
JA5A1
Connector
32
NIC connector
2
JA7A1, J6A2
Connector
Intel® RMM4 Lite
1
J3B1
Connector
8
SATA Key to enable ESRT2 RAID5
1
J9K1
Header
4
System fans
4
J3K2, J8K2, J8K3, J8B1
Header
4
CPU fan
1
J7K1
Header
4
Battery
1
BT2F1
Battery holder
2
VGA 1 J8A1
Connector
15
Display Port
1
J4A1
Connector
4
Serial port
1
J9A1
Connector
9
Front panel
1
J9E1
Header
24
USB 2.0 rear IO
1
J6A1
connector
8
Internal Dual USB 3.0
1
J1J1
Header
20
Internal Dual USB 2.0
1
J1J2
Header
10
M.2 SSD
1
J2G1
connector
75
Internal USB
1
J1K3
Type-A USB
4
SATA
8
J1K4, J1K1, J1K5,
J1K2, J2K4, J2K3, J2K1, J2K2
Connector
7
HSBP_I2C
1
J3K3
Header
3
SATA SGPIO
2
J2K5, J2K6
Header
5
LCP (Header reserved but LCP module
not supported)
1
J1G3
Header
7
8 On-board Connector/Header Overview
The following section provides detailed information regarding all connectors, headers, and jumpers on the
server boards.
8.1 Board Connector Information
The following table lists all connector types available on the board and the corresponding preference
designators printed on the silkscreen.
Table 20. Board Connector Matrix
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Intel® Server Board S1200SP Family Technical Product Specification
Connector
Quantity
Reference Designators
Connector Type
Pin Count
IPMB
1
J1G2
Header
4
Configuration jumpers
5
J4B1 (Force Integrated BMC update),
J1F4 (Password Clear),
J7B1 (BIOS Recovery),
J4C1 (Reset BIOS Configuration)
J1F1 (ME Firmware Update)
Jumper
3
TPM
1
J8K1
Connector
14
Chassis Intrusion
1
J9B2
Header
2
I/O Module Connector
1
J1C1
Connector
80
SAS Module Connector
1
J4J1
Connector
80
Pin
IO
Signal Name
Pin
IO
Signal Name
1
PWR
+3.3V
13
PWR
+3.3V
2
PWR
+3.3V
14
PWR
-12V (NA for most designs)
3
GND
GND
15
GND
GND
4
PWR
+5V
16 I PS_ON#
5
GND
GND
17
GND
GND
6
PWR
+5V
18
GND
GND
7
GND
GND
19
GND
GND
8 O PWR_GD
20
NC
NC
9
PWR
SB5V
21
PWR
+5V
10
PWR
+12V
22
PWR
+5V
11
PWR
+12V
23
PWR
+5V
12
PWR
+3.3V
24
GND
GND
Pin
IO
Signal Name
Pin
IO
Signal Name
1
GND
GND
5
PWR
P12V1
2
GND
GND
6
PWR
P12V1
3
GND
GND
7
PWR
P12V2
4
GND
GND
8
PWR
P12V2
8.2 Power Connectors
The main power supply connection uses an SSI-compliant 2x12 pin connector (J9H1).
Two additional power-related connectors also exist:
• One SSI-compliant 2x4 pin power connector (J9B1) to provide 12-V power to the CPU voltage regulators
and memory.
• One SSI-compliant 1x5 pin connector (J9F1) to provide I2C monitoring of the power supply.
The following tables define these connector pin-outs:
Table 21. Main Power Connector Pin-out (J9H1)
Table 22. CPU Power Connector Pin-out (J9B1)
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
1 I PMBUS_CLK
2
IO
PMBUS_DATA
3 O IRQ_PMBUS_ALERT_N
4
GND
GND Return Sense
5 I P3V3 Sense
Pin
IO
Signal Name
1
PWR
P3V_BAT
2
GND
GND
Pin
IO
Name
Pin
IO
Name
1
PWR
P5V_AUX
17 I USB3_TX_DN
2
IO
USB2_DN
18 I USB3_TX_DP
3
IO
USB2_DP
19
PWR
VCT
4
GND
GND
20
IO
MDI_P0
5 O USB3_RX_DN
21
IO
MDI_N0
6 O USB3_RX_DP
22
IO
MDI_P1
7
GND
GND
23
IO
MDI_N1
8 I USB3_TX_DN
24
IO
MDI_P2
9 I USB3_TX_DP
25
IO
MDI_N2
10
PWR
P5V_AUX
26
IO
MDI_P3
11
IO
USB2_DN
27
IO
MDI_N3
12
IO
USB2_DP
28
GND
GND
13
GND
GND
29 I LED1_ANODE
14 O USB3_RX_DN
30 O LED1_CATHODE
15 O USB3_RX_DP
31
IO
LED2_ANODE
16
GND
GND
32
IO
LED2_CATHODE
Table 23. PMBUS SSI Connector Pin-out (J9F1)
Table 24. Battery Holder (BT2F1)
8.3 System Management Headers
8.3.1 Intel
®
Remote Management Module 4 Lite Connector
The Intel® Server Board S1200SPL and S1200SPO provide a 7-pin Intel® RMM4 Lite connector and a stacked
connector that includes a USB 3.0 and a dedicated 1GbE RJ45 Management Port. The management port is
active with or without the RMM4 Lite key installed. The S1200SPS board does not support Intel® RMM4.
This server board does not support third-party management cards.
Note: This connector is not compatible with the previous generation Intel® Remote Management Modules
(Intel® RMM/RMM2/RMM3)
Table 25. Stacked connector of USB 3.0+ dedicated RJ45 Management Port Pin-out (JA5A1)
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
Pin
IO
Signal Name
1
PWR
P3V3_AUX
2 O SPI_RMM4_LITE_DI
3
NC
NC 4 I
SPI_RMM4_LITE_CLK
5 I SPI_RMM4_LITE_DO
6
GND
GND
7 I SPI_RMM4_LITE_CS_N
8
GND
GND
Pin
IO
Signal Name
Pin
IO
Signal Name
1
NC
Key Pin
2
IO
LPC_LAD<1>
3
IO
LPC_LAD<0>
4
GND
GND
5
IO
IRQ_SERIAL
6 I LPC_FRAME_N
7
PWR
P3V3
8
GND
GND
9 I RST_BMC_NIC_LRESET_LVC3_R_N
10 I CLK_33M_TPM_CONN
11
IO
LPC_LAD<3>
12
GND
GND
13
GND
GND
14
IO
LPC_LAD<2>
Pin
IO
Signal Name
1
GND
GND
2 I Pull-up (to P3V3_AUX)
3
GND
GND
4 I OW_PCH_SATA_RAID_KEY
Pin
IO
Signal Name
1
IO
SMB_HSBP_DATA
2
GND
GND
3 I SMB_HSBP_CLK
Table 26. Intel® RMM4 – Lite Connector Pin-out (J3B1)
8.3.2 TPM Connector
The Intel® Server Board S1200SPL and S1200SPO support TPM 2.0 module AXXTPMSPE6. The S1200SPS
server board does not support TPM 2.0 module.
Table 27. TPM Connector Pin-out (J8K1)
8.3.3 Intel
®
ESRT2 RAID Upgrade Key Connector
The server board provides one connector to support Intel® ESRT2 RAID Upgrade Key. The I Upgrade Key is a
small PCB board that enables RAID 5 software stack of ESRT2 SW RAID. The pin configuration of connector is
identical and defined in the following table:
Table 28. Intel® ESRT2 RAID Upgrade Key Connector Pin-out (J9K1)
Note: The ESRT2 RAID 5 under legacy BIOS mode IS NOT supported.
8.3.4 HSBP SMBUS Header
73
Table 29. HSBP SMBUS Header Pin-out (J3K3)
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Intel® Server Board S1200SP Family Technical Product Specification
Header State
Description
Pins 1 and 2 closed
BMC CHASIS_N is pulled HIGH. Chassis cover is closed.
Pins 1 and 2 open
BMC CHASIS_N is pulled LOW. Chassis cover is removed.
Pin
IO
Signal Name
1 I SGPIO_CLOCK
2 I SGPIO_LOAD
3
GND
GND
4 I SGPIO_DATAOUT
5 O SGPIO_DATAIN
Pin
IO
Signal Name
1
IO
SMB_IPMB_5VSTBY_DATA
2
GND
GND
3 I SMB_IPMB_5VSTBY_CLK
4
PWR
P5V_AUX
8.3.5 Chassis Intrusion Header
The Chassis Intrusion header is connected via a two-wire cable to a switch assembly that is mounted just under
the chassis cover on systems that support this feature. When the chassis cover is removed, the switch and thus
the electrical connection between the pins on this header become open allowing the BMC’s CHASIS_N pin to
be pulled LOW. The BMC’s CHASIS-N pin is used by FW to note the change in the chassis cover status.
Table 30. Chassis Intrusion Header Pin-out (J9B2)
8.3.6 SATA SGPIO Header
Two SATA SGPIO 5 pin headers are implemented on the Intel® Server Board S1200SPL and S1200SPO: one is
for Port0-3 (White) and the other is for Port4-7 (Black).
Table 31. SATA SGPIO Header Pin-out (J2K5, J2K6)
8.3.7 IPMB Connector
An IPMB header is provided on the baseboard to support connectivity with other IPMI-compliant controllers
(e.g. 3rd party management PCIe* cards).
Table 32. IPMB Connector Pin-out (J1G2)
8.4 Front Panel Connector
The server board provides a 24-pin front panel connector for use with Intel® and third-party chassis. The
connector consists of a 24-pin SSI compatible front panel connector. The 24-pin SSI front panel connector
provides various front panel features including:
• Power/Sleep Button
• System ID Button
• NMI Button
• NIC Activity LEDs
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Pin
IO
Signal Name
Pin
IO
Signal Name
1
PWR
3VSB (Power LED Anode)
2
PWR
3VSB (Front Panel Power)
3
NC
Key
4
PWR
5VSB (ID LED Anode)
5
I
FP_PWR_LED_N
6 I FP_ID_LED_N
7
PWR
3.3V (HDD Activity LED Anode)
8 I LED_STATUS_GREEN_N
9 I LED_HDD_ACTIVITY_N
10 I LED_STATUS_AMBER_N
11
O
FP_PWR_BTN_N
12 I LED_NIC1_ACT_N
13
GND
GND (Power Button GND)
14 I LED_NIC1_LINK_N
15
O
SYS_RESET
16
IO
SMB_SDA
17
GND
GND (Reset GND)
18
I
SMB_SCL
19
O
FP_ID_BTN_N
20 O FM_INTRUDER_N
21
IO
Pull-up (1-wire Temp Sensor)
22 I LED_NIC2_ACT_N
23
O
FP_NMI_BTN_N
24 I LED_NIC2_LINK_N
State
Power Mode
LED
Description
Power-off
Non-ACPI
Off
System power is off, and the BIOS has not initialized the chipset.
Power-on
Non-ACPI
On
System power is on
S5
ACPI
Off
Mechanical is off, and the operating system has not saved any
context to the hard disk.
S4
ACPI
Off
Mechanical is off. The operating system has saved context to the
hard disk.
S3-S1
ACPI
Slow blink
DC power is still on. The operating system has saved context and
gone into a level of low-power state.
S0
ACPI
Steady on
System and the operating system are up and running.
• Hard Drive Activity LEDs
• System Status LED
• System ID LED
The following table provides the pin-out for this connector:
Table 33. Front Panel 24-pin Connector Pin-out (J9E1)
8.4.1 Power/Sleep Button and LED Support
Pressing the Power button will toggle the system power on and off. This button also functions as a sleep button
if enabled by an ACPI compliant operating system. Pressing this button will send a signal to the integrated
BMC, which will power on or power off the system. The power LED is a single color and is capable of supporting
different indicator states as defined in the following table.
Table 34. Power/Sleep LED Functional States
8.4.2 System ID Button and LED Support
Pressing the System ID Button will toggle both the ID LED on the front panel and the Blue ID LED on the server
board on and off. The System ID LED is used to identify the system for maintenance when installed in a rack
of similar server systems. The System ID LED can also be toggled on and off remotely using the IPMI Chassis
Identify command which will cause the LED to blink for 15 seconds.
8.4.3 System Reset Button Support
When pressed, this button will reboot and re-initialize the system.
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Causal Event
NMI
Signal
Generation
Front Panel Diag Interrupt Sensor Event Logging
Support
Chassis Control command (pulse diagnostic interrupt)
X
–
Front panel diagnostic interrupt button pressed
X
X
Watchdog Timer pre-timeout expiration with
NMI/diagnostic interrupt action
X
X
8.4.4 NMI Button Support
When the NMI button is pressed, it puts the server in a halt state and causes the BMC to issue a non-maskable
interrupt (NMI). This can be useful when performing diagnostics for a given issue where a memory download
is necessary to help determine the cause of the problem. Once an NMI has been generated by the BMC, the
BMC does not generate another NMI until the system has been reset or powered down.
• The following actions cause the BMC to generate an NMI pulse:
• Receiving a Chassis Control command to pulse the diagnostic interrupt. This command does not cause an
event to be logged in the SEL.
Watchdog timer pre-timeout expiration with NMI/diagnostic interrupt pre-timeout action enabled.
The following table describes behavior regarding NMI signal generation and event logging by the BMC.
Table 35. NMI Signal Generation and Event Logging
8.4.5 NIC Activity LED Support
The Front Control Panel includes an activity LED indicator for each on-board Network Interface Controller
(NIC). When a network link is detected, the LED will turn on solid. The LED will blink once network activity
occurs at a rate that is consistent with the amount of network activity that is occurring.
8.4.6 Hard Drive Activity LED Support
The drive activity LED on the front panel indicates drive activity from the on-board hard disk controllers. The
server board also provides a header giving access to this LED for add-in controllers.
8.4.7 System Status LED Support
The System Status LED is a bi-color (Green/Amber) indicator that shows the current health of the server
system. The system provides two locations for this feature; one is located on the Front Control Panel, the other
is located on the back edge of the server board, viewable from the back of the system. Both LEDs are tied
together and will show the same state. The System Status LED states are driven by the on-board platform
management sub-system.
8.5 I/O Connectors
8.5.1 VGA Connector
The following table details the pin-out definition of the VGA connector.
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
1
A/O
V_IO_R
2
A/O
V_IO_G
3
A/O
V_IO_B
4
NC
TP_VGA_J_4
5
GND
GND
6
GND
GND
7
GND
GND
8
GND
GND
9
NC
TP_VGA_J11_9
10
GND
GND
11
NC
TP_VGA_J_11
12
IO
V_BMC_5V_DDC_SDA
13
I
V_IO_HSYN
14
I
V_IO_VSYN
15 I V_BMC_5V_DDC_SCL
Pin
IO
Signal Name
Pin
IO
Signal Name
1 I DP_DDI_TX_DP0
2
GND
GND
3 I DP_DDI_TX_DN0
4
I
DP_DDI_TX_DP1
5
GND
GND
6
I
DP_DDI_TX_DN1
7 I DP_DDI_TX_DP2
8
GND
GND
9 I DP_DDI_TX_DN2
10
I
DP_DDI_TX_DP3
11
GND
GND
12
I
DP_DDI_TX_DN3
13 O FM_DP_DNG_DETECT
14
I
PD_DP_CONFIG2
15
IO
DP_AUX_DP
16
GND
GND
17
IO
DP_AUX_DN
18
O
FM_DP_HPD_SINK
19
GND
GND
20
PWR
P3V3
Table 36. VGA Connector Pin-out (J8A1)
8.5.2 Display Port Connector
The following table details the pin-out definition of the Display Port connector that is only available on
S1200SPL.
Table 37. Display Port Connector Pin-out (J4A1)
8.5.3 SATA Connectors
The Intel® Server Board S1200SPL and S1200SPO provide up to eight on-board SATA connectors, while the
Intel® Server Board S1200SPS provides six SATA connectors: SATA-0 (J2K4), SATA-1 (J2K2), SATA-2 (J2K3),
SATA-3 (J2K1), SATA-4 (J1K5), SATA-5 (J1K2), SATA-6 (J1K4), and SATA-7 (J1K1).
SATA-4 connector is designed to be compatible with Apacer* SATADOM.
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Pin
IO
Signal Name
MH1
PWR
GND
1
GND
GND
2
I
SATA_TX_P
3
I
SATA_TX_N
4
GND
GND
5
O
SATA_RX_N
6
O
SATA_RX_P
7
PWR
GND
MH2
PWR
P5V (For Apacer* SATADOM)
GND (For SATA)
Table 38. SATA/SATADOM capable Connector Pin-out (J1K4, J1K1, J1K5, J1K2, J2K4, J2K3, J2K1, J2K2)
8.5.4 M.2 SATA Connector (J2G1)
The Intel® Server Board S1200SPL and S1200SPO support one 22x42mm enterprise M.2 SATA SSD. In order
to use M.2 device, a SATA cable need to be connected between any of the SATA connectors (SATA-0 to SATA7, recommend SATA-7 for better cable routing) and the SATA connector (black) next to the jumpers. See
illustration below. The cable shown can be purchased separately.
Figure 21. Installing M.2 Device
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
Pin
IO
Signal Name
1 O SPA_DCD
2 O SPA_DSR
3 O SPA_SIN_N
4 I SPA_RTS
5 I SPA_SOUT_N
6 O SPA_CTS
7 I SPA_DTR
8 O SPA_RI
9
GND
GND
Table 39. M.2 SATA Connector Pinout
8.5.5 Serial Port Connector
The server board provides one internal 9-pin Serial header. The following tables define the pin-out.
Table 40. Internal 9-pin Serial Header Pin-out (J9A1)
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
Pin
IO
Signal Name
1
PWR
P5V_AUX
2
PWR
P5V_AUX
3
IO
USB_N
4
IO
USB_N
5
IO
USB_P
6
IO
USB_P
7
GND
GND
8
GND
GND
9
NC
Key Pin
10
NC
NC
Pin
IO
Signal Name
Pin
IO
Signal Name
1
PWR
P5V_AUX
key
NC
KEY
2 O USB3_RX_DN
19
PWR
P5V_AUX
3 O USB3_RX_DP
18 O USB3_RX_DN
4
GND
GND
17 O USB3_RX_DP
5 I USB3_TX_DN
16
GND
GND
6 I USB3_TX_DP
15 I USB3_TX_DN
7
GND
GND
14 I USB3_TX_DP
8
IO
USB2_DN
13
GND
GND
9
IO
USB2_DP
12
IO
USB2_DN
10 O TP_USB3_ID
11
IO
USB2_DP
Pin
IO
Signal Name
Pin
IO
Signal Name
1
PWR
P5V_AUX
5
PWR
P5V_AUX
2
IO
USB2_DN
6
IO
USB2_DN
3
IO
USB2_DP
7
IO
USB2_DP
4
GND
GND
8
GND
GND
Pin
IO
Signal Name
1
PWR
P5V_AUX
2
IO
USB2_DN
3
IO
USB2_DP
4
GND
GND
8.5.6 USB Connector
The Server Board S1200SP Series provide:
One 2x5 pin USB 2.0 header, providing front panel support for two USB ports respectively
One 2x10 pin USB 3.0 header on S1200SPL and S1200SPO, providing front panel support for two USB
3.0 ports respectively (P4000XXSFDR chassis)
2x USB 2.0 ports at the back of the board
2x USB 3.0 ports at the back of the board
1x internal Type-A USB 2.0 port to support the installation of a USB device inside the server chassis
Table 41. USB 2.0 FP Header (J1J2)
Table 42. USB3.0 FP Header (J1J1)
Table 43. USB 2.0 Connector (Rear IO) (J6A1)
Table 44. Internal Type A USB Port Pin-out (J1K3)
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
Pin
IO
Signal Name
1
PWR
3.3V
2
PWR
12V
3
PWR
3.3V
4
PWR
12V
5
PWR
3.3V
6
PWR
12V
7
PWR
3.3V
8
PWR
12V
9
NC
RSVD_SE
10 I FRU/TEMP ADDR [0]
11
GND
GND
12
PWR
5V STBY
13
NC
RSVD_DP
14 I FM_IO_MODULE_EN
15
NC
RSVD_DN
16
PWR
3.3V STBY
17
GND
GND
18 O LED_GLOBAL ACT#
19
NC
RSVD_DP
20 O FM_IOM_PRESENT_N
21
NC
RSVD_DN
22 O WAKE#
23
GND
GND
24 I PERST#
25
I
SMB CLK
26
GND
GND
27
IO
SMB DAT
28 I rIOM REFCLK+ [0]
29
GND
GND
30 I rIOM REFCLK- [0]
31 I PCIe Gen3 Tn [7]
32
GND
GND
33 I PCIe Gen3 Tp [7]
34 O PCIe Gen3 Rn [7]
35
GND
GND
36 O PCIe Gen3 Rp [7]]
37 I PCIe Gen3 Tn [6]
38
GND
GND
39 I PCIe Gen3 Tp [6]
40 O PCIe Gen3 Rn [6]
41
GND
GND
42 O PCIe Gen3 Rp [6]
43 I PCIe Gen3 Tn [5]
44
GND
GND
45 I PCIe Gen3 Tp [5]
46 O PCIe Gen3 Rn [5]
47
GND
GND
48 O PCIe Gen3 Rp [5]
49 I PCIe Gen3 Tn [4]
50
GND
GND
51 I PCIe Gen3 Tp [4]
52 O PCIe Gen3 Rn [4]
53
GND
GND
54 O PCIe Gen3 Rp [4]
55 I PCIe Gen3 Tn [3]
56
GND
GND
57 I PCIe Gen3 Tp [3]
58 O PCIe Gen3 Rn [3]
59
GND
GND
60 O PCIe Gen3 Rp [3]
61 I PCIe Gen3 Tn [2]
62
GND
GND
63 I PCIe Gen3 Tp [2]
64 O PCIe Gen3 Rn [2]
65
GND
GND
66 O PCIe Gen3 Rp [2]
67 I PCIe Gen3 Tn [1]
68
GND
GND
69 I PCIe Gen3 Tp [1]
70 O PCIe Gen3 Rn [1]
71
GND
GND
72 O PCIe Gen3 Rp [1]
73 I PCIe Gen3 Tn [0]
74
GND
GND
75 I PCIe Gen3 Tp [0]
76 O PCIe Gen3 Rn [0]
77
GND
GND
78 O PCIe Gen3 Rp [0]
79
NC
RSVD_SE
80
GND
GND
8.5.7 I/O Module Connector
The following table details the pin-out definition of the I/O Module connector which is available only on the
Intel® Server Board S1200SPO.
Table 45. I/O Module Connector Pin-out (J1C1)
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
Pin
IO
Signal Name
79
PWR
3.3V
80
PWR
12V
77
PWR
3.3V
78
PWR
12V
75
PWR
3.3V
76
PWR
12V
73
PWR
3.3V
74
PWR
12V
71
NC
RSVD_SE
72 I FRU/TEMP ADDR [0]
69
GND
GND
70
PWR
5V STBY
67
NC
RSVD_DP
68 I FM_SAS_MODULE_EN_N
65
NC
RSVD_DN
66
PWR
3.3V STBY
63
GND
GND
64 O LED_HDD_N
61
NC
RSVD_DP
62 O FM_SAS_PRESENT_N
59
NC
RSVD_DN
60
O
WAKE#
57
GND
GND
58
I
PERST#
55
I
SMB CLK
56
GND
GND
53
IO
SMB DAT
54 I rSASm REFCLK+ [0]
51
GND
GND
52 I rSASm REFCLK- [0]
49 I PCIe Gen3 Tn [7]
50
GND
GND
47 I PCIe Gen3 Tp [7]
48 O PCIe Gen3 Rn [7]
45
GND
GND
46 O PCIe Gen3 Rp [7]
43 I PCIe Gen3 Tn [6]
44
GND
GND
41 I PCIe Gen3 Tp [6]
42 O PCIe Gen3 Rn [6]
39
GND
GND
40 O PCIe Gen3 Rp [6]
37 I PCIe Gen3 Tn [5]
38
GND
GND
35 I PCIe Gen3 Tp [5]
36 O PCIe Gen3 Rn [5]
33
GND
GND
34 O PCIe Gen3 Rp [5]
31 I PCIe Gen3 Tn [4]
32
GND
GND
29 I PCIe Gen3 Tp [4]
30 O PCIe Gen3 Rn [4]
8.5.8 SAS/ROC Module Connector
The Intel® Server Board S1200SPL and S1200SPO support Intel® Integrated RAID Module (known as SAS/ROC
module). The SAS/ROC module can be installed to the server board as shown below.
Figure 22. Installing Intel® Integrated RAID Module
The following table details the pin-out definition of the SAS/ROC module connector.
Table 46. I/O Module Connector Pin-out (J4J1)
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
IO
Signal Name
Pin
IO
Signal Name
27
GND
GND
28 O PCIe Gen3 Rp [4]
25 I PCIe Gen3 Tn [3]
26
GND
GND
23 I PCIe Gen3 Tp [3]
24 O PCIe Gen3 Rn [3]
21
GND
GND
22 O PCIe Gen3 Rp [3]
19 I PCIe Gen3 Tn [2]
20
GND
GND
17 I PCIe Gen3 Tp [2]
18 O PCIe Gen3 Rn [2]
15
GND
GND
16 O PCIe Gen3 Rp [2]
13 I PCIe Gen3 Tn [1]
14
GND
GND
11 I PCIe Gen3 Tp [1]
12 O PCIe Gen3 Rn [1]
9
GND
GND
10 O PCIe Gen3 Rp [1]
7 I PCIe Gen3 Tn [0]
8
GND
GND
5 I PCIe Gen3 Tp [0]
6 O PCIe Gen3 Rn [0]
3
GND
GND
4 O PCIe Gen3 Rp [0]
1
NC
RSVD_SE
2
GND
GND
Pin
IO
Signal Name
R1
PWR
NIC_TRCT
R2
IO
MDI_DP0
R3
IO
MDI_DN0
R4
IO
MDI_DP1
R5
IO
MDI_DN1
R6
IO
MDI_DP2
R7
IO
MDI_DN2
R8
IO
MDI_DP3
R9
IO
MDI_DN3
R10
GND
GND
L1
IO
LED2_1G_N
L2
IO
LED2_100M_N
L3 O LED1_LINK_ACT_N
L4
I
P3V3
8.5.9 NIC Connector
Table 47. NIC Connector Pin-out (JA7A1, J6A2)
8.6 Fan Headers
The server board provides five SSI-compliant 4-pin fans to use as CPU and I/O cooling fans. 3-pin fans are
supported on all fan headers. The pin configuration for each of the 4-pin fan headers is identical and defined
in the following tables.
One 4-pin fan header is designated as processor cooling fan:
- CPU fan (J7K1)
Three 4-pin fan headers are designated as system fans:
- System fan 1 (J3K2)
- System fan 2 (J8K2)
- System fan 3 (J8K3)
One 4-pin fan header is designated as a rear system fan:
- System fan 4 (J8B1)
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Intel® Server Board S1200SP Family Technical Product Specification
Pin
Signal Name
Type
Description
1
Ground
GND
Ground is the power supply ground
2
12V
Power
Power supply 12 V
3
Fan Tach Fan
PWM
In Out
FAN_TACH signal is connected to the BMC to monitor the fan speed
FAN_PWM signal to control fan speed
4
Fan PWM Fan
Tach
Out In
FAN_PWM signal to control fan speed FAN_TACH signal is connected to the
BMC to monitor the fan speed
The CPU fan and System fans are shown as below.
Figure 23. Fan Headers on the Server Borad
Table 48. SSI 4-pin Fan Header Pin-out (J3K2, J8B1, J7K1, J8K2, J8K3)
Note: Intel Corporation server boards support peripheral components and can contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are
designed and tested to meet the intended thermal requirements of these components when the fully
integrated system is used together. It is the responsibility of the system integrator that chooses not to use
Intel developed server building blocks to consult vendor datasheets and operating parameters to determine
the amount of airflow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible if components fail or the server board does not operate correctly when used
outside any of its published operating or non-operating limits.
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Intel® Server Board S1200SP Family Technical Product Specification
9 Jumper Blocks
The server board includes several 3-pin jumper blocks which are used to as part of a process to restore a board
function back to a normal functional state. The following diagram and sections identify the location of each
jumper block and provides a description of their use.
The following symbol identifies Pin 1 on each jumper block on the silkscreen:
Figure 24. Jumper Blocks (J4B1, J1F1, J1F4 J7B1, J4C1)
Note:
1. For safety purposes, the power cord should be disconnected from a system before removing any system
components or moving any of the on-board jumper blocks.
2. System Update and Recovery files are included in the System Update Packages (SUP) posted to Intel’s
website.
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Jumper Name
Pins
System Results
J4C1: BIOS Default
1-2
These pins should have a jumper in place for normal system operation. (Default)
2-3
If pins 2-3 are jumpered with AC power plugged in, the CMOS settings clear in 5 seconds.
Pins 2-3 should not be jumpered for normal system operation.
J7B1: BIOS Recovery
1-2
Pins 1-2 should be jumpered for normal system operation. (Default)
2-3
The main system BIOS does not boot with pins 2-3 jumpered. The system only boots
from EFI-bootable recovery media with a recovery BIOS image present.
J1F4: Password Clear
1-2
These pins should have a jumper in place for normal system operation.
2-3
To clear administrator and user passwords, power on the system with pins 2-3
connected. The administrator and user passwords clear in 5-10 seconds after power on.
Pins 2-3 should not be connected for normal system operation.
J1F1: ME Force Update
1-2
ME Firmware Force Update Mode – Disabled (Default)
2-3
ME Firmware Force Update Mode – Enabled
J4B1: BMC Force Update
1-2
BMC Firmware Force Update Mode – Disabled (Default)
2-3
BMC Firmware Force Update Mode – Enabled
Table 49. Server Board Jumpers (J4B1, J1F1, J1F4, J7B1, J4C1)
9.1 BIOS Default Jumper (J4C1)
1. This jumper resets BIOS Setup options to their default factory settings.
2. Power down the server and unplug the power cords.
3. Open the chassis and remove the Riser #2 assembly.
4. Move BIOS DFLT jumper from the default (pins 1 and 2) position to the Set BIOS Defaults position (pins
2 and 3).
5. Wait 5 seconds then move the jumper back to the default position of pins 1 and 2.
6. Install riser card assembly.
7. Install Power Cords.
8. Power on system.
Note: BIOS Error Manager should report a 5220 error code (BIOS Settings reset to default settings).
9.2 BIOS Recovery Jumper (J7B1)
When the BIOS Recovery jumper block is moved from its default pin position, the system will boot into a BIOS
Recovery Mode. It is used when the system BIOS has become corrupted and is non-functional, requiring a new
BIOS image to be loaded on to the server board.
Note: The BIOS Recovery jumper is ONLY used to re-install a BIOS image in the event the BIOS has become
corrupted. This jumper is NOT used when the BIOS is operating normally and you need to update the BIOS
from one version to another.
The following steps demonstrate the BIOS recovery process:
1. After downloading the latest System Update Package (SUP) from the Intel
files to the root directory of a USB media device:
86
- IPMI.EFI
®
website, copy the following
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