Intel Quark SoC X1000 User Manual
Intel® Quark SoC X1000
Debug Operations
User Guide
January 2014
Order Number: 329866-002US
Contents
Contents
1 Introduction .....................................................................................................4
1.1 Terminology ..........................................................................................5
1.2 Related Documents .................................................................................5
2 JTAG Interface ..................................................................................................7
2.1 SKU-Based JTAG Debug Capability ............................................................7
2.2 CLTAPC Instruction Table ........................................................................7
2.3 CLTAPC Data Register Table .....................................................................8
2.3.1 CLIDCODE ................................................................................8
2.3.2 CLBYPASS ................................................................................8
2.3.3 CLTAPC_SELECT .......................................................................8
2.3.4 CLTAPC_CPU_VPREQ .................................................................9
2.3.5 CLTAPC_CPU_TAPSTATUS ........................................................ 10
2.3.6 CLTAPC_CPU_VPRDY ............................................................... 10
2.3.7 CLTAPC_TAPNW_STATUS ......................................................... 10
3 Putting It All Together ..................................................................................... 12
3.1 Initial JTAG Discovery ........................................................................... 12
3.2 Check Core Powergood .......................................................................... 12
3.3 Add Core TAP to the JTAG Chain ............................................................. 12
3.4 Verify Core IDCODE .............................................................................. 13
4 JTAG Interface ................................................................................................ 14
4.1 TAP Instruction Table ............................................................................ 14
5 Run Control .................................................................................................... 15
5.1 Introduction to Probe Mode .................................................................... 15
5.2 Probe Mode Entry ................................................................................. 15
5.3 Probe Mode Exit ................................................................................... 16
5.4 Reset Break ......................................................................................... 16
5.5 TAPSTATUS Register ............................................................................. 16
5.6 Accessing Architectural Registers ............................................................ 17
5.6.1 Submitting Instructions to the Core ........................................... 17
5.6.1.1 Instruction Faults ...................................................... 17
5.6.2 EIP Management ..................................................................... 18
5.6.3 DR7 Management .................................................................... 18
5.6.3.1 EIP and Software Breakpoints ..................................... 18
5.6.4 WRITEPIR Register Format ....................................................... 18
5.6.5 Register Read ......................................................................... 19
5.6.6 Register Write ......................................................................... 19
5.6.7 Special Cases for Register Access .............................................. 19
5.6.7.1 PMCR ...................................................................... 19
5.6.7.2 Register Access after HLT Instruction Execution ............ 19
5.6.8 Checking for HALT State ........................................................... 20
5.6.9 Pseudo Opcodes for Architectural Register Access ........................ 20
5.6.10 Probe Mode Control Register ..................................................... 21
5.6.11 Accessing Model Specific Registers (MSR) ................................... 22
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Contents
Figures
5.7 Reading and Writing Memory ................................................................. 22
5.7.1 Management of Architectural Registers for Memory Access ............ 22
5.7.1.1 DS Selector ............................................................. 23
5.7.1.2 Adjust CPL Prior to Memory Access .............................. 23
5.7.1.3 Disable Interrupts Prior to Memory Access .................... 23
5.7.1.4 Processor Cache Flush Prior to Memory Access .............. 23
5.7.1.5 CR0 ........................................................................ 23
5.7.2 Memory Read ......................................................................... 24
5.7.3 Memory Write ......................................................................... 24
5.8 Reading and Writing I/O Ports ................................................................ 24
5.8.1 I/O Read ................................................................................ 24
5.8.2 I/O Write ............................................................................... 24
5.9 Hardware Breakpoints ........................................................................... 25
5.10 Software Breakpoints ............................................................................ 25
5.11 Single Step .......................................................................................... 25
5.12 Redirections into Probe Mode ................................................................. 25
5.12.1 Shutdown Break ...................................................................... 25
Figure 1. Intel® Quark SoC X1000 ....................................................................................4
Tables
Table 1. Terminology .....................................................................................................5
Table 2. Related Documents ...........................................................................................5
Table 3. CLTAPC TAP Instructions ....................................................................................7
Table 4. CLTAPC TAP Data Registers ................................................................................8
Table 5. CLTAPC_SELECT ...............................................................................................8
Table 6. CLTAPC_CPU_VPREQ .........................................................................................9
Table 7. CLTAPC_CPU_TAPSTATUS ................................................................................ 10
Table 8. CLTAPC_TAPNW_STATUS ................................................................................. 11
Table 9. TAP Instructions ............................................................................................. 14
Table 10. TAPSTATUS Data Register ................................................................................ 16
Table 11. Register Access PIR Values ............................................................................... 21
Table 12. PMCR Description ............................................................................................ 22
Table 13. DS Selector Values for Memory Access ............................................................... 23
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1 Introduction
Introduction
The Intel
Intel
®
Quark SoC X1000 processor is the next generation secure, low-power
®
Architecture (IA) SoC for deeply embedded applications. The SoC integrates the
Intel® Quark SoC X1000 Core plus all the required hardware components to run offthe-shelf operating systems and to leverage the vast x86 software ecosystem. For
details, see the Intel® Quark SoC X1000 Datasheet.
The Intel® Quark SoC X1000 Core (codenamed Lakemont) enables a range of lowcost, high-performance embedded system designs capable of running applications
written for the Intel architecture. The Intel® Quark SoC X1000 Core integrates a 16Kbyte unified cache and floating-point hardware onchip for improved performance. For
further details, including the Intel® Quark Core feature list, see the Intel® Quark SoC
X1000 Core Hardware Reference Manual and Intel® Quark SoC X1000 Core
Developer’s Manual.
This document assumes that the reader has some familiarity with JTAG based debug
tools and the use of JTAG for run control of an execution core.
This document provides details on JTAG based debug for any product based on the
Intel® Quark SoC X1000.
Figure 1. Intel® Quark SoC X1000
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Term
Description
ACPI Sx states
System sleep states as defined by the ACPI standard:
http://www.acpi.info/
CLTAPC
Chip level TAP Controller. This is the top level standard compliant TAP
controller for the SoC.
Debug Software
Generic term for software that controls a hardware probe connected to
the JTAG pins.
JTAG
“Joint Test Action Group” of the IEEE. This is now a generic term to
refer to the TAP and the pins used for communication with TAPs.
PIR
Probe Mode Instruction Register
PRDY#
Probe Mode Ready package pin (active low); this pin is used to signal
to Debug Software that the core has entered Probe Mode
PREQ#
Probe Mode Request package pin (active low); this pin may be used by
Debug Software to request that the core enter Probe Mode
SoC
System on chip
TAP
Test Access Port as defined by the IEEE 1149.1-1990 (including IEEE
1149.1a-1993), “IEEE Standard Test Access Port and Boundary-Scan
Architecture”
TDI
TAP Data In; the serial data input pin for the TAP chain
TDO
TAP Data Out; the serial data output pin for the TAP chain
TDR
TAP Data Register; a serial TAP data register selected by a TAP
instruction
Title and Location
Document #
Intel® Quark SoC X1000 Datasheet
https://communities.intel.com/docs/DOC-21828
329676
Intel® Quark SoC X1000 Core Hardware Reference Manual
https://communities.intel.com/docs/DOC-21825
329678
Intel® Quark SoC X1000 Core Developer’s Manual
https://communities.intel.com/docs/DOC-21826
329679
Introduction
1.1 Terminology
Table 1. Terminology
1.2 Related Documents
Table 2. Related Documents
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Title and Location
Document #
Intel® 64 and IA-32 Architectures Software Developer Manuals contain
details on architectural registers:
http://www.intel.com/content/www/us/en/processors/architecturessoftware-developer-manuals.html
Multiple
volumes
Introduction
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Function/Category
Instruction Mnemonic
Opcode (8 bits)
TDR Name
SOC IDCODE
CLIDCODE
0x02
CLIDCODE
BYPASS
CLBYPASS
0xFF
CLBYPASS
TAP NETWORK
CLTAPC_SELECT
0x11
CLTAPC_SELECT
IA Run Control
CLTAPC_CPU_VPREQ
0x51
CLTAPC_CPU_VPREQ
CLTAPC_CPU_TAPSTATUS
0x52
CLTAPC_CPU_TAPSTATUS
CLTAPC_CPU_VPRDY
0x53
CLTAPC_CPU_VPRDY
TapNW Status
CLTAPC_TAPNW_STATUS
0x69
CLTAPC_TAPNW_STATUS
RESERVED
-
All other values
-
JTAG Interface
2 JTAG Interface
The Intel® Quark SoC X1000 has the standard set of JTAG pins, TCLK, TDI, TDO, TMS,
and TRST# on the package which are routed to a debug header on the system board.
The SoC exposes a single IEEE compliant TAP by default, called the ‘Chip-Level TAP
Controller’ (CLTAPC). This TAP provides some basic system status and has the ability
to ‘add’ child TAP controllers to the serial JTAG chain.
Debug Software tools that wish to provide run control for the Intel® Quark SoC X1000
must interact with the CLTAPC to add the CPU core to the JTAG chain. The Debug
Software may also use TAP data registers (TDRs) in the CLTAPC to monitor system
status. The CLTAPC provides some features related to run control of the core which is
described in detail in Section 5.
2.1 SKU-Based JTAG Debug Capability
Not all SKUs of the Intel® Quark SoC X1000 ship with JTAG debugging enabled. To
receive details on how to enable JTAG on these SKUs, contact your Intel account
team.
2.2 CLTAPC Instruction Table
Table 3. CLTAPC TAP Instructions
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2.3 CLTAPC Data Register Table
TDR Name
TDR Length (Bits)
Reset Mechanism
Access
CLIDCODE
32b
TRST/SYNC TAP RST
Read-Only
CLBYPASS
1b
TRST/SYNC TAP RST
Read-Write
CLTAPC_SELECT
64b
TRST/SYNC TAP RST
Read-Write
CLTAPC_CPU_VPREQ
8b
PWR_GOOD†
Read-Write
CLTAPC_CPU_TAPSTATUS
8b
PWR_GOOD†
Read-Only
CLTAPC_CPU_VPRDY
1b
PWR_GOOD†
Read-Write
CLTAPC_TAPNW_STATUS
64b
PWR_GOOD†
Read-Write
† The external power supply signal is used for PWR_GOOD. These values survive a board reset if
the power supply is still connected to the board.
CLTAPC_SELECT
Bit Number
Name
Reset Value
Comments
1:0
CPUCORE_TAP_SEL
2'b00
2'b01 = Normal;
2'b10 = Excluded;
2'b11 = Shadow
63:2
RESERVED
2'b00
RESERVED
Table 4. CLTAPC TAP Data Registers
2.3.1 CLIDCODE
JTAG Interface
The CLTAPC IDCODE register is 32 bits in size. This value may be used by Debug
Software to confirm there is a working JTAG connection to the board and to confirm
the identity of the SoC.
The Intel® Quark SoC X1000 IDCODE is 0x0E681013.
2.3.2 CLBYPASS
This is the IEEE standard BYPASS data register; it is one bit in size.
2.3.3 CLTAPC_SELECT
This data register contains bits that control the presence of the children TAPs in the
SoC on the JTAG chain.
Table 5. CLTAPC_SELECT
When bits 1:0 are set to the value 01 by Debug Software, the CPU Core TAP is added
to the JTAG chain immediately after the CLTAPC.
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