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Intel Quark D2000 Design Manual

Intel® Quark™ Microcontroller D2000
Platform Design Guide
November 2016
Document Number: 333580-002EN
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Contents
1.0 Introduction ................................................................................................................................................. 7
1.1 Overview ................................................................................................................................................................ 7
1.2 Audience and Purpose .................................................................................................................................... 7
1.3 Terminology ......................................................................................................................................................... 8
1.4 Reference Documents ..................................................................................................................................... 8
2.0 System Assumptions ................................................................................................................................. 9
2.1 General Assumptions ....................................................................................................................................... 9
2.1.1 PCB Technology and Stackup ................................................................................................ 11
2.1.2 PCB Technology Considerations .......................................................................................... 11
2.2 Backward and Forward Coupling Coefficient Calculation ............................................................ 14
2.3 Feature Set ........................................................................................................................................................ 15
2.4 CRB Pin Mapping ............................................................................................................................................ 17
3.0 Subsystem Details ....................................................................................................................................18
3.1 Design Recommendations .......................................................................................................................... 18
3.2 General Design Guideline Assumptions ............................................................................................... 19
4.0 I²C Interface ...............................................................................................................................................20
4.1 I²C Interface Signals ...................................................................................................................................... 20
4.2 Interface Routing Guidelines ..................................................................................................................... 21
4.2.1 General Design Considerations ............................................................................................. 22
5.0 Pulse Width Modulation (PWM) ............................................................................................................23
5.1 PWM Signaling ................................................................................................................................................. 24
5.2 Functional Operation .................................................................................................................................... 24
6.0 UART ...........................................................................................................................................................26
6.1 Signal Descriptions ........................................................................................................................................ 27
6.2 Features .............................................................................................................................................................. 28
7.0 SPI ................................................................................................................................................................30
7.1 Features .............................................................................................................................................................. 31
8.0 Clocking ......................................................................................................................................................33
8.1 Features .............................................................................................................................................................. 34
9.0 General Purpose I/O (GPIO) ...................................................................................................................35
9.1 Signal Descriptions ........................................................................................................................................ 35
9.2 Features .............................................................................................................................................................. 36
10.0 JTAG ............................................................................................................................................................38
11.0 Analog-to-Digital Converter (ADC) .......................................................................................................39
Intel® Quark™ Microcontroller D2000 November 2016 Platform Design Guide Document Number: 333580-002EN 3
11.1 Features .............................................................................................................................................................. 39
12.0 Power Delivery ..........................................................................................................................................41
12.1 DVDD Linear Regulator ................................................................................................................................ 41
12.1.1 Operation of an Active Pull – Down Circuit ...................................................................... 41
12.1.2 Implementation of an Active Pull – Down Circuit .......................................................... 41
Figures
Figure 1. Block Diagram ..................................................................................................................................................... 9
Figure 2. PCB Floor Plan ................................................................................................................................................. 10
Figure 3. System Diagram .............................................................................................................................................. 11
Figure 4. Single-Ended Microstrip Diagram ........................................................................................................... 12
Figure 5. Differential Microstrip Diagram ................................................................................................................ 13
Figure 6. Backward Coupling Coefficient ................................................................................................................ 14
Figure 7. Forward Coupling Coefficient ................................................................................................................... 14
Figure 8. Single-Ended Kb Diagram........................................................................................................................... 15
Figure 9. Differential Kb Diagram ............................................................................................................................... 15
Figure 10. CRB Pin Mapping Diagram .......................................................................................................................... 17
Figure 11. I²C Interface....................................................................................................................................................... 20
Figure 12. I²C Point-to-Point Topology ...................................................................................................................... 21
Figure 13. PWM ..................................................................................................................................................................... 23
Figure 14. Duty Cycle of 20% .......................................................................................................................................... 24
Figure 15. Duty Cycle of 50% .......................................................................................................................................... 24
Figure 16. Duty Cycle of 80% .......................................................................................................................................... 24
Figure 17. UART .................................................................................................................................................................... 26
Figure 18. UART 2-Via Point-to-Point Topology .................................................................................................... 27
Figure 19. SPIO ...................................................................................................................................................................... 30
Figure 20. SPI Point-to-Point Single-Ended Topology ........................................................................................ 31
Figure 21. RTC ........................................................................................................................................................................ 33
Figure 22. RTC Topology ................................................................................................................................................... 34
Figure 23. GPIO ..................................................................................................................................................................... 35
Figure 24. GPIO Pin Routing Topology ....................................................................................................................... 36
Figure 25. JTAG Connectivity .......................................................................................................................................... 38
Figure 26. Analog Shielding Requirements .............................................................................................................. 39
Figure 27. Active Pull – Down circuit implementation ......................................................................................... 41
Tables
Table 1. Terminology ......................................................................................................................................................... 8
Table 2. Reference Documents ..................................................................................................................................... 8
Table 3. Stackup Details ................................................................................................................................................ 13
Table 4. Good Layout Practices ................................................................................................................................. 19
Table 5. I²C Point-to-Point Platform Routing Guidelines ............................................................................... 21
Table 6. PWM Timing ...................................................................................................................................................... 25
Table 7. Timer Period ..................................................................................................................................................... 25
Table 8. UART Signals .................................................................................................................................................... 27
Table 9. UART Point-to-Point Topology Platform Routing Guidelines .................................................... 28
Table 10. UART Point-to-Point Topology Platform Routing Guidelines .................................................... 28
Table 11. SPI Platform Routing Guidelines ............................................................................................................. 31
Table 12. RTC Signals........................................................................................................................................................ 34
Table 13. GPIO Pin Routing Guidelines ..................................................................................................................... 36
Table 14. Generic Routing Requirements................................................................................................................. 38
Table 15. Active Pull – Down circuit BOM ................................................................................................................ 42
Intel® Quark™ Microcontroller D2000 November 2016 Platform Design Guide Document Number: 333580-002EN 5
Revision History
Date
Revision
Description
November 2016
002
Memory specification updated. Power Delivery chapter added.
December 2015
001
Initial release.
§
Introduction
1.0 Introduction
1.1 Overview
This design guide provides motherboard implementation recommendations for the Intel® Quark™ Microcontroller D2000 platform, based on the Intel® Quark™ Microcontroller D2000 processor. This document includes design guidelines for Intel® Quark™ Microcontroller D2000 platforms and the hardware integration aspects that must be considered when designing a platform.
This design guide has been developed to ensure maximum flexibility for board designers while reducing the risk of board-related issues. Design recommendations are based on Intel's simulations and lab experience and are strongly recommended, if not necessary, to meet the timing and signal quality specifications. Design recommendations are based on the reference platforms designed by Intel. They should be used as an example but may not be applicable to particular designs.
Note: The guidelines recommended in this document are based on experience, simulation,
and preliminary validation work done at Intel while developing the Intel® Quark™ Microcontroller D2000 processor-based platform. This work is ongoing, and these recommendations are subject to change.
Caution: If the guidelines listed in this document are not followed, it is very important that
designers perform thorough signal integrity and timing simulations. Even when following these guidelines, Intel recommends the critical signals to be simulated to ensure proper signal integrity and flight time. Any deviation from the guidelines should be simulated.
Metric units are used in some sections in addition to the standard use of U.S. customary system of units (USCS). If there is a discrepancy between the metric and USCS units, assume the USCS unit is most accurate. The conversion factor used is 1 inch (1000 mils) = 25.4 mm.
1.2 Audience and Purpose
The Intel® Quark™ Microcontroller D2000 is a highly integrated, ultra-low-power part designed to enable innovative wearable solutions with long battery life for fitness/health/wellness monitors, smart watches, and so on.
This document is intended to aid platform hardware designers in system implementation and reference design reuse by:
Documenting the hardware implementation of a specific form factor wearable
based on the Intel® Quark™ Microcontroller D2000 platform
Intel® Quark™ Microcontroller D2000 November 2016 Platform Design Guide Document Number: 333580-002EN 7
Providing details such as block diagrams, which illustrate connectivity, system level
Term
Description
ADC
Analog-to-Digital Converter
CRB
Customer Reference Board
GPIO
General Purpose Input/Output
I²C
Inter-Integrated Circuit
I2S
Inter-IC Sound
JTAG
Joint Test Action Group
OSC
Oscillator
PWM
Pulse Width Modulation
RTC
Real-Time Clock
SIO
Serial I/O
SoC
System on Chip
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver Transmitter
XTAL
Crystal
Document
Document No.
Intel® Quark™ Microcontroller D2000 Datasheet
333577
considerations, options, and design guidelines
Describing the theory of operation or principles considered in deriving a design
guideline
1.3 Terminology
Table 1. Terminology
Introduction
1.4 Reference Documents
Table 2. Reference Documents
§
System Assumptions
2.0 System Assumptions
2.1 General Assumptions
This section covers general Intel® Quark™ Microcontroller D2000 and Intel® Quark™ Microcontroller D2000 Customer Reference Board (CRB) system topology and interface connectivity assumptions. The Intel® Quark™ Microcontroller D2000 CRB is used as a baseline reference example for guidelines.
Figure 1. Block Diagram
Intel® Quark™ Microcontroller D2000 November 2016 Platform Design Guide Document Number: 333580-002EN 9
Figure 2. PCB Floor Plan
System Assumptions
System Assumptions
Figure 3. System Diagram
2.1.1 PCB Technology and Stackup
The system uses the PCB technology of a standard interconnect, Type 3, 4-layer board, no blind or buried vias. It is important to note that variations in the stackup of a motherboard, such as changes in the dielectric height, trace widths, and spacing, can impact the impedance, loss, and jitter characteristics of all the interfaces. Such changes may be intentional, or may be the result of variations in the manufacturing process. In either case, they must be properly considered when designing interconnects. This design guide applies the CRB PCB stackup and trace width/spacing that is shown in
Figure 4.
Note: All the routing guidelines in this document are simulated based on the CRB stackup.
2.1.2 PCB Technology Considerations
The typical values, including the design and material tolerances, are centered on a nominal single line impedance specification of 50𝛺 ± 15% for microstrip. Many interfaces specify a different nominal single-ended impedance. For more details on the
Intel® Quark™ Microcontroller D2000 November 2016 Platform Design Guide Document Number: 333580-002EN 11
System Assumptions
nominal trace width to meet those impedance targets, refer to the individual interface section.
The following general stackup recommendations should be followed:
Microstrip layers are assumed to be built from 1/2oz. foil, plated up nominally
another 1 oz.; however, the trace thickness range defined allows for significant process variance around this nominal.
Based on the Intel® Quark™ Microcontroller D2000 layout layers, 3/4 dual stripline
is assumed to be built from 1 oz. copper.
All high-speed signals should reference solid planes over the length of their routing
and should not cross plane splits. Ground referencing is preferred.
Reference plane stitching vias must be used in conjunction with high-speed signal
layer transitions that include a reference plane change. Refer to each signal group section for more specification.
The parameter values for internal and external traces are the final thickness and
width after the motherboard materials are laminated, conductors plated, and etched. Intel uses these exact values to generate the associated electrical models for simulation.
Figure 4. Single-Ended Microstrip Diagram
OPCM Stack-Up Information
Layer
Cu Weight
Proposed Thickness (mils)
Structure
Ref
Single End
Differential
50 Ohm ± 10%
90 Ohm ± 10%
Target LW
Finished LW
Target LW/SP
Finished LW/SP
Soldermask
0.50
L1
Top
Hoz+Plating
1.80 L2 3.94 4.2/8
Prepreg
2.70
1080
L2
GND
1oz
1.20
Core 50
50mil core
L3
GND
1oz
1.20 Prepreg
2.70
1080
L4
Bottom
Hoz+Plating
1.80 L3 3.94 4.2/8
Soldermask
0.50
Finished Thickness (mils)
62.40
System Assumptions
Figure 5. Differential Microstrip Diagram
Table 3. Stackup Details
Intel® Quark™ Microcontroller D2000 November 2016 Platform Design Guide Document Number: 333580-002EN 13
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