Intel IQ80960RM, IQ80960RN User Manual

IQ80960RM/RN Evaluation Platform

Board Ma nu al

September 1998

Order Number: 273160-003

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The IQ80960RM/RN may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

IQ80960RM/RN Evaluation P lat form Board Manual

Figures

1-1 IQ80960RM/IQ80960RN Platform Functional Block Diagram...................................................1-1

1-2 IQ80960RN Platform Physical Diagram....................................................................................1-2

3-1 LED Register Bitmap.................................................................................................................3-8

4-1 i960

4-2 IQ80960RM/RN Platform Memory Map.................................. ..... .. ..... .. ..... ..... .. ..... .. ..... .. ..... ..... .4-2

4-3 i960 4-4 i960

4-5 Application Accelerator Uni t.......................................................................................................4-7

®

RM/RN I/O Processor Block Diagram..............................................................................4-1

®

RM/RN I/O Processor Interrupt Controller Connections..................................................4-4

®

RM/RN I/O Processor DMA Controller ............................................................................4-6

Tables

1-1 Document Information...............................................................................................................1-9

1-2 Cyclone Contacts. ......................................................................................................................1-9

3-1 IQ80960RN Platform Power Requirements...............................................................................3-1

3-2 IQ80960RM Platform Power Requirements .............................................. ..... .. ..... ....... .. ..... ......3-1

3-3 SDRAM Performance................................................................................................................3-2

3-4 SDRAM Configurations..............................................................................................................3-3

3-5 UART Register Addresses.........................................................................................................3-4

3-6 Secondary PCI Bus Interrupt and IDSEL Routing .....................................................................3-5

3-7 Logic Analyzer Header Definitions.............................................................................................3-6

3-8 JTAG Header Pinout..................................................................................................................3-7

3-9 Switch S1 Settings.....................................................................................................................3-7

3-10 Start-up LEDs MON960.............................................................................................................3-8

3-11 IQ80960RM/RN Connectors and LEDs....................................... .. ..... .. ..... ..... .. ....... ..... .. ..... ..... .3-9

5-1 Initialization Modes .............................................. ............ ............ ......... ............ ....... ..................5-3

A-1 IQ80960RN Bill of Materials .....................................................................................................A-1

A-2 IQ80960RM Bill of Materials.................................................................................... ....... ..........A-5

B-1 IQ80960RN Schematics List. ....................................................................................................B-1

B-2 IQ80960RM Schematics List ....................................................................................................B-2

IQ80960RM/RN Evaluation Platform Board Manual v

Introduction

This manual describes the IQ80960RM and IQ80960RN evaluation platforms for Intel’s i960® RM/RN I/O processor. The i960 RM/RN I/O processors combine an 80960JT c ore with two PCI bus interfaces , as well as a m emory controller, DMA ch an nels, an in terrup t contro ller interf ace, and an I 64-bit primary PCI and s econdary P CI buse s while the 80960 RM uti lizes bot h a 32 -bit prim ary and secondary PCI bus . The IQ8096 0RM a nd IQ80960RN pl at forms are full-l ength PCI adapte r boards

and are 8.9” in height to accommodate four standard PCI connectors on the secondary PCI bus. The boards can be installed in any PCI host system tha t complies with the PCI Local Bus Specification Revision 2.1. PCI devices can be connected to the secondary bus to build powerful intelligent I/O subsystems.

Figure 1-1. IQ80960RM/IQ80960RN Platform Function al Block Diagram

2

C serial bus. The difference between the two processors is that the 80960RN utilizes

Secondary PCI Slot 4

Secon dary PCI Slot 3

Secondary PCI Slot 2

1

Battery

Backup

Support

Secondary PCI Slot 1

SDRAM (x72)

Logic Analyzer Interface

i960® RM/RN I/O Processor

Primary PCI Bus 32/64-bits

Secondar y PC I

Bus 32/64-bits

ROM Bus

Flash ROM

Logic Analyzer Interface

Console

Port

RS-232

Serial Port

UART

User LED

LED

Register

IQ80960RM/RN Evaluation Board Ma nual 1-1

Introduction

Figure 1-2. IQ80960RN Platform Physical Diagram

64-Bit Secondary PCI Slo ts

J4

J3

J2

J1

J5

J8 J9 J10 J11 J12

U9

Logic Analyzer Connec tors

i960

U15

168-Pin SDRAM DIMM Socket

RS-232 Serial Port

Flash Memory

SW1

1 2 3 4

OFF

J6

U11

®

64-Bit PCI

CR1 CR2

CR3 CR4 CR5

JTAG Port

NiCd Batteries

J7

1-2 IQ80960RM/RN Evaluation Board Man ual

Introduction

1.1 i960® RM/RN I/O Processor and IQ80960RM/RN Features

The i960 RM/RN I/O processor serv es as the mai n component of a high performance, PCI-based intelligent I/O subsystem. The IQ80960RM and IQ80960RN platforms allow the developer to connect PCI devices to the i960 RM/RN I/O processors usi ng the four secondary PCI expa nsi on connectors. The features of the IQ80960RM and IQ80960RN platforms are enumerated below and shown in Figure 1-1 and Figure 1-2.

• i960 RM/RN I/O processor

• Modified PCI long-card form factor

• 64-bit or 32-bit primary PCI bus interface (80960RM 32-bit only)

• 64-bit or 32-bit secondary PCI bus connected to the primary PCI interface with a PCI-to-PCI

bridge (80960RM 32-bit only)

• DMA channels on both PCI buses

2

• I

C Serial Bus

• 168-pin, 3.3V DIMM socket supporting 16 to 128 Mbytes of Synchronous DRAM organized

x72 to support Error Correction Code (ECC) and clocke d at 66 MHz (ships with 16 M/ECC installed)

• Serial console port based on 16C550 UART

• Eight user-programmable LEDs

• 3 Indicator LEDs: proces sor has passed self- test, 3.3 V is supplied to SDRAM, and 3.3 V is

supplied to sec ondary PCI slots

• Flash ROM, 2 Mbytes

• Logic analyzer connectors for SDRAM bus, ROM bus and secondary P CI arbitration signals

• Fan heatsink monitor circuit

• Battery backup for SDRAM

• JTAG header

1.2 Software Development Tools

A number of software development tools are available for the i960® processor family1. This

manual provides information on two software development toolsets: Wind River System’s IxWorks* and Intel’s CTOOLS. If you are using other software development tools, read through the infor mation in this ch apter and in Chapter 2 to gain a general understanding of how to use your tools with this board.

1. To view the electronic tools catalog, access http://developer.intel.com/design/develop.htm/ from the web.

IQ80960RM/RN Evaluation Board Ma nual 1-3

Introduction

1.3 IxWorks Software Development Toolset

IxWorks is a comple te toolset feat uring an integrated development environme nt including a compiler, assembler, linker, and debugger. It also features a real-time operating system.

1.3.1 IxWorks Real-Time Operating System

The IQ80960RM/RN platforms are equipped with Wind River Systems, Inc.’s IxWorks. IxWorks provides for the elements of the I protocols, and executive modules for configuration and control. IxWorks also allows for the writing of basic device drivers and provides NOS-to-driver independence. TORNADO for I provides a visua l environment for building, testing and debugg ing of I

1.3.2 TORNADO Build Tools

TORNADO for I2O includes a coll ection of supporting tools that provide a complete development tool chain. These include the compiler, assembler, linker and binary utilities. Also provided is an

I

O module builder, which creates I2O-loadable modules .

2

O standard: an event-driven driver framework, host message

2

O drivers.

2

O

2

1.3.3 TORNADO Test and Debug T ools

TORNADO for I2O test and debug tools include the dynamic loader, the CrossWind∗ debugger, the WindSh* interactive shell, and a system browser.

The dynamic loader allows for interactive loading, testing, and replac ement of individual object modules that c omprise a driver.

CrossWind is an extended version of GDB960. Using it you can debug I breakpoints on desired I locals, stack frame, memory and so on.

WindSh allows you to communicate to the IQ80960RM/RN platform via an RS-232 serial port. The IQ80960RM/RN pla tform supports port speeds from 300 to 115,200 bps. The shell can be used to:

• control and monitor I

• format, send and receive driver messages

• examine hardware registers

• run automated I

The shell also provides essential debugging capabilities; including breakpoints, single stepping, stack checking, and disassembly.

O components. A variety of windows display source code, registers,

2

O drivers

2

O test suites

2

O drivers by setting

2

1-4 IQ80960RM/RN Evaluation Board Man ual

1.4 CTOOLS Software Development Toolset

Inte l’s i96 0 p rocessor software development toolset, CTOOLS, features ad vanced C/C++ - language compilers for the i960 processor family. CTOOLS development toolse t is available for Windows* 95/NT-based systems and a variety of UNIX workstation hosts. These products provide execution profiling and instruction scheduling optimizations and include an assembler, a linker, and utilities designed for embedded processor software development.

1.4.1 CTOOLS and the MON960 Debug Monitor

In place of IxWorks, the IQ80960RM/RN platform can be equipped with Intel’s MON960, an on-board software monitor that allows you to execute and debug programs written for i960 processors in a non-I step, memory display, and other useful functions for running and debugging a program.

The IQ80960RM/RN platform works with the source-level debuggers provided with CT OOLS, including GDB960 (command line version) and GDB960V (GUI version).

1.4.1.1 MON960 Host Communications

MON960 allows you to communicate and download programs developed for the IQ80960RM/RN platform across a host system’s serial port or PCI interface. The IQ80960RM/RN platform supports two methods of communication: terminal emulation and Host Debugger Interface (HDI).

2

O environment. The monitor provides program download, breakpoint, single

Introduction

1.4.1.2 Terminal Emulation Method

Terminal emulation software on your host system can communicate to MON960 on the IQ80960RM/RN platform via an RS-232 serial port. The IQ80960RM/RN platform supports port speeds from 300 to 115,200 bps. Serial downloads to MON960 require that the terminal emulation software support th e XMODEM proto col.

Configure the serial port on the host system for 300-115,200 baud, 8 bits, one stop bit, no parity with XON/XOFF flow control.

1.4.1.3 Host Debugger Interface (HDI) Method

You may use a source-l eve l debugger, such as Intel’s GDB960 and GDB960V to estab lish serial or PCI communications with the IQ80960RM/RN platform. The MON960 Host Debugger Interface (HDI) provides a defined mess aging layer between MON960 and the debugger. For more information on this interface, see the MON960 Debug Monitor User’s Manual (484290).

HDI connection requests cannot be detected by MON960 if the user has already initiated a connection using a terminal emulator. In this case, the IQ80960RM/RN platform must be reset before the debugger can conne ct to MON960.

IQ80960RM/RN Evaluation Board Ma nual 1-5

Introduction

1.5 About This Manual

A brief description of the contents of this manu al follows.

Chapter 1, “Introduction”

Chapter 2, “Getting Started”

Chapter3, “Hardware Refere nce”

Chapter 4, “i960® RM/RN I/O Processor Overview”

Chapter 5, “MON960 Support for IQ80960RM/RN”

Appendix A, “Bill of Materials”

Appendix B, “Schematics”

Appendix C, “PLD Code” Appendix D, “Recycling the

Battery”

Introduces the IQ80960RM chapter also describes Intel’s C TOOLS* and WindRiver Systems IxWorks* software development tools, and defines notational-conventions and related documentation.

Provid es st ep-b y-s te p i ns tru ct ions fo r in st al li ng t he IQ8 0960 R M or I Q80 96 0RN platform in a host system and downloading and executing an application program. This chapter also describes Intel’s software development tools, the MON960 Debug Monitor, IxWORKS, software installation, and hardware configuration.

Descri bes the locations of connectors, switche s and LEDs on the IQ80960RM and IQ80960RN platforms. Header pinouts and register descriptions are also provided in this chapter.

Presents an overview of the capabilities of the i960 RM/RN I/O pro c essor and inclu des the CPU memory map.

Describes a number of features added to MON960 to support application development on the i960 RM/RN I/O processor.

Shows complete parts list IQ80960RM and IQ80960RN Evaluation Platforms. Complete set of schematics for the IQ80960RM and IQ80960RN Evaluati on

Platforms. Example PLD code used on IQ80960RM and IQ80960RN evaluation boards

for SDR AM battery backup. Information on the RBRC program and the locations of participating recycling

centers.

and IQ80960RN Evaluation Board features. This

1-6 IQ80960RM/RN Evaluation Board Man ual

1.6 Notational-Conventions

The following notation conventions are consistent with other i960 RM/RN I/O processor documentation and general industry standards.

Introduction

# or overbar

Bold Indicates user entry and/or commands .

Italics Indicates a ref erence to related documents; also used to show emphasis. Courier font Indicates code examples and file directories and names. Asterisks (*) On non-Intel company an d pr oduct names, a trailing asterisk indicates

UPPERCASE In text, signal name s are shown in upperc ase. When seve ral signal s share

Designations for hexadecima l and binary numbers

In code examples the pound symbol (#) is appended to a signal name to indi cate that t h e signal is active. Normall y in v erted clock signals are indicate d with an overbar above the signal name (e.g., RAS).

PLD sig n a l names ar e in bo l d lo w ercase letters (e. g ., h_off, h_on).

the item is a trademark or re g istere d tr ademar k . Such brand s and names are the pr o perty of th eir respective o w ne r s .

a common name, each signa l is represented by the signa l name followed by a number; the group is represented by the signal name followed by a variable (n). In cod e ex amples, si gn al names ar e sh o w n in th e cas e required by the software development tool in use.

In text, instead of using subscripted “base” designators (e.g., FF leading “0x” (e.g., 0xFF) hexadecimal numbers are represented by a string of hex digi ts followed by the lette r H. A zero prefix is added to numbers that begin with A through F. (e.g., FF is shown as 0FFH.) In examples of actual code, “0x” is used. Decimal and binary numbers are represented by their customary nota tions. (e.g., 255 is a decimal number and 1111 1111 is a binary num ber. In some cases, the letter B is added to binary numbers for clari ty.)

16

) or

IQ80960RM/RN Evaluation Board Ma nual 1-7

Introduction

1.7 Techn ical Suppo rt

Up-to-date produc t and technical info rma tion is available el ectronically from:

• Intel’s World-Wide Web (WWW) Location: http://www.intel.com

• IQ80960RM and IQ80960RN Product Information: http://developer.intel.com/design/i960

For techn i cal assist an c e, electroni c mai l (e- mail) prov id e s th e f ast est route to re ac h en g i ne er s specializing in IQ80960RM and IQ80960RN issues. Posting messages on the Embedded Microprocessor Forum at http://support.intle.com/newsgroups/ is also a direct route for IQ80960RM and IQ80960RN technical assistance. See Section 1.7.2.

Within the United States and Canada you may contact the Intel Technical Support Hotline. See

Section 1.7.1 for a list of customer support sources for the US and oth er ge ographical areas.

1.7.1 Intel Customer Electronic Mail Support

For direct support from engine ers spec iali ng in i960® Microprocessor issues s end e-mail in english to 960tools@intel.com.

Questions and other messages may be posted to the Embedded Microprocessor Forum at http://support.intel.com/newsgroups/.

1.7.2 Intel Customer Support Contacts

Contact Intel Corporation for technical assistance for the IQ80960RM/RN evaluation platform.

Country Literatu re Customer Support Numbe r

United S tates 800-548-4725 800-628-8686 Canada 800-468-8118 or 303-297-7763 800-628-8686 Europe Contact local distributor Contact local distributor Austral ia Contact local distributor Contac t local distributor Israel Contact local d istributor Contact local distributor Japan Contact local distribu tor Contac t local distributor

1-8 IQ80960RM/RN Evaluation Board Man ual

1.7.3 Related In fo rmat io n

T o orde r printe d manua ls fro m Intel, c ontac t your loc al sales re prese ntati ve or Intel L iteratur e Sal es (1-800-548-4725 ).

Table 1-1. Document Information

Product Document Name Compan y/ Order #

All

80960RM/RN

Developers’ Insight CD-ROM i

960®

RM/RN I/O Processor Developer’s Ma nual 80960RM I/O Processor 80960RN I/O Processor MON960 Debug Monitor User’s Guide

PCI Local Bus Specification

Writing I2O Device Drivers in IxWorks

IxWorks Reference Manual

VxWorks Programmer’s Guide

Tornado User’ s Guide

Tornado for I2O

Tornado for I2O Compact Disk

Intel # 273000 Intel # 273158

Data Sheet Intel # 273156

Data Sheet Intel # 273157

Intel #484290

Revisio n2.1

Rev. 1.0 #TDK-12380-ZC-00

PCI Special Interest Group 1-800-433-5177

Wind River Systems, Inc. #DOC-1173-8D-02

Wind River Systems, Inc. #DOC-1173-8D-03

Wind River Systems, Inc. #DOC-11045-ZD-01

Wind River Systems, Inc. #DOC-1116-8D-01

Wind River Systems, Inc. #DOC-12381-8D-00

Introduction

Contact Cyclo ne Microsystems for additional information about their products and literature:

Table 1-2. Cyclone Contacts

Phone: 203-786-5536

Cyclone Microsystems

25 Science Park

New Haven CT 06511

IQ80960RM/RN Evaluation Board Ma nual 1-9

F AX: 203-786-5025 e-mail: info@cyclone.com

WWW: http://www.cyclone.com

Getting Started

This chapter c ontains in st ructio ns for ins tall ing the IQ80960RM/ RN pla tform in a host sys tem and, how to download and execute an application program using Wi nd River System’ s IxWorks∗ or

Intel’s CTOOLS software development tools ets.

2.1 Pre-Installation Considerations

This section pr ovides a general overview of the components required to develop and execute a program on the IQ80960RM/RN platform. IQ80960RM/RN eva luation boards support two software development toolsets, Wind River System’s IxWorks and Intel’s CTOOLS.

IxWorks is a complete toolset featuring an integrated development environment including a compiler, assembler, linker, and debugger. It also features a real-time operating system. If you are using the IxWorks opera ting system with the TORNADO* dev elopment environment, refer to the Wind River Systems, Inc. documentation referenced in Section 1.7.3.

CTOOLS is a complete C/C++-language software-development toolset for developing embedded applications to run on i960 processors. It contains a C/C++ compiler, the gcc960 and ic960 compiler driver programs, an assembler, runtime libraries, a collection of software-development tools and utilities, and printed and on-line documentation. The MON960 Debug Monitor User’s Guide fully

describes the components of MON960, including MON960 commands, the Host Debugger Interface Library (HDIL), and the MONDB.EXE utility. If you are using MON960 and the CTOOLS toolset, refer to section Section 2.2.1, “Installing Software Development T ools” on page 2-1.

2

See Chapter 1 for more information on the IxWorks and CTOOLS features. The IQ80960RM/RN evaluation boards are supplied with IxWorks intel ligent real-tim e ope rating

system pre-lo ade d into the on-board Flash. You also have the option of installing the MON960 debug monitor, which is required if you are using the CTOOLS deb ugging tools, GDB960, GDB960V, or MONDB. Section3.3.1 des cribe s the Flash ROM pro gramming utilit y, which allows you to load MON960 onto the platform or re-load IxWorks.

2.2 Software Installation

2.2.1 Installing Software Development Tools

If you haven’t done so already, install your development softwar e as described in its manuals. All references in this manual to CTOOLS or CrossWind assume that the default directories were selected during installat ion. If this is not the case , substitute th e appropriate path for the default path wherever file locations are referenced in this manual.

IQ80960RM/RN Evaluation Board Ma nual 2-1

Getting Started

2.3 Hardware Installation

Follow these in st ructions to get your new IQ80960RM/RN platform running. Be sure all items on the checklist were provided with your IQ80960RM/RN.

Warning: Static charges can severely damage the IQ80960 RM/RN platforms. Be sure you are prop erly

grounded before re moving the IQ80960RM/RN platform from the anti-stati c bag.

2.3.1 Battery Bac ku p

Battery backup is provided to save any information in SDRAM during a power failure. The IQ80960RM/RN platform contains four AA NiCd batter ies, a charging circuit and a regulator circuit. The batteries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr.

SDRAM technology provides a simple way of enabling data preservation through the self-refresh command. When the processor receives an active Primary PCI reset it issues the self-refresh command and drive s the SCKE signals low. Upon seeing this condition, a P A L on the IQ80960RM/RN platform holds SCKE low before the process or los es power. The batteries maintain power to the SDRAM and the PAL to ensure self-refresh mode. When the PAL detects PRST# returning to ina ctive state, the PAL releases the hold on SCKE.

The battery circuit can be disabled by removing the batteries. LED CR4 indicates when the SDRAMs have sufficient power. If the batteries remain in the evaluation platform when it is depowered and/or removed from the chassis, the batteries will maintain the SDRAM for approximately 30 hours. Once power is again applied, the batteries will be fully charged in about 4 hours.

2.3.2 Installing the IQ80960RM/RN Platforms in the Host System

If you are installing the IQ80960RM/RN pla tform for the first time, vis ually inspect the board for any damage that may have occurred during shipment. If there are visible defect s , return the board

for repl acement. Follow the host system manufa cturer’s instructions for inst alling a PCI adapter. The IQ80960RM/RN pl atform is a full-leng th P CI adapter and requires a PCI s lot that is free from obstructions. The IQ80960RM/RN platform is taller than specified in the PCI Local Bus Specification Revision 2.1. The extended height of the board will require you to keep the cover off of your PC. Refer to Chapt er 3 for physical dimensions of the boa rd.

2.3.3 Verify IQ80960RM/RN Platform is Functional

These instruct ions ass ume that you have alrea dy install ed the IQ8 0960RM/RN pla tfo rm in the host system as described in Section 2.3.2 .

1. To connect the serial port for communicating with and downloading to the IQ80960RM/RN platform, connect the RS-232 cable (provided with the IQ80960RM/RN) from a free serial port on the host system to the phone jack-style connector on the IQ80960RM/RN platform.

2. Upon power-up, the red FAIL LED turns off, indicating that the processor has passed its self-test.

3. If you have IxWorks installed in the flash ROM, the user L EDs displ ay the bina ry pat tern 99H. In the IxWorks deve lopment environment, raw serial input/output is not used. Instead, the Wind DeBug (WDB) protocol is run over the serial port, to allow communica tion with Tornado developm ent tools. If the terminal emulation package is run ning at 115, 200 baud, the letters “WDB_READY” display prior to launching in the WDB serial proto col.

2-2 IQ80960RM/RN Evaluation Board Man ual

4. If you have MON960 installed in th e flash ROM, pre ss <ENTER> on a term inal connected to

the IQ80960RM/RN platform to bring up the MON960 prompt. MON960 automatically adjusts its baud rate to match that of the termi nal at start-up. At baud rates other than 9600, it may be necessary to press <ENTER> several times.

2.4 Creating and Downloading Executable Files

To download code to the IQ80960RM/RN platform running IxWorks, consult Wind Riv er documentation on the supplied TORNADO for I IQ80960RM/RN platform, your compiler produces an ELF-format object file.

To download code to the IQ80960RM/RN platform running CTOOLS, consult the CTOOLS documentation for information regarding compiling, linking, and downloading applications. During a download, MON960 checks the link address sto r ed in the ELF file, and stores the file at that locati on on the IQ80960RM/RN platform. If the executable file is linke d to an invalid addres s on the IQ80960RM/RN platform, MON960 aborts the downloa d.

2.4.1 Sample Download and Execution Using GDB960

This example shows you how to us e GBD960 to download and execute a file named myapp via the serial port.

O CD-ROM. To downl oad code to the

2

Getting Started

• Invoke GDB960. From a Windows 95/NT command prompt, issue the command:

gdb960 -r com2 myapp This command establishes communication and downloads the fil e myapp.

• To execute the program, enter the command from the GDB960 command prompt:

(gdb960) run

More information on the GDB960 commands mentioned in this section can be found in the GDB960 User’s Manual.

IQ80960RM/RN Evaluation Board Ma nual 2-3

Hardware Reference

3.1 Power Requirements

The IQ80960RM/RN platform draws power from the PCI bus. The power requirements of th e IQ80960RM/RN platforms are shown in Table 3-1 and Table 3-2. The numbers do not include th e power required by a PCI card(s) mounted on one or more of the IQ80960RM/RN platforms’ four

expansion slot s.

Table 3-1. IQ80960RN Platform Power Requirements

Voltage Typical Current Maximum Current

+3.3 V 0 V* 0 V*

+5 V 1.45 A 1.96 A

+12 V 286 mA 485 mA

-12 V 1 mA 1 mA

NOTE: Does not include the power required by a PCI card(s) mounted on the IQ80960RN platform.

* +3.3V for 80960RN Processor created on board from +5V.

Table 3-2. IQ80960RM Platform Power Requirements

3

NOTE: Does not include the power required by a PCI car d(s) moun ted on the IQ80960RM platform.

* +3.3V for 80960RM Proc essor created on board from +5V.

3.2 SDRAM

The IQ80960RM/RN platform is equipped with a 168-pin DIMM socket formatted to accept +3.3V synchronous DRAM with or without Error Correction Code (ECC). The socket will accept SDRAM from 8 Mbytes to 128 Mbytes. 128 Mbyte SDRAMs are available in both x64 and x72 configurations. Note that 8 Mbyte SDRAMs are only for x64 or non-ECC memory. The SDRAM is accessible from either of the PCI buses, via the ATUs, and the local bus on the IQ80960RM/RN platform.

Voltage Typical Current Maximum Current

+3.3 V 0 V* 0 V*

+5 V 1.32 A 1.86 A

+12 V 284 mA 485 mA

-12 V 1 mA 1 mA

IQ80960RM/RN Evaluation Board Ma nual 3-1

Hardware Reference

3.2.1 SDRAM Performance

The IQ80960RM/RN pla tform uses 72-bit SDRAM with ECC or 64-bit SDRAM without ECC. SDRAM allows zero data-to-data wait state operation at 66 MHz. The memory controller unit (MCU ) of the i 96 0 of four enables se am less read/write burs ting of long data strea ms, as long as the MCU does not cross the page boundary. Page boundaries are naturally aligned 2 Kbyte blocks. 72-bit SDRAM with ECC allows a maximum throughput of 528 Mbytes per second.

Both 16 Mbit and 64 Mbit SDRAM devic es are supported. The MCU keeps two pages per bank open simult aneous ly for 16 Mbit de vices a nd 4 pages pe r bank fo r 64 Mb it device s. Simulta neous ly open pages allo w for greate r performanc e for seq uential ac cess , distribu te d acros s multipl e inte rnal bus transactions. Table 3-3 shows re ad a nd wr it e exa m p l es of a sin g l e 8 byt e acce s s an d fo r a multiple 40 byte access.

Table 3-3. SDRAM Performance

Read Pag e H it ( 8 by tes) 7 76 Mbyt es / s ec

Read Page Miss (8 bytes) 12 44 Mbytes/sec

Read Page Hit (40 bytes) 11 240 Mbytes/sec

Read Page Miss ( 40 bytes) 16 165 Mbytes/sec

Write Page Hit (8 bytes) 4 132 Mbytes/sec

Write Page Miss (8 bytes) 8 66 Mbytes/sec

Write Page Hit (40 bytes) 8 330 Mbytes/sec

Write Page Miss (40 byte s) 12 220 Mbytes/sec

®

RM/RN I/O processor supports SDRAM burst le ngths of four. A burst length

Cycle Type Table Clocks Performance Bandwidth

Note that if ECC is enabled and you attempt a partial write — less than 64 bits — you will incur a penalty. Because ECC is enabled, the MCU will trans late the write into a read-modify-wri te transaction. Therefore, for a single byte write the clock count will be 11.

3-2 IQ80960RM/RN Evaluation Board Man ual

3.2.2 Upgrading SDRAM

The IQ80960RM/RN is equipped with 16 Mbytes of SDRAM with ECC ins erted in the 168-pin DIMM socket. The memory may be expanded by inserting up to a 128 Mbyte module into the DIMM socket. The various memory combinations are shown in Table 3-4. Only 168-pin +3.3V SDRAM modules with or without ECC rated at 10 ns shoul d be us ed on the IQ80960RM/RN platform. The column labeled ECC dete rmines if that particular memory configuration can be used with ECC.

Table 3-4. SDRAM Configurations

Hardware Reference

SDRAM

Technology

16 Mbit

64 Mbit

SDRAM

Arrangement

2M x 8

1M x 16

8M x 8

4M x 16

# Banks Row Column ECC

1 2 Yes 32 Mbytes 1 2 No 16 Mbytes 1 2 Yes 128 Mbyt es 1 2 No 64 Mbytes

3.3 Flash ROM

An E28F016S5 (2 Mbytes) Flash ROM is included on the IQ80960RM/RN platform. This Flash ROM contains IxWorks* and may be used to store user applications.

3.3.1 Flash ROM Programming

Two types of Flash ROM prog rammi ng exist on the IQ80960RM/RN platform. The first is normal application development programming. This occurs using IxWorks to download new software and the 80960JT core to writ e the new code to the Flash ROM. During this tim e the boot sectors (containing IxWorks) are write protected.

11 9

11 8

12 9

12 8

Total Memory

SIze

Yes 16 Mbytes

No 8 Mbytes

Yes 64 Mbytes

No 32 Mbytes

The second type of Flash ROM programming is loading the boot sectors. You will not be required to load the boot sectors except:

• To load MON960

• To load a new rele ase of IxWorks

• To change between the check build and the free build of IxWorks

The following steps ar e requ ired to program the Flash ROM boot sectors :

1. Set switch S1 #’s 1 and 2 to the on position.

2. Reset the board by cycling power on the worksta tion.

3. Run the Intel DOS-based flash utility to program the Flash ROM boot sect ors.

4. Set switch S1 #’s 1 and 2 to the off position.

5. Reset the board by cycling power on the worksta tion.

IQ80960RM/RN Evaluation Board Ma nual 3-3

Hardware Reference

3.4 Console Serial Port

The console seri al port on the IQ80960RM/RN platform, based on a 16C550 UART, is capable of operation from 300 to 115,200 bps. The port is connected to a phone ja ck-style plug on the IQ80960RM/RN pla tform. The DB25 to RJ-45 cable inc luded with the IQ80960RM/R N can be used to connect the console port to any sta ndard RS-232 port on the host system.

The UART on the IQ80960RM/RN platf orm is clocked with a 1.843 MHz clock, and may be programmed to use th is clo ck with it s inte rnal baud rate coun ters . The UAR T regis ter addr esses are shown in Table 3-5; refer to the 16C550 device data book for a detailed description of the registe rs and device operat ion. Note that some UART addresses refer to di fferent registers depending on whether a read or a write is being per f orm ed.

Table 3-5. UART Register Addresses

Address Read Register Write Register

E000 0000H Receive Holding Register Transmit Hold ing Register E000 0001H Unused Interrupt Enable Register E000 0002H Interrupt Status Register FIFO Control Register E000 0003H Unused Line Control Register E000 0014H Unused Modem Control Regis ter E000 0015H Line Status Register Unused E000 0016H Modem St atus Register Unused E000 0017H Scratch pad Register Scratchpad Register

3.5 Secondary PCI Bus Expansion Connectors

Four PCI Expansion Slots are available on the IQ80960RM/RN platform. The IQ80960RM supports 32-bit PCI expansion and the IQ80960RN supports 64-bit PCI expans ion. The slots are designed for +5V PCI signalling and accommodate PCI cards with +5V or universal sig nalling capabilities.

3.5.1 PCI Slots Power Availability

Power from the Primary PCI bus, +3.3V, +5V, +12V, and –12V, is routed to the Secondary PCI bus expansion s lots. +3.3V is only avai lable at the secondary PCI slots if the host system makes +3.3V available on the Primary PCI slots. LED CR5 indicates if this power is available.

3-4 IQ80960RM/RN Evaluation Board Man ual

3.5.2 Interru pt and IDS E L Rou ti ng

Table 3-6. Secondary PCI Bus Interrupt and IDSEL Routing

Connector IDSEL INTA# INTB# INTC# INTD#

J11 SAD16 SINTA# SINTB# SINTC# SINTD# J12 SAD17 SINTB# SINTC# SINTD# SINTA# J13 SAD18 SINTC# SINTD# SINTA# SINTB# J14 SAD19 SINTD# SINTA# SINTB# SINTC#

3.6 Battery Backup

Battery backu p is provided to save any inform ation in SDRAM during a power fail ure. The IQ80960RM/RN platform contains four AA NiCd batteries, a charging circuit and a regulator circuit. The bat teries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr.

SDRAM technology provides a simple way of enabling data preservation though the self-refresh command. When the processor receives an active Primary PCI reset it will issue the self-refresh command and drive the SCKE signals low. Upon seeing this condition a PAL on the IQ80960RM/RN platfor m will hol d SCKE low before the proce ssor los es power. The batteries will maintain power to the SDRAM and the PAL to ensure self-ref r esh mo de. When the PAL sees PRST# r et urning to in ac t iv e s t at e th e PAL will re lease the hold on SCKE.

Hardware Reference

The battery circuit can be disabled by removi ng the batteries. LE D CR4 indicates when the SDRAMs have suff icient power. If the batteries remain in the evaluation platform when it is depowered and/or removed from the chassis, the batteries will maint ain the SDRAM for approximately 30 hours. Once power is again applied, the batteries will be fully charged in about four hours.

3.7 Loss of Fan Detect

The i960 RM/RN I/O processor can be cooled by an active heat sin k mount ed on top. The fan provides a square wave output that is monitored by a comparator circuit on the IQ80960RM/RN platform. The frequen cy of the fan output is approxi mately 9K RPM. If the frequency falls below approximately 8K RPM the circuit will provide an interrupt to the processor.

Note: The standard production boards will be shipped with attached pass ive heat sinks. In the case of

utilizing a passive heat sink, the proces s or never sees an interrupt from not having a fan.

IQ80960RM/RN Evaluation Board Ma nual 3-5

Hardware Reference

3.8 Logic Analyzer Headers

There are five logic analyzer connectors on the IQ80960RM/RN platform. The connectors are Mictor type, AMP part # 767054-1. Hewlett-Packar d and Tektronix manufacture and sell interfaces to these connectors. The logic analyzer connectors allow for interfacing to the SDRAM and ROM buses along wit h secondary PCI arbitration signals. Table 3-7 shows the connectors and the pin assignments for each.

Table 3-7. Logic Analyzer Header Definitions

PIN J9 J11 J12 J10 J8

3 SDRAMCLK 4 DQ15 SDQM7 DQ31 RAD15 5 DQ14 SDQM6 DQ30 RAD14 6 DQ13 SDQM5 DQ29 RAD13 7 DQ12 SDQM4 DQ28 RAD12 8 DQ11 SDQM3 DQ27 RAD11

9 DQ10 SDQM2 DQ26 RAD10 10 DQ9 SDQM1 DQ25 RAD9 11 DQ8 SDQM0 DQ24 RAD8 12 DQ7 SCB7 DQ23 RAD7 13 DQ6 SCB6 DQ22 RAD6 14 DQ5 SCB5 DQ21 RAD5 15 DQ4 SCB4 DQ20 RAD4 16 DQ3 SCB3 DQ19 SCE0# RAD3 17 DQ2 SCB2 DQ18 SCE1# RAD2 18 DQ1 SCB1 DQ17 SBA1 RAD1 19 DQ0 SCB0 DQ16 SBA0 RAD0 20 DQ32 SA0 DQ48 SREQ0# RAD16 21 DQ33 SA1 DQ49 SREQ1# 22 DQ34 SA2 DQ50 SREQ2# 23 DQ35 SA3 DQ51 SREQ3# RALE 24 DQ36 SA4 DQ52 SREQ4# RCE0# 25 DQ37 SA5 DQ53 SREQ5# RCE1# 26 DQ38 SA6 DQ54 SGNT0# ROE# 27 DQ39 SA7 DQ55 SGNT1# RWE# 28 DQ40 SA8 DQ56 SGNT2# 29 DQ41 SA9 DQ57 SGNT3# I_RST# 30 DQ42 SA10 DQ58 SGNT4# 31 DQ43 SA11 DQ59 SGNT5# 32 DQ44 DQ60 33 DQ45 SWE# DQ61 34 DQ46 SCAS# DQ62 35 DQ47 SRAS# DQ63 36 P_PCICLK RALE

3-6 IQ80960RM/RN Evaluation Board Man ual

3.9 JTAG Header

The JTAG header allows debugging hardware to be quickly and easily connecte d to s ome of the

IQ80960RM/RN processor’s logic signals. The JTAG header is a 16-pin header. A 3M connector (part number 2516-6002UG) is required to

connect to this header. The pinout for the JTAG header is shown in Table 3-8. The header and connector are keyed using a tab on the connector and a slot on the header to ensure proper installation.

Hardware Reference

Each signal in the JTAG header is paired with its own ground connection to avoid the noi se problems associated with long ribbon cables. Signal descriptions are found in the i960

Developer’s Manual, 80960RM I/O Processor Data Sheet and the 80960RN I/O Process or Data Sheet.

Table 3-8. JTAG Header Pinout

Pin Signal Input/Output to 80960RM/RN Pin Signal

1 TRST# IN 2 GND 3 TDI IN 4 GND 5 TDO OUT 6 GND 7TMS IN 8GND

9TCK IN 10GND 11 LCDINIT# IN 12 GND 13 I_RST# OUT 14 GND 15 PWRVLD OUT 16 GND

Table 3-9 describes switch setting options and defaults. These switch settings are sampled at

Primary PCI Reset. See Table 5-1 “Initialization Modes” on page 5-3 for processor initialization

configurations.

Table 3-9. Switch S1 Settings

Position Name Description Default

S1-1 RST_MODE#

S1-2 RETRY

S1-3 32BITMEM_EN#

a

S1-4

a. This switch is active for IQ80960RN ONLY.

32BITPCI_EN#

®

RM/RN I /O Processo r

Determines if the processor is to be held in reset. ON = hold in rest OFF = allows pr ocessor initialization

Deter m ines if the Prim ary PCI interface will be disabled. ON = allows Primar y PCI configurat ion cycles to occur OFF = retries all Primary PCI configuration cycles

Notifies Memory Controller of the SDRAM width. ON = Memory Controller utilizes 32-bit SDRAM access protocol OFF = Memory Contoller utilizes 64-bit SDRAM access p rotocol

Determines whether Secondary PCI bus is a 32- or 64-bit bus. ON = indicates Secondary PCI bus is a 32-bit bus OFF = indicates Secondary PCI bus is a 64-bit bus

OFF

IQ80960RM/RN Evaluation Board Ma nual 3-7

Hardware Reference

3.10 User LEDs

The IQ80 960RM /RN plat form ha s a bank o f eig ht user -prog rammab le LE Ds, loca ted on t he uppe r edge of the adapter board. These LEDs are controlled by a write-only register and used as a debugging aid during development. Software can control the state of the user LEDs by writing to the LED Register, located at E004 0000H. Each of the eight bits of this register correspond to one of the user LEDs. Clearing a bit in the

LED Register by writing a “0” to it turns the corresponding LED “on”, while setting a bit by writing a “1” to it turns the corresponding LED “off”. Resetting the IQ80960RM/RN platform results in clearing the register and turning all the LEDs “on”. The LED Register bitmap is shown in Figure 3-1.

The user LEDs are numbered in de sc ending order from left to righ t, with LED7 being on the left when looking at the component side of the adapter.

Figure 3-1. LED Register Bitmap

76543210

User LED 7 User LED 6 User LED 5 User LED 4 User LED 3 User LED 2 User LED 1 User LED 0

3.10.1 User LEDs During Initialization

MON960 indica tes the progres s of its hardware initializ ation on the user LEDs. In the event tha t initia lization should fail for some r eason, the numbe r of lit LEDs can be used to determine the cause of th e f ai lu r e . Table 3-10 lists the tests that correspond to each lit LED.

Table 3-10. Start-up LEDs MON960

LEDs Tests

LED 0 SDRAM serial EEPROM checksum validated LED 1 UART walking ones test passed LED 2 DRAM walking ones test passed LED 3 DRAM multiword test passed LED 4 Hardware initialization started LED 5 Flash ROM initialized LED 6 PCI-to-PCI Bridge initialized LED 7 UART int ernal loopback t est passed

3-8 IQ80960RM/RN Evaluation Board Man ual

Table 3-11 lists the connec to rs and LEDs.

Table 3-11. IQ80960RM/RN Connectors and LED s

Item Description

J1-J4 Secondary PCI bus expansion con nector

J5 168-pin SDRAM DIMM socket J6 JTAG connector J7 Serial port connector J8 Logic analyzer connector for f lash ROM bus

J10 Logic analyzer connector for Secondary PCI bus arbitrat ion signals

J9, J11, J12 Lo gic analyzer conn ector for a ccess to SDRAM bus

J13 Active heatsink connector for example fan monitor circuit

CR1, CR2 Eight user LEDs

CR3 Self-test fail LED CR4 Battery backup SDRAM, 3.3 V avail able CR5 Indicates host system providing 3.3 V to Secondary PCI bus connectors

S1 DIP switch (Tabl e 3-9)

Hardware Reference

IQ80960RM/RN Evaluation Board Ma nual 3-9

i960® RM/RN I/O Processor Overview

4

This chapter desc ribes the features and opera tion of the processor on the IQ8096 0RM/RN platform. For more detail, refer to the i960

Figure 4-1. i960

®

RM/RN I/O Processor Developer’s Manual.

®

RM/RN I/O Processor Block Diagram

Local Memory

(SDRAM, Flash)

80960 Core

Processor

Memory

Controller

Messaging

Unit

Two DMA Channels

Bus

Interface

Unit

64-bit Internal Bus

Address

Translat ion

Unit

I2C Serial Bus

I2C Bus

Interface

Application Accelerator

One DMA

Channel

Internal

Arbitration

Address

Translation

Unit

PCI to PCI

64-bit/32-bit Primary PCI Bus

Performance

Monitoring

Unit

IQ80960RM/RN Evaluation Board Ma nual 4-1

Bridge

64-bit/32-bit Secondary PCI Bus

Secondary

PCI

Arbitration

i960® RM/RN I/O Processor Overview

4.1 CPU Memory Map

The memory map for the IQ80960RM/RN platform is shown in Figure 4-2. All addresses below 9002 0000H on the IQ80960RM/RN platform are reserved for vari ous functions of the i960 RM/RN I/O proce ssor, a s shown on the memory map. Document ation for t hese are as, as well as t he processor memory m apped registe rs at FF00 000 0H and the IBR , can be found in t he i960 I/O Pro ce ssor Developer’s Manu al.

Figure 4-2. IQ80960RM/RN Platform Memory Map

®

RM/RN

F000 00 00H

E000 0000H

B000 0000H

A000 0000H

9002 0000H

8000 0000H

0000 2000H

0000 1900H

0000 0800H

0000 0400H

0000 0000H

Flash ROM

and

Processor Registers

On-board Devices

Reserved

DRAM

Reserved

ATU Outbo un d

Translation Windows

ATU Outbo un d

Direct Addressing Window

Reserved

Peripheral

Memory Mapped Regi sters

Reserved

Processor Internal Data RAM

Processor

Memory Mapped

Registers

Flash ROM

Reserved

LED Register

(write only)

UART

FF00 0000H

FEE0 0000H

F000 00 00H

E004 0000H E000 0000H

4-2 IQ80960RM/RN Evaluation Board Man ual

4.2 Local Interrupts

The i960 RM/RN I/O processor is built around an 80960JT core, which has seven external interrupt lines designated XINT0# through XINT5# and NMI#. In the i960 RM/RN I/O processor, these interrupt lines are not directly connected to external interrupts, but pass through a layer of internal interrupt routing logic. Figure 4-3 shows the interrupt connections on the i960 RM/RN I/O processor.

XINT0# through XINT3# on the 80960JT core ca n be used to receive PCI interrupts from the secondary PCI bus, or these interrupts can be pa ssed through to the primary PCI interface, depending on the setting of the XINT Select bit of the PCI Interrupt Routing Sel ect Register in the i960 RM/RN I/O processor . On the IQ80 960RM/RN platform, XINT0# through XINT3# are configured to receive interrupts from the secondary PCI bus.

XINT4# and XINT5# on the i960 RM/RN I/O processor may be connected to interrupt sources external to th e process or . On the IQ80960RM/ RN pla tform, XINT4# is conne cted to th e loss of fan detect and XINT5# is conne cted to the 16C550 UART.

XINT6#, XINT7# receive interrupt s from internal sources. NMI# receives interrupts from internal sources an d from an ex ternal source. Since all of these interrupts accept signals from multiple sources, a status regis ter is provided for each of the m to allow s ervice routines to identify the source of th e interrupt. Each of the possible interrupt s ources is assigned a bit position in the status register. The interrupt sources for these lines are shown in Figure 4- 3. On the IQ80960RM/RN platform, the NMI# inter r u pt is not connected to any external interrupt sourc e and receives interrupts only from the internal devices on the i960 RM/RN I/O processor. Note tha t all error conditions result in an NMI# interrupt.

i960® RM/RN I/O Processor Overview

IQ80960RM/RN Evaluation Board Ma nual 4-3

i960® RM/RN I/O Processor Overview

Figure 4-3. i960® RM/RN I/O Processor Interrupt Controller Connections

P_INTB# Output

P_INTC# Output

P_INTD# Output

P_INTA# Output

i960®RN/RM I/O Processor

S_INTA#/XINT0#

S_INTB#/XINT1#

S_INTC#/XINT2#

S_INTD#/XINT3#

XINT4#

(Loss of Fan)

XINT5# (UART)

NMI# (N/C)

S_INTD# Select bit

S_INTC# Select bit

S_INTB# Select bit

S_INTA# Select bit

m

u x

m

u x

m

u x

m

u x

DMA Channel 0 Interrupt Pending DMA Channel 1 Interrupt Pending DMA Channel 2 Interrupt Pending

Performance Monitor Unit Interrupt Pending

Application Accelerator Interrupt Pending

I2C Bus Interface Unit Interrupt Pending

Messaging Unit Interrupt Pending

Primary ATU/Start BIST Interrupt Pending

Primary PCI Bridge Interface Error

Secondary PCI Bridge Interface Error

Application Accelerator Unit Error

Bus Interface Unit Error

Primary ATU Error

Secondary ATU Error

Memory Controller Unit Error

DMA Channel 0 Error DMA Channel 1 Error DMA Channel 2 Error

Messaging Unit Error

80960 Outbound Doorbell 0 80960 Outbound Doorbell 1 80960 Outbound Doorbell 2 80960 Outbound Doorbell 3

Latch

XINT6 Interrupt

Latch

XINT7 Interrupt

Latch

NMI Interrupt

XINT0# XINT1# XINT2# XINT3# XINT4# XINT5# XINT6# XINT7# NMI#

i960 Core Processor

4-4 IQ80960RM/RN Evaluation Board Man ual

4.3 CPU Counter/Timers

The i960 RM/RN I/O processor is equipped with two on-chip counter/timers whic h are clocked with the i960 RM/ RN I/O proc essor c lock signa l. T he i960 R M/RN I/O proc essor re ceives its c lock from the primary PCI interface clock, generated by the motherboard. Most motherboards generate a 33 MHz clock signal, although the PCI specification requires a clock frequency between 0 and 33 MHz. The timers can be programmed for single-shot or continuous mode, and can generate interrupts to the proces s or when the countdown expires.

4.4 Primary PCI Interface

The primary PCI interface on the IQ80960RM/RN platform provides the i960 RM/RN I/O processor with a connection to the PCI bus on the host system. Only the P CI-to-PCI bridge unit on the i960 RM/RN I/O pro cessor i s direct ly conne cted t o the prima ry PCI int er face. Devi ces insta ll ed on the expansion sl ots are connected to the PCI bus via the bridge unit on the i960 RM/RN I/O processor. The PCI-to-PCI bridge accepts Type 1 configuration cycles destined for devices on the secondary bus, and will forward them as Type 0 or Type 1 configur ation cycles, or as special cycles. The IQ80960RN pla tform interfaces to a 64-bit PCI bus and the IQ80960RM platform interfaces to a 32- bit PCI bus.

i960® RM/RN I/O Processor Overview

4.5 Secondary PCI Interface

The secondary PCI interface provided by the i960 RM/RN I/O proc essor is used to connect PCI

cards via the expansion slots to the host system’s PCI bus. PCI cards are attache d to the IQ80960RM/RN platform with a standard PCI connector and may contain up to four separate PCI devices. The i960 RM/RN I/O processor provides PCI-to-P CI bridge func tionality to m ap installe d PCI devices onto the host P CI bus , and supports transa ction forwarding in both direc tions across the bridge. PCI devi ce s connected via the exp ans ion slots can ther efore act as masters or sl aves on the host syste m’s PCI bus. Addit ional PCI-to- PCI bri dge devi ces are suppor ted by t he i 960 RM/RN I/O processor on its secondary PCI interface and can be designed into add-on PCI cards. In addition, the i960 RM/RN I/O processor supports “private” PCI devices on its secondary bus. Private devices are hidden from initialization code on the host system, and are configured and accessed directly by the i960 RM/RN I/O processor. The se devices are not part of the norma l PCI address space, but they can act as PCI bus masters an d transfer data to and from othe r PCI devices in the system.

Unless designat ed as private devices, PCI devic es ins talled on the secondary PCI interface of the IQ80960RM/RN platform are mapped into the system-wide PCI address space by configuration software running on the host system. No logical distinction is made at the system level between devices on the prim ary PCI bus and devices on secondary buses; all transaction forwardin g is handled tr ansparently by the PCI-to-PCI bridge. Configuration cycles and read and write accesses from the host are forwarded through the PCI-to-PCI bridge unit of the i960 RM/RN I/O pr oce ssor. Master read and write cycles from devices on the secondary PCI bus are also forwarded to the host bus by the PCI-to-PCI bridge unit.

IxWORKS allows secondary PCI devices to be con f ig u red as Pub lic or Private. Public devices are configured by the PCI host. Private devices are configured by the IxWORKS kernel and the device-spec ific HDM.

IQ80960RM/RN Evaluation Board Ma nual 4-5

i960® RM/RN I/O Processor Overview

4.6 DMA Channels

The i960 RM/RN I/O processor features three independent DMA channels, two of which operate on the primary PCI interfa ce , whereas the remaining one operates on the secondary PCI interface.

All three of the DMA channels connect to the i960 RM/RN I/O proces sor’s local bus and can be used to transfer data from PCI devices to memory on the IQ80960RM/RN platfor m. Support for chaining, and scatter/gather is bu ilt into all three ch an nels. The DMA can address the entire 2 bytes of address space on the PCI bus and 2

Figure 4-4. i960

®

RM/RN I/O Processor DMA Controller

Primary PCI Bus

32

bytes of address space on the internal bus.

DMA Channel 0

64

DMA Channel 1

PCI to PCI Bridge

DMA Channel 2

Secondary PCI Bus

4.7 Application Accelerator Unit

The Application Accelerator provi des low-latency, high-throughput data transf er capability between the AA unit and 80960 local memory. It executes data transfers to and fr om 8096 0 local memory and also provides the ne cessary programming int erface. The Application Accelerator performs the following functions:

• Transfers data (read) from memory controller

• Performs an optional boolean operation (XOR) on read data

• Transfers data (write) to memory controller

The AA unit features:

• 128-byte, arranged as 8-byte x 16-deep store queue

• Utilization of the 80960RN/RM processor memory cont roller interface

32

• 2

addressing range on the 80960 local memory interface

80960 Local Bus

• Hardware support for unalign ed da ta transfers for the inte rnal bus

• Full programmability from the i960 core processor

• Support for automatic data chaining for gathering and scattering of data blocks

4-6 IQ80960RM/RN Evaluation Board Man ual

Figure 4-5 shows a simplified connection of the Application Accelera tor to the i960 RM/RN I/O

Processor Internal Bus.

Figure 4-5. Application Accelerator Unit

Application Accelerator Unit

Data Queue

Boolea n U ni t

i960® RM/RN I/O Processor Overview

Packing/

Unpacking

Unit

4.8 Performance Monitor Unit

The Performance Moni toring features aid in measuring and monito ring various system para me ters that contribute to the overall performance of the processor. The monitoring facility is generically

referred to as PMON – Performance Monitoring. The facility is mod el s pecific, not architect ur al; its intended use is to gather performance measurements that can be used to retune/refine code for better system level performance.

The PMON facility provided on the i960 RM/RN I/O processor comprises:

• One dedicated global Time Stamp c ounter, a nd

• Fourteen (14) Programmable Event counters

The global time stamp c ounter is a dedicated, free running 32-bit counter . The programmable event counters are 32-bits wide. Each counter can be programmed to observe

an event from a defined set of events. An event consists of a set of parameters which define a start condition and a stop condition . T he m onitored events ar e selected by programmi ng an event select register (ESR).

80960

Bus Interface

64-bit Internal Bus

IQ80960RM/RN Evaluation Board Ma nual 4-7

MON960 Support for IQ8 09 60 RM/RN

5

This chapter discusses a number of additions that have been made to MON960 to support the IQ80960RM/RN in an optional non-I MON960, see the MON960 Debug Monitor User’s Guide. Th e IQ80960RM/RN evaluation platform ships with IxWorks* from W ind River Systems installed in flash firmware . To use CTOOLS and MON960 instead of IxWorks, you need to download MON960 into the onboard Flash. See Chapter 2 for more information on updating the onboard Flash. See Chapter 1 for descriptions of both IxWorks and CTOOLS.

2

O capacity. For com plete documentation on the operation of

5.1 Secondary PCI Bus Expansion Connectors

The IQ80960RM/RN pl atform con tains four se condar y PCI bus e xpansion c onne ctors to g ive users access to the second ary PCI bus of the i960 perform secondary PCI bus initialization including the establishment of a secondary PCI bus address map. Routines compatible with the PCI Local Bus Specification Revision 2.1 allow the software on the IQ80960RM/RN pla tform to search for devices o n the secondary P CI bus and read and write the configuration space of those devices.

®

RM/RN I/O processor. Extensions to MON960

5.2 MON960 Components

The remaining sections of this chapte r assume that MON960 is installe d in the onboard Flash, replacing IxWorks. The IQ80960RM/RN optional MON960 debug monitor consists of four main components:

• Initialization firmware • MON960 extensions

• MO N 9 60 kern el • Diagnostics/e xample code

These four components together are referred to as MON960.

5.2.1 MON960 Initialization

At initialization, MON960 puts the I Q80960RM/RN platform into a known, functional state that allows the host processor to perform P CI initializati on. Once in this state, the MON960 kernel and the MON960 extensions ca n load and execute correctly. Initiali zation is performed after a RES ET condition. MON960 initialization encompasses all m ajor portions of the i960 RM/RN I/O processor and IQ8 0960RM/RN pl at form includ ing 80 960JT core ini tial izat ion, Memory C ontr oll er initialization , SDRAM initialization, Primary PCI Addres s Translation Unit (ATU) initial ization, and PCI-to-PCI Bridge Unit initializat ion.

The IQ80960RM/RN pl atform is desi gned to use th e Conf igur ation Mode of the i96 0 RM/R N I/O processor. Conf igu ration Mode all ows th e 8 0960 JT core t o in itia li ze an d cont rol the i nit iali zati on proc ess before the PCI host conf igures the i960 RM/RN I/O process or. By utili zing Configur ation Mode, the user

IQ80960RM/RN Evaluation Board Ma nual 5-1

MON960 Support for IQ80960RM/RN

is give n the ability to initialize the PCI configuration re gisters to values other than the default power-up values. Confi gura tion Mod e giv es the user maxi mum flexi bil ity to c ustom ize t he way in which the i96 0 RM/RN I/O process or and IQ80960 RM/R N platform app ear to th e PCI host confi gura tion s oftware.

5.2.2 80960JT Core Initialization

The 80960JT core begins the init ializ ation process by readin g its I nitia l Memory Image (IMI) from a fixed address in the boot ROM (FEFF FF30H in the i960 address space). The IMI incl udes the Initialization Boot Record (IBR), the Proce ss Control Block (PRCB), and several syst em data structures. The IBR provides initial configuration information for the core and integrated perip h erals, p o i nters to the system data structures and the first instruction to be executed after processor initialization, and checksum words that the processor uses in its self-test routine. In addition to the IBR and PRCB, the required data structures are the:

• System Procedure Table

• Control Table

• Interrupt Table

• Fault Table

• User Stack (application dependent)

• Supervisor Stack

• Interrupt Stack

5.2.3 Memory Controller Initialization

Since the i960 RM/RN I/O processor Memory Controller is integral to the design and operati on of the IQ80960RM/RN platform, the operational parameters for Bank 0 and Bank 1 are established immediately after processor core initialization. Memory Bank 0 is associated with the ROM on the IQ80960RM/RN platform. Memory Bank 1 is associated with the UART and the LED Control Register. Parameters such as Bank Base Address, Read Wait States, and Write Wait States must be established to ensure the proper oper ation of the IQ80960RM/RN platform. The Memory Controll er is initialize d so as to be consistent with the IQ80960RM/RN platform memory map shown in Figure 4-2.

5.2.4 SDRAM Initializatio n

SDRAM initialization includes setting operational parameters for the SDRAM controller, and sizing and clearing the installed SDRAM configuration. To configure the system properly, Presence Detect data is read from the EEPROM of the SDRAM module, using the 80960RM/RN I Unit. Presence Detect data includes the number and size of SDRAM banks present on the installed module. On power-up, 64 bytes of Presence Detect data are read and validated. The SDRAM controller is then configured by setting the base address of SDRAM, the boundary limits for each SDRAM bank, the refresh cycle interval, and the output buffer drive strength. Once the SDRAM controller is configured, the SDRAM is cleared in preparation for the C language runtime environment. The actual SDRAM size is stored for later use (e.g., to establish the size of the IQ80960RM/RN platform PCI Slave image). The SDRAM controller is initialized to be consistent with the IQ80960RM/RN platform memory map shown in Figure 4-2.

2

C Bus Interface

5-2 IQ80960RM/RN Evaluation Board Man ual

5.2.5 Primary PCI Interface Initialization

The IQ80960RM/RN platform is a multi-function PCI device. On the primary PCI bus, two functions (from a PCI Configuration Space standpoint) are supported.

• Function 0 is the PCI-to-P CI Bridge of the i960 RM/RN I/O processor, which optionally

provides access capability between the pr im ary PCI bus and the secondary PCI bus.

• Function 1 i s the Primary ATU which provides access capability between the primary PC I bus

and the local i960 bus.

The platform can be initialized into one of four modes. Modes 0 and 3 are described below.

Table 5-1. Initialization Modes

MON960 Support for IQ80960RM/RN

RST_MODE#/

SW1-1

0/ON 0/ON Mode 0 Accepts Transactions Held in Reset

0/ON 1/OFF Mode 1 Retrie s All Configuration Transact ions Held in Reset 1/OFF 0/ON Mode 2 Accepts Transactions Initializes 1/OFF 1/OFF Mode 3 (default) Retries All Configuration Transa ctions Initializes

RETRY/

SW1-2

Initialization

Mode

When the IQ80960RM/RN is opera ting in Mode 0, the processor core is held in reset, allowing register defa ult s to be us ed on the Primary PCI int erfac e. This mode is u sed to program the onboa rd Flash with either IxWORKS* or MON960.

When the IQ80960RM/RN pla tform i s operatin g in Mode 3, the Conf igura tion Cyc le Dis able bi t in the Extended Bridge Control Register (EBCR) is set after IQ80960RM/RN processor reset. In this mode, the IQ80960RM/RN platform sends PCI Retrie s when the PCI host attempts to access the

platform’s Configura tion S pace. Thi s mode al lows the IQ80960RM/RN proc essor t ime to i nit ializ e its internal registers. The process or remains in this mode until the Configuration Cyc le Disable bit in the Extended Bridge Control Register (EBCR) is cleared. For this reason, and to prevent PCI host problems, Pri mar y P CI initialization occurs at the earliest possible opportu nity after Memory and SDRAM controll er initialization.

5.2.6 Primary ATU Initialization

Primary ATU (Bridge) initialization includes initialization by the 80960JT core and initialization by the PCI host processor. Local in itialization occurs fi r st and consists mainly of esta blishing the operational paramete rs for access to the local IQ80960 RM/RN pla tform bus. The Primar y Inbound ATU Limit Registe r (P IALR) is initialized to establish the block si ze of memory required by the Primary ATU. The PIALR value is based on the installed SDRAM configuration. The Primary Inbound ATU Translate Value Register (PIATVR) is initializ ed to es tabl ish t he trans lat ion value for PCI-to - Local accesses. The PIATVR value is set to reference the b ase of local SDRAM. The Primary Outbou nd Memory Window Value Register (POMWVR) is initialized to establish the translation value for Local-to-PCI accesses. The POMWVR value remains at its default value of “0” to allow the IQ80960RM/RN platform to access the st art of the PCI Memory address map, which is typically occupied by PCI host memory. Likewise, the Prim ary Outbound I/O W indow Value Register (POIOWVR) remains at its def ault value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI I/O address map. PCI Doorbell-related parameters are also establishe d to allow for communicatio n betwe en the IQ80960RM/RN platform and a PCI bus master using the doorbell mechanism.

Primary PCI Interface

i960 Core

Processor

IQ80960RM/RN Evaluation Board Ma nual 5-3

MON960 Support for IQ80960RM/RN

By default, Primary Outbound Configura tion Cycle parameters are not established. The ATU Configuration Register (AT UCR) is initialized to establish the operational parameters for the Doorbell Unit and ATU interrupts (both primary and secondary), and to enable the primary and secondary ATUs. The PCI hos t is respo n sible for allocating PCI address space (Memo ry, Memory Mapped I/O, and I/O), and assigning the PCI Base addresses for the IQ80960RM/RN platform.

5.2.7 PCI-to-PCI Bridge Initialization

PCI-to-PCI Bridge initialization includes initialization by the 80960JT core and initialization by the PCI host processor . Local initialization occurs first and consists mainly of establishing the operational parameters for the secondary PCI interface of the PCI-to-PCI bridge. On the IQ80960RM/RN platform, the secondary PCI bus is configured to consist of private devices (not visible to PCI host configuration cycles). To support a private secondary PCI bus, the Secondary IDSEL Select Register (SISR) is initialized to prevent the secondary PCI address bits [20:16] from being asserted during conversion of PCI Type 1 configuration cycles on the primary PCI bus to PCI Type 0 configuration cycles on the secondary PCI bus. Secondary PCI bus masters are prevented from initiating transactions that will be forwarded to the primary PCI interface. The PCI host is responsible for assigning and initializing the PCI bus numbers, allocating PCI address space (Memory, Memory Mapped I/O, and I/O), and assigning the IRQ numbers to valid interrupt routing values.

5.2.8 Secondary ATU Initialization

Secondary ATU (Bridge) initialization consists mainly of establishing the operational parameters for access between the local IQ80960RM/RN platform bus and the secondary PCI devices. The Secondary Inbound ATU Base Address Register (SIABAR) is initialized to establish the PCI base address of IQ80960RM/RN platform local memory from the se condary PCI bus. By convention,

the secondary PCI base address for access to IQ80960RM/RN pla tform local memory is “0”. The Secondary Inbound ATU Limit Register (SIALR) is initialized to establish the block size of memory required by the secondary ATU. The SIALR value is based on the installed SDRAM configuration. The Secondary Inbound ATU Translate Value Register (SIATVR) is initialized to establi sh the translation value for Secondary PCI-t o-Local accesses. Th e SI ATVR value is set to reference the ba se of loca l S DRAM. T he Secondary Outbound Memory Window Value Register (SOMWVR) is initialized to establish the translation value for Loc al-to-Seconda ry PCI acces ses. The SOMWVR value is left at its default value of “0” to allow the IQ8 0960RM/RN platform to access the start of the PCI Memory address map. Likewis e, the Secondary Outbound I/ O W indow Value Register (SOIOWVR) is left at its default value of “0” to allow the IQ80960RM/RN platfo rm to access the start of the PCI I/O address map.

On the secondary PCI bus, the IQ80960RM/RN platform assumes the duties of PCI host and, as such, is required to configure the devices of the secondary PCI bus. Secondary Outbound Configuration Cycle parameters are established during s ec ondary PCI bus configuration. Secondary PCI bus configuration is ac com plished via MON960 Extens ion routines.

5-4 IQ80960RM/RN Evaluation Board Man ual

5.3 MON960 Kernel

The MON960 Kernel (monitor) provides the IQ80960RM/RN user with a software platform on which application software can be developed and run. The monitor provides several features available to the IQ80960RM/RN user to speed application development. Among the available features are:

• Communication with a terminal or termi nal emulation package on a host computer through a

seria l cab l e w it h automa ti c b a u d ra te det ection

• Communication with a software debugger such a s GDB960 (available from Intel ) usi ng the

Host Debugger Interface (HDI) softwa re i nterface

• Communication with the host computer via the primary PCI bus

• Downloads of ELF obje ct fil es vi a the pr imary PCI bus or vi a t he seria l cons ole port at rat es up

to 115,200 baud

• Downloads of ELF object files via the primary PCI bus

• On-board erasure and prog rammi ng of Intel 28F016S5 Flash ROM

• Memory display and m odification capability

• Breakpoint and single-step capability to support debugging of user code

• Disassembly of i96 0 processor instructions

MON960 Support for IQ80960RM/RN

5.4 MON960 Extensions

The monitor has been extended to include the sec ondary PCI bus initializ ation and also the BIOS routines which are contained in the PCI BIOS Specificati on Revision 2.1.

5.4.1 Secondary PCI Initialization

MON960 extensions are res ponsible for initializing the devices on the secondary PCI bus of the IQ80960RM/RN platform . Secondary PCI initialization involves allocating address spaces (Memory, Memory Mapped I/O, a nd I/ O), ass igning PCI ba se addre sses , assigni ng IR Q value s, and enabling PCI masters hip. MON960 does not support devices containing PCI-to-PCI bridges and hierarch i cal buses.

IQ80960RM/RN Evaluation Board Ma nual 5-5

MON960 Support for IQ80960RM/RN

5.4.2 PCI BIOS Routines

MON960 includes PCI BIOS rout ines to aid applicati on software initial iza tion of the secondary PCI bus. The supported BIOS functions are described in the subsections that follow.

sysPCIBIOSPresent sysFindPCIDevice sysFINDPCIClassCode sysGenerateSpecialCycle sysReadConfigByte sysReadConfigWord sysReadConfigDword sysWriteConfigByte sysWriteConfigWord sysWriteConfigDword sysGetIrqRoutingOptions sysSetPCIIrq

These functions preserve, as close ly as possible, the paramet ers and return values described in the PCI Local Bus Specification Revision 2.1. Functions that return multiple va lues do so by filling in the fields of a structure passed by the calling routine.

You can acces s t hes e functions via a calls ins truction. The syst em call indices are de fined in the MON 9 60 s o ur ce file PCI_BIOS.H. The function prototypes are defined in the IQRP_ASM.H file.

5.4.2.1 sysPCIBIOSPresent

This function allows the caller to determine whether the PCI BIOS interface function set is present, and the current interfa ce version level. It also provides information about the hardware mechanism used for accessing co nfigurat ion space and whethe r or not the hard ware supports genera tion of PCI Special Cycle s.

Calling convention: int sysPCIBIOSPresent ( PCI_BIOS_INFO *info ); Return values: This function always returns SUCCESSFUL.

5-6 IQ80960RM/RN Evaluation Board Man ual

5.4.2.2 sysFindPCIDevice

This function r eturns the locati on of PCI devices that have a specific Device ID and Vendor ID. Given a Vendor ID, a Device ID, and an Index, the function returns the Bus Number, Device Number, and Funct ion Number of t he Nt h Device/F uncti on whose Vendor ID and Device ID match the input parameters .

Calling software can find all devices having the same Vendor ID and Device ID by making

successive calls to this function starting with the index se t to “0”, and incrementing the index until the function returns DEVICE_NOT_FOUND. A return value of BAD_VENDOR_ID indicates that the Vendor ID value passed had a value of all “1”s.

Calling convention: int sysFindPCIDevice ( int device_id, int vendor_id, int index );

MON960 Support for IQ80960RM/RN

Return values: This function returns SUCCESSFUL if the indicated d evice is locate d, DEVICE_NOT_FOUND if

the indicated device cannot be locate d, or BAD_VENDOR_ID if the vendor_id value is illegal.

5.4.2.3 sysFindPCIC lass C ode

This functio n r eturns the locati on of PCI devices that have a spe cific Class Code. Given a Class Code and an Index, t he f unction returns the Bus Num ber , Device Num ber , and Fu nction Nu mber of the Nth Device/Fun ction whose Class Code matche s the input parameters.

Calling software can find all devices having the same Class Code by making successive calls to this functi on sta rting wi th t he inde x set to “0”, and in cre menti ng the i ndex unt il t he func tio n returns DEVICE_NOT_FOUND.

Calling convention: int sysFindPCIClassCode (

int class_code, int index

); Return values: This function returns SUCCESSFUL when the indicated device is located, or

DEVICE_NOT_FOUND when the indicated device cannot be located.

IQ80960RM/RN Evaluation Board Ma nual 5-7

MON960 Support for IQ80960RM/RN

5.4.2.4 sysGenerateSpecialCycle

This function a llows for generati on of PCI Spe cial Cycles. The ge nerated s pecia l cycl e is br oadcast on a specific PCI Bus in the system.

PCI Special Cycl es are not supported on the IQ80960RM/RN platform secondary PCI bus . Calling convention: int sysGenerateSpecialCycle (

int bus_numb er, int special_cycle_data

); Return values: Since PCI Specia l Cycles are not supported by the IQ80960RM/RN platform, t his function always

returns FUNC_NOT_SUPPORTED.

5.4.2.5 sysReadConfigByte

This function allows the caller to read individual bytes from the configuration space of a specific device.

Calling convention: int sysReadConfigByte (

int bus_number,

int device_number,

int function_number,

int register_number, /* 0,1,2,...,255 */

UINT8 *data

); Return values: This function returns SUCCESSFUL when the indicated byte was read correctly, or ERROR when

there is a problem with the parameters.

5-8 IQ80960RM/RN Evaluation Board Man ual

5.4.2.6 sysReadConfigWord

This function allows the caller to read individual shorts (16 bits) from the configuration space of a

specific device. The Register Number parameter must be a multi ple of two (i.e., bit 0 must be set to “0”). Calling convention: int sysReadConfigWord (

int bus_number, int device_number, int function_number, int register_number, /* 0,2,4,...,254 */ UINT16 *data

); Return values: This function returns SUCCESSFUL when the indicated word was read correctl y , or ERROR when

there is a pro b l em w i th th e pa r ameters.

MON960 Support for IQ80960RM/RN

5.4.2.7 sysReadConfigDword

This function allows the caller to read individual longs (32 bits) from the configuration space of a specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must be set to “0”) .

Calling convention: int sysReadConfigDword (

int bus_number,

int device_number,

int function_number,

int register_number, /* 0,4,8,...,252 */

UINT32 *data

); Return values: This function returns S U CCESSFUL when the indicated long was read c orrectly, or ERROR when

there is a pro b l em w i th th e pa r ameters.

IQ80960RM/RN Evaluation Board Ma nual 5-9

MON960 Support for IQ80960RM/RN

5.4.2.8 sysWriteConfigByte

This function allows the caller to w r ite in d iv id ual byte s to the configuration space of a specif ic d ev ice. Calling convention: int sysWriteConfigByte (

int bus_number, int device_number, int function_number, int register_number, /* 0,1,2,...,255 */ UINT8 *data

); Return values: This function returns SUCCESSFUL when the indicated byte was written correctly, or ERROR

when there is a problem with the parameters.

5.4.2.9 sysWriteConfigWord

This function allows the c aller to writ e individual shorts (16 bits ) to t he configuration space of a specific

device. The Registe r Numbe r parameter must be a multiple of two (i.e., bit 0 must be set to “0”). Calling convention: int sysWriteConfigWord (

int bus_number,

int device_number,

int function_number,

int register_number, /* 0,2,4,...,254 */

UINT16 *data

); Return values: This function returns SUCCESSFUL when the indicated word was written correctly, or ERROR

when there is a problem with the parameters.

5-10 IQ80960RM/RN Evaluation Board Man ual

5.4.2.10 sysWriteConfigDword

This function allows the caller to write individual longs (32 bits) to the configuration space of a specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must

be set to “0”) . Calling convention: int sysWriteConfigDword (

int bus_number, int device_number, int function_number, int register_number, /* 0,4,8,...,252 */ UINT32 *data );

Return values:

MON960 Support for IQ80960RM/RN

This function returns SUCCESSFUL when the indicated long was written correctly, or ERROR when the r e is a problem with the parameters .

5.4.2.11 sysGetIrqRoutingOpti ons

The PCI Interrupt routing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed mapping relationships); therefore, this function is not supported.

Calling convention: int sysGetIrqRoutingOptions (

PCI_IRQ_ROUTING_TABLE *table

); Return values: This function always returns FUNC_NOT_SUPPORTED.

IQ80960RM/RN Evaluation Board Ma nual 5-11

MON960 Support for IQ80960RM/RN

5.4.2.12 sysSetPCIIrq

The PCI Interrupt rout ing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed mapping relationships); therefore, this function is not supported.

Calling convention: int sysSetPCIIrq (

int int_pin, int irq_num, int bus_dev

); Return values: This function always returns FUNC_NOT_SUPPORTED.

5.4.3 Additional MON960 Commands

The following commands have been added to the UI interface of MON960 to support the IQ80960RM/RN platform.

5.4.3.1 print_pci Utility

A print _pc i c omma nd to MON96 0 i s acc e sse d t hroug h t he MON9 60 c o mmand prom pt . Th is co mma nd displays the contents of the PCI configuration space on a selected adapter on the secondary PCI interface or on the i960 RM/RN I/O processor itself. For more information on the meaning of the fields in PCI configuration space, refer to the PCI Local Bus Specification Revisi on2.1. Th e s ynta x o f t his com man d is :

pp <bus number> <device number> <function number>

5.5 Diagnostics / Example Code

IQ80960RM/RN platform diagnostic routines serve a twofold purpose: to verify proper hardware operation and to provide example code for users who need similar functions in their applications. Diagnostic routines fall into two categories: board level diagnostics and PCI expansion module diagnostics.

5.5.1 Board Level Diagnostics

Board level diagnostics exercise all basic areas of the IQ80960RM/RN platform. Diagnostic routines include SDRAM tests, UART tests, LED tests, internal timer tests, I Primary PCI bus tests exercise the primary A TU, the PCI Doorbell unit, and the PCI DMA controller. Interru pts fr om bot h loca l and P CI so urces a re gen erate d and h andle d. The P CI bus tests r equi re an exter nal test sui te ru nn ing on a PC to veri fy comp let e fun c tion a lit y of th e IQ80 960 RM /RN pl a tform .

2

C bus tests, and primary PCI bus tests.

5.5.2 Secondary PCI Diagnostics

Secondary PCI diagn ost ics exercise the secondary P CI bus , thereby confirming hardware functionality, as well as illustrating the use of the PCI BIOS routines present in MON960.

5-12 IQ80960RM/RN Evaluation Board Man ual

Bill of Materia ls A

This appendix ide ntifies all components on the IQ80960RN Evaluat ion P latform (Table A-1), and the IQ80960RM Evaluation Platform (Table A-2).

Table A-1. IQ80960RN Bill of Materials (Sheet 1 of 4)

Item Qty Locati on Part Descripti on Manufactur er Manufacturer Part #

1 1 U13 IC/SM 74ALS32 SOIC-14

2 1 U6 IC/SM 74ALS04 SOIC

3 1 U3 IC/SM 74ABT273 SOIC

4 2 U1,U2 IC/SM 74ABT573 SOIC

5 1 U16 IC/SM 74ALS08 SOIC

6 1 U5 IC / SM 1488A SOIC

7 1 U7 IC / SM 1489A SOIC 8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY

9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 10 1 U10 IC/S M LM 33 9 S OI C- 1 4 11 1 U8 IC/S M MAX1651 CSA SOIC -8 M axim MAX1651CSA

12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE 13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 PROCESSOR (from I ntel) 80960RN Intel

15 1 U12 VLSI I/O UART 16C550 PLCC 16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0

C2, C3, C10, C11, C18, C19,

17 15

C26, C27, C55, C58, C61, C68, C77, C83, C96

CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC

National Semiconductor

Texas Instruments

Texas Instrumen ts

National Semiconductor

National Semiconducto r

Texas Instruments

DM74ALS32M

DM74ALS04BM

SN74ABT273DW

SN74ABT573DW

DM74ALS08M

DS1488M

DS1489AM

LM339M

TL16C550AFN

IQ80960RM/RN Evaluation Board Ma nual A-1

Bill of Materials

Table A-1. IQ80960RN Bill of Materials (Sheet 2 of 4)

Item Qty Location Part Description Manufacturer Manufacturer Part #

C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C48, C49,

18 79

19 1 C110 CAP SM, 18 pF (0805) Kemet C0805C180J5GAC 20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT 21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT 22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT

23 4 24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT

25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT 26 3 27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT

28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT 29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT 30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT 31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT

C50, C51, C53, C59, C62, C66, C67, C69, C70, C71, C73, C79, C80, C81, C85, C86, C87, C94, C95, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C1 11, C1 12 , C11 3, C1 15, C11 6, C1 14, C11 7

R35, R39, R58, R59

R14, R41, R42

CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2

R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT

R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT

A-2 IQ80960RM/RN Evaluation Board Man ual

Table A-1. IQ80960RN Bill of Materials (Sheet 3 of 4)

Item Qty Locati on Part Descripti on Manufactur er Manufacturer Part #

32 2 R2, R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT 33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT 34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT 35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT 36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT 37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT 38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT

39 4

40 5

41 4 42 1 J5 CONN DIMM 168P/RAng/S ocket/TH Molex 73790-0059

43 1 J7 CONN TJ6 PCB 6/6 LP thru hole KYCON GM-N-66 44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03 45 1 J6 CONN Hdr 16 pin/w she ll, pcb AMP 10330 8-3

46 4 47 1 L1 Inductor/SM 47µH 20% Coilcraft D03340P-473

48 1 L2 Inductor/SM 3.3 µH 20% C oi lc r af t D03 31 6P - 33 2 49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S 50 1 U4 OSC 1.8432 MHz 1/2 - Thru hole Kyocera KH0HC1CSE 1.843 51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC

52 1 CR5 LED Green

53 1 CR3 LED-Red

54 1 CR4 LED Green LP 55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001

56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM 57 1 Q4 Tra nsistor 2N6109 (Thru Hole) Mot orola 2N6109 58 1 U19 SOCKET PLCC2 0 LP Surface Mount AMP 822269-1

60 8

61 1 U19 P ALLV16V8Z-20JI AMD PALLV16V8Z-20JI 62 1 U11 MEM Flash E28F016S5-090 TSOP Intel E2 8F016S5-090

63 8

R30, R43, R54, R56

J8, J9, J10, J11, J12

J1, J2, J3, J4

Z1, Z2, Z3, Z4

BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8

R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT

CONN SM/TH Mictor 43P Recptcl AMP 767054-1

CONN PCI 64BIT 5 V/PCB ThruHole AMP 145166-4

Jumper JUMP2X1 Molex 22-54-1402

Battery Clips/PC/Snap-In/AA Keystone #92

Batte ry A A Ni C d @ 60 0 mA/Hour SAFT NIC-AA- 60 0- S A FT

Hewlett Packard

Bill of Materials

HLMP-3507$010

HLMP3301$010

HLMP4740#010

IQ80960RM/RN Evaluation Board Ma nual A-3

Bill of Materials

Table A-1. IQ80960RN Bill of Materials (Sheet 4 of 4)

Item Qty Location Part Description Manufacturer Manufacturer Part #

64 1 U15 HeatSink/Fan Assy 8 0960RM/RN Panasonic UDQFNBEOIF 65 1 C84 CAP SM, 0.22 µF (12 06 ) P hi lip s 12062E224M9 B B2

66 3

67 4 68 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T 69 4 70 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T

71 1 C74 CAP TANT SM 1 µF, 16 V (32 16) Sprague 293D1 05X0016A 2T 72 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprag ue 293D1060025D2T 73 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100 74 1 C64 CAP TANT SM 330 µF 6.3 V (7343 AVX TPSE337K063R0100 75 1 C82 CAP SM, 0.047 µF (0805) Keme t C0805 C473K5RAC 76 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012 77 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050 78 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT

79 16

80 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR 81 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR 82 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR 83 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR

84 1 CR9 Diode CMPSH3 Surface Mount 85 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3 86 1 CR8 Diode/SM 1N4001 (CMR1-02) 87 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG

C60, C75, C78

C89, C90, C91, C93

C57, C76, C88, C92

R1, R3, R4, R5, R6, R7, R8, R9, R10, R1 1, R12, R33, R36, R38, R44, R45,

CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010

CAP TANT SM 47 µF, 16 V (7343) A VX TPSD476K016R015

CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T

Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR

Central Semiconductor

CMPSH3

CMR1-02

A-4 IQ80960RM/RN Evaluation Board Man ual

Table A-2. IQ80960RM Bill of Materials (Sheet 1 of 4)

Item Qty Locati on Part Descripti on Manufactur er Manufacturer Part #

1 1 U13 IC/SM 74ALS32 SOIC-14

2 1 U6 IC/SM 74ALS04 SOIC

3 1 U3 IC/SM 74ABT273 SOIC

4 2 U1, U2 IC/SM 74ABT573 SOIC

5 1 U16 IC/SM 74ALS08 SOIC

6 1 U5 IC / SM 1488A SOIC

7 1 U7 IC / SM 1489A SOIC

8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY

9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 10 1 U10 IC/SM LM 33 9 S O IC- 1 4 11 1 U8 IC/SM MAX1651CSA SO IC-8 Maxim MAX1651C SA

12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE 13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 PROCESSOR (frm Intel) i960RM Intel

15 1 U12 VLSI I/O UART 16C550 PLCC 16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0

C2, C3, C10, C11, C18, C19,

17 15

C26, C27, C55, C58, C61, C68, C77, C83, C96

CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC

National Semiconductor

Texas Instruments

National Semiconductor

National Semiconducto r

Texas Instruments

Bill of Materials

DM74ALS32M

DM74ALS04BM

SN74ABT273DW

SN74ABT573DW

DM74ALS08M

DS1488M

DS1489AM

LM339M

TL16C550AFN

IQ80960RM/RN Evaluation Board Ma nual A-5

Bill of Materials

Table A-2. IQ80960RM Bill of Materials (Sheet 2 of 4)

Item Qty Location Part Description Manufacturer Manufacturer Part #

C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46,

18 79

19 1 C110 CAP SM, 18 pF(0805) Kemet C0805C180J5GAC 20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT 21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT 22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT

23 12

24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT 25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT

26 3 27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT

28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT

C48, C49, C50, C51, C53, C59, C62, C66, C67, C69, C70, C71, C73, C79, C80, C81, C85, C86, C87, C94, C95, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C1 11, C1 12 , C11 3, C1 14, C11 5, C1 16, C11 7

R5, R6, R7 R8, R9, R10, R1 1, R12, R35, R39, R58, R59

R14, R41, R42

CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2

R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT

R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT

A-6 IQ80960RM/RN Evaluation Board Man ual

Table A-2. IQ80960RM Bill of Materials (Sheet 3 of 4)

Item Qty Locati on Part Descripti on Manufactur er Manufacturer Part #

29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT 30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT 31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT 32 1 R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT 33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT 34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT 35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT 36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT 37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT 38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT

39 4

40 5

41 4 42 1 J5 CONN DIMM 168P/RAng/Socket/TH Molex 73790-0059

43 1 J7 CONN TJ6 P CB 6/6 LP thru hole KYCON GM-N-66 44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03 45 1 J6 CONN Hdr 16 pin/w she ll, pcb AMP 10330 8-3

46 4 47 1 L1 Inductor/SM 47 µH 20% Coilcraft D03340P-473

48 1 L2 Inductor/SM 3.3 µH 20% C oi lc r af t D03 31 6P - 33 2 49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S 50 1 U4 OSC 1.8432 MHz 1/2 - Thru hole Kyocera KH0HC1CSE 1.843 51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC

52 1 CR5 LED Green

53 1 CR3 LED-Red

54 1 CR4 LED Green LP 55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001

56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM 57 1 Q4 Tra nsistor 2N6109 (Thru Hole) Mot orola 2N6109 58 1 U19 SOCKET PLCC2 0 LP Surface Mount AMP 822269-1 60 1 U11 SOCKET / SM / TSOP / 40 pin Meritec 980020-40-02

61 8

R30, R43, R54, R56

J8, J9, J10, J11, J12

J1, J2, J3, J4

Z1, Z2, Z3, Z4

BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8

R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT

CONN SM/TH Mictor 43P Recptcl AMP 767054-1

CONN PCI Slot 5V/PCB ThruHole AMP 145154-4

Jumper JUMP2X1 Molex 22-54-1402

Battery Clips/PC/Snap-In/AA Keystone #92

Hewlett Packard

Bill of Materials

HLMP-3507$010

HLMP3301$010

HLMP4740#010

IQ80960RM/RN Evaluation Board Ma nual A-7

Bill of Materials

Table A-2. IQ80960RM Bill of Materials (Sheet 4 of 4)

Item Qty Location Part Description Manufacturer Manufacturer Part #

62 1 U19 PALLV16V8Z-20JI AMD PALLV16V8Z-20JI 63 1 U11 MEM Flash E28 F016S5-090 TSOP Intel E28F016S5-090

BT1, BT2,

64 8

65 1 U15 HeatSink/Fan Assy 8 0960RN/RM Panasonic UDQFNBEOIF 66 3 C84 CAP SM, 0.22 µF (12 06 ) P hi lip s 12062E224M9 B B2

67 3

68 4 69 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T

70 4 71 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T

72 1 C74 CAP TANT SM 1 µF, 16 V (32 16) Sprague 293D1 05X0016A 2T 73 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprag ue 293D1060025D2T 74 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100 75 1 C64 CAP TANT SM 330 µF 6.3 V (7343) AVX TPSE337K063R0100 76 1 C82 CAP SM, 0.047 µF (0805) Keme t C0805 C473K5RAC 77 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012 78 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050 79 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT

80 7

81 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR 82 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR 83 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR 84 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR

85 1 CR9 Diode CMPSH3 Surface Mount

86 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3 87 1 CR8 Diode/SM 1N4001 (CMR1-02) 88 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG

BT3, BT4, BT5, BT6, BT7, BT8

C60, C75, C78

C89, C90, C91, C93

C57, C76, C88, C92

R1, R31, R33, R36, R38, R44, R45

Battery AA NiCd @ 600 mA/Hour SAFT NIC-AA-600-SAFT

CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010

CAP TANT SM 47 µF, 16 V (7343) A VX TPSD476K016R015

CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T

Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR

Central Semiconductor

CMPSH3

CMR1-02

A-8 IQ80960RM/RN Evaluation Board Man ual

Schemati cs B

This appendix inc ludes schematics for the IQ809 60RN (Table B-1) and IQ80960RM (Table B-2).

Table B-1. IQ80960RN Schematics List

Page Schematic Title

B-2 Decoupling and 3.3V Po wer B-3 Primary PCI Interface B-4 Memory Controller B-5 Flash ROM, UART, & LEDs B-6 Logic Analyzer I/F B-7 SDRAM 168-Pin DIMM B-8 Secondary PCI/960 Core

B-9 Secondary PCI Bus 1/2 B-10 Secondary PCI Bu s 3/4 B-11 SPCI Pull-ups B-12 Battery/Monitor

IQ80960RM/RN Evaluation Board Ma nual B-1

A

220uF

CAPT7343

21

+3V

NOTE: PINS 3-7 ARE VIAS

C86

21

CAP0805

0.1uF

CR9

2 3

CMPSH3

+5V

21

C60

CAPT7343

220uF

MAX767CAP

RFD16N05L

213

17

19

BST

VCC114VCC215VCC3

10

Q3

DH

3

34567

R46

1 2

COIL-SMT2

3.3uH L2

1 2

18

LX

ON/OFF#

21

0.012

1W 1%

CR6

Q2

RFD16N05L

213

16

DL

REF2SS9SYNC

8

C78

220uF

CAPT7343

C75

MBRS340T3 1 2

13

PGND

GND15GND26GND37GND411GND5

4

1

20

FB

CS

U17

B

C

D

BREV

1

TP1

Sheet of

4/14/98 01 11

80960RN

DECOUPLING & 3.3V POWER

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

R54 1 2

1/8W 5%

+5V

10

21

C88

4.7uF

CAPT7343

21

C84

0.22uF

CAP1206

21

C83

0.01uF

CAP0805

C40

C39

C38

C37

C36

C35

C34

C33

2 1

0.1uF

CAP0805

0.1uF

2 1

CAP0805

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

2 1

0.1uF

CAP0805

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

0.1uF

2 1

CAP0805

SDRAM DECOUPLING

RAM3V {04,06,11}

C91

2 1

CAPT7343

P33V {02,04,08,09}

SPCI DECOUPLING

C90

2 1

CAPT7343

+5V

47uF

C28

2 1

C32

2 1

0.1uF

CAP0805

C31

0.1uF

CAP0805

2 1

0.1uF

CAP0805

0.1uF

CAP0805

2 1

0.1uF

2 1

CAP0805

C24

C25

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

2 1

CAP0805

C23

0.1uF

2 1

CAP0805

2 1

0.1uF

2 1

CAP0805

C16

C17

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

C15

0.1uF

CAP0805

0.1uF

2 1

CAP0805

0.1uF

2 1

CAP0805

2 1

0.1uF

CAP0805

2 1

2 1C90.1uF

CAP0805

C14

C13

C12

C22

C21

C20

C30

C29

C6

0.1uF

2 1C50.1uF

2 1C40.1uF

2 1C80.1uF

CAP0805

C1

0.1uF

2 1C70.1uF

CAP0805

1 2 3 4 5 6 7 8

IC DECOUPLING

A

C116

C111

C105

0.1uF

CAP0805

C45

0.1uF

CAP0805

C79

0.1uF

CAP0805

2 1

C109

0.1uF

CAP0805

C46

0.1uF

CAP0805

C67

0.1uF

CAP0805

2 1

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

CAP0805

C112

C72

C41

2 1

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

CAP0805

C115

C81

C42

2 1

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

CAP0805

C114

C103

C66

C108

2 1

0.1uF

2 1

CAP0805

C99

0.1uF

CAP0805

C62

0.1uF

CAP0805

2 1

CAP0805

2 1

CAP0805

C106

C107

2 1

0.1uF

2 1

CAP0805

C70

C80

2 1

0.1uF

2 1

CAP0805

C93

C85

47uF

2 1

CAPT7343

+5V +3V +3V

0.1uF

C113

0.1uF

2 1

CAP0805

C59

C69

0.1uF

2 1

CAP0805

C73

C49

2 1

0.1uF

2 1

CAP0805

B

0.1uF

C117

0.1uF

2 1

C48

2 1

C

CAP0805

C43

0.1uF

CAP0805

0.1uF

2 1

CAP0805

C87

C71

C44

C50

0.1uF

2 1

CAP0805

0.1uF

2 1

CAP0805

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

2 1

0.1uF

CAP0805

1 2 3 4 5 6 7 8

D

A

B

C

D

BREV

PPCI

21

+12V

C95

0.1uF

21

CONNPCI_A

TRST#

1

CAP0805

C89

CAPT7343

47uF

C94

CAP0805

0.1uF

+12V

2

+5V18+5V210+5V3

INTA#7INTC#

TDI3TMS

5

6

4

9

+5V +5V

CONNPCI_A

C/BE7#63GND1

65

64

PC/BE7#

CONNPCI_B

GND167GND2

65

64

63

PC/BE6# PC/BE5#

GND113GND2

12

11

C/BE5#

66

C/BE6#

66

PC/BE4#

141915

+5V1

67

C/BE4#

PRST# PPAR64

PAR64

RST#

AD62

68

PAD63 PAD62

+5V4

16

AD5870AD60

GND272GND3

71

69

+5V1

AD6168AD63

70

69

PAD59 PAD58

GND3

GNT#

18

17

PGNT# PAD61

74

AD5771AD59

GND376GND4

72

73

+3V1

AD30

21

20

PAD28 PAD55 PAD54

J15

6

8

11

+5V2

AD5076AD52

AD5473AD56

GND481GND5

75

77

78

+5V2

AD4977AD51

AD5374AD55

79

78

75

+3V2

AD24

AD2622AD28

GND4

IDSEL

27

25

23

24

26

AD4679AD48

80

PAD22 PAD47 PAD46

AD4580AD47

GND585GND6

81

82

AD2028AD22

GND5

29

30

+5V3

AD4282AD44

84

83

PAD40

AD4183AD43

84

PAD41

J15

AD16

AD18

32

31

AD3488AD36

AD3885AD40

GND690GND793GND8

89

86

87

PAD36

+5V390AD3389AD35

AD3786AD39

88

87

PAD39 PAD38

PAD37

PAD35 PAD34

CONNPCI_A

+3V1

FRAME#35GND137GND2

TRDY#

33

34

36

AD32

91

92

PAD32

GND794GND8

91

92

PAD33

+3V2

STOP#

39

38

PSTOP#

U16

94

RST# {11}

J14

93

+5V

GND3

SBO#40SDONE

42

43

41

3

U16

1

R58

PRST#

1 2

1/10W 5%

10K

+3V3

AD1146AD13

AD15

PAR

GND4

45

47

44

48

PAD13

SPARES

4

5

10K

74ALS08

2

Z3

JUMP1X2

1 2

AD952C/BE0#

49

PAD9

74ALS08

R39 1 2

1/10W 5%

53

9

+3V4

U16

74ALS08

10

12

13

+5V161+5V262+5V3

AD0

AD2

AD454AD6

GND5

59

58

57

55

56

PAD2

74ALS08

PRIMARY PCI INTERFACE

80960RN

Title:

Name:

25 SCIENCE PARK

CYCLONE MICROSYSTEMS

J15

REQ64#

60

Sheet of

4/14/98 02 11

Date:

NEW HAVEN, CT 06511

AD23

GND7

28

C20

P_IRDY

L3

PIRDY#

PAD21 PAD20 PAD45

P_CLK

P_TRDY

L2

PTRDY#

AD1929AD21

30

PAD19 PAD44

P_STOP

M5

PSTOP#

H3

PIDSEL

J14

+3V2

31

P33V PAD18 PAD43 PAD42

P_IDSELN3P_PAR

PPAR

CONNPCI_B

AD17

32

33

P_REQ

A7

E6

PGNT# PC/BE2# P33V

PREQ# PAD17 PAD16

+3V1

C/BE2#37DEVSEL#

GND138GND2

IRDY#39LOCK#40PERR#42SERR#

36

34

35

P33V PTRDY#

PDEVSEL#

P_GNT

P_LOCK

P_RST

B7

M4

RST# PFRAME#

PLOCK# PIRDY#

PLOCK# P33V

P_AD0

U1

P_AD1

U2

P_AD2

U3

P_AD3

T1

P_AD4

T3

P_AD5

T4

P_AD6

T5

P_AD7

R1

P_AD8

R3

P_AD9

R5

P_AD10

P1

P_AD11

P3

P_AD12

P4

P_AD13

P5

P_AD14

N1

P_AD15

N2

P_AD16

K3

P_AD17

K4

P_AD18

K5

P_AD19

J1

P_AD20

J2

P_AD21

J3

P_AD22

J5

P_AD23

H1

P_AD24

H5

P_AD25

G1

P_AD26

G2

P_AD27

G3

P_AD28

E5

P_AD29

A6

P_AD30

C6

P_AD31

D6

41

PPERR#

+3V243+3V3

P33V PPAR

PSERR#

PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9

PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31

C/BE1#

44

PC/BE1# PAD15

45

PAD14 P33V

AD14

AD1047AD12

GND349GND4

48

46

PAD12 PAD11

PAD10

CLK_960

876

RNC4R8P

AD752AD8

54

53

P33V PAD6

PAD8 PC/BE0#

PAD7 P33V

LOGIC_CLK {05}

54

321

13

FB

CY7B9910-7

REF23TEST

3FS1

CLK

+3V4

PAD5 PAD4

R55

Q7

56

PAD3

22

RNC4R8P

AD355AD5

57

GND5

58

PAD1 PAD0

CLKA {08}

876

1

CONNPCI_B

AD2920AD31

21

PAD29 P33V PAD56

W3

GND6

22

PAD27 PAD26 PAD53

M3

P_PERR

P_PAR64

AD2523AD27

24

PAD25 PAD52

M1

P_SERR

+3V1

25

26

P33V PAD24 PAD51 PAD50

PC/BE3# PIDSEL PAD49

PREQ64# U5

V5

P_REQ64

P_ACK64

P_FRAME

L5

C/BE3#

27

PAD23 P33V PAD48

P33V

+5V16+5V2

-12V

GND1

3

5

TD TD

INTB#8INTD#9PRSNT1#11PRSNT2#

7

PINTB# PINTC#

TCK4TDO

1

2

+5V N12V +5V

C104

21

CAP0805

0.1uF C102

21

CAP0805

0.1uF C101

21

CAP0805

0.1uF C100

21

CAP0805

0.1uF

C98

21

CAP0805

0.1uF

C97

21

CAP0805

0.1uF

PINTD#

GND213GND315GND417GND5

12

10

AG2

PAD32

AG3

PAD33

AF1

PAD34

AF3

PAD35

AF4

PAD36

AF5

PAD37

AE1

PAD38

AE2

PAD39

AE3

PAD40

AE5

PAD41

AD1

PAD42

AD3

PAD43

AD4

PAD44

AD5

PAD45

AC1

PAD46

AC2

PAD47

AC3

PAD48

AC5

PAD49

AB1

PAD50

AB3

PAD51

AB4

PAD52

AB5

PAD53

AA1

PAD54

AA2

PAD55

AA3

PAD56

AA5

PAD57

Y1

PAD58

Y3

PAD59

Y4

PAD60

Y5

PAD61

W1

PAD62

W2

PAD63

14

+5V3

CLK

REQ#

19

16

18

PAD31 PAD30 PAD57

PREQ# PAD60

E8

E7

P_AD32 P_AD33

P_INTAD8P_INTB

P_INTCC7P_INTD

P_AD34 P_AD35 P_AD36 P_AD37 P_AD38 P_AD39 P_AD40 P_AD41 P_AD42 P_AD43 P_AD44 P_AD45 P_AD46 P_AD47 P_AD48

U15

i960RN

P_AD49 P_AD50 P_AD51 P_AD52 P_AD53 P_AD54 P_AD55 P_AD56 P_AD57 P_AD58 P_AD59 P_AD60 P_AD61 P_AD62 P_AD63

PRIMARY PCI SIGNALS

P_C/BE0N5P_C/BE1K1P_C/BE2H4P_C/BE3W5P_C/BE4V1P_C/BE5V3P_C/BE6V4P_C/BE7L1P_DEVSEL

R2

1 2 3 4 5 6 7 8

PC/BE0# PINTA#

PC/BE1# PINTB#

PC/BE2# PINTC#

PC/BE3# PINTD#

PC/BE4#

PC/BE5# PPAR64

PC/BE6# PPERR#

PC/BE7# PSERR#

PFRAME# PACK64#

PPCI PINTA#

PDEVSEL#

+5V161+5V262+5V3

ACK64#

AD1

59

60

PACK64# PREQ64#

CLKB {08}

3

2

CLKC {09}

CLKD {09}

54

7Q08Q110Q211Q315Q416Q518Q619

J14

22

R40

U18

1 2 3 4 5 6 7 8

A

B

C

D

A

DCLKIN

DRAMCLK_LA {05}

DCLK0 {06}

DCLK1 {06}

DCLK2 {06}

DCLK3 {06}

B

C

D

BREV

Sheet of

MEMORY CONTROLLER

4/14/98 03 11

80960RN

Title:

Name:

Date:

+3V

RNC4R8P

876

4

OUT05OUT1

MPC9140/CDC318

CLKIN38OE

11

R57 1 2

1/10W 5%

2.7K 12

R29

DCLKOUT

8

1/10W 5%

321

R23

30

RNC4R8P

5 4

OUT29OUT313OUT414OUT517OUT618OUT731OUT832OUT9

36

876

321

R22

30

5 4

35

OUT1036OUT1140OUT1241OUT1344OUT1445OUT1521OUT1628OUT17

SCLK24SDA

25

SCL {06,07}

SDA {06,07}

RAD {04,05}

SEL_LED# {04}SM2 RAD1/32BITPCI_EN#

8

25 SCIENCE PARK

SELUART# {04}

3

U13

1

U9

ROMA18

ROMA {04}

R42 1 2

1/10W 5%

1 2

1.5K

JUMP1X2

Z2

IOW# {04}

U13

9

10

6

U13

74ALS32

2

74ALS32

U6

5

RWE#

13 12

4

74ALS32

74ALS04

12

11

U6

IOR# {04}

U13

13

11 10

74ALS32

74ALS04

Z1

1 2

RAD4/STEST

JUMP1X2

TP2

1

RAD0

R41 1 2

1.5K

CYCLONE MICROSYSTEMS

1/10W 5%

NEW HAVEN, CT 06511

SCB7

SCB6

SCB5

K32

K30

V31

W32

K31

K28

V30

W30

DQ32

E22

DQ32

DQ33

B23

DQ33

DQ34

E23

DQ34

DQ35

C24

DQ35

DQ36

E24

DQ36

DQ37

B25

DQ37

DQ38

E25

DQ38

DQ39

C26

DQ39

DQ40

A27

DQ40

DQ41

C27

DQ41

DQ42

A28

DQ42

DQ43

G32

DQ43

DQ44

H31

DQ44

DQ45

H28

DQ45

DQ46

J30

DQ46

DQ47

J28

DQ47

DQ48

W28

DQ48

DQ49

Y31

DQ49

DQ50

Y28

DQ50

DQ51

AA30

DQ51

DQ52

AA28

DQ52

DQ53

AB31

DQ53

DQ54

AB28

DQ54

DQ55

AC30

DQ55

DQ56

AC28

DQ56

DQ57

AD31

DQ57

DQ58

AD28

DQ58

DQ59

AE30

DQ59

DQ60

AE28

DQ60

DQ61

AF31

DQ61

DQ62

AF28

DQ62

DQ63

AH32

DQ63

12

24

R37

1/10W 5%

1 2 3 4 5 6 7 8

SDRAM {05,06}

DCLKOUT

SCB7

DCLKOUT

E21

A22

SCB6

U15

DCLKIN

SCB3

SCB4

SCB5

i960RN

MEMORY CONTROLLER

SA10

SA11

T32

R28

SA11 SCB4

SA10 SCB3

21

18pF

SCB2

SA9

R29

SA9 SCB2

C110

CAP0805

SCB1

SA8

R30

SA8 SCB1

SCB0

SA7

R32

SA7 SCB0

D20

A20

ROE

RWE

SA4

SA5

SA6

P31

P30

P28

SA6

SA5 ROE#

SA4 RWE#

A

C19

RCE0

SA3

P32

SA3 RCE0#

E19

RCE1

SA2

N28

SA2 RCE1#

B19

RALE

SA1

N29

SA1 RALE

ONCE#

C21

D18

E18

A19

ONCE

RAD14

RAD15

RAD16

SBA0

SBA1

SA0

SRAS

T31

T30

N30

N32

SA0

SBA0 RAD16

SBA1 RAD15

SRAS# RAD14

B

C18

RAD13

SCAS

L30

SCAS# RAD13

A18

RAD12

SWE

L32

SWE# RAD12

E17

RAD11

SCE0

M30

SCE0# RAD11

RAD9 RCE1#

E15

C15

RAD9

RAD10

SCKE0

SCE1

T28

M28

SCE1# RAD10

12

R50

SCKE0 {06,11}

RAD8

RAD7

D14

E14

A15

RAD7

RAD8

SCKE1

U32

V32

SM7 RAD6/RST_MODE#

22

R51

1/10W 5%

C13

E13

A14

C14

RAD5

RAD3/RETRY

RAD4/STEST

RAD6/RST_MODE#

RAD2/32BITMEM_EN#

SDQM3

SDQM4

SDQM5

SDQM6

SDQM7

L28

U28

U29

M31

SM6 RAD5

SM5 RAD4/STEST

SM4 RAD3/RETRY

SM3 RAD2/32BITMEM_EN#

12

22

1/10W 5%

SCKE1 {06,11}

B13

A13

RAD0

RAD1/32BITPCI_EN#

SDQM0

SDQM1

SDQM2

L29

U30

M32

SM1 RAD0

SM0

C

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

D22

DQ0

A23

DQ1

C23

DQ2

A24

DQ3

D24

DQ4

A25

DQ5

C25

DQ6

A26

DQ7

E26

DQ8

B27

DQ9

E27

DQ10

C28

DQ11

H32

DQ12

H30

DQ13

J32

DQ14

J29

DQ15

W29

DQ16

Y32

DQ17

Y30

DQ18

AA32

DQ19

AA29

DQ20

AB32

DQ21

AB30

DQ22

AC32

DQ23

AC29

DQ24

AD32

DQ25

AD30

DQ26

AE32

DQ27

AE29

DQ28

AF32

DQ29

AF30

DQ30

AG32

DQ31

RAD6/RST_MODE#

876

SWDIP4

123

876

RNC4R8P

1

RAD3/RETRY

RAD1/32BITPCI_EN#

RAD2/32BITMEM_EN#

5

S1

4

54

3

2

1.5K

R13

1 2 3 4 5 6 7 8

D

A

B

C

D

BREV

3

OUTA6OUTB

1488

IN1A4IN1B5IN2B9IN3A10IN3B12IN4A13IN4B

2

+5V

16C550

13

36

TXD

D7

CONNJ6-6P

12354

8

OUTC11OUTD

37

RTS

DTR38OP135OP2

J7

6

470

R15

3 2 1

RNC4R8P

U5

U6

1

2

3

1489A

+5V

11

40

41

CTS

RXD

DSR

A2

2D03D14D25D36D47D58D69

4

U7

42

43

RI

CD

31A030A129

10

RXCLK

+5V

5

1489A

17

BAUDOUT

CS2

16

U7

6

18

32

27

19

XTAL1

XTAL2

TXRDY

RXRDY

CS015CS125IOR21IOW39RST

IOR20IOW

14

24

74ALS04

9 8

+5V

33

26

INT

DDIS

U12

AS

28

470

R16

3 2 1

RNC4R8P

21Q52Q63Q94Q125Q156Q167Q19

74ABT273

31D42D73D8

RAD9 LED0

RAD10 LED1

CR1

21

CR1

5 4

43

6

CR1

7

65

8

CR1

87

CR2

21

5 4

CR2

43

6 7

CR2

65

8

CR2

87

4D135D146D177D188D11CLK1CLR

RAD11 LED2

RAD12 LED3

RAD13 LED4

RAD14 LED5

RAD15 LED6

LED4SM

8Q

RAD16 LED7

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

U3

9

SPARES

1489A

+5V

21

CR3

LED RED

12

R17

1/10W 5%

U6

5 6

10

8

470

74ALS04

13

U7

12

11

1489A

RAM3V {01,06,11}

21

CR4

LED GREEN LP

12

R18

1.6K

1/10W 5%

U7

P33V {01,02,08,09}

21

CR5

LED GREEN

12

R19

330

1/10W 5%

Sheet of

4/14/98 04 11

FLASH ROM, UART, & LEDS

80960RN

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

5

O

OSC1.8432MHz

E/D

1

RAD16

RAD15

RAD14

RAD13

RAD12

RAD11

RAD10

SELUART# {03}

U4

ROMA {03}

191Q182Q173Q164Q155Q146Q137Q12

74ABT573

21D32D43D54D65D76D87D9

IOR# {03}

8Q

8D11LE1OC

U6

74ALS04

1 2

IOW# {03}

I_RST# {05,07} IRQUART# {07}RAD6/RST_MODE# ROMA20

191Q182Q173Q164Q155Q146Q137Q12

U1

74ABT573

21D32D43D54D65D76D87D9

+12V

11

VPP

E28F016S5

A20

40

ROMA20

36

ROMA19

ROMA18

RY/BY

ROMA17

8Q

8D11LE1OC

I_RST# {05,07}

12

RP

ROMA16

ROMA15

ROMA14

U2

ROMA13

ROMA12

14

ROMA11

ROMA10

A1013A118A127A136A145A154A163A172A181A19

A9

ROMA9

RAD8

SEL_LED# {03}

RAD7

RAD5

RAD4/STEST

RAD6/RST_MODE#

D7

21A320A419A518A617A716A815

RAD3/RETRY RAD16

A2

22

RAD2/32BITMEM_EN# RAD15

+5V

A1

RAD1/32BITPCI_EN# RAD14

24A023

RAD0 RAD13

RAD12

R59 1 2

10K

U6

3 4

WE

38

RWE# RAD11

1/10W 5%

Z4

FAIL# {07}

25D026D127D228D332D433D534D635

CE37OE

9

ROE# RAD9

1 2

RCE0# RAD10

74ALS04

U11

JUMP1X2

RAD9 ROMA9

RAD12 ROMA12

RAD11 ROMA11

RAD10 ROMA10

RALE

RAD5 ROMA19

RAD4/STEST ROMA18

RAD3/RETRY ROMA17

B

RAD16 ROMA16 RAD9

RAD15 ROMA15 RAD2/32BITMEM_EN#

RAD14 ROMA14 RAD1/32BITPCI_EN#

RAD13 ROMA13 RAD0

1 2 3 4 5 6 7 8

RAD {03,05}

A

RALE

1 2 3 4 5 6 7 8

C

D

A

B

C

D

BREV

MICTOR

CLK0

39

GND140GND241GND342GND443GND5

SCE1#

SBA1

CLK1

36

RALE

CLK1

36

SBA0

LOGIC_CLK {02}

CLK1

36

I_RST# {04,07}

SGNT5#

SGNT4#

SGNT3#

SGNT2#

SPCI {07,08,09,10}

SGNT1#

SGNT0#

2524232221

39

GND140GND241GND342GND443GND5

2524232221

SREQ5#

SREQ4#

39

GND140GND241GND342GND443GND5

2524232221

4

563

789

10

11121314151617181935343332313029282726

4

563

789

10

11121314151617181935343332313029282726

SCE0#

4

563

789

10

11121314151617181935343332313029282726

SREQ3#

SREQ2#

20

SREQ1#

SREQ0#

J8

20

J10

J12

20

Sheet of

4/14/98 05 11

LOGIC ANALYZER I/F

80960RN

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

39

DQ40 SA8 DQ56

DQ39 SA7 DQ55 RWE#

DQ38 SA6 DQ54 ROE#

GND140GND241GND342GND443GND5

2524232221

39

GND140GND241GND342GND443GND5

2524232221

DQ37 SA5 DQ53 RCE1#

DQ36 SA4 DQ52 RCE0#

MICTOR

CLK0

DRAMCLK_LA {03}

MICTOR

CLK0

4

DQ15 SM7 DQ31 RAD15

563

DQ14 SM6 DQ30 RAD14

DQ13 SM5 DQ29 RAD13

DQ3 SCB3 DQ19 RAD3/RETRY

DQ2 SCB2 DQ18 RAD2/32BITMEM_EN#

DQ1 SCB1 DQ17 RAD1/32BITPCI_EN#

DQ0 SCB0 DQ16 RAD0

CLK1

36

CLK1

36

DQ47 SWE# DQ63

789

10

11121314151617181935343332313029282726

789

10

11121314151617181935343332313029282726

DQ9 SM1 DQ25 RAD9

DQ8 SM0 DQ24 RAD8

DQ7 SCB7 DQ23 RAD7

DQ6 SCB6 DQ22 RAD6/RST_MODE#

DQ5 SCB5 DQ21 RAD5

DQ12 SM4 DQ28 RAD12

DQ11 SM3 DQ27 RAD11

DQ10 SM2 DQ26 RAD10

DQ4 SCB4 DQ20 RAD4/STEST

DQ46 SCAS# DQ62

DQ45 SRAS# DQ61

DQ44 DQ60

DQ43 SA11 DQ59

DQ42 SA10 DQ58

DQ41 SA9 DQ57

1 2 3 4 5 6 7 8

SDRAM {03,06} RAD {03,04}

A

B

C

DQ35 SA3 DQ51 RALE

DQ34 SA2 DQ50

DQ33 SA1 DQ49

J11

20

J9

20

DQ32 SA0 DQ48 RAD16

1 2 3 4 5 6 7 8

D

A

B

C

D

BREV

Sheet of

SDRAM 168-PIN DIMM

4/14/98 06 11

80960RN

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

SCKE0 {03,11}

136

128

129

127

130M6131

132

M7

CS3

NC5

CKE0

GND5

SDRAM-DIMM168P

GND1

85

43

GND5

SDRAM-DIMM168P

GND1

1

VCC1

DQ3287DQ3388DQ3489DQ3591DQ3692DQ3793DQ3894DQ3995DQ4097DQ4198DQ4299DQ43

90

86

45

46M247

44

M3

CS2

NC448NC550NC651NC7

VCC1

DQ03DQ1

DQ2

DQ3

6

2

4

5

DQ0 DQ32

DQ1 SCE0# DQ33 SCE1#

DQ2 SM2 DQ34 SM6

DQ3 SM3 DQ35 SM7

137

134

135

133

CB6

CB7

NC6

NC7

VCC5

52

49

CB253CB3

VCC6

DQ6

DQ48DQ510DQ711DQ813DQ9

9

7

DQ4 DQ36

DQ5 DQ37

DQ6 DQ38

DQ7 SCB2 DQ39 SCB6

DQ8 SCB3 DQ40 SCB7

138

139

140

141

DQ48

DQ49

DQ50

GND6

GND2

96

54

55

DQ1656DQ1757DQ1858DQ19

GND6

GND2

DQ1015DQ1116DQ1217DQ1319DQ1420DQ15

12

14

DQ9 DQ16 DQ41 DQ48

DQ10 DQ17 DQ42 DQ49

DQ11 DQ18 DQ43 DQ50

142

100

DQ12 DQ19 DQ44 DQ51

DQ51

DQ44

143

101

59

DQ13 DQ45

VCC6

DQ45

VCC7

144

102

DQ20 DQ52

60

18

DQ52

VCC2

DQ20

VCC2

148

147

145

146

149

NC8

DQ46

103

61

NC862NC9

DQ14 DQ46

150

NC9

NC10

DQ53

DQ54

GND7

CB4

CB5

GND3

NC1

DQ47

105

106

107

108

104

SCB4

DQ21 DQ53

DQ22 DQ54

SCKE1 {03,11}

63

64

65

DQ2166DQ2267DQ2369DQ2470DQ2571DQ2672DQ2774DQ2875DQ29

CKE1

GND768GND8

CB022CB1

GND3

NC1

21

23

24

DQ15 DQ47

SCB0

SCB1 SCB5

151

109

DQ23 DQ55

25

DQ55

NC2

DCLK3 {03}

152

110

26

GND8

VCC3

153

111

27

SWE# DQ24 SCAS# DQ56

DQ56

CAS

WE

154

DQ57

112M4113

28M029

SM0 DQ25 SM4 DQ57

155

SM1 DQ26 SM5 DQ58

DQ58

M5

M1

156

DQ59

CS1

114

CS0

30

SCE0# DQ27 SCE1# DQ59

157

VCC7

RAS

115

SRAS#

73

VCC8

NC3

31

158

116

DQ28 DQ60

32

DQ60

GND4

162

159

160

161

DQ61

DQ62

DQ63

GND9

A1

117

118A3119A5120A7121A9122

78

76

DQ3077DQ31

GND9

A0

33

34A235A436A637A839

SA0 DQ29 SA1 DQ61

SA2 DQ30 SA3 DQ62

SA4 DQ31 SA5 DQ63

SA6 SA7

163

164

CLK3

NC11

BA0

SA9

DCLK2 {03}

79

80

CLK2

NC1081NC11

A10

38

SA8

SA10 SBA0

165

123

SBA1 SA11

SA0

A11

BA1

166

167

SA1

SA2

CLK1

VCC4

125

124

SDA {03,07}

SCL {03,07} DCLK1 {03}

83

82

SCL

SDA

VCC441VCC5

40

168

VCC8

J5

NC4

126

84

VCC9

J5

CLK0

42

DCLK0 {03}

SDRAM {03,05}

RAM3V {01,04,11}

1 2 3 4 5 6 7 8

A

B

C

D

1 2 3 4 5 6 7 8

A

+3V

SDA {03,06}

SCL {03,06}SGNT2# SFRAME#

B

RNC4R8P

876

2

1

C8

A8

SCL

SDA

C

I_RST# {04,05}

54

2.7K

R36

3

C12

A12

C11

E11

TDI

TCK

TDO

TRST

JTAG HEADER

B11

A21

A11

TMS

I_RST

LCDINIT

10

2

J6

1

3 4

5 6

7 8

HEAD16SH

9

11 12

13 14

15 16

R14 1 2

1/10W 5%

1.5K

D

BREV

Sheet of

4/14/98 07 11

SECONDARY PCI/960 CORE

80960RN

Title:

Name:

Date:

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

SAD32 SAD33 SAD34 SAD35 SAD36 SAD37 SAD38 SAD39 SAD40 SAD41 SAD42 SAD43 SAD44 SAD45 SAD46 SAD47 SAD48 SAD49 SAD50 SAD51 SAD52 SAD53 SAD54 SAD55 SAD56 SAD57 SAD58 SAD59 SAD60 SAD61 SAD62 SAD63

+5V

RNC4R8P

AH1 AH3 AH4 AJ2 AJ5 AK5 AM5 AH6 AK6 AL6 AM6 AH7 AJ7 AK7 AM7 AH8 AK8 AL8 AM8 AH9 AJ9 AK9 AM9 AH10 AK10 AL10 AM10 AH11 AJ11 AK11 AM11 AH12

876

SC/BE0#

AH17

S_AD32 S_AD33 S_AD34 S_AD35 S_AD36 S_AD37 S_AD38 S_AD39 S_AD40 S_AD41 S_AD42 S_AD43 S_AD44 S_AD45 S_AD46 S_AD47 S_AD48 S_AD49 S_AD50 S_AD51 S_AD52 S_AD53 S_AD54 S_AD55 S_AD56 S_AD57 S_AD58 S_AD59 S_AD60 S_AD61 S_AD62 S_AD63

54

321

SC/BE1#

AJ19

AM21

AH24

S_C/BE0

S_C/BE1

S_C/BE2

S_C/BE3

U15

i960RN

SECONDARY PCI SIGNALS

S_REQ0

S_REQ1

AL26

AH27

R3

AL12

S_C/BE4

S_REQ2

AK27

2.7K

AM12

S_C/BE5

S_REQ3

AH28

RNC4R8P

AH13

AJ13

S_C/BE6

S_C/BE7

S_REQ4

S_REQ5

AL28

AJ29

876

AK13

S_REQ64

S_GNT0

AM26

321

AM13

AK21

S_ACK64

S_GNT1

AJ27

AM27

54

AJ21

S_IRDY

S_FRAME

S_GNT2

S_GNT3

AK28

AH21

S_TRDY

S_GNT4

AM28

R44

AL20

S_STOP

S_GNT5

AK29

U15

i960RN

2.7K

S_INTA/XINT0C9S_INTB/XINT1E9S_INTC/XINT2

B9

SINTA#

SINTB#

SDEVSEL#

AM20

AM19

AK26

S_RST

S_SERR

S_DEVSEL

S_PAR

S_PAR64

AK19

AK12

JX CORE/I2C/JTAG

S_INTD/XINT3

XINT4

XINT5

A10

C10

D10

SINTC#

SINTD#

IRQFAN# {11}

IRQUART# {04}

SPERR#

SLOCK#

AK20

AH20

S_LOCK

S_PERR

VCC5REF

VCCPLL1

VCCPLL2

AH14 AK14

AL14

AM14 AH15

AJ15

AK15 AM15

AJ17

AK17 AM17 AH18 AK18

AL18

AM18 AH19 AH22 AK22

AL22

AM22 AH23

AJ23

AK23 AM23 AK24

AL24

AM24 AH25

AJ25

AK25 AM25 AH26

VCCPLL3

E20

C22

B15

D26

C57

21

CAPT7343

4.7uF

C61

21

CAP0805

0.01uF

12

10

R30

1/8W 5%

SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 SAD7 SAD8 SAD9

SAD10 SAD11 SAD12 SAD13 SAD14 SAD15 SAD16 SAD17 SAD18 SAD19 SAD20 SAD21 SAD22 SAD23 SAD24 SAD25 SAD26 SAD27 SAD28 SAD29 SAD30 SAD31

C76

21

12

R52

100

1/2W 5%

+5V

+3V

CAPT7343

4.7uF

C77

21

CAP0805

0.01uF

12

R43

10

1/8W 5%

C92

21

CAPT7343

4.7uF

C96

21

CAP0805

0.01uF

12

R56

10

1/8W 5%

NMI

FAIL

A9

E12

FAIL# {04}

S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_AD8 S_AD9 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 S_AD27 S_AD28 S_AD29 S_AD30 S_AD31

1 2 3 4 5 6 7 8

SPCI {05,08,09,10}

SREQ0# SC/BE2#

SREQ1# SC/BE3#

SREQ2# SC/BE4#

SREQ3# SC/BE5#

SREQ4# SC/BE6#

SREQ5# SC/BE7#

SGNT0# SREQ64#

SGNT1# SACK64#

SGNT3# SIRDY#

SGNT4# STRDY#

SGNT5# SSTOP#

SPAR SSERR#

SPAR64 SRST#

1 2 3 4 5 6 7 8

A

B

C

D

A

SPCI CONN 1

B

C

SPCI CONN 2

D

BREV

Sheet of

SECONDARY PCI BUS 1/2

4/14/98 08 11

80960RN

Title:

Name:

Date:

+5V +5V

SC/BE7#

A63

A64

GND1

C/BE7

CONNPCI_64

GND9

B64

B63

CONNPCI_64

A66

A67

A65

+5V1

C/BE5

PAR64

GND10

C/BE4

C/BE6

B67

B66

B65

SC/BE4#

P33V {01,02,04,09}

SFRAME# SPAR64

A33

A32

A34

+3V1

AD16

FRAME

AD17

GND6

C/BE2

B32

B34

B33

A68

B68

A35

B35

AD62

AD63

GND1

IRDY

A69

GND2

AD61

B69

STRDY# SAD61

A36

TRDY

+3V5

B36

A70

AD60

+5V4

B70

A37

GND2

DEVSEL

B37

A71

B71

A38

B38

AD58

AD59

STOP

GND7

A72

B72

A39

B39

GND3

AD57

+3V2

LOCK

A73

AD56

GND11

B73

A40

SDONE

PERR

B40

A74

AD54

AD55

B74

SAD55 SAD54

A41

SBO

+3V6

B41

A75

B75

A42

B42

+5V2

AD53

GND3

SERR

A76

AD52

GND12

B76

SPAR SAD52

A43

PAR

+3V7

B43

A77

B77

A44

B44

AD50

AD51

AD15

C/BE1

A78

B78

A45

B45

GND4

AD49

+3V3

AD14

A79

B79

A46

B46

AD48

+5V5

AD13

GND8

SAD56

A84

A86

A85

A83

A82

A80

A81

+5V3

AD38

AD40

AD42

AD44

AD46

GND5

AD39

AD41

AD43

AD45

AD47

GND13

GND14

B86

B84

B83

B81

B80

B82

B85

SAD43 SAD42

A53

A49

A47

A48

A52

+3V4

AD09

AD11

GND4

C/BE0

AD07

AD08

AD10

AD12

GND9

B53

B52

B48

B47

B49

A87

B87

A54

B54

GND6

AD37

AD06

+3V8

A91

A89

A88

A90

A93

A92

A94

AD32

AD34

AD36

GND7

GND8

J1

+5V6

AD33

AD35

GND15

B90

A57

AD02

GND10

B57

GND16

B91

B94

B92

B93

A59

A61

A58

A60

+5V1

+5V2

AD00

REQ64

+5V4

+5V5

AD01

ACK64

B59

B61

B58

B60

B88

B89

A55

A56

AD04

GND5

AD03

AD05

B56

B55

A63

CONNPCI_64

B63

A62

+5V3

J1

+5V6

B62

A65

A64

GND1

C/BE5

C/BE7

GND9

C/BE6

B64

B65

SC/BE6# SC/BE5#

P33V {01,02,04,09}

A33

A32

+3V1

AD16

CONNPCI_64

AD17

C/BE2

B32

B33

A66

A67

+5V1

C/BE4

B67

B66

SFRAME# SC/BE4#

A35

A34

FRAME

GND6

B34

B35

PAR64

GND10

GND1

IRDY

A68

AD62

AD63

B68

STRDY# SAD63 SAD62

A36

TRDY

+3V5

B36

A69

GND2

AD61

B69

A37

GND2

DEVSEL

B37

A70

B70

A38

B38

AD60

+5V4

STOP

GND7

A71

B71

A39

B39

AD58

AD59

+3V2

LOCK

A72

GND3

AD57

B72

A40

SDONE

PERR

B40

A73

AD56

GND11

B73

A41

SBO

+3V6

B41

A75

A77

A76

A74

+5V2

AD50

AD52

AD54

AD51

AD53

AD55

GND12

B77

B75

B74

B76

SPAR SAD53

A45

A44

A42

A43

PAR

+3V3

AD15

GND3

+3V7

AD14

C/BE1

SERR

B43

B45

B44

B42

A78

B78

A46

B46

GND4

AD49

AD13

GND8

A79

B79

A47

B47

AD48

+5V5

AD11

AD12

SAD44

A84

A83

A82

A80

A81

+5V3

AD42

AD44

AD46

GND5

AD41

AD43

AD45

AD47

GND13

B84

B83

B81

B80

B82

A49

A48

A52

AD09

GND4

C/BE0

AD08

AD10

GND9

B52

B48

B49

A85

AD40

GND14

B85

A53

+3V4

AD07

B53

A89

A88

A86

A87

AD36

AD38

GND6

+5V6

AD37

AD39

B88

B89

B87

B86

A57

A55

A54

A56

AD04

AD06

GND5

+3V8

AD03

AD05

B54

B56

B55

B57

A90

AD34

AD35

B90

A58

AD02

GND10

B58

GND7

AD33

AD00

AD01

A91

B91

A59

B59

AD32

GND15

+5V1

+5V4

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

A93

A92

A94

GND8

J2

GND16

B94

B92

B93

A61

A62

A60

+5V2

+5V3

REQ64

J2

+5V5

+5V6

ACK64

B61

B62

B60

1 2 3 4 5 6 7 8

SPCI {05,07,09,10}

+12V

N12V

+5V +5V +5V +5V

SAD17 SAD16 SC/BE6# SC/BE5#

SC/BE2#

STRST# {09,10}

A2

A1

+12V

TRST

CONNPCI_64

-12V

TCK

B1

B2

STCK {09,10}

A

SIRDY# SAD63 SAD62

STMS {09,10}

STDI {09,10}

A5

A4

A3

TDI

TMS

GND6

TDO

B5

B3

B4

SPERR# SAD56

P33V {01,02,04,09}

SINTA# SDEVSEL# SAD60

A9

A6

A7

INTA

INTC

+5V1A8+5V2

+5V5B6+5V6

INTB

INTDB9PRSNT1

B7

B8

SINTB# SINTC# SSTOP# SAD59 SAD58

SINTD# SLOCK# SAD57

C26

2 1

SSERR# SAD53

A10

A11

+5V3

B10

B11

0.01uF

CAP0805

A12

PRSNT2

B12

C27

GND1

GND7

2 1

SC/BE1# SAD15 SAD51 SAD50

A13

GND2

GND8

B13

SAD14 SAD49

A14

B14

0.01uF

CAP0805

SRST# SAD13 SAD48

A15

RST

GND9

B15

SAD12 SAD11 SAD47 SAD46

SGNT0# SAD10 SAD45

A16

A17

+5V4

CLK

B16

B17

CLKA {02}

GNT

GND10

A18

GND3

REQ

B18

SREQ0# SAD9 SAD44

A20

A19

AD30

+5V7

AD31

B19

B20

SAD31 SAD30 SAD41

SAD8 SC/BE0# SAD40

P33V {01,02,04,09}

SAD28 SAD7 SAD39 SAD38

A21

A23

A22

+3V1

AD26

AD28

AD27

AD29

GND11

B23

B21

B22

SAD29

SAD27 SAD26 SAD6 SAD37

B

SAD24 SAD3 SAD35 SAD34

A25

A24

A26

AD24

GND4

IDSEL

+3V3

AD25

C/BE3

B25

B24

B26

SAD25 SAD5 SAD4 SAD36

SC/BE3# SAD16 SAD2 SAD33

P33V {01,02,04,09}

A27

+3V2

AD23

B27

SAD23 SAD1 SAD0 SAD32

SAD22

A28

AD22

GND12

B28

A29

A30

AD20

GND5

AD19

AD21

B30

B29

SAD21 SAD20 SACK64# SREQ64#

SAD19

SAD18

A31

AD18

+3V4

B31

+12V

J1

CONNPCI_64

N12V

SAD17 SAD16 SC/BE7#

SC/BE2#

STRST# {09,10}

STMS {09,10}

A2

A3

A1

TMS

+12V

TRST

-12V

GND6

TCK

B1

B3

B2

STCK {09,10}

SIRDY# SPAR64

P33V {01,02,04,09}

STDI {09,10}

SINTB# SDEVSEL# SAD61

A5

A4

A6

TDI

INTA

+5V1A8+5V2

+5V5B6+5V6

TDO

B5

B4

C

A7

INTC

INTB

B7

SINTC# SINTD# SSTOP# SAD60

SPERR# SAD57

A9

INTDB9PRSNT1

B8

SINTA# SLOCK# SAD59 SAD58

C18

2 1

SSERR# SAD55 SAD54

A10

A11

+5V3

B10

B11

0.01uF

CAP0805

A12

GND1

GND7

PRSNT2

B12

C19

2 1

SC/BE1# SAD15 SAD52

A13

GND2

GND8

B13

CAP0805

SAD14 SAD51 SAD50

A14

B14

0.01uF

SRST# SAD13 SAD49

A15

RST

GND9

B15

SAD12 SAD11 SAD48

SGNT1# SAD10 SAD47 SAD46

A16

A17

+5V4

CLK

B16

B17

CLKB {02}

A18

GNT

GND10

B18

SREQ1# SAD9 SAD45

GND3

REQ

SAD28 SAD7 SAD40

SAD24 SAD3 SAD36

SAD22 SAD32

SAD18

A21

A22

A20

A19

+3V1

AD28

AD30

+5V7

AD29

AD31

GND11

B19

B21

B20

B22

SAD31 SAD30 SAD43 SAD42

SAD29 SAD8 SC/BE0# SAD41

A23

AD26

AD27

B23

SAD27 SAD26 SAD6 SAD39 SAD38

A24

GND4

AD25

B24

SAD25 SAD5 SAD4 SAD37

A27

A31

A29

A28

A25

AD24

+3V3

B25

A26

IDSEL

C/BE3

B26

SC/BE3# SAD17 SAD2 SAD35 SAD34

+3V2

AD23

B27

SAD23 SAD1 SAD0 SAD33

B28

AD22

GND12

B29

SAD21 SAD20 SACK64# SREQ64#

AD20

AD21

A30

GND5

AD19

B30

SAD19

AD18

J2

+3V4

B31

1 2 3 4 5 6 7 8

D

A

SPCI CONN 3

B

C

SPCI CONN 4

D

BREV

Sheet of

SECONDARY PCI BUS 3/4

4/14/98 09 11

80960RN

Title:

Name:

Date:

+5V +5V

SC/BE7#

A63

A64

GND1

C/BE7

CONNPCI_64

GND9

B64

B63

CONNPCI_64

A66

A67

A65

+5V1

C/BE5

PAR64

GND10

C/BE4

C/BE6

B67

B66

B65

SC/BE4#

P33V {01,02,04,08}

SFRAME# SPAR64

A33

A32

A34

+3V1

AD16

FRAME

AD17

GND6

C/BE2

B32

B34

B33

A68

B68

A35

B35

AD62

AD63

GND1

IRDY

A69

GND2

AD61

B69

STRDY# SAD61

A36

TRDY

+3V5

B36

A71

A70

AD60

+5V4

B70

B71

A37

A38

GND2

DEVSEL

B38

B37

AD58

AD59

STOP

GND7

SAD56

A66

A70

A65

A64

+5V1

C/BE5

C/BE7

GND9

C/BE4

C/BE6

B64

B66

B65

SC/BE6# SC/BE5#

P33V {01,02,04,08}

SFRAME# SC/BE4#

A33

A32

A34

+3V1

AD16

FRAME

AD17

GND6

C/BE2

B32

B34

B33

A67

PAR64

GND10

B67

A35

GND1

IRDY

B35

A68

AD62

AD63

B68

STRDY# SAD63 SAD62

A36

TRDY

+3V5

B36

A69

GND2

AD61

B69

A37

GND2

DEVSEL

B37

B70

A38

B38

AD60

+5V4

STOP

GND7

A75

A79

A77

A76

A74

A73

A72

AD56

GND3

AD57

GND11

B72

B73

A39

A40

+3V2

SDONE

LOCK

PERR

B39

B40

AD54

AD55

B74

SAD55 SAD54

A41

SBO

+3V6

B41

B75

A42

B42

+5V2

AD53

GND3

SERR

AD52

GND12

B76

SPAR SAD52

A43

PAR

+3V7

B43

B77

A44

B44

AD50

AD51

AD15

C/BE1

A78

B78

A45

B45

GND4

AD49

+3V3

AD14

B79

A46

B46

AD48

+5V5

AD13

GND8

A84

A86

A85

A83

A82

A80

A81

+5V3

AD38

AD40

AD42

AD44

AD46

GND5

AD39

AD41

AD43

AD45

AD47

GND13

GND14

B86

B84

B83

B81

B80

B82

B85

SAD43 SAD42

A53

A49

A47

A48

A52

+3V4

AD09

AD11

GND4

C/BE0

AD07

AD08

AD10

AD12

GND9

B53

B52

B48

B47

B49

A87

B87

A54

B54

GND6

AD37

AD06

+3V8

A88

B88

A55

B55

AD36

+5V6

AD04

AD05

A89

B89

A56

B56

AD34

AD35

GND5

AD03

A90

GND7

AD33

B90

A57

AD02

GND10

B57

A91

AD32

GND15

B91

A58

AD00

AD01

B58

A63

A93

A92

A94

GND1

GND8

J3

CONNPCI_64

GND16

B63

B94

B92

B93

A59

A61

A62

A60

+5V1

+5V2

+5V3

REQ64

J3

CONNPCI_64

+5V4

+5V5

+5V6

ACK64

B59

B61

B62

B60

A71

B71

A39

B39

AD58

AD59

+3V2

LOCK

A72

GND3

AD57

B72

A40

SDONE

PERR

B40

A73

B73

A41

B41

A74

AD56

GND11

B74

A42

SBO

+3V6

B42

AD54

AD55

GND3

SERR

A75

+5V2

AD53

B75

SPAR SAD53

A43

PAR

+3V7

B43

A76

B76

A44

B44

A77

AD52

GND12

B77

A45

AD15

C/BE1

B45

AD50

AD51

+3V3

AD14

A78

B78

A46

B46

GND4

AD49

AD13

GND8

SAD44

A84

A83

A82

A80

A79

A81

+5V3

AD42

AD44

AD46

AD48

GND5

+5V5

B79

A47

AD11

AD12

B47

B80

A48

B48

AD47

GND4

AD10

B81

A49

B49

AD45

AD09

GND9

B82

GND13

B83

AD43

B84

A52

B52

AD41

C/BE0

AD08

A85

AD40

GND14

B85

A53

+3V4

AD07

B53

A89

A88

A86

A87

AD34

AD36

AD38

GND6

+5V6

AD35

AD37

AD39

B88

B89

B87

B86

A57

A55

A54

A56

AD02

AD04

AD06

GND5

+3V8

AD03

AD05

GND10

B54

B56

B55

B57

A90

B90

A58

B58

GND7

AD33

AD00

AD01

A91

AD32

GND15

B91

A59

+5V1

+5V4

B59

A92

B92

A60

B60

REQ64

ACK64

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

A93

A94

GND8

J4

GND16

B94

B93

A61

A62

+5V2

+5V3

J4

+5V5

+5V6

B61

B62

1 2 3 4 5 6 7 8

SPCI {05,07,08,10}

+12V

+5V N12V +5V +5V +5V

SAD17 SAD16 SC/BE6# SC/BE5#

SC/BE2#

STRST# {08,10}

A2

A1

+12V

TRST

CONNPCI_64

-12V

TCK

B1

B2

STCK {08,10}

A

SIRDY# SAD63 SAD62

STMS {08,10}

STDI {08,10}

A5

A4

A3

TDI

TMS

GND6

TDO

B5

B3

B4

SPERR# SAD56

P33V {01,02,04,08}

SINTC# SDEVSEL# SAD60

A9

A6

A7

INTA

INTC

+5V1A8+5V2

+5V5B6+5V6

INTB

INTDB9PRSNT1

B7

B8

SINTB# SLOCK# SAD57

SINTD# SINTA# SSTOP# SAD59 SAD58

C10

2 1

SSERR# SAD53

A10

A11

+5V3

B10

B11

0.01uF

CAP0805

A12

GND1

GND7

PRSNT2

B12

C11

2 1

SC/BE1# SAD15 SAD51 SAD50

A13

GND2

GND8

B13

CAP0805

SAD14 SAD49

A14

B14

0.01uF

SRST# SAD13 SAD48

A15

RST

GND9

B15

SAD12 SAD11 SAD47 SAD46

SGNT2# SAD10 SAD45

A16

A17

+5V4

CLK

B16

B17

CLKC {02}

A18

GNT

GND10

B18

SREQ2# SAD9 SAD44

GND3

REQ

A19

B19

+5V7

A20

AD30

AD31

B20

SAD31 SAD30 SAD41

SAD8 SC/BE0# SAD40

A21

B21

SAD29

B

P33V {01,02,04,08}

SAD28 SAD7 SAD39 SAD38

SAD24 SAD3 SAD35 SAD34

A25

A23

A22

A24

+3V1

AD26

AD28

GND4

AD25

AD27

AD29

GND11

B25

B24

B23

B22

SAD27 SAD26 SAD6 SAD37

SAD25 SAD5 SAD4 SAD36

SAD22

A27

A29

A28

A26

+3V2

AD22

AD24

IDSEL

+3V3

AD23

GND12

C/BE3

B29

B27

B28

B26

SAD23 SAD1 SAD0 SAD32

SAD21 SAD20 SACK64# SREQ64#

SC/BE3# SAD18 SAD2 SAD33

P33V {01,02,04,08}

AD20

AD21

A30

GND5

AD19

B30

SAD19

SAD18

A31

AD18

J3

+3V4

B31

SAD17 SAD16 SC/BE7#

SC/BE2#

STRST# {08,10}

+12V

A2

A1

+12V

TRST

CONNPCI_64

-12V

TCK

B1

B2

N12V

STCK {08,10}

SIRDY# SPAR64

STMS {08,10}

STDI {08,10}

A4

A3

TDI

TMS

GND6

TDO

B3

B4

P33V {01,02,04,08}

SINTD# SDEVSEL# SAD61

A5

A6

A7

INTA

INTC

+5V1A8+5V2

+5V5B6+5V6

INTB

INTDB9PRSNT1

B5

B7

B8

SINTA# SINTB# SSTOP# SAD60

SINTC# SLOCK# SAD59 SAD58

C

SPERR# SAD57

A9

2 1

A10

+5V3

B10

CAP0805

SSERR# SAD55 SAD54

A11

PRSNT2

B11

C3

A12

B12

GND1

GND7

2 1C20.01uF

SC/BE1# SAD15 SAD52

A13

GND2

GND8

B13

CAP0805

SAD14 SAD51 SAD50

A14

B14

0.01uF

SRST# SAD13 SAD49

A15

RST

GND9

B15

SAD12 SAD11 SAD48

SGNT3# SAD10 SAD47 SAD46

A16

A17

+5V4

CLK

B16

B17

CLKD {02}

GNT

GND10

A18

GND3

REQ

B18

SREQ3# SAD9 SAD45

SAD28 SAD7 SAD40

SAD24 SAD3 SAD36

SAD22 SAD32

SAD18

A21

A22

A20

A19

+3V1

AD28

AD30

+5V7

AD29

AD31

GND11

B19

B21

B20

B22

SAD31 SAD30 SAD43 SAD42

SAD29 SAD8 SC/BE0# SAD41

A23

AD26

AD27

B23

SAD27 SAD26 SAD6 SAD39 SAD38

A24

GND4

AD25

B24

SAD25 SAD5 SAD4 SAD37

A27

A31

A29

A28

A25

AD24

+3V3

B25

A26

IDSEL

C/BE3

B26

SC/BE3# SAD19 SAD2 SAD35 SAD34

+3V2

AD23

B27

SAD23 SAD1 SAD0 SAD33

AD22

GND12

B28

A30

AD20

GND5

AD19

AD21

B30

B29

SAD21 SAD20 SACK64# SREQ64#

SAD19

AD18

J4

+3V4

B31

1 2 3 4 5 6 7 8

D

A

876

54

876

B

876

54

C

876

D

BREV

Sheet of

SPCI PULL-UPS

4/14/98 10 11

80960RN

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

54

+5V +5V

+5V

RNC4R8P

876

SAD32 SAD52

SAD33 SAD53

876

321

SAD34 SAD54

54

SAD35 SAD55

R4

3

SAD46 SC/BE6#

54

SAD47 SC/BE7#

54

2.7K 12

R2

2.7K

1/10W 5%

876

54

321

SAD50

SAD51

2.7K

R8

54

2.7K

R9

RNC4R8P

SAD48 SPAR64

SAD49

876

R5

321

SAD42 SAD62

54

SAD43 SAD63

54

2.7K RNC4R8P

2

1

876

2.7K

R10

RNC4R8P

2

1

SAD44 SC/BE4#

SAD45 SC/BE5#

876

R6

3

SAD38 SAD58

54

SAD39 SAD59

2.7K RNC4R8P

876

2.7K

R11

RNC4R8P

SAD40 SAD60

SAD41 SAD61

54

876

R7

2.7K RNC4R8P

2

1

876

2.7K

R12

RNC4R8P

2

1

SAD36 SAD56

SAD37 SAD57

+5V

54

876

1 2 3 4 5 6 7 8

SPCI {05,07,08,09}

RNC4R8P

1

STMS

2

STDI

3

STRST#

STCK

321

SIRDY#

SDEVSEL#

2.7K

R45

RNC4R8P

2

1

SSTOP#

SSERR#

R1

2.7K RNC4R8P

STRDY#

SFRAME#

3

SPERR#

SLOCK#

2.7K

R38

RNC4R8P

SREQ0#

SREQ1#

321

SREQ2#

SREQ3#

2.7K

R33

RNC4R8P

SREQ4#

SREQ5#

321

SACK64#

SREQ64#

2.7K

R31

1 2 3 4 5 6 7 8

A

B

C

D

A

SCKE0 {03,06}

12F013F114F215F316F417F518F619

U19

1I02I13I24I35I46I57I68I79

PART # 101-1950-01

SCKE1 {03,06}

F7

I811I9

RST# {02}

RAM3V {01,04,06}

20

VCC

PALLV16V8Z-20JI

21

100uF

C56

C53

CAP0805

0.1uF

R21 1 2

1W 1%

0.05

CAPT7343H

76543

3 2 1

SI9430

4

B

7

Q1

6 5

RAM3V {01,04,06}

21

47uH L1

1 2

8

C63

33uF

330uF

C64

CR7

CAPT7343

CAPT7343H

MBRS340T3

1 2

C

SPARES

D

BREV

Sheet of

BATTERY/MONITOR

4/14/98 11 11

80960RN

Title:

Name:

13

U10

LM339

-

11+10

+5V

14

U10

9+8

LM339

-

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

6CS7

21

10uF

R26 1 2

68K

REF

4

C52

CAPT7343

BT6

BATT_HLDR 1

2

BT3

BATT_HLDR 1

2

TEMP

7

1/10W 5%

1

EXT

2FB8

BT2

BATT_HLDR

1 2

+

8

FASTCHG

TLO

6

11CC13

22K

OUT

U8

GND

BT7

BATT_HLDR

1 2

+

12

BATT-

GND

21 R34 1 2

1/10W 5%

C51

21

0.1uF

BT8

BATT_HLDR

1 2

BT1

BATT_HLDR

1 2

U14

C68

CAP0805

0.01uF

CAP0805

R28 1 2

1

1/10W 5%

R60 1 2

10

R27

1 2

1/10W 5%

1

1/10W 5%

IRQFAN# {07}

R47 1 2

1/10W 5%

2.4K

R32 1 2

1/10W 5%

CAP0805

0.047uF

1/10W 5%

1

U10

7+6

LM339

-

C47

21

CAPT7343

22uF

2

U10

LM339

-

5+4

NOTE: VCC FOR LM339 IS +5V

C65

21

CAP1206

0.47uF

R35

1 2

1/10W 5%

10K

R48

1 2

1/10W 5%

4.7K R24

1 2

1/10W 5%

100K

C58

R53

1 2

21

1/10W 5%

47K

+5V

FAN CONN

0.01uF

1

FAN

J13

GND3PWR

2

CAP0805

21

100K

C82

R49 1 2

4.7K

1 2 3 4 5 6 7 8

5

V+

BATTERY

MAX1651

SHDN

3

BT5

BATT_HLDR

1 2

+

CR8

12

2

Q4

1

2N6109

3

21

150

C55

R20 1 2

CAP0805

0.01uF

1/10W 5%

R25

1 2

1K

+12V

1/10W 5%

14

DRV

MAX712

THI

5

CMR1-02

V+

15

2

BATT+

21

1

1uF

VLIMIT

CAPT3216

C74

10uF

C54

BT4

BATT_HLDR

1 2

+

REF

16

CAPT7343

3

PGM04PGM19PGM210PGM3

1 2 3 4 5 6 7 8

A

B

C

D

Table B-2. IQ80960RM Schematics List

Page Schematic Title

B-14 Decoupling and 3.3V Power B-15 Primary PCI Interface B-16 Memory Controller B-17 Flash ROM, UART, & LEDs B-18 Logic Analyzer I /F B-19 SDRAM 168-Pin DIMM B-20 Secondary PCI/960 Core B-21 Secondary PCI Bu s 1/2 B-22 Secondary PCI Bu s 3/4 B-23 Battery/Monitor

Schematics

IQ80960RM/RN Evaluation Board Ma nual B-13

A

220uF

CAPT7343

21

+3V

NOTE: PINS 3-7 ARE VIAS

C86

21

0.1uF

CR9

2 3

CMPSH3

+5V

21

C60

CAPT7343

220uF

MAX767CAP

RFD16N05L

213

17

19

BST

VCC114VCC215VCC3

10

Q3

DH

34567

R46

1 2

COIL-SMT2

3.3uH L2

1 2

CAP0805

18

LX

ON/OFF#

3

21

0.012

1W 1%

CR6

Q2

RFD16N05L

213

16

DL

REF2SS9SYNC

8

C78

220uF

CAPT7343

C75

MBRS340T3 1 2

13

PGND

GND15GND26GND37GND411GND5

4

1

20

FB

CS

U17

B

C

D

BREV

1

TP1

Sheet of

4/14/98 01 10

80960RM

DECOUPLING & 3.3V POWER

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

R54 1 2

1/8W 5%

+5V

10

21

C88

4.7uF

CAPT7343

21

C84

0.22uF

CAP1206

21

C83

0.01uF

CAP0805

C40

C39

C38

C37

C36

C35

C34

C33

2 1

0.1uF

CAP0805

0.1uF

2 1

CAP0805

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

0.1uF

2 1

CAP0805

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

2 1

0.1uF

CAP0805

SDRAM DECOUPLING

RAM3V {04,06,10}

C91

2 1

CAPT7343

P33V {02,04,08,09}

SPCI DECOUPLING

C90

2 1

CAPT7343

+5V

47uF

C28

2 1

C32

2 1

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

2 1

CAP0805

C31

0.1uF

2 1

CAP0805

2 1

0.1uF

2 1

CAP0805

C24

C25

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

2 1

CAP0805

C23

0.1uF

2 1

CAP0805

2 1

0.1uF

2 1

CAP0805

C16

C17

2 1

0.1uF

2 1

CAP0805

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

2 1

CAP0805

C15

0.1uF

2 1

CAP0805

2 1

0.1uF

CAP0805

2 1

CAP0805

2 1C90.1uF

CAP0805

C14

C13

C12

C22

C21

C20

C30

C29

C6

0.1uF

2 1C50.1uF

2 1C40.1uF

2 1C80.1uF

CAP0805

C1

CAP0805

2 1C70.1uF

CAP0805

0.1uF

CAP0805

1 2 3 4 5 6 7 8

IC DECOUPLING

A

C116

C111

C105

0.1uF

C109

0.1uF

2 1

CAP0805

C45

C46

0.1uF

2 1

CAP0805

C67

C79

2 1

0.1uF

2 1

CAP0805

0.1uF

C112

C72

C41

2 1

0.1uF

CAP0805

0.1uF

CAP0805

0.1uF

CAP0805

C115

C81

C42

2 1

CAP0805

2 1

CAP0805

2 1

CAP0805

0.1uF

C114

C103

C66

2 1

C108

0.1uF

CAP0805

C99

0.1uF

CAP0805

C62

0.1uF

CAP0805

2 1

CAP0805

2 1

CAP0805

2 1

CAP0805

C106

C107

2 1

0.1uF

2 1

CAP0805

C70

C80

2 1

0.1uF

2 1

CAP0805

C93

C85

47uF

2 1

CAP0805

CAPT7343

+5V +3V +3V

0.1uF

C113

0.1uF

2 1

CAP0805

C59

C69

0.1uF

2 1

CAP0805

C73

C49

2 1

0.1uF

2 1

CAP0805

B

0.1uF

C117

0.1uF

2 1

C48

2 1

C

CAP0805

C43

0.1uF

CAP0805

0.1uF

2 1

CAP0805

C87

C71

C44

C50

0.1uF

2 1

CAP0805

2 1

0.1uF

CAP0805

2 1

0.1uF

CAP0805

2 1

0.1uF

CAP0805

2 1

0.1uF

CAP0805

1 2 3 4 5 6 7 8

D

PPCI

+12V

21

A

C89

47uF

C94

0.1uF

CAPT7343

CAP0805

B

RST# {10}PAD27 PAD26

R39 1 2

1/10W 5%

10K

3

U16

74ALS08

1

2

R58

1 2

1/10W 5%

+5V

10K

Z3

JUMP1X2

1 2

SPARES

C

6

8

11

U16

74ALS08

4

5

9

U16

74ALS08

10

74ALS08

12

13

D

BREV

Sheet of

PRIMARY PCI INTERFACE

4/14/98 02 10

80960RM

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

+3V2

AD23

PAD22

28

PPAR

AD2028AD22

GND5

29

30

AD1929AD21

GND7

30

PAD21 PAD20

PAD19

P_GNT

P_REQB7P_RST

A7

E6

PGNT#

PREQ#

RST#

AD18

31

+3V2

31

P33V PAD18

J15

32

J14

32

PAD17 PAD16

P_LOCK

M4

PLOCK#

CONNPCI_A

+3V1

AD16

FRAME#35GND137GND2

TRDY#

33

34

36

PFRAME#

CONNPCI_B

+3V1

AD17

C/BE2#37DEVSEL#

GND138GND2

IRDY#39LOCK#40PERR#42SERR#

36

33

34

35

P33V PTRDY#

PIRDY#

PC/BE2# P33V

PDEVSEL#

P_AD0

U1

P_AD1

U2

P_AD2

U3

P_AD3

T1

P_AD4

T3

P_AD5

T4

P_AD6

T5

P_AD7

R1

P_AD8

R3

P_AD9

R5

P_AD10

P1

P_AD11

P3

P_AD12

P4

P_AD13

P5

P_AD14

N1

P_AD15

N2

P_AD16

K3

P_AD17

K4

P_AD18

K5

P_AD19

J1

P_AD20

J2

P_AD21

J3

P_AD22

J5

P_AD23

H1

P_AD24

H5

P_AD25

G1

P_AD26

G2

P_AD27

G3

P_AD28

E5

P_AD29

A6

P_AD30

C6

P_AD31

D6

STOP#

39

38

PSTOP#

PLOCK# P33V

PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9

PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31

+3V2

41

PPERR#

GND3

PAR

SBO#40SDONE

42

43

+3V243+3V3

P33V PPAR

PSERR#

AD15

44

C/BE1#

44

PC/BE1# PAD15

45

PAD14 P33V

+3V3

AD1146AD13

47

PAD13

AD14

GND349GND4

46

PAD12 PAD11

RNC4R8P

AD952C/BE0#

GND4

49

48

PAD9

AD1047AD12

48

PAD10

CLK_960

876

+3V4

53

AD752AD8

54

53

P33V PAD6

PAD8 PC/BE0#

PAD7 P33V

LOGIC_CLK {05}

54

321

13

FB

CY7B9910-7

REF23TEST

3FS1

CLK

+3V4

55

PAD5 PAD4

R55

Q7

AD454AD6

22

AD2

GND5

57

56

PAD2

AD355AD5

GND5

56

57

PAD3

RNC4R8P

58

PAD1 PAD0

CLKA {08}

876

1

CONNPCI_A

P33V

21

+12V

+5V18+5V210+5V3

INTA#7INTC#

TDI3TMS

TRST#

2

5

6

+5V16+5V2

INTB#8INTD#9PRSNT1#11PRSNT2#

5

7

PINTB# PINTC#

PINTD#

9

11

10

4

1

C95

CAP0805

0.1uF

CONNPCI_B

-12V

GND1

TCK4TDO

1

3

2

+5V N12V +5V

21

0.1uF

0.1uF C98

0.1uF C97

0.1uF

C104

C102

C101

C100

TD TD

CAP0805

+5V4

GND113GND2

RST#

16

12

141915

PRST#

CLK

GND213GND315GND417GND5

16

12

14

E8

R2

+3V1

AD2622AD28

AD30

GND3

GNT#

18

17

PGNT#

+5V3

REQ#

19

18

PREQ#

E7

P_INTAD8P_INTB

P_INTCC7P_INTD

U15

i960RM

P_C/BE0N5P_C/BE1K1P_C/BE2H4P_C/BE3L1P_DEVSEL

GND4

21

23

20

24

PAD28 PRST#

AD2523AD27

AD2920AD31

GND6

24

21

22

PAD31 PAD30

PAD29 P33V

PAD25

M3

M1

P_PERR

P_SERR

PRIMARY PCI SIGNALS

P_FRAME

P_IRDY

L5

L3

L2

AD24

25

+3V1

25

P33V PAD24

C20

P_CLK

P_TRDY

M5

IDSEL

27

26

C/BE3#

27

26

PAD23 P33V

PC/BE3# PIDSEL

P_IDSELN3P_PAR

P_STOP

H3

1 2 3 4 5 6 7 8

PIRDY#

PIDSEL

PTRDY#

PPCI PINTA#

PC/BE0# PINTA#

PC/BE1# PINTB#

PC/BE2# PINTC#

PC/BE3# PINTD#

PFRAME# PPERR#

PDEVSEL# PSERR#

PSTOP#

+5V161+5V262+5V3

AD0

REQ64#

59

60

+5V161+5V262+5V3

ACK64#

AD1

59

60

CLKB {08}

3

2

CLKC {09}

CLKD {09}

54

7Q08Q110Q211Q315Q416Q518Q619

J15

J14

22

R40

U18

1 2 3 4 5 6 7 8

A

B

C

D

A

DCLKIN

DRAMCLK_LA {05}

DCLK0 {06}

DCLK1 {06}

DCLK2 {06}

DCLK3 {06}

B

C

D

BREV

Sheet of

MEMORY CONTROLLER

4/14/98 03 10

80960RM

Title:

Name:

Date:

+3V

RNC4R8P

876

4

OUT05OUT1

MPC9140/CDC318

CLKIN38OE

R57

11

1 2

1/10W 5%

2.7K

12

R29

DCLKOUT

8

1/10W 5%

321

R23

30

RNC4R8P

5 4

OUT29OUT313OUT414OUT517OUT618OUT731OUT832OUT9

36

876

321

R22

30

5 4

35

OUT1036OUT1140OUT1241OUT1344OUT1445OUT1521OUT1628OUT17

SCLK24SDA

25

SCL {06,07}

SDA {06,07}

RAD {04,05}

SEL_LED# {04}SM2 RAD1

8

25 SCIENCE PARK

SELUART# {04}

3

U13

1

U9

ROMA18

ROMA {04}SCE0# RAD11 R42 1 2

1/10W 5%

1 2

1.5K

JUMP1X2

Z2

IOW# {04}

U13

9

10

6

U13

74ALS32

2

74ALS32

U6

5

RWE#

13 12

4

74ALS32

74ALS04

12

11

U6

IOR# {04}

U13

13

11 10

74ALS32

74ALS04

Z1

1 2

RAD4/STEST

JUMP1X2

TP2

1

RAD0

R41 1 2

1.5K

CYCLONE MICROSYSTEMS

1/10W 5%

NEW HAVEN, CT 06511

SCB7

SCB6

SCB5

K32

K30

V31

W32

K31

K28

V30

W30

DQ32

E22

DQ32

DQ33

B23

DQ33

DQ34

E23

DQ34

DQ35

C24

DQ35

DQ36

E24

DQ36

DQ37

B25

DQ37

DQ38

E25

DQ38

DQ39

C26

DQ39

DQ40

A27

DQ40

DQ41

C27

DQ41

DQ42

A28

DQ42

DQ43

G32

DQ43

DQ44

H31

DQ44

DQ45

H28

DQ45

DQ46

J30

DQ46

DQ47

J28

DQ47

DQ48

W28

DQ48

DQ49

Y31

DQ49

DQ50

Y28

DQ50

DQ51

AA30

DQ51

DQ52

AA28

DQ52

DQ53

AB31

DQ53

DQ54

AB28

DQ54

DQ55

AC30

DQ55

DQ56

AC28

DQ56

DQ57

AD31

DQ57

DQ58

AD28

DQ58

DQ59

AE30

DQ59

DQ60

AE28

DQ60

DQ61

AF31

DQ61

DQ62

AF28

DQ62

DQ63

AH32

DQ63

12

24

R37

1/10W 5%

1 2 3 4 5 6 7 8

SDRAM {05,06}

DCLKOUT

SCB7

DCLKOUT

E21

A22

SCB6

U15

DCLKIN

SCB3

SCB4

SCB5

i960RM

MEMORY CONTROLLER

SA10

SA11

T32

R28

SA11 SCB4

SA10 SCB3

21

18pF

SCB2

SA9

R29

SA9 SCB2

C110

CAP0805

SCB1

SA8

R30

SA8 SCB1

SCB0

SA7

R32

SA7 SCB0

D20

A20

ROE

RWE

SA4

SA5

SA6

P31

P30

P28

SA6

SA5 ROE#

SA4 RWE#

A

C19

RCE0

SA3

P32

SA3 RCE0#

E19

RCE1

SA2

N28

SA2 RCE1#

B19

RALE

SA1

N29

SA1 RALE

ONCE#

C21

D18

E18

A19

ONCE

RAD14

RAD15

RAD16

SBA0

SBA1

SA0

SRAS

T31

T30

N30

N32

SA0

SBA0 RAD16

SBA1 RAD15

SRAS# RAD14

B

C18

RAD13

SCAS

L30

SCAS# RAD13

A18

RAD12

SWE

L32

SWE# RAD12

E17

RAD11

SCE0

M30

RAD9 RCE1#

E15

C15

RAD9

RAD10

SCKE0

SCE1

T28

M28

SCE1# RAD10

12

R50

SCKE0 {06,10}

RAD8

RAD7

D14

E14

A15

RAD7

RAD8

SCKE1

U32

V32

SM7 RAD6/RST_MODE#

22

R51

1/10W 5%

C13

E13

A14

C14

RAD5

RAD3/RETRY

RAD4/STEST

RAD6/RST_MODE#

RAD2/32BITMEM_EN#

SDQM3

SDQM4

SDQM5

SDQM6

SDQM7

L28

U28

U29

M31

SM6 RAD5

SM5 RAD4/STEST

SM4 RAD3/RETRY

SM3 RAD2/32BITMEM_EN#

12

22

1/10W 5%

SCKE1 {06,10}

B13

RAD1

SDQM2

U30

A13

RAD0

SDQM1

M32

SM1 RAD0

SDQM0

L29

SM0

DQ0

D22

DQ0

DQ1

A23

DQ1

DQ2

C23

DQ2

DQ3

A24

DQ3

DQ4

D24

DQ4

DQ5

A25

DQ5

DQ6

C25

DQ6

DQ7

A26

DQ7

DQ8

E26

DQ8

DQ9

B27

DQ9

DQ10

E27

DQ10

DQ11

C28

DQ11

DQ12

H32

DQ12

DQ13

H30

DQ13

DQ14

J32

DQ14

DQ15

J29

DQ15

DQ16

W29

DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ16

Y32

DQ17

Y30

DQ18

AA32

DQ19

AA29

DQ20

AB32

DQ21

AB30

DQ22

AC32

DQ23

AC29

DQ24

AD32

DQ25

AD30

DQ26

AE32

DQ27

AE29

DQ28

AF32

DQ29

AF30

DQ30

AG32

DQ31

RAD6/RST_MODE#

876

SWDIP4

123

876

RNC4R8P

1

RAD3/RETRY

RAD2/32BITMEM_EN#

5

S1

4

54

3

2

1.5K

R13

1 2 3 4 5 6 7 8

C

D

A

B

C

D

BREV

3

OUTA6OUTB

1488

IN1A4IN1B5IN2B9IN3A10IN3B12IN4A13IN4B

2

+5V

16C550

13

36

TXD

D7

CONNJ6-6P

12354

8

OUTC11OUTD

37

RTS

DTR38OP135OP2

J7

6

470

R15

3 2 1

RNC4R8P

U5

U6

1

2

3

1489A

+5V

11

40

41

CTS

RXD

DSR

A2

2D03D14D25D36D47D58D69

4

U7

42

43

RI

CD

31A030A129

10

RXCLK

+5V

5

1489A

17

BAUDOUT

CS2

16

U7

6

18

32

27

19

XTAL1

XTAL2

TXRDY

RXRDY

CS015CS125IOR21IOW39RST

IOR20IOW

14

24

74ALS04

9 8

+5V

33

26

INT

DDIS

U12

AS

28

470

R16

3 2 1

RNC4R8P

21Q52Q63Q94Q125Q156Q167Q19

74ABT273

31D42D73D8

RAD9 LED0

RAD10 LED1

CR1

21

CR1

5 4

43

6

CR1

7

65

8

CR1

87

CR2

21

CR2

5 4

43

6 7

CR2

65

8

CR2

87

4D135D146D177D188D11CLK1CLR

RAD11 LED2

RAD12 LED3

RAD13 LED4

RAD14 LED5

RAD15 LED6

LED4SM

8Q

RAD16 LED7

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

U3

9

SPARES

1489A

+5V

21

CR3

LED RED

12

R17

1/10W 5%

U6

5 6

10

8

470

74ALS04

13

U7

12

11

1489A

RAM3V {01,06,10}

21

CR4

LED GREEN LP

12

R18

1.6K

1/10W 5%

U7

P33V {01,02,08,09}

21

CR5

LED GREEN

12

R19

330

1/10W 5%

Sheet of

4/14/98 04 10

FLASH ROM, UART, & LEDS

80960RM

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

5

O

OSC1.8432MHz

E/D

1

RAD16

RAD15

RAD14

RAD13

RAD12

RAD11

RAD10

SELUART# {03}

U4

ROMA {03}

191Q182Q173Q164Q155Q146Q137Q12

74ABT573

21D32D43D54D65D76D87D9

IOR# {03}

8Q

8D11LE1OC

U6

74ALS04

1 2

IOW# {03}

I_RST# {05,07} IRQUART# {07}RAD6/RST_MODE# ROMA20

191Q182Q173Q164Q155Q146Q137Q12

U1

74ABT573

21D32D43D54D65D76D87D9

+12V

11

VPP

E28F016S5

A20

40

ROMA20

36

ROMA19

ROMA18

RY/BY

ROMA17

8Q

8D11LE1OC

I_RST# {05,07}

12

RP

ROMA16

ROMA15

ROMA14

U2

ROMA13

ROMA12

14

ROMA11

ROMA10

A1013A118A127A136A145A154A163A172A181A19

A9

ROMA9

RAD8

SEL_LED# {03}

RAD7

RAD5

RAD4/STEST

RAD6/RST_MODE#

21A320A419A518A617A716A815

RAD3/RETRY RAD16

+5V

D7

A2

22

RAD2/32BITMEM_EN# RAD15

A1

RAD1 RAD14

24A023

RAD0 RAD13

R59 1 2

10K

U6

RAD12

38

RWE# RAD11

1/10W 5%

3 4

FAIL# {07}

CE37OE

WE

9

Z4

1 2

RCE0# RAD10

74ALS04

25D026D127D228D332D433D534D635

U11

ROE# RAD9

JUMP1X2

RAD13 ROMA13 RAD0

RAD12 ROMA12

RAD11 ROMA11

RAD9 ROMA9

RAD10 ROMA10

RAD5 ROMA19

RAD4/STEST ROMA18

RAD3/RETRY ROMA17

RAD16 ROMA16 RAD9

RAD15 ROMA15 RAD2/32BITMEM_EN#

RAD14 ROMA14 RAD1

RALE

1 2 3 4 5 6 7 8

RAD {03,05}

A

B

RALE

1 2 3 4 5 6 7 8

C

D

A

B

C

D

BREV

MICTOR

CLK0

39

GND140GND241GND342GND443GND5

SCE1#

SBA1

CLK1

36

RALE

CLK1

36

SBA0

LOGIC_CLK {02}

CLK1

36

SGNT5#

SGNT4#

SGNT3#

SPCI {07,08,09}

I_RST# {04,07}

SGNT2#

SGNT1#

SGNT0#

2524232221

39

GND140GND241GND342GND443GND5

2524232221

SREQ5#

SREQ4#

39

GND140GND241GND342GND443GND5

2524232221

4

563

789

10

11121314151617181935343332313029282726

4

563

789

10

11121314151617181935343332313029282726

SCE0#

4

563

789

10

11121314151617181935343332313029282726

SREQ3#

SREQ2#

20

SREQ1#

SREQ0#

J8

20

J10

J12

20

Sheet of

4/14/98 05 10

LOGIC ANALYZER I/F

80960RM

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

39

DQ40 SA8 DQ56

DQ39 SA7 DQ55 RWE#

DQ38 SA6 DQ54 ROE#

GND140GND241GND342GND443GND5

2524232221

39

GND140GND241GND342GND443GND5

2524232221

DQ37 SA5 DQ53 RCE1#

DQ36 SA4 DQ52 RCE0#

MICTOR

CLK0

DRAMCLK_LA {03}

MICTOR

CLK0

4

DQ15 SM7 DQ31 RAD15

563

DQ14 SM6 DQ30 RAD14

DQ13 SM5 DQ29 RAD13

DQ3 SCB3 DQ19 RAD3/RETRY

DQ2 SCB2 DQ18 RAD2/32BITMEM_EN#

DQ1 SCB1 DQ17 RAD1

DQ0 SCB0 DQ16 RAD0

CLK1

36

CLK1

36

DQ47 SWE# DQ63

789

10

11121314151617181935343332313029282726

789

10

11121314151617181935343332313029282726

DQ9 SM1 DQ25 RAD9

DQ8 SM0 DQ24 RAD8

DQ7 SCB7 DQ23 RAD7

DQ6 SCB6 DQ22 RAD6/RST_MODE#

DQ5 SCB5 DQ21 RAD5

DQ12 SM4 DQ28 RAD12

DQ11 SM3 DQ27 RAD11

DQ10 SM2 DQ26 RAD10

DQ4 SCB4 DQ20 RAD4/STEST

DQ46 SCAS# DQ62

DQ45 SRAS# DQ61

DQ44 DQ60

DQ43 SA11 DQ59

DQ42 SA10 DQ58

DQ41 SA9 DQ57

1 2 3 4 5 6 7 8

SDRAM {03,06} RAD {03,04}

A

B

C

DQ35 SA3 DQ51 RALE

DQ34 SA2 DQ50

DQ33 SA1 DQ49

J11

20

J9

20

DQ32 SA0 DQ48 RAD16

1 2 3 4 5 6 7 8

D

A

B

C

D

BREV

Sheet of

SDRAM 168-PIN DIMM

4/14/98 06 10

80960RM

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

SCKE0 {03,10}

136

128

129

127

130M6131

132

M7

CS3

NC5

CKE0

GND5

SDRAM-DIMM168P

GND1

85

43

GND5

SDRAM-DIMM168P

GND1

1

VCC1

DQ3287DQ3388DQ3489DQ3591DQ3692DQ3793DQ3894DQ3995DQ4097DQ4198DQ4299DQ43

90

86

45

46M247

44

M3

CS2

NC448NC550NC651NC7

VCC1

DQ03DQ1

DQ2

DQ3

6

2

4

5

DQ0 DQ32

DQ1 SCE0# DQ33 SCE1#

DQ2 SM2 DQ34 SM6

DQ3 SM3 DQ35 SM7

137

134

135

133

CB6

CB7

NC6

NC7

VCC5

52

49

CB253CB3

VCC6

DQ6

DQ48DQ510DQ711DQ813DQ9

9

7

DQ4 DQ36

DQ5 DQ37

DQ6 DQ38

DQ7 SCB2 DQ39 SCB6

DQ8 SCB3 DQ40 SCB7

138

139

140

141

DQ48

DQ49

DQ50

GND6

GND2

96

54

55

DQ1656DQ1757DQ1858DQ19

GND6

GND2

DQ1015DQ1116DQ1217DQ1319DQ1420DQ15

12

14

DQ9 DQ16 DQ41 DQ48

DQ10 DQ17 DQ42 DQ49

DQ11 DQ18 DQ43 DQ50

142

100

DQ12 DQ19 DQ44 DQ51

DQ51

DQ44

143

101

59

DQ13 DQ45

VCC6

DQ45

VCC7

144

102

DQ20 DQ52

60

18

DQ52

VCC2

DQ20

VCC2

148

147

145

146

149

NC8

DQ46

103

61

NC862NC9

DQ14 DQ46

150

NC9

NC10

DQ53

DQ54

GND7

CB4

CB5

GND3

NC1

DQ47

105

106

107

108

104

SCB4

DQ21 DQ53

DQ22 DQ54

SCKE1 {03,10}

63

64

65

DQ2166DQ2267DQ2369DQ2470DQ2571DQ2672DQ2774DQ2875DQ29

CKE1

GND768GND8

CB022CB1

GND3

NC1

21

23

24

DQ15 DQ47

SCB0

SCB1 SCB5

151

109

DQ23 DQ55

25

DQ55

NC2

DCLK3 {03}

152

110

26

GND8

VCC3

153

111

27

SWE# DQ24 SCAS# DQ56

DQ56

CAS

WE

154

DQ57

112M4113

28M029

SM0 DQ25 SM4 DQ57

155

SM1 DQ26 SM5 DQ58

DQ58

M5

M1

156

DQ59

CS1

114

CS0

30

SCE0# DQ27 SCE1# DQ59

157

VCC7

RAS

115

SRAS#

73

VCC8

NC3

31

158

116

DQ28 DQ60

32

DQ60

GND4

162

159

160

161

DQ61

DQ62

DQ63

GND9

A1

117

118A3119A5120A7121A9122

78

76

DQ3077DQ31

GND9

A0

33

34A235A436A637A839

SA0 DQ29 SA1 DQ61

SA2 DQ30 SA3 DQ62

SA4 DQ31 SA5 DQ63

SA6 SA7

163

164

CLK3

NC11

BA0

SA9

DCLK2 {03}

79

80

CLK2

NC1081NC11

A10

38

SA8

SA10 SBA0

165

123

SBA1 SA11

SA0

A11

BA1

166

167

SA1

SA2

CLK1

VCC4

125

124

SDA {03,07}

SCL {03,07} DCLK1 {03}

83

82

SCL

SDA

VCC441VCC5

40

168

VCC8

J5

NC4

126

84

VCC9

J5

CLK0

42

DCLK0 {03}

SDRAM {03,05}

RAM3V {01,04,10}

1 2 3 4 5 6 7 8

A

B

C

D

1 2 3 4 5 6 7 8

A

+3V

SDA {03,06}

SCL {03,06}SGNT2# SDEVSEL#

B

RNC4R8P

876

2

1

C8

A8

SCL

SDA

C

I_RST# {04,05}

54

2.7K

R36

3

C12

A12

C11

E11

TDI

TCK

TDO

TRST

JTAG HEADER

B11

A21

A11

TMS

I_RST

LCDINIT

10

2

J6

1

3 4

5 6

7 8

HEAD16SH

9

11 12

13 14

15 16

R14 1 2

1/10W 5%

1.5K

D

BREV

Sheet of

4/14/98 07 10

SECONDARY PCI/960 CORE

80960RM

Title:

Name:

Date:

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

+5V

RNC4R8P

876

U15

i960RM

2.7K

R44

S_INTA/XINT0C9S_INTB/XINT1E9S_INTC/XINT2

B9

SINTA#

SLOCK#

AK20

AH20

S_LOCK

S_PERR

S_GNT5

AK19

AK29

JX CORE/I2C/JTAG

SINTB#

SINTC#

S_PAR

S_INTD/XINT3

XINT4

A10

C10

D10

SINTD#

IRQFAN# {10}

S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_AD8 S_AD9 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 S_AD27 S_AD28 S_AD29 S_AD30 S_AD31

NMI

XINT5

A9

E12

IRQUART# {04}

AH14 AK14

AL14

AM14 AH15

AJ15

AK15 AM15

AJ17

AK17 AM17 AH18 AK18

AL18

AM18 AH19 AH22 AK22

AL22

AM22 AH23

AJ23

AK23 AM23 AK24

AL24

AM24 AH25

AJ25

AK25 AM25 AH26

FAIL

FAIL# {04}

SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 SAD7 SAD8 SAD9

VCC5REF

VCCPLL1

E20

C22

SAD10 SAD11 SAD12 SAD13 SAD14 SAD15 SAD16 SAD17 SAD18 SAD19 SAD20 SAD21 SAD22 SAD23 SAD24 SAD25 SAD26 SAD27 SAD28 SAD29 SAD30 SAD31

VCCPLL2

B15

D26

VCCPLL3

C76

21

12

R52

100

1/2W 5%

+5V

+3V

CAPT7343

4.7uF

C77

21

CAP0805

0.01uF

12

R43

10

1/8W 5%

C92

21

CAPT7343

4.7uF

C96

21

CAP0805

0.01uF

12

R56

10

1/8W 5%

C57

21

CAPT7343

4.7uF

C61

21

CAP0805

0.01uF

12

10

R30

1/8W 5%

54

321

AH17

AJ19

S_C/BE0

S_REQ0

AL26

AH27

R3

AM21

S_C/BE1

S_C/BE2

S_REQ1

S_REQ2

AK27

2.7K

AH24

S_C/BE3

S_REQ3

AH28

876

RNC4R8P

321

SIRDY#

AK21

AJ21

AL20

AH21

S_IRDY

S_TRDY

S_STOP

S_FRAME

U15

i960RM

SECONDARY PCI SIGNALS

S_REQ4

S_REQ5

S_GNT0

S_GNT1

AL28

AJ29

AJ27

AM26

54

AM20

AM19

S_SERR

S_DEVSEL

S_GNT2

S_GNT3

AK28

AM27

AK26

S_RST

S_GNT4

AM28

1 2 3 4 5 6 7 8

SPCI {05,08,09}

SREQ0# SC/BE0#

SREQ1# SC/BE1#

SREQ2# SC/BE2#

SREQ3# SC/BE3#

SREQ4#

SREQ5# SFRAME#

SGNT0# STRDY#

SGNT1# SSTOP#

SGNT3# SSERR#

SGNT4# SRST#

SGNT5# SPERR#

SPAR

1 2 3 4 5 6 7 8

A

B

C

D

A

B

C

D

BREV

P33V {01,02,04,09}

A33

A32

+3V1

AD16

CONNPCI_32

AD17

C/BE2

B32

B33

SAD17 SAD16

SC/BE2#

+5V

SFRAME#

A35

A34

GND1

FRAME

GND6

IRDY

B34

B35

SIRDY#

876

RNC4R8P

STMS

STRDY#

A39

A37

A38

A36

+3V2

TRDY

STOP

GND2

+3V5

GND7

DEVSEL

LOCK

B36

B38

B37

B39

P33V {01,02,04,09}

A40

SDONE

PERR

B40

SPERR# STDI

321

STRST#

A41

SBO

+3V6

B41

54

STCK

SPAR

A42

A43

GND3

SERR

B43

B42

SSERR#

PAR

+3V7

A44

AD15

C/BE1

B44

SC/BE1# SAD15

R1

A45

B45

SAD14

2.7K

+3V3

AD14

A46

B46

AD13

GND8

+5V

RNC4R8P

A47

A48

AD11

AD12

B48

B47

SAD12 SAD11

876

1

SFRAME#

A49

AD09

GND4

AD10

GND9

B49

2

STRDY#

3

SIRDY#

A52

B52

SAD8 SC/BE0#

54

SDEVSEL#

A53

A54

+3V4

C/BE0

AD07

AD08

B54

B53

AD06

+3V8

SECONDARY PCI BUS 1/2

80960RM

Title:

Name:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

12

R9

10K

1/10W 5%

A59

A61

A62

A60

+5V1

+5V2

+5V3

REQ64

J2

+5V4

+5V5

+5V6

ACK64

B59

B61

B62

B60

12

R10

10K

1/10W 5%

Sheet of

4/14/98 08 10

Date:

876

SREQ4#

A46

AD13

GND8

B46

SREQ5#

A47

AD11

AD12

B47

SAD12 SAD11

A48

B48

GND4

AD10

321

A49

B49

AD09

GND9

54

2.7K

R31

+5V

A52

B52

C/BE0

AD08

A53

+3V4

AD07

B53

A58

A57

A55

A54

A56

AD00

AD02

AD04

AD06

GND5

+3V8

AD01

AD03

AD05

GND10

B54

B58

B56

B55

B57

SAD1 SAD0

+5V

876

3

2

1

SREQ0#

SREQ1#

STRDY#

A39

A37

A38

A36

+3V2

TRDY

STOP

GND2

+3V5

GND7

DEVSEL

LOCK

B36

B38

B37

B39

P33V {01,02,04,09}

54

SREQ3#

A40

A41

SDONE

PERR

B41

B40

SPERR#

SBO

+3V6

2.7K

R33

SPAR

A42

A43

GND3

SERR

B43

B42

SSERR#

PAR

+3V7

A44

AD15

C/BE1

B44

SC/BE1# SAD15

RNC4R8P

A45

+3V3

AD14

B45

SAD14

876

54

2.7K

R45

RNC4R8P

SSTOP#

+5V

12

R11

A59

A58

A57

A55

A56

A60

+5V1

AD00

AD02

AD04

GND5

REQ64

+5V4

AD01

AD03

AD05

GND10

ACK64

B59

B58

B56

B55

B57

B60

SAD1 SAD0

12

R12

+5V

321

SPERR#

10K

1/10W 5%

A61

A62

+5V2

+5V3

+5V5

+5V6

B61

B62

10K

1/10W 5%

SLOCK#

J1

CONNPCI_32

2.7K

R38

P33V {01,02,04,09}

SFRAME#

A33

A32

A34

+3V1

AD16

FRAME

AD17

GND6

C/BE2

B32

B34

B33

SAD17 SAD16

SC/BE2#

RNC4R8P

A35

GND1

IRDY

B35

SIRDY#

SPCI {05,07,09}

1 2 3 4 5 6 7 8

+12V

N12V

+5V +5V +5V +5V

STRST# {09}

A2

A1

+12V

TRST

CONNPCI_32

-12V

TCK

B1

B2

STCK {09}

STMS {09}

A4

A3

TMS

GND6

B3

B4

STDI {09}

SINTA# SDEVSEL#

A5

A6

TDI

INTA

+5V1A8+5V2

+5V5B6+5V6

TDO

B5

A7

B7

SINTB# SINTC# SSTOP#

A10

A12

A13

A9

A11

INTC

+5V3

GND1

INTDB9PRSNT1

B8

SINTD# SLOCK#

C26

2 1

B10

B11

0.01uF

CAP0805

GND7

PRSNT2

B12

C27

2 1

B13

INTB

SPCI CONN 1

A14

GND2

GND8

B14

CAP0805

0.01uF

SRST# SAD13

A15

RST

GND9

B15

SGNT0# SAD10

A16

A17

+5V4

CLK

B16

B17

CLKA {02}

A18

GNT

GND10

B18

SREQ0# SAD9

GND3

REQ

A19

B19

+5V7

A20

AD30

AD31

B20

SAD31 SAD30

A21

B21

SAD29

P33V {01,02,04,09}

SAD28 SAD7

SAD24 SAD3

A25

A23

A22

A24

+3V1

AD26

AD28

GND4

AD25

AD27

AD29

GND11

B25

B24

B23

B22

SAD27 SAD26 SAD6

SAD25 SAD5 SAD4

SAD22

A27

A29

A28

A26

+3V2

AD22

AD24

IDSEL

+3V3

AD23

GND12

C/BE3

B29

B27

B28

B26

SAD23

SAD21 SAD20 SSERR#

SC/BE3# SAD16 SAD2

P33V {01,02,04,09}

AD20

AD21

A30

GND5

AD19

B30

SAD19

SAD18

A31

AD18

J1

+3V4

B31

STRST# {09}

+12V

A2

A1

+12V

TRST

CONNPCI_32

-12V

TCK

B1

B2

N12V

STCK {09}

STMS {09}

A4

A3

TMS

GND6

B3

B4

STDI {09}

SINTB# SDEVSEL#

A5

A6

TDI

INTA

+5V1A8+5V2

+5V5B6+5V6

TDO

B5

A10

A12

A9

A11

A7

INTC

+5V3

GND1

INTDB9PRSNT1

B8

SINTA# SLOCK# SREQ2#

C18

2 1

B10

CAP0805

PRSNT2

B11

C19

0.01uF

B12

GND7

2 1

INTB

B7

SINTC# SINTD# SSTOP#

SPCI CONN 2

A13

GND2

GND8

B13

CAP0805

A14

B14

0.01uF

SRST# SAD13

A15

RST

GND9

B15

SGNT1# SAD10

A16

A17

+5V4

CLK

B16

B17

CLKB {02}

GNT

GND10

A18

B18

SREQ1# SAD9

GND3

REQ

SAD28 SAD7

SAD24 SAD3

SAD22

SAD18

A21

A22

A20

A19

+3V1

AD28

AD30

+5V7

AD29

AD31

GND11

B19

B21

B20

B22

SAD31 SAD30

SAD29 SAD8 SC/BE0#

A23

AD26

AD27

B23

SAD27 SAD26 SAD6

A24

GND4

AD25

B24

SAD25 SAD5 SAD4

A27

A31

A29

A28

A25

AD24

+3V3

B25

A26

B26

SC/BE3# SAD17 SAD2

IDSEL

C/BE3

+3V2

AD23

B27

SAD23

AD22

GND12

B28

AD20

AD21

B29

SAD21 SAD20

A30

GND5

AD19

B30

SAD19

AD18

J2

+3V4

B31

1 2 3 4 5 6 7 8

A

B

C

D

A

P33V {01,02,04,08}

STRDY#

SFRAME#

SPAR

B

+5V

12

R7

10K

1/10W 5%

P33V {01,02,04,08}

SFRAME#

STRDY#

C

SPAR

D

BREV

Sheet of

SECONDARY PCI BUS 3/4

4/14/98 09 10

80960RM

Title:

Name:

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

+5V

12

R5

10K

1/10W 5%

+12V

N12V

+5V +5V +5V +5V

A33

A32

+3V1

AD16

CONNPCI_32

AD17

C/BE2

B32

B33

SAD17 SAD16

SC/BE2#

STRST# {08}

A2

A1

+12V

TRST

CONNPCI_32

-12V

TCK

B1

B2

A35

A34

FRAME

GND6

B34

B35

SIRDY#

STMS {08}

A4

A3

TMS

GND6

B3

B4

GND1

IRDY

STDI {08}

TDI

TDO

A39

A37

A38

A36

+3V2

TRDY

STOP

GND2

+3V5

GND7

DEVSEL

LOCK

B36

B38

B37

B39

P33V {01,02,04,08}

SINTC# SDEVSEL#

A5

A6

A7

INTA

INTC

+5V1A8+5V2

+5V5B6+5V6

INTB

INTDB9PRSNT1

B5

B7

B8

A40

SDONE

PERR

B40

SPERR#

A9

A41

B41

A10

B10

SBO

+3V6

+5V3

A42

A43

GND3

SERR

B43

B42

SSERR#

A12

A11

PRSNT2

B12

B11

PAR

+3V7

GND1

GND7

A44

AD15

C/BE1

B44

SC/BE1# SAD15

A13

GND2

GND8

B13

A45

+3V3

AD14

B45

SAD14

A14

B14

A46

AD13

GND8

B46

SRST# SAD13

A15

RST

GND9

B15

A47

AD11

AD12

B47

SAD12 SAD11

A16

+5V4

CLK

B16

A48

GND4

AD10

B48

SGNT2# SAD10

A17

GNT

GND10

B17

A49

B49

A18

B18

AD09

GND9

GND3

REQ

A20

A19

AD30

+5V7

AD31

B19

B20

A53

A55

A54

A52

+3V4

AD06

C/BE0

+3V8

AD07

AD08

B54

B55

B53

B52

SAD8 SC/BE0#

P33V {01,02,04,08}

SAD28 SAD7

A21

A23

A22

A24

+3V1

AD26

AD28

AD27

AD29

GND11

B24

B23

B21

B22

AD04

AD05

GND4

AD25

A56

GND5

AD03

B56

SAD24 SAD3

A25

AD24

+3V3

B25

A57

AD02

GND10

B57

A26

IDSEL

C/BE3

B26

A58

AD00

AD01

B58

SAD1 SAD0

+5V

A27

+3V2

AD23

B27

A59

+5V1

+5V4

B59

R8

SAD22

A28

AD22

GND12

B28

A60

B60

12

A29

B29

REQ64

ACK64

AD20

AD21

A61

A62

+5V2

+5V3

+5V5

+5V6

B61

B62

10K

1/10W 5%

SAD18

A31

A30

AD18

GND5

+3V4

AD19

B31

B30

J3

CONNPCI_32

+12V

J3

CONNPCI_32

A33

A32

+3V1

AD16

AD17

C/BE2

B32

B33

SAD17 SAD16

SC/BE2#

STRST# {08}

A2

A1

+12V

TRST

-12V

TCK

B1

B2

A35

A34

FRAME

GND6

B34

B35

SIRDY#

STMS {08}

A4

A3

TMS

GND6

B3

B4

GND1

IRDY

STDI {08}

TDI

TDO

A39

A37

A38

A36

+3V2

TRDY

STOP

GND2

+3V5

GND7

DEVSEL

LOCK

B36

B38

B37

B39

P33V {01,02,04,08}

SINTD# SDEVSEL#

A5

A6

A7

INTA

INTC

+5V1A8+5V2

+5V5B6+5V6

INTB

INTDB9PRSNT1

B5

B7

B8

A40

A41

SDONE

PERR

B41

B40

SPERR#

A10

A9

B10

SBO

+3V6

+5V3

A42

A43

GND3

SERR

B43

B42

SSERR#

A12

A11

PRSNT2

B12

B11

PAR

+3V7

GND1

GND7

A44

AD15

C/BE1

B44

SC/BE1# SAD15

A13

GND2

GND8

B13

A45

+3V3

AD14

B45

SAD14

A14

B14

A46

AD13

GND8

B46

SRST# SAD13

A15

RST

GND9

B15

A47

AD11

AD12

B47

SAD12 SAD11

A16

+5V4

CLK

B16

A48

GND4

AD10

B48

SGNT3# SAD10

A17

GNT

GND10

B17

A49

B49

A18

B18

AD09

GND9

GND3

REQ

A53

A54

A52

+3V4

AD06

C/BE0

+3V8

AD07

AD08

B54

B53

B52

SAD28 SAD7

A21

A23

A22

A20

A19

+3V1

AD26

AD28

AD30

+5V7

AD27

AD29

AD31

GND11

B19

B23

B21

B20

B22

A55

B55

A24

B24

AD04

AD05

GND4

AD25

A56

B56

SAD24 SAD3

A25

B25

GND5

AD03

AD24

+3V3

A57

B57

A26

B26

A58

AD02

GND10

B58

SAD1 SAD0

+5V

A27

IDSEL

C/BE3

B27

AD00

AD01

+3V2

AD23

A59

+5V1

+5V4

B59

R6

SAD22

A28

AD22

GND12

B28

A60

B60

12

A29

B29

REQ64

ACK64

AD20

AD21

A61

A62

+5V2

+5V3

+5V5

+5V6

B61

B62

10K

1/10W 5%

SAD18

A31

A30

AD18

GND5

+3V4

AD19

B31

B30

J4

SPCI {05,07,08}

1 2 3 4 5 6 7 8

STCK {08}

A

SINTD# SINTA# SSTOP#

SINTB# SLOCK#

C11

C10

2 1

0.01uF

2 1

CAP0805

SPCI CONN 3

0.01uF

CAP0805

CLKC {02}

SREQ2# SAD9

SAD31 SAD30

SAD29

B

SAD27 SAD26 SAD6

SAD25 SAD5 SAD4

SAD23

SAD21 SAD20

SC/BE3# SAD18 SAD2

P33V {01,02,04,08}

SAD19

N12V

STCK {08}

SINTA# SINTB# SSTOP#

SINTC# SLOCK#

C3

2 1C20.01uF

2 1

CAP0805

SPCI CONN 4

C

0.01uF

CAP0805

CLKD {02}

SREQ3# SAD9

SAD31 SAD30

SAD29 SAD8 SC/BE0#

SAD27 SAD26 SAD6

SAD25 SAD5 SAD4

SAD23

SAD21 SAD20

SAD19

SC/BE3# SAD19 SAD2

1 2 3 4 5 6 7 8

D

A

SCKE0 {03,06}

12F013F114F215F316F417F518F619

U19

1I02I13I24I35I46I57I68I79

PART # 101-1950-01

SCKE1 {03,06}

F7

I811I9

RST# {02}

RAM3V {01,04,06}

20

VCC

PALLV16V8-10JC

21

100uF

C56

C53

CAP0805

0.1uF

R21 1 2

1W 1%

0.05

CAPT7343H

76543

3 2 1

SI9430

4

B

7

Q1

6 5

RAM3V {01,04,06}

21

47uH L1

1 2

8

C63

33uF

330uF

C64

CR7

CAPT7343

CAPT7343H

MBRS340T3

1 2

C

SPARES

D

BREV

Sheet of

BATTERY/MONITOR

4/14/98 10 10

80960RM

Title:

Name:

13

U10

LM339

-

11+10

+5V

14

U10

9+8

LM339

-

Date:

25 SCIENCE PARK

NEW HAVEN, CT 06511

CYCLONE MICROSYSTEMS

6CS7

21

10uF

R26 1 2

68K

REF

4

C52

CAPT7343

BT6

BATT_HLDR 1

2

BT3

BATT_HLDR 1

2

TEMP

7

1/10W 5%

1

EXT

2FB8

BT2

BATT_HLDR

1 2

+

8

FASTCHG

TLO

6

11CC13

22K

OUT

U8

GND

BT7

BATT_HLDR

1 2

+

12

BATT-

GND

21 R34 1 2

1/10W 5%

C51

21

0.1uF

BT8

BATT_HLDR

1 2

BT1

BATT_HLDR

1 2

U14

C68

CAP0805

0.01uF

CAP0805

R28 1 2

1

1/10W 5%

R60 1 2

1/10W 5%

10

1

R27 1 2

1/10W 5%

IRQFAN# {07}

R47 1 2

1/10W 5%

2.4K

R32 1 2

1/10W 5%

CAP0805

0.047uF

1/10W 5%

1

U10

7+6

LM339

-

C47

21

CAPT7343

22uF

2

U10

LM339

-

5+4

NOTE: VCC FOR LM339 IS +5V

C65

21

CAP1206

0.47uF

R35

1 2

1/10W 5%

10K

R48

1 2

1/10W 5%

4.7K R24

1 2

1/10W 5%

100K

C58

R53

1 2

21

1/10W 5%

47K

+5V

FAN CONN

0.01uF

1

FAN

J13

GND3PWR

2

CAP0805

21

100K

C82

R49 1 2

4.7K

1 2 3 4 5 6 7 8

5

V+

BATTERY

MAX1651

SHDN

3

BT5

BATT_HLDR

1 2

+

CR8

12

2

Q4

1

2N6109

3

21

150

C55

R20 1 2

CAP0805

0.01uF

1/10W 5%

R25 1 2

1K

+12V

1/10W 5%

14

DRV

MAX712

THI

5

CMR1-02

V+

15

2

BATT+

21

1

1uF

VLIMIT

CAPT3216

C74

C54

10uF

BT4

BATT_HLDR

1 2

+

REF

16

CAPT7343

3

PGM04PGM19PGM210PGM3

1 2 3 4 5 6 7 8

A

B

C

D

PLD Code C

MODULE BATT //TITLE SDRAM Battery Backup En able

//PATTERN 101-1809-01 //REVISION //AUTHOR J. Neumann //COMPANY Cyclone Microsystems Inc. //DATE 10/30/97 //CHIP PALLV16V8Z-20JI // 1/20/98 Modify target device to PALLV16V8Z-20JI

//Initial release.

PRSTn PIN 9;//Primary PCI reset SCKE0 PIN 13; //SDRAM bank 0 clock enable SCKE1 PIN 16; //SDRAM bank 1 clock enable OUT0 PIN 14; //SCKE0 output enable

OUT1 PIN 17; //SCKE1 output enable EQUATIONS // If SDRAM clock enable goes low, SDRAM clock enable

// must be held low to ensure that the SDRAM is held in auto refresh mode. // Reset going high will release the hold on SCKE.

END

OUT0 = SCKE0.PIN & PRSTn //SCKE is the set te r m, PRSTn is the reset term

# SCKE0.PIN & OUT0.PIN # !SCKE0.PIN & PRSTn;

SCKE0 = 0;

SCKE0.OE = !OUT0; //When OUT = 0, SCKE is grounded

//When OUT = 1, SCKE is high impedance

OUT1 = SCKE1.PIN & PRSTn

# SCKE1.PIN & OUT1.PIN # !SCKE1.PIN & PRSTn;

SCKE1 = 0;

SCKE1.OE = !OUT1;

IQ80960RM/RN Evaluation Board Ma nual C-1

Recycling the Bat tery D

The IQ80960RM/RN platform contains four AA NiCd batteries. Each battery has the logo of the Rechargeable Ba ttery Rec ycling Corporation (RBRC) stamped on it. The recycling fees have been prepaid on these bat teries. Do not dispose of a rec hargeable battery with regular trash in a landfill. Rechargeable batteries contain toxic chemi cals and metals that a re harmful to the environment. Improperly disposing of rechargeable batteries is also illegal. The RBRC logo on a battery is a verification that rec ycling fees have been prepaid to the RBRC and such a battery can be rec ycled at no additional cost to the user. The RBRC is a non-profit corpor ation that promotes the recycling of rechargeable batteries , including NiCd batteries.

Informati on on the RBRC program and the locations of participating recycling centers can be obtained by telephoning 1-800-8-BATTERY (in the USA), and following the recorded instructions. The information obtained from t his telephone numbe r is updated frequen tly, since the RBRC program is growing, the ne w recycling location s ar e bei ng added regularly.

IQ80960RM/RN Evaluation Board Ma nual D-1

Intel IQ80960RM, IQ80960RN User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Figures

Tables

1.2 Software Development Tools

1.3 IxWorks Software Development Toolset

1.3.1 IxWorks Real-Time Operating System

1.3.2 TORNADO Build Tools

1.3.3 TORNADO Test and Debug T ools

1.4 CTOOLS Software Development Toolset

1.4.1 CTOOLS and the MON960 Debug Monitor

1.4.1.1 MON960 Host Communications

1.4.1.2 Terminal Emulation Method

1.4.1.3 Host Debugger Interface (HDI) Method

1.5 About This Manual

1.6 Notational-Conventions

1.7 Techn ical Suppo rt

1.7.1 Intel Customer Electronic Mail Support

1.7.2 Intel Customer Support Contacts

1.7.3 Related In fo rmat io n

2.1 Pre-Installation Considerations

2.2 Software Installation

2.2.1 Installing Software Development Tools

2.3 Hardware Installation

2.3.1 Battery Bac ku p

2.3.3 Verify IQ80960RM/RN Platform is Functional

2.4 Creating and Downloading Executable Files

2.4.1 Sample Download and Execution Using GDB960

3.1 Power Requirements

3.2 SDRAM

3.2.1 SDRAM Performance

3.2.2 Upgrading SDRAM

3.3 Flash ROM

3.3.1 Flash ROM Programming

3.4 Console Serial Port

3.5 Secondary PCI Bus Expansion Connectors

3.5.1 PCI Slots Power Availability

3.5.2 Interru pt and IDS E L Rou ti ng

3.6 Battery Backup

3.7 Loss of Fan Detect

3.8 Logic Analyzer Headers

3.9 JTAG Header

3.10 User LEDs

3.10.1 User LEDs During Initialization

4.1 CPU Memory Map

4.2 Local Interrupts

4.3 CPU Counter/Timers

4.4 Primary PCI Interface

4.5 Secondary PCI Interface

4.6 DMA Channels

4.7 Application Accelerator Unit

4.8 Performance Monitor Unit

5.1 Secondary PCI Bus Expansion Connectors

5.2 MON960 Components

5.2.1 MON960 Initialization

5.2.2 80960JT Core Initialization

5.2.3 Memory Controller Initialization

5.2.4 SDRAM Initializatio n

5.2.5 Primary PCI Interface Initialization

5.2.6 Primary ATU Initialization

5.2.7 PCI-to-PCI Bridge Initialization

5.2.8 Secondary ATU Initialization

5.3 MON960 Kernel

5.4 MON960 Extensions

5.4.1 Secondary PCI Initialization

5.4.2 PCI BIOS Routines

5.4.2.1 sysPCIBIOSPresent

5.4.2.2 sysFindPCIDevice

5.4.2.3 sysFindPCIC lass C ode

5.4.2.4 sysGenerateSpecialCycle

5.4.2.5 sysReadConfigByte

5.4.2.6 sysReadConfigWord

5.4.2.7 sysReadConfigDword

5.4.2.8 sysWriteConfigByte

5.4.2.9 sysWriteConfigWord

5.4.2.10 sysWriteConfigDword

5.4.2.11 sysGetIrqRoutingOpti ons