The DK440LX motherboard may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are documented in the DK440LX Motherboard Specification Update.
Revision History
RevisionRevision HistoryDate
-001Release -001 of the DK440LX Motherboard Technical Product
Specification
This product specification applies only to standard DK440LX motherboards with BIOS identifier
4D4KL0x0.86A.
Changes to this specification will be published in the DK440LX Motherboard Specification Update
before being incorporated into a revision of this document.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
October 1997
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The DK440LX motherboard may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call in North America 1-800-879-4683, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Third-party brands and names are the property of their respective owners.
††
Wake on LAN is a trademark of IBM Corporation.
Copyright Intel Corporation, 1997. All Rights Reserved.
78.Compliance with Specifications................................................................................105
7
8
1 Motherboard Description
1.1 Overview
The DK440LX motherboard supports the following features:
Custom ATX form factor
Processor
• Single or dual Pentium
• 66 MHz bus speed
• Supports all published Pentium II processor speeds and voltages
• 512 KB second-level cache on the Single Edge Contact (S.E.C.) cartridge
• S.E.C. cartridge Slot 1 connectors
Main Memory
• Four 168-pin DIMM sockets
• Supports up to 512 MB of synchronous DRAM (SDRAM) or 1 GB of extended data out
(EDO) memory
• ECC memory support
II processor support
Intel 440LX AGPset and PCI/IDE Interface
• Intel 82443LX PCI/A.G.P. controller (PAC)
Integrated PCI bus mastering controller
Integrated Accelerated Graphics Port (A.G.P.) bus controller
• Intel 82371AB PCI/ISA/IDE Xcelerator (PIIX4)
Supports up to four IDE drives or devices
Multifunction PCI-to-ISA bridge
USB and DMA controllers
Two fast IDE interfaces
Power management logic
Real-time clock
SCSI Subsystem
†
• Adaptec
• Dual channel
• 8-bit Narrow, 8-bit Fast, 16-bit Wide, and 16-bit Ultra Wide SCSI, providing 10 MB/sec to
40 MB/sec sustained throughput per channel
• Supports burst data transfers on the PCI bus up to 133 MB/sec
• Two Ultra Wide 68-pin connectors and one 50-pin connector
• RAIDport
AIC-7895 PCI Bus Master Multichannel SCSI Host Adapter
ASerial port 2 header (optional)UNarrow (8-bit) SCSI connector
BRear chassis fan headerVSleep LED header
CATAPI CD audio connector (optional)WFront panel I/O header
DATAPI-style telephony connector (optional)XAIC-7895 SCSI Host Adapter
EATAPI-style Line In connector (optional)YHDD LED input header (4-pin)
F2 mm CD audio connector (optional)ZFront chassis 2 fan header
GCPU 2 fan headerAAFront chassis 1 fan header
HBack panel I/O connectorsBBSpeaker
ICPU 1 fan headerCC Battery
JAuxiliary power connectorDD HDD LED header (2-pin)
KBoot processor Slot 1EEWake-on-Modem header
LIntel 82443LX PACFFPC97307 SuperI/O Controller
MATX power connectorGG Wake on LAN header
The motherboard is designed to fit into an ATX form-factor chassis. Figure 2 shows that the I/O
connector locations and the mounting hole locations are in compliance with the ATX specification
(see Section 7.2).
0.203.30
12.70
12.30
11.40
0.30
0.00
0.00
5.10
5.350.45
Figure 2. Motherboard Dimensions
11.30
6.20
3.35
11.55
3.10
OM06273
14
Motherboard Description
1.5 I/O Shield
The back panel I/O shield for the motherboard must meet specific dimension and material
requirements. Systems based on this motherboard need the back panel I/O shield to pass EMI
compliance verification. Figure 3 shows the critical dimensions of a chassis-independent I/O
shield and the location of the EMI gasket on the I/O shield. Additional design considerations for
I/O shields relative to chassis requirements are described in the ATX specification. See Section 7.2
for information about the ATX specification.
0.201
0.00
0.461
1.209
1.216
1.433
1.689
0.207
0.00
0.409
0.773
1.534
1.803
Outside(Rear)
View of Shield
2.959
4.180
5.184
EMI Gasket
5.785
5.975
0.617
1.207
1.450
1.489
6.183
OM06888
Figure 3. Back Panel I/O Shield Dimensions (ATX Chassis-Independent)
The motherboard supports configurations of one or two Pentium II processors. The processor’s
VID pins automatically program the voltage regulator on the motherboard to the required processor
voltage. The motherboard currently supports processors that run internally at 233 MHz, 266 MHz,
or 300 MHz , have a 512 KB second-level cache, and identical processor voltages. In order to
ensure reliable motherboard operation across the widest possible range of processor and chassis
combinations, it is recommended that only Pentium II processors with fan/heatsinks be installed on
the DK440LX motherboard.
1.6.1 Processor Packaging
The processor is packaged in a Single Edge Contact (S.E.C.) cartridge. The cartridge includes the
processor core, second-level cache, thermal plate, and back cover.
The processor connects to the motherboard through the Slot 1 connector, a 242-pin edge connector.
When mounted in a Slot 1 connector, the processor is secured by a retention mechanism attached to
the motherboard.
1.6.2 Second Level Cache
The second-level cache is located on the substrate of the S.E.C. cartridge. The ECC cache includes
burst pipelined synchronous static RAM (BSRAM) and tag RAM. There are four BSRAM
components totaling 512 KB in size. Only up to 512 MB of system memory is cacheable.
1.6.3 Processor Upgrades
NOTE
✏
In a uniprocessor configuration, the processor must be installed in the boot processor slot (the slot
closest to the back panel) and a termination card must be installed in the application processor
slot. If the processor is installed in the application processor slot, the computer will not boot.
Two microprocessor upgrades are available:
• Upgrade to a higher speed processor(s)
• Single to dual processors
If you are installing two processors, the following values must be identical for both processors:
• L2 cache size and type (ECC or non-ECC)
• Operating voltages
• Bus and core frequencies
The core stepping value may differ by one step, such as C0 to C1. These values can be determined
by checking the parameters of the s-spec number. The s-spec number is a five-character code, for
example, SL28R, printed on the top edge of the S.E.C.
For information about s-spec parameters, refer to the Pentium II processor quick reference guide at
the Intel developer’s web site.
16
Motherboard Description
CAUTION
If the operating voltages do not match, the computer will not boot.
When upgrading the processor, use the BIOS configuration mode to change the processor speed if
necessary (see Section 1.18.2).
1.7 Memory
1.7.1 Main Memory
The motherboard has four dual inline memory module (DIMM) sockets. Minimum memory size is
16 MB; maximum memory size is 512 MB with SDRAM and 1 GB with EDO DRAM. The BIOS
automatically detects memory type, size, and speed.
The motherboard supports the following memory features:
• JEDEC MO-161 compliant 168-pin DIMMs with gold-plated contacts (see Section 7.2 for
information about this specification)
• Unbuffered 66-MHz ECC/non-ECC SDRAM or 60-ns EDO ECC/non-ECC DIMMs
• 3.3 V memory only
• Single- or double-sided DIMMs in the sizes listed in Table 1
Table 1.Supported DIMM Sizes
DIMM SizeConfiguration
16 MB2 Mbit x 72/64
32 MB4 Mbit x 72/64
64 MB8 Mbit x 72/64
128 MB16 Mbit x 72/64
256 MB (EDO DRAM only)32 Mbit x 72/64
Memory can be installed in one, two, three, or four sockets. Memory type, size, and speed can
vary between sockets, so EDO and SDRAM DIMMs can be installed on the same motherboard.
NOTE
✏
There may be mechanical interference with the DIMM 0 socket (J6G3) and the DIMM 1 (J6G2)
socket in some combinations of ATX chassis and peripherals, such as CD-ROMs.
NOTE
✏
The DK440LX motherboard supports DIMMs with both asymmetrically and symmetrically
addressable DRAMs.
Synchronous DRAM (SDRAM) improves memory performance through memory access that is
synchronous with the memory clock. This simplifies the timing design and increases memory
speed because all timing is dependent on the number of memory clock cycles.
1.7.3 ECC Memory
Error checking and correcting (ECC) memory detects multiple-bit errors and corrects single-bit
errors. When ECC memory is installed, the BIOS supports both ECC and non-ECC mode. ECC
mode is enabled in the Setup program. The BIOS automatically detects if ECC memory is
installed and provides the Setup option for selecting ECC mode.
1.8 Chipset
The Intel 440LX AGPset is designed for the Pentium II processor and the Accelerated Graphics
Port (A.G.P.). It consists of the Intel 82443LX PCI/A.G.P. controller (PAC) and the Intel
82371AB PCI/ISA IDE Xccelerator (PIIX4) bridge chip.
1.8.1 Intel 82443LX PCI/A.G.P. Controller (PAC)
The PAC provides bus-control signals, address paths, and data paths for transfers between the
processor’s host bus, PCI bus, the A.G.P., and main memory. The PAC features:
• Processor interface control
Processor host bus speed at 66 MHz
Support for dual Pentium II processor configurations
32-bit addressing
GTL+ compliant host bus interface
• Integrated DRAM controller
Supports synchronous DRAM (SDRAM) and EDO
64/72-bit path-to-memory
Auto detection of memory type
Supports 4-, 16-, 64-Mbit DRAM devices
Symmetrical and asymmetrical DRAM addressing
Supports 3.3 V DRAMs
• Accelerated Graphics Port Interface
Complies with A.G.P. specification (see Section 7.2 for specification information)
Supports 3.3 V A.G.P. devices with data transfer rates up to 532 MB/sec
Synchronous coupling to the host-bus frequency
• Fully-synchronous PCI bus interface
Complies with PCI specification (see Section 7.2 for specification information)
PCI-to-DRAM access greater than 100 MB/sec
Supports five PCI bus masters in addition to the host and PCI-to-ISA I/O bridge
Delayed transactions
18
Motherboard Description
• Data Buffering
Host-to-DRAM, PCI-to-DRAM, and A.G.P.-to-DRAM write-data buffering
Write-combining for host-to-PCI burst writes
Supports concurrent host, PCI, and A.G.P. transactions to main memory
• Supports system management mode (SMM)
1.8.2 Intel 82371AB PCI ISA IDE Xcelerator (PIIX4)
The PIIX4 is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE
functionality, Universal Serial Bus (USB) host/hub function, and enhanced power management.
The PIIX4 features:
• Multifunction PCI-to-ISA bridge
Supports the PCI bus at 33 MHz
Complies with PCI specification (see Section 7.2 for specification information)
Full ISA bus support
• USB controller
Two USB ports (see Section 7.2 for specification information)
Supports legacy keyboard and mouse
Supports UHCI Design Guide, revision 1.1, interface
• Integrated dual-channel enhanced IDE interface
Supports up to four IDE devices
PIO Mode 4 transfers at up to 14 MB/sec
Supports Ultra DMA/33 synchronous DMA mode transfers up to 33 MB/sec
Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfers
• Enhanced DMA controller
Two 8237-based DMA controllers
Supports PCI DMA with three PC/PCI channels and distributed DMA protocols
Fast type-F DMA for reduced PCI bus usage
• Interrupt controller based on 82C59
Supports 15 interrupts
Programmable for edge/level sensitivity
• Power management logic
Sleep/resume logic
Supports Wake-on-Modem, Wake on LAN technology, and wake on PME
• Real-Time Clock
256 byte battery-backed CMOS SRAM
Includes date alarm
The Intel 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) provides interrupt
management and incorporates both static and dynamic symmetric interrupt distribution across all
processors in a multiprocessor system. The 82093AA IOAPIC features 24 interrupts as follows:
• 13 ISA interrupts
• Four PCI interrupts
• One Interrupt/SMI# rerouting
• Two motherboard interrupts
• One interrupt used for INTR input
• Three general purpose interrupts
1.8.4 Accelerated Graphics Port (A.G.P.)
The Accelerated Graphics Port (A.G.P.) is a high-performance interconnect for graphic-intensive
applications, such as 3D applications. A.G.P. is independent of the PCI bus and is intended for
exclusive use with graphical display devices. A.G.P. provides these performance features:
• Pipelined-memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for near 100 percent bus efficiency
• AC timing for 133 MHz data transfer rates, allowing data throughput of 533 MB/sec
See Section 7.2 for more information about the A.G.P. specification.
1.8.5 Universal Serial Bus (USB)
The motherboard has two USB ports; one USB peripheral can be connected to each port. For more
than two USB devices, an external hub can be connected to either port. The motherboard fully
supports the universal host controller interface (UHCI) and uses UHCI-compatible software
drivers. See Section 7.2 for information about the USB specification. USB features include:
• Self-identifying, hot pluggable peripherals
• Automatic mapping of function to driver and configuration
• Support of isochronous and asynchronous transfer types
• Support for a maximum of 127 physical devices
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error handling and fault recovery mechanisms built into protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for high-speed devices.
20
Motherboard Description
1.8.6 IDE Support
The motherboard has two independent bus-mastering IDE interfaces. These interfaces support PIO
Mode 3, PIO Mode 4, ATAPI devices (e.g., CD-ROM), and Ultra DMA synchronous-DMA mode
transfers. The BIOS supports logical block addressing (LBA) and extended cylinder head sector
(ECHS) translation modes. The BIOS automatically detects the IDE device transfer rate and
translation mode.
The motherboard supports LS-120 diskette technology through its IDE interfaces. LS-120 diskette
technology enables users to store 120 MB of data on a single, 3.5-inch removable diskette. LS-120
technology is backward (both read and write) compatible with 1.44 MB and 720 KB DOS-
†
formatted diskettes and is supported by Windows
95 and Windows NT† operating systems.
The motherboard allows connection of an LS-120 compatible drive and a standard 3.5-inch diskette
drive. If an LS-120 drive is connected to an IDE connector and configured as the A drive and a
standard 3.5-inch floppy is configured as a B drive, the standard floppy must be connected to the
floppy drive cable's "A" connector (the connector at the end of the cable). The LS-120 drive can be
configured as a boot device, if selected in the BIOS setup utility.
1.8.7 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for
BIOS use.
The time, date, and CMOS values can be specified in the Setup program. The CMOS values can
be returned to their defaults by using the Setup program.
An external coin-cell battery powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the 3 V standby current from the power supply extends the life of the
battery. The clock is accurate to ± 13 minutes/year at 25 ºC with 5 V applied.
The PC97307 SuperI/O controller from National Semiconductor is an ISA Plug and Play
compatible (see Section 7.2), multifunction I/O device that provides the following features:
• Serial ports
Two 16450/16550A-software compatible UARTs
Internal send/receive 16-byte FIFO buffer
Four internal 8-bit DMA options for the UART with SIR support (USI)
• Multimode bidirectional parallel port
Standard mode: IBM and Centronics compatible
Enhanced parallel port (EPP) mode with BIOS and driver support
High-speed extended capabilities port (ECP) mode
• Floppy disk controller
DP8473 and N82077 compatible
16-byte FIFO buffer
†
PS/2
High-performance digital data separator (DDS)
PC-AT
• Keyboard and mouse controller
Industry standard 8042A compatible
General-purpose microcontroller
8-bit internal data bus
diagnostic-register support
†
, PS/2, and 3-mode floppy disk drive-mode support
By default, the I/O controller interfaces are automatically configured during boot up. The I/O
controller can also be manually configured in the Setup program.
1.9.1 Serial Ports
The two 9-pin D-Sub serial port connectors on the back panel are compatible with 16450 and
16550A UARTs. An optional onboard keyed 10-pin header is available for internal cabling of
serial port 2. If the optional onboard serial port 2 header is installed, the 9-pin D-Sub serial port 2
connector is not installed.
1.9.2 Parallel Port
The connector for the multimode bidirectional parallel port is a 25-pin D-Sub connector located on
the back panel. In the Setup program, the parallel port can be configured for the following:
• Compatible (standard mode)
• Bidirectional (PS/2 compatible)
• Extended Parallel Port (EPP)
• Enhanced Capabilities Port (ECP)
22
Motherboard Description
1.9.3 Floppy Controller
The I/O controller is software compatible with the DP8473 and N82077 floppy drive controllers
and supports both PC-AT and PS/2 modes. In the Setup program, the floppy interface can be
configured for the following floppy drive capacities and sizes:
• 360 KB, 5.25-inch
• 1.2 MB, 5.25-inch
• 720 KB, 3.5-inch
• 1.2 MB, 3.5-inch (driver required)
• 1.25/1.44 MB, 3.5-inch
• 2.88 MB, 3.5-inch
1.9.4 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The 5 V lines to these
connectors are protected with a PolySwitch
connection after an over-current condition is removed.
NOTE
✏
The mouse and keyboard can be plugged into either of the PS/2 connectors. Power to the
computer should be turned off before a keyboard or mouse is connected or disconnected.
The keyboard controller contains the AMI Megakey keyboard and mouse controller code, provides
the keyboard and mouse control functions, and supports password protection for power on/reset. A
power on/reset password can be specified in Setup.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del> for a software
reset. This key sequence resets the computer’s software by jumping to the beginning of the BIOS
code and running the Power-On Self Test (POST).
†
circuit that, like a self-healing fuse, reestablishes the
The optional onboard audio subsystem features the Crystal CS4236B, an audio codec with an
integrated FM synthesizer. The audio subsystem provides all the digital audio and analog mixing
functions needed for recording and playing sound on personal computers. Together, these
components feature the following:
• Stereo analog-to-digital and digital-to-analog converters
• Analog mixing, anti-aliasing, and reconstruction filters
• Line and microphone level inputs
• ADPCM, A-law, or µlaw digital audio compression/decompression
• Full digital control of all mixer and volume control functions
• AdLib, Sound Blaster Pro 2.0, Windows Sound System, and MPU-401 support
• Full DOS games compatibility
• MIDI/Game port support
• OPL3 compatible FM synthesizer
• BIOS Setup-based enable/disable
• Onboard Crystal CS9236 Wavetable Music Synthesizer (optional)
The audio subsystem requires up to two DMA channels and one IRQ. Table 2 shows the IRQ,
DMA channel, and base I/O address options. These options are automatically chosen by the Plug
and Play interface, so there are no default settings.
Table 2.Audio Subsystem Resources
IRQ
Resource
Sound Blaster
(DMA playback, DMA / IRQ shared
with Windows Sound System capture)
Table 3 lists the performance characteristics of the audio subsystem.
Table 3.Audio Subsystem Performance
CharacteristicTest Result
Frequency Response-1.3 dB @ 20 Hz
-0.6 dB @ 20 kHz
Signal-to-Noise Ratio-91.05 dB
Total Harmonic Distortion vs. Amplitude0.0044% @ -4.813 dB
Total Harmonic Distortion vs. Frequency0.0042% @ 9355 Hz
Crosstalk L-to-R-92.69 dB
Crosstalk R-to-L-93.12 dB
1.10.2 Audio Drivers and Utilities
Motherboard Description
Audio software and utilities are available from Intel’s World Wide Web site (see Section 7.1).
Audio driver support is provided for the Microsoft Windows NT
†
Windows 95, and IBM OS/2
Warp† (versions 3.0 and 4.0) operating systems.
(versions 3.51 and 4.0), Microsoft
1.10.3 Audio Connectors
The audio connectors include the following:
• Back panel connectors: Line In, Line Out, Mic In (see Section 1.16.4)
• CD-ROM audio (ATAPI or 2 mm)
• Telephony (ATAPI style)
• MIDI/Game port header
• Line In (ATAPI style)
See Section 1.16.4 for the location and pinouts of the audio connectors.
1.10.3.1 CD-ROM Audio
An optional 1 x 4-pin ATAPI-style (J1F1) or 1 x 4-pin 2 mm (J1E1) connector is available for
connecting an internal CD-ROM drive to the audio mixer.
1.10.3.2 Telephony
An optional 1 x 4-pin ATAPI-style connector (J0E1) is available for connecting the monaural
audio signals of an internal telephony device, such as a modem, to the audio subsystem. A
monaural audio-in and audio-out signal interface is necessary for telephony applications such as
speakerphones, modem, and answering machines.
1.10.3.3 MIDI/Game Port Header
An optional 2 x 8-pin MIDI/Game port header (J2E2) is available for connecting MIDI devices and
joysticks.
An optional 1 x 4-pin ATAPI-style Line In connector (J0F2) is available for connecting the left and
right channel signals of an internal audio device to the audio subsystem. An audio-in signal
interface of this type is useful in applications such as TV tuners.
1.10.4 Hardware Wavetable Support
The optional hardware wavetable support is implemented with a Crystal CS9236 Wavetable Music
Synthesizer. The CS9236 device is a complete General MIDI wavetable music synthesizer on a
single chip. The MIDI interpreter, synthesis engine, effects processing, and all RAM and ROM
(including the wavetable sample ROM) are included on-chip. The CS9236 includes the following
features:
• General MIDI compliant
• 32-note polyphony at 44.1 kHz rate
• Independent reverb and chorus levels for each MIDI channel
1.11 Hardware Monitor Subsystem
The hardware monitor subsystem includes a National Semiconductor LM79 Microprocessor
System Hardware Monitor, an analog multiplexer, and a chassis security header. Its features
include:
• Management Level 3 functionality.
• Integrated temperature and voltage sense monitoring to detect levels above or below acceptable
values (+12 V, -12 V, +5 V, -5 V, and +3.3V). When suggested ratings for temperature, fan
speed, or voltage are exceeded, an interrupt is activated.
• Fan speed sensors for up to five fans with the onboard analog multiplexer.
• Header for an external chassis security feature.
• 8-bit I/O map to ISA bus or access from SMBus.
Figure 4 shows a block diagram of the hardware monitor subsystem.
26
LM79
Motherboard Description
Rear Chassis Fan
Front Chassis 1 Fan
Front Chassis 2 Fan
Control 3(8)
Status 4(8)
Limit 1(8)
Limit 2 (8)
Limit 17(8)
FAN Intvl
Timers (3)
POST Regs
(32 x 8)
Port 80/84
Shadow
2
I C I/F
Slave
CPU 1 Fan
CPU 2 Fan
Multi-
plexer
2 Pulse/Rev
2 Pulse/Rev
2 Pulse/Rev
Chassis
Security
Header
Power Switch
(Bypass)
BTI
VOLTAGE
+5 Sense
-5
+12
-12
+3.3
+2.5A
+2.5B
Temp
Sensor
Security
RESET
8 Bit
8 Ch
MUX
A/D
Figure 4. Block Diagram of Hardware Management Subsystem
SDA
SCL
VID[0...3]
OM06922
The 1 x 2-pin chassis security header (J0A1) can be connected to a normally-open mechanical
switch on the chassis. See Section 1.16 for the location and pinouts of the chassis security header.
1.12 EtherExpress PRO/100WfM PCI LAN Subsystem
The optional Intel EtherExpress PRO/100WfM PCI LAN subsystem (see Figure 5) is an
Ethernet
include:
•
•
•
•
•
†
LAN interface that provides both 10Base-T and 100Base-TX connectivity. Features
32-bit direct bus mastering on the PCI bus
Shared memory structure in the host memory that copies data directly to/from host memory
10Base-T and 100Base-TX capability using a single RJ-45 connector with connection and
activity status LEDs
IEEE 802.3µ Auto-Negotiation for the fastest available connection
Jumperless configuration; the LAN subsystem is completely software configurable
The Intel 82557 LAN Controller provides the following functions:
• CSMA/CD Protocol Engine
• PCI compatibility
• DMA engine for movement of commands, status, and network data across the PCI bus
• Standard MII interface for access to IEEE 802.3µ-compliant physical layer devices
(PIIX4)
OM06270A
1.12.2 10 / 100 Mbit/sec Physical Layer Interface
The physical layer interface is implemented by the Intel 82555 Physical Layer Interface (PHY)
device. This device provides:
• Complete functionality necessary for the 10Base-T and 100Base-TX interfaces; when in
10 Mbit/sec mode, the interface drives the cable directly
• A complete set of MII management registers for control and status reporting
• 802.3µ Auto-Negotiation for automatically establishing the best operating mode when
connected to other 10Base-T or 100Base-TX devices
1.12.3 Wake on LAN ASIC
The Wake on LAN ASIC performs remote wakeup of the motherboard via the onboard LAN
interface. When the system is powered off, the Wake on LAN ASIC remains powered by the 5 V
standby voltage. The ASIC monitors network traffic at the MII interface and when it detects a
Magic Packet
†
it asserts a wakeup signal that powers up the computer.
28
Motherboard Description
1.12.4 LAN Subsystem Software
The EtherExpress PRO/100WfM PCI LAN software provided includes setup/diagnostic software
(SETUP.EXE), a readme file viewer (README.EXE) and the drivers listed in Table 4. The LAN
software is available from Intel’s World Wide Web site (see Section 7.1).
Table 4.EtherExpress PRO/100WfM PCI Drivers
DriverDescriptionEnvironment(s)
E100BODI.COMNovell† ODINetWare† DOS Client
E100BODI.SYSNovell ODINetWare OS/2 Client
E100B.LANNovell ODINetWare 3.11 Server
NetWare 3.12 Server
NetWare 4.0x Server
NetWare NT Requester
NetWare for OS/2
E100B.DOSNDIS 2.0.1Windows for Workgroups 3.11
MS-DOS
E100B.OS2NDIS 2.0.1MS OS/2 1.3
IBM OS/2 2.11
IBM OS/2 Warp
E100B.SYSNDIS 3.XWindows 95
Windows NT 3.5x
E100BNT.SYSNDIS 4.0Windows NT 4.0
†
LANMAN 2.1
1.13 Wake on LAN Header
Header J6D1 is used to implement the Wake on LAN feature. Connect this header to a network
interface card (NIC) that supports the Wake on LAN technology. The NIC monitors network
traffic. When the NIC detects a Magic Packet, it asserts a signal through the Wake on LAN header
to wake up the computer. This signal can wake up the computer only when the power cord is still
plugged into the socket and the computer is turned off. Wake on LAN can be enabled through the
BIOS Setup program.
NOTE
✏
The computer’s power supply must provide sufficient +5 VSB current to the NIC; without enough
+5 VSB current, the Wake on LAN feature will not function and the motherboard may not boot.
Check the NIC’s documentation for its +5 VSB current requirements. See Section 1.22 for
information on the motherboard’s power requirements.
1.14 Wake on Modem
The Wake-on-Modem feature allows the computer to wake from Sleep mode when a call is
received on a telephony device, such as a modem. The first incoming call will power up the
motherboard, but a second call must be made to access the computer.
The onboard SCSI subsystem features the Adaptec AIC-7895, which contains a dual-channel SCSI
controller and a PCI bus master interface. The AIC-7895 supports the following:
• Narrow (8-bit, 50-pin) or Wide (16-bit, 68-pin) Fast SCSI providing 10-20 MB/sec throughput
• Burst data transfers on the PCI bus up to the maximum rate of 133 MB/sec per channel using
the on-chip 256-byte FIFO buffer
• RAIDport connector interface
• Two Wide 68-pin connectors
• One Narrow 50-pin connector
• Subsystem Vendor and Device ID support
• Spin down of SCSI drive
• SCAM (SCSI Configured Automatically) Level 2
1.15.1 SCSI Drivers and Utilities
SCSI drivers are available from Intel’s World Wide Web site (see Section 7.1). SCSI driver
support is provided for the Microsoft Windows NT
Windows 95, and IBM OS/2 Warp (versions 3.0 and 4.0) operating systems.
(versions 3.51 and 4.0), Microsoft
1.15.2 SCSI Interface
The AIC 7895 also offers active negation outputs and a disk activity output signal. Active
negation outputs reduce the chance of data errors by actively driving both polarities of the SCSI
bus, avoiding indeterminate voltage levels. The SCSI output drivers can directly drive a 48 mA
single-ended SCSI bus with no additional drivers. Synchronous SCSI can handle up to 15 REQ
control signals simultaneously.
1.15.3 SCSI Bus
Each channel’s SCSI data bus is 8- or 16-bits wide with odd ECC generated per byte. SCSI
control signals are the same for either bus width. The motherboard has three onboard SCSI
connectors. Channel A has a high-density 68-pin Wide connector, while channel B has a highdensity 68-pin Wide connector as well as a 50-pin Narrow connector (see Figure 7). On a 16-bit
wide SCSI bus, the AIC-7895 assigns the highest arbitration priority to the low byte of the 16-bit
word. This way, 16-bit targets can be mixed with 8-bit targets if the 8-bit devices are placed on the
low data byte. During chip powerdown, all inputs are disabled to reduce power consumption.
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