Intel® Core™ i7-900 Desktop
Processor Extreme Edition Series
®
and Intel
Core™ i7-900 Desktop
Processor Series on 32-nm Process
Datasheet, Volume 1
June 2011
Document # 323252-003
Page 2
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future
changes to them.
®
The Intel
as errata which may cause the product to deviate from published specifications.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time
processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number
progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
Core™ i7-900 desktop processor Extreme Edition series on 32-nm process ma y co ntain design defects or errors known
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technologyenabled chipset, BIOS and operating system. Performance will va ry de pe ndi ng on the specific hardware and software y ou use. For
more information including details on which processors support HT Technology, see
64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled
Intel
®
for Intel
depending on your hardware and software configuration s. See www .intel.com/info/em64t for more information in cluding details on
which processors support Intel
± Intel
for some uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on
64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary
®
®
Virtualization T echnology requires a compute r system with a processor, chipset, BIOS, virtual machine monitor (VMM) and
64 or consult with your system vendor for more information.
hardware and software configurations. Intel Virtualization Technology-enabled VMM applications are currently in development.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Enhanced Intel® SpeedStep Technology. See the Processor Spec Finder
or contact your Intel representative for more information.
Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com
.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Intel SpeedStep, Intel Core, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
The Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel® Core™
i7-900 desktop processor series on 32-nm process processor is intended for high
performance, high-end desktop systems. Several architectural and microarchitectural
enhancements have been added to this processor including six processor cores in the
processor package and increased shared cache.
®
The Intel
Core™ i7-970 desktop processor series on 32-nm process is a desktop multi-core
processor with these key technologies:
• Integrated memory control ler
• Point-to-point link interface based on Intel QuickPath Interconnect (Intel QPI)
Figure 1-1 shows the interfaces used with these new technologies.
Figure 1-1. High-Level View of Processor Interfaces
Core™ i7-900 desktop processor Extreme Edition series and and Intel®
Note:In this document the Intel® Core™ i7-900 desktop processor Extreme Edition series on
32-nm process will be referred to as “the processor.”
®
Note:The Intel
refers to the Intel
Note:The Intel
Intel
Core™ i7-900 desktop processor Extreme Edition series on 32-nm process
®
Core™ i7-900 desktop processor series on 32-nm process refers to the
®
Core™ i7-980 and i7-970 desktop processors.
®
Core™ i7-980X and i7-990X desktop processor Extreme Edition.
The processor is optimized for performance with the power efficiency of a low-power
microarchitecture.
This document provides DC electrical specifications, differential signaling specifications,
pinout and signal definitions, package mechanical specifications and thermal
requirements, and additional features pertinent to the implementation and operation of
the processor.
Datasheet, Volume 19
The processor is a multi-core processor built on the 32-nm process technology, that
uses up to 130 W thermal design power (TDP). The processor features an Intel QPI
point-to-point link capable of up to 6.4 GT/s, 12 MB Level 3 cache, and an integrated
memory controller.
Page 10
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2),
Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The
processor supports several Advanced Technologies: Intel
Enhanced Intel SpeedStep® Technology, Intel® Virtualization Technology (Intel® VT),
Turbo Boost Technology, and Hyper-Threading Technology.
1.1Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when VTTPWRGOOD is high, the VTT power rail is
stable.
‘_N’ and ‘_P’ after a signal name refers to a differential pair.
Commonly used terms are explained here for clarification:
®
• Intel
Core™ i7-900 desktop processor series on 32-nm process — The entire
product, including processor substrate and integrated heat spreader (IHS).
• 1366-land LGA package — The processor is available in a Flip-Chip Land Grid
Array (FC-LGA) package, consisting of the processor mounted on a land grid array
substrate with an integrated heat spreader (IHS).
• LGA1366 Socket — The processor (in the LGA 1366 package) mates with the
system board through this surface mount, 1366-contact socket.
• DDR3 — Double Data Rate 3 Synchronous Dynamic Random Access Memory
(SDRAM) is the name of the new DDR memory standard that is being developed as
the successor to DDR2 SRDRAM.
• Intel
point-to-point link-based electrical interconnect specification for Intel processors
and chipsets.
• Intel® QuickPath Technology Memor y Controller — A memory controller that
is integrated into the processor die.
• Integrated Heat Spreader (IHS) — A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Functional Operation — Refers to the normal operating conditions in which all
processor specifications, including DC, AC, signal quality, mechanical, and thermal,
are satisfied.
• Enhanced Intel SpeedStep
Technology allows the operating system to reduce power consumption when
performance is not needed.
• Execute Disable Bit — Execute Disable allows memory to be marked as
executable or non-executable when combined with a supporting operating system.
If code attempts to run in non-executable memory , the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
for more detailed information. Refer to http://developer.intel.com/ for future
reference on up to date nomenclatures.
• Intel
allowing the processor to execute operating systems and applications written to
Core™ i7-900 desktop processor Extreme Edition series and Intel®
®
QuickPath Interconnect (Intel® QPI)— Intel QPI is a cache-coherent,
®
64 Architecture — An enhancement to the Intel IA-32 architecture,
®
64 Technology (Intel® 64),
®
Technology — Enhanced Intel SpeedStep
®
Architecture Software Developer's Manual
Introduction
10Datasheet, Volume 1
Page 11
Introduction
take advantage of Intel 64. Further details on the Intel 64 architecture and
programming model can be found at
http://developer.intel.com/technology/intel64/.
• Intel® Virtualization Technology (Intel® VT) — A set of hardware
enhancements to Intel server and client platforms that can improve virtualization
solutions. Intel
®
VT provides a foundation for widely-deployed virtualization
solutions and enables a more robust hardware assisted virtualization solution. More
information can be found at: http://www.intel.com/technology/virtualization/
• Unit Interval (UI) — Signaling convention that is binary and unidirectional. In
this binary signaling, one bit is sent for every edge of the forwarded clock, whether
it is a rising edge or a falling edge. If a number of edges are collected at instances
, t2, tn,...., tk then the UI at instance “n” is defined as:
t
1
• Jitter — Any timing variation of a transition edge or edges from the defined Unit
Interval.
• Storage Conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray , or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
• OEM — Original Equipment Manufacturer.
1.2References
Material and concepts available in the following documents may be beneficial when
reading this document.
Table 1-1.References
®
Core™ i7-900 Desktop Processor Extreme Edition Series and
Intel
®
Intel
Core™ i7-900 Desktop Processor Series on 32-nm Process
Specification Update
®
Intel
Core™ i7-900 Desktop Processor Extreme Edition Series on
32-nm Process Datasheet, Volume 2
®
Core™ i7-900 Desktop Processor Extreme Edition Series and
Intel
®
Core™ i7-900 Desktop Processor Series and LGA1366 Socket
The processor provides an Intel QPI port for high speed serial transfer between other
Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links
(for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of
opposite-polarity (D_P, D_N) signals are used.
On-die termination (ODT) provided on the processor silicon and termination is to V
Intel chipsets also provide ODT; thus, eliminating the need to terminate the Intel QPI
links on the system board.
Intel strongly recommends performing analog simulations of the Intel QPI interface.
Figure 2-1 illustrates the active ODT. Signal listings are included in Table 2-3 and
Table 2-4. See Chapter 5 for the pin signal definitions. All Intel QPI signals are in the
differential signal group.
Figure 2-1. Active ODT for a Differential Link Example
2.2Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 210 VCC pads
and 119 VSS pads associated with VCC; 8 VTTA pads and 5 VSS pads associated with
; 28 VTTD pads and 17 VSS pads associated with V
V
TTA
pads associated with V
VCCPLL lands must be connected to their respective processor power planes, while all
VSS lands must be connected to the system ground plane. The processor VCC lands
must be supplied with the voltage determined by the processor Voltage IDentification
(VID) signals. Table 2-1 specifies the voltage level for the various VIDs.
; and 3 VCCPLL pads. All VCCP, VTTA, VTTD, VDDQ, and
DDQ
, 28 VDDQ pads and 17 VSS
TTD
SS
.
2.3Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Larger bulk storage (C
current during longer lasting changes in current demand; such as, coming out of an idle
condition. Similarly, capacitors act as a storage well for current when entering an idle
Datasheet, Volume 113
), such as electrolytic capacitors, supply
BULK
Page 14
Electrical Specifications
condition from a running condition. Care must be taken in the baseboard design to
ensure that the voltage provided to the processor remains within the specifications
listed in Table 2-7. Failure to do so can result in timing violations or reduced lifetime of
the processor.
2.3.1VCC, V
Voltage regulator solutions need to provide bulk capacitance and the base b oard
designer must assure a low interconnect resistance from the regulator to the LGA1366
socket. Bulk decoupling must be provided on the baseboard to handle large current
swings. The power delivery solution must insure the voltage and current specifications
are met (as defined in Table 2-7).
TTA
, V
TTD
, V
Decoupling
DDQ
2.4Processor Clocking (BCLK_DP, BCLK_DN)
The processor core, Intel QPI, and integrated memory controller frequencies are
generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side
bus architecture, there is no direct link between core frequency and Intel QPI link
frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum
core frequency, Intel QPI link frequency and integrated memory controller frequency,
are set during manufacturing. It is possible to override the processor core frequency
setting using software. This permits operation at lower core frequencies than the
factory set maximum core frequency.
The processor’s maximum non-turbo core frequency is configured during power-on
reset by using values stored internally during manufacturing. The stored value sets the
highest core multiplier at which the particular processor can operate. If lower maximum
non-turbo speeds are desired, the appropriate ratio can be configured using the
CLOCK_FLEX_MAX MSR.
The processor uses differential clocks (B CLK_DP, BCLK_DN). Clock multiplying within
the processor is provided by the internal phase locked loop (PLL) that requires a
constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum
clocking. The processor core frequency is determined by multiplying the ratio by
133 MHz.
2.4.1PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Table 2-7 for DC
specifications.
14Datasheet, Volume 1
Page 15
Electrical Specifications
2.5Voltage Identification (VID)
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator Down (VRD) 11.1 Design Guidelines. The voltage set by the VID signals is
the reference voltage regulator output voltage to be delivered to the processor VCC
pins. VID signals are CMOS push/pull drivers. Refer to Table 2-15 for the DC
specifications for these signals. The VID codes will change due to temperature and/or
current load changes in order to minimize the power of the part. A voltage range is
provided in Table 2-7. The specifications have been set such that one voltage regulator
can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing such that two devices
at the same core frequency may have different default VID settings. This is reflected by
the VID range values provided in Table 2-1.
The processor
uses eight voltage identification signals, VID[7:0], to support automatic
selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of
VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low
voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
must disable itself. See the Voltage Regulator Down (VRD) 11.1 Design Guidelines for
further details.
The processor
provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the
loadline. It should be noted that a low-to-high or high-to-low voltage state change will
result in as many VID transitions as necessary to reach the target core voltage.
T ransitions above the maximum specified VID are not permitted. Table 2-8 includes VID
step sizes and DC shift ranges. Minimum and maximum voltages must be maintained
as shown in Table 2-8.
The VR used must be capable of regulating its output to the value defined by the new
VID. DC specifications for dynamic VID transitions are included in Table 2-7 and
Table 2-8. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for
further details.
Datasheet, Volume 115
Page 16
Electrical Specifications
Table 2-1.Voltage Identification Definition (Sheet 1 of 2)
1. The MSID[2:0] signals are provided to indicate the market segment for the processor and may be used for
future processor compatibility or for keying.
Core™ i7-900 desktop processor Extreme Edition series and
®
Core™ i7-900 desktop processor series on 32-nm process
Intel
2.6Reserved or Unused Signals
All Reserved (RSVD) signals must remain unconnected. Connection of these signals to
VCC, V
result in component malfunction or incompatibility with future processors. See
Chapter 4 for a land listing of the processor and the location of all Reserved signals.
TTA
, V
TTD
, V
DDQ
, V
, VSS, or to any other signal (including each other) can
CCPLL
Electrical Specifications
1
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level, except for unused integrated memory controller inputs,
outputs, and bi-directional pins that may be left floating. Unused active high inputs
should be connected through a resistor to ground (V
). Unused outputs may be left
SS
unconnected; however, this may interfere with some Test Access Port (TAP) functions,
complicate debug probing, and prevent boundary scan testing. A resistor must be used
when tying bi-directional signals to power or ground. When tying any signal to power or
ground, a resistor will also allow for system testability.
18Datasheet, Volume 1
Page 19
Electrical Specifications
2.7Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board. The signals that have ODT are listed in Table 2-4.
Table 2-3.Signal Groups (Sheet 1 of 2)
Signal GroupTypeSignals
System Reference Clock
DifferentialClock InputBCLK_DP, BCLK_DN
Intel QPI Signal Groups
DifferentialIntel QPI Input
DifferentialIntel QPI Output
DDR3 Reference Clocks
DifferentialDDR3 Output
1,2
QPI_DRX_D[N/P][19:0], QPI_CLKRX_DP,
QPI_CLKRX_DN
QPI_DTX_D[N/P][19:0], QPI_CLKTX_DP,
QPI_CLKTX_DN
DDR{0/1/2}_CLK[D/P][3:0]
DDR3 Command Signals
Single endedCMOS Output
Single endedAsynchronous OutputDDR{0/1/2}_RESET#
DDR3 Control Signals
Single endedCMOS Output
DDR3 Data Signals
Single endedCMOS Bi-directionalDDR{0/1/2}_DQ[63:0]
DifferentialCMOS Bi-directionalDDR{0/1/2}_DQS_[N/P][7:0]
TAP
Single endedTAP InputTCK, TDI, TMS, TRST#
Single endedGTL OutputTDO
Control Sideband
Single endedAsynchronous GTL OutputPRDY#
Single endedAsynchronous GTL InputPREQ#
Single endedGTL Bi-directionalCAT_ERR#, BPM#[7:0]
Single EndedAsynchronous Bi-directionalPECI
Single EndedAnalog InputCOMP0, QPI_CMP[0], DDR_COMP[2:0]
• D DR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_PAR_ERR#[0:2], VDDPWRGOOD
• BCLK_ITP_D[N/P]
•PECI
• BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD
Note:
1.Unless otherwise specified, signals have ODT in the package with 50 pulldown to V
2.PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35 pullup to V
3.VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 k to 20 k pulldown
4.TRST# has ODT in package with a 1 k to 5 k pullup to V
5.All DDR signals are terminated to VDDQ/2
6.DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
7.While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 1–5 k
8.While TCK does not have On-Die Termination, this signal is weakly pulled down using a 1–5 kresistor to
.
to V
SS
resistor to V
V
.
SS
.
TT
TT
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least eight BCLKs for the processor to recognize the proper signal state. See
Section 2.11 for the DC specifications. See Chapter 6 for additional timing
requirements for entering and leaving the low power states.
2.8Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
.
SS
.
TT
20Datasheet, Volume 1
Page 21
Electrical Specifications
2.9Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read the DTS temperature for thermal management and fan speed control. More
detailed information may be found in the Platform Environment Control Interface
(PECI) Specification.
2.9.1DC Characteristics
The PECI interface operates at a nominal voltage set by V
specifications shown in Table 2-5 is used with devices normally operating from a V
interface supply . V
nominal levels will vary between processor families. All PECI
TTD
devices will operate at the V
system. For specific nominal V
Table 2-5.PECI DC Electrical Limits
SymbolDefinition and ConditionsMinMaxUnitsNotes
V
V
hysteresis
V
V
I
source
I
sink
I
leak+
I
leak-
C
V
noise
Note:
1.V
2.The leakage specification applies to powered devices on the PECI bus.
Input Voltage Range-0.150V
in
Hysteresis0.1 * V
Negative-edge threshold voltage0.275 * V
n
Positive-edge threshold voltage0.550 * V
p
High level output source
= 0.75 * V
(V
OH
Low level output sink
= 0.25 * V
(V
OL
High impedance state leakage to V
= VOL)
(V
leak
High impedance leakage to GND
= VOH)
(V
leak
Bus capacitance per nodeN/A10pF
bus
Signal noise immunity above 300 MHz0.1 * V
supplies the PECI interface. PECI behavior does not affect V
TTD
TTD
TTD
. The set of DC electrical
TTD
level determined by the processor installed in the
TTD
levels, refer to Table 2-7.
TTD
V
TTD
TTD
TTD
TTD
)
)
TTD
-6.0N/AmA
0.51.0mA
N/A100µA2
N/A100µA2
TTD
TTD
N/AV
0.500 * V
0.725 * V
min/max specifications.
TTD
TTD
N/AV
V
V
p-p
TTD
1
Datasheet, Volume 121
Page 22
2.9.2Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TTD
PECI Ground
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 2-2 as a guide for input buffer design.
Figure 2-2. Input Device Hysteresis
Electrical Specifications
2.10Absolute Maximum and Minimum Ratings
Table 2-6 specifies absolute maximum and minimum ratings, which lie outside the
functional limits of the processor. Only within specified operation limits can functionality
and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor l ong-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from ElectroStatic Discharge (ESD), precautions should always be taken to avoid high static
voltages or electric fields.
22Datasheet, Volume 1
Page 23
Electrical Specifications
.
Table 2-6.Processor Absolute Minimum and Maximum Ratings
SymbolParameterMinMaxUnit Notes
V
CC
V
TTA
V
TTD
V
DDQ
V
CCPLL
T
CASE
T
STORAGE
Notes:
1.For functional ope ratio n, all processor electri cal, signal quality, mechanical and thermal specifications must
be satisfied.
2.Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3.V
Processor Core voltage with respect to V
Voltage for the analog portion of the integrated
memory controller, QPI link and Shared Cache
with respect to V
Voltage for the digital portion of the integrated
memory controller, QPI link and Shared Cache
with respect to V
Processor I/O supply voltage for DDR3 with
respect to V
Processor PLL voltage with respect to V
Processor case temperatureSee
Storage temperatureSee
TTA
and V
should be derived from the same VR.
TTD
SS
SS
SS
SS
SS
-0.31.4V
-0.31.4V3
-0.31.4V3
-0.31.8V
-0.32.0V
Chapter 6
Chapter 6
See
Chapter 6
See
Chapter 6
1, 2
C
C
2.11Processor DC Specifications
The processor DC specifications in this section are defined at the processor
pads, unless noted otherwise. See Chapter 4 for the processor land listings and
Chapter 5 for signal definitions. Voltage and current specifications are detailed in
Table 2-7. For platform planning, refer to Table 2-8 that provides V
transient tolerances. This same information is presented graphically in Figure 2-3.
The DC specifications for the DDR3 signals are listed in Table 2-11. Control Sideband
and Test Access Port (TAP) are listed in Table 2-12 through Table 2-15.
Table 2-7 through Table 2-15 list the DC specifications for the processor and are valid
only while meeting specifications for case temperature (T
“Thermal Specifications”), clock frequency, and input voltages. Care should be taken to
read all notes associated with each parameter.
static and
CC
as specified in Chapter 6,
CASE
Datasheet, Volume 123
Page 24
2.11.1DC Voltage and Current Specification
Notes:
Table 2-7.V oltage and Curre nt Specificat ions
SymbolParameterMinTypMaxUnitNotes
VIDVID range0.81.375V
V
for processor core
CC
3.46 GHz
3.33 GHz
3.33 GHz
3.20 GHz
for processor
I
CC
3.46 GHz
3.33 GHz
3.33 GHz
3.20 GHz
See Table 2-8 and Figure 2-3V
See Table 2-10 and Figure 2-4V
See Table 2-9 and Figure 2-4V5
1.711.81.89V
——
——5A
——23A
——1A
V
CC
V
TTA
V
TTD
V
DDQ
V
CCPLL
I
CC
I
TTA
I
TTD
I
DDQ
I
S3
DDQ
I
CC_VCCPLL
Processor
Number
i7-990X
i7-980X
i7-980
i7-970
Voltage for the analog portion of the
integrated memory controller, QPI link
and Shared Cache
Voltage for the digital portion of the
integrated memory controller, QPI link
and Shared Cache
Processor I/O supply voltage for DDR3 1.4251.51.575V
PLL supply voltage (DC + AC
specification)
Processor
Number
i7-990X
i7-980X
i7-980
i7-970
Current for the analog portion of the
integrated memory controller, QPI link
and Shared Cache
Current for the digital portion of the
integrated memory controller, QPI link
and Shared Cache
Processor I/O supply current for DDR3 ——6A
Processor I/O supply current for DDR3
while in S3
PLL supply current (DC + AC specification)——1.1A
Electrical Specifications
1
2
3,4
5
145
145
A
6
145
145
7
1.Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later date
2.Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibr ated during manufacturing
such that two processors at the same frequency may have different settings wit hin the VID range. Not e that
this differs from the VID employed by the processor during a power management event (Adaptive Thermal
Monitor, Enhanced Intel SpeedStep
3.The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
4.Refer to Table 2-8 and Figure 2-3 for the minimum, typical, and maximum V
processor should not be subjected to any V
5.See Table 2-9 for details on VTT Voltage Identification. See Table 2-10 and Figure 2-4 for details on the VTT
Loadline
6.I
7.This specification is based on a processor temperature, as reported by the DTS, of less than or equal to
2.This table is intended to aid in reading discrete points on Figure 2-3.
3.The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SE NSE land s. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for socket load line
CC_MIN
and V
loadlines represent static and transient limits. See Section 2.11.2 for VCC
CC_MAX
guidelines and VR implementation.
Datasheet, Volume 125
Page 26
Figure 2-3. VCC Static and Transient Tolerance Load Lines
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
0 102030405060708090100110120130140
V
c
c
V
Icc [ A ]
Vcc Maximum
Vcc Typica l
Vcc Mini mu m
Electrical Specifications
Table 2-9. VTT Voltage Identification (VID) Definition
1.The associated voltage with the VTT_VID codes listed in this table do not match the Voltage RegulatorDown (VRD) 11.1 Design Guidelines, they include a +20 mV offset.
2.This is a typical voltage. See Table 2-10 for VTT_Max and VTT_Min voltage.
2. The loadlines specify voltage limits at the die measured at the VTT_SENSE and VSS_SENSE_VTT lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from the processor VTT_SENSE and
TTA
and I
TTD
.
VSS_SENSE_VTT lands.
Datasheet, Volume 127
Page 28
Figure 2-4. VTT Static and Transient Tolerance Load Line
-0.2125
-0.2000
-0.1875
-0.1750
-0.1625
-0.1500
-0.1375
-0.1250
-0.1125
-0.1000
-0.0875
-0.0750
-0.0625
-0.0500
-0.0375
-0.0250
-0.0125
0.0000
0.0125
0.0250
0.0375
0.0500
0510152025
V
t
t
V
Itt [A] (sum of Itta and Ittd)
Vtt Maximum
Vtt Typical
Vtt Mini mu m
Electrical Specifications
Table 2-11. D DR3 Signal Group DC Specificati ons
SymbolParameterMinTypMaxUnitsNotes
V
Input Low Voltage——0.43*V
IL
V
Input High Voltage0.57*V
IH
V
V
R
R
28Datasheet, Volume 1
R
R
R
DDR_COMP0
DDR_COMP1
DDR_COMP2
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
IL
value.
DDQ
—
—
V
(R
21—317
16—24
25—75
21—31
21—33
——V3
(V
/ 2)* (R
DDQ
(R
ON+RVTT_TERM
– ((V
DDQ
/(RON+R
ON
ON
/ 2)*
DDQ
VTT_TERM
/
))
))
DDQ
—V
—V4
V2,4
1
Page 29
Electrical Specifications
3.VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
and VOH may experience excursions above V
4.V
IH
signal quality specifications.
5.COMP resistance must be provided on the system board with 1% resistors. DDR_COMP[2:0] resistors are
to V
6.This is the pull down driver resistance.
SS
Table 2-12. RESET# Signal DC Specifications
SymbolParameterMinTypMaxUnitsNotes
V
Input Low Voltage——0.40 * V
IL
V
Input High Voltage0.80 * V
IH
I
Input Leakage Current——± 200A3
LI
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For Vin between 0 V and V
4.V
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
Table 2-13. TAP Signal Group DC Specifications
SymbolParameterMinTypMaxUnitsNotes
V
Input Low Voltage——0.40 * V
IL
V
Input High Voltage 0.75 * V
IH
V
V
RonBuffer on Resistance10—18
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For Vin between 0 V and V
4.V
Output Low Voltage
OL
Output High VoltageV
OH
I
Input Leakage Current——± 200A3
LI
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
——
TTA
. However, input signal drivers must comply with the
DDQ
V2
V2
V
)
TTA
TTA
TTA
——V2,4
.
TTA
TTA
——V2,4
V
* RON /
TTA
+ R
(R
ON
sys_term
——V2,4
.
TTA
1
1
2
Datasheet, Volume 129
Page 30
Table 2-14. P WRG OOD Signal Group DC Specificati ons
SymbolParameterMinTypMaxUnitsNotes
Input Low Voltage for
V
VCCPWRGOOD and VTTPWRGOOD
IL
Signals
Input Low Voltage for
V
IL
VDDPWRGOOD Signal
Input High Voltage for
VCCPWRGOOD and VTTPWRGOOD
V
IH
Signals
Input High Voltage for
V
IH
VDDPWRGOOD Signal
RonBuffer on Resistance10—18
I
Input Leakage Current——± 200A3
LI
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For Vin between 0 V and V
4.V
5.This specification applies to VCCPWRGOOD and VTTPWRGOOD
6.This specification applies to VDDPWRGOOD
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
——0.25 * V
——0.29V6
0.75 * V
0.87
TTA
Electrical Specifications
1
TTA
V2,5
——V2,5
——V6
.
TTA
Table 2-15. Control Sideband Signal Group DC Specifications
SymbolParameterMinTypMaxUnitsNotes
V
Input Low Voltage——0.64 * V
IL
V
Input Low Voltage——0.61 * V
IL
V
Input High Voltage0.76 * V
IH
V
V
Output Low Voltage
OL
Output High VoltageV
OH
TTA
——
TTA
RonBuffer on Resistance10—18
Ron
Buffer on Resistance for
VID[7:0]
I
Input Leakage Current——± 200A3
LI
—100—
COMP0COMP Resistance49.449.950.405
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For Vin between 0 V and V
4.V
5.COMP resistance must be provided on the system board with 1% resistors. COMP0 resistors are to V
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
——V2
——V2,4
V
* RON / (RON
TTA
+ R
sys_term
TTA
1
TTA
TTA
)
V2
V2
V2,4
.
.
SS
30Datasheet, Volume 1
Page 31
Electrical Specifications
Time
Example Overshoot Waveform
Voltage (V)
VID
VID + V
OS
T
OS
V
OS
TOS: Overshoot time above VID
V
OS
: Overshoot above VID
2.11.2VCC Overshoot Specification
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high-to-low current load condition. This overshoot
cannot exceed VID + V
OS_MAX
VID). These specifications apply to the processor die voltage as measured across the
VCC_SENSE and VSS_SENSE lands.
(V
OS_MAX
is the maximum allowable overshoot above
Table 2-16. V
Overshoot Specifications
CC
SymbolParameterMinMaxUnitsFigureNotes
V
OS_MAX
T
OS_MAX
Magnitude of V
Time duration of V
CCP
overshoot above VID—50mV2-5
overshoot above VID—25µs2-5
CCP
Figure 2-5. VCC Overshoot Example Waveform
2.11.3Die Voltage Validation
Core voltage (VCC) overshoot events at the processor must meet the specifications in
Table 2-16 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot
events that are < 10 ns in duration may be ignored. These measurements of processor
die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.
The processor Intel QPI specifications in this section are defined at the processor pins.
Routing topologies are dependent on the processors supported and the chipset used in
the design. In most cases, termination resistors are not required as these are
integrated into the processor silicon.
Table 2-17. Intel
®
QuickPath Interconnect (Intel QPI) Specifications
SymbolParameterMinNomMaxUnitNotes
UIavg
T
slew-rise-fall-pin
Average UI size at “x” GT/s
(Where x= 4.8 GT/s, 6.4 GT/s, etc.)
Defined as the slope of the rising or
falling waveform as measured between
±100 mV of the differential transmitter
output, for any data or clock.
0.999 *
nominal
1000/f
1.001 *
nominal
10—25V / nsec
psec
Defined as:
Z
TX_LOW_CM_DC
± (max(Z
min(Z
expressed in%, over full range of Tx
TX_LOW_CM_DC
TX_LOW_CM_DC)) /ZTX_LOW_CM_DC
) –
-606
% of
Z
TX_LOW_CM_DC
single ended voltage
Z
RX_LOW_CM_DC
Defined as: ±(max(Z
min(Z
TX_LOW_CM_DC)) /ZTX_LOW_CM_DC
expressed in%, over full range of Tx
single ended voltage
TX_LOW_CM_DC
) –
-606
% of
Z
TX_LOW_CM_DC
# of UI over which the ey e mask voltage
N
MIN-UI-Validation
Z
TX_HIGH_CM_DC
Z
RX_HIGH_CM_DC
Z
TX_LINK_DETECT
T
Refclk-Tx-Variability
L
D+/D-RX-Skew
T
CLK_DET
T
CLK_FREQ_DET
BER
Lane
TX
EQ-error
and timing specification needs to be
validated
Single ended DC impedance to GND for
either D+ or D- of any data bit at Tx
Single ended DC impedance to GND for
either D+ or D- of any data bit at Tx
Link Detection Resistor
Phase variability between reference Clk
(at Tx input) and Tx output.
Phase skew between D+ and D- lines for
any data bit at Rx
Time taken by clock detector to observe
clock stability
Time taken by clock frequency detector
to decide slow vs operational clock after
stable clock
Bit Error Rate per lane valid for 4.8 GT/s
and 6.4 GT/s
% error in Tx equalization setting as
measured by errors in DC levels when
sending a steady “1”.
1,000,000——
10 k——
10 k——
500—2000
——500psec
——0.03UI
——20KUI
——32
Clock Cycles
——1.0E-14Events
-10010% of V
Reference
O
QPI_CMP[0]COMP Resistance20.792121.21
1
2
3
1. Indicates the output impedance of the transmitter during initialization when the transmitter is “OFF”, that is, the output driver
is disconnected and only the minimum termination is connected. The link detection resistor is assumed not connected when
specifying this parameter.
2. Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination is connected.
3. COMP resistance must be provided on the system board with 1% resistors. QPI_CMP[0] resistors are to V
SS.
32Datasheet, Volume 1
Page 33
Electrical Specifications
Notes:
Table 2-18. Parameter Values for Intel® QuickPath Interconnect (Intel® QPI) Channel at
6.4 GT/s
Symbol
1
ParameterMinNomMaxUnitNotes
DC resistance of Tx terminations at half the
Z
TX_LOW_CM_DC
Z
RX_LOW_CM_DC
V
Tx-diff-pp-pin
V
Tx-cm-dc-pin
V
Tx-cm-ac-pin
TX
duty-pin
TX
jitUI-UI-1E-7pin
TX
jitUI-UI-1E-9pin
single ended swing (which is usually 0.25*V
diff-pp-pin
DC resistance of Rx terminations at half the
single ended swing (which is usually 0.25*V
diff-pp-pin
) bias point
) bias point
Tx-
Tx-
Transmitter Differential swing
T ransmitter output DC common mode, defined as
average of V
T rans mitter output AC common mode, defi ned as
((V
+ VD–)/2 – V
D+
and VD-
D+
TX-cm-dc-pin
).
Average of UI-UI jitter
UI-UI jitter measured at Tx output pins with 1E-7
probability
UI-UI jitter measured at Tx output pins with 1E-9
probability
38—52ohms
38—52ohms
800—1400mV
0.23—27
–0.0375—0.0375
-0.05—0.05UI
-0.07—0.07UI
-0.075—0.075UI
Fraction of
V
TX-diff-pp-pin
Fraction of
V
TX-diff-pp-pin
P-p accumulated jitter out of any Tx data or clock
TX
clk-acc-jit-N_UI-1E-7
TX
clk-acc-jit-N_UI-1E-9
T
Tx-data-clk-skew-pin
T
Rx-data-clk-skew-pin
over 0 n N UI where N=12, measured with
1E-7 probability.
P-p accumulated jitter out of any Tx data or clock
over 0 n N UI where N=12, measured with 1E9 probability.
Delay of any data lane relative to clock lane, as
measured at Tx output (UI)
Delay of any data lane relative to the clock lane,
as measured at the end of Tx+Channel. This
parameter is a collective sum of effects of data
clock mismatches in Tx and on the medium
connecting Tx and Rx. (UI).
0—0.18UI
0—0.2UI
-0.5—0.5UI
-1—4UI
DC common mode ranges at the Rx input for any
V
Rx-cm-dc-pin
V
Rx-cm-ac-pin
T
Rx-margin
V
Rx-margin
T
Rx-margin-RxEQ
data or clock channel, d
and V
AC common mode ranges at the Rx input for any
data or clock channel, defined as ((VD+ + VD-)/2
D-
(mV)
efined as average of VD+
– VRX-cm-dc-pin).
Measured timing margin during receiver
margining with any receiver equalizer off
Measured voltage margin during receiver
margining with receiver equalizer off
Measured timing margin during receiver
margining with receiver equalizer on and at the
optimum setting that maximizes the timing
90—350mV
–50—50mV
0.1—UI
40—mV
0.12—UI
margin
Measured voltage margin during receiver
V
Rx-margin-RxEQ
margining with receiver equalizer on and at the
optimum setting that maximizes the voltage
50—mV
margin
1. It is expected that the receiver will have equalization, which will boost received voltage and mitigate timing jitter, with the
minimum level of swing specified. Platform electrical design should determine the optimum level of equalization necessary,
depending on the link.
§
Datasheet, Volume 133
Page 34
Electrical Specifications
34Datasheet, Volume 1
Page 35
Package Mechanical Specifications
IHS
Substrate
LGA1366 Socket
System Board
Capacitors
TIM
IHS
Substrate
LGA
System Board
Capacitors
Die
TIM
3Package Mechanical
Specifications
The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with
the motherboard using an LGA1366 socket. The package consists of a processor
mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to
the package substrate and core and serves as the mating surface for processor thermal
solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package
components and how they are assembled together. Refer to the appropriate processor
Thermal and Mechanical Design Guidelines (see Section 1.2) for complete details on
the LGA1366 socket.
The package components shown in Figure 3-1 include the following:
• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors
Figure 3-1. Processor Package Assembly Sketch
Note:
1.Socket and motherboard are included for reference and are not part of the processor package.
3.1Package Mechanical Drawing
The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The
drawings include dimensions necessary to design a thermal solution for the processor.
These dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm.
• Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the appropriate processor Thermal
and Mechanical Design Guidelines (see Section 1.2).
Datasheet, Volume 135
Page 36
Figure 3-2. Processor Package Drawing (Sheet 1 of 2)
8 7 6 5 4 3 2
H
G
F
E
D
C
B
A
8 7 6 5 4 3 2 1
H
G
F
E
D
C
B
A
A
A
R
D
E
C
C
4X RM
1
M
2
M
3
F
4
F
2
B1C
1
C
3
B
2
C
2
C
4
G
2
G
1
H
1
H
2
J
1
J
2
0.02
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS
MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
D7612617
DWG. NOSHT. REV
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS
MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
D7612617
DWG. NOSHT. REV
DEPARTMENT
2200 MISSION COLLEGE BLVD.
P.O. BOX 58119
SANTA CLARA, CA 95052-8119
TITLE
EMTS DRAWING
SIZE DRAWING NUMBERREV
A1D761267
SCALE: 2:1
DO NOT SCALE DRAWING
SHEET 1 OF 2
FINISHMATERIAL
DATEAPPROVED BY
DATECHECKED BY
DATEDRAWN BY
DATEDESIGNED BY
UNLESS OTHERWISE SPECIFIED
INTERPRET DIMENSIONS AND TOLERANCES
IN ACCORDANCE WITH ASME Y14.5M-1994
DIMENSIONS ARE IN MILLIMETERS
ALL UNTOLERANCED LINEAR
DIMENSIONS ±0
ANGLES ±0.5
THIRD ANGLE PROJECTION
SEE DETAIL B
SEE DETAIL B
SEE DETAIL B
SEE DETAIL B
IHS LID
SEE DETAIL B
PIN 1
SEE DETAIL C
PIN 1
BAAY AWAV AU
AT
ARAP ANAM ALAK AJAH AGAF AEAD ACAB AAY WV UT RP NM LK JH GF ED CB A
ARAP ANAM ALAK AJAH AGAF AEAD ACAB AAY WV UT RP NM LK JH GF ED CB A
DETAIL D
SCALE 15:1
0.23 C H E
M N
NM
R
2
DETAIL
E
SCALE 15:1
0.23 C H G
J K
KJ
R
1
4X
SURFACE
TEST PAD AREA
SYMBOL
MILLIMETERS
COMMENTS
MINMAX
R
1
R1.09--
R
2
R1.09--
T
1
0.2--
T
2
11.7--
V
1
0.2--
V
2
11.7--
Figure 3-3. Processor Package Drawing (Sheet 2 of 2)
Datasheet, Volume 137
Page 38
Package Mechanical Specifications
3.2Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
top-side or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
3.3Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
.
Table 3-1.Processor Loading Specifications
thermal and mechanical solution.
ParameterMaximumNotes
Static Compressive Load934 N [210 lbf]1, 2, 3
Dynamic Compressive Load1834 N [410 lbf] [max static
compressive + dynamic load]
1, 3, 4
Notes:
1.These specifications apply to un iform compressive loading in a direction normal to the processor IHS.
2.This is the minimum and maximum static force that can be applied by the heatsink and retention solution
to maintain the heatsink and processor interface.
3.These specifications are based on limited testing for design characterization. Loading limits are for the
package only and do not include the limits of the processor socket.
4.Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
3.4Package Handling Guidelines
Table 3-2 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 3-2.Package Handling Guidelines
ParameterMaximum RecommendedNotes
Shear70 lbsTensile25 lbsTorque35 in.lbs-
3.5Package Insertion Specifications
The processor can be inserted into and removed from an LGA1366 socket 15 times. The
socket should meet the LGA1366 requirements detailed in the appropriate processor
Thermal and Mechanical Design Guidelines (see Section 1.2).
Figure 3-4 shows the top-side markings on the processor. This diagram is to aid in the
identification of the processor.
Figure 3-4. Processor Top-side Markings
Datasheet, Volume 139
Page 40
Package Mechanical Specifications
3.9Processor Land Coordinates
Figure 3-5 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
Figure 3-5. Processor Land Coordinates and Quadrants, Top View
§
40Datasheet, Volume 1
Page 41
Land Listing
4Land Listing
This chapter provides sorted land lists in Table 4-1 and Table 4-2. Table 4-1 is a listing
of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all
processor lands ordered by land number.
DDR{0/1/2}_CS[5:4]#
DDR{0/1/2}_DQ[63:0]I/ODDR3 Data bits.1
IDifferential bus clock input to the processor.
OBuffered differential bus clock pair to ITP.
BPM#[7:0] are breakpoint and performance monitor signals.
They are outputs from the processor that indicate the status
of breakpoints and programmable counters used for
monitoring processor perf ormance.
Indicates that the system has experienced a catastrophic erro r
and cannot continue to operate. The processor will set this for
non-recoverable machine check errors and other internal
unrecoverable error. Since this is an I/O pin, external agents
are allowed to assert this pin which will cause the processor to
take a machine check exception.
Impedance compensation must be terminated on the system
board using a precision resistor.
I
Intel QPI received clock is the input clock that corresponds to
the received data.
I
O
Intel QPI forwarded clock sent with the outbound data.
O
Must be terminated on the system board using a precision
resistor .
QPI_DRX_DN[19:0] and QPI_DRX_DP[19:0] comprise the
I
differential receive data for the QPI port. The inbound 20 lanes
I
are connected to another component’s outbound direction.
QPI_DTX_DN[19:0] and QPIQPI_DTX_DP[19:0] comprise the
O
differential transmit data for the QPI port. The outbound 20
lanes are connected to another component’s inbound
O
direction.
DBR# is used only in systems where no debug port is
implemented on the system board. DBR# is used by a debug
port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is
a no connect in the system. DBR# is not a processor signal.
Must be terminated on the system board using precision
resistors.
Defines the bank which is the destination for the current
Activate, Read, Write, or Precharge command.
Differential clocks to the DIMM. All command and control
O
signals are valid on the rising edge of clock.
Each signal selects one rank as the target of the command
O
and address.
1
1
1
Datasheet, Volume 171
Page 72
Table 5-1.Signal Definitions (Sheet 2 of 4)
NameTypeDescriptionNotes
Differential pair, Data Strobe x8. Differential strobes latch
DDR{0/1/2}_DQS_N[7:0]
DDR{0/1/2}_DQS_P[7:0]
DDR{0/1/2}_MA[15:0]O
DDR{0/1/2}_ODT[3:0]O
DDR{0/1/2}_RAS#ORow Address Strobe.1
DDR{0/1/2}_RESET#O
DDR{0/1/2}_WE#OWrite Enable.1
ISENSEICurrent sense from VRD11.1.
PECII/O
PRDY#O
PREQ#I/O
PROCHOT#I/O
PSI#O
RESET#I
SKTOCC#O
TCKI
data/ECC for each DRAM. Different numbers of strobes are
I/O
used depending on whether the connected DRAMs are x4 or
x8. Driven with edges in center of data, receive edges are
aligned with data edges.
Selects the Row address for reads and writes, and the column
address for activates. Also used to set values for DRAM
configuration registers.
Enables various combinations of termination resistance in the
target and non-target DIMMs when data is read or written
Resets DRAMs. Held low on power up, held high during self
refresh; otherwise, controlled by configuration register.
PECI (Platform Environment Control Interface) is the serial
sideband interface to the processor and is used primarily for
thermal, power, and error management. Details regarding the
PECI electrical specifications, protocols, and functions can be
found in the Platform Environment Control Interface
Specification.
PRDY# is a processor output used by debug t ools to determine
processor debug readiness.
PREQ# is used by debug tools to request debug operation of
the processor.
PROCHOT# will go active when the processor temperature
monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the
processor Thermal Control Circuit has been activated, if
enabled. This signal can also be driven to the processor to
activate the Thermal Control Circuit. This signal does not have
on-die termination and must be terminated on the system
board.
Processor Power Status Indicator signal. This signal is
asserted when maximum possible processor core current
consumption is less than 20 A. Assertion of this signal is an
indication that the VR controller does not cu rrently need to be
able to provide I
this information to move to a more efficient operation point.
This signal will de-assert at least 3.3 us before the current
consumption will exceed 20 A. The minimum PSI#
assertion and de-assertion time is 1 BCLK.
Asserting the RES ET# signal resets the processor to a known
state and invalidates its internal caches without writing back
any of their contents. Note that some PLL, QPI, and error
states are not effected by reset and only VCCPWRGOOD forces
them to a known state. For a power-on Reset, RESET# must
stay active for at least one millisecond after V
have reached their proper specifications. RESET# must not be
kept asserted for more than 10 ms while VCCPWRGOOD is
asserted. RESET# must be held de-asserted for at least 1 ms
before it is asserted again. RESET# must be held asserted
before VCCPWRGOOD is asserted. This signal does not have
on-die termination and must be terminated on the system
board. RESET# is a common clock signal.
SKTOCC# (Socket Occupied) will be pulled to ground on the
processor package. There is no connection to the processor
silicon for this signal. System board designers may use this
signal to determine if the processor is present.
TCK (Test Clock) provides the clock input for the processor
Test Bus (also known as the Test Access Port).
Signal Descriptions
above 20 A, and the VR controller can use
CC
and BCLK
CC
1
1
1
1
72Datasheet, Volume 1
Page 73
Signal Descriptions
Table 5-1.Signal Definitions (Sheet 3 of 4)
NameTypeDescriptionNotes
TDII
TDOO
TESTLOWI
THERMTRIP#O
TMSI
TRST#I
VCCIPower for processor core.
VCC_SENSE
VSS_SENSE
VCCPLLIPower for on-die PLL filter.
VCCPWRGOODI
VDDPWRGOODI
TDI (T est Data In) tr ansfers serial test data into th e processor.
TDI provides the serial input needed for JTAG specification
support.
TDO (Test Data Out) transfers serial test data out of the
processor. TDO provides the serial output needed for JTAG
specification support.
TESTLOW must be connected to ground through a resistor for
proper processor operation.
Assertion of THERMTRIP# (Thermal Trip) indicates the
processor junction temperature has reached a level beyond
which permanent silicon damage may occur. Measurement of
the temperature is accomplished through an internal thermal
sensor. Upon assertion of THERMTRIP#, the processor will
shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To
further protect the processor, its core voltage (V
and V
THERMTRIP#. Once activated, THERMTRIP# remains latched
until RESET# is asserted. While the assertion of the RESET#
signal may de-assert THERMTRIP#, if the processor junction
temperature remains at or above the trip level, THERMTRIP#
will again be asserted after RESET# is de-asserted.
TMS (Test Mode Select) is a JTAG specification support signal
used by debug tools.
TRST# (Test Reset) resets the Test Access Port (TAP) logic.
TRST# must be driven low during power on Reset.
VCC_SENSE and VSS_SENSE provide an isolated, low
O
impedance connection to the processor core power and
ground. They can be used to sense or measure voltage near
O
the silicon.
VCCPWRGOOD (Power Good) is a processor input. The
processor requires this signal to be a clean indication that
BCLK, V
within their specifications. 'Clean' implies that the signal will
remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on
until they come within specification. The signal must then
transition monotonically to a high state. VCCPWRGOOD can be
driven inactive at any time, but BCLK and power must again
be stable before a subsequent rising edge of VCCPWRGOOD.
In addition, at the time VCCPWRGOOD is asserted RESET#
must be active. The PWRGOOD signal must be supplied to the
processor. It should be driven high throughout boundary scan
operation.
VDDPWRGOOD is an input that indicates the V
supply is good. The processor requires this signal to be a clean
indication that the V
specifications. "Clean" implies that the signal will remain low
(capable of sinking leakage current), without glitches, from
the time that the V
within specification. The signals must then transition
monotonically to a high state.
The PWRGOOD signal must be supplied to the processor.
must be removed following the assertion of
DDQ
, V
, V
CC
CCPLL
and V
TTA
power supply is stable and within
DDQ
supply is turned on until it comes
DDQ
supplies are stable and
TTD
CC
DDQ
), V
TTA VTTD
power
,
Datasheet, Volume 173
Page 74
Table 5-1.Signal Definitions (Sheet 4 of 4)
NameTypeDescriptionNotes
VID[7:0] (Voltage ID) are used to support automatic selection
of power supply voltages (V
Regulator-Down (VRD) 11.1 Design Guidelines for more
information. The voltage supply for these signals must be
valid before the VR can supply V
Conversely, the VR output must be disabled until the voltage
supply for the VID signals become valid. The VR must supply
the voltage that is requested by the signals, or disable itself.
VID7 and VID6 should be tied separately to V
VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
VTTAI
VTTDI
VTT_VID[4:2]O
VTT_SENSE
VSS_SENSE_VTT
VTTPWRGOODI
resistor during reset (This value is latched on the rising edge
of VTTPWRGOOD).
I/O
MSID[2:0] — MSID[2:0] is used to indicate to the processor
whether the platform supports a particular TDP. A processor
will only boot if the MSID[2:0] pins are strapped to the
appropriate setting on the platform (see Table 2-2 for MSID
encodings). In addition, MSID protects the pl a tform by
preventing a higher power processor from booting in a
platform designed for lower power processors.
CSC[2:0] — Current Sense Configuratio n bits, for ISENSE gain
setting. See Voltage Regulator-Down (VRD) 11.1 Design Guidelines for gain setting information. This value is latched
on the rising edge of VTTPWRGOOD.
Power for the analog portion of the integrated memory
controller, QPI, and Shared Cache.
Power for the digital portion of the integrated memory
controller, QPI, and Shared Cache.
VTT_VID[2:4] (V
selection of power supply voltages (V
Regulator-Down (VRD) 11.1 Design Guidelines for more
information.
VTT_SENSE and VSS_SENSE_VTT provide an isolate d, low
O
impedance connection to the processor V
ground. They can be used to sense or measure voltage near
O
the silicon.
The processor requires this input signal to be a clean
indication that the V
specifications. 'Clean' implies that the signal will remain low
(capable of sinking leakage current), without glitches, from
the time that the power supplies are turned on until they
come within specification. The signal must then transition
monotonically to a high state. Note that it is not valid for
VTTPWRGOOD to be de-asserted while VCCPWRGOOD is
asserted.
Signal Descriptions
). Refer to the Voltage
CC
to the processor.
CC
using a 1 k
SS
Voltage ID) are used to support automatic
TT
power supply is stable and within
TT
). Refer to the Voltage
TT
voltage and
TT
Note:
1.DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
§
74Datasheet, Volume 1
Page 75
Thermal Specifications
6Thermal Specifications
6.1Package Thermal Specifications
The processor requires a thermal solution to maintain temperatures within its operating
limits. Any attempt to operate the processor outside these operating limits may result
in permanent damage to the processor and potentially other components within the
system. Maintaining the proper thermal environment is key to reliable, long-term
system operation.
A complete solution includes both component and system level thermal management
features. Component level thermal solutions can include active or passive heatsinks
attached to the processor integrated heat spreader (IHS).
This chapter provides data necessary for developing a complete thermal solution. For
more information on designing a component level thermal solution, refer to the
appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).
6.1.1Thermal Specifications
The processor thermal specification uses the on-die Digital Thermal Sensor (DTS) value
reported using the PECI interface for all processor temperature measurements. The
DTS is a factory calibrated, analog-to-digital thermal sensor. As a result, it will no
longer be necessary to measure the processors case temperature. Consequently, there
will be no need for a Thermal Profile specification defining the relationship between the
processors T
Note:Unless otherwise specified, the term “DTS” refers to the DTS value returned by from
the PECI interface gettemp command.
Note:A thermal solution that was verified compliant to the processor case temperature
thermal profile at the customer defined boundary conditions is expected to be
compliant with this update. No redesign of the thermal solution should be necessary. A
fan speed control algorithm that was compliant to the previous thermal requirements is
also expected to be compliant with this specification. The fan speed control algorithm
can be updated to use the additional information to optimize acoustics.
To allow the optimal operation and long-term reliability of Intel processor-based
systems, the processor thermal solution must deliver the specified thermal solution
performance in response to the DTS sensor value. The thermal solution performance
will be measured using a Thermal Test Vehicle (TTV). See Table 6-1 and Figure 6-1 or
Figure 6-2 for the TTV thermal profile. See Table 6-4 for the required thermal solution
performance table when DTS values are greater than T
designed to provide this level of thermal capability may affect the long-term reliability
of the processor and system. When the DTS value is less than T
solution performance is not defined and the fans may be slowed down. This is
unchanged from the prior specification. For more details on thermal solution design,
refer to the appropriate processor Thermal and Mechanical Design Guidelines (see
Section 1.2).
and power dissipation.
CASE
CONTROL
. Thermal solutions not
CONTROL
, the thermal
The processors implement a methodology for managing processor temperatures, which
is intended to support acoustic noise reduction through fan speed control and to assure
processor reliability. Selection of the appropriate fan speed is based on the relative
temperature data reported by the processor’s Digital Temperature Sensor (DTS). The
Datasheet, Volume 175
Page 76
Thermal Specifications
DTS can be read using the Platform En vironm ent Control In terface (PECI) as described
in Section 6.3. The temperature reported over PECI is always a negative value and
represents a delta below the onset of thermal control circuit (TCC) activation, as
indicated by PROCHOT# (see Section 6.2, Processor Thermal Features). Systems that
implement fan speed control must be designed to use this data. Systems that do not
alter the fan speed only need to ensure the thermal solution provides the
CA
that
meets the TTV thermal profile specifications.
A single integer change in the PECI value corresponds to approximately 1 °C change in
processor temperature. Although each processors DTS is factory calibrated, the
accuracy of the DTS will vary from part to part and may also vary slightly with
temperature and voltage. In general, each integer change in PECI should equal a
temperature change between 0.9 °C and 1.1 °C.
Analysis indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP), instead of
the maximum processor power consumption. The Adaptive Thermal Monitor feature is
intended to help protect the processor in the event that an application exceeds the TDP
recommendation for a sustained time period. For more details on this feature, refer to
Section 6.2. Refer to the appropriate processor Thermal and Mechanical Design
Guidelines (see Section 1.2). for details on system thermal solution design, thermal
profiles and environmental considerations.
Table 6-1. Processor Thermal Specifications
Processor
i7-990X3.46 GHz130125
i7-980X3.33 GHz130125
i7-9803.33 GHz130125
i7-9703.20 GHz130125
Notes:
1.These values are specified at V
2.Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
3.These specifications are based on initial silicon characterization. These specifications may be further
4.Power specifications are defined at all VIDs found in Table 2-1. The processor may be shipped under
5.Target -ca Using the processor TTV (°C/W) is based on a T
6.Processor idle power is specified under the lowest possible idle state: processor package C6 state.
Core
Frequency
the processor is not to be subjected to any static V
specified I
maximum power that the processor can dissipate. TDP is measured at the TCC activation temperature.
updated as more characterization data becomes available.
multiple VIDs for each frequency.
Achieving processor package C6 state is not supported by all chipsets. See the Intel X58 Express Chipset Datasheet for more details.
CC
Thermal
Design Power
(W)
. Refer to the loadline specifications in Chapter 2.
Idle
Power
(W)
for all processor frequencies. Systems must be designed to ensure
6.1.1.1Specification for Operation Where Digital Thermal Sensor Exceeds
T
CONTROL
When the DTS value is less than T
CONTROL
the speed of the thermal solution fan. This remains the same as with the previous
guidance for fan speed control.
, the fan speed control algorithm can reduce
During operation where the DTS value is greater than T
algorithm must drive the fan speed to meet or exceed the target thermal solution
performance (
(T
AMBIENT
) is required to fully implement the specification as the target
) shown in Table 6-4. The ability to monitor the inlet temperature
CA
defined for various ambient temperature conditions. See the appropriate proc ess or
Thermal and Mechanical Design Guidelines (see Section 1.2) for details on
characterizing the fan speed to
and ambient temperature measurement.
CA
Table 6-4.Thermal Solution Performance above T
T
1
AMBIENT
43.20.1900.190
42.00.2060.199
41.00.2190.207
40.00.2320.215
39.00.2450.222
38.00.2580.230
37.00.2710.238
36.00.2840.245
35.00.2970.253
34.00.3100.261
33.00.3230.268
32.00.3360.276
31.00.3490.284
30.00.3620.292
29.00.3750.299
28.00.3880.307
27.00.4010.315
26.00.4140.322
25.00.4270.330
24.00.4400.338
23.00.4530.345
22.00.4660.353
21.00.4790.361
20.00.4920.368
19.00.5050.376
18.00.5190.384
at DTS = T
CA
CONTROL
2
CONTROL
CONTROL
at DTS = -1
CA
, the fan speed control
is explicitly
CA
3
Notes:
1.The ambient temperature is measured at the inlet to the processor thermal solution.
2.This column can be expressed as a function of T
Y
3.This column can be expressed as a function of T
Datasheet, Volume 179
= 0.19 + (43.2 – T
Y
CA
= 0.19 + (43.2 – T
CA
AMBIENT
AMBIENT
) * 0.013
) * 0.0077
by the following equation:
AMBIENT
by the following equation:
AMBIENT
Page 80
6.1.2Thermal Metrology
Thermal Specifications
The minimum and maximum TTV case temperatures (T
and Table 6-2 and are measured at the geometric top center of the thermal test vehicle
integrated heat spreader (IHS). Figure 6-3 illustrates the location where T
temperature measurements should be made. For detailed guidelines on temperature
measurement methodology and attaching the thermocouple, refer to the appropriate
processor Thermal and Mechanical Design Guidelines (see Section 1.2).
Figure 6-3. Thermal Test Vehicle (TTV) Case Temperature (T
) are specified in Table 6-1,
CASE
CASE
) Measurement Location
CASE
Notes:
1.Figure is not to scale and is for reference only.
2.B1: Max = 45.07 mm, Min = 44.93 mm.
3.B2: Max = 42.57 mm, Min = 42.43 mm.
4.C1: Max = 39.1 mm, Min = 38.9 mm.
5.C2: Max = 36.6 mm, Min = 36.4 mm.
6.C3: Max = 2.3 mm, Min = 2.2 mm
7.C4: Max = 2.3 mm, Min = 2.2 mm.
8.Refer to the appropriate Thermal and Mechanical Design Guide (see Section 1.2) for instructions on
thermocouple installation on the processor TTV package.
80Datasheet, Volume 1
Page 81
Thermal Specifications
6.2Processor Thermal Features
6.2.1Processor Temperature
The processor contains a software readable field in the IA32_TEMPERATURE_TARGET
register that contains the minimum temperature at which the TCC will be activated and
PROCHOT# will be asserted. The TCC activation temper ature is calibr ated on a part -by part basis and normal factory variation may result in the actual TCC activation
temperature being higher than the value listed in the register. TCC activation
temperatures may change based on processor stepping, frequency or manufacturing
efficiencies.
Note:There is no specified correlation between DTS temperatures and processor case
temperatures; therefore it is not possible to use this feature to ensure the processor
case temperature meets the Thermal Profile specifications.
6.2.2Adaptive Thermal Monitor
The Adaptive Thermal Monitor feature provides an enhanced method for controlling the
processor temperature when the processor silicon exceeds the Thermal Control Circuit
(TCC) activation temperature. Adaptive Thermal Monitor uses T C C activ ation to reduce
processor power using a combination of methods. The first method (Frequency/VID
control, similar to Thermal Monitor 2 (TM2) in previous generation processors) involves
the processor reducing its operating frequency (using the core ratio multiplier) and
input voltage (using the VID signals). This combination of lower frequency and VID
results in a reduction of the processor power consumption. The second method (clock
modulation, known as Thermal Monitor 1 (TM1) in previous generation processors)
reduces power consumption by modulating (starting and stopping) the internal
processor core clocks. The processor intelligently selects the appropriate TCC method
to use on a dynamic basis. BIOS is not required to select a specific method (as with
previous-generation processors supporting TM1 or TM2). The temperature at which
Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and
is not user configurable. Snooping and interrupt processing are performed in the
normal manner while the TCC is active.
When the TCC activation temperature is reached, the processor will initiate TM2 in
attempt to reduce its temperature. If TM2 is unable to reduce the processor
temperature, then TM1 will be also be activated. TM1 and TM2 will work together
(clocks will be modulated at the lowest frequency ratio) to reduce power dissipation
and temperature.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment ma y cause a noticeable performance loss,
and in some cases may result in a T
temperature and may affect the long-term reliability of the processor. In addition, a
thermal solution that is significantly under-designed may not be capable of cooling the
processor even when the TCC is active continuously. Refer to the appropriate processor
Thermal and Mechanical Design Guidelines (see Section 1.2) for information on
designing a compliant thermal solution.
The Thermal Monitor does not require any additional hardware, software drivers, or
interrupt handling routines. The following sections provide more details on the different
TCC mechanisms used by the processor.
Datasheet, Volume 181
that exceeds the specified maximum
CASE
Page 82
6.2.2.1Frequency/VID Control
Temperatu re
f
MAX
f
1
f
2
VIDf
MAX
VID
Frequency
VIDf
2
VIDf
1
PROCHOT#
Temperatu re
f
MAX
f
1
f
2
VIDf
MAX
VID
Frequency
VIDf
2
VIDf
1
PROCHOT#
When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures
reported using PECI may not equal zero when PROCHOT# is activated, see Section 6.3
for further details), the TCC will be activated and the PROCHOT# signal will be
asserted. This indicates the processor temperature has met or exceeded the factory
calibrated trip temperature and it will take action to reduce the temperature.
Upon activation of the TCC, the processor will stop the core clocks, reduce the core
ratio multiplier by 1 ratio and restart the clocks. All processor activity stops during this
frequency transition, which occurs within 2 us. Once the clocks have been restarted at
the new lower frequency , processor activity resumes while the voltage requested by the
VID lines is stepped down to the minimum possible for the particular frequency.
Running the processor at the lower frequency and voltage will reduce power
consumption and should allow the processor to cool off. If after 1 ms the processor is
still too hot (the temperature has not dropped below the TCC activation point, DTS
still = 0 and PROCHOT is still active), then a second frequency and voltage transition
will take place. This sequence of temperature checking and Frequency/VID reduction
will continue until either the minimum frequency has been reached or the processor
temperature has dropped below the TCC activation point.
If the processor temperature remains above the TCC activation point even after the
minimum frequency has been reached, then clock modulation (described below) at that
minimum frequency will be initiated.
There is no end user software or hardware mechanism to initiate this automated TCC
activation behavior.
Thermal Specifications
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near the TCC activation
temperature. Once the temperature has dropped below the trip temperature, and the
hysteresis timer has expired, the operating frequency and voltage transition back to
the normal system operating point using the intermediate VID/frequency points.
T ransition of the VID code will occur first, to insure proper operation as the frequency is
increased. Refer to Table 6-4 for an illustration of this ordering.
Figure 6-4. Frequency and Voltage Ordering
82Datasheet, Volume 1
Page 83
Thermal Specifications
6.2.2.2Clock Modulation
Clock modulation is a second method of thermal control available to the processor.
Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle
that should reduce power dissipation by about 50% (typically a 30–50% duty cycle).
Clocks often will not be off for more than 32 us when the TCC is active. Cycle times are
independent of processor frequency . The duty cy cle for the T CC, when activ ated by the
Thermal Monitor, is factory configured and cannot be modified.
It is possible for software to initiate clock modulation with configurable duty cycles.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
6.2.2.3Immediate Transiton to combined TM1 and TM2
As mentioned above, when the TCC is activated, the processor will sequentially step
down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature. If
the temperature continues to increase and exceeds the TCC activation temperature by
approximately 5 °C before the lowest ratio/VID combination has been reached, then
the processor will immediately transition to the combined TM1/TM2 condition. The
processor will remain in this state until the temperature has dropped below the TCC
activation point. Once below the TCC activation temperature, TM1 will be discontinued
and TM2 will be exited by stepping up to the appropriate ratio/VID state.
6.2.2.4Critical Temperature Flag
If TM2 is unable to reduce the processor temperature, then TM1 will be also be
activated. TM1 and TM2 will then work together to reduce power dissipation and
temperature. It is expected that only a catastrophic thermal solution failure would
create a situation where both TM1 and TM2 are active.
If TM1 and TM2 have both been active for greater than 20 ms and the processor
temperature has not dropped below the TCC activation point, then the Critical
Temperature Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator
of a catastrophic thermal solution failure and that the processor cannot reduce its
temperature. Unless immediate action is taken to resolve the failure, the processor will
probably reach the Thermtrip temperature (see Section 6.2.3 ) within a short time. To
prevent possible permanent silicon damage, Intel recommends removing power from
the processor within ½ second of the Critical Temperature Flag being set.
6.2.2.5PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled
(note that it must be enabled for the processor to be operating within specification),
the TCC will be active when PROCHOT# is asserted.
The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Although the PROCHOT# signal is an output by default, it may be configured as bidirectional. When configured in bi-directional mode, it is either an output indicating the
processor has exceeded its TCC activation temperature or it can be driven from an
Datasheet, Volume 183
Page 84
external source (such as, a voltage regulator) to activate the TCC. The ability to
activate the TCC using PROCHOT# can provide a means for thermal protection of
system components.
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that one or more cores has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC for all cores. TCC activation when
PROCHOT# is asserted by the system will result in the processor immediately
transitioning to the minimum frequency and corresponding voltage (using Freq/VID
control). Clock modulation is not activated in this case. The TCC will remain active until
the system de-asserts PROCHOT#.
Use of PROCHOT# in bi-directional mode can allow VR thermal designs to target
maximum sustained current instead of maximum current. Systems should still provide
proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system
cooling failure. The system thermal design should allow the power delivery circuitry to
operate within its temperature specification even while the processor is operating at its
Thermal Design Power.
6.2.3THERMTRIP# Signal
Thermal Specifications
Regardless of whether or not Adaptive Thermal Monitor is enabled, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the silicon
has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 5-1). THERMTRIP# activation is independent of processor activity. The
temperature at which THERMTRIP# asserts is not user configurable and is not software
visible.
6.3Platform Environment Control Interface (PECI)
6.3.1Introduction
The Platform Environment Control Interface (PECI) is a one-wire interface that provides
a communication channel between the Intel processor and chipset components to
external monitoring devices. The processor implements a PECI interface to allow
communication of processor thermal and other information to other devices on the
platform. The processor provides a digital thermal sensor (DTS) for fan speed control.
The DTS is calibrated at the factory to provide a digital representation of relative
processor temperature. Instantaneous temperature readings from the DTS are
available using the IA32_THERM_STATUS MSR; averaged DTS values are read using
the PECI interface.
The PECI physical layer is a self-clocked one-wire bus that begins each bit with a
driven, rising edge from an idle level near zero volts. The duration of the signal driven
high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes
variable data transfer rate established with every message. The single wire interface
provides low board routing overhead for the multiple load connections in the congested
routing area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability to transfer
critical device operating conditions and configuration information.
84Datasheet, Volume 1
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Thermal Specifications
6.3.1.1Fan Speed Control with Digital Thermal Sensor
Fan speed control solutions use a v alue stored in the static variable, T
temperature data that is delivered over PECI (in response to a GetTemp0() command),
is compared to this T
value versus an absolute value. The temperature reported over PECI is always a
CONTROL
reference. The DTS temperature is reported as a relative
CONTROL
. The DTS
negative value and represents a delta below the onset of thermal control circuit (TCC)
activation, as indicated by PROCHOT#. Therefore, as the temperature approaches TCC
activation, the value approaches zero degrees.
6.3.1.2Processor Thermal Data Sample Rate and Filtering
The processor digital thermal sensor (DTS) provides an improved capability to monitor
device hot spots that inherently leads to more varying temperature readings over short
time intervals. To reduce the sample rate requirements on PECI and improve thermal
data stability versus time the processor DTS implements an averaging algorithm that
filters the incoming data. This filter is expressed mathematically as:
PECI(t) = PECI(t–1)+1 / (2^^X)*[Temp – PECI(t–1)]
Where: PECI(t) is the new averaged temperature, PECI(t-1) is the previous
averaged temperature; Temp is the raw temperature data from the DTS; X is the
Thermal Averaging Constant (TAC)
Note:Only values read using the PECI interface are averaged. Temperature values read using
the IA32_THERM_STATUS MSR are not averaged.
The Thermal Averaging Constant is a BIOS configurable value that determines the time
in milliseconds over which the DTS temperature values are averaged. Short averaging
times will make the averaged temperature values respond more quickly to DTS
changes. Long averaging times will result in better overall thermal smoothing but also
incur a larger time lag between fast DST temperature changes and the value read using
PECI. Refer to the appropriate processor Thermal and Mechanical Design Guidelines
(see Section 1.2) for further details on the Data Filter and the Thermal Averaging
Constant.
Within the processor, the DTS converts an analog signal into a digital value
representing the temperature relative to TCC activation. The conversions are in
integers with each single number change corresponding to approximately 1 °C. DTS
values reported using the internal processor MSR will be in whole integers.
As a result of the averaging function described above, DTS values reported over PECI
will include a 6-bit fractional value. Under typical operating conditions, where the
temperature is close to T
the temperature approaches zero, the fractional values can be used to detect the
CONTROL
, the fractional values may not be of interest. But when
activation of the TCC. An averaged temperature value between 0 and 1 can only occur
if the TCC has been activated during the averaging window. As TCC activation time
increases, the fractional value will approach zero. Fan control circuits can detect this
situation and take appropriate action as determined by the system designers. Of
course, fan control chips can also monitor the PROCHOT# pin to detect TCC activation
using a dedicated input pin on the package. Further details on how the Thermal
Averaging Constant influences the fractional temperature values are available in the
Thermal Design Guide.
Datasheet, Volume 185
Page 86
6.3.2PECI Specifications
6.3.2.1PECI Device Address
The PECI register resides at address 30h.
6.3.2.2PECI Command Support
The processor supports the PECI commands listed in Table 6-5.
Table 6-5.Supported PECI Command Functions and Codes
Thermal Specifications
Command
Function
Ping()N/A
GetTemp0()01h
CodeComments
This command targets a valid PECI device address followed by zero Write
Length and zero Read Length.
Write Length: 1
Read Length: 2
Returns the temperature of the processor in Domain 0
6.3.2.3PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification. The PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is known to be unresponsive. Prior to a
power on RESET# and during RESET# assertion, PECI is not ensured to provide reliable
thermal data. System designs should implement a default power-on condition that
ensures proper processor operation during the time frame when reliable data is not
available using PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the host controller should take action to protect the system from
possible damaging states. If the host controller cannot complete a valid PECI
transactions of GetTemp0() with a given PECI device over 3 consecutive failed
transactions or a one second maximum specified interval, then it should take
appropriate actions to protect the corresponding device and/or other system
components from overheating. The host controller may also implement an alert to
software in the event of a critical or continuous fault condition.
6.3.2.4PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
Table 6-6.
Table 6-6.G etTemp0() Error Codes
Error CodeDescription
8000hGeneral sensor error
86Datasheet, Volume 1
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Thermal Specifications
6.4Storage Conditions Specifications
Environmental storage condition limits define the temperature and relative humidity
limits to which the device is exposed to while being stored. The specified storage
conditions are for component level prior to board attach (see following notes on post
board attach limits).
Table 6-7 specifies absolute maximum and minimum storage temperature limits that
represent the maximum or minimum device condition beyond which damage, latent or
otherwise, may occur. The table also specifies sustained storage temperature, relative
humidity, and time-duration limits. At conditions outside sustained limits, but within
absolute maximum and minimum ratings, quality and reliability may be affected.
Table 6-7.Storage Condition Ratings
SymbolParameterMinMaxNotes
The minimum/maximum device storage
T
abs storage
T
sustained storage
RH
sustained storage
Time
sustained storage
temperature beyond which damage (late nt
or otherwise) may occur when subjected
to for any length of time.
The minimum/maximum device storage
temperature for a sustained period of time
The maximum device storage relative
humidity for a sustained period of time
-55 °C125 °C1, 2, 3, 4, 5
-5 °C40 °C1, 2, 3, 4, 5
0 months6 months1, 2, 3, 4, 5
—
60% @
24 °C
1, 2, 3, 4, 5
Notes:
1.Storage conditions are applicable to storage environments only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, refer to the processor case temperature
specifications.
2.These ratings apply to the Intel component and do not include the tray or packaging.
3.Failure to adhere to this specification can affect the long-term reliability of the processor.
4.Non operating storage limits for post board attach: Storage condition limits for the component, once
attached to the application board, are not specified.
5.Device storage temperature qualification methods follow JESD22-A119 (low temp) and JESD22-A103 (high
temp) standards.
§
Datasheet, Volume 187
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Thermal Specifications
88Datasheet, Volume 1
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Features
7Features
7.1Power-On Configuration (POC)
Several configuration options can be configured by hardware. For electrical
specifications on these options, refer to Chapter 2. Note that request to execute BIST is
not selected by hardware but is passed across the Intel QPI link during initialization.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a “power-on” reset.
Table 7-1.Power On Configuration Signal Options
Configuration OptionSignal
MSIDVID[2:0]/MSID[2:0]
CSCVID[5:3]/CSC[2:0]
Notes:
1.Latched when VTTPWRGOOD is asserted and all internal power good conditions are met.
2.See the signal definitions in Table 6-1 for the description of MSID and CSC.
1, 2
1, 2
7.2Clock Control and Low Power States
The processor supports low power states at the individual thread, core, and package
level for optimal power management. The processor implements software interfaces for
requesting low power states: MWAIT instruction extensions with sub-state hints, the
HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block
mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to
equivalent MWAIT C-state requests inside the processor and do not directly result in
I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up
before using the P_LVLx I/O read interface.
Software may make C-state requests by using a legacy method involving I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
feature is designed to provide legacy support for operating systems that initiate C-state
transitions using access to pre-defined ICH registers. The base P_LVLx register is
P_LVL2, corresponding to a C3 request. P_LVL3 is C6.
P_LVL2 is defined in the PMG_IO_CAPTURE MSR. P_LVLx is limited to a subset of Cstates. For Example, P_LVL8 is not supported and will not cause an I/O redirection to a
C8 request. Instead, it will fall through like a normal I/O instruction. The range of I/O
addresses that may be converted into C-state requests is also defined in the
PMG_IO_CAPTURE MSR, in the ‘C-state Range’ field. This field maybe written by BIOS
to restrict the range of I/O addresses that are trapped and redirected to MWAIT
instructions. Note that when I/O instructions are used, no MWAIT substates can be
defined, as therefore the request defaults to have a sub-state or zero, but always
assumes the ‘break on IF==0’ control that can be selected using ECX with an MWAIT
instruction.
Datasheet, Volume 189
Page 90
Figure 7-1. Power State
C0
1. No transition to C0 is needed to service a snoop wh en in C 1 or C 1E .
,
.
2. Transitions back to C0 occur on an interrupt or on acces s to m onitored address (if state was en tered via M W A IT).
.
2
2
C1
1
1
CE
1
C3
C6
2
2
MWAIT C1,
HLT
MWAIT C1,
HLT (C1E
enabled)
MWAIT C6,
I/O C6
MWAIT C3,
I/O C3
Features
7.2.1Thread and Core Power State Descriptions
Individual threads may request low power states. Core power states are automatically
resolved by the processor as shown in Table 7-2.
Table 7-2.Coordination of Thread Power States at the Core Level
Thread1 State
1
1
1
1
®
64 and IA-32 Architecture Software Developer 's
Thread0
State
Notes:
1.If enabled, state will be C1E.
7.2.1.1C0 State
This is the normal operating state in the processor.
7.2.1.2C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1E) instruction. The processor thread will transition to the C0 state upon
occurrence of an interrupt or an access to the monitored address if the state was
entered using the MWAIT instruction. RESET# will cause the processor to initialize
itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the C1 state. See the IntelManuals, Volume III: System Programmer's Guide for more information.
While in C1/C1E state, the processor will process bus snoops and snoops from the
other threads.
Core State
C0C1
C0C0C0C0C0
1
C1
C3C0C1
C6C0C1
C0C1
C3C6
1
C1
C3C3
C3C6
C1
1
90Datasheet, Volume 1
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Features
7.2.1.3C3 State
Individual threads of the processor can enter the C3 state by initiating a P_LVL2 I/O
read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, the processor
flushes the contents of its caches. Except for the caches, the processor core maintains
all its architectural state while in the C3 state. All of the clocks in the processor core are
stopped in the C3 state.
Because the core’s caches are flushed, the processor keeps the core in the C3 state
when the processor detects a snoop on the Intel QPI Link or when another logical
processor in the same package accesses cacheable memory. The processor core will
transition to the C0 state upon occurrence of an interrupt. RESET# will cause the
processor core to initialize itself.
7.2.1.4C6 State
Individual threads of the processor can enter the C6 state by initiating a P_LVL3 read to
the P_BLK or an MWAIT(C6) instruction. Before entering Core C6, the processor saves
core state data (such as, registers) to the last level cache. This data is retired after
exiting core C6. The processor achieves additional power savings in the core C6 state.
7.2.2Package Power State Descriptions
The package supports C0, C3, and C6 power states. Note that there is no package C1
state. The package power state is automatically resolved by the processor depending
on the core power states and permission from the rest of the system as described in
the following sections.
7.2.2.1Package C0 State
This is the normal operating state for the processor. The processor remains in the
Normal state when at least one of its cores is in the C0 or C1 state or when another
component in the system has not granted permission to the processor to go into a low
power state. Individual components of the processor may be in low power states while
the package is in C0.
7.2.2.2Package C1/C1E State
The package will enter the C1/C1E low power state when at least one core is in the
C1/C1E state and the rest of the cores are in the C1/C1E or lower power state. The
processor will also enter the C1/C1E state when all cores are in a power state lower
than C1/C1E but the package low power state is limited to C1/C1E using the
PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically
transition to the lowest power operating point (lowest supported voltage an d associated
frequency). When entering the C1E state, the processor will first switch to the lowest
bus ratio and then transition to the lower VID. No notification to the system occurs
upon entry to C1/C1E.
7.2.2.3Package C3 State
The package will enter the C3 low power state when all cores are in the C3 or lower
power state and the processor has been granted permission by the other component(s)
in the system to enter the C3 state. The package will also enter the C3 state when all
cores are in an idle state lower than C3 but other component(s) in the system have
only granted permission to enter C3.
If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and
for processors with an integrated memory controller, the DRAM will be put into selfrefresh.
Datasheet, Volume 191
Page 92
7.2.2.4Package C6 State
The package will enter the C6 low power state when all cores are in the C6 or lower
power state and the processor has been granted permission by the other component(s)
in the system to enter the C6 state. The package will also enter the C6 state when all
cores are in an idle state lower than C6 but the other component(s) have only granted
permission to enter C6.
If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and
the shared cache will enter a deep sleep state. Additionally, for processors with an
integrated memory controller, the DRAM will be put into self-refresh.
7.3Sleep States
The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in
Table 7-3. For information on ACPI S-states and related terminology, refer to ACPI
Specification. The S-state transitions are coordinated by the processor in response PM
Request (PMReq) messages from the chipset. The processor itself will never request a
particular S-state.
Table 7-3.Processor S-States
S-StatePower ReductionAllowed Transitions
S0Normal Code ExecutionS1 (using PMReq)
S1
S3
S4/S5Processor responds with CmpD(S4/S5) message.S0 (using reset)
Cores in C1E like state, processor responds with
CmpD(S1) message.
Memory put into self-refresh, processor responds with
CmpD(S3) message.
Features
S0 (using reset or PMReq)
S3, S4 (using PMReq)
S0 (using reset)
Notes:
1.If the chipset requests an S-state transition, which is not allowed, a machine check error
will be generated by the processor.
7.4ACPI P-States (Intel® Turbo Boost Technology)
The processor supports ACPI P-States. A new feature is that the P0 ACPI state will be a
request for Turbo Boost Technology. Turbo Boost Technology opportunistically and
automatically allows the processor to run faster than its marked frequency if the
processor is operating below power, thermal, and current specifications. Maximum
turbo frequency is dependant on the processor component and number of active cores.
No special hardware support is necessary for Turbo Boost Technology. BIOS and the
operating system can enable or disable Turbo Boost Technology.
92Datasheet, Volume 1
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Features
7.5Enhanced Intel SpeedStep® Technology
The processor features Enhanced Intel SpeedStep Technology. Following are the key
features of Enhanced Intel SpeedStep Technology:
• Multiple voltage and frequency operating points p rovide optimal performance at the
lowest power.
• Voltage and frequency selection is software controlled by writing to processor
MSRs:
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps by placing new values on the VID pins and the PLL then locks to the
new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
new frequency and the VCC is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in
progress, the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp rates internally to ensure smooth transitions.
• Low transition latency and large number of transitions possible per second:
— Processor core (including shared cache) is unavailable for less than 5 µs during
the frequency transition.
§
Datasheet, Volume 193
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Features
94Datasheet, Volume 1
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Boxed Processor Specifications
8Boxed Processor Specifications
8.1Introduction
The processor will also be offered as an Intel boxed processor. Intel boxed processors
are intended for system integrators who build systems from baseboards and standard
components. The boxed processor will be supplied with a cooling solution. This chapter
documents baseboard and system requirements for the cooling solution that will be
supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators.
Note:Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets]. Figure 8-1 shows a mechanical representation of a boxed
processor.
Note:Drawings in this section reflect only the specifications on the Intel boxed processor
Figure 8-1. Mechanical Representation of the Boxed Processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the appropriate processor Thermal and Mechanical
Design Guidelines (see Section 1.2) for further guidance. Contact your local Intel Sales
Representative for this document.
Note: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
Datasheet, Volume 195
Page 96
Boxed Processor Specifications
8.2Mechanical Specifications
8.2.1Boxed Processor Cooling Solution Dimensions
This section covers the mechanical specifications of the boxed processor. The boxed
processor will be shipped with an unattached fan heatsink. Figure 8-1 shows a
mechanical representation of the boxed processor.
Clearance is required around the fan heatsi nk to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 8-2 (side view), and Figure 8-3 (top view).
The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 8-7 and Figure 8-8. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 8-2. Space Requirements for the Boxed Processor (side view)
96Datasheet, Volume 1
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Boxed Processor Specifications
Figure 8-3. Space Requirements for the Boxed Processor (top view)
Notes:
1.Diagram does not show the attached hardware for the clip design and is provided only as a mechanical
representation.
Figure 8-4. Space Requirements for the Boxed Processor (overall view)
Datasheet, Volume 197
Page 98
Boxed Processor Specifications
Pin
Signal
12
34
1
2
3
4
GND
+12 V
SENSE
CONTROL
Straight square pin, 4- pin terminal housing with
polarizing ribs and fricti on locking ramp.
0.100" pitch, 0.025" square pin width.
Match with straight pin, friction loc k header on
mainboard.
8.2.2Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 6
and the appropriate processor Thermal and Mechanical Design Guidelines (see
Section 1.2) for details on the processor weight and heatsink requirements.
8.2.3Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.
8.3Electrical Requirements
8.3.1Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 8-5. Baseboards
must provide a matched power header to support the boxed processor. Table 8-1
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal that is an open-collector output that pulses at
a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.
The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the
connector labeled as CONTROL.
The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and
does not support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 8-6 shows the
location of the fan power connector relative to the processor socket. The baseboard
power header should be positioned w ithin 110 mm [4.33 inches] from the center of the
processor socket.
Figure 8-5. Boxed Processor Fan Heatsink Power Cable Connector Description
OH
to
98Datasheet, Volume 1
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Boxed Processor Specifications
Notes:
B
C
R110
[4.33]
Table 8-1.Fan Heatsink Power and Signal Specifications
DescriptionMinTypMaxUnitNotes
+12 V: 12 volt fan power supply10.81213.2VIC:
- Peak steady-state fan current draw
- Average steady-state fan current draw
SENSE: SENSE frequenc y
CONTROL212528kHz
1. Baseboard should pull this pin up to 5 V with a resistor.
2. Open drain type, pulse width modulated.
3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.
—
—
—2—
—
—
3.0
2.0
pulses per fan
revolution
Figure 8-6. Baseboard Power Header Placement Relative to Processor Socket
A
A
-
1
2, 3
8.4Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the
boxed processor.
8.4.1Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. Howeve r, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
temperature specification is found in Chapter 6 of this document. The boxed processor
fan heatsink is able to keep the processor temperature within the specifications (see
Table 6-1) in chassis that provide good thermal management. For the boxed processor
fan heatsink to operate properly, it is critical that the airflow provided to the fan
heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the
sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow
through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink
reduces the cooling efficiency and decreases fan life. Figure 8-7 and Figure 8-8
illustrate an acceptable airspace clearance for the fan heatsink. The air temperature
entering the fan should be kept below 40 ºC. Again, meeting the processor's
temperature specification is the responsibility of the system integrator.